Commit Graph

27 Commits

Author SHA1 Message Date
Dhaval Khandla
2d2c5b1b91 am64x/am243x: examples/source: Fix the license text
Fixes: PINDSW-6908

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-09-13 18:46:41 +05:30
Rajul Bhambay
0d9a5d95eb am64x/am243x: HDSL: Multi-channel Sync Mode bugs
- Multiple setups fix
 - Multiple encoders fix

Fixes: PINDSW-6893

Signed-off-by: Rajul Bhambay <r-bhambay@ti.com>
2023-09-13 16:07:23 +05:30
Dhaval Khandla
c52e07cb7b Pull request #22: HDSL: Merge HDSL Examples
Merge in PINDSW/motor_control_sdk from PINDSW-6651_merge_hdsl_examples to next

* commit '47060ba7b13cc305a30560f28d33651a56a74321':
  am64x/am243x: hdsl: Add retry for Udma_ringDequeueRaw if it fails
  am64x/am243x: hdsl: Merge the trace example with the main example
  am243x: hdsl: Set 300 MHz ICSSG core clock frequency fo am243x-lp examples
2023-09-13 04:34:59 -05:00
Rajul Bhambay
2247d9b77b am64x/am243x: HDSL: Multi-channel Sync Mode bugs
- Multiple setups fix
 - Multiple encoders fix

Fixes: PINDSW-6893

Signed-off-by: Rajul Bhambay <r-bhambay@ti.com>
2023-09-13 13:49:29 +05:30
Achala Ram
af61f50a46 am64x/am243x: EnDat: Enable long time test run
- Enable long time test run for position command
- Load all core firmware in load share mode

Fixes: PINDSW-6686

Signed-off-by: Achala Ram <a-ram@ti.com>
2023-09-11 15:44:28 +05:30
Dhaval Khandla
db642b84db am64x/am243x: hdsl: Merge the trace example with the main example
- Update the UART options
- Fix and update the variable names for tracing
- Enable DMA in sysconfig

Fixes: PINDSW-6639, PINDSW-6651

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-09-11 11:47:35 +05:30
Dhaval Khandla
a3cfd189bf Pull request #21: am64x/am243x: hdsl: Remove UART option 16 for long message test
Merge in PINDSW/motor_control_sdk from PINDSW-6641_fix_long_message_test_case to next

* commit 'e0a42c5a8286af60c1570a1c97d66993afd9e14e':
  am64x/am243x: hdsl: Remove UART option 16 for long message test
2023-09-10 23:07:49 -05:00
Dhaval Khandla
e0a42c5a82 am64x/am243x: hdsl: Remove UART option 16 for long message test
- Test case does not have correct pass/fail conditions

Fixes: PINDSW-6641

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-09-07 09:22:10 +05:30
Dhaval Khandla
81850f6662 allsoc: docs: Update the main page of documentation
- Update the text
- Update the block diagram and links
- Add links to IC SDK and MCU+ SDK
- Fix the documentation build warnings

Fixes: PINDSW-6552

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-09-04 13:09:23 +05:30
Dhaval Khandla
3cc1c220cd allsoc: docs: Fix the doxygen groups for API documentation
- Create separate groups for position sense and current sense

Fixes: PINDSW-6632

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-09-04 13:09:22 +05:30
Achala Ram
ed38acdd56 Pull request #13: am64x/am243x: EnDat: remove rx waiting bug
Merge in PINDSW/motor_control_sdk from a0502729_PINDSW-6569_EnDat_release_bug to next

* commit '84de86d58c05d9416377d7cf6c93774b2de0bc44':
  am64x/am243x: EnDat: Resolve rx waiting bug
2023-08-29 06:18:50 -05:00
Achala Ram
84de86d58c am64x/am243x: EnDat: Resolve rx waiting bug
-Resolve rx waiting for channel0 and channel2

Fixes: PINDSW-6569

Signed-off-by: Achala Ram <a-ram@ti.com>
2023-08-29 15:37:07 +05:30
Rajul Bhambay
7f45f14721 am64x/am243x: HDSL: Multi-channel Sync Mode
- 2 channels in Sync mode
 - fix for long msg issue

Fixes: PINDSW-5489, PINDSW-5538

Signed-off-by: Rajul Bhambay <r-bhambay@ti.com>
2023-08-29 15:01:42 +05:30
Dhaval Khandla
7bc9f4f7bf am64x/am243x: hdsl: Update VERSION register definition
- Remove coding field
- Higher 4 bits represent major version
- Update version to 0.5

Fixes: PINDSW-6536

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-27 15:58:23 +05:30
Dhaval Khandla
c1f342479a am64x/am243x: hdsl: Remove maximum deviation related processing
- Remove MAXDEV_H, MAXDEV_L, MAXDEV_H_THRES, MAXDEV_L_THRES from memory map
  in driver
- Fix the typo in register names for threshold registers

Fixes: PINDSW-6543

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-27 15:58:23 +05:30
Achala Ram
34b6260184 am64x/am243: EnDat: Enable periodic trigger mode for multi-channel
- Also fix propagation delay related configuration

Fixes: PINDSW-5681,PINDSW-6533

Signed-off-by: Achala Ram <a-ram@ti.com>
2023-08-25 22:16:39 +05:30
Dhaval Khandla
47b87f5cf7 am64x/am243x: hdsl: Remove SUC instruction usage
- SUC instruction does not work as expected

Fixes: PINDSW-6531

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 17:00:53 +05:30
Dhaval Khandla
0fe32fbc31 am64x/am243x: hdsl: Fix ONLINE_STATUS_1 register corruption
- TEMP_REG1 was being used by QM_ADD and ONLINE STATUS update in
  v-frame processing
- Update version to 0.4

Fixes: PINDSW-6487

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 14:40:01 +05:30
Dhaval Khandla
4f8af91522 am64x/am243x: hdsl: Fix QMLW bits in ONLINE STATUS registers
- Mask was not applied to QM register before checking the low value
- Enable QMLW/POS checks for all H-frames

Fixes: PINDSW-6530

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 14:40:01 +05:30
Dhaval Khandla
dd0d2e356b am64x/am243x: hdsl: Make FREL/FRES bit set sticky in EVENT/EVENT_S
- Firmware should not clear these bits in EVENT/EVENT_S registers
- Update the version to 0.3

Fixes: PINDSW-6526

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 14:40:01 +05:30
Dhaval Khandla
6b8d4c32cc am64x/am243x: hdsl: Fix reset behaviour after triggering manual reset
- Remove HALT instructions
- Clear all registers after reset

Fixes: PINDSW-6492

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 14:40:01 +05:30
Dhaval Khandla
36a591f12b am64x/am243x: hdsl: Add versioning in firmware
- Update the version to 0.2
- Use the VERSION and VERSION2 register
- Remove the hardcoding from driver

Fixes: PINDSW-6518

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 14:40:01 +05:30
Dhaval Khandla
7605041284 am64x/am243x: hdsl: Fix the SUM/SSUM/FIX1 bit configuration in ONLINE STATUS registers
- MASK_SUM should not be used for masking SUMMARY while updating these
  SUM and SSUM bits in ONLINE STATUS registers
- Fix the mask for SCE and VPOS updates

Fixes: PINDSW-6487, PINDSW-6488

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 14:40:01 +05:30
Dhaval Khandla
8d4349c792 am64x/am243x: hdsl: Fix the fast position and velocity calculation
- Fix sign extension in estimator for relative position and acceleration
  addition
- Fix sign estimation for relative position calculation
- Remove an unnecessary RET instruction
- Fix register corruption for ALIGN_PH
- Fix register usage for DTE error signaling

Fixes: PINDSW-5689

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 14:40:01 +05:30
Dhaval Khandla
9ac1395d6e am64x/am243x: hdsl: Fix the two most significant bytes of fast position
- Register corruption was causing loss of multi-turn data in fast position

Fixes: PINDSW-5651

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 14:40:00 +05:30
Dhaval Khandla
9ce9770c05 am64x/am243x: hdsl: Update the register memory map
- Fix the address of ONLINE STATUS bytes by adding a reserved byte
- Create separate entries for low and high bytes of ONLINE STATUS registers
- Add SAFE_CTRL and POSTX registers
- Use high and low addresses in firmware for ONLINE STATUS registers

Fixes: PINDSW-6489

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
2023-08-22 14:40:00 +05:30
Naresh A
206f344bd1 am64x/am243x/am263x : remove motor_control folder from the repository
remove motor_control folder from the repository

Fixes: PINDSW-5635

Signed-off-by: Naresh A <nareshk@ti.com>
2023-07-13 15:23:20 +05:30