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am64x/am243x: HDSL: Multi-channel Sync Mode bugs

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- Multiple setups fix
 - Multiple encoders fix

Fixes: PINDSW-6893

Signed-off-by: Rajul Bhambay <r-bhambay@ti.com>
This commit is contained in:
Rajul Bhambay 2023-09-13 12:14:12 +05:30
parent c35b23f9aa
commit 2247d9b77b
9 changed files with 1040 additions and 1006 deletions
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3
examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c
View File

@ -209,9 +209,6 @@ void sync_calculation(HDSL_Handle hdslHandle)
{
DebugP_log("\r\n ERROR: ES or period selected is Invalid ");
}
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
wait_before_start=4968;
#endif
DebugP_log("\r\n ********************************************************************");
DebugP_log("\r\n SYNC MODE: period = %d", period);
DebugP_log("\r\n SYNC MODE: ES = %d", ES);

4
examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c
View File

@ -239,9 +239,7 @@ void sync_calculation(HDSL_Handle hdslHandle)
{
DebugP_log("\r\n ERROR: ES or period selected is Invalid ");
}
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
wait_before_start=4968;
#endif
DebugP_log("\r\n ********************************************************************");
DebugP_log("\r\n SYNC MODE: period = %d", period);
DebugP_log("\r\n SYNC MODE: ES = %d", ES);

80
source/position_sense/hdsl/firmware/datalink.asm
View File

@ -224,6 +224,7 @@ modified_header_early_data_push_done:
modified_header_early_data_push_done:
;go to H-Frame callback on transport layer (max. 120-50=70 cycles)
CALL transport_on_h_frame
sub LOOP_CNT.b2, LOOP_CNT.b2, 1
qbeq hframe_7_fifo_push,LOOP_CNT.b2,7
qblt Hframe_fifo_push, LOOP_CNT.b2, 0
@ -232,12 +233,11 @@ modified_header_early_data_push_done:
Hframe_fifo_push:
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
LOOP push_2b_0_0 ,2
LOOP push_2b_0_0 ,4
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff
PUSH_FIFO_CONST 0xff
push_2b_0_0:
qbeq free_run_mode_0, EXTRA_SIZE, 0
PUSH_FIFO_CONST 0xff
@ -313,7 +313,7 @@ datalink_receive_signal_last_received_0_1:
lsl r19, r19, 3
CLEAR_VAL
; same delay code as in learn
ldi REG_TMP1, (74*CYCLES_BIT+7-2);-7=14iters;-35 ;-34; -9 for 100 m
ldi REG_TMP1, (74*CYCLES_BIT+9);-7=14iters;-35 ;-34; -9 for 100 m
READ_CYCLCNT REG_TMP0
qble receive_skip_wait, REG_TMP0, REG_TMP1
sub REG_TMP0, REG_TMP1, REG_TMP0
@ -1254,8 +1254,6 @@ send_header_300m:
;check if we have an EXTRA period
;if we have a EXTRA period: do TX FIFO synchronization here to gain processing time
qbeq send_header_no_extra_wait, EXTRA_SIZE, 0
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff
RESET_CYCLCNT
send_header_modified:
@ -1307,6 +1305,7 @@ send_header_end_disp:
; V-frame processing is split into two parts : transport_on_v_frame and
; transport_on_v_frame_2.
qbne datalink_transport_no_v_frame, LOOP_CNT.b2, 8
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
PUSH_FIFO_CONST 0xff
jmp transport_on_v_frame
@ -1317,6 +1316,7 @@ datalink_transport_no_v_frame:
; is being sent). If yes, perform the remaining part of V-frame processing
qbne datalink_transport_no_v_frame_2, LOOP_CNT.b2, 7
qbbc dont_push_for_non7_hframe_1, H_FRAME.flags, FLAG_NORMAL_FLOW
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff
PUSH_FIFO_CONST 0xff
dont_push_for_non7_hframe_1:
@ -1585,7 +1585,7 @@ SAFE_CTRL_PRST_cleared:
and FIFO_L, FIFO_L, 0x1f
qbeq No_long_short_msg, FIFO_L, S_PAR_IDLE
qbbs No_long_short_msg, H_FRAME.flags, FLAG_WAIT_IDLE
and FIFO_L, H_FRAME.s_par, 0x1f
qbbs No_long_short_msg, FIFO_L, 4
mov FIFO_L,REG_FNC.b3
ldi LEARN_STATE_STARTED , 3
jmp comp_logic_starts
@ -1595,9 +1595,7 @@ comp_logic_done1:
No_long_short_msg:
mov FIFO_L,REG_FNC.b3
ldi LEARN_STATE_STARTED , 2
LOOP push_2B,2
PUSH_FIFO_2B_8x
push_2B:
jmp comp_logic_starts
Push_done:
jmp transport_layer_recv_msg
@ -1657,6 +1655,7 @@ send_stuffing:
.if $defined(EXT_SYNC_ENABLE)
mov REG_TMP11, RET_ADDR1
;do calc
;stuffing value decide starts
qbeq num_pulses_is_one, NUM_PULSES, 1
mov REG_FNC.b3, NUM_STUFFING
@ -1665,18 +1664,21 @@ num_pulses_is_one:
mov REG_FNC.b3, NUM_STUFFING_COMP
stuffing_value_decided:
;stuffing value decide ends
;remainder increament logic starts
lbco &REG_TMP0.b0, MASTER_REGS_CONST, SYNC_STUFFING_REMAINDER, 1 ;reload ES
qbgt remainder_increament_done, REG_TMP0.b0, NUM_PULSES
add REG_FNC.b3, REG_FNC.b3, 1
remainder_increament_done:
;remainder increament logic ends
;ES reload starts
sub NUM_PULSES, NUM_PULSES, 1
qbne num_pulses_non_zero, NUM_PULSES, 0
lbco &NUM_PULSES, MASTER_REGS_CONST, SYNC_CTRL, 1 ;reload ES
num_pulses_non_zero:
;ES reload ends
qbeq send_stuffing_no_stuffing, REG_FNC.b3, 0
;check if we have stuffing
READ_CYCLCNT REG_TMP0
@ -1688,7 +1690,6 @@ learn_state_started:
rsb REG_TMP2, REG_TMP0, (4*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4)
calculation_for_wait_done:
nop
.else
mov REG_TMP11, RET_ADDR1
qbeq send_stuffing_no_stuffing, NUM_STUFFING, 0
@ -1697,13 +1698,15 @@ calculation_for_wait_done:
rsb REG_TMP2, REG_TMP0, (5*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4)
mov REG_FNC.b3, NUM_STUFFING
.endif;EXT_SYNC_ENABLE
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
@ -1748,17 +1751,27 @@ send_stuffing_loop_8x:
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff
PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
PUSH_FIFO_CONST 0xff
PUSH_FIFO_CONST 0xff
sub REG_FNC.b3, REG_FNC.b3, 1
qbne send_stuffing_loop_8x, REG_FNC.b3, 0
qbne send_stuffing_loop_8x, REG_FNC.b3, 1
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
PUSH_FIFO_CONST 0xff
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
PUSH_FIFO_CONST 0xff
PUSH_FIFO_CONST 0xff
.else
send_stuffing_loop:
@ -1812,9 +1825,9 @@ send_trailer:
PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff
PUSH_FIFO_CONST 0xff
.else
PUSH_FIFO_CONST 0x03
TX_CHANNEL
@ -1827,7 +1840,6 @@ send_trailer:
NOP_2
NOP_2
NOP_2
.if !$defined("HDSL_MULTICHANNEL")
.if $defined("FREERUN_300_MHZ")
NOP_2
NOP_2
@ -1835,7 +1847,6 @@ send_trailer:
NOP_2
NOP_2
.endif
.endif
.if !$defined("HDSL_MULTICHANNEL")
TX_CLK_DIV CLKDIV_SLOW, REG_TMP0
.endif
@ -1858,7 +1869,6 @@ send_trailer_dont_update_qm:
.if !$defined("HDSL_MULTICHANNEL")
WAIT_CLK_LOW REG_TMP0
.endif
RESET_CYCLCNT
RET1
;--------------------------------------------------------------------------------------------------
@ -1906,6 +1916,7 @@ update_events_no_int18:
; REG_TMP0, REG_FNC
;--------------------------------------------------------------------------------------------------
switch_clk:
.if !$defined("HDSL_MULTICHANNEL")
WAIT_CLK_LOW REG_TMP0
WAIT_CLK_HIGH REG_TMP0
sub REG_FNC.b2, REG_FNC.b2, 1
@ -1914,6 +1925,7 @@ switch_clk:
;ldi REG_SCRATCH, P0EDTXCFG+2
sbco &REG_FNC.w0, ICSS_CFGx, EDTXCFG+2, 2
WAIT_CLK_HIGH REG_TMP0
.endif
RET1
;--------------------------------------------------------------------------------------------------
;Function: qm_add (RET_ADDR1)
@ -1976,6 +1988,7 @@ wait_delay:
NOP_2
NOP_2
NOP_2
NOP_2
.endif ;HDSL_MULTICHANNEL
; same code as in learn
@ -2067,9 +2080,8 @@ calc_rssi_discard:
comp_logic_starts:
.if $defined(EXT_SYNC_ENABLE)
;compensation logic for diff between sync signal and extra edge starts;
qbne num_pulses_is_not_one2, NUM_PULSES, 1 ;not the last frame of period
PUSH_FIFO_2B_8x
mov EXTRA_EDGE_COMP, EXTRA_EDGE
mov EXTRA_SIZE_COMP, EXTRA_SIZE
mov NUM_STUFFING_COMP, NUM_STUFFING
@ -2090,7 +2102,7 @@ comp_logic_starts:
no_capping1:
mov REG_TMP1, REG_FNC ;taking backup
mov REG_FNC.w0, REG_TMP0
ldi REG_FNC.w2, 4;3
ldi REG_FNC.w2, 3;3
CALL1 int_div
mov REG_TMP0.b0, REG_FNC.b2
qbeq no_reminder1, REG_FNC.w0, 0
@ -2109,7 +2121,7 @@ extra_edge_ahead:
no_capping2:
mov REG_TMP1, REG_FNC ;taking backup
mov REG_FNC.w0, REG_TMP0
ldi REG_FNC.w2, 4;3
ldi REG_FNC.w2, 3;3
CALL1 int_div
mov REG_TMP0.b0, REG_FNC.b2
qbeq no_reminder2, REG_FNC.w0, 0
@ -2124,7 +2136,6 @@ cycle_diff_more_than_max_allowed:
child_overhead_more1:
.if $defined("HDSL_MULTICHANNEL")
PUSH_FIFO_2B_8x
.endif
ldi REG_TMP1.b0, 8
sub REG_TMP1.b0, REG_TMP1.b0, TIME_REST_COMP
@ -2140,7 +2151,6 @@ time_rest_comp_not_8_1:
qba check_time_rest_size_violation1
self_overhead_more1:
.if $defined("HDSL_MULTICHANNEL")
PUSH_FIFO_2B_8x
.endif
ldi REG_TMP1.b0, 8
sub REG_TMP1.b0, REG_TMP1.b0, TIME_REST_COMP
@ -2165,6 +2175,10 @@ check_time_rest_size_violation1:
comp_done1:
mov REG_TMP0.b1, TIME_REST_COMP
ldi EXTRA_EDGE_COMP, 0
.if $defined("HDSL_MULTICHANNEL")
PUSH_FIFO_2B_8x
.endif
qbeq extra_edge_bit_setting_loop_end1, REG_TMP0.b1, 0
ldi REG_TMP0.b2, 7
extra_edge_bit_setting1:
@ -2190,9 +2204,7 @@ send_header_extra_not_too_small1:
add NUM_STUFFING_COMP, NUM_STUFFING_COMP, 1
extra_size_validation_done1:
num_pulses_is_not_one2:
.if $defined("HDSL_MULTICHANNEL")
PUSH_FIFO_2B_8x
.endif
.if !$defined("HDSL_MULTICHANNEL")
jmp comp_logic_done_1
.endif
@ -2207,7 +2219,7 @@ num_pulses_is_not_one2:
.endif
.if $defined("HDSL_MULTICHANNEL")
comp_logic_ends:
qbeq comp1,LEARN_STATE_STARTED,2
qbeq comp2,LEARN_STATE_STARTED,2
qbeq comp1,LEARN_STATE_STARTED,3
ldi LEARN_STATE_STARTED , 1
jmp comp_logic_done
@ -2215,5 +2227,11 @@ comp_logic_ends:
comp1:
ldi LEARN_STATE_STARTED , 1
jmp transport_layer_recv_msg
comp2:
WAIT_TX_FIFO_FREE
PUSH_FIFO_1_8x
PUSH_FIFO_2_8x
ldi LEARN_STATE_STARTED , 1
jmp transport_layer_recv_msg
.endif
;***********************************************************************************************************;

7
source/position_sense/hdsl/firmware/datalink_init.asm
View File

@ -268,11 +268,10 @@ datalink_learn:
NOP_2
.endif
.if $defined("HDSL_MULTICHANNEL")
.if $defined("CHANNEL_0")
NOP_2
NOP_2
.endif
.endif
; measured starting point at 0 cable length
; first 8 bits will be all ones is delay from encoder and transceiver
; second 8 bits is oversampled DSL bit which is 0 on test pattern
@ -361,12 +360,13 @@ datalink_learn_skip_one_bit_1:
; pre-load register to save time on last bit
; ldi REG_TMP2, (74*CYCLES_BIT-9) ; 100 m
.if $defined("FREERUN_300_MHZ")
ldi r3, (74*CYCLES_BIT+9-2)
ldi r3, (74*CYCLES_BIT+9)
.else
ldi r3, (74*CYCLES_BIT+9)
.endif
datalink_learn_recv_loop_last_bit:
qbbc datalink_learn_recv_loop_last_bit, r31, RX_VALID_FLAG
; now finisch with last bit sample and store
@ -396,7 +396,6 @@ datalink_learn_recv_loop_final:
sub REG_TMP11, r3, REG_TMP2
MOV REG_TMP2.b0, REG_TMP11.b0
; WAIT subracts -1 from parameter before compare. On 0 it wraps around!!!
WAIT REG_TMP11
datalink_learn_skip_wait:

431
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
View File

@ -54,15 +54,15 @@
*
*/
const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x21078400,
0x21078b00,
0x2eff8f8e,
0x24000725,
0x24041e8d,
0x2301d49d,
0x2301599d,
0x2301d19d,
0x2301569d,
0x05012525,
0x510025cb,
0x2302dcd1,
0x510025c8,
0x2302cbd1,
0xd70170f8,
0xcf0723f7,
0x1f02c4c4,
@ -94,62 +94,59 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x11807070,
0x1031310d,
0x51015904,
0x2301d49d,
0x2301d19d,
0x24000159,
0x79000003,
0x2301ef9d,
0x2301e99d,
0x10e0e0e0,
0x2301599d,
0x2301569d,
0xd101700f,
0xc9072306,
0x5101450a,
0x2400040d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000009,
0x69014508,
0x2400060d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000004,
0x2400010d,
0x000d6666,
0x230344d1,
0x23033bd1,
0x1d03c4c4,
0x2302dcd1,
0x2305ab9d,
0x2302cbd1,
0x2305ae9d,
0x05014545,
0x51074517,
0x51074514,
0x49004502,
0x21005300,
0x21005000,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x31010005,
0x31030004,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x51000c02,
0x2400ff1e,
0x810c3c80,
0x7f0000cd,
0x7f0000d0,
0x24000070,
0x24000845,
0x1f01c4c4,
0x2400ff1e,
0x7f0000c8,
0xcf01c4ec,
0x7f0000cb,
0xcf01c4ef,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400001e,
0x7f0000c2,
0x7f0000c5,
0x24002005,
0x230352d1,
0x230349d1,
0x24000080,
0x2405a4eb,
0x2eff8992,
@ -162,7 +159,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f6,
0x24001d05,
0xc918ff00,
@ -174,7 +171,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0105f6,
0xc918ff00,
0x101f1f00,
@ -182,7 +179,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00f3f3,
0x0903f3f3,
0x1f18ffff,
0x240945e1,
0x240949e1,
0x910c3c80,
0x58e1e006,
0x04e0e1e0,
@ -191,8 +188,8 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x0501e0e0,
0x4f00e0ff,
0x1d007e7e,
0x2302ffd1,
0x2302dcd1,
0x2302fad1,
0x2302cbd1,
0x209d0000,
0x91502181,
0x91502194,
@ -264,7 +261,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x240012e0,
0x810c3c80,
0x20d10000,
0x21032300,
0x21032500,
0x10d1d182,
0x240000cd,
0xc918ff00,
@ -275,7 +272,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -294,7 +291,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -317,7 +314,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x23036bd1,
0x230363d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -342,7 +339,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -361,7 +358,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -384,7 +381,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x23036bd1,
0x230363d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -401,10 +398,10 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x20d10000,
0x24000605,
0x2eff8283,
0x230352d1,
0x230349d1,
0x240000c0,
0x2400002d,
0x2300d3d1,
0x2300d0d1,
0x100d0d03,
0x0908f3f3,
0x0b18f2e0,
@ -421,7 +418,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10808098,
0x2400012d,
0x24000605,
0x2300d3d1,
0x2300d0d1,
0x100d0d23,
0x0905f7f7,
0x0b1bf6e0,
@ -431,15 +428,15 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x12e0f6f6,
0x2400022d,
0x24000605,
0x2300d3d1,
0x2300d0d1,
0x100d0d43,
0x2400032d,
0x24000605,
0x2300d3d1,
0x2300d0d1,
0x100d0d84,
0x2400042d,
0x24000605,
0x2300d3d1,
0x2300d0d1,
0x09088484,
0x120d8484,
0x240000c0,
@ -455,32 +452,32 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f04c4c4,
0x2400060d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000006,
0xc9005005,
0x51fd0304,
0x2400020d,
0x040d6666,
0x230344d1,
0x23033bd1,
0xc9017005,
0x2400010d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000005,
0xc9015004,
0x2400020d,
0x040d6666,
0x230344d1,
0x23033bd1,
0xc9027004,
0x2400010d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x111870e0,
0x5100e006,
0x1f03c4c4,
0x2400020d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000008,
0xc9035002,
0x69fd2403,
@ -488,10 +485,10 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x51fd0404,
0x2400020d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x2400052d,
0x24000605,
0x230116d1,
0x230113d1,
0x1d007e7e,
0x240949e1,
0x910c3c80,
@ -500,7 +497,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x0b01e0e0,
0x0501e0e0,
0x4f00e0ff,
0x2302ffd1,
0x2302fad1,
0x100d0d63,
0x0908f5f5,
0x0b18f4e0,
@ -512,7 +509,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f05c4c4,
0x2400080d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x14637878,
0x69014502,
0x15ff7878,
@ -544,10 +541,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x51000c05,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x51000c02,
0x810c3c80,
0x000c1111,
0xd107110b,
@ -575,16 +569,20 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x24013081,
0x24ffffc1,
0x808113c1,
0xc901c40a,
0x69084504,
0xc901c40e,
0x69084506,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400ff1e,
0x21039a00,
0x69074505,
0xc901c403,
0x2103ae00,
0x69074507,
0xc901c405,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x2103e700,
0x21040200,
0x51000c2d,
0x51015b04,
0x100c0c02,
@ -693,7 +691,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21052000,
0x21052300,
0xd1077905,
0xd104ff00,
0xd703ffff,
@ -727,45 +725,30 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x2300a4d1,
0x79000039,
0x511f0d38,
0x51190d37,
0x2300a1d1,
0x7900002a,
0x511f0d29,
0x51190d28,
0x91001879,
0xc9077902,
0x2102b500,
0x2102b300,
0x91351879,
0xc9077902,
0x2102b500,
0x2102b300,
0x10f7f779,
0x0b037979,
0x111f7979,
0x51107907,
0xd10ac406,
0x111f2379,
0xd1047905,
0x106d6d79,
0x2400037b,
0x21037000,
0x2102c700,
0x21036800,
0x2102b600,
0x106d6d79,
0x2400027b,
0x3101000f,
0xd1077905,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x79000004,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0x21037000,
0x21043300,
0x21036800,
0x21044e00,
0xd104ff00,
0xd703ffff,
0xd1074d03,
@ -787,38 +770,50 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x24000126,
0x209d0000,
0x10d1d1eb,
0x51002c20,
0x51002c2c,
0x910c3c80,
0x0da4e0e2,
0x102c2c6d,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400001e,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400ff1e,
0xd104ff00,
0xd703ffff,
0x2400001e,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x05016d6d,
0x51006d0f,
0x51006d19,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400001e,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400001e,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400ff1e,
0x2400ff1e,
0x05016d6d,
0x6f006df3,
0x6f016df5,
0xd104ff00,
0xd703ffff,
0x2400001e,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400ff1e,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400ff1e,
0x2400ff1e,
0x10ebebd1,
0x20d10000,
0x31010001,
@ -840,6 +835,8 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd104ff00,
0xd703ffff,
0x2400001e,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x09041001,
@ -847,13 +844,18 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x24000011,
0x810a1801,
0x59021006,
0x10d1d18b,
0x2400040d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x108b8bd1,
0x810c3c80,
0x20d10000,
@ -877,24 +879,13 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00c0c0,
0x1f008181,
0x81505880,
0x21063900,
0x91042580,
0xd708e0ff,
0x91042580,
0xcf08e0ff,
0x05014d4d,
0x6f014dfb,
0x91042580,
0xd708e0ff,
0x8106058d,
0x91042580,
0xcf08e0ff,
0x21064000,
0x20d10000,
0x117f6666,
0xc9066604,
0x24000066,
0x81031866,
0x7f0000db,
0x7f0000e6,
0x710f6602,
0x24000f66,
0x590e6604,
@ -918,6 +909,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x1f007e7e,
0x810c3c80,
0x24000c10,
@ -962,12 +954,40 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x51027b04,
0x51027b06,
0x51037b03,
0x2400017b,
0x2102c800,
0x2102b700,
0x2400017b,
0x21043300,
0x21044e00,
0xd104ff00,
0xd703ffff,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0xd1077905,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x79000004,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0x2400017b,
0x21044e00,
0x2eff838e,
0x24003f00,
0x81401800,
@ -995,11 +1015,15 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81521802,
0x2400060d,
0x040d6666,
0x230344d1,
0x7900002d,
0x23033bd1,
0x7900002e,
0xd104ff00,
0xd703ffff,
0x31020002,
0x2400ff1e,
0x2400010d,
0x000d6666,
0x230344d1,
0x23033bd1,
0x69fd7309,
0x913d1880,
0x1f040000,
@ -1008,7 +1032,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400269f,
0x1f020202,
0x81521802,
0x79000021,
0x79000023,
0x81521802,
0x0908f3e2,
0x10727202,
@ -1021,15 +1045,11 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xc91fe203,
0x1600e2e2,
0x0101e2e2,
0xd104ff00,
0xd703ffff,
0x31010002,
0x2400ff1e,
0x6900e104,
0x686e5303,
0x24000019,
0x79000002,
0x230619d1,
0x230620d1,
0x10535300,
0x10333320,
0x10131340,
@ -1041,8 +1061,15 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x2103f500,
0x31010004,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x51000c03,
0x2400ff1e,
0x51000c05,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x810c3c80,
0x240000e0,
@ -1052,7 +1079,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10abab8d,
0x240000f8,
0x11cf4444,
0x21020e00,
0x21020a00,
0x108d8dab,
0x91637881,
0x91541800,
@ -1064,13 +1091,13 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81541800,
0x2400060d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000017,
0x1d058000,
0x81541800,
0x2400010d,
0x000d6666,
0x230344d1,
0x23033bd1,
0x91541800,
0x69fd6204,
0x1f028000,
@ -1088,11 +1115,6 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81463882,
0x814a3881,
0x2400249f,
0x915a1800,
0x69010004,
0x915b7800,
0x81197800,
0x2400239f,
0x69074509,
0xc901c408,
0xd104ff00,
@ -1102,6 +1124,11 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x51000c03,
0x2400ff1e,
0x810c3c80,
0x915a1800,
0x69010004,
0x915b7800,
0x81197800,
0x2400239f,
0x24000300,
0x814e1800,
0x91701800,
@ -1128,13 +1155,13 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f060242,
0x81503802,
0x10abab8d,
0x21021300,
0x21021100,
0x91001800,
0xc9070002,
0x21032300,
0x21032500,
0x91351800,
0xc9070002,
0x21032300,
0x21032500,
0x51005c2c,
0x110ff602,
0x49085c02,
@ -1178,12 +1205,12 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1d050000,
0x81511800,
0x05045c5c,
0x790000bb,
0x790000a3,
0x0b03f700,
0x111f0000,
0x5110008f,
0xd10ac4b7,
0xd104008e,
0x51100077,
0xd10ac49f,
0xd1040076,
0x1f0ac4c4,
0x111f006b,
0x09046b6b,
@ -1192,17 +1219,6 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x12200000,
0x110f0000,
0x12006b6b,
0x10f6f6e2,
0x24002c01,
0x31020007,
0x110f0220,
0x0b01e240,
0x11f04040,
0x12402000,
0x2d000001,
0x0b0ae2e2,
0xd1076b38,
0x24003001,
0xd104ff00,
0xd703ffff,
0xd1077903,
@ -1229,10 +1245,21 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x10f6f6e2,
0x24002c01,
0x31020007,
0x110f0220,
0x0b01e240,
0x11f04040,
0x12402000,
0x2d000001,
0x0b0ae2e2,
0xd1076b1e,
0x24003001,
0xd1066b0e,
0x2400010d,
0x230776d1,
0x68ab8d5d,
0x23077dd1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
0x1f008080,
@ -1242,10 +1269,10 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91531800,
0x1f000000,
0x81531800,
0x79000053,
0x7900003b,
0x2400020d,
0x230776d1,
0x688b8d50,
0x23077dd1,
0x688b8d38,
0x8137184b,
0x13803b3b,
0x913d1880,
@ -1256,7 +1283,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91531800,
0x1f000000,
0x81531800,
0x79000045,
0x7900002d,
0x0b026b00,
0x11030000,
0x2400005c,
@ -1285,33 +1312,9 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f010000,
0x81511800,
0x1d09c4c4,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0xd1077905,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x79000004,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0x2400040d,
0x24003001,
0x230776d1,
0x23077dd1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1365,7 +1368,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400181b,
0xc9027a02,
0x01081b1b,
0x2102c800,
0x2102b700,
0xc901c460,
0x24001031,
0x91001800,
@ -1504,13 +1507,9 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x79000002,
0x1d030101,
0x81501801,
0x21028000,
0x21027e00,
0x24000000,
0x814e1800,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400001e,
0xd103c40a,
0x151f8484,
0x240478e2,
@ -1520,13 +1519,13 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xf020020d,
0x69000d03,
0x24fdfd80,
0x68808426,
0x6880842a,
0x91381800,
0x01010000,
0x81381800,
0x91411820,
0x60200002,
0x21032300,
0x21032500,
0x109d9d8b,
0x0901c880,
0x090288c0,
@ -1552,12 +1551,16 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x108787c7,
0x04c98087,
0x108080c9,
0x230600d1,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400001e,
0x230607d1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
0x81aa1800,
0x79000010,
0x79000014,
0x8138180d,
0x0b05848d,
0x14e0e0e0,
@ -1572,7 +1575,11 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x108787c7,
0x04c98087,
0x108080c9,
0x230600d1,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x2400001e,
0x230607d1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1665,7 +1672,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x810b1800,
0x81441800,
0x2eff8383,
0x2303929d,
0x2303a69d,
0x24000866,
0x2400000c,
0x2400002c,
@ -1695,7 +1702,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x9101185b,
0x51005b0e,
0x7900000d,
0x23008cd1,
0x230089d1,
0x91dc388c,
0x240000e2,
0x91e21882,
@ -1703,7 +1710,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x100c0c2a,
0x106c6c4a,
0x102c2c6a,
0x23008cd1,
0x230089d1,
0x0b01e2e2,
0x0501e2e2,
0x4f00e2ff,
@ -1717,20 +1724,20 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400001e,
0x2400001c,
0x24001f8d,
0x2301d49d,
0x2302dcd1,
0x2301d19d,
0x2302cbd1,
0x01011c1c,
0x6f021cfc,
0x2400001c,
0x2400198d,
0x2301d49d,
0x2302dcd1,
0x2301d19d,
0x2302cbd1,
0x01011c1c,
0x6f101cfc,
0x2400017b,
0x24000925,
0x24001a8d,
0x2301d49d,
0x2301d19d,
0xd105ff00,
0x31010001,
0x31010001,
@ -1780,7 +1787,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2d802101,
0x05080505,
0x6f0005e3,
0x240947e3,
0x240949e3,
0xc918ff00,
0x101f1f00,
0x05014545,
@ -1884,7 +1891,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x0b077200,
0x12001313,
0x0901f2f2,
0x230098d1,
0x230095d1,
0x510e6506,
0x6f010df6,
0x10656546,
@ -1911,24 +1918,24 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x7d0000fb,
0x24000925,
0x24001b8d,
0x2301d49d,
0x23005e9d,
0x230098d1,
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010ded,
0x05012525,
0x4f0025fa,
0x24001025,
0x24001c8d,
0x2301d49d,
0x23005e9d,
0x230098d1,
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010de1,
0x05012525,
0x4f0025fa,
0x810a1846,
0x24001d8d,
0x2301d49d,
0x2301599d,
0x2301d19d,
0x2301569d,
0x6e0403da,
0x6e2423d9,
0x110f4300,
@ -1942,7 +1949,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x810d3801,
0x2400000d,
0x000d6666,
0x230344d1,
0x23033bd1,
0x1f08c4c4,
0x110fe05d,
0x01085d5d,
@ -1956,7 +1963,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x24ffff81,
0x0a00e1e1,
0x81e43881,
0x2302dcd1,
0x2302cbd1,
0x21000100,
0x91043880,
0x1e0d8080,
@ -1981,5 +1988,5 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x21063900};
0x21064000};

491
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h
View File

File diff suppressed because it is too large Load Diff

439
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h
View File

@ -2,7 +2,7 @@
* hdsl_master_icssg_multichannel_ch1_bin.h
*
*
* Copyright (c)2021-2023, Texas Instruments Incorporated
* Copyright (c) 2021-2023, Texas Instruments Incorporated
* All rights reserved not granted herein.
*
* Limited License.
@ -54,15 +54,15 @@
*
*/
const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x21078300,
0x21078c00,
0x2eff8f8e,
0x24000725,
0x24041e8d,
0x2301d49d,
0x2301599d,
0x2301d19d,
0x2301569d,
0x05012525,
0x510025cb,
0x2302dcd1,
0x510025c8,
0x2302cbd1,
0xd70170f8,
0xcf0723f7,
0x1f02c4c4,
@ -94,62 +94,59 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x11807070,
0x1031310d,
0x51015904,
0x2301d49d,
0x2301d19d,
0x24000159,
0x79000003,
0x2301ef9d,
0x2301e99d,
0x10e0e0e0,
0x2301599d,
0x2301569d,
0xd101700f,
0xc9072306,
0x5101450a,
0x2400040d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000009,
0x69014508,
0x2400060d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000004,
0x2400010d,
0x000d6666,
0x230344d1,
0x23033bd1,
0x1d03c4c4,
0x2302dcd1,
0x2305ab9d,
0x2302cbd1,
0x2305ae9d,
0x05014545,
0x51074517,
0x51074514,
0x49004502,
0x21005300,
0x21005000,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x31010005,
0x31030004,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400ff1e,
0x51000c02,
0x2400ff1e,
0x810c3c80,
0x7f0000cd,
0x7f0000d0,
0x24000070,
0x24000845,
0x1f01c4c4,
0x2400ff1e,
0x7f0000c8,
0xcf01c4ec,
0x7f0000cb,
0xcf01c4ef,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400001e,
0x7f0000c2,
0x7f0000c5,
0x24002005,
0x230352d1,
0x230349d1,
0x24000080,
0x240ca4eb,
0x2eff8992,
@ -162,7 +159,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f6,
0x24001d05,
0xc919ff00,
@ -174,7 +171,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0105f6,
0xc919ff00,
0x103f3f00,
@ -182,7 +179,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f00f3f3,
0x0903f3f3,
0x1f19ffff,
0x240945e1,
0x240949e1,
0x910c3c80,
0x58e1e006,
0x04e0e1e0,
@ -191,8 +188,8 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x0501e0e0,
0x4f00e0ff,
0x1d017e7e,
0x2302ffd1,
0x2302dcd1,
0x2302fad1,
0x2302cbd1,
0x209d0000,
0x91502181,
0x91502194,
@ -264,7 +261,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x240012e0,
0x810c3c80,
0x20d10000,
0x21032300,
0x21032500,
0x10d1d182,
0x240000cd,
0xc919ff00,
@ -275,7 +272,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f7,
0x240820eb,
0xf0cd0b0d,
@ -294,7 +291,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -317,7 +314,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x23036bd1,
0x230363d1,
0x110fcdc0,
0x240868eb,
0xf0c00b00,
@ -342,7 +339,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f7,
0x240820eb,
0xf0cd0b0d,
@ -361,7 +358,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x23036bd1,
0x230363d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -384,7 +381,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x23036bd1,
0x230363d1,
0x110fcdc0,
0x240868eb,
0xf0c00b00,
@ -401,10 +398,10 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x20d10000,
0x24000605,
0x2eff8283,
0x230352d1,
0x230349d1,
0x240000c0,
0x2400002d,
0x2300d3d1,
0x2300d0d1,
0x100d0d03,
0x0908f3f3,
0x0b18f2e0,
@ -421,7 +418,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10808098,
0x2400012d,
0x24000605,
0x2300d3d1,
0x2300d0d1,
0x100d0d23,
0x0905f7f7,
0x0b1bf6e0,
@ -431,15 +428,15 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x12e0f6f6,
0x2400022d,
0x24000605,
0x2300d3d1,
0x2300d0d1,
0x100d0d43,
0x2400032d,
0x24000605,
0x2300d3d1,
0x2300d0d1,
0x100d0d84,
0x2400042d,
0x24000605,
0x2300d3d1,
0x2300d0d1,
0x09088484,
0x120d8484,
0x240000c0,
@ -455,32 +452,32 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f04c4c4,
0x2400060d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000006,
0xc9005005,
0x51fd0304,
0x2400020d,
0x040d6666,
0x230344d1,
0x23033bd1,
0xc9017005,
0x2400010d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000005,
0xc9015004,
0x2400020d,
0x040d6666,
0x230344d1,
0x23033bd1,
0xc9027004,
0x2400010d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x111870e0,
0x5100e006,
0x1f03c4c4,
0x2400020d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000008,
0xc9035002,
0x69fd2403,
@ -488,10 +485,10 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x51fd0404,
0x2400020d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x2400052d,
0x24000605,
0x230116d1,
0x230113d1,
0x1d017e7e,
0x240949e1,
0x910c3c80,
@ -500,7 +497,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x0b01e0e0,
0x0501e0e0,
0x4f00e0ff,
0x2302ffd1,
0x2302fad1,
0x100d0d63,
0x0908f5f5,
0x0b18f4e0,
@ -512,7 +509,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f05c4c4,
0x2400080d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x14637878,
0x69014502,
0x15ff7878,
@ -544,10 +541,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd70bffff,
0x2400ff1e,
0x2400ff1e,
0x51000c05,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x51000c02,
0x810c3c80,
0x000c1111,
0xd107110b,
@ -575,16 +569,20 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x24013081,
0x24ffffc1,
0x808113c1,
0xc901c40a,
0x69084504,
0xc901c40e,
0x69084506,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400ff1e,
0x21039a00,
0x69074505,
0xc901c403,
0x2103ae00,
0x69074507,
0xc901c405,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400ff1e,
0x2103e700,
0x21040200,
0x51000c2d,
0x51015b04,
0x100c0c02,
@ -693,7 +691,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21052000,
0x21052300,
0xd1077905,
0xd10cff00,
0xd70bffff,
@ -727,45 +725,30 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x2300a4d1,
0x79000039,
0x511f0d38,
0x51190d37,
0x2300a1d1,
0x7900002a,
0x511f0d29,
0x51190d28,
0x91001879,
0xc9077902,
0x2102b500,
0x2102b300,
0x91351879,
0xc9077902,
0x2102b500,
0x2102b300,
0x10f7f779,
0x0b037979,
0x111f7979,
0x51107907,
0xd10ac406,
0x111f2379,
0xd1047905,
0x106d6d79,
0x2400037b,
0x21037000,
0x2102c700,
0x21036800,
0x2102b600,
0x106d6d79,
0x2400027b,
0x3101000f,
0xd1077905,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x79000004,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0x21037000,
0x21043300,
0x21036800,
0x21044e00,
0xd10cff00,
0xd70bffff,
0xd1074d03,
@ -787,38 +770,50 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x24000126,
0x209d0000,
0x10d1d1eb,
0x51002c20,
0x51002c2c,
0x910c3c80,
0x0da4e0e2,
0x102c2c6d,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400001e,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400ff1e,
0xd10cff00,
0xd70bffff,
0x2400001e,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400ff1e,
0x05016d6d,
0x51006d0f,
0x51006d19,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400001e,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400001e,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400ff1e,
0x2400ff1e,
0x05016d6d,
0x6f006df3,
0x6f016df5,
0xd10cff00,
0xd70bffff,
0x2400001e,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400ff1e,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400ff1e,
0x2400ff1e,
0x10ebebd1,
0x20d10000,
0x31010001,
@ -840,6 +835,8 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd10cff00,
0xd70bffff,
0x2400001e,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400ff1e,
0x09041001,
@ -847,13 +844,18 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x24000011,
0x810a1801,
0x59021006,
0x10d1d18b,
0x2400040d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x108b8bd1,
0x810c3c80,
0x20d10000,
@ -877,24 +879,13 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f00c0c0,
0x1f008181,
0x81505880,
0x21063900,
0x91042580,
0xd709e0ff,
0x91042580,
0xcf09e0ff,
0x05014d4d,
0x6f014dfb,
0x91042580,
0xd709e0ff,
0x8106058d,
0x91042580,
0xcf09e0ff,
0x21064000,
0x20d10000,
0x117f6666,
0xc9066604,
0x24000066,
0x81031866,
0x7f0000db,
0x7f0000e6,
0x710f6602,
0x24000f66,
0x590e6604,
@ -918,6 +909,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x1f017e7e,
0x810c3c80,
0x24000c10,
@ -962,12 +954,40 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x51027b04,
0x51027b06,
0x51037b03,
0x2400017b,
0x2102c800,
0x2102b700,
0x2400017b,
0x21043300,
0x21044e00,
0xd10cff00,
0xd70bffff,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0xd1077905,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x79000004,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0x2400017b,
0x21044e00,
0x2eff838e,
0x24003f00,
0x81401800,
@ -995,11 +1015,15 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81521802,
0x2400060d,
0x040d6666,
0x230344d1,
0x7900002d,
0x23033bd1,
0x7900002e,
0xd10cff00,
0xd70bffff,
0x31020002,
0x2400ff1e,
0x2400010d,
0x000d6666,
0x230344d1,
0x23033bd1,
0x69fd7309,
0x913d1880,
0x1f040000,
@ -1008,7 +1032,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400269f,
0x1f020202,
0x81521802,
0x79000021,
0x79000023,
0x81521802,
0x0908f3e2,
0x10727202,
@ -1021,15 +1045,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xc91fe203,
0x1600e2e2,
0x0101e2e2,
0xd10cff00,
0xd70bffff,
0x31010002,
0x2400ff1e,
0x6900e104,
0x686e5303,
0x24000019,
0x79000002,
0x230619d1,
0x230620d1,
0x10535300,
0x10333320,
0x10131340,
@ -1041,8 +1061,15 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x2103f500,
0x31010004,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x51000c03,
0x2400ff1e,
0x51000c05,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x810c3c80,
0x240000e0,
@ -1052,7 +1079,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10abab8d,
0x240000f8,
0x11cf4444,
0x21020e00,
0x21020a00,
0x108d8dab,
0x91637881,
0x91541800,
@ -1064,13 +1091,13 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81541800,
0x2400060d,
0x040d6666,
0x230344d1,
0x23033bd1,
0x79000017,
0x1d058000,
0x81541800,
0x2400010d,
0x000d6666,
0x230344d1,
0x23033bd1,
0x91541800,
0x69fd6204,
0x1f028000,
@ -1088,11 +1115,6 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81463882,
0x814a3881,
0x2400249f,
0x915a1800,
0x69010004,
0x915b7800,
0x81197800,
0x2400239f,
0x69074509,
0xc901c408,
0xd10cff00,
@ -1102,6 +1124,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x51000c03,
0x2400ff1e,
0x810c3c80,
0x915a1800,
0x69010004,
0x915b7800,
0x81197800,
0x2400239f,
0x24000300,
0x814e1800,
0x91701800,
@ -1128,13 +1155,13 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f060242,
0x81503802,
0x10abab8d,
0x21021300,
0x21021100,
0x91001800,
0xc9070002,
0x21032300,
0x21032500,
0x91351800,
0xc9070002,
0x21032300,
0x21032500,
0x51005c2c,
0x110ff602,
0x49085c02,
@ -1178,12 +1205,12 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1d050000,
0x81511800,
0x05045c5c,
0x790000bb,
0x790000a3,
0x0b03f700,
0x111f0000,
0x5110008f,
0xd10ac4b7,
0xd104008e,
0x51100077,
0xd10ac49f,
0xd1040076,
0x1f0ac4c4,
0x111f006b,
0x09046b6b,
@ -1192,17 +1219,6 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x12200000,
0x110f0000,
0x12006b6b,
0x10f6f6e2,
0x24002c01,
0x31020007,
0x110f0220,
0x0b01e240,
0x11f04040,
0x12402000,
0x2d000001,
0x0b0ae2e2,
0xd1076b38,
0x24003001,
0xd10cff00,
0xd70bffff,
0xd1077903,
@ -1229,10 +1245,21 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x10f6f6e2,
0x24002c01,
0x31020007,
0x110f0220,
0x0b01e240,
0x11f04040,
0x12402000,
0x2d000001,
0x0b0ae2e2,
0xd1076b1e,
0x24003001,
0xd1066b0e,
0x2400010d,
0x230775d1,
0x68ab8d5d,
0x23077ed1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
0x1f008080,
@ -1242,10 +1269,10 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x91531800,
0x1f000000,
0x81531800,
0x79000053,
0x7900003b,
0x2400020d,
0x230775d1,
0x688b8d50,
0x23077ed1,
0x688b8d38,
0x8137184b,
0x13803b3b,
0x913d1880,
@ -1256,7 +1283,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x91531800,
0x1f000000,
0x81531800,
0x79000045,
0x7900002d,
0x0b026b00,
0x11030000,
0x2400005c,
@ -1285,33 +1312,9 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f010000,
0x81511800,
0x1d09c4c4,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0xd1077905,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x79000004,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0x2400040d,
0x24003001,
0x230775d1,
0x23077ed1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1365,7 +1368,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400181b,
0xc9027a02,
0x01081b1b,
0x2102c800,
0x2102b700,
0xc901c460,
0x24001031,
0x91001800,
@ -1504,13 +1507,9 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x79000002,
0x1d030101,
0x81501801,
0x21028000,
0x21027e00,
0x24000000,
0x814e1800,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400001e,
0xd103c40a,
0x151f8484,
0x240b78e2,
@ -1520,13 +1519,13 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xf020020d,
0x69000d03,
0x24fdfd80,
0x68808426,
0x6880842a,
0x91381800,
0x01010000,
0x81381800,
0x91411820,
0x60200002,
0x21032300,
0x21032500,
0x109d9d8b,
0x0901c880,
0x090288c0,
@ -1552,12 +1551,16 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x108787c7,
0x04c98087,
0x108080c9,
0x230600d1,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400001e,
0x230607d1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
0x81aa1800,
0x79000010,
0x79000014,
0x8138180d,
0x0b05848d,
0x14e0e0e0,
@ -1572,7 +1575,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x108787c7,
0x04c98087,
0x108080c9,
0x230600d1,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x2400001e,
0x230607d1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1666,7 +1673,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x810b1800,
0x81441800,
0x2eff8383,
0x2303929d,
0x2303a69d,
0x24000866,
0x2400000c,
0x2400002c,
@ -1696,7 +1703,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x9101185b,
0x51005b0e,
0x7900000d,
0x23008cd1,
0x230089d1,
0x91dc388c,
0x240000e2,
0x91e21882,
@ -1704,7 +1711,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x100c0c2a,
0x106c6c4a,
0x102c2c6a,
0x23008cd1,
0x230089d1,
0x0b01e2e2,
0x0501e2e2,
0x4f00e2ff,
@ -1718,20 +1725,20 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400001e,
0x2400001c,
0x24001f8d,
0x2301d49d,
0x2302dcd1,
0x2301d19d,
0x2302cbd1,
0x01011c1c,
0x6f021cfc,
0x2400001c,
0x2400198d,
0x2301d49d,
0x2302dcd1,
0x2301d19d,
0x2302cbd1,
0x01011c1c,
0x6f101cfc,
0x2400017b,
0x24000925,
0x24001a8d,
0x2301d49d,
0x2301d19d,
0xd10dff00,
0x31010001,
0x31010001,
@ -1741,6 +1748,8 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31000002,
0x0100e0e0,
0x1f017e7e,
@ -1779,7 +1788,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2d802101,
0x05080505,
0x6f0005e3,
0x240947e3,
0x240949e3,
0xc919ff00,
0x103f3f00,
0x05014545,
@ -1883,12 +1892,12 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x0b077200,
0x12001313,
0x0901f2f2,
0x230098d1,
0x230095d1,
0x510e6506,
0x6f010df6,
0x10656546,
0x05012525,
0x4f002562,
0x4f002560,
0x79000013,
0xd119fe04,
0xd10dff00,
@ -1907,27 +1916,27 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x813d1800,
0xc9022002,
0x2400269f,
0x7d0000fc,
0x7d0000fa,
0x24000925,
0x24001b8d,
0x2301d49d,
0x23005e9d,
0x230098d1,
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010ded,
0x05012525,
0x4f0025fa,
0x24001025,
0x24001c8d,
0x2301d49d,
0x23005e9d,
0x230098d1,
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010de1,
0x05012525,
0x4f0025fa,
0x810a1846,
0x24001d8d,
0x2301d49d,
0x2301599d,
0x2301d19d,
0x2301569d,
0x6e0403da,
0x6e2423d9,
0x110f4300,
@ -1941,7 +1950,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x810d3801,
0x2400000d,
0x000d6666,
0x230344d1,
0x23033bd1,
0x1f08c4c4,
0x110fe05d,
0x01085d5d,
@ -1955,7 +1964,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x24ffff81,
0x0a00e1e1,
0x81e43881,
0x2302dcd1,
0x2302cbd1,
0x21000100,
0x91043880,
0x1e0d8080,
@ -1980,5 +1989,5 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x21063900};
0x21064000};

497
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h
View File

File diff suppressed because it is too large Load Diff

94
source/position_sense/hdsl/firmware/transport.asm
View File

@ -137,6 +137,12 @@ transport_on_v_frame_dont_update_qm:
.endif
qba transport_on_v_frame_exit
check_for_slave_error_on_v_frame:
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
LOOP push_1B,3
PUSH_FIFO_CONST 0xff
push_1B:
.endif
;CRC was correct -> add 1 to QM
;Note: QM_ADD uses REG_TMP1
QM_ADD 1
@ -154,14 +160,16 @@ update_events_no_int5:
; Set ONLINE_STATUS_1_VPOS in ONLINE_STATUS_1 register
set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_VPOS
sbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
qba transport_on_v_frame_exit
qba no_first_push_for_exit
transport_on_v_frame_check_pos:
sbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
lsl REG_TMP2, CHANNEL.ch_verth, 8
mov REG_TMP2.b0, VERT_L.b3
;first V-Frame? -> update FAST POS with SAFE POS
transport_on_v_frame_not_first:
;check for LAST FAST POS and SAFE POS mismatch
lbco &REG_TMP0.b0, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS
sub REG_TMP1.w0, VERT_L.w2, REG_TMP0.w0
sub REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2
@ -176,12 +184,7 @@ no_sub_carry:
add REG_TMP2, REG_TMP2, 1
transport_on_v_frame_diff_pos:
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
LOOP push_1B,2
PUSH_FIFO_CONST 0xff
push_1B:
.endif
;check for diff. is 0 -> estimate if not
qbne transport_on_v_frame_estimate, REG_TMP1, 0
@ -219,13 +222,21 @@ transport_on_v_frame_no_pos_mismatch:
sbco &CRC_SEC, MASTER_REGS_CONST, CRC_SEC_TEMP, 2
; store the 8 bytes from secondary channel
sbco &R20, MASTER_REGS_CONST, VPOS2_TEMP, 8
jmp no_first_push_for_exit
transport_on_v_frame_exit:
;we are in RX0
;reset rel. pos
.if $defined("HDSL_MULTICHANNEL")
loop Wait_and_Push_2_byte,2
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff
Wait_and_Push_2_byte:
PUSH_FIFO_CONST 0xff
no_first_push_for_exit:
.if $defined("HDSL_MULTICHANNEL")
qbeq free_run_mode1, EXTRA_SIZE, 0
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff
RESET_CYCLCNT
free_run_mode1:
@ -321,7 +332,19 @@ online_status_2_sum2_not_set:
ldi r31.w0, PRU0_ARM_IRQ2
transport_on_v_frame_2_exit:
qbne not_7th_hframe_0, LOOP_CNT.b2, 7
qbbc not_7th_hframe_0, H_FRAME.flags, FLAG_NORMAL_FLOW
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
LOOP push_1B_0 ,2
PUSH_FIFO_CONST 0xff
push_1B_0:
qbeq free_run_mode2, EXTRA_SIZE, 0
PUSH_FIFO_CONST 0xff
RESET_CYCLCNT
free_run_mode2:
.endif
not_7th_hframe_0:
; Check for VPOS_VALID, If it is valid, update the position and crc to DMEM
; and raise interrupt
lbco &REG_TMP0.b0, MASTER_REGS_CONST, VPOS_VALID, 1
@ -331,19 +354,7 @@ transport_on_v_frame_2_exit:
; generate interrupt PRU0_ARM_IRQ1
ldi r31.w0, PRU0_ARM_IRQ1
transport_skip_vpos_update:
qbne not_7th_hframe_0, LOOP_CNT.b2, 7
qbbc not_7th_hframe_0, H_FRAME.flags, FLAG_NORMAL_FLOW
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
LOOP push_1B_0 ,2
PUSH_FIFO_CONST 0xff
push_1B_0:
qbeq free_run_mode2, EXTRA_SIZE, 0
PUSH_FIFO_CONST 0xff
RESET_CYCLCNT
free_run_mode2:
.endif
not_7th_hframe_0:
; Set POSTX to 3
ldi REG_TMP0.b0, 0x3
@ -497,6 +508,7 @@ transport_layer_check_for_new_msg:
;check for special character
qbbs transport_layer_recv_msg_check_for_nak, REG_TMP0.b0, 4
;set flag to signalize that we need to wait for next S_PAR_IDLE again, so we do not parse data multiple times
set H_FRAME.flags, H_FRAME.flags, FLAG_WAIT_IDLE
;reassemble 32 bits of msg, 5bits->4bits
@ -507,7 +519,11 @@ transport_layer_check_for_new_msg:
or REG_TMP0.b0, REG_TMP0.b0, REG_TMP0.b1
and REG_TMP0.b0, REG_TMP0.b0, 0x0f
or REG_TMP11.b3, REG_TMP11.b3, REG_TMP0.b0
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
PUSH_FIFO_1_8x
PUSH_FIFO_2_8x
.endif
mov REG_TMP2, CHANNEL.ch_paral
ldi REG_TMP1.b0, &REG_TMP11.b0
loop transport_layer_reassemble_msg_loop, 3
@ -519,16 +535,13 @@ transport_layer_check_for_new_msg:
lsr REG_TMP2, REG_TMP2, 10
transport_layer_reassemble_msg_loop:
;identify message type
qbbs transport_layer_received_long_msg, REG_TMP11.b3, 7
transport_layer_received_short_msg:
;check crc
ldi REG_TMP1.b0, &r12.b0
;read or write?
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
PUSH_FIFO_1_8x
PUSH_FIFO_2_8x
.endif
qbbs transport_layer_short_msg_recv_read, REG_TMP11.b3, 6
;received write ack
ldi REG_FNC.b0, 1
@ -624,10 +637,7 @@ update_events_no_int11:
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
clr H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY
transport_layer_received_long_msg_loffset_end:
.if $defined("HDSL_MULTICHANNEL")
PUSH_FIFO_1_8x
PUSH_FIFO_2_8x
.endif
;calculate CRC for already recevied bits
ldi REG_FNC.b0, 4
ldi r1.b0, &r12.b0
@ -994,11 +1004,7 @@ transport_on_h_frame:
sbco &REG_TMP0.b0, MASTER_REGS_CONST, POSTX, 1
;check for byte error in acceleration channel
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
PUSH_FIFO_CONST 0x00
.endif
qbbs transport_acc_err_inc, H_FRAME.flags, FLAG_ERR_ACC
;crc error verification
;CALL1 calc_acc_crc
@ -1014,6 +1020,7 @@ transport_on_h_frame:
ldi REG_TMP0.w0, DOUBLE_K29_7
qbne delta_delta_position, H_FRAME.acc, REG_TMP0.w0
transport_acc_err_inc:
;update the acc_err_cnt register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
add REG_TMP0.b0, REG_TMP0.b0, 1
@ -1074,6 +1081,11 @@ calc_speed_extend_acc1:
mov DELTA_ACC1, DELTA_ACC0
sub DELTA_ACC0, REG_TMP0.w0, LAST_ACC
mov LAST_ACC, REG_TMP0.w0
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
PUSH_FIFO_CONST 0x00
.endif
CALL1 calc_fastpos
;restore return addr
mov RET_ADDR0, REG_TMP11.w0
@ -1084,6 +1096,7 @@ calc_speed_extend_acc1:
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1
qba transport_on_h_frame_exit
delta_delta_position:
;reset ACC_ERR_CNT
sbco &REG_FNC.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
;shift out crc bits
@ -1105,6 +1118,11 @@ calc_speed_extend_acc0:
mov DELTA_ACC1, DELTA_ACC0
sub DELTA_ACC0, REG_TMP0.w0, LAST_ACC
mov LAST_ACC, REG_TMP0.w0
.if $defined("HDSL_MULTICHANNEL")
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00
PUSH_FIFO_CONST 0x00
.endif
CALL1 calc_fastpos
transport_on_h_frame_exit:
;calculate rel. pos and store