8d4349c792
- Fix sign extension in estimator for relative position and acceleration addition - Fix sign estimation for relative position calculation - Remove an unnecessary RET instruction - Fix register corruption for ALIGN_PH - Fix register usage for DTE error signaling Fixes: PINDSW-5689 Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
513 lines
18 KiB
PHP
513 lines
18 KiB
PHP
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; Copyright (C) 2021-2023 Texas Instruments Incorporated
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the
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; distribution.
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;
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; Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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;--------------------------------------------------------------------------------------------------
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;Offsets
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;--------------------------------------------------------------------------------------------------
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;ICSS_CFG .set C4
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;SYSCFG .set 0x04
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;GPCFG0 .set 0x08
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;GPCFG1 .set 0x0c
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;PMAO .set 0x28
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P0EDRXCFG .set 0xe0
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P0EDTXCFG .set 0xe4
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P0EDCH0CFG0 .set 0xe8
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P0EDCH0CFG1 .set 0xec
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P0EDCH1CFG0 .set 0xf0
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P0EDCH1CFG1 .set 0xf4
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P0EDCH2CFG0 .set 0xf8
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P0EDCH2CFG1 .set 0xfc
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P1EDRXCFG .set 0x100
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P1EDTXCFG .set 0x104
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P1EDCH0CFG0 .set 0x108
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P1EDCH0CFG1 .set 0x10C
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P1EDCH1CFG0 .set 0x110
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P1EDCH1CFG1 .set 0x114
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P1EDCH2CFG0 .set 0x118
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P1EDCH2CFG1 .set 0x11C
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;--------------------------------------------------------------------------------------------------
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;ICSS0 PRU0 DMEM
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;--------------------------------------------------------------------------------------------------
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.if $defined(PRU1)
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ICSS_CFGx .set C5
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EDTXCFG .set (P1EDTXCFG-0x100)
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EDRXCFG .set (P1EDRXCFG-0x100)
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EDCH0CFG0 .set (P1EDCH0CFG0-0x100)
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EDCH0CFG1 .set (P1EDCH0CFG1-0x100)
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EDCH1CFG0 .set (P1EDCH1CFG0-0x100)
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EDCH1CFG1 .set (P1EDCH1CFG1-0x100)
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EDCH2CFG0 .set (P1EDCH2CFG0-0x100)
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EDCH2CFG1 .set (P1EDCH2CFG1-0x100)
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.else
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ICSS_CFGx .set C4
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EDTXCFG .set P0EDTXCFG
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EDRXCFG .set P0EDRXCFG
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EDCH0CFG0 .set P0EDCH0CFG0
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EDCH0CFG1 .set P0EDCH0CFG1
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EDCH1CFG0 .set P0EDCH1CFG0
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EDCH1CFG1 .set P0EDCH1CFG1
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EDCH2CFG0 .set P0EDCH2CFG0
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EDCH2CFG1 .set P0EDCH2CFG1
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.endif
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; Each HDSL channel will use a portion of DMEM for HDSL shared/local data storage for that channel.
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; CHANNEL_0: 0x0000 - 0x06FF
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; CHANNEL_1: 0x0700 - 0x0DFF
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; CHANNEL_2: 0x0E00 - 0x0~FF
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.if $defined(CHANNEL_2) ; TX_PRU
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PDMEM00 .set 0x0E00
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.endif
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.if $defined(CHANNEL_1) ; PRU
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PDMEM00 .set 0x0700
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.endif
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.if $defined(CHANNEL_0) ; RTU_PRU
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PDMEM00 .set 0x0000
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.endif
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PDMEM00_CONST .set C24
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MASTER_REGS_CONST .set C24
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IEP1_BASE_CONST .set C1
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;Hiperface DSL Master Registers
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MASTER_REGS .set 0x00
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MASTER_REGS_SIZE .set (DUMMY_END + 1)
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;LUT for 5b/6b encoding
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LUT_5b6b_ENC .set (MASTER_REGS + MASTER_REGS_SIZE)
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LUT_5b6b_ENC_SIZE .set 32
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;LUT for 5b/6b decoding
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LUT_5b6b_DEC .set (LUT_5b6b_ENC + LUT_5b6b_ENC_SIZE)
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LUT_5b6b_DEC_SIZE .set 64
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;LUT for 3b/4b encoding
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LUT_3b4b_ENC .set (LUT_5b6b_DEC + LUT_5b6b_DEC_SIZE)
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LUT_3b4b_ENC_SIZE .set 8
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;LUT for 3b/4b decoding
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LUT_3b4b_DEC .set (LUT_3b4b_ENC + LUT_3b4b_ENC_SIZE)
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LUT_3b4b_DEC_SIZE .set 16
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LUT_BITCNT .set (LUT_3b4b_DEC + LUT_3b4b_DEC_SIZE)
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LUT_BITCNT_SIZE .set 256
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LUT_CRC16 .set (LUT_BITCNT + LUT_BITCNT_SIZE)
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LUT_CRC16_SIZE .set (256*2)
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LUT_CRC5 .set (LUT_CRC16 + LUT_CRC16_SIZE)
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LUT_CRC5_SIZE .set (1*256)
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ABS_ERR_PTR .set (LUT_CRC5 + LUT_CRC5_SIZE)
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ABS_ERR_PTR_SIZE .set 2
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ABS_ERR_BUF .set (ABS_ERR_PTR + ABS_ERR_PTR_SIZE)
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ABS_ERR_BUF_SIZE .set (NUM_FRAMES_AVG*4)
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LUT_B2B .set (ABS_ERR_BUF + 2 + ABS_ERR_BUF_SIZE) ;+2 is for 4-byte address alignment
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LUT_B2B_SIZE .set (4*16)
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LUT_RSSI .set (LUT_B2B + LUT_B2B_SIZE)
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LUT_RSSI_SIZE .set (256)
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LUT_EE .set (0x5e4 + LUT_RSSI_SIZE);(LUT_RSSI + LUT_RSSI_SIZE)
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LUT_EE_SIZE .set 9
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;--------------------------------------------------------------------------------------------------
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;Register Usage
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;--------------------------------------------------------------------------------------------------
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;channel structure
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channel_s .struct
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ch_vertl .int
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ch_verth .int
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ch_secl .int
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ch_sech .int
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ch_paral .int
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ch_parah .int
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.endstruct
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CHANNEL .sassign r18, channel_s
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.asg r18.w0, crc_vert
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.asg r18, VERT_L
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.asg r19, VERT_H
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; R18, R19, R20, R21, R22 and R23 are used for channel_s
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h_frame_s .struct
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vert .byte
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s_par .byte
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pipe .byte
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secondary .byte
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acc .short
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flags .short
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.endstruct
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H_FRAME .sassign r3, h_frame_s
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.asg r4.b0, H_FRAME_acc0
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.asg r4.b1, H_FRAME_acc1
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.asg r4.b2, H_FRAME_flags_l
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.asg r4.b3, H_FRAME_flags_h
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short_msg_s .struct
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crc .short
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data .byte
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addr .byte
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bits_left .byte
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timeout .byte
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.endstruct
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SHORT_MSG .sassign r26, short_msg_s
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.asg r26, SHORT_MSG32
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.asg r26.b0, SHORT_MSG_CRC_L
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.asg r26.b1, SHORT_MSG_CRC_H
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long_msg_recv_s .struct
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crc .short
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bits_left .byte
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ptr .byte
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.endstruct
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LONG_MSG_RECV .sassign r28, long_msg_recv_s
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.asg r28.b1, LONG_MSG_RECV_CRC_H
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.asg r28.b0, LONG_MSG_RECV_CRC_L
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.asg r6.b3, QM
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.asg r6.b2, SLAVE_DELAY
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.asg r6.b1, LAST_BIT_SENT
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.asg r6.b0, SAMPLE_EDGE
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.asg r5, LOOP_CNT
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.asg r0, REG_TMP0
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.asg r1, REG_TMP1
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.asg r2, REG_TMP2
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.asg r20, REG_SCRATCH
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.asg r11, REG_TMP11
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.asg r16.b0, RSSI
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.asg r16.b1, CUR_EDGES
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.asg r16.b2, SPECIAL_CHARACTER
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.asg r16.b3, BYTE_ERROR
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.asg r15, FAST_POSH
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.asg r14.b3, FAST_POSL
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.asg r14, SPEED ; NOTE: r14.b3 is used as FAST_POSL
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.asg r17.b0, DISPARITY
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.asg r17.b1, SEND_PARA
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.asg r29.w0, RET_ADDR0
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.asg r17.w2, RET_ADDR1
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.asg r29.b2, NUM_ACC_BITS
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.asg r29.b3, NUM_ST_BITS
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.asg r13, REG_FNC
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.asg r7.w0, DELTA_ACC0
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.asg r7.w2, DELTA_ACC1
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.asg r8.w0, DELTA_ACC2
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.asg r8.w2, DELTA_ACC3
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.asg r9.w0, DELTA_ACC4
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.asg r9.w2, LAST_ACC
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;.asg r10, EXTRA_POS
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;.asg r10.w0, TIME_COMP
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;.asg r10.w2, LAST_TIME_COMP
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.asg r10.w0, SYNC_DIFF0
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.asg r10.w2, LOOP_CNT_0
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.asg r12.b0, EXTRA_SIZE
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.asg r12.b1, NUM_STUFFING
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.asg r12.b2, EXTRA_EDGE
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.asg r12.b3, TIME_REST
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.asg r27.b2, NUM_PULSES
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.asg r25.b2, TIME_EXTRA_WINDOW ;free for am65xx use case
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.asg r25.b3,FIFO_L ;load fifo
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.asg r25.b2, MODIFIED_HEADER_STARTED
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.asg r27.b3, LEARN_STATE_STARTED
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.asg r25.b0, ALIGN_PH
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.asg r24, CRC
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.asg r24.w0, CRC_VERT
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.asg r24.b1, CRC_VERT_H
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.asg r24.b0, CRC_VERT_L
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.asg r24.w2, CRC_SEC
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.asg r24.b3, CRC_SEC_H
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.asg r24.b2, CRC_SEC_L
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.asg r2.b0, EXTRA_SIZE_SELF ;take care! these are not persistent registers, r2 is actually temp reigister. these names are
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.asg r2.b1, EXTRA_EDGE_SELF ;given to temp register for ease of reading. they are used as temp.
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.asg r10.b0, EXTRA_EDGE_COMP
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.asg r10.b1, EXTRA_SIZE_COMP
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.asg r10.b2, TIME_REST_COMP
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.asg r10.b3, NUM_STUFFING_COMP
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;--------------------------------------------------------------------------------------------------
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;DSL Master Register offsets
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SYS_CTRL .set 0x00
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SYNC_CTRL .set 0x01
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MASTER_QM .set 0x03
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EVENT_H .set 0x04
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EVENT_L .set 0x05
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MASK_H .set 0x06
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MASK_L .set 0x07
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MASK_SUM .set 0x08
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EDGES .set 0x09
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DELAY .set 0x0A
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VERSION .set 0x0B
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ENC_ID2 .set 0x0D
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ENC_ID1 .set 0x0E
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ENC_ID0 .set 0x0F
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POS4 .set 0x10
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POS3 .set 0x11
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POS2 .set 0x12
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POS1 .set 0x13
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POS0 .set 0x14
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VEL2 .set 0x15
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VEL1 .set 0x16
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VEL0 .set 0x17
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;SUMMARY/MIR_SUM is not supported
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;SUMMARY .set 0x18
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VPOS4 .set 0x19
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VPOS3 .set 0x1A
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VPOS2 .set 0x1B
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VPOS1 .set 0x1C
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VPOS0 .set 0x1D
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VPOSCRC_H .set 0x1E
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VPOSCRC_L .set 0x1F
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PC_BUFFER0 .set 0x20
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PC_BUFFER1 .set 0x21
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PC_BUFFER2 .set 0x22
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PC_BUFFER3 .set 0x23
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PC_BUFFER4 .set 0x24
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PC_BUFFER5 .set 0x25
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PC_BUFFER6 .set 0x26
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PC_BUFFER7 .set 0x27
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PC_ADD_H .set 0x28
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PC_ADD_L .set 0x29
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PC_OFF_H .set 0x2A
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PC_OFF_L .set 0x2B
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PC_CTRL .set 0x2C
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PIPE_S .set 0x2D
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PIPE_D .set 0x2E
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PC_DATA .set 0x2F
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SAFE_CTRL .set 0x35
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SAFE_SUM .set 0x36
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S_PC_DATA .set 0x37
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ACC_ERR_CNT .set 0x38
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MAXACC .set 0x39
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MAXDEV_H .set 0x3A
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MAXDEV_L .set 0x3B
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EVENT_S .set 0x3D
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MASK_S .set 0x3E
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DUMMY .set 0x3F
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;extra Master Registers as workaround for different access method depended behaviour (r/w)
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SLAVE_REG_CTRL .set 0x40
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ACC_ERR_CNT_TRESH .set 0x41
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MAXDEV_TRESH_H .set 0x42
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MAXDEV_TRESH_L .set 0x43
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;extra MASTER registers (not in the specification! little endian!)
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NUM_VERT_ERR0 .set 0x90
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NUM_VERT_ERR1 .set 0x91
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NUM_VERT_ERR2 .set 0x92
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NUM_VERT_ERR3 .set 0x93
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NUM_VERT_FRAMES0 .set 0x94
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NUM_VERT_FRAMES1 .set 0x95
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NUM_VERT_FRAMES2 .set 0x96
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NUM_VERT_FRAMES3 .set 0x97
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REL_POS0 .set 0x98
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REL_POS1 .set 0x99
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REL_POS2 .set 0x9a
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REL_POS3 .set 0x9b
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MISMATCH0 .set 0x9c
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MISMATCH1 .set 0x9d
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MISMATCH2 .set 0x9e
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MISMATCH3 .set 0x9f
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NUM_H_ERR0 .set 0xa0
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NUM_H_ERR1 .set 0xa1
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NUM_H_ERR2 .set 0xa2
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NUM_H_ERR3 .set 0xa3
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LAST_FAST_POS0 .set 0xa4
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LAST_FAST_POS1 .set 0xa5
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LAST_FAST_POS2 .set 0xa6
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LAST_FAST_POS3 .set 0xa7
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LAST_FAST_POS4 .set 0xa8
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NUM_RESETS .set 0xa9
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EVENT_UPDATE_PENDING .set 0xaa
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;EVENT_UPDATE_PENDING Bit Defines
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EVENT_UPDATE_PENDING_QMLW .set (0)
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EVENT_UPDATE_PENDING_POS .set (1)
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EVENT_UPDATE_PENDING_BIT_2 .set (2)
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EVENT_UPDATE_PENDING_BIT_3 .set (3)
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EVENT_UPDATE_PENDING_BIT_4 .set (4)
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EVENT_UPDATE_PENDING_BIT_5 .set (5)
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EVENT_UPDATE_PENDING_BIT_6 .set (6)
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EVENT_UPDATE_PENDING_BIT_7 .set (7)
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TEST_PATTERN0 .set 0xac
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TEST_PATTERN1 .set 0xad
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TEST_PATTERN2 .set 0xae
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TEST_PATTERN3 .set 0xaf
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TEST_PATTERN4 .set 0xb0
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TEST_PATTERN5 .set 0xb1
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TEST_PATTERN6 .set 0xb2
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TEST_PATTERN7 .set 0xb3
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TEST_PAT_MASK0 .set 0xb4
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TEST_PAT_MASK1 .set 0xb5
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TEST_PAT_MASK2 .set 0xb6
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TEST_PAT_MASK3 .set 0xb7
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SYNC_DIFF .set 0xb8
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SYNC_PULSE_PERIOD .set 0xbc
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LONG_MSG_BUFFER .set 0xc4
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SYNC_PULSE_ERROR .set 0xc0
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ECAP_OFFSETS .set 0xce
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EXTRA_EDGE_TIMESTAMP .set 0xd8;4bytes
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SYNC_PARAM1 .set 0xdc;4bytes
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SYNC_EXTRA_REMAINDER .set 0xe0;1bytes
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SYNC_STUFFING_REMAINDER .set 0xe1;1bytes
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WAIT_BEFORE_START .set 0xe2;2bytes ;free
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MASK_POS .set 0xe4;4bytes
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SYNC_JITTER .set 0xe8;2bytes
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SYNC_DIFF_HIST_CNT .set 0xea;2bytes
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SYNC_DIFF_HIST .set 0xec;2*8bytes
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DUMMY_END .set 0xff
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ADDR .set 0x15ff
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;--------------------------------------------------------------------------------------------------
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;Memory offsets
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;--------------------------------------------------------------------------------------------------
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PRU_CTRL_CONST .set C28
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;PRU_CTRL .set 0x00022000
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PRU_CYCLCNT .set 0x0c
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PWMSS1_CONST .set C19 ;AM437x specific for sync pule synchronization
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PWMSS1_ECAP .set 0x48302100 ;AM437x specific for sync pule synchronization
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PWMSS2_CONST .set C20 ;AM437x specific for sync pule synchronization
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ECAP .set 0x100 ;AM437x specific for sync pule synchronization
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ECAP_ECCLR .set 0x30 ;AM437x specific for sync pule synchronization
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ECAP_ECEINT .set 0x2c ;AM437x specific for sync pule synchronization
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ECAP_CAP1 .set 0x08 ;AM437x specific for sync pule synchronization
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ECAP_ECCTL1 .set 0x28 ;AM437x specific for sync pule synchronization
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INTC_SICR .set 0x24 ;AM437x specific for sync pule synchronization
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INTC_SECR1 .set 0x284 ;AM437x specific for sync pule synchronization
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INTC_SECR0 .set 0x280 ;AM437x specific for sync pule synchronization
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INTC_CONST .set C0 ;AM437x specific for sync pule synchronization
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IEP_CONST .set C26
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IEP1_CONST .set 0x2F000
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IEP_CNT .set 0x14 ;todo TSmod check as 64bit now (old0x0c)
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IEP_CAPR6_RISE .set 0x50
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SHARED_MEM_CONST .set 0x0b010000;0x54442000+0x10000
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;--------------------------------------------------------------------------------------------------
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;Memory offsets for dynamic loading of PRU code
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;--------------------------------------------------------------------------------------------------
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CODE_BASE .set (0x40300000);(0x54400000+0x00040000+0x2100)
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CODE_SIZE .set 0x600
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DYNAMIC_CODE_OFFSET .set 0x1000 ;0x2100
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;--------------------------------------------------------------------------------------------------
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;R31 flags for RX
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;--------------------------------------------------------------------------------------------------
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.if $defined(CHANNEL_2)
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RX_OVERFLOW_FLAG .set 29
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RX_VALID_FLAG .set 26
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.endif
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.if $defined(CHANNEL_1)
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RX_OVERFLOW_FLAG .set 28
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RX_VALID_FLAG .set 25
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.endif
|
|
|
|
.if $defined(CHANNEL_0)
|
|
RX_OVERFLOW_FLAG .set 27
|
|
RX_VALID_FLAG .set 24
|
|
.endif
|
|
|
|
;--------------------------------------------------------------------------------------------------
|
|
;R30 flags for RX
|
|
;--------------------------------------------------------------------------------------------------
|
|
.if $defined(CHANNEL_2)
|
|
RX_ENABLE .set 26
|
|
.endif
|
|
|
|
.if $defined(CHANNEL_1)
|
|
RX_ENABLE .set 25
|
|
.endif
|
|
|
|
.if $defined(CHANNEL_0)
|
|
RX_ENABLE .set 24
|
|
.endif
|
|
|
|
;--------------------------------------------------------------------------------------------------
|
|
;R31 flags for TX
|
|
;--------------------------------------------------------------------------------------------------
|
|
|
|
;global flags
|
|
TX_GLOBAL_TX_GO .set 20
|
|
TX_GLOBAL_REINIT .set 19
|
|
TX_CHANNEL_GO .set 18
|
|
|
|
.if $defined(CHANNEL_2)
|
|
TX_GLOBAL_REINIT_ACTIVE .set 21
|
|
TX_UNDERRUN .set 17
|
|
TX_OVERRUN .set 16
|
|
.endif
|
|
|
|
.if $defined(CHANNEL_1)
|
|
TX_GLOBAL_REINIT_ACTIVE .set 13
|
|
TX_UNDERRUN .set 9
|
|
TX_OVERRUN .set 8
|
|
.endif
|
|
|
|
.if $defined(CHANNEL_0)
|
|
TX_GLOBAL_REINIT_ACTIVE .set 5
|
|
TX_UNDERRUN .set 1
|
|
TX_OVERRUN .set 0
|
|
.endif
|
|
|
|
;--------------------------------------------------------------------------------------------------
|
|
;R30 flags for TX
|
|
;--------------------------------------------------------------------------------------------------
|
|
|
|
.if $defined(CHANNEL_2)
|
|
CHANNEL_NUM .set 1
|
|
.endif
|
|
|
|
.if $defined(CHANNEL_1)
|
|
CHANNEL_NUM .set 0
|
|
.endif
|
|
|
|
VERSION2 .set 0x44
|
|
ENC2_ID .set 0x45
|
|
STATUS2 .set 0x46
|
|
VPOS24 .set 0x47
|
|
VPOS23 .set 0x48
|
|
VPOS22 .set 0x49
|
|
VPOS21 .set 0x4A
|
|
VPOS20 .set 0x4B
|
|
VPOSCRC2_H .set 0x4C
|
|
VPOSCRC2_L .set 0x4D
|
|
POSTX .set 0x4E
|
|
|
|
ONLINE_STATUS_D_H .set 0x50
|
|
ONLINE_STATUS_D_L .set 0x51
|
|
ONLINE_STATUS_1_H .set 0x52
|
|
ONLINE_STATUS_1_L .set 0x53
|
|
ONLINE_STATUS_2_H .set 0x54
|
|
ONLINE_STATUS_2_L .set 0x55
|
|
|
|
H_FRAME_FLAGS_TEMP .set 0x56 ; 2 bytes
|
|
CRC_SEC_TEMP .set 0x58 ; 2 bytes
|
|
VPOS_VALID .set 0x5A ; 1 byte
|
|
VPOS_TEMP .set 0x5B ; 5 bytes
|
|
VPOSCRC_TEMP .set 0x60 ; 2 bytes
|
|
STATUS2_TEMP .set 0x62 ; 1 byte
|
|
VPOS2_TEMP .set 0x63 ; 5 bytes
|
|
VPOSCRC2_TEMP .set 0x68 ; 2 bytes
|
|
SAFE_SUM_TEMP .set 0x70 ; 1 byte
|