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Pull request #9: Bug-fixes for HDSL

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Merge in PINDSW/motor_control_sdk from PINDSW-5486_hdsl_bug_fixes to next

* commit '47b87f5cf7dd98e755c9ae554a89339f6559bac3':
  am64x/am243x: hdsl: Remove SUC instruction usage
  am64x/am243x: hdsl: Fix ONLINE_STATUS_1 register corruption
  am64x/am243x: hdsl: Fix QMLW bits in ONLINE STATUS registers
  am64x/am243x: hdsl: Make FREL/FRES bit set sticky in EVENT/EVENT_S
  am64x/am243x: hdsl: Fix reset behaviour after triggering manual reset
  am64x/am243x: hdsl: Add versioning in firmware
  am64x/am243x: hdsl: Fix the SUM/SSUM/FIX1 bit configuration in ONLINE STATUS registers
  am64x/am243x: hdsl: Fix the fast position and velocity calculation
  am64x/am243x: hdsl: Fix the two most significant bytes of fast position
  am64x/am243x: hdsl: Update the register memory map
  am64x/am243x: hdsl: Remove the scanf waiting for Enter during initialization
This commit is contained in:
Dhaval Khandla 2023-08-25 03:23:10 -05:00 committed by Pratheesh Gangadhar TK
commit 5a8f9f83ea
15 changed files with 393 additions and 352 deletions
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2
examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c
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@ -523,8 +523,6 @@ void hdsl_init(void)
hdsl_pruss_init(); hdsl_pruss_init();
HDSL_iep_init(gHdslHandleCh0); HDSL_iep_init(gHdslHandleCh0);
DebugP_log("\r\nPress Enter to start application\n");
DebugP_scanf("%d",&ES);
ClockP_usleep(5000); ClockP_usleep(5000);
if(CONFIG_HDSL0_MODE==0) if(CONFIG_HDSL0_MODE==0)
{ {

2
examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c
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@ -452,8 +452,6 @@ void hdsl_init(void)
HwiP_construct(&gPRUHwiObject, &hwiPrms); HwiP_construct(&gPRUHwiObject, &hwiPrms);
HDSL_iep_init(gHdslHandleCh0); HDSL_iep_init(gHdslHandleCh0);
DebugP_log("\r\nPress Enter to start application\n");
DebugP_scanf("%d",&ES);
ClockP_usleep(5000); ClockP_usleep(5000);
if(CONFIG_HDSL0_MODE==0) if(CONFIG_HDSL0_MODE==0)

21
source/position_sense/hdsl/driver/hdsl_drv.c
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@ -213,28 +213,28 @@ uint8_t HDSL_get_safe_events(HDSL_Handle hdslHandle)
uint16_t HDSL_get_online_status_d(HDSL_Handle hdslHandle) uint16_t HDSL_get_online_status_d(HDSL_Handle hdslHandle)
{ {
uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_D; uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_D_L | (hdslHandle->hdslInterface->ONLINE_STATUS_D_H << 8);
return ureg; return ureg;
} }
uint16_t HDSL_get_online_status_1(HDSL_Handle hdslHandle) uint16_t HDSL_get_online_status_1(HDSL_Handle hdslHandle)
{ {
uint16_t ureg =hdslHandle->hdslInterface->ONLINE_STATUS_1; uint16_t ureg =hdslHandle->hdslInterface->ONLINE_STATUS_1_L | (hdslHandle->hdslInterface->ONLINE_STATUS_1_H << 8);
return ureg; return ureg;
} }
uint16_t HDSL_get_online_status_2(HDSL_Handle hdslHandle) uint16_t HDSL_get_online_status_2(HDSL_Handle hdslHandle)
{ {
uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_2; uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_2_L | (hdslHandle->hdslInterface->ONLINE_STATUS_2_H << 8);
return ureg; return ureg;
} }
uint8_t HDSL_get_sum(HDSL_Handle hdslHandle) uint8_t HDSL_get_sum(HDSL_Handle hdslHandle)
{ {
uint8_t ureg = hdslHandle->hdslInterface->SAFE_SUM; uint8_t ureg = hdslHandle->hdslInterface->SAFE_SUM;
return ureg; return ureg;
} }
uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle) uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle)
{ {
return (uint8_t) (hdslHandle->hdslInterface->ACC_ERR_CNT & 0x1F); return (uint8_t) (hdslHandle->hdslInterface->ACC_ERR_CNT & 0x1F);
@ -251,7 +251,7 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat
uint64_t end; uint64_t end;
end = ClockP_getTimeUsec() + timeout; end = ClockP_getTimeUsec() + timeout;
while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1)
{ {
if(ClockP_getTimeUsec() > end) if(ClockP_getTimeUsec() > end)
{ {
@ -260,14 +260,14 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat
} }
hdslHandle->hdslInterface->S_PC_DATA = data; hdslHandle->hdslInterface->S_PC_DATA = data;
hdslHandle->hdslInterface->SLAVE_REG_CTRL = addr; hdslHandle->hdslInterface->SLAVE_REG_CTRL = addr;
while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 0) while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 0)
{ {
if(ClockP_getTimeUsec() > end) if(ClockP_getTimeUsec() > end)
{ {
return SystemP_TIMEOUT; return SystemP_TIMEOUT;
} }
} }
while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1)
{ {
if(ClockP_getTimeUsec() > end) if(ClockP_getTimeUsec() > end)
{ {
@ -279,11 +279,10 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat
int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *data, uint64_t timeout) int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *data, uint64_t timeout)
{ {
uint64_t end; uint64_t end;
end = ClockP_getTimeUsec() + timeout; end = ClockP_getTimeUsec() + timeout;
while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1)
{ {
if(ClockP_getTimeUsec() > end) if(ClockP_getTimeUsec() > end)
{ {
@ -292,14 +291,14 @@ int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *dat
} }
hdslHandle->hdslInterface->S_PC_DATA = 0; hdslHandle->hdslInterface->S_PC_DATA = 0;
hdslHandle->hdslInterface->SLAVE_REG_CTRL = (addr | (1<<7)); hdslHandle->hdslInterface->SLAVE_REG_CTRL = (addr | (1<<7));
while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 0) while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 0)
{ {
if(ClockP_getTimeUsec() > end) if(ClockP_getTimeUsec() > end)
{ {
return SystemP_TIMEOUT; return SystemP_TIMEOUT;
} }
} }
while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1)
{ {
if(ClockP_getTimeUsec() > end) if(ClockP_getTimeUsec() > end)
{ {

1
source/position_sense/hdsl/driver/hdsl_lut.c
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@ -1283,7 +1283,6 @@ static void hdsl_configure_register_if(HDSL_Handle hdslHandle)
hdslHandle->hdslInterface->MAXDEV_L = 0x0; hdslHandle->hdslInterface->MAXDEV_L = 0x0;
hdslHandle->hdslInterface->MAXDEV_H_THRES = 0xFF; hdslHandle->hdslInterface->MAXDEV_H_THRES = 0xFF;
hdslHandle->hdslInterface->MAXDEV_L_THRES = 0xFF; hdslHandle->hdslInterface->MAXDEV_L_THRES = 0xFF;
hdslHandle->hdslInterface->VERSION = 0x41;
hdslHandle->hdslInterface->ACC_ERR_CNT_THRES = 0x1F; hdslHandle->hdslInterface->ACC_ERR_CNT_THRES = 0x1F;
HW_WR_REG32(((uint32_t)(hdslHandle->baseMemAddr) + 0xac), 0x4cc8115d); HW_WR_REG32(((uint32_t)(hdslHandle->baseMemAddr) + 0xac), 0x4cc8115d);

27
source/position_sense/hdsl/firmware/datalink.asm
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@ -159,9 +159,9 @@ datalink_wait_vsynch:
ldi r31.w0, PRU0_ARM_IRQ4 ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int0: update_events_no_int0:
; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1
; Set EVENT_FREL in EVENT_L register ; Set EVENT_FREL in EVENT_L register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4 lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
set REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL set REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL
@ -172,9 +172,9 @@ update_events_no_int0:
ldi r31.w0, PRU0_ARM_IRQ ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int1: update_events_no_int1:
; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
;-------------------------------------------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------
;State RX0-RX7 ;State RX0-RX7
ldi LOOP_CNT.w2, 8 ldi LOOP_CNT.w2, 8
@ -1074,11 +1074,11 @@ send_header_encode_sec_subblock_end:
lsr REG_TMP0.b0, REG_FNC.b2, 2 lsr REG_TMP0.b0, REG_FNC.b2, 2
or REG_FNC.b3, REG_FNC.b3, REG_TMP0.b0 or REG_FNC.b3, REG_FNC.b3, REG_TMP0.b0
lsl REG_FNC.b2, REG_FNC.b2, 6 lsl REG_FNC.b2, REG_FNC.b2, 6
qbbc transport_layer_send_msg_done1, H_FRAME.flags, FLAG_NORMAL_FLOW
.if $defined("HDSL_MULTICHANNEL") .if $defined("HDSL_MULTICHANNEL")
PUSH_FIFO_1_8x PUSH_FIFO_1_8x
PUSH_FIFO_2_8x PUSH_FIFO_2_8x
.endif .endif
; transport_layer_send_msg sends short/long message (if pending) and also checks for QMLW/POS errors
jmp transport_layer_send_msg jmp transport_layer_send_msg
transport_layer_send_msg_done1: transport_layer_send_msg_done1:
.if $defined("HDSL_MULTICHANNEL") .if $defined("HDSL_MULTICHANNEL")
@ -1402,7 +1402,6 @@ calculation_for_wait_done:
mov REG_TMP11, RET_ADDR1 mov REG_TMP11, RET_ADDR1
qbeq send_stuffing_no_stuffing, NUM_STUFFING, 0 qbeq send_stuffing_no_stuffing, NUM_STUFFING, 0
;check if we have stuffing ;check if we have stuffing
;halt
READ_CYCLCNT REG_TMP0 READ_CYCLCNT REG_TMP0
rsb REG_TMP2, REG_TMP0, (5*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4) rsb REG_TMP2, REG_TMP0, (5*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4)
mov REG_FNC.b3, NUM_STUFFING mov REG_FNC.b3, NUM_STUFFING
@ -1560,11 +1559,11 @@ update_events_no_int2:
update_events_no_int18: update_events_no_int18:
; Set PRST bits in ONLINE_STATUS registers ; Set PRST bits in ONLINE_STATUS registers
lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST
set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST
set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
jmp datalink_reset jmp datalink_reset
;-------------------------------------------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------
;Function: switch_clk (RET_ADDR1) ;Function: switch_clk (RET_ADDR1)
@ -1593,17 +1592,13 @@ switch_clk:
;input: ;input:
; REG_FNC.b0: value ; REG_FNC.b0: value
;modifies: ;modifies:
; REG_TMP0, REG_FNC ; REG_TMP1, REG_FNC
;-------------------------------------------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------
qm_add: qm_add:
.if 1 .if 1
and QM, QM, 0x7f and QM, QM, 0x7f
;check if negative (bit 7 indicates there is a link -> check bit 6) ;check if negative (bit 7 indicates there is a link -> check bit 6)
qbbc qm_add_no_reset, QM, 6 qbbc qm_add_no_reset, QM, 6
; set EDIO28
;ldi32 REG_TMP1, 0x02e300
;sbbo &REG_TMP1.b0, REG_TMP1, 0x13, 1
halt
ldi QM, 0 ldi QM, 0
;update MASTER_QM ;update MASTER_QM
sbco &QM, MASTER_REGS_CONST, MASTER_QM, 1 sbco &QM, MASTER_REGS_CONST, MASTER_QM, 1
@ -1617,9 +1612,9 @@ qm_add_no_capping:
qble qm_add_below_not_14, QM, 14 qble qm_add_below_not_14, QM, 14
; Defer the events register update to later ; Defer the events register update to later
; Set EVENT_UPDATE_PENDING_QMLW to indicate a low QM value ; Set EVENT_UPDATE_PENDING_QMLW to indicate a low QM value
lbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 lbco &REG_TMP1.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1
set REG_TMP0.b0, REG_TMP0.w0, EVENT_UPDATE_PENDING_QMLW set REG_TMP1.b0, REG_TMP1.b0, EVENT_UPDATE_PENDING_QMLW
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 sbco &REG_TMP1.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1
qm_add_below_not_14: qm_add_below_not_14:
or QM, QM, (1<<7) or QM, QM, (1<<7)
;update MASTER_QM ;update MASTER_QM

46
source/position_sense/hdsl/firmware/datalink_init.asm
View File

@ -54,10 +54,10 @@
relocatable0: relocatable0:
datalink_init_start: datalink_init_start:
datalink_reset:
;State RESET ;State RESET
zero &r0, 124 zero &r0, 124
;send 2 times ;send 2 times
datalink_reset:
;setup ICSS encoder peripheral for Hiperface DSL ;setup ICSS encoder peripheral for Hiperface DSL
ldi DISPARITY, 0x00 ldi DISPARITY, 0x00
@ -70,6 +70,12 @@ datalink_reset:
.else .else
TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0
.endif .endif
; set the VERSION and VERSION2 register
ldi REG_TMP0.b0, ICSS_FIRMWARE_RELEASE
sbco &REG_TMP0.b0, MASTER_REGS_CONST, VERSION, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, VERSION2, 1
zero &H_FRAME, (4*2) zero &H_FRAME, (4*2)
;init transport layer here ;init transport layer here
CALL transport_init CALL transport_init
@ -85,31 +91,31 @@ datalink_reset:
;reset SAFE_CTRL register ;reset SAFE_CTRL register
zero &REG_TMP0.b0, 1 zero &REG_TMP0.b0, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, SAFE_CTRL, 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, SAFE_CTRL, 1
; Write the fixed bits and reset PRST bits in ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2 ; Initialize ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2
; In ONLINE_STATUS_D high, bit 2 is FIX0, bit 4 is FIX1 and bit 5 is FIX0 ; In ONLINE_STATUS_D high, bit 2 is FIX0, bit 4 is FIX1 and bit 5 is FIX0
; In ONLINE_STATUS_D low, bit 0 is FIX0 and bit 3 is FIX0 ; In ONLINE_STATUS_D low, bit 0 is FIX0 and bit 3 is FIX0
lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_D, 2 lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 2
; clearing bits with fix0 and PRST bit ; clearing bits
and REG_TMP0.w0, REG_TMP0.w0, ((~((1<<ONLINE_STATUS_D_PRST) | (1<<ONLINE_STATUS_D_HIGH_BIT5_FIX0) | (1<<ONLINE_STATUS_D_HIGH_BIT2_FIX0) | (1<<ONLINE_STATUS_D_LOW_BIT3_FIX0) | (1<<ONLINE_STATUS_D_LOW_BIT0_FIX0))) & 0xFF) ldi REG_TMP0.w0, 0
; setting bits with fix1 ; setting bits with fix1
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_D_HIGH_BIT4_FIX1) or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_D_HIGH_BIT4_FIX1)
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 2 sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 2
; In ONLINE_STATUS_1 high, bit 1 is FIX0, bit 3 is FIX0 and bit 4 is FIX1 ; In ONLINE_STATUS_1 high, bit 1 is FIX0, bit 3 is FIX0 and bit 4 is FIX1
; In ONLINE_STATUS_1 low, bit 1 is FIX0, bit 3 is FIX0 and bit 4 is FIX0 ; In ONLINE_STATUS_1 low, bit 1 is FIX0, bit 3 is FIX0 and bit 4 is FIX0
lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_1, 2 lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 2
; clearing bits with fix0 and PRST bit ; clearing bits
and REG_TMP0.w0, REG_TMP0.w0, ((~((1<<ONLINE_STATUS_1_PRST) | (1<<ONLINE_STATUS_1_HIGH_BIT1_FIX0) | (1<<ONLINE_STATUS_1_HIGH_BIT3_FIX0) | (1<<ONLINE_STATUS_1_LOW_BIT4_FIX0) | (1<<ONLINE_STATUS_1_LOW_BIT3_FIX0) | (1<<ONLINE_STATUS_1_LOW_BIT1_FIX0))) & 0xFF) ldi REG_TMP0.w0, 0
; setting bits with fix1 ; setting bits with fix1
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_1_HIGH_BIT4_FIX1) or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_1_HIGH_BIT4_FIX1)
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_1, 2 sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 2
; In ONLINE_STATUS_2 high, bit 1 is FIX0, bit 3 is FIX0, bit 4 is FIX1 and bit7 is FIX1 ; In ONLINE_STATUS_2 high, bit 1 is FIX0, bit 3 is FIX0, bit 4 is FIX1 and bit7 is FIX1
; In ONLINE_STATUS_2 low, bits 0, 1, 3, 4, 5 are FIX0 ; In ONLINE_STATUS_2 low, bits 0, 1, 3, 4, 5 are FIX0
lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_2, 2 lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 2
; clearing bits with fix0 and PRST bit ; clearing bits
and REG_TMP0.w0, REG_TMP0.w0, ((~((1<<ONLINE_STATUS_2_PRST) | (1<<ONLINE_STATUS_2_HIGH_BIT1_FIX0) | (1<<ONLINE_STATUS_2_HIGH_BIT3_FIX0) | (1<<ONLINE_STATUS_2_HIGH_BIT7_FIX0) | (1<<ONLINE_STATUS_2_LOW_BIT0_FIX0) | (1<<ONLINE_STATUS_2_LOW_BIT1_FIX0) | (1<<ONLINE_STATUS_2_LOW_BIT3_FIX0) | (1<<ONLINE_STATUS_2_LOW_BIT4_FIX0) | (1<<ONLINE_STATUS_2_LOW_BIT5_FIX0))) & 0xFF) ldi REG_TMP0.w0, 0
; setting bits with fix1 ; setting bits with fix1
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_2_HIGH_BIT4_FIX1) or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_2_HIGH_BIT4_FIX1)
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_2, 2 sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 2
;check for SPOL and configure eCAP accordingly ;check for SPOL and configure eCAP accordingly
ldi REG_TMP1, (ECAP+ECAP_ECCTL1) ldi REG_TMP1, (ECAP+ECAP_ECCTL1)
lbco &REG_TMP2, PWMSS1_CONST, REG_TMP1, 4 lbco &REG_TMP2, PWMSS1_CONST, REG_TMP1, 4
@ -376,12 +382,12 @@ datalink_learn_recv_loop_final:
sbco &REG_TMP2, c25, 0, 4 sbco &REG_TMP2, c25, 0, 4
.endif .endif
READ_CYCLCNT r25 READ_CYCLCNT REG_TMP2
; avoid wrap around, need to skip on equal as wait does not work for 0. ; avoid wrap around, need to skip on equal as wait does not work for 0.
; qble datalink_learn_skip_wait, r25, r3 ; qble datalink_learn_skip_wait, REG_TMP2, r3
qble datalink_abort2, r25, r3 qble datalink_abort2, REG_TMP2, r3
sub REG_TMP11, r3, r25 sub REG_TMP11, r3, REG_TMP2
MOV r25.b0, REG_TMP11.b0 MOV REG_TMP2.b0, REG_TMP11.b0
; WAIT subracts -1 from parameter before compare. On 0 it wraps around!!! ; WAIT subracts -1 from parameter before compare. On 0 it wraps around!!!
WAIT REG_TMP11 WAIT REG_TMP11
datalink_learn_skip_wait: datalink_learn_skip_wait:
@ -540,7 +546,6 @@ datalink_learn_end:
qba datalink_learn2_before qba datalink_learn2_before
;-------------------------------------------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------
datalink_abort2: datalink_abort2:
halt
qbbs datalink_abort2_no_wait, r30, RX_ENABLE ;changed here from 24 to 26 qbbs datalink_abort2_no_wait, r30, RX_ENABLE ;changed here from 24 to 26
WAIT_TX_DONE WAIT_TX_DONE
.if $defined("FREERUN_300_MHZ") .if $defined("FREERUN_300_MHZ")
@ -555,7 +560,6 @@ datalink_abort2:
NOP_2 NOP_2
.endif .endif
datalink_abort3: datalink_abort3:
halt
datalink_abort2_no_wait: datalink_abort2_no_wait:
lbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
add REG_TMP0.b0, REG_TMP0.b0, 1 add REG_TMP0.b0, REG_TMP0.b0, 1

9
source/position_sense/hdsl/firmware/defines.inc
View File

@ -30,6 +30,15 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; ;
;Firmware version
FIRMWARE_VERSION_CODING .set 0x1
; bit5..4 major number
FIRMWARE_VERSION_MAJOR .set 0x0
; bit3..0 minor number
FIRMWARE_VERSION_MINOR .set 0x4
ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_CODING << 6) | (FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0))
;number of cycles for 1 bit ;number of cycles for 1 bit
.if $defined("FREERUN_300_MHZ") .if $defined("FREERUN_300_MHZ")
;number of cycles for 1 bit ;number of cycles for 1 bit

275
source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h
View File

@ -55,7 +55,7 @@
*/ */
const unsigned int Hiperface_DSL2_0[]= { const unsigned int Hiperface_DSL2_0[]= {
0x21066e00, 0x21067700,
0x24000125, 0x24000125,
0x2eff818f, 0x2eff818f,
0x24001d8d, 0x24001d8d,
@ -71,8 +71,8 @@ const unsigned int Hiperface_DSL2_0[]= {
0x0b01e0e0, 0x0b01e0e0,
0x0501e0e0, 0x0501e0e0,
0x4f00e0ff, 0x4f00e0ff,
0x230216d1, 0x230215d1,
0x2301f7d1, 0x2301f6d1,
0x05012525, 0x05012525,
0x6f0025f0, 0x6f0025f0,
0x2eff8f8e, 0x2eff8f8e,
@ -84,7 +84,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x2300ef9d, 0x2300ef9d,
0x05012525, 0x05012525,
0x5100254c, 0x5100254c,
0x2301f7d1, 0x2301f6d1,
0xd70170f8, 0xd70170f8,
0xcf0723f7, 0xcf0723f7,
0x1f02c4c4, 0x1f02c4c4,
@ -127,18 +127,18 @@ const unsigned int Hiperface_DSL2_0[]= {
0x5101450a, 0x5101450a,
0x2400040d, 0x2400040d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x79000009, 0x79000009,
0x69014508, 0x69014508,
0x2400060d, 0x2400060d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x79000004, 0x79000004,
0x2400010d, 0x2400010d,
0x000d6666, 0x000d6666,
0x230253d1, 0x230252d1,
0x1d03c4c4, 0x1d03c4c4,
0x2301f7d1, 0x2301f6d1,
0x51000c09, 0x51000c09,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
@ -151,7 +151,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0x24002f1e, 0x24002f1e,
0x23046a9d, 0x2304689d,
0x05014545, 0x05014545,
0x4f0045d2, 0x4f0045d2,
0x24000070, 0x24000070,
@ -159,7 +159,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x24000845, 0x24000845,
0x1f01c4c4, 0x1f01c4c4,
0x7f0000cd, 0x7f0000cd,
0x21023200, 0x21023100,
0x10d1d182, 0x10d1d182,
0x240000cd, 0x240000cd,
0xc918ff00, 0xc918ff00,
@ -170,7 +170,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1e05cdcd, 0x1e05cdcd,
0x0b018001, 0x0b018001,
0x14000130, 0x14000130,
0x230277d1, 0x230275d1,
0x6f0005f7, 0x6f0005f7,
0x240120eb, 0x240120eb,
0xf0cd0b0d, 0xf0cd0b0d,
@ -189,7 +189,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1e05cdcd, 0x1e05cdcd,
0x0b018001, 0x0b018001,
0x14000130, 0x14000130,
0x230277d1, 0x230275d1,
0x6f0005f7, 0x6f0005f7,
0x24000001, 0x24000001,
0x1c2d5050, 0x1c2d5050,
@ -212,7 +212,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1f00cdcd, 0x1f00cdcd,
0x0b018021, 0x0b018021,
0x14002130, 0x14002130,
0x230277d1, 0x230275d1,
0x110fcdc0, 0x110fcdc0,
0x240168eb, 0x240168eb,
0xf0c00b00, 0xf0c00b00,
@ -237,7 +237,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1e05cdcd, 0x1e05cdcd,
0x0b018001, 0x0b018001,
0x14000130, 0x14000130,
0x230277d1, 0x230275d1,
0x6f0005f7, 0x6f0005f7,
0x240120eb, 0x240120eb,
0xf0cd0b0d, 0xf0cd0b0d,
@ -256,7 +256,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1e05cdcd, 0x1e05cdcd,
0x0b018001, 0x0b018001,
0x14000130, 0x14000130,
0x230277d1, 0x230275d1,
0x6f0005f7, 0x6f0005f7,
0x24000001, 0x24000001,
0x1c2d5050, 0x1c2d5050,
@ -279,7 +279,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1f00cdcd, 0x1f00cdcd,
0x0b018021, 0x0b018021,
0x14002130, 0x14002130,
0x230277d1, 0x230275d1,
0x110fcdc0, 0x110fcdc0,
0x240168eb, 0x240168eb,
0xf0c00b00, 0xf0c00b00,
@ -296,7 +296,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x20d10000, 0x20d10000,
0x24000605, 0x24000605,
0x2eff8283, 0x2eff8283,
0x230262d1, 0x230260d1,
0x240000c0, 0x240000c0,
0x2400002d, 0x2400002d,
0x230069d1, 0x230069d1,
@ -350,32 +350,32 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1f04c4c4, 0x1f04c4c4,
0x2400060d, 0x2400060d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x79000006, 0x79000006,
0xc9005005, 0xc9005005,
0x51fd0304, 0x51fd0304,
0x2400020d, 0x2400020d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0xc9017005, 0xc9017005,
0x2400010d, 0x2400010d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x79000005, 0x79000005,
0xc9015004, 0xc9015004,
0x2400020d, 0x2400020d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0xc9027004, 0xc9027004,
0x2400010d, 0x2400010d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x111870e0, 0x111870e0,
0x5100e006, 0x5100e006,
0x1f03c4c4, 0x1f03c4c4,
0x2400020d, 0x2400020d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x79000008, 0x79000008,
0xc9035002, 0xc9035002,
0x69fd2403, 0x69fd2403,
@ -383,7 +383,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x51fd0404, 0x51fd0404,
0x2400020d, 0x2400020d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x2400052d, 0x2400052d,
0x24000605, 0x24000605,
0x2300acd1, 0x2300acd1,
@ -395,7 +395,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x0b01e0e0, 0x0b01e0e0,
0x0501e0e0, 0x0501e0e0,
0x4f00e0ff, 0x4f00e0ff,
0x230216d1, 0x230215d1,
0x100d0d63, 0x100d0d63,
0x0908f5f5, 0x0908f5f5,
0x0b18f4e0, 0x0b18f4e0,
@ -407,7 +407,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1f05c4c4, 0x1f05c4c4,
0x2400080d, 0x2400080d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x14637878, 0x14637878,
0x69014502, 0x69014502,
0x15ff7878, 0x15ff7878,
@ -451,7 +451,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x808113c1, 0x808113c1,
0xc901c405, 0xc901c405,
0x69084502, 0x69084502,
0x21028400, 0x21028200,
0x69074502, 0x69074502,
0x2102df00, 0x2102df00,
0x51000c2b, 0x51000c2b,
@ -522,15 +522,14 @@ const unsigned int Hiperface_DSL2_0[]= {
0x0b024d00, 0x0b024d00,
0x12006d6d, 0x12006d6d,
0x09064d4d, 0x09064d4d,
0xc901c402, 0x2103dd00,
0x2103db00,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0x106d6d1e, 0x106d6d1e,
0x511f0d03, 0x511f0d03,
0x51190d02, 0x51190d02,
0x79000003, 0x79000003,
0x230635d1, 0x23063ed1,
0x7900001a, 0x7900001a,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
@ -542,7 +541,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x511f0d12, 0x511f0d12,
0x51190d11, 0x51190d11,
0xc901c402, 0xc901c402,
0x21032000, 0x21032200,
0x910c3c81, 0x910c3c81,
0x240117e0, 0x240117e0,
0x04e1e0e0, 0x04e1e0e0,
@ -573,7 +572,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x810605c1, 0x810605c1,
0x24001f8d, 0x24001f8d,
0x2400044d, 0x2400044d,
0x230247d1, 0x230246d1,
0x05016d6d, 0x05016d6d,
0x51006d0c, 0x51006d0c,
0xd104ff00, 0xd104ff00,
@ -581,10 +580,10 @@ const unsigned int Hiperface_DSL2_0[]= {
0x24000b1e, 0x24000b1e,
0x24000f8d, 0x24000f8d,
0x2400044d, 0x2400044d,
0x230247d1, 0x230246d1,
0x24001f8d, 0x24001f8d,
0x2400034d, 0x2400034d,
0x230247d1, 0x230246d1,
0x05016d6d, 0x05016d6d,
0x6f006df6, 0x6f006df6,
0x10ebebd1, 0x10ebebd1,
@ -609,7 +608,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x10d1d18b, 0x10d1d18b,
0x2400040d, 0x2400040d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x108b8bd1, 0x108b8bd1,
0x24001fc0, 0x24001fc0,
0x810605c0, 0x810605c0,
@ -637,7 +636,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1f00c0c0, 0x1f00c0c0,
0x1f008181, 0x1f008181,
0x81505880, 0x81505880,
0x2104eb00, 0x2104f200,
0x91042580, 0x91042580,
0xd708e0ff, 0xd708e0ff,
0x91042580, 0x91042580,
@ -651,17 +650,16 @@ const unsigned int Hiperface_DSL2_0[]= {
0xcf08e0ff, 0xcf08e0ff,
0x20d10000, 0x20d10000,
0x117f6666, 0x117f6666,
0xc9066605, 0xc9066604,
0x2a000000,
0x24000066, 0x24000066,
0x81031866, 0x81031866,
0x7f0000da, 0x7f0000db,
0x710f6602, 0x710f6602,
0x24000f66, 0x24000f66,
0x590e6604, 0x590e6604,
0x91aa1800, 0x91aa1801,
0x1f008000, 0x1f000101,
0x81aa1800, 0x81aa1801,
0x13806666, 0x13806666,
0x81031866, 0x81031866,
0x20d10000, 0x20d10000,
@ -706,38 +704,40 @@ const unsigned int Hiperface_DSL2_0[]= {
0x10121221, 0x10121221,
0x81601881, 0x81601881,
0xd104c40e, 0xd104c40e,
0x91521801, 0x91521802,
0x110b0101, 0x11db0202,
0x5100980c, 0x5100980c,
0x913d1880, 0x913d1880,
0x1f050000, 0x1f050000,
0x813d1800, 0x813d1800,
0xc9052002, 0xc9052002,
0x2400269f, 0x2400269f,
0x1f050101, 0x1f050202,
0x81521801, 0x81521802,
0x2400060d, 0x2400060d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x7900003f, 0x79000041,
0x2400010d, 0x2400010d,
0x000d6666, 0x000d6666,
0x230253d1, 0x230252d1,
0x69fd7309, 0x69fd7309,
0x913d1880, 0x913d1880,
0x1f040000, 0x1f040000,
0x813d1800, 0x813d1800,
0xc9042002, 0xc9042002,
0x2400269f, 0x2400269f,
0x1f020101, 0x1f020202,
0x81521801, 0x81521802,
0x79000033, 0x79000035,
0x81521801, 0x81521802,
0x0908f3e2, 0x0908f3e2,
0x10727202, 0x10727202,
0x91a45800, 0x91a45800,
0x0480d281, 0x0480d281,
0x06c093c1, 0x04c093c1,
0x5880d202,
0x0501c1c1,
0x10e1e1e2, 0x10e1e1e2,
0xc91fe203, 0xc91fe203,
0x1600e2e2, 0x1600e2e2,
@ -746,7 +746,6 @@ const unsigned int Hiperface_DSL2_0[]= {
0x10404000, 0x10404000,
0x10606040, 0x10606040,
0x10000060, 0x10000060,
0x91501801,
0x70c0e204, 0x70c0e204,
0x10222200, 0x10222200,
0x10020220, 0x10020220,
@ -755,22 +754,23 @@ const unsigned int Hiperface_DSL2_0[]= {
0x10404000, 0x10404000,
0x10606040, 0x10606040,
0x10000060, 0x10000060,
0x91501801, 0x70c0e208,
0x70c0e207, 0x91501802,
0x1f010101, 0x1f010202,
0x91043880, 0x91043880,
0x1f018080, 0x1f018080,
0x81041880, 0x81041880,
0xc901c002, 0xc901c002,
0x2400229f, 0x2400229f,
0x1d010101, 0x91501802,
0x81501801, 0x1d010202,
0x81501802,
0x6900e105, 0x6900e105,
0x686e5304, 0x686e5304,
0x813a188d, 0x813a188d,
0x24000019, 0x24000019,
0x79000002, 0x79000002,
0x2304d1d1, 0x2304d2d1,
0x10535300, 0x10535300,
0x10333320, 0x10333320,
0x10131340, 0x10131340,
@ -801,13 +801,13 @@ const unsigned int Hiperface_DSL2_0[]= {
0x81541800, 0x81541800,
0x2400060d, 0x2400060d,
0x040d6666, 0x040d6666,
0x230253d1, 0x230252d1,
0x79000017, 0x79000017,
0x1d058000, 0x1d058000,
0x81541800, 0x81541800,
0x2400010d, 0x2400010d,
0x000d6666, 0x000d6666,
0x230253d1, 0x230252d1,
0x91541800, 0x91541800,
0x69fd6204, 0x69fd6204,
0x1f028000, 0x1f028000,
@ -836,10 +836,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x81361800, 0x81361800,
0x91081821, 0x91081821,
0x10210001, 0x10210001,
0x91503802, 0x5100010b,
0x1d060202,
0x1d060242,
0x5100010d,
0x91043880, 0x91043880,
0x1f068080, 0x1f068080,
0x81041880, 0x81041880,
@ -850,6 +847,11 @@ const unsigned int Hiperface_DSL2_0[]= {
0x813d1880, 0x813d1880,
0xc9062002, 0xc9062002,
0x2400269f, 0x2400269f,
0x91361800,
0x91503802,
0x1d060202,
0x1d060242,
0x51000003,
0x1f060202, 0x1f060202,
0x1f060242, 0x1f060242,
0x81503802, 0x81503802,
@ -857,10 +859,10 @@ const unsigned int Hiperface_DSL2_0[]= {
0x21018f00, 0x21018f00,
0x91001800, 0x91001800,
0xc9070002, 0xc9070002,
0x21023200, 0x21023100,
0x91351800, 0x91351800,
0xc9070002, 0xc9070002,
0x21023200, 0x21023100,
0x51005c2c, 0x51005c2c,
0x110ff602, 0x110ff602,
0x49085c02, 0x49085c02,
@ -931,7 +933,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x24003001, 0x24003001,
0xd1066b0e, 0xd1066b0e,
0x2400010d, 0x2400010d,
0x230660d1, 0x230669d1,
0x68ab8d45, 0x68ab8d45,
0x13803b3b, 0x13803b3b,
0x913d1880, 0x913d1880,
@ -944,7 +946,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x81531800, 0x81531800,
0x7900003b, 0x7900003b,
0x2400020d, 0x2400020d,
0x230660d1, 0x230669d1,
0x688b8d38, 0x688b8d38,
0x8137184b, 0x8137184b,
0x13803b3b, 0x13803b3b,
@ -987,7 +989,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1d09c4c4, 0x1d09c4c4,
0x2400040d, 0x2400040d,
0x24003001, 0x24003001,
0x230660d1, 0x230669d1,
0x15ff8d9c, 0x15ff8d9c,
0x69005c34, 0x69005c34,
0x51009c33, 0x51009c33,
@ -1041,7 +1043,8 @@ const unsigned int Hiperface_DSL2_0[]= {
0x2400181b, 0x2400181b,
0xc9027a02, 0xc9027a02,
0x01081b1b, 0x01081b1b,
0x2101e800, 0x2101e700,
0xc901c460,
0x24001031, 0x24001031,
0x91001800, 0x91001800,
0xc9060007, 0xc9060007,
@ -1050,7 +1053,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x24001e31, 0x24001e31,
0x2eff829a, 0x2eff829a,
0x1d09c4c4, 0x1d09c4c4,
0x7900005d, 0x79000057,
0x91351800, 0x91351800,
0xc9060007, 0xc9060007,
0x1d060000, 0x1d060000,
@ -1058,7 +1061,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x24001e31, 0x24001e31,
0x2eff829a, 0x2eff829a,
0x1d09c4c4, 0x1d09c4c4,
0x79000055, 0x7900004f,
0xc909c41c, 0xc909c41c,
0x05041b1b, 0x05041b1b,
0x490c1b06, 0x490c1b06,
@ -1066,7 +1069,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x110f3131, 0x110f3131,
0x69001b02, 0x69001b02,
0x1d09c4c4, 0x1d09c4c4,
0x7900004d, 0x79000047,
0xc9077a08, 0xc9077a08,
0x905a1831, 0x905a1831,
0xc9021b03, 0xc9021b03,
@ -1086,12 +1089,9 @@ const unsigned int Hiperface_DSL2_0[]= {
0x14809a9a, 0x14809a9a,
0x69101b02, 0x69101b02,
0x15ff1a1a, 0x15ff1a1a,
0x79000039, 0x79000033,
0x91401800, 0x91401800,
0x513f0016, 0x513f0013,
0x913d1840,
0x1d004040,
0x813d1840,
0x91531840, 0x91531840,
0x1d004040, 0x1d004040,
0x81531840, 0x81531840,
@ -1109,15 +1109,12 @@ const unsigned int Hiperface_DSL2_0[]= {
0x2400201b, 0x2400201b,
0x2400403b, 0x2400403b,
0x1f09c4c4, 0x1f09c4c4,
0x79000022, 0x7900001f,
0x912c1800, 0x912c1800,
0xc9000020, 0xc900001d,
0x1d000000, 0x1d000000,
0x812c1800, 0x812c1800,
0x1f09c4c4, 0x1f09c4c4,
0x91041880,
0x1d098080,
0x81041880,
0x91511800, 0x91511800,
0x1d010000, 0x1d010000,
0x81511800, 0x81511800,
@ -1158,6 +1155,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1d008080, 0x1d008080,
0x81aa1800, 0x81aa1800,
0x91031800, 0x91031800,
0x117f0000,
0x590e0007, 0x590e0007,
0x91505880, 0x91505880,
0x1f0a8080, 0x1f0a8080,
@ -1184,7 +1182,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x79000002, 0x79000002,
0x1d030101, 0x1d030101,
0x81501801, 0x81501801,
0x2101d500, 0x2101d400,
0x24000000, 0x24000000,
0x814e1800, 0x814e1800,
0xd103c40a, 0xd103c40a,
@ -1196,13 +1194,13 @@ const unsigned int Hiperface_DSL2_0[]= {
0xf020020d, 0xf020020d,
0x69000d03, 0x69000d03,
0x24fdfd80, 0x24fdfd80,
0x68808427, 0x68808426,
0x91381800, 0x91381800,
0x01010000, 0x01010000,
0x81381800, 0x81381800,
0x91411820, 0x91411820,
0x60200002, 0x60200002,
0x21023200, 0x21023100,
0x109d9d8b, 0x109d9d8b,
0x0901c880, 0x0901c880,
0x090288c0, 0x090288c0,
@ -1228,8 +1226,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x108787c7, 0x108787c7,
0x04c98087, 0x04c98087,
0x108080c9, 0x108080c9,
0x2304b8d1, 0x2304b9d1,
0x209d0000,
0x108b8b9d, 0x108b8b9d,
0x91aa1800, 0x91aa1800,
0x1f018000, 0x1f018000,
@ -1249,10 +1246,14 @@ const unsigned int Hiperface_DSL2_0[]= {
0x108787c7, 0x108787c7,
0x04c98087, 0x04c98087,
0x108080c9, 0x108080c9,
0x2304b8d1, 0x2304b9d1,
0x91983880, 0x91983880,
0x008e8080, 0x10eeeee1,
0x024ec0c0, 0x24000061,
0xc917ee02,
0x2400ff61,
0x00818080,
0x02c1c0c0,
0x81983880, 0x81983880,
0x10efefe0, 0x10efefe0,
0x10eeeee1, 0x10eeeee1,
@ -1293,18 +1294,25 @@ const unsigned int Hiperface_DSL2_0[]= {
0x0000526e, 0x0000526e,
0x0220720f, 0x0220720f,
0x02c093af, 0x02c093af,
0xc91fe003,
0x03ff536f,
0x79000002,
0x0300536f, 0x0300536f,
0x6902190b, 0x6902190f,
0xc90fc907, 0x24000040,
0xc90fc909,
0x1600c980, 0x1600c980,
0x01018080, 0x01018080,
0x0b038080, 0x0b038080,
0x16008080, 0x16008080,
0x01018080, 0x01018080,
0x79000002, 0x51008005,
0x13ff4040,
0x79000003,
0x10c9c980,
0x0b038080, 0x0b038080,
0x00808e8e, 0x00808e8e,
0x03006e6e, 0x02404e4e,
0x20d10000, 0x20d10000,
0x151f8484, 0x151f8484,
0x240478e2, 0x240478e2,
@ -1327,8 +1335,11 @@ const unsigned int Hiperface_DSL2_0[]= {
0x81080580, 0x81080580,
0x24001fc0, 0x24001fc0,
0x810605c0, 0x810605c0,
0x24004400,
0x810b1800,
0x81441800,
0x2eff8383, 0x2eff8383,
0x23027c9d, 0x23027a9d,
0x24000866, 0x24000866,
0x2400000c, 0x2400000c,
0x2400002c, 0x2400002c,
@ -1338,15 +1349,15 @@ const unsigned int Hiperface_DSL2_0[]= {
0x2eff8000, 0x2eff8000,
0x81351800, 0x81351800,
0x91501880, 0x91501880,
0x11da8080, 0x24000080,
0x13108080, 0x13108080,
0x81501880, 0x81501880,
0x91521880, 0x91521880,
0x11f48080, 0x24000080,
0x13108080, 0x13108080,
0x81521880, 0x81521880,
0x91541880, 0x91541880,
0x11748080, 0x24000080,
0x13108080, 0x13108080,
0x81541880, 0x81541880,
0x240128e1, 0x240128e1,
@ -1358,7 +1369,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x9101185b, 0x9101185b,
0x51005b0e, 0x51005b0e,
0x7900000d, 0x7900000d,
0x23061dd1, 0x230626d1,
0x91dc388c, 0x91dc388c,
0x240000e2, 0x240000e2,
0x91e21882, 0x91e21882,
@ -1366,7 +1377,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x100c0c2a, 0x100c0c2a,
0x106c6c4a, 0x106c6c4a,
0x102c2c6a, 0x102c2c6a,
0x23061dd1, 0x230626d1,
0x0b01e2e2, 0x0b01e2e2,
0x0501e2e2, 0x0501e2e2,
0x4f00e2ff, 0x4f00e2ff,
@ -1376,13 +1387,13 @@ const unsigned int Hiperface_DSL2_0[]= {
0x240000ca, 0x240000ca,
0x24001f8d, 0x24001f8d,
0x23016a9d, 0x23016a9d,
0x2301f7d1, 0x2301f6d1,
0x0101caca, 0x0101caca,
0x6f02cafc, 0x6f02cafc,
0x240000ca, 0x240000ca,
0x2400198d, 0x2400198d,
0x23016a9d, 0x23016a9d,
0x2301f7d1, 0x2301f6d1,
0x0101caca, 0x0101caca,
0x6f10cafc, 0x6f10cafc,
0x2400017b, 0x2400017b,
@ -1444,10 +1455,10 @@ const unsigned int Hiperface_DSL2_0[]= {
0x1e452121, 0x1e452121,
0x10000020, 0x10000020,
0x2d802101, 0x2d802101,
0x910c3c99, 0x910c3c82,
0x58e3f933, 0x58e3e233,
0x04f9e3eb, 0x04e2e3eb,
0x100b0b19, 0x100b0b02,
0x0b01ebeb, 0x0b01ebeb,
0x0501ebeb, 0x0501ebeb,
0x4f00ebff, 0x4f00ebff,
@ -1489,15 +1500,14 @@ const unsigned int Hiperface_DSL2_0[]= {
0x0b077200, 0x0b077200,
0x12001313, 0x12001313,
0x0901f2f2, 0x0901f2f2,
0x230629d1, 0x230632d1,
0x510e6506, 0x510e6506,
0x6f010df6, 0x6f010df6,
0x10656546, 0x10656546,
0x05012525, 0x05012525,
0x4f002595, 0x4f002595,
0x7900001c, 0x7900001a,
0x2a000000, 0xd118fe0b,
0xd118fe0c,
0xd105ff00, 0xd105ff00,
0x31010001, 0x31010001,
0x31010001, 0x31010001,
@ -1508,7 +1518,6 @@ const unsigned int Hiperface_DSL2_0[]= {
0x31010001, 0x31010001,
0x31010001, 0x31010001,
0x31010001, 0x31010001,
0x2a000000,
0x91a91800, 0x91a91800,
0x01010000, 0x01010000,
0x81a91800, 0x81a91800,
@ -1522,34 +1531,34 @@ const unsigned int Hiperface_DSL2_0[]= {
0x813d1800, 0x813d1800,
0xc9022002, 0xc9022002,
0x2400269f, 0x2400269f,
0x7f000030, 0x7f00002e,
0x24000925, 0x24000925,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0x24001b8d, 0x24001b8d,
0x23016a9d, 0x23016a9d,
0x2305ef9d, 0x2305f89d,
0x230629d1, 0x230632d1,
0x6f010dea, 0x6f010deb,
0x05012525, 0x05012525,
0x4f0025f8, 0x4f0025f8,
0x24001025, 0x24001025,
0x24001c8d, 0x24001c8d,
0x23016a9d, 0x23016a9d,
0x2305ef9d, 0x2305f89d,
0x230629d1, 0x230632d1,
0x6f010dd6, 0x6f010dd8,
0x05012525, 0x05012525,
0x4f0025fa, 0x4f0025fa,
0x810a1846, 0x810a1846,
0x24001d8d, 0x24001d8d,
0x23016a9d, 0x23016a9d,
0x2300ef9d, 0x2300ef9d,
0x6e0403cf, 0x6e0403d1,
0x6e2423ce, 0x6e2423d0,
0x110f4300, 0x110f4300,
0x0b044320, 0x0b044320,
0x6e2000cb, 0x6e2000cd,
0x10848480, 0x10848480,
0x10434340, 0x10434340,
0x10404001, 0x10404001,
@ -1558,7 +1567,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x810d3801, 0x810d3801,
0x2400000d, 0x2400000d,
0x000d6666, 0x000d6666,
0x230253d1, 0x230252d1,
0x1f08c4c4, 0x1f08c4c4,
0x110fe05d, 0x110fe05d,
0x01085d5d, 0x01085d5d,
@ -1572,10 +1581,10 @@ const unsigned int Hiperface_DSL2_0[]= {
0x24ffff81, 0x24ffff81,
0x0a00e1e1, 0x0a00e1e1,
0x81e43881, 0x81e43881,
0x2301f7d1, 0x2301f6d1,
0x21001600, 0x21001600,
0x24002005, 0x24002005,
0x230262d1, 0x230260d1,
0x24000080, 0x24000080,
0x2405a4eb, 0x2405a4eb,
0x2eff8992, 0x2eff8992,
@ -1588,7 +1597,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x10000020, 0x10000020,
0x0b018001, 0x0b018001,
0x14000130, 0x14000130,
0x230277d1, 0x230275d1,
0x6f0005f6, 0x6f0005f6,
0x24001d05, 0x24001d05,
0xc918ff00, 0xc918ff00,
@ -1600,7 +1609,7 @@ const unsigned int Hiperface_DSL2_0[]= {
0x10000020, 0x10000020,
0x0b018001, 0x0b018001,
0x14000130, 0x14000130,
0x230277d1, 0x230275d1,
0x6f0105f6, 0x6f0105f6,
0xc918ff00, 0xc918ff00,
0x101f1f00, 0x101f1f00,
@ -1617,8 +1626,8 @@ const unsigned int Hiperface_DSL2_0[]= {
0x0501e0e0, 0x0501e0e0,
0x4f00e0ff, 0x4f00e0ff,
0x1d007e7e, 0x1d007e7e,
0x230216d1, 0x230215d1,
0x2301f7d1, 0x2301f6d1,
0x209d0000, 0x209d0000,
0x91502181, 0x91502181,
0x91502194, 0x91502194,
@ -1704,4 +1713,4 @@ const unsigned int Hiperface_DSL2_0[]= {
0x91003c82, 0x91003c82,
0x1308e2e2, 0x1308e2e2,
0x81003c82, 0x81003c82,
0x2104ea00 }; 0x2104f200 };

6
source/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h
View File

@ -1324,15 +1324,15 @@ const unsigned int Hiperface_DSL2_0[]= {
0x2eff8000, 0x2eff8000,
0x81351800, 0x81351800,
0x91501880, 0x91501880,
0x11da8080, 0x24000080,
0x13108080, 0x13108080,
0x81501880, 0x81501880,
0x91521880, 0x91521880,
0x11f48080, 0x24000080,
0x13108080, 0x13108080,
0x81521880, 0x81521880,
0x91541880, 0x91541880,
0x11748080, 0x24000080,
0x13108080, 0x13108080,
0x81541880, 0x81541880,
0x240128e1, 0x240128e1,

6
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
View File

@ -1543,15 +1543,15 @@ const unsigned int Hiperface_DSL2_0_RTU[]= {
0x2eff8000, 0x2eff8000,
0x81351800, 0x81351800,
0x91501880, 0x91501880,
0x11da8080, 0x24000080,
0x13108080, 0x13108080,
0x81501880, 0x81501880,
0x91521880, 0x91521880,
0x11f48080, 0x24000080,
0x13108080, 0x13108080,
0x81521880, 0x81521880,
0x91541880, 0x91541880,
0x11748080, 0x24000080,
0x13108080, 0x13108080,
0x81541880, 0x81541880,
0x240128e1, 0x240128e1,

6
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h
View File

@ -1544,15 +1544,15 @@ const unsigned int Hiperface_DSL2_0_PRU[]= {
0x2eff8000, 0x2eff8000,
0x81351800, 0x81351800,
0x91501880, 0x91501880,
0x11da8080, 0x24000080,
0x13108080, 0x13108080,
0x81501880, 0x81501880,
0x91521880, 0x91521880,
0x11f48080, 0x24000080,
0x13108080, 0x13108080,
0x81521880, 0x81521880,
0x91541880, 0x91541880,
0x11748080, 0x24000080,
0x13108080, 0x13108080,
0x81541880, 0x81541880,
0x240128e1, 0x240128e1,

8
source/position_sense/hdsl/firmware/hdsl_master_icssg_sync_bin.h
View File

@ -2,7 +2,7 @@
* hdsl_master_icssg_sync_bin.h * hdsl_master_icssg_sync_bin.h
* *
* *
* Copyright (c) 2021-2023, Texas Instruments Incorporated * Copyright (c) 2015 - 2016, Texas Instruments Incorporated
* All rights reserved not granted herein. * All rights reserved not granted herein.
* *
* Limited License. * Limited License.
@ -1454,15 +1454,15 @@ const unsigned int Hiperface_DSL_SYNC2_0[]= {
0x2eff8000, 0x2eff8000,
0x81351800, 0x81351800,
0x91501880, 0x91501880,
0x11da8080, 0x24000080,
0x13108080, 0x13108080,
0x81501880, 0x81501880,
0x91521880, 0x91521880,
0x11f48080, 0x24000080,
0x13108080, 0x13108080,
0x81521880, 0x81521880,
0x91541880, 0x91541880,
0x11748080, 0x24000080,
0x13108080, 0x13108080,
0x81541880, 0x81541880,
0x240128e1, 0x240128e1,

13
source/position_sense/hdsl/firmware/memory.inc
View File

@ -202,7 +202,7 @@ LONG_MSG_RECV .sassign r28, long_msg_recv_s
.asg r16.b3, BYTE_ERROR .asg r16.b3, BYTE_ERROR
.asg r15, FAST_POSH .asg r15, FAST_POSH
.asg r14.b3, FAST_POSL .asg r14.b3, FAST_POSL
.asg r14, SPEED .asg r14, SPEED ; NOTE: r14.b3 is used as FAST_POSL
.asg r17.b0, DISPARITY .asg r17.b0, DISPARITY
.asg r17.b1, SEND_PARA .asg r17.b1, SEND_PARA
.asg r29.w0, RET_ADDR0 .asg r29.w0, RET_ADDR0
@ -494,9 +494,12 @@ VPOSCRC2_H .set 0x4C
VPOSCRC2_L .set 0x4D VPOSCRC2_L .set 0x4D
POSTX .set 0x4E POSTX .set 0x4E
ONLINE_STATUS_D .set 0x50 ONLINE_STATUS_D_H .set 0x50
ONLINE_STATUS_1 .set 0x52 ONLINE_STATUS_D_L .set 0x51
ONLINE_STATUS_2 .set 0x54 ONLINE_STATUS_1_H .set 0x52
ONLINE_STATUS_1_L .set 0x53
ONLINE_STATUS_2_H .set 0x54
ONLINE_STATUS_2_L .set 0x55
H_FRAME_FLAGS_TEMP .set 0x56 ; 2 bytes H_FRAME_FLAGS_TEMP .set 0x56 ; 2 bytes
CRC_SEC_TEMP .set 0x58 ; 2 bytes CRC_SEC_TEMP .set 0x58 ; 2 bytes
@ -506,4 +509,4 @@ VPOSCRC_TEMP .set 0x60 ; 2 bytes
STATUS2_TEMP .set 0x62 ; 1 byte STATUS2_TEMP .set 0x62 ; 1 byte
VPOS2_TEMP .set 0x63 ; 5 bytes VPOS2_TEMP .set 0x63 ; 5 bytes
VPOSCRC2_TEMP .set 0x68 ; 2 bytes VPOSCRC2_TEMP .set 0x68 ; 2 bytes
SAFE_SUM_TEMP .set 0x70 ; 1 byte SAFE_SUM_TEMP .set 0x70 ; 1 byte

161
source/position_sense/hdsl/firmware/transport.asm
View File

@ -111,8 +111,8 @@ transport_on_v_frame:
sbco &REG_TMP1, MASTER_REGS_CONST, VPOSCRC_TEMP, 2 sbco &REG_TMP1, MASTER_REGS_CONST, VPOSCRC_TEMP, 2
;transmission error? ;transmission error?
qbbs transport_on_v_frame_dont_update_qm, H_FRAME.flags, FLAG_ERR_VERT qbbs transport_on_v_frame_dont_update_qm, H_FRAME.flags, FLAG_ERR_VERT
lbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1, 1 lbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
and REG_TMP1.b0, REG_TMP1.b0, (~((1<<ONLINE_STATUS_1_SCE) | (1<<ONLINE_STATUS_1_VPOS)) & 0xF) and REG_TMP2.b0, REG_TMP2.b0, (~((1<<ONLINE_STATUS_1_SCE) | (1<<ONLINE_STATUS_1_VPOS)) & 0xFF)
;checking for crc error ;checking for crc error
qbeq check_for_slave_error_on_v_frame, CRC_VERT, 0 qbeq check_for_slave_error_on_v_frame, CRC_VERT, 0
; Set EVENT_S_SCE in EVENT register ; Set EVENT_S_SCE in EVENT register
@ -125,8 +125,8 @@ transport_on_v_frame:
ldi r31.w0, PRU0_ARM_IRQ4 ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int4: update_events_no_int4:
; Set ONLINE_STATUS_1_SCE in ONLINE_STATUS_1 register ; Set ONLINE_STATUS_1_SCE in ONLINE_STATUS_1 register
set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_1_SCE set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_SCE
sbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1, 1 sbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
QM_SUB 6 QM_SUB 6
transport_on_v_frame_dont_update_qm: transport_on_v_frame_dont_update_qm:
;update CRC error count ;update CRC error count
@ -135,10 +135,10 @@ transport_on_v_frame_dont_update_qm:
add REG_TMP1, REG_TMP1, 1 add REG_TMP1, REG_TMP1, 1
sbco &REG_TMP1, MASTER_REGS_CONST, NUM_VERT_ERR0, 4 sbco &REG_TMP1, MASTER_REGS_CONST, NUM_VERT_ERR0, 4
.endif .endif
;HALT
qba transport_on_v_frame_exit qba transport_on_v_frame_exit
check_for_slave_error_on_v_frame: check_for_slave_error_on_v_frame:
;CRC was correct -> add 1 to QM ;CRC was correct -> add 1 to QM
;Note: QM_ADD uses REG_TMP1
QM_ADD 1 QM_ADD 1
;check for special character: K29.7 is sent in first byte of vertical channel if slave error occured ;check for special character: K29.7 is sent in first byte of vertical channel if slave error occured
qbne transport_on_v_frame_check_pos, VERT_H.b3, K29_7 qbne transport_on_v_frame_check_pos, VERT_H.b3, K29_7
@ -152,11 +152,11 @@ check_for_slave_error_on_v_frame:
ldi r31.w0, PRU0_ARM_IRQ4 ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int5: update_events_no_int5:
; Set ONLINE_STATUS_1_VPOS in ONLINE_STATUS_1 register ; Set ONLINE_STATUS_1_VPOS in ONLINE_STATUS_1 register
set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_1_VPOS set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_VPOS
sbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1, 1 sbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
qba transport_on_v_frame_exit qba transport_on_v_frame_exit
transport_on_v_frame_check_pos: transport_on_v_frame_check_pos:
sbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1, 1 sbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
lsl REG_TMP2, CHANNEL.ch_verth, 8 lsl REG_TMP2, CHANNEL.ch_verth, 8
mov REG_TMP2.b0, VERT_L.b3 mov REG_TMP2.b0, VERT_L.b3
;first V-Frame? -> update FAST POS with SAFE POS ;first V-Frame? -> update FAST POS with SAFE POS
@ -164,7 +164,11 @@ transport_on_v_frame_not_first:
;check for LAST FAST POS and SAFE POS mismatch ;check for LAST FAST POS and SAFE POS mismatch
lbco &REG_TMP0.b0, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS lbco &REG_TMP0.b0, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS
sub REG_TMP1.w0, VERT_L.w2, REG_TMP0.w0 sub REG_TMP1.w0, VERT_L.w2, REG_TMP0.w0
suc REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2 sub REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2
qble no_sub_carry, VERT_L.w2, REG_TMP0.w0
; if carry is needed, subtract 1 separately
sub REG_TMP1.w2, REG_TMP1.w2, 1
no_sub_carry:
mov REG_TMP2, REG_TMP1 mov REG_TMP2, REG_TMP1
;check if diff is neg, ;check if diff is neg,
qbbc transport_on_v_frame_diff_pos, REG_TMP2, 31 qbbc transport_on_v_frame_diff_pos, REG_TMP2, 31
@ -177,7 +181,6 @@ transport_on_v_frame_diff_pos:
mov REG_TMP0.b2, REG_TMP0.b3 mov REG_TMP0.b2, REG_TMP0.b3
mov REG_TMP0.b3, REG_TMP0.b0 mov REG_TMP0.b3, REG_TMP0.b0
;check if it is larger ;check if it is larger
lbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1
qbge transport_on_v_frame_dont_update_maxdev, REG_TMP2, REG_TMP0.w2 qbge transport_on_v_frame_dont_update_maxdev, REG_TMP2, REG_TMP0.w2
mov REG_TMP0.b0, REG_TMP2.b1 mov REG_TMP0.b0, REG_TMP2.b1
mov REG_TMP0.b1, REG_TMP2.b0 mov REG_TMP0.b1, REG_TMP2.b0
@ -193,10 +196,10 @@ transport_on_v_frame_dont_update_maxdev:
mov REG_TMP0.b2, REG_TMP0.b3 mov REG_TMP0.b2, REG_TMP0.b3
mov REG_TMP0.b3, REG_TMP0.b0 mov REG_TMP0.b3, REG_TMP0.b0
;check if it is larger ;check if it is larger
lbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1
qbge transport_on_v_frame_dont_update_dte, REG_TMP2, REG_TMP0.w2 qbge transport_on_v_frame_dont_update_dte, REG_TMP2, REG_TMP0.w2
; Set EVENT_DTE in ONLINE_STATUS_D register ; Set EVENT_DTE in ONLINE_STATUS_D register
set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE lbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1
set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_DTE
; Set EVENT_DTE in EVENT register ; Set EVENT_DTE in EVENT register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4 lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
set REG_TMP0.w0, REG_TMP0.w0, EVENT_DTE set REG_TMP0.w0, REG_TMP0.w0, EVENT_DTE
@ -208,8 +211,9 @@ transport_on_v_frame_dont_update_maxdev:
update_events_no_int6: update_events_no_int6:
transport_on_v_frame_dont_update_dte: transport_on_v_frame_dont_update_dte:
; Clear EVENT_DTE in ONLINE_STATUS_D register ; Clear EVENT_DTE in ONLINE_STATUS_D register
clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE lbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1
sbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_DTE
sbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1
;check for diff. is 0 -> estimate if not ;check for diff. is 0 -> estimate if not
qbne transport_on_v_frame_estimate, REG_TMP1, 0 qbne transport_on_v_frame_estimate, REG_TMP1, 0
@ -287,7 +291,7 @@ transport_on_v_frame_2:
lbco &REG_TMP1, MASTER_REGS_CONST, VPOS2_TEMP, 8 lbco &REG_TMP1, MASTER_REGS_CONST, VPOS2_TEMP, 8
; error checks for secondary channel ; error checks for secondary channel
lbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
; retrieve H_FRAME.flags from H_FRAME_FLAGS_TEMP ; retrieve H_FRAME.flags from H_FRAME_FLAGS_TEMP
lbco &REG_TMP0.w2, MASTER_REGS_CONST, H_FRAME_FLAGS_TEMP, 2 lbco &REG_TMP0.w2, MASTER_REGS_CONST, H_FRAME_FLAGS_TEMP, 2
;channel 2 transmission error? ;channel 2 transmission error?
@ -298,24 +302,24 @@ transport_on_v_frame_2:
qbeq check_for_slave_error_on_secondary_channel, REG_TMP0.w2, 0 qbeq check_for_slave_error_on_secondary_channel, REG_TMP0.w2, 0
; set SCE2 bit in ONLINE_STATUS_2 ; set SCE2 bit in ONLINE_STATUS_2
set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2
sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
QM_SUB 6 QM_SUB 6
transport_on_v_frame_dont_update_qm_secondary_channel: transport_on_v_frame_dont_update_qm_secondary_channel:
qba transport_on_v_frame_2_exit qba transport_on_v_frame_2_exit
check_for_slave_error_on_secondary_channel: check_for_slave_error_on_secondary_channel:
; clear SCE2 bit in ONLINE_STATUS_2 ; clear SCE2 bit in ONLINE_STATUS_2
clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2
sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
;CRC was correct -> add 1 to QM ;CRC was correct -> add 1 to QM
QM_ADD 1 QM_ADD 1
; NOTE: QM_ADD uses REG_TMP0. Loading REG_TMP0 again here. It can be optimized. ; NOTE: QM_ADD uses REG_TMP0. Loading REG_TMP0 again here. It can be optimized.
lbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
;check for special character: K29.7 is sent in first byte of secondary vertical channel if slave error occured ;check for special character: K29.7 is sent in first byte of secondary vertical channel if slave error occured
; assumption: r21.b3 contains the first byte of secondary vertical channel ; assumption: r21.b3 contains the first byte of secondary vertical channel
qbne transport_on_v_frame_no_vpos2_error, REG_TMP2.b3, K29_7 qbne transport_on_v_frame_no_vpos2_error, REG_TMP2.b3, K29_7
; set VPOS2 bit in ONLINE_STATUS_2 ; set VPOS2 bit in ONLINE_STATUS_2
set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2
sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
qba transport_on_v_frame_vpos2_error_exit qba transport_on_v_frame_vpos2_error_exit
transport_on_v_frame_no_vpos2_error: transport_on_v_frame_no_vpos2_error:
clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2
@ -335,7 +339,7 @@ transport_on_v_frame_vpos2_error_exit:
online_status_2_sum2_set: online_status_2_sum2_set:
set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SUM2 set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SUM2
online_status_2_sum2_not_set: online_status_2_sum2_not_set:
sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
; Store STATUS2, VPOS24, VPOS23 and VPOS22 ; Store STATUS2, VPOS24, VPOS23 and VPOS22
@ -366,9 +370,6 @@ transport_skip_vpos_update:
;check SUMMARY and MASK_SUM ;check SUMMARY and MASK_SUM
lbco &REG_TMP1.b1, MASTER_REGS_CONST, MASK_SUM, 1 lbco &REG_TMP1.b1, MASTER_REGS_CONST, MASK_SUM, 1
and REG_TMP1.b0, REG_TMP0.b0, REG_TMP1.b1 and REG_TMP1.b0, REG_TMP0.b0, REG_TMP1.b1
lbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 3
clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM
clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM
qbeq summary_no_int, REG_TMP1.b0, 0x00 qbeq summary_no_int, REG_TMP1.b0, 0x00
;set event and generate interrupt ;set event and generate interrupt
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4 lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
@ -389,10 +390,18 @@ update_events_no_int7:
; generate interrupt_s ; generate interrupt_s
ldi r31.w0, PRU0_ARM_IRQ4 ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int17: update_events_no_int17:
summary_no_int:
; Update SUM and SSUM bits in ONLINE_STATUS registers
lbco &REG_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM, 1
lbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3
clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM
clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM
qbeq online_status_sum_clear, REG_TMP0.b0, 0x00
set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM
set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM
summary_no_int: online_status_sum_clear:
sbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 3 sbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3
;restore REG_FNC.w0 content ;restore REG_FNC.w0 content
mov REG_FNC.w0, REG_TMP11.w1 mov REG_FNC.w0, REG_TMP11.w1
@ -472,9 +481,9 @@ transport_layer_recving_long_msg_crc:
ldi r31.w0, PRU0_ARM_IRQ ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int8: update_events_no_int8:
; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
;check for crc error ;check for crc error
qbeq transport_layer_recving_long_msg_end, LONG_MSG_RECV.crc, 0 qbeq transport_layer_recving_long_msg_end, LONG_MSG_RECV.crc, 0
; Set EVENT_ANS in EVENT register ; Set EVENT_ANS in EVENT register
@ -487,14 +496,14 @@ update_events_no_int8:
ldi r31.w0, PRU0_ARM_IRQ ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int9: update_events_no_int9:
; Set ANS in ONLINE_STATUS_D register ; Set ANS in ONLINE_STATUS_D register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
transport_layer_recving_long_msg_end: transport_layer_recving_long_msg_end:
; Clear ANS in ONLINE_STATUS_D register ; Clear ANS in ONLINE_STATUS_D register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
sub LONG_MSG_RECV.bits_left, LONG_MSG_RECV.bits_left, 4 sub LONG_MSG_RECV.bits_left, LONG_MSG_RECV.bits_left, 4
qba transport_layer_recv_msg_end qba transport_layer_recv_msg_end
transport_layer_check_for_new_msg: transport_layer_check_for_new_msg:
@ -551,9 +560,9 @@ transport_layer_received_short_msg:
ldi r31.w0, PRU0_ARM_IRQ ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int100: update_events_no_int100:
; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1
qba transport_layer_recv_msg_check_for_nak qba transport_layer_recv_msg_check_for_nak
transport_layer_short_msg_recv_read: transport_layer_short_msg_recv_read:
;received read answer ;received read answer
@ -575,9 +584,9 @@ transport_layer_short_msg_recv_read:
ldi r31.w0, PRU0_ARM_IRQ ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int10: update_events_no_int10:
; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1
qba transport_layer_recv_msg_check_for_nak qba transport_layer_recv_msg_check_for_nak
transport_layer_received_long_msg: transport_layer_received_long_msg:
@ -623,9 +632,9 @@ transport_layer_received_long_msg_no_loffset_crc:
ldi r31.w0, PRU0_ARM_IRQ ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int11: update_events_no_int11:
; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
clr H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY clr H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY
transport_layer_received_long_msg_loffset_end: transport_layer_received_long_msg_loffset_end:
;calculate CRC for already recevied bits ;calculate CRC for already recevied bits
@ -646,9 +655,9 @@ transport_layer_received_long_msg_loffset_end:
ldi r31.w0, PRU0_ARM_IRQ ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int12: update_events_no_int12:
; Set ANS in ONLINE_STATUS_D register ; Set ANS in ONLINE_STATUS_D register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
qba transport_layer_resend_msg_end qba transport_layer_resend_msg_end
transport_layer_recv_no_msg: transport_layer_recv_no_msg:
;reset flag ;reset flag
@ -670,9 +679,9 @@ transport_layer_recv_msg_check_for_nak:
ldi r31.w0, PRU0_ARM_IRQ ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int13: update_events_no_int13:
; Set ANS in ONLINE_STATUS_D register ; Set ANS in ONLINE_STATUS_D register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
qba transport_layer_recv_msg_check_for_init_no_init qba transport_layer_recv_msg_check_for_init_no_init
transport_layer_recv_msg_check_for_nak_no_lnak: transport_layer_recv_msg_check_for_nak_no_lnak:
;check for S_PAR_INIT ;check for S_PAR_INIT
@ -696,17 +705,17 @@ update_events_no_int19:
; generate interrupt ; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ4 ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int20: update_events_no_int20:
lbco &REG_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 lbco &REG_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3
set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8)
set REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_MIN-8) set REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_MIN-8)
sbco &REG_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 sbco &REG_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3
qba transport_layer_min_update_done qba transport_layer_min_update_done
transport_layer_recv_msg_check_for_init_no_init: transport_layer_recv_msg_check_for_init_no_init:
transport_layer_min_unset: transport_layer_min_unset:
lbco &REG_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 lbco &REG_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3
clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8)
clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_MIN-8) clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_MIN-8)
sbco &REG_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 sbco &REG_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3
transport_layer_min_update_done: transport_layer_min_update_done:
;check for timeout - count only down when bitsleft = 0 amnd timeout != 0 ;check for timeout - count only down when bitsleft = 0 amnd timeout != 0
qbne transport_layer_resend_msg_end, SHORT_MSG.bits_left, 0 qbne transport_layer_resend_msg_end, SHORT_MSG.bits_left, 0
@ -736,6 +745,8 @@ transport_layer_recv_msg_end:
;---------------------------------------------------- ;----------------------------------------------------
transport_layer_send_msg: transport_layer_send_msg:
;TODO: reduce cycles ;TODO: reduce cycles
; Skip message processing until one v-frame is complete
qbbc transport_layer_send_msg_end, H_FRAME.flags, FLAG_NORMAL_FLOW
ldi SEND_PARA, M_PAR_IDLE ldi SEND_PARA, M_PAR_IDLE
;check if we discard any messages and reset parameter channel ;check if we discard any messages and reset parameter channel
lbco &REG_TMP0.b0, MASTER_REGS_CONST, SYS_CTRL, 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, SYS_CTRL, 1
@ -820,14 +831,10 @@ transport_layer_check_for_new_short_msg:
lbco &REG_TMP0.b0, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1
qbeq transport_layer_no_short_msg, REG_TMP0.b0, 0x3f qbeq transport_layer_no_short_msg, REG_TMP0.b0, 0x3f
;set short msg channel to busy (reset EVENT_S_FRES) ; Clear ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register
lbco &REG_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 lbco &REG_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1
clr REG_TMP0.b2, REG_TMP0.b2, EVENT_S_FRES
sbco &REG_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1
; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register
lbco &REG_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1
clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_FRES-8) clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_FRES-8)
sbco &REG_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 sbco &REG_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1
;reset ;reset
ldi REG_TMP0.b1, 0x3f ldi REG_TMP0.b1, 0x3f
sbco &REG_TMP0.b1, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1 sbco &REG_TMP0.b1, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1
@ -864,14 +871,10 @@ transport_layer_no_short_msg:
sbco &REG_TMP0.b0, MASTER_REGS_CONST, PC_CTRL, 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, PC_CTRL, 1
;set para channel to busy ;set para channel to busy
set H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY set H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY
;set long msg channel to busy (reset FREL) ; Clear ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 2 lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
clr REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL
sbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 2
; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register
lbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1
clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
lbco &REG_TMP1, MASTER_REGS_CONST, PC_ADD_H, 4 lbco &REG_TMP1, MASTER_REGS_CONST, PC_ADD_H, 4
mov SHORT_MSG.addr, REG_TMP1.b0 mov SHORT_MSG.addr, REG_TMP1.b0
ldi SHORT_MSG.bits_left, 16 ldi SHORT_MSG.bits_left, 16
@ -939,25 +942,27 @@ transport_layer_no_qmlw_event:
; Update QMLW bits in ONLINE_STATUS registers ; Update QMLW bits in ONLINE_STATUS registers
lbco &REG_TMP0.b0, MASTER_REGS_CONST, MASTER_QM, 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, MASTER_QM, 1
and REG_TMP0.b0, REG_TMP0.b0, 0x7f
; Set QMLW if value is < 14
qble transport_layer_online_status_qm_not_low, REG_TMP0.b0, 14 qble transport_layer_online_status_qm_not_low, REG_TMP0.b0, 14
; Set QMLW bits ; Set QMLW bits
lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW
set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW
set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
qba transport_layer_online_status_qm_update_done qba transport_layer_online_status_qm_update_done
transport_layer_online_status_qm_not_low: transport_layer_online_status_qm_not_low:
; Clear QMLW bits ; Clear QMLW bits
lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
clr REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW clr REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW
clr REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW clr REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW
clr REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW clr REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
transport_layer_online_status_qm_update_done: transport_layer_online_status_qm_update_done:
; update POS bits in ONLINE_STATUS_D and EVENT ; update POS bits in ONLINE_STATUS_D and EVENT
lbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 lbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1
; Check EVENT_UPDATE_PENDING_POS to process a pending POS set ; Check EVENT_UPDATE_PENDING_POS to process a pending POS set
lbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1
qbbc transport_layer_no_pos_event, REG_TMP0.b0, EVENT_UPDATE_PENDING_POS qbbc transport_layer_no_pos_event, REG_TMP0.b0, EVENT_UPDATE_PENDING_POS
@ -979,7 +984,7 @@ update_events_no_int14:
transport_layer_no_pos_event: transport_layer_no_pos_event:
clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_POS clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_POS
transport_layer_pos_update_done: transport_layer_pos_update_done:
sbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 sbco &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1
jmp transport_layer_send_msg_done jmp transport_layer_send_msg_done
;---------------------------------------------------- ;----------------------------------------------------
@ -1073,7 +1078,6 @@ calc_speed_extend_acc1:
sub DELTA_ACC0, REG_TMP0.w0, LAST_ACC sub DELTA_ACC0, REG_TMP0.w0, LAST_ACC
mov LAST_ACC, REG_TMP0.w0 mov LAST_ACC, REG_TMP0.w0
CALL1 calc_fastpos CALL1 calc_fastpos
RET
;restore return addr ;restore return addr
mov RET_ADDR0, REG_TMP11.w0 mov RET_ADDR0, REG_TMP11.w0
; Moving the event and online register update during stuffing ; Moving the event and online register update during stuffing
@ -1108,8 +1112,14 @@ calc_speed_extend_acc0:
transport_on_h_frame_exit: transport_on_h_frame_exit:
;calculate rel. pos and store ;calculate rel. pos and store
lbco &REG_TMP0, MASTER_REGS_CONST, REL_POS0, 4 lbco &REG_TMP0, MASTER_REGS_CONST, REL_POS0, 4
add REG_TMP0.w0, REG_TMP0.w0, SPEED.w0 ;sign extend speed to 32 bits and add it to REL_POS
adc REG_TMP0.w2, REG_TMP0.w2, SPEED.b2 mov REG_TMP1, SPEED
ldi REG_TMP1.b3, 0
qbbc calc_relpos_extend_vel, SPEED, 23
ldi REG_TMP1.b3, 0xff
calc_relpos_extend_vel:
add REG_TMP0.w0, REG_TMP0.w0, REG_TMP1.w0
adc REG_TMP0.w2, REG_TMP0.w2, REG_TMP1.w2
sbco &REG_TMP0, MASTER_REGS_CONST, REL_POS0, 4 sbco &REG_TMP0, MASTER_REGS_CONST, REL_POS0, 4
;store fast pos. and velocity ;store fast pos. and velocity
mov REG_TMP0, FAST_POSH mov REG_TMP0, FAST_POSH
@ -1205,21 +1215,32 @@ estimator_fpos:
add FAST_POSL, VERT_L.b2, REG_TMP0.b0 add FAST_POSL, VERT_L.b2, REG_TMP0.b0
adc FAST_POSH.b0, VERT_L.b3, REG_TMP0.b1 adc FAST_POSH.b0, VERT_L.b3, REG_TMP0.b1
adc FAST_POSH.w1, VERT_H.w0, REG_TMP0.w2 adc FAST_POSH.w1, VERT_H.w0, REG_TMP0.w2
;sign extend relative position to 40 bits
qbbc estimator_fpos_add_relpos_positive, REG_TMP0, 31
adc FAST_POSH.b3, VERT_H.b2, 0xFF
qba estimator_fpos_add_relpos_done
estimator_fpos_add_relpos_positive:
adc FAST_POSH.b3, VERT_H.b2, 0 adc FAST_POSH.b3, VERT_H.b2, 0
estimator_fpos_add_relpos_done:
qbne estimator_fpos_align_ph_not_2, ALIGN_PH, 2 qbne estimator_fpos_align_ph_not_2, ALIGN_PH, 2
;vel = vel+acc/8 ;vel = vel+acc/8
qbbc estimator_fpos_acc_pos, LAST_ACC, 15 ldi REG_TMP0.b2, 0
qbbc estimator_fpos_acc_pos, LAST_ACC, 15
not REG_TMP0.w0, LAST_ACC not REG_TMP0.w0, LAST_ACC
add REG_TMP0.w0, REG_TMP0.w0, 1 add REG_TMP0.w0, REG_TMP0.w0, 1
lsr REG_TMP0.w0, REG_TMP0.w0, 3 lsr REG_TMP0.w0, REG_TMP0.w0, 3
not REG_TMP0.w0, REG_TMP0.w0 not REG_TMP0.w0, REG_TMP0.w0
add REG_TMP0.w0, REG_TMP0.w0, 1 add REG_TMP0.w0, REG_TMP0.w0, 1
;sign extend acceleration to 24 bit -> speed size
qbeq estimator_fpos_acc_sing_check_end, REG_TMP0.w0, 0
or REG_TMP0.b2, REG_TMP0.b2, 0xFF
qba estimator_fpos_acc_sing_check_end qba estimator_fpos_acc_sing_check_end
estimator_fpos_acc_pos: estimator_fpos_acc_pos:
mov REG_TMP0.w0, LAST_ACC
lsr REG_TMP0.w0, REG_TMP0.w0, 3 lsr REG_TMP0.w0, REG_TMP0.w0, 3
estimator_fpos_acc_sing_check_end: estimator_fpos_acc_sing_check_end:
add SPEED.w0, SPEED.w0, REG_TMP0.w0 add SPEED.w0, SPEED.w0, REG_TMP0.w0
adc SPEED.b3, SPEED.b3, 0 adc SPEED.b2, SPEED.b2, REG_TMP0.b2
estimator_fpos_align_ph_not_2: estimator_fpos_align_ph_not_2:
RET1 RET1
;-------------------------------------------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------

162
source/position_sense/hdsl/include/hdsl_drv.h
View File

@ -92,6 +92,8 @@ extern "C" {
/* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */ /* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */
#define SYNCEVT_RTR_SYNC10_EVT 0x2C #define SYNCEVT_RTR_SYNC10_EVT 0x2C
#define ONLINE_STATUS_1_L_FRES (1<<0)
enum { enum {
MENU_SAFE_POSITION, MENU_SAFE_POSITION,
MENU_QUALITY_MONITORING, MENU_QUALITY_MONITORING,
@ -126,90 +128,94 @@ typedef struct HDSL_Config_s *HDSL_Handle;
* @{ * @{
*/ */
typedef struct { typedef struct {
volatile uint8_t SYS_CTRL; /**< System control */ volatile uint8_t SYS_CTRL; /**< System control */
volatile uint8_t SYNC_CTRL; /**< Synchronization control */ volatile uint8_t SYNC_CTRL; /**< Synchronization control */
volatile uint8_t resvd0; /**< Reserved 0 */ volatile uint8_t resvd0; /**< Reserved 0 */
volatile uint8_t MASTER_QM; /**< Quality monitoring */ volatile uint8_t MASTER_QM; /**< Quality monitoring */
volatile uint8_t EVENT_H; /**< High bytes event */ volatile uint8_t EVENT_H; /**< High bytes event */
volatile uint8_t EVENT_L; /**< Low bytes event */ volatile uint8_t EVENT_L; /**< Low bytes event */
volatile uint8_t MASK_H; /**< High byte event mask */ volatile uint8_t MASK_H; /**< High byte event mask */
volatile uint8_t MASK_L; /**< Low byte event mask */ volatile uint8_t MASK_L; /**< Low byte event mask */
volatile uint8_t MASK_SUM; /**< Summary mask */ volatile uint8_t MASK_SUM; /**< Summary mask */
volatile uint8_t EDGES; /**< Cable bit sampling time control */ volatile uint8_t EDGES; /**< Cable bit sampling time control */
volatile uint8_t DELAY; /**< Run time delay of system cable and signal strength */ volatile uint8_t DELAY; /**< Run time delay of system cable and signal strength */
volatile uint8_t VERSION; /**< Version */ volatile uint8_t VERSION; /**< Version */
volatile uint8_t resvd1; /**< Reserved 1 */ volatile uint8_t resvd1; /**< Reserved 1 */
volatile uint8_t ENC_ID2; /**< Encoder ID, byte 2 */ volatile uint8_t ENC_ID2; /**< Encoder ID, byte 2 */
volatile uint8_t ENC_ID1; /**< Encoder ID, byte 1 */ volatile uint8_t ENC_ID1; /**< Encoder ID, byte 1 */
volatile uint8_t ENC_ID0; /**< Encoder ID, byte 0 */ volatile uint8_t ENC_ID0; /**< Encoder ID, byte 0 */
volatile uint8_t POS4; /**< Fast position, byte 4 */ volatile uint8_t POS4; /**< Fast position, byte 4 */
volatile uint8_t POS3; /**< Fast position, byte 3 */ volatile uint8_t POS3; /**< Fast position, byte 3 */
volatile uint8_t POS2; /**< Fast position, byte 2 */ volatile uint8_t POS2; /**< Fast position, byte 2 */
volatile uint8_t POS1; /**< Fast position, byte 1 */ volatile uint8_t POS1; /**< Fast position, byte 1 */
volatile uint8_t POS0; /**< Fast position, byte 0 */ volatile uint8_t POS0; /**< Fast position, byte 0 */
volatile uint8_t VEL2; /**< Speed, byte 2 */ volatile uint8_t VEL2; /**< Speed, byte 2 */
volatile uint8_t VEL1; /**< Speed, byte 1 */ volatile uint8_t VEL1; /**< Speed, byte 1 */
volatile uint8_t VEL0; /**< Speed, byte 0 */ volatile uint8_t VEL0; /**< Speed, byte 0 */
volatile uint8_t resvd2; /**< Reserved 2 */ volatile uint8_t resvd2; /**< Reserved 2 */
volatile uint8_t VPOS4; /**< Safe position, byte 4 */ volatile uint8_t VPOS4; /**< Safe position, byte 4 */
volatile uint8_t VPOS3; /**< Safe position, byte 3 */ volatile uint8_t VPOS3; /**< Safe position, byte 3 */
volatile uint8_t VPOS2; /**< Safe position, byte 2 */ volatile uint8_t VPOS2; /**< Safe position, byte 2 */
volatile uint8_t VPOS1; /**< Safe position, byte 1 */ volatile uint8_t VPOS1; /**< Safe position, byte 1 */
volatile uint8_t VPOS0; /**< Safe position, byte 0 */ volatile uint8_t VPOS0; /**< Safe position, byte 0 */
volatile uint8_t VPOSCRC_H; /**< CRC of Safe position, byte 1 */ volatile uint8_t VPOSCRC_H; /**< CRC of Safe position, byte 1 */
volatile uint8_t VPOSCRC_L; /**< CRC of Safe position, byte 0 */ volatile uint8_t VPOSCRC_L; /**< CRC of Safe position, byte 0 */
volatile uint8_t PC_BUFFER0; /**< Parameters channel buffer, byte 0 */ volatile uint8_t PC_BUFFER0; /**< Parameters channel buffer, byte 0 */
volatile uint8_t PC_BUFFER1; /**< Parameters channel buffer, byte 1 */ volatile uint8_t PC_BUFFER1; /**< Parameters channel buffer, byte 1 */
volatile uint8_t PC_BUFFER2; /**< Parameters channel buffer, byte 2 */ volatile uint8_t PC_BUFFER2; /**< Parameters channel buffer, byte 2 */
volatile uint8_t PC_BUFFER3; /**< Parameters channel buffer, byte 3 */ volatile uint8_t PC_BUFFER3; /**< Parameters channel buffer, byte 3 */
volatile uint8_t PC_BUFFER4; /**< Parameters channel buffer, byte 4 */ volatile uint8_t PC_BUFFER4; /**< Parameters channel buffer, byte 4 */
volatile uint8_t PC_BUFFER5; /**< Parameters channel buffer, byte 5 */ volatile uint8_t PC_BUFFER5; /**< Parameters channel buffer, byte 5 */
volatile uint8_t PC_BUFFER6; /**< Parameters channel buffer, byte 6 */ volatile uint8_t PC_BUFFER6; /**< Parameters channel buffer, byte 6 */
volatile uint8_t PC_BUFFER7; /**< Parameters channel buffer, byte 7 */ volatile uint8_t PC_BUFFER7; /**< Parameters channel buffer, byte 7 */
volatile uint8_t PC_ADD_H; /**< Long message address, byte 1 */ volatile uint8_t PC_ADD_H; /**< Long message address, byte 1 */
volatile uint8_t PC_ADD_L; /**< Long message address, byte 0 */ volatile uint8_t PC_ADD_L; /**< Long message address, byte 0 */
volatile uint8_t PC_OFF_H; /**< Long message address offset, byte 1 */ volatile uint8_t PC_OFF_H; /**< Long message address offset, byte 1 */
volatile uint8_t PC_OFF_L; /**< Long message address offset, byte 0 */ volatile uint8_t PC_OFF_L; /**< Long message address offset, byte 0 */
volatile uint8_t PC_CTRL; /**< Parameters channel control */ volatile uint8_t PC_CTRL; /**< Parameters channel control */
volatile uint8_t PIPE_S; /**< Sensor hub channel status */ volatile uint8_t PIPE_S; /**< Sensor hub channel status */
volatile uint8_t PIPE_D; /**< Sensor hub channel data */ volatile uint8_t PIPE_D; /**< Sensor hub channel data */
volatile uint8_t PC_DATA; /**< Short message parameters channel data */ volatile uint8_t PC_DATA; /**< Short message parameters channel data */
volatile uint8_t resvd3; /**< Reserved 3 */ volatile uint8_t resvd3; /**< Reserved 3 */
volatile uint8_t resvd4; /**< Reserved 4 */ volatile uint8_t resvd4; /**< Reserved 4 */
volatile uint8_t resvd5; /**< Reserved 5 */ volatile uint8_t resvd5; /**< Reserved 5 */
volatile uint8_t resvd6; /**< Reserved 6 */ volatile uint8_t resvd6; /**< Reserved 6 */
volatile uint8_t resvd7; /**< Reserved 7 */ volatile uint8_t resvd7; /**< Reserved 7 */
volatile uint8_t resvd8; /**< Reserved 8 */ volatile uint8_t SAFE_CTRL; /**< Safe System Control */
volatile uint8_t SAFE_SUM; /**< Summarized slave status */ volatile uint8_t SAFE_SUM; /**< Summarized slave status */
volatile uint8_t S_PC_DATA; /**< Response of Short message parameters channel Read for safe1 channel */ volatile uint8_t S_PC_DATA; /**< Response of Short message parameters channel Read for safe1 channel */
volatile uint8_t ACC_ERR_CNT; /**< Fast position error counter */ volatile uint8_t ACC_ERR_CNT; /**< Fast position error counter */
volatile uint8_t MAXACC; /**< Fast position acceleration boundary */ volatile uint8_t MAXACC; /**< Fast position acceleration boundary */
volatile uint8_t MAXDEV_H; /**< Fast position estimator deviation high byte */ volatile uint8_t MAXDEV_H; /**< Fast position estimator deviation high byte */
volatile uint8_t MAXDEV_L; /**< Fast position estimator deviation low byte */ volatile uint8_t MAXDEV_L; /**< Fast position estimator deviation low byte */
volatile uint8_t resvd9; /**< Reserved 9 */ volatile uint8_t resvd9; /**< Reserved 9 */
volatile uint8_t EVENT_S; /**< Safe Events */ volatile uint8_t EVENT_S; /**< Safe Events */
volatile uint8_t resvd10; /**< Reserved 10 */ volatile uint8_t MASK_S; /**< Safe Event Mask */
volatile uint8_t DUMMY; /**< Dummy, no data */ volatile uint8_t DUMMY; /**< Dummy, no data */
volatile uint8_t SLAVE_REG_CTRL; /**< Short message control */ volatile uint8_t SLAVE_REG_CTRL; /**< Short message control */
volatile uint8_t ACC_ERR_CNT_THRES; /**< Fast position error counter threshold */ volatile uint8_t ACC_ERR_CNT_THRES; /**< Fast position error counter threshold */
volatile uint8_t MAXDEV_H_THRES; /**< Fast position estimator deviation high byte threshold */ volatile uint8_t MAXDEV_H_THRES; /**< Fast position estimator deviation high byte threshold */
volatile uint8_t MAXDEV_L_THRES; /**< Fast position estimator deviation low byte threshold */ volatile uint8_t MAXDEV_L_THRES; /**< Fast position estimator deviation low byte threshold */
/*Safe 2 Interface */ /*Safe 2 Interface */
volatile uint8_t version; volatile uint8_t VERSION2; /**< Version in Safe Channel 2 */
volatile uint8_t ENC2_ID; volatile uint8_t ENC2_ID; /**< Encoder ID in Safe Channel 2 */
volatile uint8_t STATUS2; volatile uint8_t STATUS2; /**< Safe Channel 2 Status */
volatile uint8_t VPOS24; volatile uint8_t VPOS24; /**< Safe Position 2, byte 4 */
volatile uint8_t VPOS23; volatile uint8_t VPOS23; /**< Safe Position 2, byte 3 */
volatile uint8_t VPOS22; volatile uint8_t VPOS22; /**< Safe Position 2, byte 2 */
volatile uint8_t VPOS21; volatile uint8_t VPOS21; /**< Safe Position 2, byte 1 */
volatile uint8_t VPOS20; volatile uint8_t VPOS20; /**< Safe Position 2, byte 0 */
volatile uint8_t VPOSCRC2_H; volatile uint8_t VPOSCRC2_H; /**< CRC of Safe Position 2, byte 1 */
volatile uint8_t VPOSCRC2_L; volatile uint8_t VPOSCRC2_L; /**< CRC of Safe Position 2, byte 0 */
volatile uint8_t DUMMY2; volatile uint8_t POSTX; /**< Position transmission status */
volatile uint8_t resvd10; /**< Reserved 10 */
/* Online Status*/ /* Online Status*/
volatile uint16_t ONLINE_STATUS_D; volatile uint8_t ONLINE_STATUS_D_H; /**< Online Status D, high byte*/
volatile uint16_t ONLINE_STATUS_1; volatile uint8_t ONLINE_STATUS_D_L; /**< Online Status D, low byte*/
volatile uint16_t ONLINE_STATUS_2; volatile uint8_t ONLINE_STATUS_1_H; /**< Online Status 1, high byte*/
volatile uint8_t ONLINE_STATUS_1_L; /**< Online Status 1, low byte*/
volatile uint8_t ONLINE_STATUS_2_H; /**< Online Status 2, high byte*/
volatile uint8_t ONLINE_STATUS_2_L; /**< Online Status 2, low byte*/
} HDSL_Interface; } HDSL_Interface;
/** @} */ /** @} */