diff --git a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c index b215fa1..47fe97f 100644 --- a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c +++ b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c @@ -523,8 +523,6 @@ void hdsl_init(void) hdsl_pruss_init(); HDSL_iep_init(gHdslHandleCh0); - DebugP_log("\r\nPress Enter to start application\n"); - DebugP_scanf("%d",&ES); ClockP_usleep(5000); if(CONFIG_HDSL0_MODE==0) { diff --git a/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c b/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c index b16e74b..6a1024d 100644 --- a/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c +++ b/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c @@ -452,8 +452,6 @@ void hdsl_init(void) HwiP_construct(&gPRUHwiObject, &hwiPrms); HDSL_iep_init(gHdslHandleCh0); - DebugP_log("\r\nPress Enter to start application\n"); - DebugP_scanf("%d",&ES); ClockP_usleep(5000); if(CONFIG_HDSL0_MODE==0) diff --git a/source/position_sense/hdsl/driver/hdsl_drv.c b/source/position_sense/hdsl/driver/hdsl_drv.c index 6ae86ef..dbde6a1 100644 --- a/source/position_sense/hdsl/driver/hdsl_drv.c +++ b/source/position_sense/hdsl/driver/hdsl_drv.c @@ -213,28 +213,28 @@ uint8_t HDSL_get_safe_events(HDSL_Handle hdslHandle) uint16_t HDSL_get_online_status_d(HDSL_Handle hdslHandle) { - uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_D; + uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_D_L | (hdslHandle->hdslInterface->ONLINE_STATUS_D_H << 8); return ureg; } uint16_t HDSL_get_online_status_1(HDSL_Handle hdslHandle) { - uint16_t ureg =hdslHandle->hdslInterface->ONLINE_STATUS_1; + uint16_t ureg =hdslHandle->hdslInterface->ONLINE_STATUS_1_L | (hdslHandle->hdslInterface->ONLINE_STATUS_1_H << 8); return ureg; } uint16_t HDSL_get_online_status_2(HDSL_Handle hdslHandle) { - uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_2; + uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_2_L | (hdslHandle->hdslInterface->ONLINE_STATUS_2_H << 8); return ureg; } + uint8_t HDSL_get_sum(HDSL_Handle hdslHandle) { uint8_t ureg = hdslHandle->hdslInterface->SAFE_SUM; return ureg; } - uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle) { return (uint8_t) (hdslHandle->hdslInterface->ACC_ERR_CNT & 0x1F); @@ -251,7 +251,7 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat uint64_t end; end = ClockP_getTimeUsec() + timeout; - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1) { if(ClockP_getTimeUsec() > end) { @@ -260,14 +260,14 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat } hdslHandle->hdslInterface->S_PC_DATA = data; hdslHandle->hdslInterface->SLAVE_REG_CTRL = addr; - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 0) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 0) { if(ClockP_getTimeUsec() > end) { return SystemP_TIMEOUT; } } - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1) { if(ClockP_getTimeUsec() > end) { @@ -279,11 +279,10 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *data, uint64_t timeout) { - uint64_t end; end = ClockP_getTimeUsec() + timeout; - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1) { if(ClockP_getTimeUsec() > end) { @@ -292,14 +291,14 @@ int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *dat } hdslHandle->hdslInterface->S_PC_DATA = 0; hdslHandle->hdslInterface->SLAVE_REG_CTRL = (addr | (1<<7)); - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 0) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 0) { if(ClockP_getTimeUsec() > end) { return SystemP_TIMEOUT; } } - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1) { if(ClockP_getTimeUsec() > end) { diff --git a/source/position_sense/hdsl/driver/hdsl_lut.c b/source/position_sense/hdsl/driver/hdsl_lut.c index 0e76a4f..44b23f3 100644 --- a/source/position_sense/hdsl/driver/hdsl_lut.c +++ b/source/position_sense/hdsl/driver/hdsl_lut.c @@ -1283,7 +1283,6 @@ static void hdsl_configure_register_if(HDSL_Handle hdslHandle) hdslHandle->hdslInterface->MAXDEV_L = 0x0; hdslHandle->hdslInterface->MAXDEV_H_THRES = 0xFF; hdslHandle->hdslInterface->MAXDEV_L_THRES = 0xFF; - hdslHandle->hdslInterface->VERSION = 0x41; hdslHandle->hdslInterface->ACC_ERR_CNT_THRES = 0x1F; HW_WR_REG32(((uint32_t)(hdslHandle->baseMemAddr) + 0xac), 0x4cc8115d); diff --git a/source/position_sense/hdsl/firmware/datalink.asm b/source/position_sense/hdsl/firmware/datalink.asm index 4339d52..6950c44 100644 --- a/source/position_sense/hdsl/firmware/datalink.asm +++ b/source/position_sense/hdsl/firmware/datalink.asm @@ -159,9 +159,9 @@ datalink_wait_vsynch: ldi r31.w0, PRU0_ARM_IRQ4 update_events_no_int0: ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 ; Set EVENT_FREL in EVENT_L register lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 set REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL @@ -172,9 +172,9 @@ update_events_no_int0: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int1: ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 ;-------------------------------------------------------------------------------------------------- ;State RX0-RX7 ldi LOOP_CNT.w2, 8 @@ -1074,11 +1074,11 @@ send_header_encode_sec_subblock_end: lsr REG_TMP0.b0, REG_FNC.b2, 2 or REG_FNC.b3, REG_FNC.b3, REG_TMP0.b0 lsl REG_FNC.b2, REG_FNC.b2, 6 - qbbc transport_layer_send_msg_done1, H_FRAME.flags, FLAG_NORMAL_FLOW .if $defined("HDSL_MULTICHANNEL") PUSH_FIFO_1_8x PUSH_FIFO_2_8x .endif +; transport_layer_send_msg sends short/long message (if pending) and also checks for QMLW/POS errors jmp transport_layer_send_msg transport_layer_send_msg_done1: .if $defined("HDSL_MULTICHANNEL") @@ -1402,7 +1402,6 @@ calculation_for_wait_done: mov REG_TMP11, RET_ADDR1 qbeq send_stuffing_no_stuffing, NUM_STUFFING, 0 ;check if we have stuffing - ;halt READ_CYCLCNT REG_TMP0 rsb REG_TMP2, REG_TMP0, (5*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4) mov REG_FNC.b3, NUM_STUFFING @@ -1560,11 +1559,11 @@ update_events_no_int2: update_events_no_int18: ; Set PRST bits in ONLINE_STATUS registers - lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST - sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 jmp datalink_reset ;-------------------------------------------------------------------------------------------------- ;Function: switch_clk (RET_ADDR1) @@ -1593,17 +1592,13 @@ switch_clk: ;input: ; REG_FNC.b0: value ;modifies: -; REG_TMP0, REG_FNC +; REG_TMP1, REG_FNC ;-------------------------------------------------------------------------------------------------- qm_add: .if 1 and QM, QM, 0x7f ;check if negative (bit 7 indicates there is a link -> check bit 6) qbbc qm_add_no_reset, QM, 6 - ; set EDIO28 - ;ldi32 REG_TMP1, 0x02e300 - ;sbbo ®_TMP1.b0, REG_TMP1, 0x13, 1 - halt ldi QM, 0 ;update MASTER_QM sbco &QM, MASTER_REGS_CONST, MASTER_QM, 1 @@ -1617,9 +1612,9 @@ qm_add_no_capping: qble qm_add_below_not_14, QM, 14 ; Defer the events register update to later ; Set EVENT_UPDATE_PENDING_QMLW to indicate a low QM value - lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 - set REG_TMP0.b0, REG_TMP0.w0, EVENT_UPDATE_PENDING_QMLW - sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + lbco ®_TMP1.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + set REG_TMP1.b0, REG_TMP1.b0, EVENT_UPDATE_PENDING_QMLW + sbco ®_TMP1.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 qm_add_below_not_14: or QM, QM, (1<<7) ;update MASTER_QM diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm index 57c2bf2..640a3a0 100644 --- a/source/position_sense/hdsl/firmware/datalink_init.asm +++ b/source/position_sense/hdsl/firmware/datalink_init.asm @@ -54,10 +54,10 @@ relocatable0: datalink_init_start: +datalink_reset: ;State RESET zero &r0, 124 ;send 2 times -datalink_reset: ;setup ICSS encoder peripheral for Hiperface DSL ldi DISPARITY, 0x00 @@ -70,6 +70,12 @@ datalink_reset: .else TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 .endif + +; set the VERSION and VERSION2 register + ldi REG_TMP0.b0, ICSS_FIRMWARE_RELEASE + sbco ®_TMP0.b0, MASTER_REGS_CONST, VERSION, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, VERSION2, 1 + zero &H_FRAME, (4*2) ;init transport layer here CALL transport_init @@ -85,31 +91,31 @@ datalink_reset: ;reset SAFE_CTRL register zero ®_TMP0.b0, 1 sbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_CTRL, 1 -; Write the fixed bits and reset PRST bits in ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2 +; Initialize ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2 ; In ONLINE_STATUS_D high, bit 2 is FIX0, bit 4 is FIX1 and bit 5 is FIX0 ; In ONLINE_STATUS_D low, bit 0 is FIX0 and bit 3 is FIX0 - lbco ®_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_D, 2 - ; clearing bits with fix0 and PRST bit - and REG_TMP0.w0, REG_TMP0.w0, ((~((1< add 1 to QM +;Note: QM_ADD uses REG_TMP1 QM_ADD 1 ;check for special character: K29.7 is sent in first byte of vertical channel if slave error occured qbne transport_on_v_frame_check_pos, VERT_H.b3, K29_7 @@ -152,11 +152,11 @@ check_for_slave_error_on_v_frame: ldi r31.w0, PRU0_ARM_IRQ4 update_events_no_int5: ; Set ONLINE_STATUS_1_VPOS in ONLINE_STATUS_1 register - set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_1_VPOS - sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1, 1 + set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_VPOS + sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1 qba transport_on_v_frame_exit transport_on_v_frame_check_pos: - sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1, 1 + sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1 lsl REG_TMP2, CHANNEL.ch_verth, 8 mov REG_TMP2.b0, VERT_L.b3 ;first V-Frame? -> update FAST POS with SAFE POS @@ -164,7 +164,11 @@ transport_on_v_frame_not_first: ;check for LAST FAST POS and SAFE POS mismatch lbco ®_TMP0.b0, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS sub REG_TMP1.w0, VERT_L.w2, REG_TMP0.w0 - suc REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2 + sub REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2 + qble no_sub_carry, VERT_L.w2, REG_TMP0.w0 +; if carry is needed, subtract 1 separately + sub REG_TMP1.w2, REG_TMP1.w2, 1 +no_sub_carry: mov REG_TMP2, REG_TMP1 ;check if diff is neg, qbbc transport_on_v_frame_diff_pos, REG_TMP2, 31 @@ -177,7 +181,6 @@ transport_on_v_frame_diff_pos: mov REG_TMP0.b2, REG_TMP0.b3 mov REG_TMP0.b3, REG_TMP0.b0 ;check if it is larger - lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 qbge transport_on_v_frame_dont_update_maxdev, REG_TMP2, REG_TMP0.w2 mov REG_TMP0.b0, REG_TMP2.b1 mov REG_TMP0.b1, REG_TMP2.b0 @@ -193,10 +196,10 @@ transport_on_v_frame_dont_update_maxdev: mov REG_TMP0.b2, REG_TMP0.b3 mov REG_TMP0.b3, REG_TMP0.b0 ;check if it is larger - lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 qbge transport_on_v_frame_dont_update_dte, REG_TMP2, REG_TMP0.w2 ; Set EVENT_DTE in ONLINE_STATUS_D register - set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE + lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 + set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_DTE ; Set EVENT_DTE in EVENT register lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 set REG_TMP0.w0, REG_TMP0.w0, EVENT_DTE @@ -208,8 +211,9 @@ transport_on_v_frame_dont_update_maxdev: update_events_no_int6: transport_on_v_frame_dont_update_dte: ; Clear EVENT_DTE in ONLINE_STATUS_D register - clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE - sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 + clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_DTE + sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 ;check for diff. is 0 -> estimate if not qbne transport_on_v_frame_estimate, REG_TMP1, 0 @@ -287,7 +291,7 @@ transport_on_v_frame_2: lbco ®_TMP1, MASTER_REGS_CONST, VPOS2_TEMP, 8 ; error checks for secondary channel - lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ; retrieve H_FRAME.flags from H_FRAME_FLAGS_TEMP lbco ®_TMP0.w2, MASTER_REGS_CONST, H_FRAME_FLAGS_TEMP, 2 ;channel 2 transmission error? @@ -298,24 +302,24 @@ transport_on_v_frame_2: qbeq check_for_slave_error_on_secondary_channel, REG_TMP0.w2, 0 ; set SCE2 bit in ONLINE_STATUS_2 set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 - sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 QM_SUB 6 transport_on_v_frame_dont_update_qm_secondary_channel: qba transport_on_v_frame_2_exit check_for_slave_error_on_secondary_channel: ; clear SCE2 bit in ONLINE_STATUS_2 clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 - sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ;CRC was correct -> add 1 to QM QM_ADD 1 ; NOTE: QM_ADD uses REG_TMP0. Loading REG_TMP0 again here. It can be optimized. - lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ;check for special character: K29.7 is sent in first byte of secondary vertical channel if slave error occured ; assumption: r21.b3 contains the first byte of secondary vertical channel qbne transport_on_v_frame_no_vpos2_error, REG_TMP2.b3, K29_7 ; set VPOS2 bit in ONLINE_STATUS_2 set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 - sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 qba transport_on_v_frame_vpos2_error_exit transport_on_v_frame_no_vpos2_error: clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 @@ -335,7 +339,7 @@ transport_on_v_frame_vpos2_error_exit: online_status_2_sum2_set: set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SUM2 online_status_2_sum2_not_set: - sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ; Store STATUS2, VPOS24, VPOS23 and VPOS22 @@ -366,9 +370,6 @@ transport_skip_vpos_update: ;check SUMMARY and MASK_SUM lbco ®_TMP1.b1, MASTER_REGS_CONST, MASK_SUM, 1 and REG_TMP1.b0, REG_TMP0.b0, REG_TMP1.b1 - lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 3 - clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM - clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM qbeq summary_no_int, REG_TMP1.b0, 0x00 ;set event and generate interrupt lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 @@ -389,10 +390,18 @@ update_events_no_int7: ; generate interrupt_s ldi r31.w0, PRU0_ARM_IRQ4 update_events_no_int17: +summary_no_int: + +; Update SUM and SSUM bits in ONLINE_STATUS registers + lbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM, 1 + lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 + clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM + clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM + qbeq online_status_sum_clear, REG_TMP0.b0, 0x00 set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM -summary_no_int: - sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 3 +online_status_sum_clear: + sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 ;restore REG_FNC.w0 content mov REG_FNC.w0, REG_TMP11.w1 @@ -472,9 +481,9 @@ transport_layer_recving_long_msg_crc: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int8: ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 ;check for crc error qbeq transport_layer_recving_long_msg_end, LONG_MSG_RECV.crc, 0 ; Set EVENT_ANS in EVENT register @@ -487,14 +496,14 @@ update_events_no_int8: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int9: ; Set ANS in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 transport_layer_recving_long_msg_end: ; Clear ANS in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 sub LONG_MSG_RECV.bits_left, LONG_MSG_RECV.bits_left, 4 qba transport_layer_recv_msg_end transport_layer_check_for_new_msg: @@ -551,9 +560,9 @@ transport_layer_received_short_msg: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int100: ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 qba transport_layer_recv_msg_check_for_nak transport_layer_short_msg_recv_read: ;received read answer @@ -575,9 +584,9 @@ transport_layer_short_msg_recv_read: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int10: ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 qba transport_layer_recv_msg_check_for_nak transport_layer_received_long_msg: @@ -623,9 +632,9 @@ transport_layer_received_long_msg_no_loffset_crc: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int11: ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 clr H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY transport_layer_received_long_msg_loffset_end: ;calculate CRC for already recevied bits @@ -646,9 +655,9 @@ transport_layer_received_long_msg_loffset_end: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int12: ; Set ANS in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 qba transport_layer_resend_msg_end transport_layer_recv_no_msg: ;reset flag @@ -670,9 +679,9 @@ transport_layer_recv_msg_check_for_nak: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int13: ; Set ANS in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 qba transport_layer_recv_msg_check_for_init_no_init transport_layer_recv_msg_check_for_nak_no_lnak: ;check for S_PAR_INIT @@ -696,17 +705,17 @@ update_events_no_int19: ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ4 update_events_no_int20: - lbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 + lbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) set REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_MIN-8) - sbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 + sbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3 qba transport_layer_min_update_done transport_layer_recv_msg_check_for_init_no_init: transport_layer_min_unset: - lbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 + lbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3 clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_MIN-8) - sbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 + sbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3 transport_layer_min_update_done: ;check for timeout - count only down when bitsleft = 0 amnd timeout != 0 qbne transport_layer_resend_msg_end, SHORT_MSG.bits_left, 0 @@ -736,6 +745,8 @@ transport_layer_recv_msg_end: ;---------------------------------------------------- transport_layer_send_msg: ;TODO: reduce cycles +; Skip message processing until one v-frame is complete + qbbc transport_layer_send_msg_end, H_FRAME.flags, FLAG_NORMAL_FLOW ldi SEND_PARA, M_PAR_IDLE ;check if we discard any messages and reset parameter channel lbco ®_TMP0.b0, MASTER_REGS_CONST, SYS_CTRL, 1 @@ -820,14 +831,10 @@ transport_layer_check_for_new_short_msg: lbco ®_TMP0.b0, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1 qbeq transport_layer_no_short_msg, REG_TMP0.b0, 0x3f -;set short msg channel to busy (reset EVENT_S_FRES) - lbco ®_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 - clr REG_TMP0.b2, REG_TMP0.b2, EVENT_S_FRES - sbco ®_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 -; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register - lbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 +; Clear ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register + lbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_FRES-8) - sbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + sbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 ;reset ldi REG_TMP0.b1, 0x3f sbco ®_TMP0.b1, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1 @@ -864,14 +871,10 @@ transport_layer_no_short_msg: sbco ®_TMP0.b0, MASTER_REGS_CONST, PC_CTRL, 1 ;set para channel to busy set H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY -;set long msg channel to busy (reset FREL) - lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 2 - clr REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL - sbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 2 -; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 +; Clear ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 lbco ®_TMP1, MASTER_REGS_CONST, PC_ADD_H, 4 mov SHORT_MSG.addr, REG_TMP1.b0 ldi SHORT_MSG.bits_left, 16 @@ -939,25 +942,27 @@ transport_layer_no_qmlw_event: ; Update QMLW bits in ONLINE_STATUS registers lbco ®_TMP0.b0, MASTER_REGS_CONST, MASTER_QM, 1 + and REG_TMP0.b0, REG_TMP0.b0, 0x7f +; Set QMLW if value is < 14 qble transport_layer_online_status_qm_not_low, REG_TMP0.b0, 14 ; Set QMLW bits - lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW - sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 qba transport_layer_online_status_qm_update_done transport_layer_online_status_qm_not_low: ; Clear QMLW bits - lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 clr REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW clr REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW clr REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW - sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 transport_layer_online_status_qm_update_done: ; update POS bits in ONLINE_STATUS_D and EVENT - lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 ; Check EVENT_UPDATE_PENDING_POS to process a pending POS set lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 qbbc transport_layer_no_pos_event, REG_TMP0.b0, EVENT_UPDATE_PENDING_POS @@ -979,7 +984,7 @@ update_events_no_int14: transport_layer_no_pos_event: clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_POS transport_layer_pos_update_done: - sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 jmp transport_layer_send_msg_done ;---------------------------------------------------- @@ -1073,7 +1078,6 @@ calc_speed_extend_acc1: sub DELTA_ACC0, REG_TMP0.w0, LAST_ACC mov LAST_ACC, REG_TMP0.w0 CALL1 calc_fastpos - RET ;restore return addr mov RET_ADDR0, REG_TMP11.w0 ; Moving the event and online register update during stuffing @@ -1108,8 +1112,14 @@ calc_speed_extend_acc0: transport_on_h_frame_exit: ;calculate rel. pos and store lbco ®_TMP0, MASTER_REGS_CONST, REL_POS0, 4 - add REG_TMP0.w0, REG_TMP0.w0, SPEED.w0 - adc REG_TMP0.w2, REG_TMP0.w2, SPEED.b2 +;sign extend speed to 32 bits and add it to REL_POS + mov REG_TMP1, SPEED + ldi REG_TMP1.b3, 0 + qbbc calc_relpos_extend_vel, SPEED, 23 + ldi REG_TMP1.b3, 0xff +calc_relpos_extend_vel: + add REG_TMP0.w0, REG_TMP0.w0, REG_TMP1.w0 + adc REG_TMP0.w2, REG_TMP0.w2, REG_TMP1.w2 sbco ®_TMP0, MASTER_REGS_CONST, REL_POS0, 4 ;store fast pos. and velocity mov REG_TMP0, FAST_POSH @@ -1205,21 +1215,32 @@ estimator_fpos: add FAST_POSL, VERT_L.b2, REG_TMP0.b0 adc FAST_POSH.b0, VERT_L.b3, REG_TMP0.b1 adc FAST_POSH.w1, VERT_H.w0, REG_TMP0.w2 +;sign extend relative position to 40 bits + qbbc estimator_fpos_add_relpos_positive, REG_TMP0, 31 + adc FAST_POSH.b3, VERT_H.b2, 0xFF + qba estimator_fpos_add_relpos_done +estimator_fpos_add_relpos_positive: adc FAST_POSH.b3, VERT_H.b2, 0 +estimator_fpos_add_relpos_done: qbne estimator_fpos_align_ph_not_2, ALIGN_PH, 2 ;vel = vel+acc/8 - qbbc estimator_fpos_acc_pos, LAST_ACC, 15 + ldi REG_TMP0.b2, 0 + qbbc estimator_fpos_acc_pos, LAST_ACC, 15 not REG_TMP0.w0, LAST_ACC add REG_TMP0.w0, REG_TMP0.w0, 1 lsr REG_TMP0.w0, REG_TMP0.w0, 3 not REG_TMP0.w0, REG_TMP0.w0 add REG_TMP0.w0, REG_TMP0.w0, 1 +;sign extend acceleration to 24 bit -> speed size + qbeq estimator_fpos_acc_sing_check_end, REG_TMP0.w0, 0 + or REG_TMP0.b2, REG_TMP0.b2, 0xFF qba estimator_fpos_acc_sing_check_end estimator_fpos_acc_pos: + mov REG_TMP0.w0, LAST_ACC lsr REG_TMP0.w0, REG_TMP0.w0, 3 estimator_fpos_acc_sing_check_end: add SPEED.w0, SPEED.w0, REG_TMP0.w0 - adc SPEED.b3, SPEED.b3, 0 + adc SPEED.b2, SPEED.b2, REG_TMP0.b2 estimator_fpos_align_ph_not_2: RET1 ;-------------------------------------------------------------------------------------------------- diff --git a/source/position_sense/hdsl/include/hdsl_drv.h b/source/position_sense/hdsl/include/hdsl_drv.h index 1310cc0..90e331e 100644 --- a/source/position_sense/hdsl/include/hdsl_drv.h +++ b/source/position_sense/hdsl/include/hdsl_drv.h @@ -92,6 +92,8 @@ extern "C" { /* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */ #define SYNCEVT_RTR_SYNC10_EVT 0x2C +#define ONLINE_STATUS_1_L_FRES (1<<0) + enum { MENU_SAFE_POSITION, MENU_QUALITY_MONITORING, @@ -126,90 +128,94 @@ typedef struct HDSL_Config_s *HDSL_Handle; * @{ */ typedef struct { - volatile uint8_t SYS_CTRL; /**< System control */ - volatile uint8_t SYNC_CTRL; /**< Synchronization control */ - volatile uint8_t resvd0; /**< Reserved 0 */ - volatile uint8_t MASTER_QM; /**< Quality monitoring */ - volatile uint8_t EVENT_H; /**< High bytes event */ - volatile uint8_t EVENT_L; /**< Low bytes event */ - volatile uint8_t MASK_H; /**< High byte event mask */ - volatile uint8_t MASK_L; /**< Low byte event mask */ - volatile uint8_t MASK_SUM; /**< Summary mask */ - volatile uint8_t EDGES; /**< Cable bit sampling time control */ - volatile uint8_t DELAY; /**< Run time delay of system cable and signal strength */ - volatile uint8_t VERSION; /**< Version */ - volatile uint8_t resvd1; /**< Reserved 1 */ - volatile uint8_t ENC_ID2; /**< Encoder ID, byte 2 */ - volatile uint8_t ENC_ID1; /**< Encoder ID, byte 1 */ - volatile uint8_t ENC_ID0; /**< Encoder ID, byte 0 */ - volatile uint8_t POS4; /**< Fast position, byte 4 */ - volatile uint8_t POS3; /**< Fast position, byte 3 */ - volatile uint8_t POS2; /**< Fast position, byte 2 */ - volatile uint8_t POS1; /**< Fast position, byte 1 */ - volatile uint8_t POS0; /**< Fast position, byte 0 */ - volatile uint8_t VEL2; /**< Speed, byte 2 */ - volatile uint8_t VEL1; /**< Speed, byte 1 */ - volatile uint8_t VEL0; /**< Speed, byte 0 */ - volatile uint8_t resvd2; /**< Reserved 2 */ - volatile uint8_t VPOS4; /**< Safe position, byte 4 */ - volatile uint8_t VPOS3; /**< Safe position, byte 3 */ - volatile uint8_t VPOS2; /**< Safe position, byte 2 */ - volatile uint8_t VPOS1; /**< Safe position, byte 1 */ - volatile uint8_t VPOS0; /**< Safe position, byte 0 */ - volatile uint8_t VPOSCRC_H; /**< CRC of Safe position, byte 1 */ - volatile uint8_t VPOSCRC_L; /**< CRC of Safe position, byte 0 */ - volatile uint8_t PC_BUFFER0; /**< Parameters channel buffer, byte 0 */ - volatile uint8_t PC_BUFFER1; /**< Parameters channel buffer, byte 1 */ - volatile uint8_t PC_BUFFER2; /**< Parameters channel buffer, byte 2 */ - volatile uint8_t PC_BUFFER3; /**< Parameters channel buffer, byte 3 */ - volatile uint8_t PC_BUFFER4; /**< Parameters channel buffer, byte 4 */ - volatile uint8_t PC_BUFFER5; /**< Parameters channel buffer, byte 5 */ - volatile uint8_t PC_BUFFER6; /**< Parameters channel buffer, byte 6 */ - volatile uint8_t PC_BUFFER7; /**< Parameters channel buffer, byte 7 */ - volatile uint8_t PC_ADD_H; /**< Long message address, byte 1 */ - volatile uint8_t PC_ADD_L; /**< Long message address, byte 0 */ - volatile uint8_t PC_OFF_H; /**< Long message address offset, byte 1 */ - volatile uint8_t PC_OFF_L; /**< Long message address offset, byte 0 */ - volatile uint8_t PC_CTRL; /**< Parameters channel control */ - volatile uint8_t PIPE_S; /**< Sensor hub channel status */ - volatile uint8_t PIPE_D; /**< Sensor hub channel data */ - volatile uint8_t PC_DATA; /**< Short message parameters channel data */ - volatile uint8_t resvd3; /**< Reserved 3 */ - volatile uint8_t resvd4; /**< Reserved 4 */ - volatile uint8_t resvd5; /**< Reserved 5 */ - volatile uint8_t resvd6; /**< Reserved 6 */ - volatile uint8_t resvd7; /**< Reserved 7 */ - volatile uint8_t resvd8; /**< Reserved 8 */ - volatile uint8_t SAFE_SUM; /**< Summarized slave status */ - volatile uint8_t S_PC_DATA; /**< Response of Short message parameters channel Read for safe1 channel */ - volatile uint8_t ACC_ERR_CNT; /**< Fast position error counter */ - volatile uint8_t MAXACC; /**< Fast position acceleration boundary */ - volatile uint8_t MAXDEV_H; /**< Fast position estimator deviation high byte */ - volatile uint8_t MAXDEV_L; /**< Fast position estimator deviation low byte */ - volatile uint8_t resvd9; /**< Reserved 9 */ - volatile uint8_t EVENT_S; /**< Safe Events */ - volatile uint8_t resvd10; /**< Reserved 10 */ - volatile uint8_t DUMMY; /**< Dummy, no data */ + volatile uint8_t SYS_CTRL; /**< System control */ + volatile uint8_t SYNC_CTRL; /**< Synchronization control */ + volatile uint8_t resvd0; /**< Reserved 0 */ + volatile uint8_t MASTER_QM; /**< Quality monitoring */ + volatile uint8_t EVENT_H; /**< High bytes event */ + volatile uint8_t EVENT_L; /**< Low bytes event */ + volatile uint8_t MASK_H; /**< High byte event mask */ + volatile uint8_t MASK_L; /**< Low byte event mask */ + volatile uint8_t MASK_SUM; /**< Summary mask */ + volatile uint8_t EDGES; /**< Cable bit sampling time control */ + volatile uint8_t DELAY; /**< Run time delay of system cable and signal strength */ + volatile uint8_t VERSION; /**< Version */ + volatile uint8_t resvd1; /**< Reserved 1 */ + volatile uint8_t ENC_ID2; /**< Encoder ID, byte 2 */ + volatile uint8_t ENC_ID1; /**< Encoder ID, byte 1 */ + volatile uint8_t ENC_ID0; /**< Encoder ID, byte 0 */ + volatile uint8_t POS4; /**< Fast position, byte 4 */ + volatile uint8_t POS3; /**< Fast position, byte 3 */ + volatile uint8_t POS2; /**< Fast position, byte 2 */ + volatile uint8_t POS1; /**< Fast position, byte 1 */ + volatile uint8_t POS0; /**< Fast position, byte 0 */ + volatile uint8_t VEL2; /**< Speed, byte 2 */ + volatile uint8_t VEL1; /**< Speed, byte 1 */ + volatile uint8_t VEL0; /**< Speed, byte 0 */ + volatile uint8_t resvd2; /**< Reserved 2 */ + volatile uint8_t VPOS4; /**< Safe position, byte 4 */ + volatile uint8_t VPOS3; /**< Safe position, byte 3 */ + volatile uint8_t VPOS2; /**< Safe position, byte 2 */ + volatile uint8_t VPOS1; /**< Safe position, byte 1 */ + volatile uint8_t VPOS0; /**< Safe position, byte 0 */ + volatile uint8_t VPOSCRC_H; /**< CRC of Safe position, byte 1 */ + volatile uint8_t VPOSCRC_L; /**< CRC of Safe position, byte 0 */ + volatile uint8_t PC_BUFFER0; /**< Parameters channel buffer, byte 0 */ + volatile uint8_t PC_BUFFER1; /**< Parameters channel buffer, byte 1 */ + volatile uint8_t PC_BUFFER2; /**< Parameters channel buffer, byte 2 */ + volatile uint8_t PC_BUFFER3; /**< Parameters channel buffer, byte 3 */ + volatile uint8_t PC_BUFFER4; /**< Parameters channel buffer, byte 4 */ + volatile uint8_t PC_BUFFER5; /**< Parameters channel buffer, byte 5 */ + volatile uint8_t PC_BUFFER6; /**< Parameters channel buffer, byte 6 */ + volatile uint8_t PC_BUFFER7; /**< Parameters channel buffer, byte 7 */ + volatile uint8_t PC_ADD_H; /**< Long message address, byte 1 */ + volatile uint8_t PC_ADD_L; /**< Long message address, byte 0 */ + volatile uint8_t PC_OFF_H; /**< Long message address offset, byte 1 */ + volatile uint8_t PC_OFF_L; /**< Long message address offset, byte 0 */ + volatile uint8_t PC_CTRL; /**< Parameters channel control */ + volatile uint8_t PIPE_S; /**< Sensor hub channel status */ + volatile uint8_t PIPE_D; /**< Sensor hub channel data */ + volatile uint8_t PC_DATA; /**< Short message parameters channel data */ + volatile uint8_t resvd3; /**< Reserved 3 */ + volatile uint8_t resvd4; /**< Reserved 4 */ + volatile uint8_t resvd5; /**< Reserved 5 */ + volatile uint8_t resvd6; /**< Reserved 6 */ + volatile uint8_t resvd7; /**< Reserved 7 */ + volatile uint8_t SAFE_CTRL; /**< Safe System Control */ + volatile uint8_t SAFE_SUM; /**< Summarized slave status */ + volatile uint8_t S_PC_DATA; /**< Response of Short message parameters channel Read for safe1 channel */ + volatile uint8_t ACC_ERR_CNT; /**< Fast position error counter */ + volatile uint8_t MAXACC; /**< Fast position acceleration boundary */ + volatile uint8_t MAXDEV_H; /**< Fast position estimator deviation high byte */ + volatile uint8_t MAXDEV_L; /**< Fast position estimator deviation low byte */ + volatile uint8_t resvd9; /**< Reserved 9 */ + volatile uint8_t EVENT_S; /**< Safe Events */ + volatile uint8_t MASK_S; /**< Safe Event Mask */ + volatile uint8_t DUMMY; /**< Dummy, no data */ volatile uint8_t SLAVE_REG_CTRL; /**< Short message control */ volatile uint8_t ACC_ERR_CNT_THRES; /**< Fast position error counter threshold */ volatile uint8_t MAXDEV_H_THRES; /**< Fast position estimator deviation high byte threshold */ volatile uint8_t MAXDEV_L_THRES; /**< Fast position estimator deviation low byte threshold */ /*Safe 2 Interface */ - volatile uint8_t version; - volatile uint8_t ENC2_ID; - volatile uint8_t STATUS2; - volatile uint8_t VPOS24; - volatile uint8_t VPOS23; - volatile uint8_t VPOS22; - volatile uint8_t VPOS21; - volatile uint8_t VPOS20; - volatile uint8_t VPOSCRC2_H; - volatile uint8_t VPOSCRC2_L; - volatile uint8_t DUMMY2; + volatile uint8_t VERSION2; /**< Version in Safe Channel 2 */ + volatile uint8_t ENC2_ID; /**< Encoder ID in Safe Channel 2 */ + volatile uint8_t STATUS2; /**< Safe Channel 2 Status */ + volatile uint8_t VPOS24; /**< Safe Position 2, byte 4 */ + volatile uint8_t VPOS23; /**< Safe Position 2, byte 3 */ + volatile uint8_t VPOS22; /**< Safe Position 2, byte 2 */ + volatile uint8_t VPOS21; /**< Safe Position 2, byte 1 */ + volatile uint8_t VPOS20; /**< Safe Position 2, byte 0 */ + volatile uint8_t VPOSCRC2_H; /**< CRC of Safe Position 2, byte 1 */ + volatile uint8_t VPOSCRC2_L; /**< CRC of Safe Position 2, byte 0 */ + volatile uint8_t POSTX; /**< Position transmission status */ + volatile uint8_t resvd10; /**< Reserved 10 */ /* Online Status*/ - volatile uint16_t ONLINE_STATUS_D; - volatile uint16_t ONLINE_STATUS_1; - volatile uint16_t ONLINE_STATUS_2; + volatile uint8_t ONLINE_STATUS_D_H; /**< Online Status D, high byte*/ + volatile uint8_t ONLINE_STATUS_D_L; /**< Online Status D, low byte*/ + volatile uint8_t ONLINE_STATUS_1_H; /**< Online Status 1, high byte*/ + volatile uint8_t ONLINE_STATUS_1_L; /**< Online Status 1, low byte*/ + volatile uint8_t ONLINE_STATUS_2_H; /**< Online Status 2, high byte*/ + volatile uint8_t ONLINE_STATUS_2_L; /**< Online Status 2, low byte*/ } HDSL_Interface; /** @} */