From 9ac546cfd9d6e042c3f662bf88105632a3d2cb50 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Mon, 21 Aug 2023 11:28:10 +0530 Subject: [PATCH 01/11] am64x/am243x: hdsl: Remove the scanf waiting for Enter during initialization Fixes: PINDSW-6517 Signed-off-by: Dhaval Khandla --- examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c | 2 -- .../hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c index b215fa1..47fe97f 100644 --- a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c +++ b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c @@ -523,8 +523,6 @@ void hdsl_init(void) hdsl_pruss_init(); HDSL_iep_init(gHdslHandleCh0); - DebugP_log("\r\nPress Enter to start application\n"); - DebugP_scanf("%d",&ES); ClockP_usleep(5000); if(CONFIG_HDSL0_MODE==0) { diff --git a/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c b/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c index b16e74b..6a1024d 100644 --- a/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c +++ b/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c @@ -452,8 +452,6 @@ void hdsl_init(void) HwiP_construct(&gPRUHwiObject, &hwiPrms); HDSL_iep_init(gHdslHandleCh0); - DebugP_log("\r\nPress Enter to start application\n"); - DebugP_scanf("%d",&ES); ClockP_usleep(5000); if(CONFIG_HDSL0_MODE==0) From 9ce9770c05000df91f67e199b0a3cb2f167efbfb Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Mon, 21 Aug 2023 11:43:53 +0530 Subject: [PATCH 02/11] am64x/am243x: hdsl: Update the register memory map - Fix the address of ONLINE STATUS bytes by adding a reserved byte - Create separate entries for low and high bytes of ONLINE STATUS registers - Add SAFE_CTRL and POSTX registers - Use high and low addresses in firmware for ONLINE STATUS registers Fixes: PINDSW-6489 Signed-off-by: Dhaval Khandla --- source/position_sense/hdsl/driver/hdsl_drv.c | 21 ++- .../position_sense/hdsl/firmware/datalink.asm | 12 +- .../hdsl/firmware/datalink_init.asm | 26 +-- .../firmware/hdsl_master_icssg_300_mhz_bin.h | 6 +- .../hdsl/firmware/hdsl_master_icssg_bin.h | 6 +- .../hdsl_master_icssg_multichannel_ch0_bin.h | 6 +- .../hdsl_master_icssg_multichannel_ch1_bin.h | 6 +- .../firmware/hdsl_master_icssg_sync_bin.h | 8 +- .../position_sense/hdsl/firmware/memory.inc | 9 +- .../hdsl/firmware/transport.asm | 90 +++++----- source/position_sense/hdsl/include/hdsl_drv.h | 162 +++++++++--------- 11 files changed, 180 insertions(+), 172 deletions(-) diff --git a/source/position_sense/hdsl/driver/hdsl_drv.c b/source/position_sense/hdsl/driver/hdsl_drv.c index 6ae86ef..dbde6a1 100644 --- a/source/position_sense/hdsl/driver/hdsl_drv.c +++ b/source/position_sense/hdsl/driver/hdsl_drv.c @@ -213,28 +213,28 @@ uint8_t HDSL_get_safe_events(HDSL_Handle hdslHandle) uint16_t HDSL_get_online_status_d(HDSL_Handle hdslHandle) { - uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_D; + uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_D_L | (hdslHandle->hdslInterface->ONLINE_STATUS_D_H << 8); return ureg; } uint16_t HDSL_get_online_status_1(HDSL_Handle hdslHandle) { - uint16_t ureg =hdslHandle->hdslInterface->ONLINE_STATUS_1; + uint16_t ureg =hdslHandle->hdslInterface->ONLINE_STATUS_1_L | (hdslHandle->hdslInterface->ONLINE_STATUS_1_H << 8); return ureg; } uint16_t HDSL_get_online_status_2(HDSL_Handle hdslHandle) { - uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_2; + uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_2_L | (hdslHandle->hdslInterface->ONLINE_STATUS_2_H << 8); return ureg; } + uint8_t HDSL_get_sum(HDSL_Handle hdslHandle) { uint8_t ureg = hdslHandle->hdslInterface->SAFE_SUM; return ureg; } - uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle) { return (uint8_t) (hdslHandle->hdslInterface->ACC_ERR_CNT & 0x1F); @@ -251,7 +251,7 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat uint64_t end; end = ClockP_getTimeUsec() + timeout; - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1) { if(ClockP_getTimeUsec() > end) { @@ -260,14 +260,14 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat } hdslHandle->hdslInterface->S_PC_DATA = data; hdslHandle->hdslInterface->SLAVE_REG_CTRL = addr; - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 0) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 0) { if(ClockP_getTimeUsec() > end) { return SystemP_TIMEOUT; } } - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1) { if(ClockP_getTimeUsec() > end) { @@ -279,11 +279,10 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *data, uint64_t timeout) { - uint64_t end; end = ClockP_getTimeUsec() + timeout; - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1) { if(ClockP_getTimeUsec() > end) { @@ -292,14 +291,14 @@ int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *dat } hdslHandle->hdslInterface->S_PC_DATA = 0; hdslHandle->hdslInterface->SLAVE_REG_CTRL = (addr | (1<<7)); - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 0) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 0) { if(ClockP_getTimeUsec() > end) { return SystemP_TIMEOUT; } } - while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + while((hdslHandle->hdslInterface->ONLINE_STATUS_1_L & ONLINE_STATUS_1_L_FRES) != 1) { if(ClockP_getTimeUsec() > end) { diff --git a/source/position_sense/hdsl/firmware/datalink.asm b/source/position_sense/hdsl/firmware/datalink.asm index 4339d52..a92f368 100644 --- a/source/position_sense/hdsl/firmware/datalink.asm +++ b/source/position_sense/hdsl/firmware/datalink.asm @@ -159,9 +159,9 @@ datalink_wait_vsynch: ldi r31.w0, PRU0_ARM_IRQ4 update_events_no_int0: ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 ; Set EVENT_FREL in EVENT_L register lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 set REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL @@ -172,9 +172,9 @@ update_events_no_int0: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int1: ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 ;-------------------------------------------------------------------------------------------------- ;State RX0-RX7 ldi LOOP_CNT.w2, 8 @@ -1560,11 +1560,11 @@ update_events_no_int2: update_events_no_int18: ; Set PRST bits in ONLINE_STATUS registers - lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST - sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 jmp datalink_reset ;-------------------------------------------------------------------------------------------------- ;Function: switch_clk (RET_ADDR1) diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm index 57c2bf2..83426eb 100644 --- a/source/position_sense/hdsl/firmware/datalink_init.asm +++ b/source/position_sense/hdsl/firmware/datalink_init.asm @@ -85,31 +85,31 @@ datalink_reset: ;reset SAFE_CTRL register zero ®_TMP0.b0, 1 sbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_CTRL, 1 -; Write the fixed bits and reset PRST bits in ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2 +; Initialize ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2 ; In ONLINE_STATUS_D high, bit 2 is FIX0, bit 4 is FIX1 and bit 5 is FIX0 ; In ONLINE_STATUS_D low, bit 0 is FIX0 and bit 3 is FIX0 - lbco ®_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_D, 2 - ; clearing bits with fix0 and PRST bit - and REG_TMP0.w0, REG_TMP0.w0, ((~((1< update FAST POS with SAFE POS @@ -177,7 +177,7 @@ transport_on_v_frame_diff_pos: mov REG_TMP0.b2, REG_TMP0.b3 mov REG_TMP0.b3, REG_TMP0.b0 ;check if it is larger - lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 qbge transport_on_v_frame_dont_update_maxdev, REG_TMP2, REG_TMP0.w2 mov REG_TMP0.b0, REG_TMP2.b1 mov REG_TMP0.b1, REG_TMP2.b0 @@ -193,7 +193,7 @@ transport_on_v_frame_dont_update_maxdev: mov REG_TMP0.b2, REG_TMP0.b3 mov REG_TMP0.b3, REG_TMP0.b0 ;check if it is larger - lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 qbge transport_on_v_frame_dont_update_dte, REG_TMP2, REG_TMP0.w2 ; Set EVENT_DTE in ONLINE_STATUS_D register set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE @@ -209,7 +209,7 @@ update_events_no_int6: transport_on_v_frame_dont_update_dte: ; Clear EVENT_DTE in ONLINE_STATUS_D register clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE - sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 ;check for diff. is 0 -> estimate if not qbne transport_on_v_frame_estimate, REG_TMP1, 0 @@ -287,7 +287,7 @@ transport_on_v_frame_2: lbco ®_TMP1, MASTER_REGS_CONST, VPOS2_TEMP, 8 ; error checks for secondary channel - lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ; retrieve H_FRAME.flags from H_FRAME_FLAGS_TEMP lbco ®_TMP0.w2, MASTER_REGS_CONST, H_FRAME_FLAGS_TEMP, 2 ;channel 2 transmission error? @@ -298,24 +298,24 @@ transport_on_v_frame_2: qbeq check_for_slave_error_on_secondary_channel, REG_TMP0.w2, 0 ; set SCE2 bit in ONLINE_STATUS_2 set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 - sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 QM_SUB 6 transport_on_v_frame_dont_update_qm_secondary_channel: qba transport_on_v_frame_2_exit check_for_slave_error_on_secondary_channel: ; clear SCE2 bit in ONLINE_STATUS_2 clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 - sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ;CRC was correct -> add 1 to QM QM_ADD 1 ; NOTE: QM_ADD uses REG_TMP0. Loading REG_TMP0 again here. It can be optimized. - lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ;check for special character: K29.7 is sent in first byte of secondary vertical channel if slave error occured ; assumption: r21.b3 contains the first byte of secondary vertical channel qbne transport_on_v_frame_no_vpos2_error, REG_TMP2.b3, K29_7 ; set VPOS2 bit in ONLINE_STATUS_2 set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 - sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 qba transport_on_v_frame_vpos2_error_exit transport_on_v_frame_no_vpos2_error: clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 @@ -335,7 +335,7 @@ transport_on_v_frame_vpos2_error_exit: online_status_2_sum2_set: set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SUM2 online_status_2_sum2_not_set: - sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ; Store STATUS2, VPOS24, VPOS23 and VPOS22 @@ -366,7 +366,7 @@ transport_skip_vpos_update: ;check SUMMARY and MASK_SUM lbco ®_TMP1.b1, MASTER_REGS_CONST, MASK_SUM, 1 and REG_TMP1.b0, REG_TMP0.b0, REG_TMP1.b1 - lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 3 + lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM qbeq summary_no_int, REG_TMP1.b0, 0x00 @@ -392,7 +392,7 @@ update_events_no_int17: set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM summary_no_int: - sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 3 + sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 ;restore REG_FNC.w0 content mov REG_FNC.w0, REG_TMP11.w1 @@ -472,9 +472,9 @@ transport_layer_recving_long_msg_crc: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int8: ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 ;check for crc error qbeq transport_layer_recving_long_msg_end, LONG_MSG_RECV.crc, 0 ; Set EVENT_ANS in EVENT register @@ -487,14 +487,14 @@ update_events_no_int8: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int9: ; Set ANS in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 transport_layer_recving_long_msg_end: ; Clear ANS in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 sub LONG_MSG_RECV.bits_left, LONG_MSG_RECV.bits_left, 4 qba transport_layer_recv_msg_end transport_layer_check_for_new_msg: @@ -551,9 +551,9 @@ transport_layer_received_short_msg: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int100: ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 qba transport_layer_recv_msg_check_for_nak transport_layer_short_msg_recv_read: ;received read answer @@ -575,9 +575,9 @@ transport_layer_short_msg_recv_read: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int10: ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 qba transport_layer_recv_msg_check_for_nak transport_layer_received_long_msg: @@ -623,9 +623,9 @@ transport_layer_received_long_msg_no_loffset_crc: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int11: ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 clr H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY transport_layer_received_long_msg_loffset_end: ;calculate CRC for already recevied bits @@ -646,9 +646,9 @@ transport_layer_received_long_msg_loffset_end: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int12: ; Set ANS in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 qba transport_layer_resend_msg_end transport_layer_recv_no_msg: ;reset flag @@ -670,9 +670,9 @@ transport_layer_recv_msg_check_for_nak: ldi r31.w0, PRU0_ARM_IRQ update_events_no_int13: ; Set ANS in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 qba transport_layer_recv_msg_check_for_init_no_init transport_layer_recv_msg_check_for_nak_no_lnak: ;check for S_PAR_INIT @@ -696,17 +696,17 @@ update_events_no_int19: ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ4 update_events_no_int20: - lbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 + lbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3 set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) set REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_MIN-8) - sbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 + sbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3 qba transport_layer_min_update_done transport_layer_recv_msg_check_for_init_no_init: transport_layer_min_unset: - lbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 + lbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3 clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_MIN-8) - sbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 3 + sbco ®_TMP0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 3 transport_layer_min_update_done: ;check for timeout - count only down when bitsleft = 0 amnd timeout != 0 qbne transport_layer_resend_msg_end, SHORT_MSG.bits_left, 0 @@ -825,9 +825,9 @@ transport_layer_check_for_new_short_msg: clr REG_TMP0.b2, REG_TMP0.b2, EVENT_S_FRES sbco ®_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 ; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register - lbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + lbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_FRES-8) - sbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + sbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 ;reset ldi REG_TMP0.b1, 0x3f sbco ®_TMP0.b1, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1 @@ -869,9 +869,9 @@ transport_layer_no_short_msg: clr REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL sbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 2 ; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register - lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) - sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 lbco ®_TMP1, MASTER_REGS_CONST, PC_ADD_H, 4 mov SHORT_MSG.addr, REG_TMP1.b0 ldi SHORT_MSG.bits_left, 16 @@ -941,23 +941,23 @@ transport_layer_no_qmlw_event: lbco ®_TMP0.b0, MASTER_REGS_CONST, MASTER_QM, 1 qble transport_layer_online_status_qm_not_low, REG_TMP0.b0, 14 ; Set QMLW bits - lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW - sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 qba transport_layer_online_status_qm_update_done transport_layer_online_status_qm_not_low: ; Clear QMLW bits - lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 clr REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW clr REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW clr REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW - sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 transport_layer_online_status_qm_update_done: ; update POS bits in ONLINE_STATUS_D and EVENT - lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 ; Check EVENT_UPDATE_PENDING_POS to process a pending POS set lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 qbbc transport_layer_no_pos_event, REG_TMP0.b0, EVENT_UPDATE_PENDING_POS @@ -979,7 +979,7 @@ update_events_no_int14: transport_layer_no_pos_event: clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_POS transport_layer_pos_update_done: - sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 jmp transport_layer_send_msg_done ;---------------------------------------------------- diff --git a/source/position_sense/hdsl/include/hdsl_drv.h b/source/position_sense/hdsl/include/hdsl_drv.h index 1310cc0..90e331e 100644 --- a/source/position_sense/hdsl/include/hdsl_drv.h +++ b/source/position_sense/hdsl/include/hdsl_drv.h @@ -92,6 +92,8 @@ extern "C" { /* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */ #define SYNCEVT_RTR_SYNC10_EVT 0x2C +#define ONLINE_STATUS_1_L_FRES (1<<0) + enum { MENU_SAFE_POSITION, MENU_QUALITY_MONITORING, @@ -126,90 +128,94 @@ typedef struct HDSL_Config_s *HDSL_Handle; * @{ */ typedef struct { - volatile uint8_t SYS_CTRL; /**< System control */ - volatile uint8_t SYNC_CTRL; /**< Synchronization control */ - volatile uint8_t resvd0; /**< Reserved 0 */ - volatile uint8_t MASTER_QM; /**< Quality monitoring */ - volatile uint8_t EVENT_H; /**< High bytes event */ - volatile uint8_t EVENT_L; /**< Low bytes event */ - volatile uint8_t MASK_H; /**< High byte event mask */ - volatile uint8_t MASK_L; /**< Low byte event mask */ - volatile uint8_t MASK_SUM; /**< Summary mask */ - volatile uint8_t EDGES; /**< Cable bit sampling time control */ - volatile uint8_t DELAY; /**< Run time delay of system cable and signal strength */ - volatile uint8_t VERSION; /**< Version */ - volatile uint8_t resvd1; /**< Reserved 1 */ - volatile uint8_t ENC_ID2; /**< Encoder ID, byte 2 */ - volatile uint8_t ENC_ID1; /**< Encoder ID, byte 1 */ - volatile uint8_t ENC_ID0; /**< Encoder ID, byte 0 */ - volatile uint8_t POS4; /**< Fast position, byte 4 */ - volatile uint8_t POS3; /**< Fast position, byte 3 */ - volatile uint8_t POS2; /**< Fast position, byte 2 */ - volatile uint8_t POS1; /**< Fast position, byte 1 */ - volatile uint8_t POS0; /**< Fast position, byte 0 */ - volatile uint8_t VEL2; /**< Speed, byte 2 */ - volatile uint8_t VEL1; /**< Speed, byte 1 */ - volatile uint8_t VEL0; /**< Speed, byte 0 */ - volatile uint8_t resvd2; /**< Reserved 2 */ - volatile uint8_t VPOS4; /**< Safe position, byte 4 */ - volatile uint8_t VPOS3; /**< Safe position, byte 3 */ - volatile uint8_t VPOS2; /**< Safe position, byte 2 */ - volatile uint8_t VPOS1; /**< Safe position, byte 1 */ - volatile uint8_t VPOS0; /**< Safe position, byte 0 */ - volatile uint8_t VPOSCRC_H; /**< CRC of Safe position, byte 1 */ - volatile uint8_t VPOSCRC_L; /**< CRC of Safe position, byte 0 */ - volatile uint8_t PC_BUFFER0; /**< Parameters channel buffer, byte 0 */ - volatile uint8_t PC_BUFFER1; /**< Parameters channel buffer, byte 1 */ - volatile uint8_t PC_BUFFER2; /**< Parameters channel buffer, byte 2 */ - volatile uint8_t PC_BUFFER3; /**< Parameters channel buffer, byte 3 */ - volatile uint8_t PC_BUFFER4; /**< Parameters channel buffer, byte 4 */ - volatile uint8_t PC_BUFFER5; /**< Parameters channel buffer, byte 5 */ - volatile uint8_t PC_BUFFER6; /**< Parameters channel buffer, byte 6 */ - volatile uint8_t PC_BUFFER7; /**< Parameters channel buffer, byte 7 */ - volatile uint8_t PC_ADD_H; /**< Long message address, byte 1 */ - volatile uint8_t PC_ADD_L; /**< Long message address, byte 0 */ - volatile uint8_t PC_OFF_H; /**< Long message address offset, byte 1 */ - volatile uint8_t PC_OFF_L; /**< Long message address offset, byte 0 */ - volatile uint8_t PC_CTRL; /**< Parameters channel control */ - volatile uint8_t PIPE_S; /**< Sensor hub channel status */ - volatile uint8_t PIPE_D; /**< Sensor hub channel data */ - volatile uint8_t PC_DATA; /**< Short message parameters channel data */ - volatile uint8_t resvd3; /**< Reserved 3 */ - volatile uint8_t resvd4; /**< Reserved 4 */ - volatile uint8_t resvd5; /**< Reserved 5 */ - volatile uint8_t resvd6; /**< Reserved 6 */ - volatile uint8_t resvd7; /**< Reserved 7 */ - volatile uint8_t resvd8; /**< Reserved 8 */ - volatile uint8_t SAFE_SUM; /**< Summarized slave status */ - volatile uint8_t S_PC_DATA; /**< Response of Short message parameters channel Read for safe1 channel */ - volatile uint8_t ACC_ERR_CNT; /**< Fast position error counter */ - volatile uint8_t MAXACC; /**< Fast position acceleration boundary */ - volatile uint8_t MAXDEV_H; /**< Fast position estimator deviation high byte */ - volatile uint8_t MAXDEV_L; /**< Fast position estimator deviation low byte */ - volatile uint8_t resvd9; /**< Reserved 9 */ - volatile uint8_t EVENT_S; /**< Safe Events */ - volatile uint8_t resvd10; /**< Reserved 10 */ - volatile uint8_t DUMMY; /**< Dummy, no data */ + volatile uint8_t SYS_CTRL; /**< System control */ + volatile uint8_t SYNC_CTRL; /**< Synchronization control */ + volatile uint8_t resvd0; /**< Reserved 0 */ + volatile uint8_t MASTER_QM; /**< Quality monitoring */ + volatile uint8_t EVENT_H; /**< High bytes event */ + volatile uint8_t EVENT_L; /**< Low bytes event */ + volatile uint8_t MASK_H; /**< High byte event mask */ + volatile uint8_t MASK_L; /**< Low byte event mask */ + volatile uint8_t MASK_SUM; /**< Summary mask */ + volatile uint8_t EDGES; /**< Cable bit sampling time control */ + volatile uint8_t DELAY; /**< Run time delay of system cable and signal strength */ + volatile uint8_t VERSION; /**< Version */ + volatile uint8_t resvd1; /**< Reserved 1 */ + volatile uint8_t ENC_ID2; /**< Encoder ID, byte 2 */ + volatile uint8_t ENC_ID1; /**< Encoder ID, byte 1 */ + volatile uint8_t ENC_ID0; /**< Encoder ID, byte 0 */ + volatile uint8_t POS4; /**< Fast position, byte 4 */ + volatile uint8_t POS3; /**< Fast position, byte 3 */ + volatile uint8_t POS2; /**< Fast position, byte 2 */ + volatile uint8_t POS1; /**< Fast position, byte 1 */ + volatile uint8_t POS0; /**< Fast position, byte 0 */ + volatile uint8_t VEL2; /**< Speed, byte 2 */ + volatile uint8_t VEL1; /**< Speed, byte 1 */ + volatile uint8_t VEL0; /**< Speed, byte 0 */ + volatile uint8_t resvd2; /**< Reserved 2 */ + volatile uint8_t VPOS4; /**< Safe position, byte 4 */ + volatile uint8_t VPOS3; /**< Safe position, byte 3 */ + volatile uint8_t VPOS2; /**< Safe position, byte 2 */ + volatile uint8_t VPOS1; /**< Safe position, byte 1 */ + volatile uint8_t VPOS0; /**< Safe position, byte 0 */ + volatile uint8_t VPOSCRC_H; /**< CRC of Safe position, byte 1 */ + volatile uint8_t VPOSCRC_L; /**< CRC of Safe position, byte 0 */ + volatile uint8_t PC_BUFFER0; /**< Parameters channel buffer, byte 0 */ + volatile uint8_t PC_BUFFER1; /**< Parameters channel buffer, byte 1 */ + volatile uint8_t PC_BUFFER2; /**< Parameters channel buffer, byte 2 */ + volatile uint8_t PC_BUFFER3; /**< Parameters channel buffer, byte 3 */ + volatile uint8_t PC_BUFFER4; /**< Parameters channel buffer, byte 4 */ + volatile uint8_t PC_BUFFER5; /**< Parameters channel buffer, byte 5 */ + volatile uint8_t PC_BUFFER6; /**< Parameters channel buffer, byte 6 */ + volatile uint8_t PC_BUFFER7; /**< Parameters channel buffer, byte 7 */ + volatile uint8_t PC_ADD_H; /**< Long message address, byte 1 */ + volatile uint8_t PC_ADD_L; /**< Long message address, byte 0 */ + volatile uint8_t PC_OFF_H; /**< Long message address offset, byte 1 */ + volatile uint8_t PC_OFF_L; /**< Long message address offset, byte 0 */ + volatile uint8_t PC_CTRL; /**< Parameters channel control */ + volatile uint8_t PIPE_S; /**< Sensor hub channel status */ + volatile uint8_t PIPE_D; /**< Sensor hub channel data */ + volatile uint8_t PC_DATA; /**< Short message parameters channel data */ + volatile uint8_t resvd3; /**< Reserved 3 */ + volatile uint8_t resvd4; /**< Reserved 4 */ + volatile uint8_t resvd5; /**< Reserved 5 */ + volatile uint8_t resvd6; /**< Reserved 6 */ + volatile uint8_t resvd7; /**< Reserved 7 */ + volatile uint8_t SAFE_CTRL; /**< Safe System Control */ + volatile uint8_t SAFE_SUM; /**< Summarized slave status */ + volatile uint8_t S_PC_DATA; /**< Response of Short message parameters channel Read for safe1 channel */ + volatile uint8_t ACC_ERR_CNT; /**< Fast position error counter */ + volatile uint8_t MAXACC; /**< Fast position acceleration boundary */ + volatile uint8_t MAXDEV_H; /**< Fast position estimator deviation high byte */ + volatile uint8_t MAXDEV_L; /**< Fast position estimator deviation low byte */ + volatile uint8_t resvd9; /**< Reserved 9 */ + volatile uint8_t EVENT_S; /**< Safe Events */ + volatile uint8_t MASK_S; /**< Safe Event Mask */ + volatile uint8_t DUMMY; /**< Dummy, no data */ volatile uint8_t SLAVE_REG_CTRL; /**< Short message control */ volatile uint8_t ACC_ERR_CNT_THRES; /**< Fast position error counter threshold */ volatile uint8_t MAXDEV_H_THRES; /**< Fast position estimator deviation high byte threshold */ volatile uint8_t MAXDEV_L_THRES; /**< Fast position estimator deviation low byte threshold */ /*Safe 2 Interface */ - volatile uint8_t version; - volatile uint8_t ENC2_ID; - volatile uint8_t STATUS2; - volatile uint8_t VPOS24; - volatile uint8_t VPOS23; - volatile uint8_t VPOS22; - volatile uint8_t VPOS21; - volatile uint8_t VPOS20; - volatile uint8_t VPOSCRC2_H; - volatile uint8_t VPOSCRC2_L; - volatile uint8_t DUMMY2; + volatile uint8_t VERSION2; /**< Version in Safe Channel 2 */ + volatile uint8_t ENC2_ID; /**< Encoder ID in Safe Channel 2 */ + volatile uint8_t STATUS2; /**< Safe Channel 2 Status */ + volatile uint8_t VPOS24; /**< Safe Position 2, byte 4 */ + volatile uint8_t VPOS23; /**< Safe Position 2, byte 3 */ + volatile uint8_t VPOS22; /**< Safe Position 2, byte 2 */ + volatile uint8_t VPOS21; /**< Safe Position 2, byte 1 */ + volatile uint8_t VPOS20; /**< Safe Position 2, byte 0 */ + volatile uint8_t VPOSCRC2_H; /**< CRC of Safe Position 2, byte 1 */ + volatile uint8_t VPOSCRC2_L; /**< CRC of Safe Position 2, byte 0 */ + volatile uint8_t POSTX; /**< Position transmission status */ + volatile uint8_t resvd10; /**< Reserved 10 */ /* Online Status*/ - volatile uint16_t ONLINE_STATUS_D; - volatile uint16_t ONLINE_STATUS_1; - volatile uint16_t ONLINE_STATUS_2; + volatile uint8_t ONLINE_STATUS_D_H; /**< Online Status D, high byte*/ + volatile uint8_t ONLINE_STATUS_D_L; /**< Online Status D, low byte*/ + volatile uint8_t ONLINE_STATUS_1_H; /**< Online Status 1, high byte*/ + volatile uint8_t ONLINE_STATUS_1_L; /**< Online Status 1, low byte*/ + volatile uint8_t ONLINE_STATUS_2_H; /**< Online Status 2, high byte*/ + volatile uint8_t ONLINE_STATUS_2_L; /**< Online Status 2, low byte*/ } HDSL_Interface; /** @} */ From 9ac1395d6e7bb4e85a07201701c5b873786ee0b3 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Mon, 21 Aug 2023 11:55:52 +0530 Subject: [PATCH 03/11] am64x/am243x: hdsl: Fix the two most significant bytes of fast position - Register corruption was causing loss of multi-turn data in fast position Fixes: PINDSW-5651 Signed-off-by: Dhaval Khandla --- source/position_sense/hdsl/firmware/datalink.asm | 8 ++++---- .../hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/source/position_sense/hdsl/firmware/datalink.asm b/source/position_sense/hdsl/firmware/datalink.asm index a92f368..dbfe57f 100644 --- a/source/position_sense/hdsl/firmware/datalink.asm +++ b/source/position_sense/hdsl/firmware/datalink.asm @@ -1593,7 +1593,7 @@ switch_clk: ;input: ; REG_FNC.b0: value ;modifies: -; REG_TMP0, REG_FNC +; REG_TMP1, REG_FNC ;-------------------------------------------------------------------------------------------------- qm_add: .if 1 @@ -1617,9 +1617,9 @@ qm_add_no_capping: qble qm_add_below_not_14, QM, 14 ; Defer the events register update to later ; Set EVENT_UPDATE_PENDING_QMLW to indicate a low QM value - lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 - set REG_TMP0.b0, REG_TMP0.w0, EVENT_UPDATE_PENDING_QMLW - sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + lbco ®_TMP1.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + set REG_TMP1.b0, REG_TMP1.b0, EVENT_UPDATE_PENDING_QMLW + sbco ®_TMP1.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 qm_add_below_not_14: or QM, QM, (1<<7) ;update MASTER_QM diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index 9dde319..b88f492 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -659,9 +659,9 @@ const unsigned int Hiperface_DSL2_0[]= { 0x710f6602, 0x24000f66, 0x590e6604, -0x91aa1800, -0x1f008000, -0x81aa1800, +0x91aa1801, +0x1f000101, +0x81aa1801, 0x13806666, 0x81031866, 0x20d10000, From 8d4349c7921fd7b473d0530c9c2f14441fe009b7 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Mon, 21 Aug 2023 12:05:13 +0530 Subject: [PATCH 04/11] am64x/am243x: hdsl: Fix the fast position and velocity calculation - Fix sign extension in estimator for relative position and acceleration addition - Fix sign estimation for relative position calculation - Remove an unnecessary RET instruction - Fix register corruption for ALIGN_PH - Fix register usage for DTE error signaling Fixes: PINDSW-5689 Signed-off-by: Dhaval Khandla --- .../hdsl/firmware/datalink_init.asm | 10 +-- .../firmware/hdsl_master_icssg_300_mhz_bin.h | 80 +++++++++++-------- .../position_sense/hdsl/firmware/memory.inc | 4 +- .../hdsl/firmware/transport.asm | 36 ++++++--- 4 files changed, 78 insertions(+), 52 deletions(-) diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm index 83426eb..73874df 100644 --- a/source/position_sense/hdsl/firmware/datalink_init.asm +++ b/source/position_sense/hdsl/firmware/datalink_init.asm @@ -376,12 +376,12 @@ datalink_learn_recv_loop_final: sbco ®_TMP2, c25, 0, 4 .endif - READ_CYCLCNT r25 + READ_CYCLCNT REG_TMP2 ; avoid wrap around, need to skip on equal as wait does not work for 0. -; qble datalink_learn_skip_wait, r25, r3 - qble datalink_abort2, r25, r3 - sub REG_TMP11, r3, r25 - MOV r25.b0, REG_TMP11.b0 +; qble datalink_learn_skip_wait, REG_TMP2, r3 + qble datalink_abort2, REG_TMP2, r3 + sub REG_TMP11, r3, REG_TMP2 + MOV REG_TMP2.b0, REG_TMP11.b0 ; WAIT subracts -1 from parameter before compare. On 0 it wraps around!!! WAIT REG_TMP11 datalink_learn_skip_wait: diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index b88f492..d15aad9 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -55,7 +55,7 @@ */ const unsigned int Hiperface_DSL2_0[]= { -0x21066e00, +0x21067800, 0x24000125, 0x2eff818f, 0x24001d8d, @@ -530,7 +530,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x511f0d03, 0x51190d02, 0x79000003, -0x230635d1, +0x23063fd1, 0x7900001a, 0xd104ff00, 0xd703ffff, @@ -637,7 +637,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00c0c0, 0x1f008181, 0x81505880, -0x2104eb00, +0x2104f500, 0x91042580, 0xd708e0ff, 0x91042580, @@ -746,7 +746,6 @@ const unsigned int Hiperface_DSL2_0[]= { 0x10404000, 0x10606040, 0x10000060, -0x91501801, 0x70c0e204, 0x10222200, 0x10020220, @@ -755,22 +754,23 @@ const unsigned int Hiperface_DSL2_0[]= { 0x10404000, 0x10606040, 0x10000060, -0x91501801, -0x70c0e207, -0x1f010101, +0x70c0e208, +0x91501802, +0x1f010202, 0x91043880, 0x1f018080, 0x81041880, 0xc901c002, 0x2400229f, -0x1d010101, -0x81501801, +0x91501802, +0x1d010202, +0x81501802, 0x6900e105, 0x686e5304, 0x813a188d, 0x24000019, 0x79000002, -0x2304d1d1, +0x2304d4d1, 0x10535300, 0x10333320, 0x10131340, @@ -931,7 +931,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24003001, 0xd1066b0e, 0x2400010d, -0x230660d1, +0x23066ad1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -944,7 +944,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81531800, 0x7900003b, 0x2400020d, -0x230660d1, +0x23066ad1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -987,7 +987,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x230660d1, +0x23066ad1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1196,7 +1196,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0xf020020d, 0x69000d03, 0x24fdfd80, -0x68808427, +0x68808426, 0x91381800, 0x01010000, 0x81381800, @@ -1228,8 +1228,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304b8d1, -0x209d0000, +0x2304bbd1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1249,10 +1248,14 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304b8d1, +0x2304bbd1, 0x91983880, -0x008e8080, -0x024ec0c0, +0x10eeeee1, +0x24000061, +0xc917ee02, +0x2400ff61, +0x00818080, +0x02c1c0c0, 0x81983880, 0x10efefe0, 0x10eeeee1, @@ -1293,18 +1296,25 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0000526e, 0x0220720f, 0x02c093af, +0xc91fe003, +0x03ff536f, +0x79000002, 0x0300536f, -0x6902190b, -0xc90fc907, +0x6902190f, +0x24000040, +0xc90fc909, 0x1600c980, 0x01018080, 0x0b038080, 0x16008080, 0x01018080, -0x79000002, +0x51008005, +0x13ff4040, +0x79000003, +0x10c9c980, 0x0b038080, 0x00808e8e, -0x03006e6e, +0x02404e4e, 0x20d10000, 0x151f8484, 0x240478e2, @@ -1358,7 +1368,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x9101185b, 0x51005b0e, 0x7900000d, -0x23061dd1, +0x230627d1, 0x91dc388c, 0x240000e2, 0x91e21882, @@ -1366,7 +1376,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x100c0c2a, 0x106c6c4a, 0x102c2c6a, -0x23061dd1, +0x230627d1, 0x0b01e2e2, 0x0501e2e2, 0x4f00e2ff, @@ -1444,10 +1454,10 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1e452121, 0x10000020, 0x2d802101, -0x910c3c99, -0x58e3f933, -0x04f9e3eb, -0x100b0b19, +0x910c3c82, +0x58e3e233, +0x04e2e3eb, +0x100b0b02, 0x0b01ebeb, 0x0501ebeb, 0x4f00ebff, @@ -1489,7 +1499,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b077200, 0x12001313, 0x0901f2f2, -0x230629d1, +0x230633d1, 0x510e6506, 0x6f010df6, 0x10656546, @@ -1528,16 +1538,16 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd703ffff, 0x24001b8d, 0x23016a9d, -0x2305ef9d, -0x230629d1, +0x2305f99d, +0x230633d1, 0x6f010dea, 0x05012525, 0x4f0025f8, 0x24001025, 0x24001c8d, 0x23016a9d, -0x2305ef9d, -0x230629d1, +0x2305f99d, +0x230633d1, 0x6f010dd6, 0x05012525, 0x4f0025fa, @@ -1704,4 +1714,4 @@ const unsigned int Hiperface_DSL2_0[]= { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2104ea00 }; +0x2104f400 }; diff --git a/source/position_sense/hdsl/firmware/memory.inc b/source/position_sense/hdsl/firmware/memory.inc index af6421a..8138b5b 100644 --- a/source/position_sense/hdsl/firmware/memory.inc +++ b/source/position_sense/hdsl/firmware/memory.inc @@ -202,7 +202,7 @@ LONG_MSG_RECV .sassign r28, long_msg_recv_s .asg r16.b3, BYTE_ERROR .asg r15, FAST_POSH .asg r14.b3, FAST_POSL - .asg r14, SPEED + .asg r14, SPEED ; NOTE: r14.b3 is used as FAST_POSL .asg r17.b0, DISPARITY .asg r17.b1, SEND_PARA .asg r29.w0, RET_ADDR0 @@ -509,4 +509,4 @@ VPOSCRC_TEMP .set 0x60 ; 2 bytes STATUS2_TEMP .set 0x62 ; 1 byte VPOS2_TEMP .set 0x63 ; 5 bytes VPOSCRC2_TEMP .set 0x68 ; 2 bytes -SAFE_SUM_TEMP .set 0x70 ; 1 byte \ No newline at end of file +SAFE_SUM_TEMP .set 0x70 ; 1 byte diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 4ba2367..3ef3f10 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -177,7 +177,6 @@ transport_on_v_frame_diff_pos: mov REG_TMP0.b2, REG_TMP0.b3 mov REG_TMP0.b3, REG_TMP0.b0 ;check if it is larger - lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 qbge transport_on_v_frame_dont_update_maxdev, REG_TMP2, REG_TMP0.w2 mov REG_TMP0.b0, REG_TMP2.b1 mov REG_TMP0.b1, REG_TMP2.b0 @@ -193,10 +192,10 @@ transport_on_v_frame_dont_update_maxdev: mov REG_TMP0.b2, REG_TMP0.b3 mov REG_TMP0.b3, REG_TMP0.b0 ;check if it is larger - lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 qbge transport_on_v_frame_dont_update_dte, REG_TMP2, REG_TMP0.w2 ; Set EVENT_DTE in ONLINE_STATUS_D register - set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE + lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 + set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_DTE ; Set EVENT_DTE in EVENT register lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 set REG_TMP0.w0, REG_TMP0.w0, EVENT_DTE @@ -208,8 +207,9 @@ transport_on_v_frame_dont_update_maxdev: update_events_no_int6: transport_on_v_frame_dont_update_dte: ; Clear EVENT_DTE in ONLINE_STATUS_D register - clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE - sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 + lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 + clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_DTE + sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1 ;check for diff. is 0 -> estimate if not qbne transport_on_v_frame_estimate, REG_TMP1, 0 @@ -1073,7 +1073,6 @@ calc_speed_extend_acc1: sub DELTA_ACC0, REG_TMP0.w0, LAST_ACC mov LAST_ACC, REG_TMP0.w0 CALL1 calc_fastpos - RET ;restore return addr mov RET_ADDR0, REG_TMP11.w0 ; Moving the event and online register update during stuffing @@ -1108,8 +1107,14 @@ calc_speed_extend_acc0: transport_on_h_frame_exit: ;calculate rel. pos and store lbco ®_TMP0, MASTER_REGS_CONST, REL_POS0, 4 - add REG_TMP0.w0, REG_TMP0.w0, SPEED.w0 - adc REG_TMP0.w2, REG_TMP0.w2, SPEED.b2 +;sign extend speed to 32 bits and add it to REL_POS + mov REG_TMP1, SPEED + ldi REG_TMP1.b3, 0 + qbbc calc_relpos_extend_vel, SPEED, 23 + ldi REG_TMP1.b3, 0xff +calc_relpos_extend_vel: + add REG_TMP0.w0, REG_TMP0.w0, REG_TMP1.w0 + adc REG_TMP0.w2, REG_TMP0.w2, REG_TMP1.w2 sbco ®_TMP0, MASTER_REGS_CONST, REL_POS0, 4 ;store fast pos. and velocity mov REG_TMP0, FAST_POSH @@ -1205,21 +1210,32 @@ estimator_fpos: add FAST_POSL, VERT_L.b2, REG_TMP0.b0 adc FAST_POSH.b0, VERT_L.b3, REG_TMP0.b1 adc FAST_POSH.w1, VERT_H.w0, REG_TMP0.w2 +;sign extend relative position to 40 bits + qbbc estimator_fpos_add_relpos_positive, REG_TMP0, 31 + adc FAST_POSH.b3, VERT_H.b2, 0xFF + qba estimator_fpos_add_relpos_done +estimator_fpos_add_relpos_positive: adc FAST_POSH.b3, VERT_H.b2, 0 +estimator_fpos_add_relpos_done: qbne estimator_fpos_align_ph_not_2, ALIGN_PH, 2 ;vel = vel+acc/8 - qbbc estimator_fpos_acc_pos, LAST_ACC, 15 + ldi REG_TMP0.b2, 0 + qbbc estimator_fpos_acc_pos, LAST_ACC, 15 not REG_TMP0.w0, LAST_ACC add REG_TMP0.w0, REG_TMP0.w0, 1 lsr REG_TMP0.w0, REG_TMP0.w0, 3 not REG_TMP0.w0, REG_TMP0.w0 add REG_TMP0.w0, REG_TMP0.w0, 1 +;sign extend acceleration to 24 bit -> speed size + qbeq estimator_fpos_acc_sing_check_end, REG_TMP0.w0, 0 + or REG_TMP0.b2, REG_TMP0.b2, 0xFF qba estimator_fpos_acc_sing_check_end estimator_fpos_acc_pos: + mov REG_TMP0.w0, LAST_ACC lsr REG_TMP0.w0, REG_TMP0.w0, 3 estimator_fpos_acc_sing_check_end: add SPEED.w0, SPEED.w0, REG_TMP0.w0 - adc SPEED.b3, SPEED.b3, 0 + adc SPEED.b2, SPEED.b2, REG_TMP0.b2 estimator_fpos_align_ph_not_2: RET1 ;-------------------------------------------------------------------------------------------------- From 7605041284ded7ea98f98980967b2102a1921af4 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 22 Aug 2023 11:52:20 +0530 Subject: [PATCH 05/11] am64x/am243x: hdsl: Fix the SUM/SSUM/FIX1 bit configuration in ONLINE STATUS registers - MASK_SUM should not be used for masking SUMMARY while updating these SUM and SSUM bits in ONLINE STATUS registers - Fix the mask for SCE and VPOS updates Fixes: PINDSW-6487, PINDSW-6488 Signed-off-by: Dhaval Khandla --- .../firmware/hdsl_master_icssg_300_mhz_bin.h | 52 ++++++++++--------- .../hdsl/firmware/transport.asm | 15 ++++-- 2 files changed, 37 insertions(+), 30 deletions(-) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index d15aad9..cd21d72 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -55,7 +55,7 @@ */ const unsigned int Hiperface_DSL2_0[]= { -0x21067800, +0x21067a00, 0x24000125, 0x2eff818f, 0x24001d8d, @@ -151,7 +151,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd104ff00, 0xd703ffff, 0x24002f1e, -0x23046a9d, +0x23046c9d, 0x05014545, 0x4f0045d2, 0x24000070, @@ -523,14 +523,14 @@ const unsigned int Hiperface_DSL2_0[]= { 0x12006d6d, 0x09064d4d, 0xc901c402, -0x2103db00, +0x2103dd00, 0xd104ff00, 0xd703ffff, 0x106d6d1e, 0x511f0d03, 0x51190d02, 0x79000003, -0x23063fd1, +0x230641d1, 0x7900001a, 0xd104ff00, 0xd703ffff, @@ -542,7 +542,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x511f0d12, 0x51190d11, 0xc901c402, -0x21032000, +0x21032200, 0x910c3c81, 0x240117e0, 0x04e1e0e0, @@ -637,7 +637,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00c0c0, 0x1f008181, 0x81505880, -0x2104f500, +0x2104f700, 0x91042580, 0xd708e0ff, 0x91042580, @@ -707,7 +707,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81601881, 0xd104c40e, 0x91521801, -0x110b0101, +0x11db0101, 0x5100980c, 0x913d1880, 0x1f050000, @@ -770,7 +770,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813a188d, 0x24000019, 0x79000002, -0x2304d4d1, +0x2304d6d1, 0x10535300, 0x10333320, 0x10131340, @@ -836,10 +836,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81361800, 0x91081821, 0x10210001, -0x91503802, -0x1d060202, -0x1d060242, -0x5100010d, +0x5100010b, 0x91043880, 0x1f068080, 0x81041880, @@ -850,6 +847,11 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813d1880, 0xc9062002, 0x2400269f, +0x91361800, +0x91503802, +0x1d060202, +0x1d060242, +0x51000003, 0x1f060202, 0x1f060242, 0x81503802, @@ -931,7 +933,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24003001, 0xd1066b0e, 0x2400010d, -0x23066ad1, +0x23066cd1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -944,7 +946,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81531800, 0x7900003b, 0x2400020d, -0x23066ad1, +0x23066cd1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -987,7 +989,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x23066ad1, +0x23066cd1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1228,7 +1230,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304bbd1, +0x2304bdd1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1248,7 +1250,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304bbd1, +0x2304bdd1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1368,7 +1370,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x9101185b, 0x51005b0e, 0x7900000d, -0x230627d1, +0x230629d1, 0x91dc388c, 0x240000e2, 0x91e21882, @@ -1376,7 +1378,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x100c0c2a, 0x106c6c4a, 0x102c2c6a, -0x230627d1, +0x230629d1, 0x0b01e2e2, 0x0501e2e2, 0x4f00e2ff, @@ -1499,7 +1501,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b077200, 0x12001313, 0x0901f2f2, -0x230633d1, +0x230635d1, 0x510e6506, 0x6f010df6, 0x10656546, @@ -1538,16 +1540,16 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd703ffff, 0x24001b8d, 0x23016a9d, -0x2305f99d, -0x230633d1, +0x2305fb9d, +0x230635d1, 0x6f010dea, 0x05012525, 0x4f0025f8, 0x24001025, 0x24001c8d, 0x23016a9d, -0x2305f99d, -0x230633d1, +0x2305fb9d, +0x230635d1, 0x6f010dd6, 0x05012525, 0x4f0025fa, @@ -1714,4 +1716,4 @@ const unsigned int Hiperface_DSL2_0[]= { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2104f400 }; +0x2104f600 }; diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 3ef3f10..e429f11 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -112,7 +112,7 @@ transport_on_v_frame: ;transmission error? qbbs transport_on_v_frame_dont_update_qm, H_FRAME.flags, FLAG_ERR_VERT lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1 - and REG_TMP1.b0, REG_TMP1.b0, (~((1< Date: Tue, 22 Aug 2023 11:58:30 +0530 Subject: [PATCH 06/11] am64x/am243x: hdsl: Add versioning in firmware - Update the version to 0.2 - Use the VERSION and VERSION2 register - Remove the hardcoding from driver Fixes: PINDSW-6518 Signed-off-by: Dhaval Khandla --- source/position_sense/hdsl/driver/hdsl_lut.c | 1 - .../hdsl/firmware/datalink_init.asm | 6 ++++ .../position_sense/hdsl/firmware/defines.inc | 9 ++++++ .../firmware/hdsl_master_icssg_300_mhz_bin.h | 29 ++++++++++--------- 4 files changed, 31 insertions(+), 14 deletions(-) diff --git a/source/position_sense/hdsl/driver/hdsl_lut.c b/source/position_sense/hdsl/driver/hdsl_lut.c index 0e76a4f..44b23f3 100644 --- a/source/position_sense/hdsl/driver/hdsl_lut.c +++ b/source/position_sense/hdsl/driver/hdsl_lut.c @@ -1283,7 +1283,6 @@ static void hdsl_configure_register_if(HDSL_Handle hdslHandle) hdslHandle->hdslInterface->MAXDEV_L = 0x0; hdslHandle->hdslInterface->MAXDEV_H_THRES = 0xFF; hdslHandle->hdslInterface->MAXDEV_L_THRES = 0xFF; - hdslHandle->hdslInterface->VERSION = 0x41; hdslHandle->hdslInterface->ACC_ERR_CNT_THRES = 0x1F; HW_WR_REG32(((uint32_t)(hdslHandle->baseMemAddr) + 0xac), 0x4cc8115d); diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm index 73874df..f45c470 100644 --- a/source/position_sense/hdsl/firmware/datalink_init.asm +++ b/source/position_sense/hdsl/firmware/datalink_init.asm @@ -70,6 +70,12 @@ datalink_reset: .else TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 .endif + +; set the VERSION and VERSION2 register + ldi REG_TMP0.b0, ICSS_FIRMWARE_RELEASE + sbco ®_TMP0.b0, MASTER_REGS_CONST, VERSION, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, VERSION2, 1 + zero &H_FRAME, (4*2) ;init transport layer here CALL transport_init diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc index d8c5781..14f9452 100644 --- a/source/position_sense/hdsl/firmware/defines.inc +++ b/source/position_sense/hdsl/firmware/defines.inc @@ -30,6 +30,15 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; +;Firmware version +FIRMWARE_VERSION_CODING .set 0x1 +; bit5..4 major number +FIRMWARE_VERSION_MAJOR .set 0x0 +; bit3..0 minor number +FIRMWARE_VERSION_MINOR .set 0x2 + +ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_CODING << 6) | (FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) + ;number of cycles for 1 bit .if $defined("FREERUN_300_MHZ") ;number of cycles for 1 bit diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index cd21d72..aff99b6 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -55,7 +55,7 @@ */ const unsigned int Hiperface_DSL2_0[]= { -0x21067a00, +0x21067d00, 0x24000125, 0x2eff818f, 0x24001d8d, @@ -530,7 +530,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x511f0d03, 0x51190d02, 0x79000003, -0x230641d1, +0x230644d1, 0x7900001a, 0xd104ff00, 0xd703ffff, @@ -933,7 +933,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24003001, 0xd1066b0e, 0x2400010d, -0x23066cd1, +0x23066fd1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -946,7 +946,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81531800, 0x7900003b, 0x2400020d, -0x23066cd1, +0x23066fd1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -989,7 +989,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x23066cd1, +0x23066fd1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1339,6 +1339,9 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81080580, 0x24001fc0, 0x810605c0, +0x24004200, +0x810b1800, +0x81441800, 0x2eff8383, 0x23027c9d, 0x24000866, @@ -1370,7 +1373,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x9101185b, 0x51005b0e, 0x7900000d, -0x230629d1, +0x23062cd1, 0x91dc388c, 0x240000e2, 0x91e21882, @@ -1378,7 +1381,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x100c0c2a, 0x106c6c4a, 0x102c2c6a, -0x230629d1, +0x23062cd1, 0x0b01e2e2, 0x0501e2e2, 0x4f00e2ff, @@ -1501,7 +1504,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b077200, 0x12001313, 0x0901f2f2, -0x230635d1, +0x230638d1, 0x510e6506, 0x6f010df6, 0x10656546, @@ -1534,22 +1537,22 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813d1800, 0xc9022002, 0x2400269f, -0x7f000030, +0x7f00002d, 0x24000925, 0xd104ff00, 0xd703ffff, 0x24001b8d, 0x23016a9d, -0x2305fb9d, -0x230635d1, +0x2305fe9d, +0x230638d1, 0x6f010dea, 0x05012525, 0x4f0025f8, 0x24001025, 0x24001c8d, 0x23016a9d, -0x2305fb9d, -0x230635d1, +0x2305fe9d, +0x230638d1, 0x6f010dd6, 0x05012525, 0x4f0025fa, From 6b8d4c32cc95d7ac358ae2681802de1d352a8fec Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 22 Aug 2023 12:05:04 +0530 Subject: [PATCH 07/11] am64x/am243x: hdsl: Fix reset behaviour after triggering manual reset - Remove HALT instructions - Clear all registers after reset Fixes: PINDSW-6492 Signed-off-by: Dhaval Khandla --- .../position_sense/hdsl/firmware/datalink.asm | 5 -- .../hdsl/firmware/datalink_init.asm | 4 +- .../firmware/hdsl_master_icssg_300_mhz_bin.h | 89 +++++++++---------- 3 files changed, 44 insertions(+), 54 deletions(-) diff --git a/source/position_sense/hdsl/firmware/datalink.asm b/source/position_sense/hdsl/firmware/datalink.asm index dbfe57f..725c22a 100644 --- a/source/position_sense/hdsl/firmware/datalink.asm +++ b/source/position_sense/hdsl/firmware/datalink.asm @@ -1402,7 +1402,6 @@ calculation_for_wait_done: mov REG_TMP11, RET_ADDR1 qbeq send_stuffing_no_stuffing, NUM_STUFFING, 0 ;check if we have stuffing - ;halt READ_CYCLCNT REG_TMP0 rsb REG_TMP2, REG_TMP0, (5*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4) mov REG_FNC.b3, NUM_STUFFING @@ -1600,10 +1599,6 @@ qm_add: and QM, QM, 0x7f ;check if negative (bit 7 indicates there is a link -> check bit 6) qbbc qm_add_no_reset, QM, 6 - ; set EDIO28 - ;ldi32 REG_TMP1, 0x02e300 - ;sbbo ®_TMP1.b0, REG_TMP1, 0x13, 1 - halt ldi QM, 0 ;update MASTER_QM sbco &QM, MASTER_REGS_CONST, MASTER_QM, 1 diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm index f45c470..640a3a0 100644 --- a/source/position_sense/hdsl/firmware/datalink_init.asm +++ b/source/position_sense/hdsl/firmware/datalink_init.asm @@ -54,10 +54,10 @@ relocatable0: datalink_init_start: +datalink_reset: ;State RESET zero &r0, 124 ;send 2 times -datalink_reset: ;setup ICSS encoder peripheral for Hiperface DSL ldi DISPARITY, 0x00 @@ -546,7 +546,6 @@ datalink_learn_end: qba datalink_learn2_before ;-------------------------------------------------------------------------------------------------- datalink_abort2: - halt qbbs datalink_abort2_no_wait, r30, RX_ENABLE ;changed here from 24 to 26 WAIT_TX_DONE .if $defined("FREERUN_300_MHZ") @@ -561,7 +560,6 @@ datalink_abort2: NOP_2 .endif datalink_abort3: - halt datalink_abort2_no_wait: lbco ®_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1 add REG_TMP0.b0, REG_TMP0.b0, 1 diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index aff99b6..79e8506 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -55,7 +55,7 @@ */ const unsigned int Hiperface_DSL2_0[]= { -0x21067d00, +0x21067a00, 0x24000125, 0x2eff818f, 0x24001d8d, @@ -151,7 +151,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd104ff00, 0xd703ffff, 0x24002f1e, -0x23046c9d, +0x23046b9d, 0x05014545, 0x4f0045d2, 0x24000070, @@ -170,7 +170,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230277d1, +0x230276d1, 0x6f0005f7, 0x240120eb, 0xf0cd0b0d, @@ -189,7 +189,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230277d1, +0x230276d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -212,7 +212,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230277d1, +0x230276d1, 0x110fcdc0, 0x240168eb, 0xf0c00b00, @@ -237,7 +237,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230277d1, +0x230276d1, 0x6f0005f7, 0x240120eb, 0xf0cd0b0d, @@ -256,7 +256,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230277d1, +0x230276d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -279,7 +279,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230277d1, +0x230276d1, 0x110fcdc0, 0x240168eb, 0xf0c00b00, @@ -296,7 +296,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x20d10000, 0x24000605, 0x2eff8283, -0x230262d1, +0x230261d1, 0x240000c0, 0x2400002d, 0x230069d1, @@ -451,9 +451,9 @@ const unsigned int Hiperface_DSL2_0[]= { 0x808113c1, 0xc901c405, 0x69084502, -0x21028400, +0x21028300, 0x69074502, -0x2102df00, +0x2102de00, 0x51000c2b, 0x51015b04, 0x100c0c02, @@ -523,14 +523,14 @@ const unsigned int Hiperface_DSL2_0[]= { 0x12006d6d, 0x09064d4d, 0xc901c402, -0x2103dd00, +0x2103dc00, 0xd104ff00, 0xd703ffff, 0x106d6d1e, 0x511f0d03, 0x51190d02, 0x79000003, -0x230644d1, +0x230641d1, 0x7900001a, 0xd104ff00, 0xd703ffff, @@ -542,7 +542,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x511f0d12, 0x51190d11, 0xc901c402, -0x21032200, +0x21032100, 0x910c3c81, 0x240117e0, 0x04e1e0e0, @@ -637,7 +637,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00c0c0, 0x1f008181, 0x81505880, -0x2104f700, +0x2104f500, 0x91042580, 0xd708e0ff, 0x91042580, @@ -651,11 +651,10 @@ const unsigned int Hiperface_DSL2_0[]= { 0xcf08e0ff, 0x20d10000, 0x117f6666, -0xc9066605, -0x2a000000, +0xc9066604, 0x24000066, 0x81031866, -0x7f0000da, +0x7f0000db, 0x710f6602, 0x24000f66, 0x590e6604, @@ -770,7 +769,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813a188d, 0x24000019, 0x79000002, -0x2304d6d1, +0x2304d5d1, 0x10535300, 0x10333320, 0x10131340, @@ -933,7 +932,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24003001, 0xd1066b0e, 0x2400010d, -0x23066fd1, +0x23066cd1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -946,7 +945,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81531800, 0x7900003b, 0x2400020d, -0x23066fd1, +0x23066cd1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -989,7 +988,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x23066fd1, +0x23066cd1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1230,7 +1229,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304bdd1, +0x2304bcd1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1250,7 +1249,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304bdd1, +0x2304bcd1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1343,7 +1342,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x810b1800, 0x81441800, 0x2eff8383, -0x23027c9d, +0x23027b9d, 0x24000866, 0x2400000c, 0x2400002c, @@ -1373,7 +1372,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x9101185b, 0x51005b0e, 0x7900000d, -0x23062cd1, +0x230629d1, 0x91dc388c, 0x240000e2, 0x91e21882, @@ -1381,7 +1380,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x100c0c2a, 0x106c6c4a, 0x102c2c6a, -0x23062cd1, +0x230629d1, 0x0b01e2e2, 0x0501e2e2, 0x4f00e2ff, @@ -1504,15 +1503,14 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b077200, 0x12001313, 0x0901f2f2, -0x230638d1, +0x230635d1, 0x510e6506, 0x6f010df6, 0x10656546, 0x05012525, 0x4f002595, -0x7900001c, -0x2a000000, -0xd118fe0c, +0x7900001a, +0xd118fe0b, 0xd105ff00, 0x31010001, 0x31010001, @@ -1523,7 +1521,6 @@ const unsigned int Hiperface_DSL2_0[]= { 0x31010001, 0x31010001, 0x31010001, -0x2a000000, 0x91a91800, 0x01010000, 0x81a91800, @@ -1537,34 +1534,34 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813d1800, 0xc9022002, 0x2400269f, -0x7f00002d, +0x7f00002e, 0x24000925, 0xd104ff00, 0xd703ffff, 0x24001b8d, 0x23016a9d, -0x2305fe9d, -0x230638d1, -0x6f010dea, +0x2305fb9d, +0x230635d1, +0x6f010deb, 0x05012525, 0x4f0025f8, 0x24001025, 0x24001c8d, 0x23016a9d, -0x2305fe9d, -0x230638d1, -0x6f010dd6, +0x2305fb9d, +0x230635d1, +0x6f010dd8, 0x05012525, 0x4f0025fa, 0x810a1846, 0x24001d8d, 0x23016a9d, 0x2300ef9d, -0x6e0403cf, -0x6e2423ce, +0x6e0403d1, +0x6e2423d0, 0x110f4300, 0x0b044320, -0x6e2000cb, +0x6e2000cd, 0x10848480, 0x10434340, 0x10404001, @@ -1590,7 +1587,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x2301f7d1, 0x21001600, 0x24002005, -0x230262d1, +0x230261d1, 0x24000080, 0x2405a4eb, 0x2eff8992, @@ -1603,7 +1600,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x10000020, 0x0b018001, 0x14000130, -0x230277d1, +0x230276d1, 0x6f0005f6, 0x24001d05, 0xc918ff00, @@ -1615,7 +1612,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x10000020, 0x0b018001, 0x14000130, -0x230277d1, +0x230276d1, 0x6f0105f6, 0xc918ff00, 0x101f1f00, @@ -1719,4 +1716,4 @@ const unsigned int Hiperface_DSL2_0[]= { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2104f600 }; +0x2104f500 }; From dd0d2e356bc673873cf49edc6fe0917add991ae3 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 22 Aug 2023 13:14:18 +0530 Subject: [PATCH 08/11] am64x/am243x: hdsl: Make FREL/FRES bit set sticky in EVENT/EVENT_S - Firmware should not clear these bits in EVENT/EVENT_S registers - Update the version to 0.3 Fixes: PINDSW-6526 Signed-off-by: Dhaval Khandla --- .../position_sense/hdsl/firmware/defines.inc | 2 +- .../firmware/hdsl_master_icssg_300_mhz_bin.h | 58 +++++++++---------- .../hdsl/firmware/transport.asm | 13 +---- 3 files changed, 29 insertions(+), 44 deletions(-) diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc index 14f9452..179f40a 100644 --- a/source/position_sense/hdsl/firmware/defines.inc +++ b/source/position_sense/hdsl/firmware/defines.inc @@ -35,7 +35,7 @@ FIRMWARE_VERSION_CODING .set 0x1 ; bit5..4 major number FIRMWARE_VERSION_MAJOR .set 0x0 ; bit3..0 minor number -FIRMWARE_VERSION_MINOR .set 0x2 +FIRMWARE_VERSION_MINOR .set 0x3 ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_CODING << 6) | (FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index 79e8506..aecf04b 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -55,7 +55,7 @@ */ const unsigned int Hiperface_DSL2_0[]= { -0x21067a00, +0x21067400, 0x24000125, 0x2eff818f, 0x24001d8d, @@ -151,7 +151,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd104ff00, 0xd703ffff, 0x24002f1e, -0x23046b9d, +0x2304659d, 0x05014545, 0x4f0045d2, 0x24000070, @@ -530,7 +530,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x511f0d03, 0x51190d02, 0x79000003, -0x230641d1, +0x23063bd1, 0x7900001a, 0xd104ff00, 0xd703ffff, @@ -637,7 +637,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00c0c0, 0x1f008181, 0x81505880, -0x2104f500, +0x2104ef00, 0x91042580, 0xd708e0ff, 0x91042580, @@ -769,7 +769,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813a188d, 0x24000019, 0x79000002, -0x2304d5d1, +0x2304cfd1, 0x10535300, 0x10333320, 0x10131340, @@ -932,7 +932,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24003001, 0xd1066b0e, 0x2400010d, -0x23066cd1, +0x230666d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -945,7 +945,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81531800, 0x7900003b, 0x2400020d, -0x23066cd1, +0x230666d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -988,7 +988,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x23066cd1, +0x230666d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1051,7 +1051,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x7900005d, +0x79000057, 0x91351800, 0xc9060007, 0x1d060000, @@ -1059,7 +1059,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x79000055, +0x7900004f, 0xc909c41c, 0x05041b1b, 0x490c1b06, @@ -1067,7 +1067,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x110f3131, 0x69001b02, 0x1d09c4c4, -0x7900004d, +0x79000047, 0xc9077a08, 0x905a1831, 0xc9021b03, @@ -1087,12 +1087,9 @@ const unsigned int Hiperface_DSL2_0[]= { 0x14809a9a, 0x69101b02, 0x15ff1a1a, -0x79000039, +0x79000033, 0x91401800, -0x513f0016, -0x913d1840, -0x1d004040, -0x813d1840, +0x513f0013, 0x91531840, 0x1d004040, 0x81531840, @@ -1110,15 +1107,12 @@ const unsigned int Hiperface_DSL2_0[]= { 0x2400201b, 0x2400403b, 0x1f09c4c4, -0x79000022, +0x7900001f, 0x912c1800, -0xc9000020, +0xc900001d, 0x1d000000, 0x812c1800, 0x1f09c4c4, -0x91041880, -0x1d098080, -0x81041880, 0x91511800, 0x1d010000, 0x81511800, @@ -1229,7 +1223,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304bcd1, +0x2304b6d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1249,7 +1243,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304bcd1, +0x2304b6d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1338,7 +1332,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81080580, 0x24001fc0, 0x810605c0, -0x24004200, +0x24004300, 0x810b1800, 0x81441800, 0x2eff8383, @@ -1372,7 +1366,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x9101185b, 0x51005b0e, 0x7900000d, -0x230629d1, +0x230623d1, 0x91dc388c, 0x240000e2, 0x91e21882, @@ -1380,7 +1374,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x100c0c2a, 0x106c6c4a, 0x102c2c6a, -0x230629d1, +0x230623d1, 0x0b01e2e2, 0x0501e2e2, 0x4f00e2ff, @@ -1503,7 +1497,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b077200, 0x12001313, 0x0901f2f2, -0x230635d1, +0x23062fd1, 0x510e6506, 0x6f010df6, 0x10656546, @@ -1540,16 +1534,16 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd703ffff, 0x24001b8d, 0x23016a9d, -0x2305fb9d, -0x230635d1, +0x2305f59d, +0x23062fd1, 0x6f010deb, 0x05012525, 0x4f0025f8, 0x24001025, 0x24001c8d, 0x23016a9d, -0x2305fb9d, -0x230635d1, +0x2305f59d, +0x23062fd1, 0x6f010dd8, 0x05012525, 0x4f0025fa, @@ -1716,4 +1710,4 @@ const unsigned int Hiperface_DSL2_0[]= { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2104f500 }; +0x2104ef00 }; diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index e429f11..6819b66 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -135,7 +135,6 @@ transport_on_v_frame_dont_update_qm: add REG_TMP1, REG_TMP1, 1 sbco ®_TMP1, MASTER_REGS_CONST, NUM_VERT_ERR0, 4 .endif - ;HALT qba transport_on_v_frame_exit check_for_slave_error_on_v_frame: ;CRC was correct -> add 1 to QM @@ -825,11 +824,7 @@ transport_layer_check_for_new_short_msg: lbco ®_TMP0.b0, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1 qbeq transport_layer_no_short_msg, REG_TMP0.b0, 0x3f -;set short msg channel to busy (reset EVENT_S_FRES) - lbco ®_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 - clr REG_TMP0.b2, REG_TMP0.b2, EVENT_S_FRES - sbco ®_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 -; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register +; Clear ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register lbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_FRES-8) sbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 @@ -869,11 +864,7 @@ transport_layer_no_short_msg: sbco ®_TMP0.b0, MASTER_REGS_CONST, PC_CTRL, 1 ;set para channel to busy set H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY -;set long msg channel to busy (reset FREL) - lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 2 - clr REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL - sbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 2 -; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register +; Clear ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 From 4f8af9152237e5d6a5b53a0d31591363fa8775c9 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 22 Aug 2023 13:36:44 +0530 Subject: [PATCH 09/11] am64x/am243x: hdsl: Fix QMLW bits in ONLINE STATUS registers - Mask was not applied to QM register before checking the low value - Enable QMLW/POS checks for all H-frames Fixes: PINDSW-6530 Signed-off-by: Dhaval Khandla --- .../position_sense/hdsl/firmware/datalink.asm | 2 +- .../firmware/hdsl_master_icssg_300_mhz_bin.h | 141 +++++++++--------- .../hdsl/firmware/transport.asm | 4 + 3 files changed, 76 insertions(+), 71 deletions(-) diff --git a/source/position_sense/hdsl/firmware/datalink.asm b/source/position_sense/hdsl/firmware/datalink.asm index 725c22a..6950c44 100644 --- a/source/position_sense/hdsl/firmware/datalink.asm +++ b/source/position_sense/hdsl/firmware/datalink.asm @@ -1074,11 +1074,11 @@ send_header_encode_sec_subblock_end: lsr REG_TMP0.b0, REG_FNC.b2, 2 or REG_FNC.b3, REG_FNC.b3, REG_TMP0.b0 lsl REG_FNC.b2, REG_FNC.b2, 6 - qbbc transport_layer_send_msg_done1, H_FRAME.flags, FLAG_NORMAL_FLOW .if $defined("HDSL_MULTICHANNEL") PUSH_FIFO_1_8x PUSH_FIFO_2_8x .endif +; transport_layer_send_msg sends short/long message (if pending) and also checks for QMLW/POS errors jmp transport_layer_send_msg transport_layer_send_msg_done1: .if $defined("HDSL_MULTICHANNEL") diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index aecf04b..9167ea6 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -55,7 +55,7 @@ */ const unsigned int Hiperface_DSL2_0[]= { -0x21067400, +0x21067500, 0x24000125, 0x2eff818f, 0x24001d8d, @@ -71,8 +71,8 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b01e0e0, 0x0501e0e0, 0x4f00e0ff, -0x230216d1, -0x2301f7d1, +0x230215d1, +0x2301f6d1, 0x05012525, 0x6f0025f0, 0x2eff8f8e, @@ -84,7 +84,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x2300ef9d, 0x05012525, 0x5100254c, -0x2301f7d1, +0x2301f6d1, 0xd70170f8, 0xcf0723f7, 0x1f02c4c4, @@ -127,18 +127,18 @@ const unsigned int Hiperface_DSL2_0[]= { 0x5101450a, 0x2400040d, 0x040d6666, -0x230253d1, +0x230252d1, 0x79000009, 0x69014508, 0x2400060d, 0x040d6666, -0x230253d1, +0x230252d1, 0x79000004, 0x2400010d, 0x000d6666, -0x230253d1, +0x230252d1, 0x1d03c4c4, -0x2301f7d1, +0x2301f6d1, 0x51000c09, 0xd104ff00, 0xd703ffff, @@ -151,7 +151,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd104ff00, 0xd703ffff, 0x24002f1e, -0x2304659d, +0x2304669d, 0x05014545, 0x4f0045d2, 0x24000070, @@ -159,7 +159,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24000845, 0x1f01c4c4, 0x7f0000cd, -0x21023200, +0x21023100, 0x10d1d182, 0x240000cd, 0xc918ff00, @@ -170,7 +170,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230276d1, +0x230275d1, 0x6f0005f7, 0x240120eb, 0xf0cd0b0d, @@ -189,7 +189,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230276d1, +0x230275d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -212,7 +212,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230276d1, +0x230275d1, 0x110fcdc0, 0x240168eb, 0xf0c00b00, @@ -237,7 +237,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230276d1, +0x230275d1, 0x6f0005f7, 0x240120eb, 0xf0cd0b0d, @@ -256,7 +256,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230276d1, +0x230275d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -279,7 +279,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230276d1, +0x230275d1, 0x110fcdc0, 0x240168eb, 0xf0c00b00, @@ -296,7 +296,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x20d10000, 0x24000605, 0x2eff8283, -0x230261d1, +0x230260d1, 0x240000c0, 0x2400002d, 0x230069d1, @@ -350,32 +350,32 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f04c4c4, 0x2400060d, 0x040d6666, -0x230253d1, +0x230252d1, 0x79000006, 0xc9005005, 0x51fd0304, 0x2400020d, 0x040d6666, -0x230253d1, +0x230252d1, 0xc9017005, 0x2400010d, 0x040d6666, -0x230253d1, +0x230252d1, 0x79000005, 0xc9015004, 0x2400020d, 0x040d6666, -0x230253d1, +0x230252d1, 0xc9027004, 0x2400010d, 0x040d6666, -0x230253d1, +0x230252d1, 0x111870e0, 0x5100e006, 0x1f03c4c4, 0x2400020d, 0x040d6666, -0x230253d1, +0x230252d1, 0x79000008, 0xc9035002, 0x69fd2403, @@ -383,7 +383,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x51fd0404, 0x2400020d, 0x040d6666, -0x230253d1, +0x230252d1, 0x2400052d, 0x24000605, 0x2300acd1, @@ -395,7 +395,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b01e0e0, 0x0501e0e0, 0x4f00e0ff, -0x230216d1, +0x230215d1, 0x100d0d63, 0x0908f5f5, 0x0b18f4e0, @@ -407,7 +407,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f05c4c4, 0x2400080d, 0x040d6666, -0x230253d1, +0x230252d1, 0x14637878, 0x69014502, 0x15ff7878, @@ -451,9 +451,9 @@ const unsigned int Hiperface_DSL2_0[]= { 0x808113c1, 0xc901c405, 0x69084502, -0x21028300, +0x21028200, 0x69074502, -0x2102de00, +0x2102dd00, 0x51000c2b, 0x51015b04, 0x100c0c02, @@ -522,15 +522,14 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b024d00, 0x12006d6d, 0x09064d4d, -0xc901c402, -0x2103dc00, +0x2103db00, 0xd104ff00, 0xd703ffff, 0x106d6d1e, 0x511f0d03, 0x51190d02, 0x79000003, -0x23063bd1, +0x23063cd1, 0x7900001a, 0xd104ff00, 0xd703ffff, @@ -542,7 +541,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x511f0d12, 0x51190d11, 0xc901c402, -0x21032100, +0x21032000, 0x910c3c81, 0x240117e0, 0x04e1e0e0, @@ -573,7 +572,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x810605c1, 0x24001f8d, 0x2400044d, -0x230247d1, +0x230246d1, 0x05016d6d, 0x51006d0c, 0xd104ff00, @@ -581,10 +580,10 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24000b1e, 0x24000f8d, 0x2400044d, -0x230247d1, +0x230246d1, 0x24001f8d, 0x2400034d, -0x230247d1, +0x230246d1, 0x05016d6d, 0x6f006df6, 0x10ebebd1, @@ -609,7 +608,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x10d1d18b, 0x2400040d, 0x040d6666, -0x230253d1, +0x230252d1, 0x108b8bd1, 0x24001fc0, 0x810605c0, @@ -637,7 +636,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00c0c0, 0x1f008181, 0x81505880, -0x2104ef00, +0x2104f000, 0x91042580, 0xd708e0ff, 0x91042580, @@ -717,11 +716,11 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81521801, 0x2400060d, 0x040d6666, -0x230253d1, +0x230252d1, 0x7900003f, 0x2400010d, 0x000d6666, -0x230253d1, +0x230252d1, 0x69fd7309, 0x913d1880, 0x1f040000, @@ -769,7 +768,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813a188d, 0x24000019, 0x79000002, -0x2304cfd1, +0x2304d0d1, 0x10535300, 0x10333320, 0x10131340, @@ -800,13 +799,13 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81541800, 0x2400060d, 0x040d6666, -0x230253d1, +0x230252d1, 0x79000017, 0x1d058000, 0x81541800, 0x2400010d, 0x000d6666, -0x230253d1, +0x230252d1, 0x91541800, 0x69fd6204, 0x1f028000, @@ -858,10 +857,10 @@ const unsigned int Hiperface_DSL2_0[]= { 0x21018f00, 0x91001800, 0xc9070002, -0x21023200, +0x21023100, 0x91351800, 0xc9070002, -0x21023200, +0x21023100, 0x51005c2c, 0x110ff602, 0x49085c02, @@ -932,7 +931,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24003001, 0xd1066b0e, 0x2400010d, -0x230666d1, +0x230667d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -945,7 +944,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81531800, 0x7900003b, 0x2400020d, -0x230666d1, +0x230667d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -988,7 +987,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x230666d1, +0x230667d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1042,7 +1041,8 @@ const unsigned int Hiperface_DSL2_0[]= { 0x2400181b, 0xc9027a02, 0x01081b1b, -0x2101e800, +0x2101e700, +0xc901c460, 0x24001031, 0x91001800, 0xc9060007, @@ -1153,6 +1153,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1d008080, 0x81aa1800, 0x91031800, +0x117f0000, 0x590e0007, 0x91505880, 0x1f0a8080, @@ -1179,7 +1180,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x79000002, 0x1d030101, 0x81501801, -0x2101d500, +0x2101d400, 0x24000000, 0x814e1800, 0xd103c40a, @@ -1197,7 +1198,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81381800, 0x91411820, 0x60200002, -0x21023200, +0x21023100, 0x109d9d8b, 0x0901c880, 0x090288c0, @@ -1223,7 +1224,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304b6d1, +0x2304b7d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1243,7 +1244,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304b6d1, +0x2304b7d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1336,7 +1337,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x810b1800, 0x81441800, 0x2eff8383, -0x23027b9d, +0x23027a9d, 0x24000866, 0x2400000c, 0x2400002c, @@ -1366,7 +1367,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x9101185b, 0x51005b0e, 0x7900000d, -0x230623d1, +0x230624d1, 0x91dc388c, 0x240000e2, 0x91e21882, @@ -1374,7 +1375,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x100c0c2a, 0x106c6c4a, 0x102c2c6a, -0x230623d1, +0x230624d1, 0x0b01e2e2, 0x0501e2e2, 0x4f00e2ff, @@ -1384,13 +1385,13 @@ const unsigned int Hiperface_DSL2_0[]= { 0x240000ca, 0x24001f8d, 0x23016a9d, -0x2301f7d1, +0x2301f6d1, 0x0101caca, 0x6f02cafc, 0x240000ca, 0x2400198d, 0x23016a9d, -0x2301f7d1, +0x2301f6d1, 0x0101caca, 0x6f10cafc, 0x2400017b, @@ -1497,7 +1498,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b077200, 0x12001313, 0x0901f2f2, -0x23062fd1, +0x230630d1, 0x510e6506, 0x6f010df6, 0x10656546, @@ -1534,16 +1535,16 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd703ffff, 0x24001b8d, 0x23016a9d, -0x2305f59d, -0x23062fd1, +0x2305f69d, +0x230630d1, 0x6f010deb, 0x05012525, 0x4f0025f8, 0x24001025, 0x24001c8d, 0x23016a9d, -0x2305f59d, -0x23062fd1, +0x2305f69d, +0x230630d1, 0x6f010dd8, 0x05012525, 0x4f0025fa, @@ -1564,7 +1565,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x810d3801, 0x2400000d, 0x000d6666, -0x230253d1, +0x230252d1, 0x1f08c4c4, 0x110fe05d, 0x01085d5d, @@ -1578,10 +1579,10 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24ffff81, 0x0a00e1e1, 0x81e43881, -0x2301f7d1, +0x2301f6d1, 0x21001600, 0x24002005, -0x230261d1, +0x230260d1, 0x24000080, 0x2405a4eb, 0x2eff8992, @@ -1594,7 +1595,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x10000020, 0x0b018001, 0x14000130, -0x230276d1, +0x230275d1, 0x6f0005f6, 0x24001d05, 0xc918ff00, @@ -1606,7 +1607,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x10000020, 0x0b018001, 0x14000130, -0x230276d1, +0x230275d1, 0x6f0105f6, 0xc918ff00, 0x101f1f00, @@ -1623,8 +1624,8 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0501e0e0, 0x4f00e0ff, 0x1d007e7e, -0x230216d1, -0x2301f7d1, +0x230215d1, +0x2301f6d1, 0x209d0000, 0x91502181, 0x91502194, @@ -1710,4 +1711,4 @@ const unsigned int Hiperface_DSL2_0[]= { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2104ef00 }; +0x2104f000 }; diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 6819b66..d1d20e2 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -740,6 +740,8 @@ transport_layer_recv_msg_end: ;---------------------------------------------------- transport_layer_send_msg: ;TODO: reduce cycles +; Skip message processing until one v-frame is complete + qbbc transport_layer_send_msg_end, H_FRAME.flags, FLAG_NORMAL_FLOW ldi SEND_PARA, M_PAR_IDLE ;check if we discard any messages and reset parameter channel lbco ®_TMP0.b0, MASTER_REGS_CONST, SYS_CTRL, 1 @@ -935,6 +937,8 @@ transport_layer_no_qmlw_event: ; Update QMLW bits in ONLINE_STATUS registers lbco ®_TMP0.b0, MASTER_REGS_CONST, MASTER_QM, 1 + and REG_TMP0.b0, REG_TMP0.b0, 0x7f +; Set QMLW if value is < 14 qble transport_layer_online_status_qm_not_low, REG_TMP0.b0, 14 ; Set QMLW bits lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 From 0fe32fbc31454d4a9214a2da9491846a5a2ac328 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 22 Aug 2023 13:55:27 +0530 Subject: [PATCH 10/11] am64x/am243x: hdsl: Fix ONLINE_STATUS_1 register corruption - TEMP_REG1 was being used by QM_ADD and ONLINE STATUS update in v-frame processing - Update version to 0.4 Fixes: PINDSW-6487 Signed-off-by: Dhaval Khandla --- source/position_sense/hdsl/firmware/defines.inc | 2 +- .../hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h | 14 +++++++------- source/position_sense/hdsl/firmware/transport.asm | 15 ++++++++------- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc index 179f40a..b0be80d 100644 --- a/source/position_sense/hdsl/firmware/defines.inc +++ b/source/position_sense/hdsl/firmware/defines.inc @@ -35,7 +35,7 @@ FIRMWARE_VERSION_CODING .set 0x1 ; bit5..4 major number FIRMWARE_VERSION_MAJOR .set 0x0 ; bit3..0 minor number -FIRMWARE_VERSION_MINOR .set 0x3 +FIRMWARE_VERSION_MINOR .set 0x4 ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_CODING << 6) | (FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index 9167ea6..7299a62 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -704,16 +704,16 @@ const unsigned int Hiperface_DSL2_0[]= { 0x10121221, 0x81601881, 0xd104c40e, -0x91521801, -0x11db0101, +0x91521802, +0x11db0202, 0x5100980c, 0x913d1880, 0x1f050000, 0x813d1800, 0xc9052002, 0x2400269f, -0x1f050101, -0x81521801, +0x1f050202, +0x81521802, 0x2400060d, 0x040d6666, 0x230252d1, @@ -727,10 +727,10 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813d1800, 0xc9042002, 0x2400269f, -0x1f020101, -0x81521801, +0x1f020202, +0x81521802, 0x79000033, -0x81521801, +0x81521802, 0x0908f3e2, 0x10727202, 0x91a45800, diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index d1d20e2..9471fc4 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -111,8 +111,8 @@ transport_on_v_frame: sbco ®_TMP1, MASTER_REGS_CONST, VPOSCRC_TEMP, 2 ;transmission error? qbbs transport_on_v_frame_dont_update_qm, H_FRAME.flags, FLAG_ERR_VERT - lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1 - and REG_TMP1.b0, REG_TMP1.b0, (~((1< add 1 to QM +;Note: QM_ADD uses REG_TMP1 QM_ADD 1 ;check for special character: K29.7 is sent in first byte of vertical channel if slave error occured qbne transport_on_v_frame_check_pos, VERT_H.b3, K29_7 @@ -151,11 +152,11 @@ check_for_slave_error_on_v_frame: ldi r31.w0, PRU0_ARM_IRQ4 update_events_no_int5: ; Set ONLINE_STATUS_1_VPOS in ONLINE_STATUS_1 register - set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_1_VPOS - sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1 + set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_VPOS + sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1 qba transport_on_v_frame_exit transport_on_v_frame_check_pos: - sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1 + sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1 lsl REG_TMP2, CHANNEL.ch_verth, 8 mov REG_TMP2.b0, VERT_L.b3 ;first V-Frame? -> update FAST POS with SAFE POS From 47b87f5cf7dd98e755c9ae554a89339f6559bac3 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 22 Aug 2023 17:00:53 +0530 Subject: [PATCH 11/11] am64x/am243x: hdsl: Remove SUC instruction usage - SUC instruction does not work as expected Fixes: PINDSW-6531 Signed-off-by: Dhaval Khandla --- .../firmware/hdsl_master_icssg_300_mhz_bin.h | 52 ++++++++++--------- .../hdsl/firmware/transport.asm | 6 ++- 2 files changed, 32 insertions(+), 26 deletions(-) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index 7299a62..176bb86 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -55,7 +55,7 @@ */ const unsigned int Hiperface_DSL2_0[]= { -0x21067500, +0x21067700, 0x24000125, 0x2eff818f, 0x24001d8d, @@ -151,7 +151,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd104ff00, 0xd703ffff, 0x24002f1e, -0x2304669d, +0x2304689d, 0x05014545, 0x4f0045d2, 0x24000070, @@ -453,7 +453,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x69084502, 0x21028200, 0x69074502, -0x2102dd00, +0x2102df00, 0x51000c2b, 0x51015b04, 0x100c0c02, @@ -522,14 +522,14 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b024d00, 0x12006d6d, 0x09064d4d, -0x2103db00, +0x2103dd00, 0xd104ff00, 0xd703ffff, 0x106d6d1e, 0x511f0d03, 0x51190d02, 0x79000003, -0x23063cd1, +0x23063ed1, 0x7900001a, 0xd104ff00, 0xd703ffff, @@ -541,7 +541,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x511f0d12, 0x51190d11, 0xc901c402, -0x21032000, +0x21032200, 0x910c3c81, 0x240117e0, 0x04e1e0e0, @@ -636,7 +636,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00c0c0, 0x1f008181, 0x81505880, -0x2104f000, +0x2104f200, 0x91042580, 0xd708e0ff, 0x91042580, @@ -717,7 +717,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x2400060d, 0x040d6666, 0x230252d1, -0x7900003f, +0x79000041, 0x2400010d, 0x000d6666, 0x230252d1, @@ -729,13 +729,15 @@ const unsigned int Hiperface_DSL2_0[]= { 0x2400269f, 0x1f020202, 0x81521802, -0x79000033, +0x79000035, 0x81521802, 0x0908f3e2, 0x10727202, 0x91a45800, 0x0480d281, -0x06c093c1, +0x04c093c1, +0x5880d202, +0x0501c1c1, 0x10e1e1e2, 0xc91fe203, 0x1600e2e2, @@ -768,7 +770,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813a188d, 0x24000019, 0x79000002, -0x2304d0d1, +0x2304d2d1, 0x10535300, 0x10333320, 0x10131340, @@ -931,7 +933,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24003001, 0xd1066b0e, 0x2400010d, -0x230667d1, +0x230669d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -944,7 +946,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81531800, 0x7900003b, 0x2400020d, -0x230667d1, +0x230669d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -987,7 +989,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x230667d1, +0x230669d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1224,7 +1226,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304b7d1, +0x2304b9d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1244,7 +1246,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304b7d1, +0x2304b9d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1333,7 +1335,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81080580, 0x24001fc0, 0x810605c0, -0x24004300, +0x24004400, 0x810b1800, 0x81441800, 0x2eff8383, @@ -1367,7 +1369,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x9101185b, 0x51005b0e, 0x7900000d, -0x230624d1, +0x230626d1, 0x91dc388c, 0x240000e2, 0x91e21882, @@ -1375,7 +1377,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x100c0c2a, 0x106c6c4a, 0x102c2c6a, -0x230624d1, +0x230626d1, 0x0b01e2e2, 0x0501e2e2, 0x4f00e2ff, @@ -1498,7 +1500,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b077200, 0x12001313, 0x0901f2f2, -0x230630d1, +0x230632d1, 0x510e6506, 0x6f010df6, 0x10656546, @@ -1535,16 +1537,16 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd703ffff, 0x24001b8d, 0x23016a9d, -0x2305f69d, -0x230630d1, +0x2305f89d, +0x230632d1, 0x6f010deb, 0x05012525, 0x4f0025f8, 0x24001025, 0x24001c8d, 0x23016a9d, -0x2305f69d, -0x230630d1, +0x2305f89d, +0x230632d1, 0x6f010dd8, 0x05012525, 0x4f0025fa, @@ -1711,4 +1713,4 @@ const unsigned int Hiperface_DSL2_0[]= { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2104f000 }; +0x2104f200 }; diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 9471fc4..32f51de 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -164,7 +164,11 @@ transport_on_v_frame_not_first: ;check for LAST FAST POS and SAFE POS mismatch lbco ®_TMP0.b0, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS sub REG_TMP1.w0, VERT_L.w2, REG_TMP0.w0 - suc REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2 + sub REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2 + qble no_sub_carry, VERT_L.w2, REG_TMP0.w0 +; if carry is needed, subtract 1 separately + sub REG_TMP1.w2, REG_TMP1.w2, 1 +no_sub_carry: mov REG_TMP2, REG_TMP1 ;check if diff is neg, qbbc transport_on_v_frame_diff_pos, REG_TMP2, 31