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am243x: hdsl: Update the linker to define alignment of copy table

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Fixes: PINDSW-5516

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
This commit is contained in:
Dhaval Khandla 2024-01-08 19:09:04 +05:30
parent 8a3e4b1ee5
commit 0fb9cd68d1
6 changed files with 12 additions and 6 deletions
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3
examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -110,7 +110,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables, As this array is typecasted into a structure with 32-bit variables,
32b alignment is required 32b alignment is required
*/ */
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM .rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
} }
/* /*

3
examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -110,7 +110,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables, As this array is typecasted into a structure with 32-bit variables,
32b alignment is required 32b alignment is required
*/ */
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM .rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
} }
/* /*

3
examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -110,7 +110,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables, As this array is typecasted into a structure with 32-bit variables,
32b alignment is required 32b alignment is required
*/ */
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM .rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
} }
/* /*

3
examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -112,7 +112,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables, As this array is typecasted into a structure with 32-bit variables,
32b alignment is required 32b alignment is required
*/ */
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM .rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
} }
/* /*

3
examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -112,7 +112,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables, As this array is typecasted into a structure with 32-bit variables,
32b alignment is required 32b alignment is required
*/ */
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM .rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
} }
/* /*

3
examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -112,7 +112,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables, As this array is typecasted into a structure with 32-bit variables,
32b alignment is required 32b alignment is required
*/ */
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM .rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
} }
/* /*