diff --git a/examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 05f4194..e5f6c16 100644
--- a/examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -110,7 +110,8 @@ SECTIONS
     As this array is typecasted into a structure with 32-bit variables,
     32b alignment is required
     */
-	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2  :   {}  align(32) > MSRAM
+	.rodata.Hiperface_DSL2_0_TX_PRU_2       :   {}  align(32) > MSRAM
 }
 
 /*
diff --git a/examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index e049e56..54cf576 100644
--- a/examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -110,7 +110,8 @@ SECTIONS
     As this array is typecasted into a structure with 32-bit variables,
     32b alignment is required
     */
-	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2  :   {}  align(32) > MSRAM
+	.rodata.Hiperface_DSL2_0_TX_PRU_2       :   {}  align(32) > MSRAM
 }
 
 /*
diff --git a/examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 05f4194..e5f6c16 100644
--- a/examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -110,7 +110,8 @@ SECTIONS
     As this array is typecasted into a structure with 32-bit variables,
     32b alignment is required
     */
-	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2  :   {}  align(32) > MSRAM
+	.rodata.Hiperface_DSL2_0_TX_PRU_2       :   {}  align(32) > MSRAM
 }
 
 /*
diff --git a/examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index c035cd5..e1a0fb4 100644
--- a/examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -112,7 +112,8 @@ SECTIONS
     As this array is typecasted into a structure with 32-bit variables,
     32b alignment is required
     */
-	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2  :   {}  align(32) > MSRAM
+	.rodata.Hiperface_DSL2_0_TX_PRU_2       :   {}  align(32) > MSRAM
 }
 
 /*
diff --git a/examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 7e5f964..26ba074 100644
--- a/examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -112,7 +112,8 @@ SECTIONS
     As this array is typecasted into a structure with 32-bit variables,
     32b alignment is required
     */
-	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2  :   {}  align(32) > MSRAM
+	.rodata.Hiperface_DSL2_0_TX_PRU_2       :   {}  align(32) > MSRAM
 }
 
 /*
diff --git a/examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index c035cd5..e1a0fb4 100644
--- a/examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -112,7 +112,8 @@ SECTIONS
     As this array is typecasted into a structure with 32-bit variables,
     32b alignment is required
     */
-	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2  :   {}  align(32) > MSRAM
+	.rodata.Hiperface_DSL2_0_TX_PRU_2       :   {}  align(32) > MSRAM
 }
 
 /*