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разделение на CPU1 и 2

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seklyuts 2024-05-03 11:19:05 +03:00
parent 1686089a10
commit 4fb36f9e64
23 changed files with 436 additions and 432 deletions
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Projects/epwm_test/Start_rfm.pmp
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Projects/epwm_test_biss_c_cpu1/Start_rfm.pmp
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Projects/epwm_test_biss_c_cpu1/epwm_test.c
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@ -17,19 +17,19 @@
#include "f28x_project.h" #include "f28x_project.h"
#include "init_perif.h" #include "init_perif.h"
#include "frmmstr_run.h" #include "frmmstr_run.h"
#include "ExtEEPROM.h"
#include "adc_init.h" #include "adc_init.h"
#include "biss.h" #include "biss.h"
void main(void) void main(void)
{ {
InitPerif(); InitPerif();
for(;;) for(;;)
{ {
// asm (" NOP"); // asm (" NOP");
frmmstr_run(); // frmmstr_run();
AdcRun(); // AdcRun();
BissClkgenRun(); // BissClkgenRun();
} }
} }

27
Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_init.c
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@ -136,22 +136,29 @@ void PWMInitInterruptEn(void)
PieVectTable.EPWM4_INT = &epwm4_isr; PieVectTable.EPWM4_INT = &epwm4_isr;
PieVectTable.EPWM8_INT = &epwm8_isr; PieVectTable.EPWM8_INT = &epwm8_isr;
PieVectTable.EPWM11_INT = &epwm11_isr; PieVectTable.EPWM11_INT = &epwm11_isr;
EDIS; // This is needed to disable write to EALLOW protected registers EDIS;
// This is needed to disable write to EALLOW protected registers
EPwm1Regs.ETCLR.bit.INT = 1;
EPwm2Regs.ETCLR.bit.INT = 1;
EPwm8Regs.ETCLR.bit.INT = 1;
EPwm11Regs.ETCLR.bit.INT = 1;
// Enable CPU INT3 which is connected to EPWM1-3 INT: // Enable CPU INT3 which is connected to EPWM1-3 INT:
// //
IER |= M_INT3; IER |= M_INT3;
// //
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150) // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150)
// //
PieCtrlRegs.PIEIER3.bit.INTx1 = 1; PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1; PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
} }
void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed) void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
@ -183,10 +190,8 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
EALLOW; EALLOW;
EPwmRegs[Num]->TZCTL.bit.TZA = 3; EPwmRegs[Num]->TZCTL.bit.TZA = 3;
EPwmRegs[Num]->TZCTL.bit.TZB = 3; EPwmRegs[Num]->TZCTL.bit.TZB = 3;
EPwmRegs[Num]->TZFRC.all = 4; EPwmRegs[Num]->TZFRC.all = 4;
EDIS; //<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TZ-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> EDIS; //
// //
// Set actions // Set actions
// //
@ -234,10 +239,6 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
} }
EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL; EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL;
// EPwm1_DB_Direction = COUNT_UP;
//
//
if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA; else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA;

12
Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_interrupts.c
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@ -1,7 +1,7 @@
/* /*
* interrupts.c * interrupts.c
* *
* Created on: 21 авг. 2023 г. * Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts * Author: seklyuts
*/ */
@ -25,7 +25,7 @@ volatile uint16_t PWM_out = 2500;
uint16_t Fault = 0, Fault_fix = 0, Ready = 0, Ready_Fix = 0; uint16_t Fault = 0, Fault_fix = 0, Ready = 0, Ready_Fix = 0;
uint16_t counter1s=0; uint16_t counter1s=0;
uint16_t FaultABC = 0, FaultABCFix = 0; uint16_t FaultABC = 0, FaultABCFix = 0;
uint16_t PwmFlagStartADC = 0; uint16_t PwmFlagStartCurrentMeashure = 0;
extern volatile struct EPWM_REGS * EPwmRegs[17]; extern volatile struct EPWM_REGS * EPwmRegs[17];
typedef struct typedef struct
@ -125,9 +125,9 @@ __interrupt void epwm2_isr(void)
// //
EPwm2Regs.ETCLR.bit.INT = 1; EPwm2Regs.ETCLR.bit.INT = 1;
TimerBaseTimeoutInc(); TimerBaseTimeoutInc();
if(PwmFlagStartADC) /// ацп не запустился, ток не был измерен if(PwmFlagStartCurrentMeashure) /// Не были отработаны измерения тока в сигма-дельта и не было запущено векторное управление
{ {
PwmFlagStartADC = 0; PwmFlagStartCurrentMeashure = 0;
FMSTREnableSet(); FMSTREnableSet();
AdcStartSet(); AdcStartSet();
BissStartSet(); BissStartSet();
@ -254,7 +254,7 @@ __interrupt void epwm11_isr(void)
if(TestStopSync != 3) sdfm_start_conversion_current(); if(TestStopSync != 3) sdfm_start_conversion_current();
PwmFlagStartADC = 1; PwmFlagStartCurrentMeashure = 1;
EPwm11Regs.ETCLR.bit.INT = 1; EPwm11Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
// Gpio4out(0); // Gpio4out(0);
@ -263,7 +263,7 @@ __interrupt void epwm11_isr(void)
void pwm_clr_PwmFlagStartADC(void) void pwm_clr_PwmFlagStartADC(void)
{ {
PwmFlagStartADC = 0; PwmFlagStartCurrentMeashure = 0;
} }
// //

20
Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.c
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@ -94,6 +94,7 @@ int16_t sdfmAdcErr[8] = {0,0,0,0,0,0,0,0};
int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0}; int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0};
uint16_t startInitCurrent = 0; uint16_t startInitCurrent = 0;
uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM}; uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM};
uint16_t AllInitDone =0;
uint16_t sdfmIndex = 0; uint16_t sdfmIndex = 0;
int16_t Test_I[16]; int16_t Test_I[16];
uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0}; uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0};
@ -179,8 +180,18 @@ void SdfmInitInterruptEn(void)
PieVectTable.SDFM1_INT = &Sdfm1_ISR; PieVectTable.SDFM1_INT = &Sdfm1_ISR;
PieVectTable.SDFM2_INT = &Sdfm2_ISR; PieVectTable.SDFM2_INT = &Sdfm2_ISR;
IER |= M_INT5; IER |= M_INT5;
Sdfm_clearFlagRegister(SDFM1,0xFFFFFFFF);
Sdfm_clearFlagRegister(SDFM2,0xFFFFFFFF);
PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 interrupt enabled PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 interrupt enabled
PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 interrupt enabled PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 interrupt enabled
PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
EDIS;
}
void SdfmTypeInit(void)
{
EALLOW;
DevCfgRegs.SDFMTYPE.all = 0x8000;
EDIS; EDIS;
} }
@ -359,7 +370,14 @@ void sdfm_check_all_current_measurements_was_done(void)
if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS) if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS)
{ {
sdfmIndex = 0; sdfmIndex = 0;
vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]); if(!AllInitDone)
{
if((initDone[SDFM_IA] == 0xFF)&&(initDone[SDFM_IB] == 0xFF)&&(initDone[SDFM_IC] == 0xFF)) AllInitDone = 1;
}
else
{
vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]);
}
} }
} }

3
Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.h
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@ -1,7 +1,7 @@
/* /*
* sdfm.h * sdfm.h
* *
* Created on: 25 àâã. 2023 ã. * Created on: 25 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts * Author: seklyuts
*/ */
@ -49,6 +49,7 @@ void SdfmInitInterruptEn(void);
void SdfmInit(void); void SdfmInit(void);
void sdfm_start_conversion_current(void); void sdfm_start_conversion_current(void);
int16_t sdfm_get(int16_t N); int16_t sdfm_get(int16_t N);
void SdfmTypeInit(void);

102
Projects/epwm_test_biss_c_cpu1/src/frm_uart.c
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@ -8,6 +8,10 @@
//#include "f2838x_pinmux.h" //#include "f2838x_pinmux.h"
#include "frm_uart.h" #include "frm_uart.h"
#define LSPCLK_HZ 50000000.0
#define BAUD 19200.0
#define BRR LSPCLK_HZ/(BAUD*8) + 1
uint16_t frmEn = 0; uint16_t frmEn = 0;
@ -26,57 +30,40 @@ void FMSTREnableSet(void)
frmEn = 1; frmEn = 1;
} }
void FRMGPIOInit(void)
{
GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
EALLOW;
GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
GpioDataRegs.GPADAT.bit.GPIO21 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
EDIS;
GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
}
void FRMUartInit(void) void FRMUartInit(void)
{ {
FMSTR_Init(); FMSTR_Init();
CpuSysRegs.PCLKCR7.bit.SCI_A = 1; CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
// For this example, only init the pins for the SCI-A port.
// GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits
// GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS
// These functions are found in the f2838x_gpio.c file.
// EALLOW;
// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up
// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;
//
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; //rx
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; //tx
// EDIS;
//
// EALLOW;
// GpioCtrlRegs.GPCPUD.bit.GPIO84 = 1; //tx
// GpioCtrlRegs.GPCPUD.bit.GPIO85 = 0;
//
// GpioCtrlRegs.GPCMUX2.bit.GPIO28 = 1; //
// GpioCtrlRegs.GPCMUX2.bit.GPIO29 = 1; //
// EDIS;
GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
EALLOW;
GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
GpioDataRegs.GPADAT.bit.GPIO21 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
EDIS;
// GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1);
// GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL);
// GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1);
GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
// //
// Note: Clocks were turned on to the SCIA peripheral // Note: Clocks were turned on to the SCIA peripheral
// in the InitSysCtrl() function // in the InitSysCtrl() function
// //
EALLOW;
SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
// No parity,8 char bits, // No parity,8 char bits,
// async mode, idle-line protocol // async mode, idle-line protocol
@ -86,36 +73,13 @@ void FRMUartInit(void)
SciaRegs.SCICTL2.bit.TXINTENA = 0; SciaRegs.SCICTL2.bit.TXINTENA = 0;
SciaRegs.SCICTL2.bit.RXBKINTENA = 0; SciaRegs.SCICTL2.bit.RXBKINTENA = 0;
// uint16_t Brr = BRR;
// SCIA at 9600 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B //8A SciaRegs.SCIHBAUD.all = 0xFF & (Brr>>8);//0x0002;
// @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86. SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B;
//
//
// SCIA at 19200 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x45.
//
//
// SCIA at 38400 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0xA2.
//
//
// SCIA at 56000 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6F.
//
//
// SCIA at 57600 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6C (6B).
//
//
// SCIA at 115200 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x35.
//
SciaRegs.SCIHBAUD.all = 0x0002;
SciaRegs.SCILBAUD.all = 0x008B;
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
EDIS;
FMSTREnableSet(); FMSTREnableSet();
} }

3
Projects/epwm_test_biss_c_cpu1/src/frm_uart.h
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@ -1,7 +1,7 @@
/* /*
* frm_uart.h * frm_uart.h
* *
* Created on: 21 àâã. 2023 ã. * Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts * Author: seklyuts
*/ */
@ -23,6 +23,7 @@ void FMSTR_SCI_TD(void);
FMSTR_SCISR FMSTR_SCI_RDCLRSR(void); FMSTR_SCISR FMSTR_SCI_RDCLRSR(void);
//void FMSTR_InitSerial(void) ; //void FMSTR_InitSerial(void) ;
void FRMUartInit(void); void FRMUartInit(void);
void FRMGPIOInit(void);
uint16_t FMSTRIsEnable(void); uint16_t FMSTRIsEnable(void);
void FMSTREnableClr(void); void FMSTREnableClr(void);

2
Projects/epwm_test_biss_c_cpu1/src/frmmstr_run.c
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@ -30,11 +30,13 @@ static uint16_t diod = 0;
diod++; diod++;
if(diod > 7) diod = 0; if(diod > 7) diod = 0;
Gpio_rainbow(diod); Gpio_rainbow(diod);
//FMSTR_SCI_PUTCHAR(0xA5);
} }
} }
FMSTR_Poll(); FMSTR_Poll();
FMSTR_Recorder(); FMSTR_Recorder();
FMSTREnableClr(); FMSTREnableClr();
Gpio95out(Rele); Gpio95out(Rele);
} }
} }

88
Projects/epwm_test_biss_c_cpu1/src/init_perif.c
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@ -1,7 +1,7 @@
/* /*
* init_perif.c * init_perif.c
* *
* Created on: 21 àâã. 2023 ã. * Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts * Author: seklyuts
*/ */
@ -23,6 +23,33 @@
#include "adc_init.h" #include "adc_init.h"
#include "biss.h" #include "biss.h"
#define TO_CPU1 0
#define TO_CPU2 1
#define CONNECT_SD1(x) EALLOW; DevCfgRegs.CPUSEL4.bit.SD1 = x; EDIS
#define CONNECT_SD2(x) EALLOW; DevCfgRegs.CPUSEL4.bit.SD2 = x; EDIS
#define CONNECT_PWM1(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM1 = x; EDIS
#define CONNECT_PWM2(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM2 = x; EDIS
#define CONNECT_PWM3(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM3 = x; EDIS
#define CONNECT_PWM4(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM4 = x; EDIS
#define CONNECT_PWM5(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM5 = x; EDIS
#define CONNECT_PWM6(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM6 = x; EDIS
#define CONNECT_PWM7(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM7 = x; EDIS
#define CONNECT_PWM8(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM8 = x; EDIS
#define CONNECT_PWM9(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM9 = x; EDIS
#define CONNECT_PWM10(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM10 = x; EDIS
#define CONNECT_PWM11(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM11 = x; EDIS
#define CONNECT_PWM12(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM12 = x; EDIS
#define CONNECT_PWM13(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM13 = x; EDIS
#define CONNECT_PWM14(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM14 = x; EDIS
#define CONNECT_PWM15(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM15 = x; EDIS
#define CONNECT_PWM16(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM16 = x; EDIS
#define CONNECT_SCIA(x) EALLOW; DevCfgRegs.CPUSEL5.bit.SCI_A = x; EDIS
void InitPerif(void) void InitPerif(void)
{ {
@ -30,6 +57,11 @@ void InitPerif(void)
GpioDiodInit(); GpioDiodInit();
GpioSetGreen(); GpioSetGreen();
EALLOW;
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
EDIS;
InitSysCtrl(); InitSysCtrl();
GpioSetBlue(); GpioSetBlue();
@ -65,33 +97,41 @@ void InitPerif(void)
InitPieVectTable(); InitPieVectTable();
GpioInit(); GpioInit();
//
SdfmInitEnable();
SdfmInit();
SdfmGpioInit(); SdfmGpioInit();
SdfmInitInterruptEn(); SdfmTypeInit();
// // SdfmInitEnable();
PWMInitEnable(); // SdfmInit();
PWMAllInit(); // SdfmInitInterruptEn();
PWMGpioInit(); PWMGpioInit();
PWMInitInterruptEn(); // PWMInitEnable();
// PWMAllInit();
// PWMInitInterruptEn();
vectorInitCurrLoop();
SpiCInit();
SpiCGpioInit();
BissGpioInit();
BissInit();
// SpiGpioInit();
// SpiInit();
// I2CMasterGpioInit();
// I2CMasterInit(I2C_OWN_ADDRESS,I2C_SLAVE_ADDRESS);
FRMUartInit();
// vectorInitCurrLoop(); // vectorInitCurrLoop();
// SpiCGpioInit();
// SpiCInit();
// BissGpioInit();
// BissInit();
FRMGPIOInit();
// FRMUartInit();
CONNECT_SD1(TO_CPU2);
CONNECT_SD2(TO_CPU2);
CONNECT_PWM1(TO_CPU2);
CONNECT_PWM2(TO_CPU2);
CONNECT_PWM5(TO_CPU2);
CONNECT_PWM7(TO_CPU2);
CONNECT_PWM8(TO_CPU2);
CONNECT_PWM3(TO_CPU2);
CONNECT_PWM11(TO_CPU2);
CONNECT_PWM12(TO_CPU2);
CONNECT_SCIA(TO_CPU2);
// ConfigureADC(); // ConfigureADC();
// //

4
Projects/epwm_test_biss_c_cpu2/.cproject
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@ -99,7 +99,7 @@
</toolChain> </toolChain>
</folderInfo> </folderInfo>
<sourceEntries> <sourceEntries>
<entry excluding="2838x_FLASH_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> <entry excluding="2838x_FLASH_lnk_cpu2.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries> </sourceEntries>
</configuration> </configuration>
</storageModule> </storageModule>
@ -414,7 +414,7 @@
</toolChain> </toolChain>
</folderInfo> </folderInfo>
<sourceEntries> <sourceEntries>
<entry excluding="2838x_RAM_combined_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> <entry excluding="lib/f2838x_epwm.c|src/Peripherals/gpio_init.c|2838x_RAM_combined_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries> </sourceEntries>
</configuration> </configuration>
</storageModule> </storageModule>

BIN
Projects/epwm_test_biss_c_cpu2/Start_rfm.pmp
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Binary file not shown.

4
Projects/epwm_test_biss_c_cpu2/epwm_test.c
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@ -17,18 +17,18 @@
#include "f28x_project.h" #include "f28x_project.h"
#include "init_perif.h" #include "init_perif.h"
#include "frmmstr_run.h" #include "frmmstr_run.h"
#include "ExtEEPROM.h"
#include "adc_init.h" #include "adc_init.h"
#include "biss.h" #include "biss.h"
void main(void) void main(void)
{ {
InitPerif(); InitPerif();
for(;;) for(;;)
{ {
// asm (" NOP"); // asm (" NOP");
frmmstr_run(); frmmstr_run();
AdcRun(); // AdcRun();
BissClkgenRun(); BissClkgenRun();
} }
} }

27
Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_init.c
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@ -136,22 +136,29 @@ void PWMInitInterruptEn(void)
PieVectTable.EPWM4_INT = &epwm4_isr; PieVectTable.EPWM4_INT = &epwm4_isr;
PieVectTable.EPWM8_INT = &epwm8_isr; PieVectTable.EPWM8_INT = &epwm8_isr;
PieVectTable.EPWM11_INT = &epwm11_isr; PieVectTable.EPWM11_INT = &epwm11_isr;
EDIS; // This is needed to disable write to EALLOW protected registers EDIS;
// This is needed to disable write to EALLOW protected registers
EPwm1Regs.ETCLR.bit.INT = 1;
EPwm2Regs.ETCLR.bit.INT = 1;
EPwm8Regs.ETCLR.bit.INT = 1;
EPwm11Regs.ETCLR.bit.INT = 1;
// Enable CPU INT3 which is connected to EPWM1-3 INT: // Enable CPU INT3 which is connected to EPWM1-3 INT:
// //
IER |= M_INT3; IER |= M_INT3;
// //
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150) // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150)
// //
PieCtrlRegs.PIEIER3.bit.INTx1 = 1; PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1; PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
} }
void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed) void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
@ -183,10 +190,8 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
EALLOW; EALLOW;
EPwmRegs[Num]->TZCTL.bit.TZA = 3; EPwmRegs[Num]->TZCTL.bit.TZA = 3;
EPwmRegs[Num]->TZCTL.bit.TZB = 3; EPwmRegs[Num]->TZCTL.bit.TZB = 3;
EPwmRegs[Num]->TZFRC.all = 4; EPwmRegs[Num]->TZFRC.all = 4;
EDIS; //<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TZ-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> EDIS; //
// //
// Set actions // Set actions
// //
@ -234,10 +239,6 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
} }
EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL; EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL;
// EPwm1_DB_Direction = COUNT_UP;
//
//
if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA; else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA;

12
Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_interrupts.c
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@ -1,7 +1,7 @@
/* /*
* interrupts.c * interrupts.c
* *
* Created on: 21 авг. 2023 г. * Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts * Author: seklyuts
*/ */
@ -25,7 +25,7 @@ volatile uint16_t PWM_out = 2500;
uint16_t Fault = 0, Fault_fix = 0, Ready = 0, Ready_Fix = 0; uint16_t Fault = 0, Fault_fix = 0, Ready = 0, Ready_Fix = 0;
uint16_t counter1s=0; uint16_t counter1s=0;
uint16_t FaultABC = 0, FaultABCFix = 0; uint16_t FaultABC = 0, FaultABCFix = 0;
uint16_t PwmFlagStartADC = 0; uint16_t PwmFlagStartCurrentMeashure = 0;
extern volatile struct EPWM_REGS * EPwmRegs[17]; extern volatile struct EPWM_REGS * EPwmRegs[17];
typedef struct typedef struct
@ -125,9 +125,9 @@ __interrupt void epwm2_isr(void)
// //
EPwm2Regs.ETCLR.bit.INT = 1; EPwm2Regs.ETCLR.bit.INT = 1;
TimerBaseTimeoutInc(); TimerBaseTimeoutInc();
if(PwmFlagStartADC) /// ацп не запустился, ток не был измерен if(PwmFlagStartCurrentMeashure) /// Не были отработаны измерения тока в сигма-дельта и не было запущено векторное управление
{ {
PwmFlagStartADC = 0; PwmFlagStartCurrentMeashure = 0;
FMSTREnableSet(); FMSTREnableSet();
AdcStartSet(); AdcStartSet();
BissStartSet(); BissStartSet();
@ -254,7 +254,7 @@ __interrupt void epwm11_isr(void)
if(TestStopSync != 3) sdfm_start_conversion_current(); if(TestStopSync != 3) sdfm_start_conversion_current();
PwmFlagStartADC = 1; PwmFlagStartCurrentMeashure = 1;
EPwm11Regs.ETCLR.bit.INT = 1; EPwm11Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
// Gpio4out(0); // Gpio4out(0);
@ -263,7 +263,7 @@ __interrupt void epwm11_isr(void)
void pwm_clr_PwmFlagStartADC(void) void pwm_clr_PwmFlagStartADC(void)
{ {
PwmFlagStartADC = 0; PwmFlagStartCurrentMeashure = 0;
} }
// //

25
Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.c
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@ -94,6 +94,7 @@ int16_t sdfmAdcErr[8] = {0,0,0,0,0,0,0,0};
int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0}; int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0};
uint16_t startInitCurrent = 0; uint16_t startInitCurrent = 0;
uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM}; uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM};
uint16_t AllInitDone =0;
uint16_t sdfmIndex = 0; uint16_t sdfmIndex = 0;
int16_t Test_I[16]; int16_t Test_I[16];
uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0}; uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0};
@ -179,20 +180,29 @@ void SdfmInitInterruptEn(void)
PieVectTable.SDFM1_INT = &Sdfm1_ISR; PieVectTable.SDFM1_INT = &Sdfm1_ISR;
PieVectTable.SDFM2_INT = &Sdfm2_ISR; PieVectTable.SDFM2_INT = &Sdfm2_ISR;
IER |= M_INT5; IER |= M_INT5;
Sdfm_clearFlagRegister(SDFM1,0xFFFFFFFF);
Sdfm_clearFlagRegister(SDFM2,0xFFFFFFFF);
PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 interrupt enabled PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 interrupt enabled
PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 interrupt enabled PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 interrupt enabled
PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
EDIS; EDIS;
} }
//void SdfmTypeInit(void)
//{
// EALLOW;
// DevCfgRegs.SDFMTYPE.all = 0x8000;
// EDIS;
//}
void SdfmInit(void) void SdfmInit(void)
{ {
uint16_t HLT, LLT; uint16_t HLT, LLT;
// //
// Configure SDFM type to 0 // Configure SDFM type to 0
// //
EALLOW;
DevCfgRegs.SDFMTYPE.all = 0x8000;
EDIS;
// //
// Input Control Module // Input Control Module
// //
@ -359,7 +369,14 @@ void sdfm_check_all_current_measurements_was_done(void)
if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS) if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS)
{ {
sdfmIndex = 0; sdfmIndex = 0;
vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]); if(!AllInitDone)
{
if((initDone[SDFM_IA] == 0xFF)&&(initDone[SDFM_IB] == 0xFF)&&(initDone[SDFM_IC] == 0xFF)) AllInitDone = 1;
}
else
{
vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]);
}
} }
} }

3
Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.h
View File

@ -1,7 +1,7 @@
/* /*
* sdfm.h * sdfm.h
* *
* Created on: 25 àâã. 2023 ã. * Created on: 25 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts * Author: seklyuts
*/ */
@ -49,6 +49,7 @@ void SdfmInitInterruptEn(void);
void SdfmInit(void); void SdfmInit(void);
void sdfm_start_conversion_current(void); void sdfm_start_conversion_current(void);
int16_t sdfm_get(int16_t N); int16_t sdfm_get(int16_t N);
void SdfmTypeInit(void);

352
Projects/epwm_test_biss_c_cpu2/src/Peripherals/spi_init.c
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@ -1,7 +1,7 @@
/* /*
* spi_init.c * spi_init.c
* *
* Created on: 5 ñåíò. 2023 ã. * Created on: 5 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts * Author: seklyuts
*/ */
@ -93,66 +93,66 @@ void SpiAInit(void)
SpiaRegs.SPICCR.bit.SPISWRESET = 1; SpiaRegs.SPICCR.bit.SPISWRESET = 1;
} }
void SpiAGpioInit(void) //void SpiAGpioInit(void)
{ //{
EALLOW; // EALLOW;
//
// // //
// Enable internal pull-up for the selected pins // // Enable internal pull-up for the selected pins
// // //
// Pull-ups can be enabled or disabled by the user. // // Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins. // // This will enable the pullups for the specified pins.
// // //
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on (SPISIMOA) // GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on (SPISIMOA)
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on (SPISOMIA) // GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on (SPISOMIA)
GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on (SPICLKA) // GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on (SPICLKA)
GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up on (SPISTEA) // GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up on (SPISTEA)
//
// // //
// Set qualification for selected pins to asynch only // // Set qualification for selected pins to asynch only
// // //
// This will select asynch (no qualification) for the selected pins. // // This will select asynch (no qualification) for the selected pins.
// // //
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input (SPISIMOA) // GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input (SPISIMOA)
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input (SPISOMIA) // GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input (SPISOMIA)
GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3; // Asynch input (SPICLKA) // GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3; // Asynch input (SPICLKA)
GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 3; // Asynch input (SPISTEA) // GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 3; // Asynch input (SPISTEA)
//
// // //
// Configure SPI-A pins // // Configure SPI-A pins
// // //
// This specifies which of the possible GPIO pins will be SPI functional // // This specifies which of the possible GPIO pins will be SPI functional
// pins. // // pins.
// // //
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 3; // Configure GPIO32 as SPISIMOA // GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 3; // Configure GPIO32 as SPISIMOA
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 3; // Configure GPIO33 as SPISOMIA // GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 3; // Configure GPIO33 as SPISOMIA
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // Configure GPIO34 as SPICLKA // GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // Configure GPIO34 as SPICLKA
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA // GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA
//
//
// SPI_PROGRAM_CS_GPAMUX1 = 0;//program CS for BL25CM1A
// SPI_PROGRAM_CS_GPAGMUX1 = 0;
// SPI_PROGRAM_CS_GPADIR = 1;
// SPI_PROGRAM_CS_GPADAT = 0;
//
// EDIS;
//}
SPI_PROGRAM_CS_GPAMUX1 = 0;//program CS for BL25CM1A //void spi_TurnOnCS1_GD25Q16E(void)
SPI_PROGRAM_CS_GPAGMUX1 = 0; //{
SPI_PROGRAM_CS_GPADIR = 1; // EALLOW;
SPI_PROGRAM_CS_GPADAT = 0; // GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA
// EDIS;
EDIS; //}
} //
//void spi_TurnOffCS1_GD25Q16E(void)
//{
void spi_TurnOnCS1_GD25Q16E(void) // EALLOW;
{ // GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0;
EALLOW; // GpioDataRegs.GPBDAT.bit.GPIO35 = 1;
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA // EDIS;
EDIS; //}
}
void spi_TurnOffCS1_GD25Q16E(void)
{
EALLOW;
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0;
GpioDataRegs.GPBDAT.bit.GPIO35 = 1;
EDIS;
}
void Gpio_SPI_CS_BL25CM1A(uint16_t out_bit) void Gpio_SPI_CS_BL25CM1A(uint16_t out_bit)
{ {
@ -250,68 +250,68 @@ void SpiBInit(void)
SpibRegs.SPICCR.bit.SPISWRESET = 1; SpibRegs.SPICCR.bit.SPISWRESET = 1;
} }
void SpiBGpioInit(void) //void SpiBGpioInit(void)
{ //{
EALLOW; // EALLOW;
//
// // //
// Enable internal pull-up for the selected pins // // Enable internal pull-up for the selected pins
// // //
// Pull-ups can be enabled or disabled by the user. // // Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins. // // This will enable the pullups for the specified pins.
// // //
GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on GPIO16 (SPISIMOB) // GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on GPIO16 (SPISIMOB)
// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO17 (SPISOMIB) //// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO17 (SPISOMIB)
//
GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on GPIO18 (SPICLKB) // GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on GPIO18 (SPICLKB)
// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO18 (SPICLKB) //// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO18 (SPICLKB)
//
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO19 (SPISTEB) // GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO19 (SPISTEB)
//
// // //
// Set qualification for selected pins to asynch only // // Set qualification for selected pins to asynch only
// // //
// This will select asynch (no qualification) for the selected pins. // // This will select asynch (no qualification) for the selected pins.
// // //
GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input GPIO16 (SPISIMOB) // GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input GPIO16 (SPISIMOB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO17 (SPISOMIB) //// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO17 (SPISOMIB)
//
GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input GPIO18 (SPICLKB) // GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input GPIO18 (SPICLKB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO18 (SPICLKB) //// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO18 (SPICLKB)
//
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO19 (SPISTEB) // GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO19 (SPISTEB)
//
//
GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0; // GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;
GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0; // GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0;
GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1; // GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1;
GpioDataRegs.GPDDAT.bit.GPIO99 = 0; // GpioDataRegs.GPDDAT.bit.GPIO99 = 0;
//
// // //
// Configure SPI-A pins // // Configure SPI-A pins
// // //
// This specifies which of the possible GPIO pins will be SPI functional // // This specifies which of the possible GPIO pins will be SPI functional
// pins. // // pins.
// // //
GPIO_SetupPinMux(100, 0, 6); // GPIO_SetupPinMux(100, 0, 6);
// GPIO_SetupPinMux(25, 0, 6); //// GPIO_SetupPinMux(25, 0, 6);
//
GPIO_SetupPinMux(102, 0, 6); // GPIO_SetupPinMux(102, 0, 6);
// GPIO_SetupPinMux(26, 0, 6); //// GPIO_SetupPinMux(26, 0, 6);
//
GPIO_SetupPinMux(27, 0, 6); // GPIO_SetupPinMux(27, 0, 6);
// SpibRegs.SPITXBUF = 0xFFFF; //// SpibRegs.SPITXBUF = 0xFFFF;
//
// GpioCtrlRegs.GPAMUX1.bit.GPIO24 = 2; // Configure GPIO16 as SPISIMOA //// GpioCtrlRegs.GPAMUX1.bit.GPIO24 = 2; // Configure GPIO16 as SPISIMOA
// GpioCtrlRegs.GPAMUX1.bit.GPIO25 = 2; // Configure GPIO17 as SPISOMIA //// GpioCtrlRegs.GPAMUX1.bit.GPIO25 = 2; // Configure GPIO17 as SPISOMIA
// GpioCtrlRegs.GPAMUX1.bit.GPIO26 = 2; // Configure GPIO18 as SPICLKA //// GpioCtrlRegs.GPAMUX1.bit.GPIO26 = 2; // Configure GPIO18 as SPICLKA
// GpioCtrlRegs.GPAMUX1.bit.GPIO27 = 2; // Configure GPIO19 as SPISTEA //// GpioCtrlRegs.GPAMUX1.bit.GPIO27 = 2; // Configure GPIO19 as SPISTEA
// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO16 as SPISIMOA //// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO16 as SPISIMOA
// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO17 as SPISOMIA //// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO17 as SPISOMIA
// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO18 as SPICLKA //// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO18 as SPICLKA
// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO19 as SPISTEA //// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO19 as SPISTEA
EDIS; // EDIS;
} //}
void transmitBData(uint16_t a) void transmitBData(uint16_t a)
{ {
@ -416,61 +416,61 @@ void SpiCInit(void)
} }
void SpiCGpioInit(void) //void SpiCGpioInit(void)
{ //{
EALLOW; // EALLOW;
//
// // //
// Enable internal pull-up for the selected pins // // Enable internal pull-up for the selected pins
// // //
// Pull-ups can be enabled or disabled by the user. // // Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins. // // This will enable the pullups for the specified pins.
// // //
GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on (SPISIMOB) // GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on (SPISIMOB)
//
//
GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on (SPICLKB) // GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on (SPICLKB)
//
//
GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0; // Enable pull-up on (SPISTEB) // GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0; // Enable pull-up on (SPISTEB)
//
// // //
// Set qualification for selected pins to asynch only // // Set qualification for selected pins to asynch only
// // //
// This will select asynch (no qualification) for the selected pins. // // This will select asynch (no qualification) for the selected pins.
// // //
GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input(SPISIMOB) // GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input(SPISIMOB)
//
//
GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input(SPICLKB) // GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input(SPICLKB)
//
//
GpioCtrlRegs.GPCQSEL1.bit.GPIO72 = 3; // Asynch input(SPISTEB) // GpioCtrlRegs.GPCQSEL1.bit.GPIO72 = 3; // Asynch input(SPISTEB)
//
//
GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0; // GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;
GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0; // GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0;
GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1; // GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1;
GpioDataRegs.GPDDAT.bit.GPIO99 = 0; // GpioDataRegs.GPDDAT.bit.GPIO99 = 0;
//
// // //
// Configure SPI-A pins // // Configure SPI-A pins
// // //
// This specifies which of the possible GPIO pins will be SPI functional // // This specifies which of the possible GPIO pins will be SPI functional
// pins. // // pins.
// // //
GPIO_SetupPinMux(100, 0, 6); // GPIO_SetupPinMux(100, 0, 6);
//
//
GPIO_SetupPinMux(102, 0, 6); // GPIO_SetupPinMux(102, 0, 6);
//
//
GPIO_SetupPinMux(72, 0, 15); // GPIO_SetupPinMux(72, 0, 15);
//
//
//
EDIS; // EDIS;
} //}
void transmitCData(uint16_t a) void transmitCData(uint16_t a)
{ {

34
Projects/epwm_test_biss_c_cpu2/src/biss.c
View File

@ -1,7 +1,7 @@
/* /*
* biss.c * biss.c
* *
* Created on: 26 äåê. 2023 ã. * Created on: 26 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts * Author: seklyuts
*/ */
#include "f28x_project.h" #include "f28x_project.h"
@ -64,22 +64,22 @@ void BissInit(void)
void BissGpioInit(void) //void BissGpioInit(void)
{ //{
EALLOW; // EALLOW;
//
GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 2;//14 = 1110 // GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 2;//14 = 1110
GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 3; // GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 3;
GpioCtrlRegs.GPDDIR.bit.GPIO96 = 1; // GpioCtrlRegs.GPDDIR.bit.GPIO96 = 1;
GpioDataRegs.GPDDAT.bit.GPIO96 = 0; // GpioDataRegs.GPDDAT.bit.GPIO96 = 0;
//
GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 2;//14 = 1110 // GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 2;//14 = 1110
GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 3; // GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 3;
GpioCtrlRegs.GPDDIR.bit.GPIO97 = 1; // GpioCtrlRegs.GPDDIR.bit.GPIO97 = 1;
GpioDataRegs.GPDDAT.bit.GPIO97 = 0; // GpioDataRegs.GPDDAT.bit.GPIO97 = 0;
//
EDIS; // EDIS;
} //}
void BissClkgenSetup(unsigned int bits_num_m, void BissClkgenSetup(unsigned int bits_num_m,

94
Projects/epwm_test_biss_c_cpu2/src/frm_uart.c
View File

@ -8,6 +8,10 @@
//#include "f2838x_pinmux.h" //#include "f2838x_pinmux.h"
#include "frm_uart.h" #include "frm_uart.h"
#define LSPCLK_HZ 50000000.0
#define BAUD 19200.0
#define BRR LSPCLK_HZ/(BAUD*8) + 1
uint16_t frmEn = 0; uint16_t frmEn = 0;
@ -26,57 +30,36 @@ void FMSTREnableSet(void)
frmEn = 1; frmEn = 1;
} }
void FRMUartInit(void) void FRMUartInit(void)
{ {
FMSTR_Init(); FMSTR_Init();
CpuSysRegs.PCLKCR7.bit.SCI_A = 1; CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
// For this example, only init the pins for the SCI-A port. // GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
// GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits // GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
// GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS // GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
// These functions are found in the f2838x_gpio.c file. // GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
// EALLOW;
// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up
// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;
// //
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; //rx // GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; //tx // GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
// GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
// GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
//
// EALLOW;
// GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
// GpioDataRegs.GPADAT.bit.GPIO21 = 1;
// GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
// EDIS; // EDIS;
// //
// EALLOW; // GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
// GpioCtrlRegs.GPCPUD.bit.GPIO84 = 1; //tx
// GpioCtrlRegs.GPCPUD.bit.GPIO85 = 0;
//
// GpioCtrlRegs.GPCMUX2.bit.GPIO28 = 1; //
// GpioCtrlRegs.GPCMUX2.bit.GPIO29 = 1; //
// EDIS;
GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
EALLOW;
GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
GpioDataRegs.GPADAT.bit.GPIO21 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
EDIS;
// GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1);
// GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL);
// GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1);
GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
// //
// Note: Clocks were turned on to the SCIA peripheral // Note: Clocks were turned on to the SCIA peripheral
// in the InitSysCtrl() function // in the InitSysCtrl() function
// //
EALLOW;
SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
// No parity,8 char bits, // No parity,8 char bits,
// async mode, idle-line protocol // async mode, idle-line protocol
@ -86,36 +69,13 @@ void FRMUartInit(void)
SciaRegs.SCICTL2.bit.TXINTENA = 0; SciaRegs.SCICTL2.bit.TXINTENA = 0;
SciaRegs.SCICTL2.bit.RXBKINTENA = 0; SciaRegs.SCICTL2.bit.RXBKINTENA = 0;
// uint16_t Brr = BRR;
// SCIA at 9600 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B //8A SciaRegs.SCIHBAUD.all = 0xFF & (Brr>>8);//0x0002;
// @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86. SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B;
//
//
// SCIA at 19200 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x45.
//
//
// SCIA at 38400 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0xA2.
//
//
// SCIA at 56000 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6F.
//
//
// SCIA at 57600 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6C (6B).
//
//
// SCIA at 115200 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x35.
//
SciaRegs.SCIHBAUD.all = 0x0002;
SciaRegs.SCILBAUD.all = 0x008B;
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
EDIS;
FMSTREnableSet(); FMSTREnableSet();
} }

4
Projects/epwm_test_biss_c_cpu2/src/frmmstr_run.c
View File

@ -29,12 +29,12 @@ static uint16_t diod = 0;
counter2++; counter2++;
diod++; diod++;
if(diod > 7) diod = 0; if(diod > 7) diod = 0;
Gpio_rainbow(diod); //Gpio_rainbow(diod);
//FMSTR_SCI_PUTCHAR(0xA5);
} }
} }
FMSTR_Poll(); FMSTR_Poll();
FMSTR_Recorder(); FMSTR_Recorder();
FMSTREnableClr(); FMSTREnableClr();
Gpio95out(Rele);
} }
} }

44
Projects/epwm_test_biss_c_cpu2/src/init_perif.c
View File

@ -1,7 +1,7 @@
/* /*
* init_perif.c * init_perif.c
* *
* Created on: 21 àâã. 2023 ã. * Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts * Author: seklyuts
*/ */
@ -27,11 +27,16 @@
void InitPerif(void) void InitPerif(void)
{ {
GpioDiodInit(); // GpioDiodInit();
//
GpioSetGreen(); // GpioSetGreen();
InitSysCtrl(); //
GpioSetBlue(); // EALLOW;
// ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
// EDIS;
//
// InitSysCtrl();
// GpioSetBlue();
@ -64,34 +69,27 @@ void InitPerif(void)
// //
InitPieVectTable(); InitPieVectTable();
GpioInit(); // GpioInit();
//
SdfmInitEnable(); SdfmInitEnable();
SdfmInit(); SdfmInit();
SdfmGpioInit(); // SdfmGpioInit();
SdfmInitInterruptEn(); SdfmInitInterruptEn();
//
PWMInitEnable(); PWMInitEnable();
PWMAllInit(); PWMAllInit();
PWMGpioInit(); // PWMGpioInit();
PWMInitInterruptEn(); PWMInitInterruptEn();
vectorInitCurrLoop(); vectorInitCurrLoop();
SpiCInit(); // SpiCInit();
SpiCGpioInit(); // SpiCGpioInit();
BissGpioInit(); // BissGpioInit();
BissInit(); // BissInit();
// SpiGpioInit();
// SpiInit();
// I2CMasterGpioInit();
// I2CMasterInit(I2C_OWN_ADDRESS,I2C_SLAVE_ADDRESS);
FRMUartInit(); FRMUartInit();
// vectorInitCurrLoop();
// ConfigureADC(); // ConfigureADC();
// //