diff --git a/Projects/epwm_test/Start_rfm.pmp b/Projects/epwm_test/Start_rfm.pmp index e2a1492..6852444 100644 Binary files a/Projects/epwm_test/Start_rfm.pmp and b/Projects/epwm_test/Start_rfm.pmp differ diff --git a/Projects/epwm_test_biss_c_cpu1/Start_rfm.pmp b/Projects/epwm_test_biss_c_cpu1/Start_rfm.pmp index 7f8af41..e2a1492 100644 Binary files a/Projects/epwm_test_biss_c_cpu1/Start_rfm.pmp and b/Projects/epwm_test_biss_c_cpu1/Start_rfm.pmp differ diff --git a/Projects/epwm_test_biss_c_cpu1/epwm_test.c b/Projects/epwm_test_biss_c_cpu1/epwm_test.c index e7f2c62..f4bbdd1 100644 --- a/Projects/epwm_test_biss_c_cpu1/epwm_test.c +++ b/Projects/epwm_test_biss_c_cpu1/epwm_test.c @@ -17,19 +17,19 @@ #include "f28x_project.h" #include "init_perif.h" #include "frmmstr_run.h" -#include "ExtEEPROM.h" #include "adc_init.h" #include "biss.h" void main(void) { InitPerif(); + for(;;) { // asm (" NOP"); - frmmstr_run(); - AdcRun(); - BissClkgenRun(); +// frmmstr_run(); +// AdcRun(); +// BissClkgenRun(); } } diff --git a/Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_init.c b/Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_init.c index 31d4b94..4d97ec3 100644 --- a/Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_init.c +++ b/Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_init.c @@ -136,22 +136,29 @@ void PWMInitInterruptEn(void) PieVectTable.EPWM4_INT = &epwm4_isr; PieVectTable.EPWM8_INT = &epwm8_isr; PieVectTable.EPWM11_INT = &epwm11_isr; - EDIS; // This is needed to disable write to EALLOW protected registers + EDIS; + // This is needed to disable write to EALLOW protected registers + + EPwm1Regs.ETCLR.bit.INT = 1; + EPwm2Regs.ETCLR.bit.INT = 1; + EPwm8Regs.ETCLR.bit.INT = 1; + EPwm11Regs.ETCLR.bit.INT = 1; // Enable CPU INT3 which is connected to EPWM1-3 INT: // - IER |= M_INT3; + IER |= M_INT3; // // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150) // - PieCtrlRegs.PIEIER3.bit.INTx1 = 1; - PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx8 = 1; + PieCtrlRegs.PIEIER3.bit.INTx11 = 1; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - PieCtrlRegs.PIEIER3.bit.INTx8 = 1; - PieCtrlRegs.PIEIER3.bit.INTx11 = 1; } void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed) @@ -183,10 +190,8 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed) EALLOW; EPwmRegs[Num]->TZCTL.bit.TZA = 3; EPwmRegs[Num]->TZCTL.bit.TZB = 3; - - EPwmRegs[Num]->TZFRC.all = 4; - EDIS; //���������� ���������� TZ-������� + EDIS; // // // Set actions // @@ -234,10 +239,6 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed) } EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL; -// EPwm1_DB_Direction = COUNT_UP; - - // - // if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA; diff --git a/Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_interrupts.c b/Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_interrupts.c index 2a3f4f5..f91bd46 100644 --- a/Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_interrupts.c +++ b/Projects/epwm_test_biss_c_cpu1/src/Peripherals/pwm_interrupts.c @@ -1,7 +1,7 @@ /* * interrupts.c * - * Created on: 21 . 2023 . + * Created on: 21 ���. 2023 �. * Author: seklyuts */ @@ -25,7 +25,7 @@ volatile uint16_t PWM_out = 2500; uint16_t Fault = 0, Fault_fix = 0, Ready = 0, Ready_Fix = 0; uint16_t counter1s=0; uint16_t FaultABC = 0, FaultABCFix = 0; -uint16_t PwmFlagStartADC = 0; +uint16_t PwmFlagStartCurrentMeashure = 0; extern volatile struct EPWM_REGS * EPwmRegs[17]; typedef struct @@ -125,9 +125,9 @@ __interrupt void epwm2_isr(void) // EPwm2Regs.ETCLR.bit.INT = 1; TimerBaseTimeoutInc(); - if(PwmFlagStartADC) /// , + if(PwmFlagStartCurrentMeashure) /// Не были отработаны измерения тока в сигма-дельта и не было запущено векторное управление { - PwmFlagStartADC = 0; + PwmFlagStartCurrentMeashure = 0; FMSTREnableSet(); AdcStartSet(); BissStartSet(); @@ -254,7 +254,7 @@ __interrupt void epwm11_isr(void) if(TestStopSync != 3) sdfm_start_conversion_current(); - PwmFlagStartADC = 1; + PwmFlagStartCurrentMeashure = 1; EPwm11Regs.ETCLR.bit.INT = 1; PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Gpio4out(0); @@ -263,7 +263,7 @@ __interrupt void epwm11_isr(void) void pwm_clr_PwmFlagStartADC(void) { - PwmFlagStartADC = 0; + PwmFlagStartCurrentMeashure = 0; } // diff --git a/Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.c b/Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.c index d2c42ba..32bb0d6 100644 --- a/Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.c +++ b/Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.c @@ -94,6 +94,7 @@ int16_t sdfmAdcErr[8] = {0,0,0,0,0,0,0,0}; int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0}; uint16_t startInitCurrent = 0; uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM}; +uint16_t AllInitDone =0; uint16_t sdfmIndex = 0; int16_t Test_I[16]; uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0}; @@ -179,8 +180,18 @@ void SdfmInitInterruptEn(void) PieVectTable.SDFM1_INT = &Sdfm1_ISR; PieVectTable.SDFM2_INT = &Sdfm2_ISR; IER |= M_INT5; + Sdfm_clearFlagRegister(SDFM1,0xFFFFFFFF); + Sdfm_clearFlagRegister(SDFM2,0xFFFFFFFF); PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 interrupt enabled PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 interrupt enabled + PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + EDIS; +} + +void SdfmTypeInit(void) +{ + EALLOW; + DevCfgRegs.SDFMTYPE.all = 0x8000; EDIS; } @@ -359,7 +370,14 @@ void sdfm_check_all_current_measurements_was_done(void) if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS) { sdfmIndex = 0; - vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]); + if(!AllInitDone) + { + if((initDone[SDFM_IA] == 0xFF)&&(initDone[SDFM_IB] == 0xFF)&&(initDone[SDFM_IC] == 0xFF)) AllInitDone = 1; + } + else + { + vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]); + } } } diff --git a/Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.h b/Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.h index 4a0d052..b8b6930 100644 --- a/Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.h +++ b/Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.h @@ -1,7 +1,7 @@ /* * sdfm.h * - * Created on: 25 . 2023 . + * Created on: 25 ���. 2023 �. * Author: seklyuts */ @@ -49,6 +49,7 @@ void SdfmInitInterruptEn(void); void SdfmInit(void); void sdfm_start_conversion_current(void); int16_t sdfm_get(int16_t N); +void SdfmTypeInit(void); diff --git a/Projects/epwm_test_biss_c_cpu1/src/frm_uart.c b/Projects/epwm_test_biss_c_cpu1/src/frm_uart.c index d2161c3..58a0f8c 100644 --- a/Projects/epwm_test_biss_c_cpu1/src/frm_uart.c +++ b/Projects/epwm_test_biss_c_cpu1/src/frm_uart.c @@ -8,6 +8,10 @@ //#include "f2838x_pinmux.h" #include "frm_uart.h" +#define LSPCLK_HZ 50000000.0 +#define BAUD 19200.0 +#define BRR LSPCLK_HZ/(BAUD*8) + 1 + uint16_t frmEn = 0; @@ -26,57 +30,40 @@ void FMSTREnableSet(void) frmEn = 1; } + +void FRMGPIOInit(void) +{ + GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5); + GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL); + GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5); + GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC); + + GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0); + GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL); + GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0); + GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL); + + EALLOW; + GpioCtrlRegs.GPADIR.bit.GPIO21 = 1; + GpioDataRegs.GPADAT.bit.GPIO21 = 1; + GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1; + GpioDataRegs.GPCDAT.bit.GPIO83 = 0; + EDIS; + + GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); +} + void FRMUartInit(void) { FMSTR_Init(); CpuSysRegs.PCLKCR7.bit.SCI_A = 1; - // For this example, only init the pins for the SCI-A port. - // GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits - // GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS - // These functions are found in the f2838x_gpio.c file. -// EALLOW; -// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up -// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; -// -// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; //rx -// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; //tx -// EDIS; -// -// EALLOW; -// GpioCtrlRegs.GPCPUD.bit.GPIO84 = 1; //tx -// GpioCtrlRegs.GPCPUD.bit.GPIO85 = 0; -// -// GpioCtrlRegs.GPCMUX2.bit.GPIO28 = 1; // -// GpioCtrlRegs.GPCMUX2.bit.GPIO29 = 1; // -// EDIS; - GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5); - GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL); - GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5); - GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC); - - GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0); - GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL); - GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0); - GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL); - - EALLOW; - GpioCtrlRegs.GPADIR.bit.GPIO21 = 1; - GpioDataRegs.GPADAT.bit.GPIO21 = 1; - GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1; - GpioDataRegs.GPCDAT.bit.GPIO83 = 0; - EDIS; - - // GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1); - // GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL); - // GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1); - GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); // // Note: Clocks were turned on to the SCIA peripheral // in the InitSysCtrl() function // - + EALLOW; SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback // No parity,8 char bits, // async mode, idle-line protocol @@ -86,36 +73,13 @@ void FRMUartInit(void) SciaRegs.SCICTL2.bit.TXINTENA = 0; SciaRegs.SCICTL2.bit.RXBKINTENA = 0; - // - // SCIA at 9600 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B //8A - // @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86. - // - // - // SCIA at 19200 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x45. - // - // - // SCIA at 38400 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0xA2. - // - // - // SCIA at 56000 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6F. - // - // - // SCIA at 57600 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6C (6B). - // - // - // SCIA at 115200 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x35. - // - SciaRegs.SCIHBAUD.all = 0x0002; - SciaRegs.SCILBAUD.all = 0x008B; + uint16_t Brr = BRR; + + SciaRegs.SCIHBAUD.all = 0xFF & (Brr>>8);//0x0002; + SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B; SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset - + EDIS; FMSTREnableSet(); } diff --git a/Projects/epwm_test_biss_c_cpu1/src/frm_uart.h b/Projects/epwm_test_biss_c_cpu1/src/frm_uart.h index 936e3d3..5a7fcf3 100644 --- a/Projects/epwm_test_biss_c_cpu1/src/frm_uart.h +++ b/Projects/epwm_test_biss_c_cpu1/src/frm_uart.h @@ -1,7 +1,7 @@ /* * frm_uart.h * - * Created on: 21 . 2023 . + * Created on: 21 ���. 2023 �. * Author: seklyuts */ @@ -23,6 +23,7 @@ void FMSTR_SCI_TD(void); FMSTR_SCISR FMSTR_SCI_RDCLRSR(void); //void FMSTR_InitSerial(void) ; void FRMUartInit(void); +void FRMGPIOInit(void); uint16_t FMSTRIsEnable(void); void FMSTREnableClr(void); diff --git a/Projects/epwm_test_biss_c_cpu1/src/frmmstr_run.c b/Projects/epwm_test_biss_c_cpu1/src/frmmstr_run.c index 7d9f509..267c09f 100644 --- a/Projects/epwm_test_biss_c_cpu1/src/frmmstr_run.c +++ b/Projects/epwm_test_biss_c_cpu1/src/frmmstr_run.c @@ -30,11 +30,13 @@ static uint16_t diod = 0; diod++; if(diod > 7) diod = 0; Gpio_rainbow(diod); + //FMSTR_SCI_PUTCHAR(0xA5); } } FMSTR_Poll(); FMSTR_Recorder(); FMSTREnableClr(); + Gpio95out(Rele); } } diff --git a/Projects/epwm_test_biss_c_cpu1/src/init_perif.c b/Projects/epwm_test_biss_c_cpu1/src/init_perif.c index 5b0d8f8..e969564 100644 --- a/Projects/epwm_test_biss_c_cpu1/src/init_perif.c +++ b/Projects/epwm_test_biss_c_cpu1/src/init_perif.c @@ -1,7 +1,7 @@ /* * init_perif.c * - * Created on: 21 . 2023 . + * Created on: 21 ���. 2023 �. * Author: seklyuts */ @@ -23,6 +23,33 @@ #include "adc_init.h" #include "biss.h" +#define TO_CPU1 0 +#define TO_CPU2 1 + + +#define CONNECT_SD1(x) EALLOW; DevCfgRegs.CPUSEL4.bit.SD1 = x; EDIS +#define CONNECT_SD2(x) EALLOW; DevCfgRegs.CPUSEL4.bit.SD2 = x; EDIS + +#define CONNECT_PWM1(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM1 = x; EDIS +#define CONNECT_PWM2(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM2 = x; EDIS +#define CONNECT_PWM3(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM3 = x; EDIS +#define CONNECT_PWM4(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM4 = x; EDIS +#define CONNECT_PWM5(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM5 = x; EDIS +#define CONNECT_PWM6(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM6 = x; EDIS +#define CONNECT_PWM7(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM7 = x; EDIS +#define CONNECT_PWM8(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM8 = x; EDIS +#define CONNECT_PWM9(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM9 = x; EDIS +#define CONNECT_PWM10(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM10 = x; EDIS +#define CONNECT_PWM11(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM11 = x; EDIS +#define CONNECT_PWM12(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM12 = x; EDIS +#define CONNECT_PWM13(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM13 = x; EDIS +#define CONNECT_PWM14(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM14 = x; EDIS +#define CONNECT_PWM15(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM15 = x; EDIS +#define CONNECT_PWM16(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM16 = x; EDIS + +#define CONNECT_SCIA(x) EALLOW; DevCfgRegs.CPUSEL5.bit.SCI_A = x; EDIS + + void InitPerif(void) { @@ -30,6 +57,11 @@ void InitPerif(void) GpioDiodInit(); GpioSetGreen(); + + EALLOW; + ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2; + EDIS; + InitSysCtrl(); GpioSetBlue(); @@ -65,33 +97,41 @@ void InitPerif(void) InitPieVectTable(); GpioInit(); -// - SdfmInitEnable(); - SdfmInit(); + SdfmGpioInit(); - SdfmInitInterruptEn(); -// - PWMInitEnable(); - PWMAllInit(); + SdfmTypeInit(); +// SdfmInitEnable(); +// SdfmInit(); +// SdfmInitInterruptEn(); + PWMGpioInit(); - PWMInitInterruptEn(); +// PWMInitEnable(); +// PWMAllInit(); +// PWMInitInterruptEn(); - vectorInitCurrLoop(); - - SpiCInit(); - SpiCGpioInit(); - BissGpioInit(); - BissInit(); - - - -// SpiGpioInit(); -// SpiInit(); -// I2CMasterGpioInit(); -// I2CMasterInit(I2C_OWN_ADDRESS,I2C_SLAVE_ADDRESS); - - FRMUartInit(); // vectorInitCurrLoop(); + + +// SpiCGpioInit(); +// SpiCInit(); +// BissGpioInit(); +// BissInit(); + + FRMGPIOInit(); +// FRMUartInit(); + + CONNECT_SD1(TO_CPU2); + CONNECT_SD2(TO_CPU2); + CONNECT_PWM1(TO_CPU2); + CONNECT_PWM2(TO_CPU2); + CONNECT_PWM5(TO_CPU2); + CONNECT_PWM7(TO_CPU2); + CONNECT_PWM8(TO_CPU2); + CONNECT_PWM3(TO_CPU2); + CONNECT_PWM11(TO_CPU2); + CONNECT_PWM12(TO_CPU2); + CONNECT_SCIA(TO_CPU2); + // ConfigureADC(); // diff --git a/Projects/epwm_test_biss_c_cpu2/.cproject b/Projects/epwm_test_biss_c_cpu2/.cproject index 12b4f14..5450965 100644 --- a/Projects/epwm_test_biss_c_cpu2/.cproject +++ b/Projects/epwm_test_biss_c_cpu2/.cproject @@ -99,7 +99,7 @@ - + @@ -414,7 +414,7 @@ - + diff --git a/Projects/epwm_test_biss_c_cpu2/Start_rfm.pmp b/Projects/epwm_test_biss_c_cpu2/Start_rfm.pmp index 7f8af41..e2a1492 100644 Binary files a/Projects/epwm_test_biss_c_cpu2/Start_rfm.pmp and b/Projects/epwm_test_biss_c_cpu2/Start_rfm.pmp differ diff --git a/Projects/epwm_test_biss_c_cpu2/epwm_test.c b/Projects/epwm_test_biss_c_cpu2/epwm_test.c index e7f2c62..22dd70e 100644 --- a/Projects/epwm_test_biss_c_cpu2/epwm_test.c +++ b/Projects/epwm_test_biss_c_cpu2/epwm_test.c @@ -17,18 +17,18 @@ #include "f28x_project.h" #include "init_perif.h" #include "frmmstr_run.h" -#include "ExtEEPROM.h" #include "adc_init.h" #include "biss.h" void main(void) { InitPerif(); + for(;;) { // asm (" NOP"); frmmstr_run(); - AdcRun(); +// AdcRun(); BissClkgenRun(); } } diff --git a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_init.c b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_init.c index 31d4b94..4d97ec3 100644 --- a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_init.c +++ b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_init.c @@ -136,22 +136,29 @@ void PWMInitInterruptEn(void) PieVectTable.EPWM4_INT = &epwm4_isr; PieVectTable.EPWM8_INT = &epwm8_isr; PieVectTable.EPWM11_INT = &epwm11_isr; - EDIS; // This is needed to disable write to EALLOW protected registers + EDIS; + // This is needed to disable write to EALLOW protected registers + + EPwm1Regs.ETCLR.bit.INT = 1; + EPwm2Regs.ETCLR.bit.INT = 1; + EPwm8Regs.ETCLR.bit.INT = 1; + EPwm11Regs.ETCLR.bit.INT = 1; // Enable CPU INT3 which is connected to EPWM1-3 INT: // - IER |= M_INT3; + IER |= M_INT3; // // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150) // - PieCtrlRegs.PIEIER3.bit.INTx1 = 1; - PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx8 = 1; + PieCtrlRegs.PIEIER3.bit.INTx11 = 1; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - PieCtrlRegs.PIEIER3.bit.INTx8 = 1; - PieCtrlRegs.PIEIER3.bit.INTx11 = 1; } void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed) @@ -183,10 +190,8 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed) EALLOW; EPwmRegs[Num]->TZCTL.bit.TZA = 3; EPwmRegs[Num]->TZCTL.bit.TZB = 3; - - EPwmRegs[Num]->TZFRC.all = 4; - EDIS; //���������� ���������� TZ-������� + EDIS; // // // Set actions // @@ -234,10 +239,6 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed) } EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL; -// EPwm1_DB_Direction = COUNT_UP; - - // - // if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA; diff --git a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_interrupts.c b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_interrupts.c index 2a3f4f5..f91bd46 100644 --- a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_interrupts.c +++ b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/pwm_interrupts.c @@ -1,7 +1,7 @@ /* * interrupts.c * - * Created on: 21 . 2023 . + * Created on: 21 ���. 2023 �. * Author: seklyuts */ @@ -25,7 +25,7 @@ volatile uint16_t PWM_out = 2500; uint16_t Fault = 0, Fault_fix = 0, Ready = 0, Ready_Fix = 0; uint16_t counter1s=0; uint16_t FaultABC = 0, FaultABCFix = 0; -uint16_t PwmFlagStartADC = 0; +uint16_t PwmFlagStartCurrentMeashure = 0; extern volatile struct EPWM_REGS * EPwmRegs[17]; typedef struct @@ -125,9 +125,9 @@ __interrupt void epwm2_isr(void) // EPwm2Regs.ETCLR.bit.INT = 1; TimerBaseTimeoutInc(); - if(PwmFlagStartADC) /// , + if(PwmFlagStartCurrentMeashure) /// Не были отработаны измерения тока в сигма-дельта и не было запущено векторное управление { - PwmFlagStartADC = 0; + PwmFlagStartCurrentMeashure = 0; FMSTREnableSet(); AdcStartSet(); BissStartSet(); @@ -254,7 +254,7 @@ __interrupt void epwm11_isr(void) if(TestStopSync != 3) sdfm_start_conversion_current(); - PwmFlagStartADC = 1; + PwmFlagStartCurrentMeashure = 1; EPwm11Regs.ETCLR.bit.INT = 1; PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Gpio4out(0); @@ -263,7 +263,7 @@ __interrupt void epwm11_isr(void) void pwm_clr_PwmFlagStartADC(void) { - PwmFlagStartADC = 0; + PwmFlagStartCurrentMeashure = 0; } // diff --git a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.c b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.c index d2c42ba..67fe514 100644 --- a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.c +++ b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.c @@ -94,6 +94,7 @@ int16_t sdfmAdcErr[8] = {0,0,0,0,0,0,0,0}; int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0}; uint16_t startInitCurrent = 0; uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM}; +uint16_t AllInitDone =0; uint16_t sdfmIndex = 0; int16_t Test_I[16]; uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0}; @@ -179,20 +180,29 @@ void SdfmInitInterruptEn(void) PieVectTable.SDFM1_INT = &Sdfm1_ISR; PieVectTable.SDFM2_INT = &Sdfm2_ISR; IER |= M_INT5; + Sdfm_clearFlagRegister(SDFM1,0xFFFFFFFF); + Sdfm_clearFlagRegister(SDFM2,0xFFFFFFFF); PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 interrupt enabled PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 interrupt enabled + PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; EDIS; } + +//void SdfmTypeInit(void) +//{ +// EALLOW; +// DevCfgRegs.SDFMTYPE.all = 0x8000; +// EDIS; +//} + + void SdfmInit(void) { uint16_t HLT, LLT; // // Configure SDFM type to 0 // - EALLOW; - DevCfgRegs.SDFMTYPE.all = 0x8000; - EDIS; // // Input Control Module // @@ -359,7 +369,14 @@ void sdfm_check_all_current_measurements_was_done(void) if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS) { sdfmIndex = 0; - vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]); + if(!AllInitDone) + { + if((initDone[SDFM_IA] == 0xFF)&&(initDone[SDFM_IB] == 0xFF)&&(initDone[SDFM_IC] == 0xFF)) AllInitDone = 1; + } + else + { + vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]); + } } } diff --git a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.h b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.h index 4a0d052..b8b6930 100644 --- a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.h +++ b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/sdfm.h @@ -1,7 +1,7 @@ /* * sdfm.h * - * Created on: 25 . 2023 . + * Created on: 25 ���. 2023 �. * Author: seklyuts */ @@ -49,6 +49,7 @@ void SdfmInitInterruptEn(void); void SdfmInit(void); void sdfm_start_conversion_current(void); int16_t sdfm_get(int16_t N); +void SdfmTypeInit(void); diff --git a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/spi_init.c b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/spi_init.c index c37c07c..11aa6ba 100644 --- a/Projects/epwm_test_biss_c_cpu2/src/Peripherals/spi_init.c +++ b/Projects/epwm_test_biss_c_cpu2/src/Peripherals/spi_init.c @@ -1,7 +1,7 @@ /* * spi_init.c * - * Created on: 5 . 2023 . + * Created on: 5 ����. 2023 �. * Author: seklyuts */ @@ -93,66 +93,66 @@ void SpiAInit(void) SpiaRegs.SPICCR.bit.SPISWRESET = 1; } -void SpiAGpioInit(void) -{ - EALLOW; - - // - // Enable internal pull-up for the selected pins - // - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // - GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on (SPISIMOA) - GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on (SPISOMIA) - GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on (SPICLKA) - GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up on (SPISTEA) - - // - // Set qualification for selected pins to asynch only - // - // This will select asynch (no qualification) for the selected pins. - // - GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input (SPISIMOA) - GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input (SPISOMIA) - GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3; // Asynch input (SPICLKA) - GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 3; // Asynch input (SPISTEA) - - // - // Configure SPI-A pins - // - // This specifies which of the possible GPIO pins will be SPI functional - // pins. - // - GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 3; // Configure GPIO32 as SPISIMOA - GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 3; // Configure GPIO33 as SPISOMIA - GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // Configure GPIO34 as SPICLKA - GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA +//void SpiAGpioInit(void) +//{ +// EALLOW; +// +// // +// // Enable internal pull-up for the selected pins +// // +// // Pull-ups can be enabled or disabled by the user. +// // This will enable the pullups for the specified pins. +// // +// GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on (SPISIMOA) +// GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on (SPISOMIA) +// GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on (SPICLKA) +// GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up on (SPISTEA) +// +// // +// // Set qualification for selected pins to asynch only +// // +// // This will select asynch (no qualification) for the selected pins. +// // +// GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input (SPISIMOA) +// GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input (SPISOMIA) +// GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3; // Asynch input (SPICLKA) +// GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 3; // Asynch input (SPISTEA) +// +// // +// // Configure SPI-A pins +// // +// // This specifies which of the possible GPIO pins will be SPI functional +// // pins. +// // +// GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 3; // Configure GPIO32 as SPISIMOA +// GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 3; // Configure GPIO33 as SPISOMIA +// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // Configure GPIO34 as SPICLKA +// GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA +// +// +// SPI_PROGRAM_CS_GPAMUX1 = 0;//program CS for BL25CM1A +// SPI_PROGRAM_CS_GPAGMUX1 = 0; +// SPI_PROGRAM_CS_GPADIR = 1; +// SPI_PROGRAM_CS_GPADAT = 0; +// +// EDIS; +//} - SPI_PROGRAM_CS_GPAMUX1 = 0;//program CS for BL25CM1A - SPI_PROGRAM_CS_GPAGMUX1 = 0; - SPI_PROGRAM_CS_GPADIR = 1; - SPI_PROGRAM_CS_GPADAT = 0; - - EDIS; -} - - -void spi_TurnOnCS1_GD25Q16E(void) -{ - EALLOW; - GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA - EDIS; -} - -void spi_TurnOffCS1_GD25Q16E(void) -{ - EALLOW; - GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0; - GpioDataRegs.GPBDAT.bit.GPIO35 = 1; - EDIS; -} +//void spi_TurnOnCS1_GD25Q16E(void) +//{ +// EALLOW; +// GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA +// EDIS; +//} +// +//void spi_TurnOffCS1_GD25Q16E(void) +//{ +// EALLOW; +// GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0; +// GpioDataRegs.GPBDAT.bit.GPIO35 = 1; +// EDIS; +//} void Gpio_SPI_CS_BL25CM1A(uint16_t out_bit) { @@ -250,68 +250,68 @@ void SpiBInit(void) SpibRegs.SPICCR.bit.SPISWRESET = 1; } -void SpiBGpioInit(void) -{ - EALLOW; - - // - // Enable internal pull-up for the selected pins - // - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // - GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on GPIO16 (SPISIMOB) -// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO17 (SPISOMIB) - - GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on GPIO18 (SPICLKB) -// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO18 (SPICLKB) - - GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO19 (SPISTEB) - - // - // Set qualification for selected pins to asynch only - // - // This will select asynch (no qualification) for the selected pins. - // - GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input GPIO16 (SPISIMOB) -// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO17 (SPISOMIB) - - GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input GPIO18 (SPICLKB) -// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO18 (SPICLKB) - - GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO19 (SPISTEB) - - - GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0; - GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0; - GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1; - GpioDataRegs.GPDDAT.bit.GPIO99 = 0; - - // - // Configure SPI-A pins - // - // This specifies which of the possible GPIO pins will be SPI functional - // pins. - // - GPIO_SetupPinMux(100, 0, 6); -// GPIO_SetupPinMux(25, 0, 6); - - GPIO_SetupPinMux(102, 0, 6); -// GPIO_SetupPinMux(26, 0, 6); - - GPIO_SetupPinMux(27, 0, 6); -// SpibRegs.SPITXBUF = 0xFFFF; - -// GpioCtrlRegs.GPAMUX1.bit.GPIO24 = 2; // Configure GPIO16 as SPISIMOA -// GpioCtrlRegs.GPAMUX1.bit.GPIO25 = 2; // Configure GPIO17 as SPISOMIA -// GpioCtrlRegs.GPAMUX1.bit.GPIO26 = 2; // Configure GPIO18 as SPICLKA -// GpioCtrlRegs.GPAMUX1.bit.GPIO27 = 2; // Configure GPIO19 as SPISTEA -// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO16 as SPISIMOA -// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO17 as SPISOMIA -// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO18 as SPICLKA -// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO19 as SPISTEA - EDIS; -} +//void SpiBGpioInit(void) +//{ +// EALLOW; +// +// // +// // Enable internal pull-up for the selected pins +// // +// // Pull-ups can be enabled or disabled by the user. +// // This will enable the pullups for the specified pins. +// // +// GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on GPIO16 (SPISIMOB) +//// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO17 (SPISOMIB) +// +// GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on GPIO18 (SPICLKB) +//// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO18 (SPICLKB) +// +// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO19 (SPISTEB) +// +// // +// // Set qualification for selected pins to asynch only +// // +// // This will select asynch (no qualification) for the selected pins. +// // +// GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input GPIO16 (SPISIMOB) +//// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO17 (SPISOMIB) +// +// GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input GPIO18 (SPICLKB) +//// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO18 (SPICLKB) +// +// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO19 (SPISTEB) +// +// +// GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0; +// GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0; +// GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1; +// GpioDataRegs.GPDDAT.bit.GPIO99 = 0; +// +// // +// // Configure SPI-A pins +// // +// // This specifies which of the possible GPIO pins will be SPI functional +// // pins. +// // +// GPIO_SetupPinMux(100, 0, 6); +//// GPIO_SetupPinMux(25, 0, 6); +// +// GPIO_SetupPinMux(102, 0, 6); +//// GPIO_SetupPinMux(26, 0, 6); +// +// GPIO_SetupPinMux(27, 0, 6); +//// SpibRegs.SPITXBUF = 0xFFFF; +// +//// GpioCtrlRegs.GPAMUX1.bit.GPIO24 = 2; // Configure GPIO16 as SPISIMOA +//// GpioCtrlRegs.GPAMUX1.bit.GPIO25 = 2; // Configure GPIO17 as SPISOMIA +//// GpioCtrlRegs.GPAMUX1.bit.GPIO26 = 2; // Configure GPIO18 as SPICLKA +//// GpioCtrlRegs.GPAMUX1.bit.GPIO27 = 2; // Configure GPIO19 as SPISTEA +//// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO16 as SPISIMOA +//// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO17 as SPISOMIA +//// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO18 as SPICLKA +//// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO19 as SPISTEA +// EDIS; +//} void transmitBData(uint16_t a) { @@ -416,61 +416,61 @@ void SpiCInit(void) } -void SpiCGpioInit(void) -{ - EALLOW; - - // - // Enable internal pull-up for the selected pins - // - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // - GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on (SPISIMOB) - - - GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on (SPICLKB) - - - GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0; // Enable pull-up on (SPISTEB) - - // - // Set qualification for selected pins to asynch only - // - // This will select asynch (no qualification) for the selected pins. - // - GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input(SPISIMOB) - - - GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input(SPICLKB) - - - GpioCtrlRegs.GPCQSEL1.bit.GPIO72 = 3; // Asynch input(SPISTEB) - - - GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0; - GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0; - GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1; - GpioDataRegs.GPDDAT.bit.GPIO99 = 0; - - // - // Configure SPI-A pins - // - // This specifies which of the possible GPIO pins will be SPI functional - // pins. - // - GPIO_SetupPinMux(100, 0, 6); - - - GPIO_SetupPinMux(102, 0, 6); - - - GPIO_SetupPinMux(72, 0, 15); - - - - EDIS; -} +//void SpiCGpioInit(void) +//{ +// EALLOW; +// +// // +// // Enable internal pull-up for the selected pins +// // +// // Pull-ups can be enabled or disabled by the user. +// // This will enable the pullups for the specified pins. +// // +// GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on (SPISIMOB) +// +// +// GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on (SPICLKB) +// +// +// GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0; // Enable pull-up on (SPISTEB) +// +// // +// // Set qualification for selected pins to asynch only +// // +// // This will select asynch (no qualification) for the selected pins. +// // +// GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input(SPISIMOB) +// +// +// GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input(SPICLKB) +// +// +// GpioCtrlRegs.GPCQSEL1.bit.GPIO72 = 3; // Asynch input(SPISTEB) +// +// +// GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0; +// GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0; +// GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1; +// GpioDataRegs.GPDDAT.bit.GPIO99 = 0; +// +// // +// // Configure SPI-A pins +// // +// // This specifies which of the possible GPIO pins will be SPI functional +// // pins. +// // +// GPIO_SetupPinMux(100, 0, 6); +// +// +// GPIO_SetupPinMux(102, 0, 6); +// +// +// GPIO_SetupPinMux(72, 0, 15); +// +// +// +// EDIS; +//} void transmitCData(uint16_t a) { diff --git a/Projects/epwm_test_biss_c_cpu2/src/biss.c b/Projects/epwm_test_biss_c_cpu2/src/biss.c index 230808e..cb0e7c8 100644 --- a/Projects/epwm_test_biss_c_cpu2/src/biss.c +++ b/Projects/epwm_test_biss_c_cpu2/src/biss.c @@ -1,7 +1,7 @@ /* * biss.c * - * Created on: 26 . 2023 . + * Created on: 26 ���. 2023 �. * Author: seklyuts */ #include "f28x_project.h" @@ -64,22 +64,22 @@ void BissInit(void) -void BissGpioInit(void) -{ - EALLOW; - - GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 2;//14 = 1110 - GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 3; - GpioCtrlRegs.GPDDIR.bit.GPIO96 = 1; - GpioDataRegs.GPDDAT.bit.GPIO96 = 0; - - GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 2;//14 = 1110 - GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 3; - GpioCtrlRegs.GPDDIR.bit.GPIO97 = 1; - GpioDataRegs.GPDDAT.bit.GPIO97 = 0; - - EDIS; -} +//void BissGpioInit(void) +//{ +// EALLOW; +// +// GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 2;//14 = 1110 +// GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 3; +// GpioCtrlRegs.GPDDIR.bit.GPIO96 = 1; +// GpioDataRegs.GPDDAT.bit.GPIO96 = 0; +// +// GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 2;//14 = 1110 +// GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 3; +// GpioCtrlRegs.GPDDIR.bit.GPIO97 = 1; +// GpioDataRegs.GPDDAT.bit.GPIO97 = 0; +// +// EDIS; +//} void BissClkgenSetup(unsigned int bits_num_m, diff --git a/Projects/epwm_test_biss_c_cpu2/src/frm_uart.c b/Projects/epwm_test_biss_c_cpu2/src/frm_uart.c index d2161c3..e5ce10c 100644 --- a/Projects/epwm_test_biss_c_cpu2/src/frm_uart.c +++ b/Projects/epwm_test_biss_c_cpu2/src/frm_uart.c @@ -8,6 +8,10 @@ //#include "f2838x_pinmux.h" #include "frm_uart.h" +#define LSPCLK_HZ 50000000.0 +#define BAUD 19200.0 +#define BRR LSPCLK_HZ/(BAUD*8) + 1 + uint16_t frmEn = 0; @@ -26,57 +30,36 @@ void FMSTREnableSet(void) frmEn = 1; } + + void FRMUartInit(void) { FMSTR_Init(); CpuSysRegs.PCLKCR7.bit.SCI_A = 1; - // For this example, only init the pins for the SCI-A port. - // GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits - // GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS - // These functions are found in the f2838x_gpio.c file. -// EALLOW; -// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up -// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; +// GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5); +// GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL); +// GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5); +// GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC); // -// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; //rx -// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; //tx +// GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0); +// GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL); +// GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0); +// GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL); +// +// EALLOW; +// GpioCtrlRegs.GPADIR.bit.GPIO21 = 1; +// GpioDataRegs.GPADAT.bit.GPIO21 = 1; +// GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1; +// GpioDataRegs.GPCDAT.bit.GPIO83 = 0; // EDIS; // -// EALLOW; -// GpioCtrlRegs.GPCPUD.bit.GPIO84 = 1; //tx -// GpioCtrlRegs.GPCPUD.bit.GPIO85 = 0; -// -// GpioCtrlRegs.GPCMUX2.bit.GPIO28 = 1; // -// GpioCtrlRegs.GPCMUX2.bit.GPIO29 = 1; // -// EDIS; - - GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5); - GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL); - GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5); - GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC); - - GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0); - GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL); - GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0); - GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL); - - EALLOW; - GpioCtrlRegs.GPADIR.bit.GPIO21 = 1; - GpioDataRegs.GPADAT.bit.GPIO21 = 1; - GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1; - GpioDataRegs.GPCDAT.bit.GPIO83 = 0; - EDIS; - - // GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1); - // GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL); - // GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1); - GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); +// GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); // // Note: Clocks were turned on to the SCIA peripheral // in the InitSysCtrl() function // - + EALLOW; SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback // No parity,8 char bits, // async mode, idle-line protocol @@ -86,36 +69,13 @@ void FRMUartInit(void) SciaRegs.SCICTL2.bit.TXINTENA = 0; SciaRegs.SCICTL2.bit.RXBKINTENA = 0; - // - // SCIA at 9600 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B //8A - // @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86. - // - // - // SCIA at 19200 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x45. - // - // - // SCIA at 38400 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0xA2. - // - // - // SCIA at 56000 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6F. - // - // - // SCIA at 57600 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6C (6B). - // - // - // SCIA at 115200 baud - // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x35. - // - SciaRegs.SCIHBAUD.all = 0x0002; - SciaRegs.SCILBAUD.all = 0x008B; + uint16_t Brr = BRR; + + SciaRegs.SCIHBAUD.all = 0xFF & (Brr>>8);//0x0002; + SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B; SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset - + EDIS; FMSTREnableSet(); } diff --git a/Projects/epwm_test_biss_c_cpu2/src/frmmstr_run.c b/Projects/epwm_test_biss_c_cpu2/src/frmmstr_run.c index 7d9f509..99805e4 100644 --- a/Projects/epwm_test_biss_c_cpu2/src/frmmstr_run.c +++ b/Projects/epwm_test_biss_c_cpu2/src/frmmstr_run.c @@ -29,12 +29,12 @@ static uint16_t diod = 0; counter2++; diod++; if(diod > 7) diod = 0; - Gpio_rainbow(diod); + //Gpio_rainbow(diod); + //FMSTR_SCI_PUTCHAR(0xA5); } } FMSTR_Poll(); FMSTR_Recorder(); FMSTREnableClr(); - Gpio95out(Rele); } } diff --git a/Projects/epwm_test_biss_c_cpu2/src/init_perif.c b/Projects/epwm_test_biss_c_cpu2/src/init_perif.c index 5b0d8f8..0d20ac1 100644 --- a/Projects/epwm_test_biss_c_cpu2/src/init_perif.c +++ b/Projects/epwm_test_biss_c_cpu2/src/init_perif.c @@ -1,7 +1,7 @@ /* * init_perif.c * - * Created on: 21 . 2023 . + * Created on: 21 ���. 2023 �. * Author: seklyuts */ @@ -27,11 +27,16 @@ void InitPerif(void) { - GpioDiodInit(); - - GpioSetGreen(); - InitSysCtrl(); - GpioSetBlue(); +// GpioDiodInit(); +// +// GpioSetGreen(); +// +// EALLOW; +// ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2; +// EDIS; +// +// InitSysCtrl(); +// GpioSetBlue(); @@ -64,34 +69,27 @@ void InitPerif(void) // InitPieVectTable(); - GpioInit(); -// +// GpioInit(); + SdfmInitEnable(); SdfmInit(); - SdfmGpioInit(); +// SdfmGpioInit(); SdfmInitInterruptEn(); -// + PWMInitEnable(); PWMAllInit(); - PWMGpioInit(); +// PWMGpioInit(); PWMInitInterruptEn(); vectorInitCurrLoop(); - SpiCInit(); - SpiCGpioInit(); - BissGpioInit(); - BissInit(); - - - -// SpiGpioInit(); -// SpiInit(); -// I2CMasterGpioInit(); -// I2CMasterInit(I2C_OWN_ADDRESS,I2C_SLAVE_ADDRESS); +// SpiCInit(); +// SpiCGpioInit(); +// BissGpioInit(); +// BissInit(); FRMUartInit(); -// vectorInitCurrLoop(); + // ConfigureADC(); //