разделение на CPU1 и 2
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@ -17,19 +17,19 @@
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#include "f28x_project.h"
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#include "init_perif.h"
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#include "frmmstr_run.h"
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#include "ExtEEPROM.h"
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#include "adc_init.h"
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#include "biss.h"
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void main(void)
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{
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InitPerif();
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for(;;)
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{
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// asm (" NOP");
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frmmstr_run();
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AdcRun();
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BissClkgenRun();
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// frmmstr_run();
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// AdcRun();
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// BissClkgenRun();
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}
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}
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@ -136,22 +136,29 @@ void PWMInitInterruptEn(void)
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PieVectTable.EPWM4_INT = &epwm4_isr;
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PieVectTable.EPWM8_INT = &epwm8_isr;
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PieVectTable.EPWM11_INT = &epwm11_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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EDIS;
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// This is needed to disable write to EALLOW protected registers
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EPwm1Regs.ETCLR.bit.INT = 1;
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EPwm2Regs.ETCLR.bit.INT = 1;
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EPwm8Regs.ETCLR.bit.INT = 1;
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EPwm11Regs.ETCLR.bit.INT = 1;
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// Enable CPU INT3 which is connected to EPWM1-3 INT:
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//
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IER |= M_INT3;
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IER |= M_INT3;
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//
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// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150)
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//
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PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
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PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
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PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
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PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
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PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
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PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
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PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
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PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
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}
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void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
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@ -183,10 +190,8 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
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EALLOW;
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EPwmRegs[Num]->TZCTL.bit.TZA = 3;
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EPwmRegs[Num]->TZCTL.bit.TZB = 3;
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EPwmRegs[Num]->TZFRC.all = 4;
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EDIS; //<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TZ-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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EDIS; //
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//
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// Set actions
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//
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@ -234,10 +239,6 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
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}
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EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL;
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// EPwm1_DB_Direction = COUNT_UP;
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//
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//
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if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
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else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA;
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@ -1,7 +1,7 @@
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/*
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* interrupts.c
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*
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* Created on: 21 авг. 2023 г.
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* Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
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* Author: seklyuts
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*/
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@ -25,7 +25,7 @@ volatile uint16_t PWM_out = 2500;
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uint16_t Fault = 0, Fault_fix = 0, Ready = 0, Ready_Fix = 0;
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uint16_t counter1s=0;
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uint16_t FaultABC = 0, FaultABCFix = 0;
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uint16_t PwmFlagStartADC = 0;
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uint16_t PwmFlagStartCurrentMeashure = 0;
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extern volatile struct EPWM_REGS * EPwmRegs[17];
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typedef struct
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@ -125,9 +125,9 @@ __interrupt void epwm2_isr(void)
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//
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EPwm2Regs.ETCLR.bit.INT = 1;
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TimerBaseTimeoutInc();
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if(PwmFlagStartADC) /// ацп не запустился, ток не был измерен
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if(PwmFlagStartCurrentMeashure) /// Не были отработаны измерения тока в сигма-дельта и не было запущено векторное управление
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{
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PwmFlagStartADC = 0;
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PwmFlagStartCurrentMeashure = 0;
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FMSTREnableSet();
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AdcStartSet();
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BissStartSet();
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@ -254,7 +254,7 @@ __interrupt void epwm11_isr(void)
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if(TestStopSync != 3) sdfm_start_conversion_current();
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PwmFlagStartADC = 1;
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PwmFlagStartCurrentMeashure = 1;
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EPwm11Regs.ETCLR.bit.INT = 1;
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
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// Gpio4out(0);
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@ -263,7 +263,7 @@ __interrupt void epwm11_isr(void)
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void pwm_clr_PwmFlagStartADC(void)
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{
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PwmFlagStartADC = 0;
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PwmFlagStartCurrentMeashure = 0;
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}
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//
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@ -94,6 +94,7 @@ int16_t sdfmAdcErr[8] = {0,0,0,0,0,0,0,0};
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int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0};
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uint16_t startInitCurrent = 0;
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uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM};
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uint16_t AllInitDone =0;
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uint16_t sdfmIndex = 0;
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int16_t Test_I[16];
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uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0};
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@ -179,8 +180,18 @@ void SdfmInitInterruptEn(void)
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PieVectTable.SDFM1_INT = &Sdfm1_ISR;
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PieVectTable.SDFM2_INT = &Sdfm2_ISR;
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IER |= M_INT5;
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Sdfm_clearFlagRegister(SDFM1,0xFFFFFFFF);
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Sdfm_clearFlagRegister(SDFM2,0xFFFFFFFF);
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PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 interrupt enabled
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PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 interrupt enabled
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
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EDIS;
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}
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void SdfmTypeInit(void)
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{
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EALLOW;
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DevCfgRegs.SDFMTYPE.all = 0x8000;
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EDIS;
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}
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@ -359,7 +370,14 @@ void sdfm_check_all_current_measurements_was_done(void)
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if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS)
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{
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sdfmIndex = 0;
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vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]);
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if(!AllInitDone)
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{
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if((initDone[SDFM_IA] == 0xFF)&&(initDone[SDFM_IB] == 0xFF)&&(initDone[SDFM_IC] == 0xFF)) AllInitDone = 1;
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}
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else
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{
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vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]);
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}
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}
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}
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@ -1,7 +1,7 @@
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/*
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* sdfm.h
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*
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* Created on: 25 àâã. 2023 ã.
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* Created on: 25 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
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* Author: seklyuts
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*/
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@ -49,6 +49,7 @@ void SdfmInitInterruptEn(void);
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void SdfmInit(void);
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void sdfm_start_conversion_current(void);
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int16_t sdfm_get(int16_t N);
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void SdfmTypeInit(void);
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@ -8,6 +8,10 @@
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//#include "f2838x_pinmux.h"
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#include "frm_uart.h"
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#define LSPCLK_HZ 50000000.0
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#define BAUD 19200.0
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#define BRR LSPCLK_HZ/(BAUD*8) + 1
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uint16_t frmEn = 0;
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@ -26,57 +30,40 @@ void FMSTREnableSet(void)
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frmEn = 1;
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}
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void FRMGPIOInit(void)
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{
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GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
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GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
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GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
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GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
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GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
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GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
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GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
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EALLOW;
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GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
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GpioDataRegs.GPADAT.bit.GPIO21 = 1;
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GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
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GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
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EDIS;
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GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
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}
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void FRMUartInit(void)
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{
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FMSTR_Init();
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CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
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// For this example, only init the pins for the SCI-A port.
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// GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits
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// GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS
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// These functions are found in the f2838x_gpio.c file.
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// EALLOW;
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// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up
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// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;
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//
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// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; //rx
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// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; //tx
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// EDIS;
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//
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// EALLOW;
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// GpioCtrlRegs.GPCPUD.bit.GPIO84 = 1; //tx
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// GpioCtrlRegs.GPCPUD.bit.GPIO85 = 0;
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//
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// GpioCtrlRegs.GPCMUX2.bit.GPIO28 = 1; //
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// GpioCtrlRegs.GPCMUX2.bit.GPIO29 = 1; //
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// EDIS;
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GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
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GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
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GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
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GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
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GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
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GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
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GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
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EALLOW;
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GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
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GpioDataRegs.GPADAT.bit.GPIO21 = 1;
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GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
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GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
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EDIS;
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// GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1);
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// GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL);
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// GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1);
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GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
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//
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// Note: Clocks were turned on to the SCIA peripheral
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// in the InitSysCtrl() function
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//
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EALLOW;
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SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
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// No parity,8 char bits,
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// async mode, idle-line protocol
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@ -86,36 +73,13 @@ void FRMUartInit(void)
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SciaRegs.SCICTL2.bit.TXINTENA = 0;
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SciaRegs.SCICTL2.bit.RXBKINTENA = 0;
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//
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// SCIA at 9600 baud
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// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B //8A
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// @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.
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//
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//
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// SCIA at 19200 baud
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// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x45.
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//
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//
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// SCIA at 38400 baud
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// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0xA2.
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//
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//
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// SCIA at 56000 baud
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// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6F.
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//
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//
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// SCIA at 57600 baud
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// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6C (6B).
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//
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//
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// SCIA at 115200 baud
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// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x35.
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//
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SciaRegs.SCIHBAUD.all = 0x0002;
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SciaRegs.SCILBAUD.all = 0x008B;
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uint16_t Brr = BRR;
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SciaRegs.SCIHBAUD.all = 0xFF & (Brr>>8);//0x0002;
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SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B;
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SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
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EDIS;
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FMSTREnableSet();
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}
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@ -1,7 +1,7 @@
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/*
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* frm_uart.h
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*
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* Created on: 21 àâã. 2023 ã.
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* Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
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* Author: seklyuts
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*/
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@ -23,6 +23,7 @@ void FMSTR_SCI_TD(void);
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FMSTR_SCISR FMSTR_SCI_RDCLRSR(void);
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//void FMSTR_InitSerial(void) ;
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void FRMUartInit(void);
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void FRMGPIOInit(void);
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uint16_t FMSTRIsEnable(void);
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void FMSTREnableClr(void);
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@ -30,11 +30,13 @@ static uint16_t diod = 0;
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diod++;
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if(diod > 7) diod = 0;
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Gpio_rainbow(diod);
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//FMSTR_SCI_PUTCHAR(0xA5);
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}
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}
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FMSTR_Poll();
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FMSTR_Recorder();
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FMSTREnableClr();
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Gpio95out(Rele);
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}
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}
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@ -1,7 +1,7 @@
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/*
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* init_perif.c
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*
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* Created on: 21 àâã. 2023 ã.
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* Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
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* Author: seklyuts
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*/
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@ -23,6 +23,33 @@
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#include "adc_init.h"
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#include "biss.h"
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#define TO_CPU1 0
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#define TO_CPU2 1
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#define CONNECT_SD1(x) EALLOW; DevCfgRegs.CPUSEL4.bit.SD1 = x; EDIS
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#define CONNECT_SD2(x) EALLOW; DevCfgRegs.CPUSEL4.bit.SD2 = x; EDIS
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#define CONNECT_PWM1(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM1 = x; EDIS
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#define CONNECT_PWM2(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM2 = x; EDIS
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#define CONNECT_PWM3(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM3 = x; EDIS
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#define CONNECT_PWM4(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM4 = x; EDIS
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#define CONNECT_PWM5(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM5 = x; EDIS
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#define CONNECT_PWM6(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM6 = x; EDIS
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#define CONNECT_PWM7(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM7 = x; EDIS
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#define CONNECT_PWM8(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM8 = x; EDIS
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#define CONNECT_PWM9(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM9 = x; EDIS
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#define CONNECT_PWM10(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM10 = x; EDIS
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#define CONNECT_PWM11(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM11 = x; EDIS
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#define CONNECT_PWM12(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM12 = x; EDIS
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#define CONNECT_PWM13(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM13 = x; EDIS
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#define CONNECT_PWM14(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM14 = x; EDIS
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#define CONNECT_PWM15(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM15 = x; EDIS
|
||||
#define CONNECT_PWM16(x) EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM16 = x; EDIS
|
||||
|
||||
#define CONNECT_SCIA(x) EALLOW; DevCfgRegs.CPUSEL5.bit.SCI_A = x; EDIS
|
||||
|
||||
|
||||
|
||||
void InitPerif(void)
|
||||
{
|
||||
@ -30,6 +57,11 @@ void InitPerif(void)
|
||||
GpioDiodInit();
|
||||
|
||||
GpioSetGreen();
|
||||
|
||||
EALLOW;
|
||||
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
|
||||
EDIS;
|
||||
|
||||
InitSysCtrl();
|
||||
GpioSetBlue();
|
||||
|
||||
@ -65,33 +97,41 @@ void InitPerif(void)
|
||||
InitPieVectTable();
|
||||
|
||||
GpioInit();
|
||||
//
|
||||
SdfmInitEnable();
|
||||
SdfmInit();
|
||||
|
||||
SdfmGpioInit();
|
||||
SdfmInitInterruptEn();
|
||||
//
|
||||
PWMInitEnable();
|
||||
PWMAllInit();
|
||||
SdfmTypeInit();
|
||||
// SdfmInitEnable();
|
||||
// SdfmInit();
|
||||
// SdfmInitInterruptEn();
|
||||
|
||||
PWMGpioInit();
|
||||
PWMInitInterruptEn();
|
||||
// PWMInitEnable();
|
||||
// PWMAllInit();
|
||||
// PWMInitInterruptEn();
|
||||
|
||||
vectorInitCurrLoop();
|
||||
|
||||
SpiCInit();
|
||||
SpiCGpioInit();
|
||||
BissGpioInit();
|
||||
BissInit();
|
||||
|
||||
|
||||
|
||||
// SpiGpioInit();
|
||||
// SpiInit();
|
||||
// I2CMasterGpioInit();
|
||||
// I2CMasterInit(I2C_OWN_ADDRESS,I2C_SLAVE_ADDRESS);
|
||||
|
||||
FRMUartInit();
|
||||
// vectorInitCurrLoop();
|
||||
|
||||
|
||||
// SpiCGpioInit();
|
||||
// SpiCInit();
|
||||
// BissGpioInit();
|
||||
// BissInit();
|
||||
|
||||
FRMGPIOInit();
|
||||
// FRMUartInit();
|
||||
|
||||
CONNECT_SD1(TO_CPU2);
|
||||
CONNECT_SD2(TO_CPU2);
|
||||
CONNECT_PWM1(TO_CPU2);
|
||||
CONNECT_PWM2(TO_CPU2);
|
||||
CONNECT_PWM5(TO_CPU2);
|
||||
CONNECT_PWM7(TO_CPU2);
|
||||
CONNECT_PWM8(TO_CPU2);
|
||||
CONNECT_PWM3(TO_CPU2);
|
||||
CONNECT_PWM11(TO_CPU2);
|
||||
CONNECT_PWM12(TO_CPU2);
|
||||
CONNECT_SCIA(TO_CPU2);
|
||||
|
||||
// ConfigureADC();
|
||||
|
||||
//
|
||||
|
||||
@ -99,7 +99,7 @@
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="2838x_FLASH_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry excluding="2838x_FLASH_lnk_cpu2.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
@ -414,7 +414,7 @@
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="2838x_RAM_combined_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry excluding="lib/f2838x_epwm.c|src/Peripherals/gpio_init.c|2838x_RAM_combined_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
|
||||
Binary file not shown.
@ -17,18 +17,18 @@
|
||||
#include "f28x_project.h"
|
||||
#include "init_perif.h"
|
||||
#include "frmmstr_run.h"
|
||||
#include "ExtEEPROM.h"
|
||||
#include "adc_init.h"
|
||||
#include "biss.h"
|
||||
|
||||
void main(void)
|
||||
{
|
||||
InitPerif();
|
||||
|
||||
for(;;)
|
||||
{
|
||||
// asm (" NOP");
|
||||
frmmstr_run();
|
||||
AdcRun();
|
||||
// AdcRun();
|
||||
BissClkgenRun();
|
||||
}
|
||||
}
|
||||
|
||||
@ -136,22 +136,29 @@ void PWMInitInterruptEn(void)
|
||||
PieVectTable.EPWM4_INT = &epwm4_isr;
|
||||
PieVectTable.EPWM8_INT = &epwm8_isr;
|
||||
PieVectTable.EPWM11_INT = &epwm11_isr;
|
||||
EDIS; // This is needed to disable write to EALLOW protected registers
|
||||
EDIS;
|
||||
// This is needed to disable write to EALLOW protected registers
|
||||
|
||||
EPwm1Regs.ETCLR.bit.INT = 1;
|
||||
EPwm2Regs.ETCLR.bit.INT = 1;
|
||||
EPwm8Regs.ETCLR.bit.INT = 1;
|
||||
EPwm11Regs.ETCLR.bit.INT = 1;
|
||||
|
||||
|
||||
// Enable CPU INT3 which is connected to EPWM1-3 INT:
|
||||
//
|
||||
IER |= M_INT3;
|
||||
IER |= M_INT3;
|
||||
|
||||
//
|
||||
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150)
|
||||
//
|
||||
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
|
||||
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
|
||||
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
|
||||
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
|
||||
PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
|
||||
PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
|
||||
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||||
|
||||
PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
|
||||
|
||||
PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
|
||||
}
|
||||
|
||||
void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
|
||||
@ -183,10 +190,8 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
|
||||
EALLOW;
|
||||
EPwmRegs[Num]->TZCTL.bit.TZA = 3;
|
||||
EPwmRegs[Num]->TZCTL.bit.TZB = 3;
|
||||
|
||||
|
||||
EPwmRegs[Num]->TZFRC.all = 4;
|
||||
EDIS; //<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TZ-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
EDIS; //
|
||||
//
|
||||
// Set actions
|
||||
//
|
||||
@ -234,10 +239,6 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
|
||||
}
|
||||
EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL;
|
||||
|
||||
// EPwm1_DB_Direction = COUNT_UP;
|
||||
|
||||
//
|
||||
//
|
||||
if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
|
||||
else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA;
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* interrupts.c
|
||||
*
|
||||
* Created on: 21 авг. 2023 г.
|
||||
* Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
|
||||
* Author: seklyuts
|
||||
*/
|
||||
|
||||
@ -25,7 +25,7 @@ volatile uint16_t PWM_out = 2500;
|
||||
uint16_t Fault = 0, Fault_fix = 0, Ready = 0, Ready_Fix = 0;
|
||||
uint16_t counter1s=0;
|
||||
uint16_t FaultABC = 0, FaultABCFix = 0;
|
||||
uint16_t PwmFlagStartADC = 0;
|
||||
uint16_t PwmFlagStartCurrentMeashure = 0;
|
||||
extern volatile struct EPWM_REGS * EPwmRegs[17];
|
||||
|
||||
typedef struct
|
||||
@ -125,9 +125,9 @@ __interrupt void epwm2_isr(void)
|
||||
//
|
||||
EPwm2Regs.ETCLR.bit.INT = 1;
|
||||
TimerBaseTimeoutInc();
|
||||
if(PwmFlagStartADC) /// ацп не запустился, ток не был измерен
|
||||
if(PwmFlagStartCurrentMeashure) /// Не были отработаны измерения тока в сигма-дельта и не было запущено векторное управление
|
||||
{
|
||||
PwmFlagStartADC = 0;
|
||||
PwmFlagStartCurrentMeashure = 0;
|
||||
FMSTREnableSet();
|
||||
AdcStartSet();
|
||||
BissStartSet();
|
||||
@ -254,7 +254,7 @@ __interrupt void epwm11_isr(void)
|
||||
|
||||
if(TestStopSync != 3) sdfm_start_conversion_current();
|
||||
|
||||
PwmFlagStartADC = 1;
|
||||
PwmFlagStartCurrentMeashure = 1;
|
||||
EPwm11Regs.ETCLR.bit.INT = 1;
|
||||
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||||
// Gpio4out(0);
|
||||
@ -263,7 +263,7 @@ __interrupt void epwm11_isr(void)
|
||||
|
||||
void pwm_clr_PwmFlagStartADC(void)
|
||||
{
|
||||
PwmFlagStartADC = 0;
|
||||
PwmFlagStartCurrentMeashure = 0;
|
||||
}
|
||||
|
||||
//
|
||||
|
||||
@ -94,6 +94,7 @@ int16_t sdfmAdcErr[8] = {0,0,0,0,0,0,0,0};
|
||||
int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0};
|
||||
uint16_t startInitCurrent = 0;
|
||||
uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM};
|
||||
uint16_t AllInitDone =0;
|
||||
uint16_t sdfmIndex = 0;
|
||||
int16_t Test_I[16];
|
||||
uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0};
|
||||
@ -179,20 +180,29 @@ void SdfmInitInterruptEn(void)
|
||||
PieVectTable.SDFM1_INT = &Sdfm1_ISR;
|
||||
PieVectTable.SDFM2_INT = &Sdfm2_ISR;
|
||||
IER |= M_INT5;
|
||||
Sdfm_clearFlagRegister(SDFM1,0xFFFFFFFF);
|
||||
Sdfm_clearFlagRegister(SDFM2,0xFFFFFFFF);
|
||||
PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 interrupt enabled
|
||||
PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 interrupt enabled
|
||||
PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
//void SdfmTypeInit(void)
|
||||
//{
|
||||
// EALLOW;
|
||||
// DevCfgRegs.SDFMTYPE.all = 0x8000;
|
||||
// EDIS;
|
||||
//}
|
||||
|
||||
|
||||
void SdfmInit(void)
|
||||
{
|
||||
uint16_t HLT, LLT;
|
||||
//
|
||||
// Configure SDFM type to 0
|
||||
//
|
||||
EALLOW;
|
||||
DevCfgRegs.SDFMTYPE.all = 0x8000;
|
||||
EDIS;
|
||||
//
|
||||
// Input Control Module
|
||||
//
|
||||
@ -359,7 +369,14 @@ void sdfm_check_all_current_measurements_was_done(void)
|
||||
if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS)
|
||||
{
|
||||
sdfmIndex = 0;
|
||||
vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]);
|
||||
if(!AllInitDone)
|
||||
{
|
||||
if((initDone[SDFM_IA] == 0xFF)&&(initDone[SDFM_IB] == 0xFF)&&(initDone[SDFM_IC] == 0xFF)) AllInitDone = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* sdfm.h
|
||||
*
|
||||
* Created on: 25 àâã. 2023 ã.
|
||||
* Created on: 25 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
|
||||
* Author: seklyuts
|
||||
*/
|
||||
|
||||
@ -49,6 +49,7 @@ void SdfmInitInterruptEn(void);
|
||||
void SdfmInit(void);
|
||||
void sdfm_start_conversion_current(void);
|
||||
int16_t sdfm_get(int16_t N);
|
||||
void SdfmTypeInit(void);
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* spi_init.c
|
||||
*
|
||||
* Created on: 5 ñåíò. 2023 ã.
|
||||
* Created on: 5 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
|
||||
* Author: seklyuts
|
||||
*/
|
||||
|
||||
@ -93,66 +93,66 @@ void SpiAInit(void)
|
||||
SpiaRegs.SPICCR.bit.SPISWRESET = 1;
|
||||
}
|
||||
|
||||
void SpiAGpioInit(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
//
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
//
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on (SPISIMOA)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on (SPISOMIA)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on (SPICLKA)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up on (SPISTEA)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
//
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
//
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input (SPISIMOA)
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input (SPISOMIA)
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3; // Asynch input (SPICLKA)
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 3; // Asynch input (SPISTEA)
|
||||
|
||||
//
|
||||
// Configure SPI-A pins
|
||||
//
|
||||
// This specifies which of the possible GPIO pins will be SPI functional
|
||||
// pins.
|
||||
//
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 3; // Configure GPIO32 as SPISIMOA
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 3; // Configure GPIO33 as SPISOMIA
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // Configure GPIO34 as SPICLKA
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA
|
||||
//void SpiAGpioInit(void)
|
||||
//{
|
||||
// EALLOW;
|
||||
//
|
||||
// //
|
||||
// // Enable internal pull-up for the selected pins
|
||||
// //
|
||||
// // Pull-ups can be enabled or disabled by the user.
|
||||
// // This will enable the pullups for the specified pins.
|
||||
// //
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on (SPISIMOA)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on (SPISOMIA)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on (SPICLKA)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up on (SPISTEA)
|
||||
//
|
||||
// //
|
||||
// // Set qualification for selected pins to asynch only
|
||||
// //
|
||||
// // This will select asynch (no qualification) for the selected pins.
|
||||
// //
|
||||
// GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input (SPISIMOA)
|
||||
// GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input (SPISOMIA)
|
||||
// GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3; // Asynch input (SPICLKA)
|
||||
// GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 3; // Asynch input (SPISTEA)
|
||||
//
|
||||
// //
|
||||
// // Configure SPI-A pins
|
||||
// //
|
||||
// // This specifies which of the possible GPIO pins will be SPI functional
|
||||
// // pins.
|
||||
// //
|
||||
// GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 3; // Configure GPIO32 as SPISIMOA
|
||||
// GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 3; // Configure GPIO33 as SPISOMIA
|
||||
// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // Configure GPIO34 as SPICLKA
|
||||
// GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA
|
||||
//
|
||||
//
|
||||
// SPI_PROGRAM_CS_GPAMUX1 = 0;//program CS for BL25CM1A
|
||||
// SPI_PROGRAM_CS_GPAGMUX1 = 0;
|
||||
// SPI_PROGRAM_CS_GPADIR = 1;
|
||||
// SPI_PROGRAM_CS_GPADAT = 0;
|
||||
//
|
||||
// EDIS;
|
||||
//}
|
||||
|
||||
|
||||
SPI_PROGRAM_CS_GPAMUX1 = 0;//program CS for BL25CM1A
|
||||
SPI_PROGRAM_CS_GPAGMUX1 = 0;
|
||||
SPI_PROGRAM_CS_GPADIR = 1;
|
||||
SPI_PROGRAM_CS_GPADAT = 0;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void spi_TurnOnCS1_GD25Q16E(void)
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void spi_TurnOffCS1_GD25Q16E(void)
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0;
|
||||
GpioDataRegs.GPBDAT.bit.GPIO35 = 1;
|
||||
EDIS;
|
||||
}
|
||||
//void spi_TurnOnCS1_GD25Q16E(void)
|
||||
//{
|
||||
// EALLOW;
|
||||
// GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA
|
||||
// EDIS;
|
||||
//}
|
||||
//
|
||||
//void spi_TurnOffCS1_GD25Q16E(void)
|
||||
//{
|
||||
// EALLOW;
|
||||
// GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0;
|
||||
// GpioDataRegs.GPBDAT.bit.GPIO35 = 1;
|
||||
// EDIS;
|
||||
//}
|
||||
|
||||
void Gpio_SPI_CS_BL25CM1A(uint16_t out_bit)
|
||||
{
|
||||
@ -250,68 +250,68 @@ void SpiBInit(void)
|
||||
SpibRegs.SPICCR.bit.SPISWRESET = 1;
|
||||
}
|
||||
|
||||
void SpiBGpioInit(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
//
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
//
|
||||
GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on GPIO16 (SPISIMOB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO17 (SPISOMIB)
|
||||
|
||||
GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on GPIO18 (SPICLKB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO18 (SPICLKB)
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO19 (SPISTEB)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
//
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
//
|
||||
GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input GPIO16 (SPISIMOB)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO17 (SPISOMIB)
|
||||
|
||||
GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input GPIO18 (SPICLKB)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO18 (SPICLKB)
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO19 (SPISTEB)
|
||||
|
||||
|
||||
GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;
|
||||
GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0;
|
||||
GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1;
|
||||
GpioDataRegs.GPDDAT.bit.GPIO99 = 0;
|
||||
|
||||
//
|
||||
// Configure SPI-A pins
|
||||
//
|
||||
// This specifies which of the possible GPIO pins will be SPI functional
|
||||
// pins.
|
||||
//
|
||||
GPIO_SetupPinMux(100, 0, 6);
|
||||
// GPIO_SetupPinMux(25, 0, 6);
|
||||
|
||||
GPIO_SetupPinMux(102, 0, 6);
|
||||
// GPIO_SetupPinMux(26, 0, 6);
|
||||
|
||||
GPIO_SetupPinMux(27, 0, 6);
|
||||
// SpibRegs.SPITXBUF = 0xFFFF;
|
||||
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO24 = 2; // Configure GPIO16 as SPISIMOA
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO25 = 2; // Configure GPIO17 as SPISOMIA
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO26 = 2; // Configure GPIO18 as SPICLKA
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO27 = 2; // Configure GPIO19 as SPISTEA
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO16 as SPISIMOA
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO17 as SPISOMIA
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO18 as SPICLKA
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO19 as SPISTEA
|
||||
EDIS;
|
||||
}
|
||||
//void SpiBGpioInit(void)
|
||||
//{
|
||||
// EALLOW;
|
||||
//
|
||||
// //
|
||||
// // Enable internal pull-up for the selected pins
|
||||
// //
|
||||
// // Pull-ups can be enabled or disabled by the user.
|
||||
// // This will enable the pullups for the specified pins.
|
||||
// //
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on GPIO16 (SPISIMOB)
|
||||
//// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO17 (SPISOMIB)
|
||||
//
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on GPIO18 (SPICLKB)
|
||||
//// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO18 (SPICLKB)
|
||||
//
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO19 (SPISTEB)
|
||||
//
|
||||
// //
|
||||
// // Set qualification for selected pins to asynch only
|
||||
// //
|
||||
// // This will select asynch (no qualification) for the selected pins.
|
||||
// //
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input GPIO16 (SPISIMOB)
|
||||
//// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO17 (SPISOMIB)
|
||||
//
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input GPIO18 (SPICLKB)
|
||||
//// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO18 (SPICLKB)
|
||||
//
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO19 (SPISTEB)
|
||||
//
|
||||
//
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0;
|
||||
// GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1;
|
||||
// GpioDataRegs.GPDDAT.bit.GPIO99 = 0;
|
||||
//
|
||||
// //
|
||||
// // Configure SPI-A pins
|
||||
// //
|
||||
// // This specifies which of the possible GPIO pins will be SPI functional
|
||||
// // pins.
|
||||
// //
|
||||
// GPIO_SetupPinMux(100, 0, 6);
|
||||
//// GPIO_SetupPinMux(25, 0, 6);
|
||||
//
|
||||
// GPIO_SetupPinMux(102, 0, 6);
|
||||
//// GPIO_SetupPinMux(26, 0, 6);
|
||||
//
|
||||
// GPIO_SetupPinMux(27, 0, 6);
|
||||
//// SpibRegs.SPITXBUF = 0xFFFF;
|
||||
//
|
||||
//// GpioCtrlRegs.GPAMUX1.bit.GPIO24 = 2; // Configure GPIO16 as SPISIMOA
|
||||
//// GpioCtrlRegs.GPAMUX1.bit.GPIO25 = 2; // Configure GPIO17 as SPISOMIA
|
||||
//// GpioCtrlRegs.GPAMUX1.bit.GPIO26 = 2; // Configure GPIO18 as SPICLKA
|
||||
//// GpioCtrlRegs.GPAMUX1.bit.GPIO27 = 2; // Configure GPIO19 as SPISTEA
|
||||
//// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO16 as SPISIMOA
|
||||
//// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO17 as SPISOMIA
|
||||
//// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO18 as SPICLKA
|
||||
//// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO19 as SPISTEA
|
||||
// EDIS;
|
||||
//}
|
||||
|
||||
void transmitBData(uint16_t a)
|
||||
{
|
||||
@ -416,61 +416,61 @@ void SpiCInit(void)
|
||||
|
||||
}
|
||||
|
||||
void SpiCGpioInit(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
//
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
//
|
||||
GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on (SPISIMOB)
|
||||
|
||||
|
||||
GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on (SPICLKB)
|
||||
|
||||
|
||||
GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0; // Enable pull-up on (SPISTEB)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
//
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
//
|
||||
GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input(SPISIMOB)
|
||||
|
||||
|
||||
GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input(SPICLKB)
|
||||
|
||||
|
||||
GpioCtrlRegs.GPCQSEL1.bit.GPIO72 = 3; // Asynch input(SPISTEB)
|
||||
|
||||
|
||||
GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;
|
||||
GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0;
|
||||
GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1;
|
||||
GpioDataRegs.GPDDAT.bit.GPIO99 = 0;
|
||||
|
||||
//
|
||||
// Configure SPI-A pins
|
||||
//
|
||||
// This specifies which of the possible GPIO pins will be SPI functional
|
||||
// pins.
|
||||
//
|
||||
GPIO_SetupPinMux(100, 0, 6);
|
||||
|
||||
|
||||
GPIO_SetupPinMux(102, 0, 6);
|
||||
|
||||
|
||||
GPIO_SetupPinMux(72, 0, 15);
|
||||
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
//void SpiCGpioInit(void)
|
||||
//{
|
||||
// EALLOW;
|
||||
//
|
||||
// //
|
||||
// // Enable internal pull-up for the selected pins
|
||||
// //
|
||||
// // Pull-ups can be enabled or disabled by the user.
|
||||
// // This will enable the pullups for the specified pins.
|
||||
// //
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on (SPISIMOB)
|
||||
//
|
||||
//
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on (SPICLKB)
|
||||
//
|
||||
//
|
||||
// GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0; // Enable pull-up on (SPISTEB)
|
||||
//
|
||||
// //
|
||||
// // Set qualification for selected pins to asynch only
|
||||
// //
|
||||
// // This will select asynch (no qualification) for the selected pins.
|
||||
// //
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input(SPISIMOB)
|
||||
//
|
||||
//
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input(SPICLKB)
|
||||
//
|
||||
//
|
||||
// GpioCtrlRegs.GPCQSEL1.bit.GPIO72 = 3; // Asynch input(SPISTEB)
|
||||
//
|
||||
//
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0;
|
||||
// GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1;
|
||||
// GpioDataRegs.GPDDAT.bit.GPIO99 = 0;
|
||||
//
|
||||
// //
|
||||
// // Configure SPI-A pins
|
||||
// //
|
||||
// // This specifies which of the possible GPIO pins will be SPI functional
|
||||
// // pins.
|
||||
// //
|
||||
// GPIO_SetupPinMux(100, 0, 6);
|
||||
//
|
||||
//
|
||||
// GPIO_SetupPinMux(102, 0, 6);
|
||||
//
|
||||
//
|
||||
// GPIO_SetupPinMux(72, 0, 15);
|
||||
//
|
||||
//
|
||||
//
|
||||
// EDIS;
|
||||
//}
|
||||
|
||||
void transmitCData(uint16_t a)
|
||||
{
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* biss.c
|
||||
*
|
||||
* Created on: 26 äåê. 2023 ã.
|
||||
* Created on: 26 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
|
||||
* Author: seklyuts
|
||||
*/
|
||||
#include "f28x_project.h"
|
||||
@ -64,22 +64,22 @@ void BissInit(void)
|
||||
|
||||
|
||||
|
||||
void BissGpioInit(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 2;//14 = 1110
|
||||
GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 3;
|
||||
GpioCtrlRegs.GPDDIR.bit.GPIO96 = 1;
|
||||
GpioDataRegs.GPDDAT.bit.GPIO96 = 0;
|
||||
|
||||
GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 2;//14 = 1110
|
||||
GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 3;
|
||||
GpioCtrlRegs.GPDDIR.bit.GPIO97 = 1;
|
||||
GpioDataRegs.GPDDAT.bit.GPIO97 = 0;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
//void BissGpioInit(void)
|
||||
//{
|
||||
// EALLOW;
|
||||
//
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 2;//14 = 1110
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 3;
|
||||
// GpioCtrlRegs.GPDDIR.bit.GPIO96 = 1;
|
||||
// GpioDataRegs.GPDDAT.bit.GPIO96 = 0;
|
||||
//
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 2;//14 = 1110
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 3;
|
||||
// GpioCtrlRegs.GPDDIR.bit.GPIO97 = 1;
|
||||
// GpioDataRegs.GPDDAT.bit.GPIO97 = 0;
|
||||
//
|
||||
// EDIS;
|
||||
//}
|
||||
|
||||
|
||||
void BissClkgenSetup(unsigned int bits_num_m,
|
||||
|
||||
@ -8,6 +8,10 @@
|
||||
//#include "f2838x_pinmux.h"
|
||||
#include "frm_uart.h"
|
||||
|
||||
#define LSPCLK_HZ 50000000.0
|
||||
#define BAUD 19200.0
|
||||
#define BRR LSPCLK_HZ/(BAUD*8) + 1
|
||||
|
||||
uint16_t frmEn = 0;
|
||||
|
||||
|
||||
@ -26,57 +30,36 @@ void FMSTREnableSet(void)
|
||||
frmEn = 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void FRMUartInit(void)
|
||||
{
|
||||
FMSTR_Init();
|
||||
CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
|
||||
|
||||
// For this example, only init the pins for the SCI-A port.
|
||||
// GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits
|
||||
// GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS
|
||||
// These functions are found in the f2838x_gpio.c file.
|
||||
// EALLOW;
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;
|
||||
// GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
|
||||
// GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
|
||||
// GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
|
||||
// GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
|
||||
//
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; //rx
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; //tx
|
||||
// GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
|
||||
// GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
|
||||
// GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
|
||||
// GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
|
||||
//
|
||||
// EALLOW;
|
||||
// GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
|
||||
// GpioDataRegs.GPADAT.bit.GPIO21 = 1;
|
||||
// GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
|
||||
// GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
|
||||
// EDIS;
|
||||
//
|
||||
// EALLOW;
|
||||
// GpioCtrlRegs.GPCPUD.bit.GPIO84 = 1; //tx
|
||||
// GpioCtrlRegs.GPCPUD.bit.GPIO85 = 0;
|
||||
//
|
||||
// GpioCtrlRegs.GPCMUX2.bit.GPIO28 = 1; //
|
||||
// GpioCtrlRegs.GPCMUX2.bit.GPIO29 = 1; //
|
||||
// EDIS;
|
||||
|
||||
GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
|
||||
GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
|
||||
GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
|
||||
GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
|
||||
|
||||
GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
|
||||
GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
|
||||
GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
|
||||
GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
|
||||
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
|
||||
GpioDataRegs.GPADAT.bit.GPIO21 = 1;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
|
||||
GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
|
||||
EDIS;
|
||||
|
||||
// GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1);
|
||||
// GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL);
|
||||
// GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1);
|
||||
GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
|
||||
// GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
|
||||
//
|
||||
// Note: Clocks were turned on to the SCIA peripheral
|
||||
// in the InitSysCtrl() function
|
||||
//
|
||||
|
||||
EALLOW;
|
||||
SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
|
||||
// No parity,8 char bits,
|
||||
// async mode, idle-line protocol
|
||||
@ -86,36 +69,13 @@ void FRMUartInit(void)
|
||||
SciaRegs.SCICTL2.bit.TXINTENA = 0;
|
||||
SciaRegs.SCICTL2.bit.RXBKINTENA = 0;
|
||||
|
||||
//
|
||||
// SCIA at 9600 baud
|
||||
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B //8A
|
||||
// @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.
|
||||
//
|
||||
//
|
||||
// SCIA at 19200 baud
|
||||
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x45.
|
||||
//
|
||||
//
|
||||
// SCIA at 38400 baud
|
||||
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0xA2.
|
||||
//
|
||||
//
|
||||
// SCIA at 56000 baud
|
||||
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6F.
|
||||
//
|
||||
//
|
||||
// SCIA at 57600 baud
|
||||
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x6C (6B).
|
||||
//
|
||||
//
|
||||
// SCIA at 115200 baud
|
||||
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x35.
|
||||
//
|
||||
SciaRegs.SCIHBAUD.all = 0x0002;
|
||||
SciaRegs.SCILBAUD.all = 0x008B;
|
||||
uint16_t Brr = BRR;
|
||||
|
||||
SciaRegs.SCIHBAUD.all = 0xFF & (Brr>>8);//0x0002;
|
||||
SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B;
|
||||
|
||||
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
|
||||
|
||||
EDIS;
|
||||
FMSTREnableSet();
|
||||
}
|
||||
|
||||
|
||||
@ -29,12 +29,12 @@ static uint16_t diod = 0;
|
||||
counter2++;
|
||||
diod++;
|
||||
if(diod > 7) diod = 0;
|
||||
Gpio_rainbow(diod);
|
||||
//Gpio_rainbow(diod);
|
||||
//FMSTR_SCI_PUTCHAR(0xA5);
|
||||
}
|
||||
}
|
||||
FMSTR_Poll();
|
||||
FMSTR_Recorder();
|
||||
FMSTREnableClr();
|
||||
Gpio95out(Rele);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* init_perif.c
|
||||
*
|
||||
* Created on: 21 àâã. 2023 ã.
|
||||
* Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
|
||||
* Author: seklyuts
|
||||
*/
|
||||
|
||||
@ -27,11 +27,16 @@
|
||||
void InitPerif(void)
|
||||
{
|
||||
|
||||
GpioDiodInit();
|
||||
|
||||
GpioSetGreen();
|
||||
InitSysCtrl();
|
||||
GpioSetBlue();
|
||||
// GpioDiodInit();
|
||||
//
|
||||
// GpioSetGreen();
|
||||
//
|
||||
// EALLOW;
|
||||
// ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
|
||||
// EDIS;
|
||||
//
|
||||
// InitSysCtrl();
|
||||
// GpioSetBlue();
|
||||
|
||||
|
||||
|
||||
@ -64,34 +69,27 @@ void InitPerif(void)
|
||||
//
|
||||
InitPieVectTable();
|
||||
|
||||
GpioInit();
|
||||
//
|
||||
// GpioInit();
|
||||
|
||||
SdfmInitEnable();
|
||||
SdfmInit();
|
||||
SdfmGpioInit();
|
||||
// SdfmGpioInit();
|
||||
SdfmInitInterruptEn();
|
||||
//
|
||||
|
||||
PWMInitEnable();
|
||||
PWMAllInit();
|
||||
PWMGpioInit();
|
||||
// PWMGpioInit();
|
||||
PWMInitInterruptEn();
|
||||
|
||||
vectorInitCurrLoop();
|
||||
|
||||
SpiCInit();
|
||||
SpiCGpioInit();
|
||||
BissGpioInit();
|
||||
BissInit();
|
||||
|
||||
|
||||
|
||||
// SpiGpioInit();
|
||||
// SpiInit();
|
||||
// I2CMasterGpioInit();
|
||||
// I2CMasterInit(I2C_OWN_ADDRESS,I2C_SLAVE_ADDRESS);
|
||||
// SpiCInit();
|
||||
// SpiCGpioInit();
|
||||
// BissGpioInit();
|
||||
// BissInit();
|
||||
|
||||
FRMUartInit();
|
||||
// vectorInitCurrLoop();
|
||||
|
||||
// ConfigureADC();
|
||||
|
||||
//
|
||||
|
||||
Loading…
Reference in New Issue
Block a user