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Виктор Лобов 2024-01-19 12:18:27 +03:00
parent 5b1f1a86a4
commit 21531c9f3b
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CMakeLists.txt Normal file
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cmake_minimum_required( VERSION 3.5)
SET (TARGET_NAME test_project)
#message( STATUS "CMAKE_INSTALL_PREFIX = ${CMAKE_INSTALL_PREFIX}" )
set(CGT_TOOLCHAIN_DIR /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS)
SET(CL2000_LINK ${CGT_TOOLCHAIN_DIR}/bin/cl2000)
SET(CMAKE_CXX_COMPILER ${CL2000_LINK} )
SET(CMAKE_C_COMPILER ${CL2000_LINK} )
SET(CMAKE_CXX_LINK_EXECUTABLE ${CL2000_LINK})
project(cmake_test)
SET (FLAGS -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5
--fp_mode=relaxed -advice:performance=all --define=_INLINE --define=bmin='0.397824735f' --define=amax='0.960433870f'
--float_operations_allowed=32 --printf_support=minimal
--include_path="/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/"
--include_path="/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/" )
include_directories( "${PROJECT_BINARY_DIR}")
add_executable(${TARGET_NAME} main.cpp
./f2833x/common/source/DSP2833x_ADC_cal.asm
./f2833x/common/source/DSP2833x_CodeStartBranch.asm
./f2833x/common/source/DSP2833x_DefaultIsr.c
./f2833x/headers/source/DSP2833x_GlobalVariableDefs.c
./f2833x/common/source/DSP2833x_PieCtrl.c
./f2833x/common/source/DSP2833x_PieVect.c
./f2833x/common/source/DSP2833x_SysCtrl.c
./f2833x/common/source/DSP2833x_usDelay.asm
)
set(INCLUDES
./f2833x
./f2833x/common/include
./f2833x/headers/include
)
target_compile_options (${TARGET_NAME} PRIVATE ${FLAGS}
)
target_include_directories(${TARGET_NAME} PRIVATE ${INCLUDES}
)

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]

BIN
build/Debug/test_project Normal file
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Binary file not shown.

650
build/Debug/test_project.map Normal file
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@ -0,0 +1,650 @@
******************************************************************************
TMS320C2000 Linker Unix v22.6.1
******************************************************************************
>> Linked Fri Jan 19 11:29:33 2024
OUTPUT FILE NAME: <test_project>
ENTRY POINT SYMBOL: "_main" address: 00000000
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
PAGE 0:
PROG 00000040 003fffc0 00000316 003ffcaa RWIX
PAGE 1:
DATA 00000000 00010000 00000a77 0000f589 RW
DATA1 00010000 003f0000 00000000 003f0000 RW
SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.text 0 00000040 00000316
00000040 00000316 DSP2833x_DefaultIsr.c.o (.text:retain)
.data 0 00000040 00000000 UNINITIALIZED
.bss 1 00000000 00000000 UNINITIALIZED
ECanaMboxesFile
* 1 00000000 00000100 UNINITIALIZED
00000000 00000100 DSP2833x_GlobalVariableDefs.c.o (ECanaMboxesFile)
ECanbMboxesFile
* 1 00000100 00000100 UNINITIALIZED
00000100 00000100 DSP2833x_GlobalVariableDefs.c.o (ECanbMboxesFile)
PieVectTableFile
* 1 00000200 00000100 UNINITIALIZED
00000200 00000100 DSP2833x_GlobalVariableDefs.c.o (PieVectTableFile)
DmaRegsFile
* 1 00000300 000000e0 UNINITIALIZED
00000300 000000e0 DSP2833x_GlobalVariableDefs.c.o (DmaRegsFile)
ECap1RegsFile
* 1 000003e0 00000020 UNINITIALIZED
000003e0 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap1RegsFile)
DevEmuRegsFile
* 1 00000400 000000d0 UNINITIALIZED
00000400 000000d0 DSP2833x_GlobalVariableDefs.c.o (DevEmuRegsFile)
GpioCtrlRegsFile
* 1 000004d0 0000002e UNINITIALIZED
000004d0 0000002e DSP2833x_GlobalVariableDefs.c.o (GpioCtrlRegsFile)
PartIdRegsFile
* 1 000004fe 00000001 UNINITIALIZED
000004fe 00000001 DSP2833x_GlobalVariableDefs.c.o (PartIdRegsFile)
ECanaLAMRegsFile
* 1 00000500 00000040 UNINITIALIZED
00000500 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanaLAMRegsFile)
ECanaMOTORegsFile
* 1 00000540 00000040 UNINITIALIZED
00000540 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanaMOTORegsFile)
ECanaMOTSRegsFile
* 1 00000580 00000040 UNINITIALIZED
00000580 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanaMOTSRegsFile)
ECanbLAMRegsFile
* 1 000005c0 00000040 UNINITIALIZED
000005c0 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanbLAMRegsFile)
ECanbMOTORegsFile
* 1 00000600 00000040 UNINITIALIZED
00000600 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanbMOTORegsFile)
ECanbMOTSRegsFile
* 1 00000640 00000040 UNINITIALIZED
00000640 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanbMOTSRegsFile)
EQep1RegsFile
* 1 00000680 00000040 UNINITIALIZED
00000680 00000040 DSP2833x_GlobalVariableDefs.c.o (EQep1RegsFile)
EQep2RegsFile
* 1 000006c0 00000040 UNINITIALIZED
000006c0 00000040 DSP2833x_GlobalVariableDefs.c.o (EQep2RegsFile)
ECanaRegsFile
* 1 00000700 00000034 UNINITIALIZED
00000700 00000034 DSP2833x_GlobalVariableDefs.c.o (ECanaRegsFile)
GpioIntRegsFile
* 1 00000734 0000000a UNINITIALIZED
00000734 0000000a DSP2833x_GlobalVariableDefs.c.o (GpioIntRegsFile)
ECanbRegsFile
* 1 00000740 00000034 UNINITIALIZED
00000740 00000034 DSP2833x_GlobalVariableDefs.c.o (ECanbRegsFile)
CpuTimer0RegsFile
* 1 00000774 00000008 UNINITIALIZED
00000774 00000008 DSP2833x_GlobalVariableDefs.c.o (CpuTimer0RegsFile)
McbspaRegsFile
* 1 00000780 00000025 UNINITIALIZED
00000780 00000025 DSP2833x_GlobalVariableDefs.c.o (McbspaRegsFile)
PieCtrlRegsFile
* 1 000007a5 0000001a UNINITIALIZED
000007a5 0000001a DSP2833x_GlobalVariableDefs.c.o (PieCtrlRegsFile)
McbspbRegsFile
* 1 000007c0 00000025 UNINITIALIZED
000007c0 00000025 DSP2833x_GlobalVariableDefs.c.o (McbspbRegsFile)
AdcMirrorFile
* 1 000007e5 00000010 UNINITIALIZED
000007e5 00000010 DSP2833x_GlobalVariableDefs.c.o (AdcMirrorFile)
CpuTimer1RegsFile
* 1 000007f6 00000008 UNINITIALIZED
000007f6 00000008 DSP2833x_GlobalVariableDefs.c.o (CpuTimer1RegsFile)
EPwm1RegsFile
* 1 00000800 00000022 UNINITIALIZED
00000800 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm1RegsFile)
AdcRegsFile
* 1 00000822 0000001e UNINITIALIZED
00000822 0000001e DSP2833x_GlobalVariableDefs.c.o (AdcRegsFile)
EPwm2RegsFile
* 1 00000840 00000022 UNINITIALIZED
00000840 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm2RegsFile)
XintfRegsFile
* 1 00000862 0000001e UNINITIALIZED
00000862 0000001e DSP2833x_GlobalVariableDefs.c.o (XintfRegsFile)
EPwm3RegsFile
* 1 00000880 00000022 UNINITIALIZED
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CsmRegsFile
* 1 000008a2 00000010 UNINITIALIZED
000008a2 00000010 DSP2833x_GlobalVariableDefs.c.o (CsmRegsFile)
CpuTimer2RegsFile
* 1 000008b2 00000008 UNINITIALIZED
000008b2 00000008 DSP2833x_GlobalVariableDefs.c.o (CpuTimer2RegsFile)
EPwm4RegsFile
* 1 000008c0 00000022 UNINITIALIZED
000008c0 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm4RegsFile)
SciaRegsFile
* 1 000008e2 00000010 UNINITIALIZED
000008e2 00000010 DSP2833x_GlobalVariableDefs.c.o (SciaRegsFile)
CsmPwlFile
* 1 000008f2 00000008 UNINITIALIZED
000008f2 00000008 DSP2833x_GlobalVariableDefs.c.o (CsmPwlFile)
EPwm5RegsFile
* 1 00000900 00000022 UNINITIALIZED
00000900 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm5RegsFile)
ScibRegsFile
* 1 00000922 00000010 UNINITIALIZED
00000922 00000010 DSP2833x_GlobalVariableDefs.c.o (ScibRegsFile)
FlashRegsFile
* 1 00000932 00000008 UNINITIALIZED
00000932 00000008 DSP2833x_GlobalVariableDefs.c.o (FlashRegsFile)
EPwm6RegsFile
* 1 00000940 00000022 UNINITIALIZED
00000940 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm6RegsFile)
ScicRegsFile
* 1 00000962 00000010 UNINITIALIZED
00000962 00000010 DSP2833x_GlobalVariableDefs.c.o (ScicRegsFile)
I2caRegsFile
* 1 00000980 00000022 UNINITIALIZED
00000980 00000022 DSP2833x_GlobalVariableDefs.c.o (I2caRegsFile)
SpiaRegsFile
* 1 000009a2 00000010 UNINITIALIZED
000009a2 00000010 DSP2833x_GlobalVariableDefs.c.o (SpiaRegsFile)
ECap2RegsFile
* 1 000009c0 00000020 UNINITIALIZED
000009c0 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap2RegsFile)
ECap3RegsFile
* 1 000009e0 00000020 UNINITIALIZED
000009e0 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap3RegsFile)
ECap4RegsFile
* 1 00000a00 00000020 UNINITIALIZED
00000a00 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap4RegsFile)
ECap5RegsFile
* 1 00000a20 00000020 UNINITIALIZED
00000a20 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap5RegsFile)
ECap6RegsFile
* 1 00000a40 00000020 UNINITIALIZED
00000a40 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap6RegsFile)
GpioDataRegsFile
* 1 00000a60 00000020 UNINITIALIZED
00000a60 00000020 DSP2833x_GlobalVariableDefs.c.o (GpioDataRegsFile)
SysCtrlRegsFile
* 1 00000a80 00000020 UNINITIALIZED
00000a80 00000020 DSP2833x_GlobalVariableDefs.c.o (SysCtrlRegsFile)
XIntruptRegsFile
* 1 00000aa0 00000010 UNINITIALIZED
00000aa0 00000010 DSP2833x_GlobalVariableDefs.c.o (XIntruptRegsFile)
MODULE SUMMARY
Module code initialized data uninitialized data
------ ---- ---------------- ------------------
CMakeFiles/test_project.dir/f2833x/common/source/
DSP2833x_DefaultIsr.c.o 790 0 0
+--+---------------------------------+------+------------------+--------------------+
Total: 790 0 0
CMakeFiles/test_project.dir/f2833x/headers/source/
DSP2833x_GlobalVariableDefs.c.o 0 0 2679
+--+---------------------------------+------+------------------+--------------------+
Total: 0 0 2679
+--+---------------------------------+------+------------------+--------------------+
Grand Total: 790 0 2679
GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE
address data page name
-------- ---------------- ----
00000000 0 (00000000) _ECanaMboxes
00000100 4 (00000100) _ECanbMboxes
00000200 8 (00000200) _PieVectTable
00000300 c (00000300) _DmaRegs
000003e0 f (000003c0) _ECap1Regs
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000004fe 13 (000004c0) _PartIdRegs
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000005c0 17 (000005c0) _ECanbLAMRegs
00000600 18 (00000600) _ECanbMOTORegs
00000640 19 (00000640) _ECanbMOTSRegs
00000680 1a (00000680) _EQep1Regs
000006c0 1b (000006c0) _EQep2Regs
00000700 1c (00000700) _ECanaRegs
00000734 1c (00000700) _GpioIntRegs
00000740 1d (00000740) _ECanbRegs
00000774 1d (00000740) _CpuTimer0Regs
00000780 1e (00000780) _McbspaRegs
000007a5 1e (00000780) _PieCtrlRegs
000007c0 1f (000007c0) _McbspbRegs
000007e5 1f (000007c0) _AdcMirror
000007f6 1f (000007c0) _CpuTimer1Regs
00000800 20 (00000800) _EPwm1Regs
00000822 20 (00000800) _AdcRegs
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00000862 21 (00000840) _XintfRegs
00000880 22 (00000880) _EPwm3Regs
000008a2 22 (00000880) _CsmRegs
000008b2 22 (00000880) _CpuTimer2Regs
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00000922 24 (00000900) _ScibRegs
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00000a40 29 (00000a40) _ECap6Regs
00000a60 29 (00000a40) _GpioDataRegs
00000a80 2a (00000a80) _SysCtrlRegs
00000aa0 2a (00000a80) _XIntruptRegs
GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
page address name
---- ------- ----
1 00000000 .bss
0 00000040 .data
0 00000040 .text
0 00000126 _ADCINT_ISR
1 000007e5 _AdcMirror
1 00000822 _AdcRegs
1 00000774 _CpuTimer0Regs
1 000007f6 _CpuTimer1Regs
1 000008b2 _CpuTimer2Regs
1 000008f2 _CsmPwl
1 000008a2 _CsmRegs
0 00000054 _DATALOG_ISR
0 00000248 _DINTCH1_ISR
0 00000252 _DINTCH2_ISR
0 0000025c _DINTCH3_ISR
0 00000266 _DINTCH4_ISR
0 00000270 _DINTCH5_ISR
0 0000027a _DINTCH6_ISR
1 00000400 _DevEmuRegs
1 00000300 _DmaRegs
0 000002d4 _ECAN0INTA_ISR
0 000002e8 _ECAN0INTB_ISR
0 000002de _ECAN1INTA_ISR
0 000002f2 _ECAN1INTB_ISR
0 000001bc _ECAP1_INT_ISR
0 000001c6 _ECAP2_INT_ISR
0 000001d0 _ECAP3_INT_ISR
0 000001da _ECAP4_INT_ISR
0 000001e4 _ECAP5_INT_ISR
0 000001ee _ECAP6_INT_ISR
1 00000500 _ECanaLAMRegs
1 00000540 _ECanaMOTORegs
1 00000580 _ECanaMOTSRegs
1 00000000 _ECanaMboxes
1 00000700 _ECanaRegs
1 000005c0 _ECanbLAMRegs
1 00000600 _ECanbMOTORegs
1 00000640 _ECanbMOTSRegs
1 00000100 _ECanbMboxes
1 00000740 _ECanbRegs
1 000003e0 _ECap1Regs
1 000009c0 _ECap2Regs
1 000009e0 _ECap3Regs
1 00000a00 _ECap4Regs
1 00000a20 _ECap5Regs
1 00000a40 _ECap6Regs
0 00000068 _EMUINT_ISR
0 00000180 _EPWM1_INT_ISR
0 00000144 _EPWM1_TZINT_ISR
0 0000018a _EPWM2_INT_ISR
0 0000014e _EPWM2_TZINT_ISR
0 00000194 _EPWM3_INT_ISR
0 00000158 _EPWM3_TZINT_ISR
0 0000019e _EPWM4_INT_ISR
0 00000162 _EPWM4_TZINT_ISR
0 000001a8 _EPWM5_INT_ISR
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0 000001b2 _EPWM6_INT_ISR
0 00000176 _EPWM6_TZINT_ISR
1 00000800 _EPwm1Regs
1 00000840 _EPwm2Regs
1 00000880 _EPwm3Regs
1 000008c0 _EPwm4Regs
1 00000900 _EPwm5Regs
1 00000940 _EPwm6Regs
0 000001f8 _EQEP1_INT_ISR
0 00000202 _EQEP2_INT_ISR
1 00000680 _EQep1Regs
1 000006c0 _EQep2Regs
1 00000932 _FlashRegs
1 000004d0 _GpioCtrlRegs
1 00000a60 _GpioDataRegs
1 00000734 _GpioIntRegs
0 00000284 _I2CINT1A_ISR
0 0000028e _I2CINT2A_ISR
1 00000980 _I2caRegs
0 0000007c _ILLEGAL_ISR
0 00000040 _INT13_ISR
0 0000004a _INT14_ISR
0 00000338 _LUF_ISR
0 0000032e _LVF_ISR
0 00000234 _MRINTA_ISR
0 00000220 _MRINTB_ISR
0 0000023e _MXINTA_ISR
0 0000022a _MXINTB_ISR
1 00000780 _McbspaRegs
1 000007c0 _McbspbRegs
0 00000072 _NMI_ISR
0 00000342 _PIE_RESERVED
1 000004fe _PartIdRegs
1 000007a5 _PieCtrlRegs
1 00000200 _PieVectTable
0 0000005e _RTOSINT_ISR
0 000002ac _SCIRXINTA_ISR
0 000002c0 _SCIRXINTB_ISR
0 00000298 _SCIRXINTC_ISR
0 000002b6 _SCITXINTA_ISR
0 000002ca _SCITXINTB_ISR
0 000002a2 _SCITXINTC_ISR
0 000000fe _SEQ1INT_ISR
0 00000108 _SEQ2INT_ISR
0 0000020c _SPIRXINTA_ISR
0 00000216 _SPITXINTA_ISR
1 000008e2 _SciaRegs
1 00000922 _ScibRegs
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1 000009a2 _SpiaRegs
1 00000a80 _SysCtrlRegs
0 00000130 _TINT0_ISR
0 000000e0 _USER10_ISR
0 000000ea _USER11_ISR
0 000000f4 _USER12_ISR
0 00000086 _USER1_ISR
0 00000090 _USER2_ISR
0 0000009a _USER3_ISR
0 000000a4 _USER4_ISR
0 000000ae _USER5_ISR
0 000000b8 _USER6_ISR
0 000000c2 _USER7_ISR
0 000000cc _USER8_ISR
0 000000d6 _USER9_ISR
0 0000013a _WAKEINT_ISR
0 00000112 _XINT1_ISR
0 0000011c _XINT2_ISR
0 000002fc _XINT3_ISR
0 00000306 _XINT4_ISR
0 00000310 _XINT5_ISR
0 0000031a _XINT6_ISR
0 00000324 _XINT7_ISR
1 00000aa0 _XIntruptRegs
1 00000862 _XintfRegs
abs ffffffff ___TI_pprof_out_hndl
abs ffffffff ___TI_prof_data_size
abs ffffffff ___TI_prof_data_start
abs ffffffff ___binit__
1 00000000 ___bss__
abs ffffffff ___c_args__
abs ffffffff ___cinit__
0 00000040 ___data__
0 00000040 ___edata__
1 00000000 ___end__
0 00000356 ___etext__
abs ffffffff ___pinit__
0 00000040 ___text__
0 0000034c _rsvd_ISR
abs ffffffff binit
abs ffffffff cinit
0 00000040 edata
1 00000000 end
0 00000356 etext
abs ffffffff pinit
GLOBAL SYMBOLS: SORTED BY Symbol Address
page address name
---- ------- ----
0 00000040 .data
0 00000040 .text
0 00000040 _INT13_ISR
0 00000040 ___data__
0 00000040 ___edata__
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6
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{
"files.associations": {
"dsp28x_project.h": "c",
"dsp2833x_device.h": "c"
}
}

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/*
// TI File $Revision: /main/10 $
// Checkin $Date: April 15, 2009 09:57:22 $
//###########################################################################
//
// FILE: 28332_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28332 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28332 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28332
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28332 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : > RAML0, PAGE = 0
#else
ramfuncs : > RAML0, PAGE = 0
#endif
#endif
.text : > RAML1, PAGE = 0
.cinit : > RAML0, PAGE = 0
.pinit : > RAML0, PAGE = 0
.switch : > RAML0, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

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/*
// TI File $Revision: /main/11 $
// Checkin $Date: April 15, 2009 09:57:28 $
//###########################################################################
//
// FILE: 28333_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28333 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28333 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28333
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28333 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : > RAML0, PAGE = 0
#else
ramfuncs : > RAML0, PAGE = 0
#endif
#endif
.text : > RAML1, PAGE = 0
.InitBoot : > RAML1, PAGE = 0
.cinit : > RAML0, PAGE = 0
.pinit : > RAML0, PAGE = 0
.switch : > RAML0, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

218
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/*
// TI File $Revision: /main/9 $
// Checkin $Date: April 15, 2009 09:57:24 $
//###########################################################################
//
// FILE: 28334_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28334 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28334 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28334
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28334 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : > RAML0, PAGE = 0
#else
ramfuncs : > RAML0, PAGE = 0
#endif
#endif
.text : > RAML1, PAGE = 0
.cinit : > RAML0, PAGE = 0
.pinit : > RAML0, PAGE = 0
.switch : > RAML0, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

216
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/*
// TI File $Revision: /main/11 $
// Checkin $Date: April 15, 2009 09:57:28 $
//###########################################################################
//
// FILE: 28335_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28335 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28335 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28335
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28335 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : > RAML0, PAGE = 0
#else
ramfuncs : > RAML0, PAGE = 0
#endif
#endif
.text : >> RAML1 | RAML2, PAGE = 0
.InitBoot : > RAML1, PAGE = 0
.cinit : > RAML0, PAGE = 0
.pinit : > RAML0, PAGE = 0
.switch : > RAML0, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

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f2833x/common/cmd/F28332.cmd Normal file
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/*
// TI File $Revision: /main/9 $
// Checkin $Date: July 9, 2008 13:43:41 $
//###########################################################################
//
// FILE: F28332.cmd
//
// TITLE: Linker Command File For F28332 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28332
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28332 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
ZONE6 : origin = 0x100000, length = 0x100000 /* XINTF zone 6 */
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
ZONE7B : origin = 0x20FC00, length = 0x0000400 /* XINTF zone 7 - data space */
FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
#else
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
#endif
#endif
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAML4 PAGE = 1
.esysmem : > RAMM1 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
/* Allocate 0x400 of XINTF Zone 7 to storing data */
ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

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/*
//###########################################################################
//
// FILE: F28333.cmd
//
// TITLE: Linker Command File For F28333 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28333
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28333 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */
FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */
FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
#else
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
#endif
#endif
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAML4 PAGE = 1
.esysmem : > RAMM1 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
/* Allocate 0x400 of XINTF Zone 7 to storing data */
ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

247
f2833x/common/cmd/F28334.cmd Normal file
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@ -0,0 +1,247 @@
/*
// TI File $Revision: /main/9 $
// Checkin $Date: July 9, 2008 13:43:49 $
//###########################################################################
//
// FILE: F28334.cmd
//
// TITLE: Linker Command File For F28334 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28334
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28334 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
ZONE6 : origin = 0x100000, length = 0x0100000 /* XINTF zone 6 */
ZONE7A : origin = 0x200000, length = 0x000FC00 /* XINTF zone 7 - program space */
FLASHH : origin = 0x320000, length = 0x004000 /* on-chip FLASH */
FLASHG : origin = 0x324000, length = 0x004000 /* on-chip FLASH */
FLASHF : origin = 0x328000, length = 0x004000 /* on-chip FLASH */
FLASHE : origin = 0x32C000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
#else
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
#endif
#endif
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAML4 PAGE = 1
.esysmem : > RAMM1 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
/* Allocate 0x400 of XINTF Zone 7 to storing data */
ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

247
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View File

@ -0,0 +1,247 @@
/*
// TI File $Revision: /main/10 $
// Checkin $Date: July 9, 2008 13:43:56 $
//###########################################################################
//
// FILE: F28335.cmd
//
// TITLE: Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28335
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28335 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */
FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */
FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
#else
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
#endif
#endif
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAML4 PAGE = 1
.esysmem : > RAMM1 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
/* Allocate 0x400 of XINTF Zone 7 to storing data */
ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

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f2833x/common/include/DSP2833x_DefaultIsr.h Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:45:37 $
//###########################################################################
//
// FILE: DSP2833x_DefaultIsr.h
//
// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_DEFAULT_ISR_H
#define DSP2833x_DEFAULT_ISR_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Default Interrupt Service Routine Declarations:
//
// The following function prototypes are for the
// default ISR routines used with the default PIE vector table.
// This default vector table is found in the DSP2833x_PieVect.h
// file.
//
//
// Non-Peripheral Interrupts
//
interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
interrupt void INT14_ISR(void); // CPU-Timer2
interrupt void DATALOG_ISR(void); // Datalogging interrupt
interrupt void RTOSINT_ISR(void); // RTOS interrupt
interrupt void EMUINT_ISR(void); // Emulation interrupt
interrupt void NMI_ISR(void); // Non-maskable interrupt
interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
interrupt void USER1_ISR(void); // User Defined trap 1
interrupt void USER2_ISR(void); // User Defined trap 2
interrupt void USER3_ISR(void); // User Defined trap 3
interrupt void USER4_ISR(void); // User Defined trap 4
interrupt void USER5_ISR(void); // User Defined trap 5
interrupt void USER6_ISR(void); // User Defined trap 6
interrupt void USER7_ISR(void); // User Defined trap 7
interrupt void USER8_ISR(void); // User Defined trap 8
interrupt void USER9_ISR(void); // User Defined trap 9
interrupt void USER10_ISR(void); // User Defined trap 10
interrupt void USER11_ISR(void); // User Defined trap 11
interrupt void USER12_ISR(void); // User Defined trap 12
//
// Group 1 PIE Interrupt Service Routines
//
interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR
interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR
interrupt void XINT1_ISR(void); // External interrupt 1
interrupt void XINT2_ISR(void); // External interrupt 2
interrupt void ADCINT_ISR(void); // ADC
interrupt void TINT0_ISR(void); // Timer 0
interrupt void WAKEINT_ISR(void); // WD
//
// Group 2 PIE Interrupt Service Routines
//
interrupt void EPWM1_TZINT_ISR(void); // EPWM-1
interrupt void EPWM2_TZINT_ISR(void); // EPWM-2
interrupt void EPWM3_TZINT_ISR(void); // EPWM-3
interrupt void EPWM4_TZINT_ISR(void); // EPWM-4
interrupt void EPWM5_TZINT_ISR(void); // EPWM-5
interrupt void EPWM6_TZINT_ISR(void); // EPWM-6
//
// Group 3 PIE Interrupt Service Routines
//
interrupt void EPWM1_INT_ISR(void); // EPWM-1
interrupt void EPWM2_INT_ISR(void); // EPWM-2
interrupt void EPWM3_INT_ISR(void); // EPWM-3
interrupt void EPWM4_INT_ISR(void); // EPWM-4
interrupt void EPWM5_INT_ISR(void); // EPWM-5
interrupt void EPWM6_INT_ISR(void); // EPWM-6
//
// Group 4 PIE Interrupt Service Routines
//
interrupt void ECAP1_INT_ISR(void); // ECAP-1
interrupt void ECAP2_INT_ISR(void); // ECAP-2
interrupt void ECAP3_INT_ISR(void); // ECAP-3
interrupt void ECAP4_INT_ISR(void); // ECAP-4
interrupt void ECAP5_INT_ISR(void); // ECAP-5
interrupt void ECAP6_INT_ISR(void); // ECAP-6
//
// Group 5 PIE Interrupt Service Routines
//
interrupt void EQEP1_INT_ISR(void); // EQEP-1
interrupt void EQEP2_INT_ISR(void); // EQEP-2
//
// Group 6 PIE Interrupt Service Routines
//
interrupt void SPIRXINTA_ISR(void); // SPI-A
interrupt void SPITXINTA_ISR(void); // SPI-A
interrupt void MRINTA_ISR(void); // McBSP-A
interrupt void MXINTA_ISR(void); // McBSP-A
interrupt void MRINTB_ISR(void); // McBSP-B
interrupt void MXINTB_ISR(void); // McBSP-B
//
// Group 7 PIE Interrupt Service Routines
//
interrupt void DINTCH1_ISR(void); // DMA-Channel 1
interrupt void DINTCH2_ISR(void); // DMA-Channel 2
interrupt void DINTCH3_ISR(void); // DMA-Channel 3
interrupt void DINTCH4_ISR(void); // DMA-Channel 4
interrupt void DINTCH5_ISR(void); // DMA-Channel 5
interrupt void DINTCH6_ISR(void); // DMA-Channel 6
//
// Group 8 PIE Interrupt Service Routines
//
interrupt void I2CINT1A_ISR(void); // I2C-A
interrupt void I2CINT2A_ISR(void); // I2C-A
interrupt void SCIRXINTC_ISR(void); // SCI-C
interrupt void SCITXINTC_ISR(void); // SCI-C
//
// Group 9 PIE Interrupt Service Routines
//
interrupt void SCIRXINTA_ISR(void); // SCI-A
interrupt void SCITXINTA_ISR(void); // SCI-A
interrupt void SCIRXINTB_ISR(void); // SCI-B
interrupt void SCITXINTB_ISR(void); // SCI-B
interrupt void ECAN0INTA_ISR(void); // eCAN-A
interrupt void ECAN1INTA_ISR(void); // eCAN-A
interrupt void ECAN0INTB_ISR(void); // eCAN-B
interrupt void ECAN1INTB_ISR(void); // eCAN-B
//
// Group 10 PIE Interrupt Service Routines
//
//
// Group 11 PIE Interrupt Service Routines
//
//
// Group 12 PIE Interrupt Service Routines
//
interrupt void XINT3_ISR(void); // External interrupt 3
interrupt void XINT4_ISR(void); // External interrupt 4
interrupt void XINT5_ISR(void); // External interrupt 5
interrupt void XINT6_ISR(void); // External interrupt 6
interrupt void XINT7_ISR(void); // External interrupt 7
interrupt void LVF_ISR(void); // Latched overflow flag
interrupt void LUF_ISR(void); // Latched underflow flag
//
// Catch-all for Reserved Locations For testing purposes
//
interrupt void PIE_RESERVED(void); // Reserved for test
interrupt void rsvd_ISR(void); // for test
interrupt void INT_NOTUSED_ISR(void); // for unused interrupts
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEFAULT_ISR_H definition
//
// End of file
//

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