diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..c0d9fe1 --- /dev/null +++ b/.cproject @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.project b/.project new file mode 100644 index 0000000..31e755a --- /dev/null +++ b/.project @@ -0,0 +1,27 @@ + + + cmake_test + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..5b6e5aa --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,48 @@ +cmake_minimum_required( VERSION 3.5) + + + +SET (TARGET_NAME test_project) + +#message( STATUS "CMAKE_INSTALL_PREFIX = ${CMAKE_INSTALL_PREFIX}" ) + +set(CGT_TOOLCHAIN_DIR /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS) + +SET(CL2000_LINK ${CGT_TOOLCHAIN_DIR}/bin/cl2000) +SET(CMAKE_CXX_COMPILER ${CL2000_LINK} ) +SET(CMAKE_C_COMPILER ${CL2000_LINK} ) +SET(CMAKE_CXX_LINK_EXECUTABLE ${CL2000_LINK}) + + +project(cmake_test) + +SET (FLAGS -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 + --fp_mode=relaxed -advice:performance=all --define=_INLINE --define=bmin='0.397824735f' --define=amax='0.960433870f' + --float_operations_allowed=32 --printf_support=minimal + --include_path="/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/" + --include_path="/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/" ) + + +include_directories( "${PROJECT_BINARY_DIR}") + +add_executable(${TARGET_NAME} main.cpp + ./f2833x/common/source/DSP2833x_ADC_cal.asm + ./f2833x/common/source/DSP2833x_CodeStartBranch.asm + ./f2833x/common/source/DSP2833x_DefaultIsr.c + ./f2833x/headers/source/DSP2833x_GlobalVariableDefs.c + ./f2833x/common/source/DSP2833x_PieCtrl.c + ./f2833x/common/source/DSP2833x_PieVect.c + ./f2833x/common/source/DSP2833x_SysCtrl.c + ./f2833x/common/source/DSP2833x_usDelay.asm +) + +set(INCLUDES + ./f2833x + ./f2833x/common/include + ./f2833x/headers/include +) + +target_compile_options (${TARGET_NAME} PRIVATE ${FLAGS} +) +target_include_directories(${TARGET_NAME} PRIVATE ${INCLUDES} +) \ No newline at end of file diff --git a/build/.cmake/api/v1/query/client-vscode/query.json b/build/.cmake/api/v1/query/client-vscode/query.json new file mode 100644 index 0000000..82bb964 --- /dev/null +++ b/build/.cmake/api/v1/query/client-vscode/query.json @@ -0,0 +1 @@ +{"requests":[{"kind":"cache","version":2},{"kind":"codemodel","version":2},{"kind":"toolchains","version":1},{"kind":"cmakeFiles","version":1}]} \ No newline at end of file diff --git a/build/.cmake/api/v1/reply/cache-v2-0e52c74274576c2bd4e8.json b/build/.cmake/api/v1/reply/cache-v2-0e52c74274576c2bd4e8.json new file mode 100644 index 0000000..efd8cae --- /dev/null +++ b/build/.cmake/api/v1/reply/cache-v2-0e52c74274576c2bd4e8.json @@ -0,0 +1,1067 @@ +{ + "entries" : + [ + { + "name" : "CMAKE_ADDR2LINE", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/usr/bin/addr2line" + }, + { + "name" : "CMAKE_AR", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/ar2000" + }, + { + "name" : "CMAKE_BUILD_TYPE", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "No help, variable specified on the command line." + } + ], + "type" : "STRING", + "value" : "Debug" + }, + { + "name" : "CMAKE_CACHEFILE_DIR", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "This is the directory where this CMakeCache.txt was created" + } + ], + "type" : "INTERNAL", + "value" : "/home/lobov/workspace/ccs12.5/cmake_test/build" + }, + { + "name" : "CMAKE_CACHE_MAJOR_VERSION", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Major version of cmake used to create the current loaded cache" + } + ], + "type" : "INTERNAL", + "value" : "3" + }, + { + "name" : "CMAKE_CACHE_MINOR_VERSION", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Minor version of cmake used to create the current loaded cache" + } + ], + "type" : "INTERNAL", + "value" : "22" + }, + { + "name" : "CMAKE_CACHE_PATCH_VERSION", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Patch version of cmake used to create the current loaded cache" + } + ], + "type" : "INTERNAL", + "value" : "1" + }, + { + "name" : "CMAKE_COLOR_MAKEFILE", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Enable/Disable color output during build." + } + ], + "type" : "BOOL", + "value" : "ON" + }, + { + "name" : "CMAKE_COMMAND", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Path to CMake executable." + } + ], + "type" : "INTERNAL", + "value" : "/usr/bin/cmake" + }, + { + "name" : "CMAKE_CPACK_COMMAND", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Path to cpack program executable." + } + ], + "type" : "INTERNAL", + "value" : "/usr/bin/cpack" + }, + { + "name" : "CMAKE_CTEST_COMMAND", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Path to ctest program executable." + } + ], + "type" : "INTERNAL", + "value" : "/usr/bin/ctest" + }, + { + "name" : "CMAKE_CXX_FLAGS", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the CXX compiler during all build types." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_CXX_FLAGS_DEBUG", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the CXX compiler during DEBUG builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_CXX_FLAGS_MINSIZEREL", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the CXX compiler during MINSIZEREL builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_CXX_FLAGS_RELEASE", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the CXX compiler during RELEASE builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_CXX_FLAGS_RELWITHDEBINFO", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the CXX compiler during RELWITHDEBINFO builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_C_FLAGS", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the C compiler during all build types." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_C_FLAGS_DEBUG", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the C compiler during DEBUG builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_C_FLAGS_MINSIZEREL", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the C compiler during MINSIZEREL builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_C_FLAGS_RELEASE", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the C compiler during RELEASE builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_C_FLAGS_RELWITHDEBINFO", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the C compiler during RELWITHDEBINFO builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_DLLTOOL", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "CMAKE_DLLTOOL-NOTFOUND" + }, + { + "name" : "CMAKE_EXECUTABLE_FORMAT", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Executable file format" + } + ], + "type" : "INTERNAL", + "value" : "Unknown" + }, + { + "name" : "CMAKE_EXE_LINKER_FLAGS", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during all build types." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_EXE_LINKER_FLAGS_DEBUG", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during DEBUG builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_EXE_LINKER_FLAGS_MINSIZEREL", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during MINSIZEREL builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_EXE_LINKER_FLAGS_RELEASE", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during RELEASE builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during RELWITHDEBINFO builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_EXPORT_COMPILE_COMMANDS", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "No help, variable specified on the command line." + } + ], + "type" : "BOOL", + "value" : "TRUE" + }, + { + "name" : "CMAKE_EXTRA_GENERATOR", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Name of external makefile project generator." + } + ], + "type" : "INTERNAL", + "value" : "" + }, + { + "name" : "CMAKE_GENERATOR", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Name of generator." + } + ], + "type" : "INTERNAL", + "value" : "Unix Makefiles" + }, + { + "name" : "CMAKE_GENERATOR_INSTANCE", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Generator instance identifier." + } + ], + "type" : "INTERNAL", + "value" : "" + }, + { + "name" : "CMAKE_GENERATOR_PLATFORM", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Name of generator platform." + } + ], + "type" : "INTERNAL", + "value" : "" + }, + { + "name" : "CMAKE_GENERATOR_TOOLSET", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Name of generator toolset." + } + ], + "type" : "INTERNAL", + "value" : "" + }, + { + "name" : "CMAKE_HOME_DIRECTORY", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Source directory with the top level CMakeLists.txt file for this project" + } + ], + "type" : "INTERNAL", + "value" : "/home/lobov/workspace/ccs12.5/cmake_test" + }, + { + "name" : "CMAKE_INSTALL_PREFIX", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Install path prefix, prepended onto install directories." + } + ], + "type" : "PATH", + "value" : "/usr/local" + }, + { + "name" : "CMAKE_INSTALL_SO_NO_EXE", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Install .so files without execute permission." + } + ], + "type" : "INTERNAL", + "value" : "1" + }, + { + "name" : "CMAKE_LINKER", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/usr/bin/ld" + }, + { + "name" : "CMAKE_MAKE_PROGRAM", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/usr/bin/gmake" + }, + { + "name" : "CMAKE_MODULE_LINKER_FLAGS", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of modules during all build types." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_MODULE_LINKER_FLAGS_DEBUG", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of modules during DEBUG builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_MODULE_LINKER_FLAGS_MINSIZEREL", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of modules during MINSIZEREL builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_MODULE_LINKER_FLAGS_RELEASE", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of modules during RELEASE builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_MODULE_LINKER_FLAGS_RELWITHDEBINFO", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of modules during RELWITHDEBINFO builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_NM", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/nm2000" + }, + { + "name" : "CMAKE_NUMBER_OF_MAKEFILES", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "number of local generators" + } + ], + "type" : "INTERNAL", + "value" : "1" + }, + { + "name" : "CMAKE_OBJCOPY", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/usr/bin/objcopy" + }, + { + "name" : "CMAKE_OBJDUMP", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/usr/bin/objdump" + }, + { + "name" : "CMAKE_PLATFORM_INFO_INITIALIZED", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Platform information initialized" + } + ], + "type" : "INTERNAL", + "value" : "1" + }, + { + "name" : "CMAKE_PROJECT_DESCRIPTION", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Value Computed by CMake" + } + ], + "type" : "STATIC", + "value" : "" + }, + { + "name" : "CMAKE_PROJECT_HOMEPAGE_URL", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Value Computed by CMake" + } + ], + "type" : "STATIC", + "value" : "" + }, + { + "name" : "CMAKE_PROJECT_NAME", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Value Computed by CMake" + } + ], + "type" : "STATIC", + "value" : "cmake_test" + }, + { + "name" : "CMAKE_RANLIB", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/usr/bin/ranlib" + }, + { + "name" : "CMAKE_READELF", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/usr/bin/readelf" + }, + { + "name" : "CMAKE_ROOT", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Path to CMake installation." + } + ], + "type" : "INTERNAL", + "value" : "/usr/share/cmake-3.22" + }, + { + "name" : "CMAKE_SHARED_LINKER_FLAGS", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of shared libraries during all build types." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_SHARED_LINKER_FLAGS_DEBUG", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of shared libraries during DEBUG builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_SHARED_LINKER_FLAGS_MINSIZEREL", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of shared libraries during MINSIZEREL builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_SHARED_LINKER_FLAGS_RELEASE", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of shared libraries during RELEASE builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_SHARED_LINKER_FLAGS_RELWITHDEBINFO", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of shared libraries during RELWITHDEBINFO builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_SKIP_INSTALL_RPATH", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "If set, runtime paths are not added when installing shared libraries, but are added when building." + } + ], + "type" : "BOOL", + "value" : "NO" + }, + { + "name" : "CMAKE_SKIP_RPATH", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "If set, runtime paths are not added when using shared libraries." + } + ], + "type" : "BOOL", + "value" : "NO" + }, + { + "name" : "CMAKE_STATIC_LINKER_FLAGS", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of static libraries during all build types." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_STATIC_LINKER_FLAGS_DEBUG", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of static libraries during DEBUG builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_STATIC_LINKER_FLAGS_MINSIZEREL", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of static libraries during MINSIZEREL builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_STATIC_LINKER_FLAGS_RELEASE", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of static libraries during RELEASE builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_STATIC_LINKER_FLAGS_RELWITHDEBINFO", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Flags used by the linker during the creation of static libraries during RELWITHDEBINFO builds." + } + ], + "type" : "STRING", + "value" : "" + }, + { + "name" : "CMAKE_STRIP", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "Path to a program." + } + ], + "type" : "FILEPATH", + "value" : "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/strip2000" + }, + { + "name" : "CMAKE_UNAME", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "uname command" + } + ], + "type" : "INTERNAL", + "value" : "/usr/bin/uname" + }, + { + "name" : "CMAKE_VERBOSE_MAKEFILE", + "properties" : + [ + { + "name" : "ADVANCED", + "value" : "1" + }, + { + "name" : "HELPSTRING", + "value" : "If this value is on, makefiles will be generated without the .SILENT directive, and all commands will be echoed to the console during the make. This is useful for debugging only. With Visual Studio IDE projects all commands are done without /nologo." + } + ], + "type" : "BOOL", + "value" : "FALSE" + }, + { + "name" : "cmake_test_BINARY_DIR", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Value Computed by CMake" + } + ], + "type" : "STATIC", + "value" : "/home/lobov/workspace/ccs12.5/cmake_test/build" + }, + { + "name" : "cmake_test_IS_TOP_LEVEL", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Value Computed by CMake" + } + ], + "type" : "STATIC", + "value" : "ON" + }, + { + "name" : "cmake_test_SOURCE_DIR", + "properties" : + [ + { + "name" : "HELPSTRING", + "value" : "Value Computed by CMake" + } + ], + "type" : "STATIC", + "value" : "/home/lobov/workspace/ccs12.5/cmake_test" + } + ], + "kind" : "cache", + "version" : + { + "major" : 2, + "minor" : 0 + } +} diff --git a/build/.cmake/api/v1/reply/cmakeFiles-v1-2a481a7a1f8814d7229f.json b/build/.cmake/api/v1/reply/cmakeFiles-v1-2a481a7a1f8814d7229f.json new file mode 100644 index 0000000..03c40f2 --- /dev/null +++ b/build/.cmake/api/v1/reply/cmakeFiles-v1-2a481a7a1f8814d7229f.json @@ -0,0 +1,136 @@ +{ + "inputs" : + [ + { + "path" : "CMakeLists.txt" + }, + { + "isGenerated" : true, + "path" : "build/CMakeFiles/3.22.1/CMakeSystem.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeSystemSpecificInitialize.cmake" + }, + { + "isGenerated" : true, + "path" : "build/CMakeFiles/3.22.1/CMakeCCompiler.cmake" + }, + { + "isGenerated" : true, + "path" : "build/CMakeFiles/3.22.1/CMakeCXXCompiler.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeSystemSpecificInformation.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeGenericSystem.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeInitializeConfigs.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Platform/Linux.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Platform/UnixPaths.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeCInformation.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeLanguageInformation.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Compiler/TI-C.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Compiler/TI.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Compiler/CMakeCommonCompilerMacros.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Platform/Linux.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Platform/UnixPaths.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeCommonLanguageInclude.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeCXXInformation.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeLanguageInformation.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Compiler/TI-CXX.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Compiler/TI.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Platform/Linux.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/Platform/UnixPaths.cmake" + }, + { + "isCMake" : true, + "isExternal" : true, + "path" : "/usr/share/cmake-3.22/Modules/CMakeCommonLanguageInclude.cmake" + } + ], + "kind" : "cmakeFiles", + "paths" : + { + "build" : "/home/lobov/workspace/ccs12.5/cmake_test/build", + "source" : "/home/lobov/workspace/ccs12.5/cmake_test" + }, + "version" : + { + "major" : 1, + "minor" : 0 + } +} diff --git a/build/.cmake/api/v1/reply/codemodel-v2-08b5dd6ad53f07ebd3c6.json b/build/.cmake/api/v1/reply/codemodel-v2-08b5dd6ad53f07ebd3c6.json new file mode 100644 index 0000000..9f2a0b6 --- /dev/null +++ b/build/.cmake/api/v1/reply/codemodel-v2-08b5dd6ad53f07ebd3c6.json @@ -0,0 +1,60 @@ +{ + "configurations" : + [ + { + "directories" : + [ + { + "build" : ".", + "jsonFile" : "directory-.-Debug-f5ebdc15457944623624.json", + "minimumCMakeVersion" : + { + "string" : "3.5" + }, + "projectIndex" : 0, + "source" : ".", + "targetIndexes" : + [ + 0 + ] + } + ], + "name" : "Debug", + "projects" : + [ + { + "directoryIndexes" : + [ + 0 + ], + "name" : "cmake_test", + "targetIndexes" : + [ + 0 + ] + } + ], + "targets" : + [ + { + "directoryIndex" : 0, + "id" : "test_project::@6890427a1f51a3e7e1df", + "jsonFile" : "target-test_project-Debug-bef79452e8ea086479b2.json", + "name" : "test_project", + "projectIndex" : 0 + } + ] + } + ], + "kind" : "codemodel", + "paths" : + { + "build" : "/home/lobov/workspace/ccs12.5/cmake_test/build", + "source" : "/home/lobov/workspace/ccs12.5/cmake_test" + }, + "version" : + { + "major" : 2, + "minor" : 3 + } +} diff --git a/build/.cmake/api/v1/reply/directory-.-Debug-f5ebdc15457944623624.json b/build/.cmake/api/v1/reply/directory-.-Debug-f5ebdc15457944623624.json new file mode 100644 index 0000000..3a67af9 --- /dev/null +++ b/build/.cmake/api/v1/reply/directory-.-Debug-f5ebdc15457944623624.json @@ -0,0 +1,14 @@ +{ + "backtraceGraph" : + { + "commands" : [], + "files" : [], + "nodes" : [] + }, + "installers" : [], + "paths" : + { + "build" : ".", + "source" : "." + } +} diff --git a/build/.cmake/api/v1/reply/index-2024-01-19T08-29-21-0604.json b/build/.cmake/api/v1/reply/index-2024-01-19T08-29-21-0604.json new file mode 100644 index 0000000..bba608f --- /dev/null +++ b/build/.cmake/api/v1/reply/index-2024-01-19T08-29-21-0604.json @@ -0,0 +1,132 @@ +{ + "cmake" : + { + "generator" : + { + "multiConfig" : false, + "name" : "Unix Makefiles" + }, + "paths" : + { + "cmake" : "/usr/bin/cmake", + "cpack" : "/usr/bin/cpack", + "ctest" : "/usr/bin/ctest", + "root" : "/usr/share/cmake-3.22" + }, + "version" : + { + "isDirty" : false, + "major" : 3, + "minor" : 22, + "patch" : 1, + "string" : "3.22.1", + "suffix" : "" + } + }, + "objects" : + [ + { + "jsonFile" : "codemodel-v2-08b5dd6ad53f07ebd3c6.json", + "kind" : "codemodel", + "version" : + { + "major" : 2, + "minor" : 3 + } + }, + { + "jsonFile" : "cache-v2-0e52c74274576c2bd4e8.json", + "kind" : "cache", + "version" : + { + "major" : 2, + "minor" : 0 + } + }, + { + "jsonFile" : "cmakeFiles-v1-2a481a7a1f8814d7229f.json", + "kind" : "cmakeFiles", + "version" : + { + "major" : 1, + "minor" : 0 + } + }, + { + "jsonFile" : "toolchains-v1-7e6a9faffa7b0e0102fa.json", + "kind" : "toolchains", + "version" : + { + "major" : 1, + "minor" : 0 + } + } + ], + "reply" : + { + "client-vscode" : + { + "query.json" : + { + "requests" : + [ + { + "kind" : "cache", + "version" : 2 + }, + { + "kind" : "codemodel", + "version" : 2 + }, + { + "kind" : "toolchains", + "version" : 1 + }, + { + "kind" : "cmakeFiles", + "version" : 1 + } + ], + "responses" : + [ + { + "jsonFile" : "cache-v2-0e52c74274576c2bd4e8.json", + "kind" : "cache", + "version" : + { + "major" : 2, + "minor" : 0 + } + }, + { + "jsonFile" : "codemodel-v2-08b5dd6ad53f07ebd3c6.json", + "kind" : "codemodel", + "version" : + { + "major" : 2, + "minor" : 3 + } + }, + { + "jsonFile" : "toolchains-v1-7e6a9faffa7b0e0102fa.json", + "kind" : "toolchains", + "version" : + { + "major" : 1, + "minor" : 0 + } + }, + { + "jsonFile" : "cmakeFiles-v1-2a481a7a1f8814d7229f.json", + "kind" : "cmakeFiles", + "version" : + { + "major" : 1, + "minor" : 0 + } + } + ] + } + } + } +} diff --git a/build/.cmake/api/v1/reply/target-test_project-Debug-bef79452e8ea086479b2.json b/build/.cmake/api/v1/reply/target-test_project-Debug-bef79452e8ea086479b2.json new file mode 100644 index 0000000..c7cd830 --- /dev/null +++ b/build/.cmake/api/v1/reply/target-test_project-Debug-bef79452e8ea086479b2.json @@ -0,0 +1,336 @@ +{ + "artifacts" : + [ + { + "path" : "test_project" + } + ], + "backtrace" : 1, + "backtraceGraph" : + { + "commands" : + [ + "add_executable", + "target_compile_options", + "include_directories", + "target_include_directories" + ], + "files" : + [ + "CMakeLists.txt" + ], + "nodes" : + [ + { + "file" : 0 + }, + { + "command" : 0, + "file" : 0, + "line" : 28, + "parent" : 0 + }, + { + "command" : 1, + "file" : 0, + "line" : 45, + "parent" : 0 + }, + { + "command" : 2, + "file" : 0, + "line" : 26, + "parent" : 0 + }, + { + "command" : 3, + "file" : 0, + "line" : 47, + "parent" : 0 + } + ] + }, + "compileGroups" : + [ + { + "compileCommandFragments" : + [ + { + "backtrace" : 2, + "fragment" : "-v28" + }, + { + "backtrace" : 2, + "fragment" : "-ml" + }, + { + "backtrace" : 2, + "fragment" : "-mt" + }, + { + "backtrace" : 2, + "fragment" : "--float_support=fpu32" + }, + { + "backtrace" : 2, + "fragment" : "-Ooff" + }, + { + "backtrace" : 2, + "fragment" : "--opt_for_speed=5" + }, + { + "backtrace" : 2, + "fragment" : "--fp_mode=relaxed" + }, + { + "backtrace" : 2, + "fragment" : "-advice:performance=all" + }, + { + "backtrace" : 2, + "fragment" : "--define=_INLINE" + }, + { + "backtrace" : 2, + "fragment" : "\"--define=bmin='0.397824735f'\"" + }, + { + "backtrace" : 2, + "fragment" : "\"--define=amax='0.960433870f'\"" + }, + { + "backtrace" : 2, + "fragment" : "--float_operations_allowed=32" + }, + { + "backtrace" : 2, + "fragment" : "--printf_support=minimal" + }, + { + "backtrace" : 2, + "fragment" : "--include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\"" + }, + { + "backtrace" : 2, + "fragment" : "--include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\"" + } + ], + "includes" : + [ + { + "backtrace" : 3, + "path" : "/home/lobov/workspace/ccs12.5/cmake_test/build" + }, + { + "backtrace" : 4, + "path" : "/home/lobov/workspace/ccs12.5/cmake_test/./f2833x" + }, + { + "backtrace" : 4, + "path" : "/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include" + }, + { + "backtrace" : 4, + "path" : "/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include" + } + ], + "language" : "CXX", + "sourceIndexes" : + [ + 0 + ] + }, + { + "compileCommandFragments" : + [ + { + "backtrace" : 2, + "fragment" : "-v28" + }, + { + "backtrace" : 2, + "fragment" : "-ml" + }, + { + "backtrace" : 2, + "fragment" : "-mt" + }, + { + "backtrace" : 2, + "fragment" : "--float_support=fpu32" + }, + { + "backtrace" : 2, + "fragment" : "-Ooff" + }, + { + "backtrace" : 2, + "fragment" : "--opt_for_speed=5" + }, + { + "backtrace" : 2, + "fragment" : "--fp_mode=relaxed" + }, + { + "backtrace" : 2, + "fragment" : "-advice:performance=all" + }, + { + "backtrace" : 2, + "fragment" : "--define=_INLINE" + }, + { + "backtrace" : 2, + "fragment" : "\"--define=bmin='0.397824735f'\"" + }, + { + "backtrace" : 2, + "fragment" : "\"--define=amax='0.960433870f'\"" + }, + { + "backtrace" : 2, + "fragment" : "--float_operations_allowed=32" + }, + { + "backtrace" : 2, + "fragment" : "--printf_support=minimal" + }, + { + "backtrace" : 2, + "fragment" : "--include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\"" + }, + { + "backtrace" : 2, + "fragment" : "--include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\"" + } + ], + "includes" : + [ + { + "backtrace" : 3, + "path" : "/home/lobov/workspace/ccs12.5/cmake_test/build" + }, + { + "backtrace" : 4, + "path" : "/home/lobov/workspace/ccs12.5/cmake_test/./f2833x" + }, + { + "backtrace" : 4, + "path" : "/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include" + }, + { + "backtrace" : 4, + "path" : "/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include" + } + ], + "language" : "C", + "sourceIndexes" : + [ + 3, + 4, + 5, + 6, + 7 + ] + } + ], + "id" : "test_project::@6890427a1f51a3e7e1df", + "link" : + { + "commandFragments" : + [ + { + "fragment" : "", + "role" : "flags" + } + ], + "language" : "CXX" + }, + "name" : "test_project", + "nameOnDisk" : "test_project", + "paths" : + { + "build" : ".", + "source" : "." + }, + "sourceGroups" : + [ + { + "name" : "Source Files", + "sourceIndexes" : + [ + 0, + 3, + 4, + 5, + 6, + 7 + ] + }, + { + "name" : "", + "sourceIndexes" : + [ + 1, + 2, + 8 + ] + } + ], + "sources" : + [ + { + "backtrace" : 1, + "compileGroupIndex" : 0, + "path" : "main.cpp", + "sourceGroupIndex" : 0 + }, + { + "backtrace" : 1, + "path" : "f2833x/common/source/DSP2833x_ADC_cal.asm", + "sourceGroupIndex" : 1 + }, + { + "backtrace" : 1, + "path" : "f2833x/common/source/DSP2833x_CodeStartBranch.asm", + "sourceGroupIndex" : 1 + }, + { + "backtrace" : 1, + "compileGroupIndex" : 1, + "path" : "f2833x/common/source/DSP2833x_DefaultIsr.c", + "sourceGroupIndex" : 0 + }, + { + "backtrace" : 1, + "compileGroupIndex" : 1, + "path" : "f2833x/headers/source/DSP2833x_GlobalVariableDefs.c", + "sourceGroupIndex" : 0 + }, + { + "backtrace" : 1, + "compileGroupIndex" : 1, + "path" : "f2833x/common/source/DSP2833x_PieCtrl.c", + "sourceGroupIndex" : 0 + }, + { + "backtrace" : 1, + "compileGroupIndex" : 1, + "path" : "f2833x/common/source/DSP2833x_PieVect.c", + "sourceGroupIndex" : 0 + }, + { + "backtrace" : 1, + "compileGroupIndex" : 1, + "path" : "f2833x/common/source/DSP2833x_SysCtrl.c", + "sourceGroupIndex" : 0 + }, + { + "backtrace" : 1, + "path" : "f2833x/common/source/DSP2833x_usDelay.asm", + "sourceGroupIndex" : 1 + } + ], + "type" : "EXECUTABLE" +} diff --git a/build/.cmake/api/v1/reply/toolchains-v1-7e6a9faffa7b0e0102fa.json b/build/.cmake/api/v1/reply/toolchains-v1-7e6a9faffa7b0e0102fa.json new file mode 100644 index 0000000..b27bd83 --- /dev/null +++ b/build/.cmake/api/v1/reply/toolchains-v1-7e6a9faffa7b0e0102fa.json @@ -0,0 +1,68 @@ +{ + "kind" : "toolchains", + "toolchains" : + [ + { + "compiler" : + { + "id" : "TI", + "implicit" : + { + "includeDirectories" : + [ + "/usr/include" + ], + "linkDirectories" : [], + "linkFrameworkDirectories" : [], + "linkLibraries" : [] + }, + "path" : "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000", + "version" : "22.6.1" + }, + "language" : "C", + "sourceFileExtensions" : + [ + "c", + "m" + ] + }, + { + "compiler" : + { + "id" : "TI", + "implicit" : + { + "includeDirectories" : + [ + "/usr/include" + ], + "linkDirectories" : [], + "linkFrameworkDirectories" : [], + "linkLibraries" : [] + }, + "path" : "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000", + "version" : "22.6.1" + }, + "language" : "CXX", + "sourceFileExtensions" : + [ + "C", + "M", + "c++", + "cc", + "cpp", + "cxx", + "mm", + "mpp", + "CPP", + "ixx", + "cppm" + ] + } + ], + "version" : + { + "major" : 1, + "minor" : 0 + } +} diff --git a/build/CMakeCache.txt b/build/CMakeCache.txt new file mode 100644 index 0000000..24292f4 --- /dev/null +++ b/build/CMakeCache.txt @@ -0,0 +1,332 @@ +# This is the CMakeCache file. +# For build in directory: /home/lobov/workspace/ccs12.5/cmake_test/build +# It was generated by CMake: /usr/bin/cmake +# You can edit this file to change values found and used by cmake. +# If you do not want to change any of the values, simply exit the editor. +# If you do want to change a value, simply edit, save, and exit the editor. +# The syntax for the file is as follows: +# KEY:TYPE=VALUE +# KEY is the name of a variable in the cache. +# TYPE is a hint to GUIs for the type of VALUE, DO NOT EDIT TYPE!. +# VALUE is the current value for the KEY. + +######################## +# EXTERNAL cache entries +######################## + +//Path to a program. +CMAKE_ADDR2LINE:FILEPATH=/usr/bin/addr2line + +//Path to a program. +CMAKE_AR:FILEPATH=/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/ar2000 + +//No help, variable specified on the command line. +CMAKE_BUILD_TYPE:STRING=Debug + +//Enable/Disable color output during build. +CMAKE_COLOR_MAKEFILE:BOOL=ON + +//Flags used by the CXX compiler during all build types. +CMAKE_CXX_FLAGS:STRING= + +//Flags used by the CXX compiler during DEBUG builds. +CMAKE_CXX_FLAGS_DEBUG:STRING= + +//Flags used by the CXX compiler during MINSIZEREL builds. +CMAKE_CXX_FLAGS_MINSIZEREL:STRING= + +//Flags used by the CXX compiler during RELEASE builds. +CMAKE_CXX_FLAGS_RELEASE:STRING= + +//Flags used by the CXX compiler during RELWITHDEBINFO builds. +CMAKE_CXX_FLAGS_RELWITHDEBINFO:STRING= + +//Flags used by the C compiler during all build types. +CMAKE_C_FLAGS:STRING= + +//Flags used by the C compiler during DEBUG builds. +CMAKE_C_FLAGS_DEBUG:STRING= + +//Flags used by the C compiler during MINSIZEREL builds. +CMAKE_C_FLAGS_MINSIZEREL:STRING= + +//Flags used by the C compiler during RELEASE builds. +CMAKE_C_FLAGS_RELEASE:STRING= + +//Flags used by the C compiler during RELWITHDEBINFO builds. +CMAKE_C_FLAGS_RELWITHDEBINFO:STRING= + +//Path to a program. +CMAKE_DLLTOOL:FILEPATH=CMAKE_DLLTOOL-NOTFOUND + +//Flags used by the linker during all build types. +CMAKE_EXE_LINKER_FLAGS:STRING= + +//Flags used by the linker during DEBUG builds. +CMAKE_EXE_LINKER_FLAGS_DEBUG:STRING= + +//Flags used by the linker during MINSIZEREL builds. +CMAKE_EXE_LINKER_FLAGS_MINSIZEREL:STRING= + +//Flags used by the linker during RELEASE builds. +CMAKE_EXE_LINKER_FLAGS_RELEASE:STRING= + +//Flags used by the linker during RELWITHDEBINFO builds. +CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO:STRING= + +//No help, variable specified on the command line. +CMAKE_EXPORT_COMPILE_COMMANDS:BOOL=TRUE + +//Install path prefix, prepended onto install directories. +CMAKE_INSTALL_PREFIX:PATH=/usr/local + +//Path to a program. +CMAKE_LINKER:FILEPATH=/usr/bin/ld + +//Path to a program. +CMAKE_MAKE_PROGRAM:FILEPATH=/usr/bin/gmake + +//Flags used by the linker during the creation of modules during +// all build types. +CMAKE_MODULE_LINKER_FLAGS:STRING= + +//Flags used by the linker during the creation of modules during +// DEBUG builds. +CMAKE_MODULE_LINKER_FLAGS_DEBUG:STRING= + +//Flags used by the linker during the creation of modules during +// MINSIZEREL builds. +CMAKE_MODULE_LINKER_FLAGS_MINSIZEREL:STRING= + +//Flags used by the linker during the creation of modules during +// RELEASE builds. +CMAKE_MODULE_LINKER_FLAGS_RELEASE:STRING= + +//Flags used by the linker during the creation of modules during +// RELWITHDEBINFO builds. +CMAKE_MODULE_LINKER_FLAGS_RELWITHDEBINFO:STRING= + +//Path to a program. +CMAKE_NM:FILEPATH=/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/nm2000 + +//Path to a program. +CMAKE_OBJCOPY:FILEPATH=/usr/bin/objcopy + +//Path to a program. +CMAKE_OBJDUMP:FILEPATH=/usr/bin/objdump + +//Value Computed by CMake +CMAKE_PROJECT_DESCRIPTION:STATIC= + +//Value Computed by CMake +CMAKE_PROJECT_HOMEPAGE_URL:STATIC= + +//Value Computed by CMake +CMAKE_PROJECT_NAME:STATIC=cmake_test + +//Path to a program. +CMAKE_RANLIB:FILEPATH=/usr/bin/ranlib + +//Path to a program. +CMAKE_READELF:FILEPATH=/usr/bin/readelf + +//Flags used by the linker during the creation of shared libraries +// during all build types. +CMAKE_SHARED_LINKER_FLAGS:STRING= + +//Flags used by the linker during the creation of shared libraries +// during DEBUG builds. +CMAKE_SHARED_LINKER_FLAGS_DEBUG:STRING= + +//Flags used by the linker during the creation of shared libraries +// during MINSIZEREL builds. +CMAKE_SHARED_LINKER_FLAGS_MINSIZEREL:STRING= + +//Flags used by the linker during the creation of shared libraries +// during RELEASE builds. +CMAKE_SHARED_LINKER_FLAGS_RELEASE:STRING= + +//Flags used by the linker during the creation of shared libraries +// during RELWITHDEBINFO builds. +CMAKE_SHARED_LINKER_FLAGS_RELWITHDEBINFO:STRING= + +//If set, runtime paths are not added when installing shared libraries, +// but are added when building. +CMAKE_SKIP_INSTALL_RPATH:BOOL=NO + +//If set, runtime paths are not added when using shared libraries. +CMAKE_SKIP_RPATH:BOOL=NO + +//Flags used by the linker during the creation of static libraries +// during all build types. +CMAKE_STATIC_LINKER_FLAGS:STRING= + +//Flags used by the linker during the creation of static libraries +// during DEBUG builds. +CMAKE_STATIC_LINKER_FLAGS_DEBUG:STRING= + +//Flags used by the linker during the creation of static libraries +// during MINSIZEREL builds. +CMAKE_STATIC_LINKER_FLAGS_MINSIZEREL:STRING= + +//Flags used by the linker during the creation of static libraries +// during RELEASE builds. +CMAKE_STATIC_LINKER_FLAGS_RELEASE:STRING= + +//Flags used by the linker during the creation of static libraries +// during RELWITHDEBINFO builds. +CMAKE_STATIC_LINKER_FLAGS_RELWITHDEBINFO:STRING= + +//Path to a program. +CMAKE_STRIP:FILEPATH=/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/strip2000 + +//If this value is on, makefiles will be generated without the +// .SILENT directive, and all commands will be echoed to the console +// during the make. This is useful for debugging only. With Visual +// Studio IDE projects all commands are done without /nologo. +CMAKE_VERBOSE_MAKEFILE:BOOL=FALSE + +//Value Computed by CMake +cmake_test_BINARY_DIR:STATIC=/home/lobov/workspace/ccs12.5/cmake_test/build + +//Value Computed by CMake +cmake_test_IS_TOP_LEVEL:STATIC=ON + +//Value Computed by CMake +cmake_test_SOURCE_DIR:STATIC=/home/lobov/workspace/ccs12.5/cmake_test + + +######################## +# INTERNAL cache entries +######################## + +//ADVANCED property for variable: CMAKE_ADDR2LINE +CMAKE_ADDR2LINE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_AR +CMAKE_AR-ADVANCED:INTERNAL=1 +//This is the directory where this CMakeCache.txt was created +CMAKE_CACHEFILE_DIR:INTERNAL=/home/lobov/workspace/ccs12.5/cmake_test/build +//Major version of cmake used to create the current loaded cache +CMAKE_CACHE_MAJOR_VERSION:INTERNAL=3 +//Minor version of cmake used to create the current loaded cache +CMAKE_CACHE_MINOR_VERSION:INTERNAL=22 +//Patch version of cmake used to create the current loaded cache +CMAKE_CACHE_PATCH_VERSION:INTERNAL=1 +//ADVANCED property for variable: CMAKE_COLOR_MAKEFILE +CMAKE_COLOR_MAKEFILE-ADVANCED:INTERNAL=1 +//Path to CMake executable. +CMAKE_COMMAND:INTERNAL=/usr/bin/cmake +//Path to cpack program executable. +CMAKE_CPACK_COMMAND:INTERNAL=/usr/bin/cpack +//Path to ctest program executable. +CMAKE_CTEST_COMMAND:INTERNAL=/usr/bin/ctest +//ADVANCED property for variable: CMAKE_CXX_FLAGS +CMAKE_CXX_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_CXX_FLAGS_DEBUG +CMAKE_CXX_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_CXX_FLAGS_MINSIZEREL +CMAKE_CXX_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_CXX_FLAGS_RELEASE +CMAKE_CXX_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_CXX_FLAGS_RELWITHDEBINFO +CMAKE_CXX_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS +CMAKE_C_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS_DEBUG +CMAKE_C_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS_MINSIZEREL +CMAKE_C_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS_RELEASE +CMAKE_C_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS_RELWITHDEBINFO +CMAKE_C_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_DLLTOOL +CMAKE_DLLTOOL-ADVANCED:INTERNAL=1 +//Executable file format +CMAKE_EXECUTABLE_FORMAT:INTERNAL=Unknown +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS +CMAKE_EXE_LINKER_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS_DEBUG +CMAKE_EXE_LINKER_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS_MINSIZEREL +CMAKE_EXE_LINKER_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS_RELEASE +CMAKE_EXE_LINKER_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO +CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//Name of external makefile project generator. +CMAKE_EXTRA_GENERATOR:INTERNAL= +//Name of generator. +CMAKE_GENERATOR:INTERNAL=Unix Makefiles +//Generator instance identifier. +CMAKE_GENERATOR_INSTANCE:INTERNAL= +//Name of generator platform. +CMAKE_GENERATOR_PLATFORM:INTERNAL= +//Name of generator toolset. +CMAKE_GENERATOR_TOOLSET:INTERNAL= +//Source directory with the top level CMakeLists.txt file for this +// project +CMAKE_HOME_DIRECTORY:INTERNAL=/home/lobov/workspace/ccs12.5/cmake_test +//Install .so files without execute permission. +CMAKE_INSTALL_SO_NO_EXE:INTERNAL=1 +//ADVANCED property for variable: CMAKE_LINKER +CMAKE_LINKER-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MAKE_PROGRAM +CMAKE_MAKE_PROGRAM-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS +CMAKE_MODULE_LINKER_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS_DEBUG +CMAKE_MODULE_LINKER_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS_MINSIZEREL +CMAKE_MODULE_LINKER_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS_RELEASE +CMAKE_MODULE_LINKER_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS_RELWITHDEBINFO +CMAKE_MODULE_LINKER_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_NM +CMAKE_NM-ADVANCED:INTERNAL=1 +//number of local generators +CMAKE_NUMBER_OF_MAKEFILES:INTERNAL=1 +//ADVANCED property for variable: CMAKE_OBJCOPY +CMAKE_OBJCOPY-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_OBJDUMP +CMAKE_OBJDUMP-ADVANCED:INTERNAL=1 +//Platform information initialized +CMAKE_PLATFORM_INFO_INITIALIZED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_RANLIB +CMAKE_RANLIB-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_READELF +CMAKE_READELF-ADVANCED:INTERNAL=1 +//Path to CMake installation. +CMAKE_ROOT:INTERNAL=/usr/share/cmake-3.22 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS +CMAKE_SHARED_LINKER_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS_DEBUG +CMAKE_SHARED_LINKER_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS_MINSIZEREL +CMAKE_SHARED_LINKER_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS_RELEASE +CMAKE_SHARED_LINKER_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS_RELWITHDEBINFO +CMAKE_SHARED_LINKER_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SKIP_INSTALL_RPATH +CMAKE_SKIP_INSTALL_RPATH-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SKIP_RPATH +CMAKE_SKIP_RPATH-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS +CMAKE_STATIC_LINKER_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS_DEBUG +CMAKE_STATIC_LINKER_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS_MINSIZEREL +CMAKE_STATIC_LINKER_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS_RELEASE +CMAKE_STATIC_LINKER_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS_RELWITHDEBINFO +CMAKE_STATIC_LINKER_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STRIP +CMAKE_STRIP-ADVANCED:INTERNAL=1 +//uname command +CMAKE_UNAME:INTERNAL=/usr/bin/uname +//ADVANCED property for variable: CMAKE_VERBOSE_MAKEFILE +CMAKE_VERBOSE_MAKEFILE-ADVANCED:INTERNAL=1 + diff --git a/build/CMakeFiles/3.22.1/CMakeCCompiler.cmake b/build/CMakeFiles/3.22.1/CMakeCCompiler.cmake new file mode 100644 index 0000000..e5e1cb6 --- /dev/null +++ b/build/CMakeFiles/3.22.1/CMakeCCompiler.cmake @@ -0,0 +1,72 @@ +set(CMAKE_C_COMPILER "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000") +set(CMAKE_C_COMPILER_ARG1 "") +set(CMAKE_C_COMPILER_ID "TI") +set(CMAKE_C_COMPILER_VERSION "22.6.1") +set(CMAKE_C_COMPILER_VERSION_INTERNAL "") +set(CMAKE_C_COMPILER_WRAPPER "") +set(CMAKE_C_STANDARD_COMPUTED_DEFAULT "90") +set(CMAKE_C_EXTENSIONS_COMPUTED_DEFAULT "ON") +set(CMAKE_C_COMPILE_FEATURES "c_std_90;c_std_99;c_std_11") +set(CMAKE_C90_COMPILE_FEATURES "c_std_90") +set(CMAKE_C99_COMPILE_FEATURES "c_std_99") +set(CMAKE_C11_COMPILE_FEATURES "c_std_11") +set(CMAKE_C17_COMPILE_FEATURES "") +set(CMAKE_C23_COMPILE_FEATURES "") + +set(CMAKE_C_PLATFORM_ID "") +set(CMAKE_C_SIMULATE_ID "") +set(CMAKE_C_COMPILER_FRONTEND_VARIANT "") +set(CMAKE_C_SIMULATE_VERSION "") +set(CMAKE_C_COMPILER_ARCHITECTURE_ID TMS320C28x) + +set(MSVC_C_ARCHITECTURE_ID TMS320C28x) + +set(CMAKE_AR "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/ar2000") +set(CMAKE_C_COMPILER_AR "") +set(CMAKE_RANLIB "/usr/bin/ranlib") +set(CMAKE_C_COMPILER_RANLIB "") +set(CMAKE_LINKER "/usr/bin/ld") +set(CMAKE_MT "") +set(CMAKE_COMPILER_IS_GNUCC ) +set(CMAKE_C_COMPILER_LOADED 1) +set(CMAKE_C_COMPILER_WORKS TRUE) +set(CMAKE_C_ABI_COMPILED TRUE) + +set(CMAKE_C_COMPILER_ENV_VAR "CC") + +set(CMAKE_C_COMPILER_ID_RUN 1) +set(CMAKE_C_SOURCE_FILE_EXTENSIONS c;m) +set(CMAKE_C_IGNORE_EXTENSIONS h;H;o;O;obj;OBJ;def;DEF;rc;RC) +set(CMAKE_C_LINKER_PREFERENCE 10) + +# Save compiler ABI information. +set(CMAKE_C_SIZEOF_DATA_PTR "") +set(CMAKE_C_COMPILER_ABI "") +set(CMAKE_C_BYTE_ORDER "") +set(CMAKE_C_LIBRARY_ARCHITECTURE "") + +if(CMAKE_C_SIZEOF_DATA_PTR) + set(CMAKE_SIZEOF_VOID_P "${CMAKE_C_SIZEOF_DATA_PTR}") +endif() + +if(CMAKE_C_COMPILER_ABI) + set(CMAKE_INTERNAL_PLATFORM_ABI "${CMAKE_C_COMPILER_ABI}") +endif() + +if(CMAKE_C_LIBRARY_ARCHITECTURE) + set(CMAKE_LIBRARY_ARCHITECTURE "") +endif() + +set(CMAKE_C_CL_SHOWINCLUDES_PREFIX "") +if(CMAKE_C_CL_SHOWINCLUDES_PREFIX) + set(CMAKE_CL_SHOWINCLUDES_PREFIX "${CMAKE_C_CL_SHOWINCLUDES_PREFIX}") +endif() + + + + + +set(CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES "/usr/include") +set(CMAKE_C_IMPLICIT_LINK_LIBRARIES "") +set(CMAKE_C_IMPLICIT_LINK_DIRECTORIES "") +set(CMAKE_C_IMPLICIT_LINK_FRAMEWORK_DIRECTORIES "") diff --git a/build/CMakeFiles/3.22.1/CMakeCXXCompiler.cmake b/build/CMakeFiles/3.22.1/CMakeCXXCompiler.cmake new file mode 100644 index 0000000..aa0c3b3 --- /dev/null +++ b/build/CMakeFiles/3.22.1/CMakeCXXCompiler.cmake @@ -0,0 +1,83 @@ +set(CMAKE_CXX_COMPILER "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000") +set(CMAKE_CXX_COMPILER_ARG1 "") +set(CMAKE_CXX_COMPILER_ID "TI") +set(CMAKE_CXX_COMPILER_VERSION "22.6.1") +set(CMAKE_CXX_COMPILER_VERSION_INTERNAL "") +set(CMAKE_CXX_COMPILER_WRAPPER "") +set(CMAKE_CXX_STANDARD_COMPUTED_DEFAULT "98") +set(CMAKE_CXX_EXTENSIONS_COMPUTED_DEFAULT "ON") +set(CMAKE_CXX_COMPILE_FEATURES "cxx_std_98") +set(CMAKE_CXX98_COMPILE_FEATURES "cxx_std_98") +set(CMAKE_CXX11_COMPILE_FEATURES "") +set(CMAKE_CXX14_COMPILE_FEATURES "") +set(CMAKE_CXX17_COMPILE_FEATURES "") +set(CMAKE_CXX20_COMPILE_FEATURES "") +set(CMAKE_CXX23_COMPILE_FEATURES "") + +set(CMAKE_CXX_PLATFORM_ID "") +set(CMAKE_CXX_SIMULATE_ID "") +set(CMAKE_CXX_COMPILER_FRONTEND_VARIANT "") +set(CMAKE_CXX_SIMULATE_VERSION "") +set(CMAKE_CXX_COMPILER_ARCHITECTURE_ID TMS320C28x) + +set(MSVC_CXX_ARCHITECTURE_ID TMS320C28x) + +set(CMAKE_AR "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/ar2000") +set(CMAKE_CXX_COMPILER_AR "") +set(CMAKE_RANLIB "/usr/bin/ranlib") +set(CMAKE_CXX_COMPILER_RANLIB "") +set(CMAKE_LINKER "/usr/bin/ld") +set(CMAKE_MT "") +set(CMAKE_COMPILER_IS_GNUCXX ) +set(CMAKE_CXX_COMPILER_LOADED 1) +set(CMAKE_CXX_COMPILER_WORKS TRUE) +set(CMAKE_CXX_ABI_COMPILED TRUE) + +set(CMAKE_CXX_COMPILER_ENV_VAR "CXX") + +set(CMAKE_CXX_COMPILER_ID_RUN 1) +set(CMAKE_CXX_SOURCE_FILE_EXTENSIONS C;M;c++;cc;cpp;cxx;m;mm;mpp;CPP;ixx;cppm) +set(CMAKE_CXX_IGNORE_EXTENSIONS inl;h;hpp;HPP;H;o;O;obj;OBJ;def;DEF;rc;RC) + +foreach (lang C OBJC OBJCXX) + if (CMAKE_${lang}_COMPILER_ID_RUN) + foreach(extension IN LISTS CMAKE_${lang}_SOURCE_FILE_EXTENSIONS) + list(REMOVE_ITEM CMAKE_CXX_SOURCE_FILE_EXTENSIONS ${extension}) + endforeach() + endif() +endforeach() + +set(CMAKE_CXX_LINKER_PREFERENCE 30) +set(CMAKE_CXX_LINKER_PREFERENCE_PROPAGATES 1) + +# Save compiler ABI information. +set(CMAKE_CXX_SIZEOF_DATA_PTR "") +set(CMAKE_CXX_COMPILER_ABI "") +set(CMAKE_CXX_BYTE_ORDER "") +set(CMAKE_CXX_LIBRARY_ARCHITECTURE "") + +if(CMAKE_CXX_SIZEOF_DATA_PTR) + set(CMAKE_SIZEOF_VOID_P "${CMAKE_CXX_SIZEOF_DATA_PTR}") +endif() + +if(CMAKE_CXX_COMPILER_ABI) + set(CMAKE_INTERNAL_PLATFORM_ABI "${CMAKE_CXX_COMPILER_ABI}") +endif() + +if(CMAKE_CXX_LIBRARY_ARCHITECTURE) + set(CMAKE_LIBRARY_ARCHITECTURE "") +endif() + +set(CMAKE_CXX_CL_SHOWINCLUDES_PREFIX "") +if(CMAKE_CXX_CL_SHOWINCLUDES_PREFIX) + set(CMAKE_CL_SHOWINCLUDES_PREFIX "${CMAKE_CXX_CL_SHOWINCLUDES_PREFIX}") +endif() + + + + + +set(CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES "/usr/include") +set(CMAKE_CXX_IMPLICIT_LINK_LIBRARIES "") +set(CMAKE_CXX_IMPLICIT_LINK_DIRECTORIES "") +set(CMAKE_CXX_IMPLICIT_LINK_FRAMEWORK_DIRECTORIES "") diff --git a/build/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_C.bin b/build/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_C.bin new file mode 100644 index 0000000..a250ab5 Binary files /dev/null and b/build/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_C.bin differ diff --git a/build/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_CXX.bin b/build/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_CXX.bin new file mode 100644 index 0000000..1553fc8 Binary files /dev/null and b/build/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_CXX.bin differ diff --git a/build/CMakeFiles/3.22.1/CMakeSystem.cmake b/build/CMakeFiles/3.22.1/CMakeSystem.cmake new file mode 100644 index 0000000..21d50c5 --- /dev/null +++ b/build/CMakeFiles/3.22.1/CMakeSystem.cmake @@ -0,0 +1,15 @@ +set(CMAKE_HOST_SYSTEM "Linux-6.2.0-39-generic") +set(CMAKE_HOST_SYSTEM_NAME "Linux") +set(CMAKE_HOST_SYSTEM_VERSION "6.2.0-39-generic") +set(CMAKE_HOST_SYSTEM_PROCESSOR "x86_64") + + + +set(CMAKE_SYSTEM "Linux-6.2.0-39-generic") +set(CMAKE_SYSTEM_NAME "Linux") +set(CMAKE_SYSTEM_VERSION "6.2.0-39-generic") +set(CMAKE_SYSTEM_PROCESSOR "x86_64") + +set(CMAKE_CROSSCOMPILING "FALSE") + +set(CMAKE_SYSTEM_LOADED 1) diff --git a/build/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.c b/build/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.c new file mode 100644 index 0000000..41b99d7 --- /dev/null +++ b/build/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.c @@ -0,0 +1,803 @@ +#ifdef __cplusplus +# error "A C++ compiler has been selected for C." +#endif + +#if defined(__18CXX) +# define ID_VOID_MAIN +#endif +#if defined(__CLASSIC_C__) +/* cv-qualifiers did not exist in K&R C */ +# define const +# define volatile +#endif + +#if !defined(__has_include) +/* If the compiler does not have __has_include, pretend the answer is + always no. */ +# define __has_include(x) 0 +#endif + + +/* Version number components: V=Version, R=Revision, P=Patch + Version date components: YYYY=Year, MM=Month, DD=Day */ + +#if defined(__INTEL_COMPILER) || defined(__ICC) +# define COMPILER_ID "Intel" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# if defined(__GNUC__) +# define SIMULATE_ID "GNU" +# endif + /* __INTEL_COMPILER = VRP prior to 2021, and then VVVV for 2021 and later, + except that a few beta releases use the old format with V=2021. */ +# if __INTEL_COMPILER < 2021 || __INTEL_COMPILER == 202110 || __INTEL_COMPILER == 202111 +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER/10 % 10) +# if defined(__INTEL_COMPILER_UPDATE) +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER_UPDATE) +# else +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER % 10) +# endif +# else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER_UPDATE) + /* The third version component from --version is an update index, + but no macro is provided for it. */ +# define COMPILER_VERSION_PATCH DEC(0) +# endif +# if defined(__INTEL_COMPILER_BUILD_DATE) + /* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */ +# define COMPILER_VERSION_TWEAK DEC(__INTEL_COMPILER_BUILD_DATE) +# endif +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif (defined(__clang__) && defined(__INTEL_CLANG_COMPILER)) || defined(__INTEL_LLVM_COMPILER) +# define COMPILER_ID "IntelLLVM" +#if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +#endif +#if defined(__GNUC__) +# define SIMULATE_ID "GNU" +#endif +/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and + * later. Look for 6 digit vs. 8 digit version number to decide encoding. + * VVVV is no smaller than the current year when a version is released. + */ +#if __INTEL_LLVM_COMPILER < 1000000L +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 10) +#else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 100) +#endif +#if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +#endif +#if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +#elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +#endif +#if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +#endif +#if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +#endif + +#elif defined(__PATHCC__) +# define COMPILER_ID "PathScale" +# define COMPILER_VERSION_MAJOR DEC(__PATHCC__) +# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__) +# if defined(__PATHCC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__) +# endif + +#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__) +# define COMPILER_ID "Embarcadero" +# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF) +# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF) +# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF) + +#elif defined(__BORLANDC__) +# define COMPILER_ID "Borland" + /* __BORLANDC__ = 0xVRR */ +# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8) +# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF) + +#elif defined(__WATCOMC__) && __WATCOMC__ < 1200 +# define COMPILER_ID "Watcom" + /* __WATCOMC__ = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__WATCOMC__) +# define COMPILER_ID "OpenWatcom" + /* __WATCOMC__ = VVRP + 1100 */ +# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__SUNPRO_C) +# define COMPILER_ID "SunPro" +# if __SUNPRO_C >= 0x5100 + /* __SUNPRO_C = 0xVRRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>12) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF) +# else + /* __SUNPRO_CC = 0xVRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>8) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF) +# endif + +#elif defined(__HP_cc) +# define COMPILER_ID "HP" + /* __HP_cc = VVRRPP */ +# define COMPILER_VERSION_MAJOR DEC(__HP_cc/10000) +# define COMPILER_VERSION_MINOR DEC(__HP_cc/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__HP_cc % 100) + +#elif defined(__DECC) +# define COMPILER_ID "Compaq" + /* __DECC_VER = VVRRTPPPP */ +# define COMPILER_VERSION_MAJOR DEC(__DECC_VER/10000000) +# define COMPILER_VERSION_MINOR DEC(__DECC_VER/100000 % 100) +# define COMPILER_VERSION_PATCH DEC(__DECC_VER % 10000) + +#elif defined(__IBMC__) && defined(__COMPILER_VER__) +# define COMPILER_ID "zOS" + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) + +#elif defined(__ibmxl__) && defined(__clang__) +# define COMPILER_ID "XLClang" +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) + + +#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ >= 800 +# define COMPILER_ID "XL" + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) + +#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ < 800 +# define COMPILER_ID "VisualAge" + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) + +#elif defined(__NVCOMPILER) +# define COMPILER_ID "NVHPC" +# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__) +# if defined(__NVCOMPILER_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__) +# endif + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif defined(_CRAYC) +# define COMPILER_ID "Cray" +# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) +# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) + +#elif defined(__TI_COMPILER_VERSION__) +# define COMPILER_ID "TI" + /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ +# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) +# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) +# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) + +#elif defined(__CLANG_FUJITSU) +# define COMPILER_ID "FujitsuClang" +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(__FUJITSU) +# define COMPILER_ID "Fujitsu" +# if defined(__FCC_version__) +# define COMPILER_VERSION __FCC_version__ +# elif defined(__FCC_major__) +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# endif +# if defined(__fcc_version) +# define COMPILER_VERSION_INTERNAL DEC(__fcc_version) +# elif defined(__FCC_VERSION) +# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION) +# endif + + +#elif defined(__ghs__) +# define COMPILER_ID "GHS" +/* __GHS_VERSION_NUMBER = VVVVRP */ +# ifdef __GHS_VERSION_NUMBER +# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100) +# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10) +# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10) +# endif + +#elif defined(__TINYC__) +# define COMPILER_ID "TinyCC" + +#elif defined(__BCC__) +# define COMPILER_ID "Bruce" + +#elif defined(__SCO_VERSION__) +# define COMPILER_ID "SCO" + +#elif defined(__ARMCC_VERSION) && !defined(__clang__) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(__clang__) && defined(__apple_build_version__) +# define COMPILER_ID "AppleClang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) + +#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION) +# define COMPILER_ID "ARMClang" + # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION % 10000) +# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__GNUC__) +# define COMPILER_ID "GNU" +# define COMPILER_VERSION_MAJOR DEC(__GNUC__) +# if defined(__GNUC_MINOR__) +# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif defined(_MSC_VER) +# define COMPILER_ID "MSVC" + /* _MSC_VER = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) +# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) +# if defined(_MSC_FULL_VER) +# if _MSC_VER >= 1400 + /* _MSC_FULL_VER = VVRRPPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) +# else + /* _MSC_FULL_VER = VVRRPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) +# endif +# endif +# if defined(_MSC_BUILD) +# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) +# endif + +#elif defined(__VISUALDSPVERSION__) || defined(__ADSPBLACKFIN__) || defined(__ADSPTS__) || defined(__ADSP21000__) +# define COMPILER_ID "ADSP" +#if defined(__VISUALDSPVERSION__) + /* __VISUALDSPVERSION__ = 0xVVRRPP00 */ +# define COMPILER_VERSION_MAJOR HEX(__VISUALDSPVERSION__>>24) +# define COMPILER_VERSION_MINOR HEX(__VISUALDSPVERSION__>>16 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__VISUALDSPVERSION__>>8 & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) && defined(__ICCARM__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) +# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) +# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + +#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC) +# define COMPILER_ID "SDCC" +# if defined(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR) +# define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH) +# else + /* SDCC = VRP */ +# define COMPILER_VERSION_MAJOR DEC(SDCC/100) +# define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10) +# define COMPILER_VERSION_PATCH DEC(SDCC % 10) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__MSYS__) +# define PLATFORM_ID "MSYS" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# elif defined(__VXWORKS__) +# define PLATFORM_ID "VxWorks" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#elif defined(__INTEGRITY) +# if defined(INT_178B) +# define PLATFORM_ID "Integrity178" + +# else /* regular Integrity */ +# define PLATFORM_ID "Integrity" +# endif + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_ARM64EC) +# define ARCHITECTURE_ID "ARM64EC" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCRX__) +# define ARCHITECTURE_ID "RX" + +# elif defined(__ICCRH850__) +# define ARCHITECTURE_ID "RH850" + +# elif defined(__ICCRL78__) +# define ARCHITECTURE_ID "RL78" + +# elif defined(__ICCRISCV__) +# define ARCHITECTURE_ID "RISCV" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# elif defined(__ICC430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__ICCV850__) +# define ARCHITECTURE_ID "V850" + +# elif defined(__ICC8051__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__ICCSTM8__) +# define ARCHITECTURE_ID "STM8" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__ghs__) +# if defined(__PPC64__) +# define ARCHITECTURE_ID "PPC64" + +# elif defined(__ppc__) +# define ARCHITECTURE_ID "PPC" + +# elif defined(__ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__x86_64__) +# define ARCHITECTURE_ID "x64" + +# elif defined(__i386__) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__TI_COMPILER_VERSION__) +# if defined(__TI_ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__MSP430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__TMS320C28XX__) +# define ARCHITECTURE_ID "TMS320C28x" + +# elif defined(__TMS320C6X__) || defined(_TMS320C6X) +# define ARCHITECTURE_ID "TMS320C6x" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number. */ +#ifdef COMPILER_VERSION +char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; + +/* Construct a string literal encoding the version number components. */ +#elif defined(COMPILER_VERSION_MAJOR) +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#elif defined(COMPILER_VERSION_INTERNAL_STR) +char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + +#if !defined(__STDC__) && !defined(__clang__) +# if defined(_MSC_VER) || defined(__ibmxl__) || defined(__IBMC__) +# define C_VERSION "90" +# else +# define C_VERSION +# endif +#elif __STDC_VERSION__ > 201710L +# define C_VERSION "23" +#elif __STDC_VERSION__ >= 201710L +# define C_VERSION "17" +#elif __STDC_VERSION__ >= 201000L +# define C_VERSION "11" +#elif __STDC_VERSION__ >= 199901L +# define C_VERSION "99" +#else +# define C_VERSION "90" +#endif +const char* info_language_standard_default = + "INFO" ":" "standard_default[" C_VERSION "]"; + +const char* info_language_extensions_default = "INFO" ":" "extensions_default[" +/* !defined(_MSC_VER) to exclude Clang's MSVC compatibility mode. */ +#if (defined(__clang__) || defined(__GNUC__) || \ + defined(__TI_COMPILER_VERSION__)) && \ + !defined(__STRICT_ANSI__) && !defined(_MSC_VER) + "ON" +#else + "OFF" +#endif +"]"; + +/*--------------------------------------------------------------------------*/ + +#ifdef ID_VOID_MAIN +void main() {} +#else +# if defined(__CLASSIC_C__) +int main(argc, argv) int argc; char *argv[]; +# else +int main(int argc, char* argv[]) +# endif +{ + int require = 0; + require += info_compiler[argc]; + require += info_platform[argc]; + require += info_arch[argc]; +#ifdef COMPILER_VERSION_MAJOR + require += info_version[argc]; +#endif +#ifdef COMPILER_VERSION_INTERNAL + require += info_version_internal[argc]; +#endif +#ifdef SIMULATE_ID + require += info_simulate[argc]; +#endif +#ifdef SIMULATE_VERSION_MAJOR + require += info_simulate_version[argc]; +#endif +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) + require += info_cray[argc]; +#endif + require += info_language_standard_default[argc]; + require += info_language_extensions_default[argc]; + (void)argv; + return require; +} +#endif diff --git a/build/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.obj b/build/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.obj new file mode 100644 index 0000000..1a2b2ae Binary files /dev/null and b/build/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.obj differ diff --git a/build/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.cpp b/build/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.cpp new file mode 100644 index 0000000..25c62a8 --- /dev/null +++ b/build/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.cpp @@ -0,0 +1,791 @@ +/* This source file must have a .cpp extension so that all C++ compilers + recognize the extension without flags. Borland does not know .cxx for + example. */ +#ifndef __cplusplus +# error "A C compiler has been selected for C++." +#endif + +#if !defined(__has_include) +/* If the compiler does not have __has_include, pretend the answer is + always no. */ +# define __has_include(x) 0 +#endif + + +/* Version number components: V=Version, R=Revision, P=Patch + Version date components: YYYY=Year, MM=Month, DD=Day */ + +#if defined(__COMO__) +# define COMPILER_ID "Comeau" + /* __COMO_VERSION__ = VRR */ +# define COMPILER_VERSION_MAJOR DEC(__COMO_VERSION__ / 100) +# define COMPILER_VERSION_MINOR DEC(__COMO_VERSION__ % 100) + +#elif defined(__INTEL_COMPILER) || defined(__ICC) +# define COMPILER_ID "Intel" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# if defined(__GNUC__) +# define SIMULATE_ID "GNU" +# endif + /* __INTEL_COMPILER = VRP prior to 2021, and then VVVV for 2021 and later, + except that a few beta releases use the old format with V=2021. */ +# if __INTEL_COMPILER < 2021 || __INTEL_COMPILER == 202110 || __INTEL_COMPILER == 202111 +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER/10 % 10) +# if defined(__INTEL_COMPILER_UPDATE) +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER_UPDATE) +# else +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER % 10) +# endif +# else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER_UPDATE) + /* The third version component from --version is an update index, + but no macro is provided for it. */ +# define COMPILER_VERSION_PATCH DEC(0) +# endif +# if defined(__INTEL_COMPILER_BUILD_DATE) + /* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */ +# define COMPILER_VERSION_TWEAK DEC(__INTEL_COMPILER_BUILD_DATE) +# endif +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif (defined(__clang__) && defined(__INTEL_CLANG_COMPILER)) || defined(__INTEL_LLVM_COMPILER) +# define COMPILER_ID "IntelLLVM" +#if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +#endif +#if defined(__GNUC__) +# define SIMULATE_ID "GNU" +#endif +/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and + * later. Look for 6 digit vs. 8 digit version number to decide encoding. + * VVVV is no smaller than the current year when a version is released. + */ +#if __INTEL_LLVM_COMPILER < 1000000L +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 10) +#else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 100) +#endif +#if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +#endif +#if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +#elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +#endif +#if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +#endif +#if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +#endif + +#elif defined(__PATHCC__) +# define COMPILER_ID "PathScale" +# define COMPILER_VERSION_MAJOR DEC(__PATHCC__) +# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__) +# if defined(__PATHCC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__) +# endif + +#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__) +# define COMPILER_ID "Embarcadero" +# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF) +# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF) +# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF) + +#elif defined(__BORLANDC__) +# define COMPILER_ID "Borland" + /* __BORLANDC__ = 0xVRR */ +# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8) +# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF) + +#elif defined(__WATCOMC__) && __WATCOMC__ < 1200 +# define COMPILER_ID "Watcom" + /* __WATCOMC__ = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__WATCOMC__) +# define COMPILER_ID "OpenWatcom" + /* __WATCOMC__ = VVRP + 1100 */ +# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__SUNPRO_CC) +# define COMPILER_ID "SunPro" +# if __SUNPRO_CC >= 0x5100 + /* __SUNPRO_CC = 0xVRRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>12) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# else + /* __SUNPRO_CC = 0xVRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>8) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# endif + +#elif defined(__HP_aCC) +# define COMPILER_ID "HP" + /* __HP_aCC = VVRRPP */ +# define COMPILER_VERSION_MAJOR DEC(__HP_aCC/10000) +# define COMPILER_VERSION_MINOR DEC(__HP_aCC/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__HP_aCC % 100) + +#elif defined(__DECCXX) +# define COMPILER_ID "Compaq" + /* __DECCXX_VER = VVRRTPPPP */ +# define COMPILER_VERSION_MAJOR DEC(__DECCXX_VER/10000000) +# define COMPILER_VERSION_MINOR DEC(__DECCXX_VER/100000 % 100) +# define COMPILER_VERSION_PATCH DEC(__DECCXX_VER % 10000) + +#elif defined(__IBMCPP__) && defined(__COMPILER_VER__) +# define COMPILER_ID "zOS" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__ibmxl__) && defined(__clang__) +# define COMPILER_ID "XLClang" +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) + + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ >= 800 +# define COMPILER_ID "XL" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ < 800 +# define COMPILER_ID "VisualAge" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__NVCOMPILER) +# define COMPILER_ID "NVHPC" +# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__) +# if defined(__NVCOMPILER_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__) +# endif + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif defined(_CRAYC) +# define COMPILER_ID "Cray" +# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) +# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) + +#elif defined(__TI_COMPILER_VERSION__) +# define COMPILER_ID "TI" + /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ +# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) +# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) +# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) + +#elif defined(__CLANG_FUJITSU) +# define COMPILER_ID "FujitsuClang" +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(__FUJITSU) +# define COMPILER_ID "Fujitsu" +# if defined(__FCC_version__) +# define COMPILER_VERSION __FCC_version__ +# elif defined(__FCC_major__) +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# endif +# if defined(__fcc_version) +# define COMPILER_VERSION_INTERNAL DEC(__fcc_version) +# elif defined(__FCC_VERSION) +# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION) +# endif + + +#elif defined(__ghs__) +# define COMPILER_ID "GHS" +/* __GHS_VERSION_NUMBER = VVVVRP */ +# ifdef __GHS_VERSION_NUMBER +# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100) +# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10) +# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10) +# endif + +#elif defined(__SCO_VERSION__) +# define COMPILER_ID "SCO" + +#elif defined(__ARMCC_VERSION) && !defined(__clang__) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(__clang__) && defined(__apple_build_version__) +# define COMPILER_ID "AppleClang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) + +#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION) +# define COMPILER_ID "ARMClang" + # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION % 10000) +# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__GNUC__) || defined(__GNUG__) +# define COMPILER_ID "GNU" +# if defined(__GNUC__) +# define COMPILER_VERSION_MAJOR DEC(__GNUC__) +# else +# define COMPILER_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif defined(_MSC_VER) +# define COMPILER_ID "MSVC" + /* _MSC_VER = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) +# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) +# if defined(_MSC_FULL_VER) +# if _MSC_VER >= 1400 + /* _MSC_FULL_VER = VVRRPPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) +# else + /* _MSC_FULL_VER = VVRRPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) +# endif +# endif +# if defined(_MSC_BUILD) +# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) +# endif + +#elif defined(__VISUALDSPVERSION__) || defined(__ADSPBLACKFIN__) || defined(__ADSPTS__) || defined(__ADSP21000__) +# define COMPILER_ID "ADSP" +#if defined(__VISUALDSPVERSION__) + /* __VISUALDSPVERSION__ = 0xVVRRPP00 */ +# define COMPILER_VERSION_MAJOR HEX(__VISUALDSPVERSION__>>24) +# define COMPILER_VERSION_MINOR HEX(__VISUALDSPVERSION__>>16 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__VISUALDSPVERSION__>>8 & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) && defined(__ICCARM__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) +# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) +# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__MSYS__) +# define PLATFORM_ID "MSYS" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# elif defined(__VXWORKS__) +# define PLATFORM_ID "VxWorks" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#elif defined(__INTEGRITY) +# if defined(INT_178B) +# define PLATFORM_ID "Integrity178" + +# else /* regular Integrity */ +# define PLATFORM_ID "Integrity" +# endif + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_ARM64EC) +# define ARCHITECTURE_ID "ARM64EC" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCRX__) +# define ARCHITECTURE_ID "RX" + +# elif defined(__ICCRH850__) +# define ARCHITECTURE_ID "RH850" + +# elif defined(__ICCRL78__) +# define ARCHITECTURE_ID "RL78" + +# elif defined(__ICCRISCV__) +# define ARCHITECTURE_ID "RISCV" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# elif defined(__ICC430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__ICCV850__) +# define ARCHITECTURE_ID "V850" + +# elif defined(__ICC8051__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__ICCSTM8__) +# define ARCHITECTURE_ID "STM8" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__ghs__) +# if defined(__PPC64__) +# define ARCHITECTURE_ID "PPC64" + +# elif defined(__ppc__) +# define ARCHITECTURE_ID "PPC" + +# elif defined(__ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__x86_64__) +# define ARCHITECTURE_ID "x64" + +# elif defined(__i386__) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__TI_COMPILER_VERSION__) +# if defined(__TI_ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__MSP430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__TMS320C28XX__) +# define ARCHITECTURE_ID "TMS320C28x" + +# elif defined(__TMS320C6X__) || defined(_TMS320C6X) +# define ARCHITECTURE_ID "TMS320C6x" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number. */ +#ifdef COMPILER_VERSION +char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; + +/* Construct a string literal encoding the version number components. */ +#elif defined(COMPILER_VERSION_MAJOR) +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#elif defined(COMPILER_VERSION_INTERNAL_STR) +char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + +#if defined(__INTEL_COMPILER) && defined(_MSVC_LANG) && _MSVC_LANG < 201403L +# if defined(__INTEL_CXX11_MODE__) +# if defined(__cpp_aggregate_nsdmi) +# define CXX_STD 201402L +# else +# define CXX_STD 201103L +# endif +# else +# define CXX_STD 199711L +# endif +#elif defined(_MSC_VER) && defined(_MSVC_LANG) +# define CXX_STD _MSVC_LANG +#else +# define CXX_STD __cplusplus +#endif + +const char* info_language_standard_default = "INFO" ":" "standard_default[" +#if CXX_STD > 202002L + "23" +#elif CXX_STD > 201703L + "20" +#elif CXX_STD >= 201703L + "17" +#elif CXX_STD >= 201402L + "14" +#elif CXX_STD >= 201103L + "11" +#else + "98" +#endif +"]"; + +const char* info_language_extensions_default = "INFO" ":" "extensions_default[" +/* !defined(_MSC_VER) to exclude Clang's MSVC compatibility mode. */ +#if (defined(__clang__) || defined(__GNUC__) || \ + defined(__TI_COMPILER_VERSION__)) && \ + !defined(__STRICT_ANSI__) && !defined(_MSC_VER) + "ON" +#else + "OFF" +#endif +"]"; + +/*--------------------------------------------------------------------------*/ + +int main(int argc, char* argv[]) +{ + int require = 0; + require += info_compiler[argc]; + require += info_platform[argc]; +#ifdef COMPILER_VERSION_MAJOR + require += info_version[argc]; +#endif +#ifdef COMPILER_VERSION_INTERNAL + require += info_version_internal[argc]; +#endif +#ifdef SIMULATE_ID + require += info_simulate[argc]; +#endif +#ifdef SIMULATE_VERSION_MAJOR + require += info_simulate_version[argc]; +#endif +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) + require += info_cray[argc]; +#endif + require += info_language_standard_default[argc]; + require += info_language_extensions_default[argc]; + (void)argv; + return require; +} diff --git a/build/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.obj b/build/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.obj new file mode 100644 index 0000000..31350a1 Binary files /dev/null and b/build/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.obj differ diff --git a/build/CMakeFiles/CMakeDirectoryInformation.cmake b/build/CMakeFiles/CMakeDirectoryInformation.cmake new file mode 100644 index 0000000..a30ee50 --- /dev/null +++ b/build/CMakeFiles/CMakeDirectoryInformation.cmake @@ -0,0 +1,16 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# Relative path conversion top directories. +set(CMAKE_RELATIVE_PATH_TOP_SOURCE "/home/lobov/workspace/ccs12.5/cmake_test") +set(CMAKE_RELATIVE_PATH_TOP_BINARY "/home/lobov/workspace/ccs12.5/cmake_test/build") + +# Force unix paths in dependencies. +set(CMAKE_FORCE_UNIX_PATHS 1) + + +# The C and CXX include file regular expressions for this directory. +set(CMAKE_C_INCLUDE_REGEX_SCAN "^.*$") +set(CMAKE_C_INCLUDE_REGEX_COMPLAIN "^$") +set(CMAKE_CXX_INCLUDE_REGEX_SCAN ${CMAKE_C_INCLUDE_REGEX_SCAN}) +set(CMAKE_CXX_INCLUDE_REGEX_COMPLAIN ${CMAKE_C_INCLUDE_REGEX_COMPLAIN}) diff --git a/build/CMakeFiles/CMakeOutput.log b/build/CMakeFiles/CMakeOutput.log new file mode 100644 index 0000000..2989da5 --- /dev/null +++ b/build/CMakeFiles/CMakeOutput.log @@ -0,0 +1,125 @@ +The system is: Linux - 6.2.0-39-generic - x86_64 +Compiling the C compiler identification source file "CMakeCCompilerId.c" succeeded. +Compiler: /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 +Build flags: +Id flags: + +The output was: +0 + + +Compilation of the C compiler identification source "CMakeCCompilerId.c" produced "CMakeCCompilerId.obj" + +The C compiler identification is TI, found in "/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.obj" + +Compiling the CXX compiler identification source file "CMakeCXXCompilerId.cpp" succeeded. +Compiler: /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 +Build flags: +Id flags: + +The output was: +0 + + +Compilation of the CXX compiler identification source "CMakeCXXCompilerId.cpp" produced "CMakeCXXCompilerId.obj" + +The CXX compiler identification is TI, found in "/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.obj" + +Detecting C compiler ABI info compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_f783a/fast && /usr/bin/gmake -f CMakeFiles/cmTC_f783a.dir/build.make CMakeFiles/cmTC_f783a.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' +Building C object CMakeFiles/cmTC_f783a.dir/CMakeCCompilerABI.c.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/usr/share/cmake-3.22/Modules/CMakeCCompilerABI.c --output_file=CMakeFiles/cmTC_f783a.dir/CMakeCCompilerABI.c.o +Linking C executable cmTC_f783a +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_f783a.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_f783a --map_file=cmTC_f783a.map CMakeFiles/cmTC_f783a.dir/CMakeCCompilerABI.c.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' + + + + + +Detecting C [--c11;--strict_ansi] compiler features compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_0302d/fast && /usr/bin/gmake -f CMakeFiles/cmTC_0302d.dir/build.make CMakeFiles/cmTC_0302d.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' +Building C object CMakeFiles/cmTC_0302d.dir/feature_tests.c.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/feature_tests.c --c11 --strict_ansi --output_file=CMakeFiles/cmTC_0302d.dir/feature_tests.c.o +Linking C executable cmTC_0302d +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_0302d.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_0302d --map_file=cmTC_0302d.map CMakeFiles/cmTC_0302d.dir/feature_tests.c.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' + + + + + +Detecting C [--c99;--strict_ansi] compiler features compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_c170b/fast && /usr/bin/gmake -f CMakeFiles/cmTC_c170b.dir/build.make CMakeFiles/cmTC_c170b.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' +Building C object CMakeFiles/cmTC_c170b.dir/feature_tests.c.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/feature_tests.c --c99 --strict_ansi --output_file=CMakeFiles/cmTC_c170b.dir/feature_tests.c.o +Linking C executable cmTC_c170b +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_c170b.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_c170b --map_file=cmTC_c170b.map CMakeFiles/cmTC_c170b.dir/feature_tests.c.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' + + + + + +Detecting C [--c89;--strict_ansi] compiler features compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_3ab19/fast && /usr/bin/gmake -f CMakeFiles/cmTC_3ab19.dir/build.make CMakeFiles/cmTC_3ab19.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' +Building C object CMakeFiles/cmTC_3ab19.dir/feature_tests.c.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/feature_tests.c --c89 --strict_ansi --output_file=CMakeFiles/cmTC_3ab19.dir/feature_tests.c.o +Linking C executable cmTC_3ab19 +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_3ab19.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_3ab19 --map_file=cmTC_3ab19.map CMakeFiles/cmTC_3ab19.dir/feature_tests.c.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' + + + +Detecting CXX compiler ABI info compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_7c04d/fast && /usr/bin/gmake -f CMakeFiles/cmTC_7c04d.dir/build.make CMakeFiles/cmTC_7c04d.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' +Building CXX object CMakeFiles/cmTC_7c04d.dir/CMakeCXXCompilerABI.cpp.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --cpp_file=/usr/share/cmake-3.22/Modules/CMakeCXXCompilerABI.cpp --output_file=CMakeFiles/cmTC_7c04d.dir/CMakeCXXCompilerABI.cpp.o +Linking CXX executable cmTC_7c04d +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_7c04d.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_7c04d --map_file=cmTC_7c04d.map CMakeFiles/cmTC_7c04d.dir/CMakeCXXCompilerABI.cpp.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' + + + + + +Detecting CXX [--c++03;--strict_ansi] compiler features compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_cb3f4/fast && /usr/bin/gmake -f CMakeFiles/cmTC_cb3f4.dir/build.make CMakeFiles/cmTC_cb3f4.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' +Building CXX object CMakeFiles/cmTC_cb3f4.dir/feature_tests.cxx.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/feature_tests.cxx --c++03 --strict_ansi --output_file=CMakeFiles/cmTC_cb3f4.dir/feature_tests.cxx.o +Linking CXX executable cmTC_cb3f4 +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_cb3f4.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_cb3f4 --map_file=cmTC_cb3f4.map CMakeFiles/cmTC_cb3f4.dir/feature_tests.cxx.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/CMakeTmp' + + + diff --git a/build/CMakeFiles/Makefile.cmake b/build/CMakeFiles/Makefile.cmake new file mode 100644 index 0000000..aefb1d1 --- /dev/null +++ b/build/CMakeFiles/Makefile.cmake @@ -0,0 +1,44 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# The generator used is: +set(CMAKE_DEPENDS_GENERATOR "Unix Makefiles") + +# The top level Makefile was generated from the following files: +set(CMAKE_MAKEFILE_DEPENDS + "CMakeCache.txt" + "../CMakeLists.txt" + "CMakeFiles/3.22.1/CMakeCCompiler.cmake" + "CMakeFiles/3.22.1/CMakeCXXCompiler.cmake" + "CMakeFiles/3.22.1/CMakeSystem.cmake" + "/usr/share/cmake-3.22/Modules/CMakeCInformation.cmake" + "/usr/share/cmake-3.22/Modules/CMakeCXXInformation.cmake" + "/usr/share/cmake-3.22/Modules/CMakeCommonLanguageInclude.cmake" + "/usr/share/cmake-3.22/Modules/CMakeGenericSystem.cmake" + "/usr/share/cmake-3.22/Modules/CMakeInitializeConfigs.cmake" + "/usr/share/cmake-3.22/Modules/CMakeLanguageInformation.cmake" + "/usr/share/cmake-3.22/Modules/CMakeSystemSpecificInformation.cmake" + "/usr/share/cmake-3.22/Modules/CMakeSystemSpecificInitialize.cmake" + "/usr/share/cmake-3.22/Modules/Compiler/CMakeCommonCompilerMacros.cmake" + "/usr/share/cmake-3.22/Modules/Compiler/TI-C.cmake" + "/usr/share/cmake-3.22/Modules/Compiler/TI-CXX.cmake" + "/usr/share/cmake-3.22/Modules/Compiler/TI.cmake" + "/usr/share/cmake-3.22/Modules/Platform/Linux.cmake" + "/usr/share/cmake-3.22/Modules/Platform/UnixPaths.cmake" + ) + +# The corresponding makefile is: +set(CMAKE_MAKEFILE_OUTPUTS + "Makefile" + "CMakeFiles/cmake.check_cache" + ) + +# Byproducts of CMake generate step: +set(CMAKE_MAKEFILE_PRODUCTS + "CMakeFiles/CMakeDirectoryInformation.cmake" + ) + +# Dependency information for all targets: +set(CMAKE_DEPEND_INFO_FILES + "CMakeFiles/test_project.dir/DependInfo.cmake" + ) diff --git a/build/CMakeFiles/Makefile2 b/build/CMakeFiles/Makefile2 new file mode 100644 index 0000000..a7efa9d --- /dev/null +++ b/build/CMakeFiles/Makefile2 @@ -0,0 +1,112 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# Default target executed when no arguments are given to make. +default_target: all +.PHONY : default_target + +#============================================================================= +# Special targets provided by cmake. + +# Disable implicit rules so canonical targets will work. +.SUFFIXES: + +# Disable VCS-based implicit rules. +% : %,v + +# Disable VCS-based implicit rules. +% : RCS/% + +# Disable VCS-based implicit rules. +% : RCS/%,v + +# Disable VCS-based implicit rules. +% : SCCS/s.% + +# Disable VCS-based implicit rules. +% : s.% + +.SUFFIXES: .hpux_make_needs_suffix_list + +# Command-line flag to silence nested $(MAKE). +$(VERBOSE)MAKESILENT = -s + +#Suppress display of executed commands. +$(VERBOSE).SILENT: + +# A target that is always out of date. +cmake_force: +.PHONY : cmake_force + +#============================================================================= +# Set environment variables for the build. + +# The shell in which to execute make rules. +SHELL = /bin/sh + +# The CMake executable. +CMAKE_COMMAND = /usr/bin/cmake + +# The command to remove a file. +RM = /usr/bin/cmake -E rm -f + +# Escaping for special characters. +EQUALS = = + +# The top-level source directory on which CMake was run. +CMAKE_SOURCE_DIR = /home/lobov/workspace/ccs12.5/cmake_test + +# The top-level build directory on which CMake was run. +CMAKE_BINARY_DIR = /home/lobov/workspace/ccs12.5/cmake_test/build + +#============================================================================= +# Directory level rules for the build root directory + +# The main recursive "all" target. +all: CMakeFiles/test_project.dir/all +.PHONY : all + +# The main recursive "preinstall" target. +preinstall: +.PHONY : preinstall + +# The main recursive "clean" target. +clean: CMakeFiles/test_project.dir/clean +.PHONY : clean + +#============================================================================= +# Target rules for target CMakeFiles/test_project.dir + +# All Build rule for target. +CMakeFiles/test_project.dir/all: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/depend + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/build + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles --progress-num=1,2,3,4,5,6,7 "Built target test_project" +.PHONY : CMakeFiles/test_project.dir/all + +# Build rule for subdir invocation for target. +CMakeFiles/test_project.dir/rule: cmake_check_build_system + $(CMAKE_COMMAND) -E cmake_progress_start /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles 7 + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 CMakeFiles/test_project.dir/all + $(CMAKE_COMMAND) -E cmake_progress_start /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles 0 +.PHONY : CMakeFiles/test_project.dir/rule + +# Convenience name for target. +test_project: CMakeFiles/test_project.dir/rule +.PHONY : test_project + +# clean rule for target. +CMakeFiles/test_project.dir/clean: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/clean +.PHONY : CMakeFiles/test_project.dir/clean + +#============================================================================= +# Special targets to cleanup operation of make. + +# Special rule to run CMake to check the build system integrity. +# No rule that depends on this can have commands that come from listfiles +# because they might be regenerated. +cmake_check_build_system: + $(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 0 +.PHONY : cmake_check_build_system + diff --git a/build/CMakeFiles/ShowIncludes/foo.h b/build/CMakeFiles/ShowIncludes/foo.h new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/build/CMakeFiles/ShowIncludes/foo.h @@ -0,0 +1 @@ + diff --git a/build/CMakeFiles/ShowIncludes/main.c b/build/CMakeFiles/ShowIncludes/main.c new file mode 100644 index 0000000..cd3cbc1 --- /dev/null +++ b/build/CMakeFiles/ShowIncludes/main.c @@ -0,0 +1,2 @@ +#include "foo.h" +int main(){} diff --git a/build/CMakeFiles/TargetDirectories.txt b/build/CMakeFiles/TargetDirectories.txt new file mode 100644 index 0000000..8b298ec --- /dev/null +++ b/build/CMakeFiles/TargetDirectories.txt @@ -0,0 +1,3 @@ +/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/test_project.dir +/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/edit_cache.dir +/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/rebuild_cache.dir diff --git a/build/CMakeFiles/cmake.check_cache b/build/CMakeFiles/cmake.check_cache new file mode 100644 index 0000000..3dccd73 --- /dev/null +++ b/build/CMakeFiles/cmake.check_cache @@ -0,0 +1 @@ +# This file is generated by cmake for dependency checking of the CMakeCache.txt file diff --git a/build/CMakeFiles/feature_tests.bin b/build/CMakeFiles/feature_tests.bin new file mode 100644 index 0000000..e3d1a31 Binary files /dev/null and b/build/CMakeFiles/feature_tests.bin differ diff --git a/build/CMakeFiles/feature_tests.c b/build/CMakeFiles/feature_tests.c new file mode 100644 index 0000000..29f0da9 --- /dev/null +++ b/build/CMakeFiles/feature_tests.c @@ -0,0 +1,6 @@ + + const char features[] = {"\n" + +}; + +int main(int argc, char** argv) { (void)argv; return features[argc]; } diff --git a/build/CMakeFiles/feature_tests.cxx b/build/CMakeFiles/feature_tests.cxx new file mode 100644 index 0000000..29f0da9 --- /dev/null +++ b/build/CMakeFiles/feature_tests.cxx @@ -0,0 +1,6 @@ + + const char features[] = {"\n" + +}; + +int main(int argc, char** argv) { (void)argv; return features[argc]; } diff --git a/build/CMakeFiles/progress.marks b/build/CMakeFiles/progress.marks new file mode 100644 index 0000000..7f8f011 --- /dev/null +++ b/build/CMakeFiles/progress.marks @@ -0,0 +1 @@ +7 diff --git a/build/CMakeFiles/test_project.dir/DependInfo.cmake b/build/CMakeFiles/test_project.dir/DependInfo.cmake new file mode 100644 index 0000000..5483408 --- /dev/null +++ b/build/CMakeFiles/test_project.dir/DependInfo.cmake @@ -0,0 +1,49 @@ + +# Consider dependencies only in project. +set(CMAKE_DEPENDS_IN_PROJECT_ONLY OFF) + +# The set of languages for which implicit dependencies are needed: +set(CMAKE_DEPENDS_LANGUAGES + "C" + "CXX" + ) +# The set of files for implicit dependencies of each language: +set(CMAKE_DEPENDS_CHECK_C + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o" + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o" + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o" + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o" + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o" + ) +set(CMAKE_C_COMPILER_ID "TI") + +# The include file search paths: +set(CMAKE_C_TARGET_INCLUDE_PATH + "." + ".././f2833x" + ".././f2833x/common/include" + ".././f2833x/headers/include" + ) +set(CMAKE_DEPENDS_CHECK_CXX + "/home/lobov/workspace/ccs12.5/cmake_test/main.cpp" "/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/test_project.dir/main.cpp.o" + ) +set(CMAKE_CXX_COMPILER_ID "TI") + +# The include file search paths: +set(CMAKE_CXX_TARGET_INCLUDE_PATH + "." + ".././f2833x" + ".././f2833x/common/include" + ".././f2833x/headers/include" + ) + +# The set of dependency files which are needed: +set(CMAKE_DEPENDS_DEPENDENCY_FILES + ) + +# Targets to which this target links. +set(CMAKE_TARGET_LINKED_INFO_FILES + ) + +# Fortran module output directory. +set(CMAKE_Fortran_TARGET_MODULE_DIR "") diff --git a/build/CMakeFiles/test_project.dir/build.make b/build/CMakeFiles/test_project.dir/build.make new file mode 100644 index 0000000..345009a --- /dev/null +++ b/build/CMakeFiles/test_project.dir/build.make @@ -0,0 +1,184 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# Delete rule output on recipe failure. +.DELETE_ON_ERROR: + +#============================================================================= +# Special targets provided by cmake. + +# Disable implicit rules so canonical targets will work. +.SUFFIXES: + +# Disable VCS-based implicit rules. +% : %,v + +# Disable VCS-based implicit rules. +% : RCS/% + +# Disable VCS-based implicit rules. +% : RCS/%,v + +# Disable VCS-based implicit rules. +% : SCCS/s.% + +# Disable VCS-based implicit rules. +% : s.% + +.SUFFIXES: .hpux_make_needs_suffix_list + +# Command-line flag to silence nested $(MAKE). +$(VERBOSE)MAKESILENT = -s + +#Suppress display of executed commands. +$(VERBOSE).SILENT: + +# A target that is always out of date. +cmake_force: +.PHONY : cmake_force + +#============================================================================= +# Set environment variables for the build. + +# The shell in which to execute make rules. +SHELL = /bin/sh + +# The CMake executable. +CMAKE_COMMAND = /usr/bin/cmake + +# The command to remove a file. +RM = /usr/bin/cmake -E rm -f + +# Escaping for special characters. +EQUALS = = + +# The top-level source directory on which CMake was run. +CMAKE_SOURCE_DIR = /home/lobov/workspace/ccs12.5/cmake_test + +# The top-level build directory on which CMake was run. +CMAKE_BINARY_DIR = /home/lobov/workspace/ccs12.5/cmake_test/build + +# Include any dependencies generated for this target. +include CMakeFiles/test_project.dir/depend.make +# Include any dependencies generated by the compiler for this target. +include CMakeFiles/test_project.dir/compiler_depend.make + +# Include the progress variables for this target. +include CMakeFiles/test_project.dir/progress.make + +# Include the compile flags for this target's objects. +include CMakeFiles/test_project.dir/flags.make + +CMakeFiles/test_project.dir/main.cpp.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/main.cpp.o: ../main.cpp + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles --progress-num=$(CMAKE_PROGRESS_1) "Building CXX object CMakeFiles/test_project.dir/main.cpp.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/main.cpp $(CXX_DEFINES) $(CXX_INCLUDES) $(CXX_FLAGS) --output_file=CMakeFiles/test_project.dir/main.cpp.o + +CMakeFiles/test_project.dir/main.cpp.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing CXX source to CMakeFiles/test_project.dir/main.cpp.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/main.cpp $(CXX_DEFINES) $(CXX_INCLUDES) $(CXX_FLAGS) --output_file=CMakeFiles/test_project.dir/main.cpp.i + +CMakeFiles/test_project.dir/main.cpp.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling CXX source to assembly CMakeFiles/test_project.dir/main.cpp.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/main.cpp $(CXX_DEFINES) $(CXX_INCLUDES) $(CXX_FLAGS) --output_file=CMakeFiles/test_project.dir/main.cpp.s + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o: ../f2833x/common/source/DSP2833x_DefaultIsr.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles --progress-num=$(CMAKE_PROGRESS_2) "Building C object CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.i + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.s + +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o: ../f2833x/headers/source/DSP2833x_GlobalVariableDefs.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles --progress-num=$(CMAKE_PROGRESS_3) "Building C object CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o + +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i + +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o: ../f2833x/common/source/DSP2833x_PieCtrl.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles --progress-num=$(CMAKE_PROGRESS_4) "Building C object CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.i + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.s + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o: ../f2833x/common/source/DSP2833x_PieVect.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles --progress-num=$(CMAKE_PROGRESS_5) "Building C object CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.i + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.s + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o: ../f2833x/common/source/DSP2833x_SysCtrl.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles --progress-num=$(CMAKE_PROGRESS_6) "Building C object CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.i + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.s + +# Object files for target test_project +test_project_OBJECTS = \ +"CMakeFiles/test_project.dir/main.cpp.o" \ +"CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o" \ +"CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o" \ +"CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o" \ +"CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o" \ +"CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o" + +# External object files for target test_project +test_project_EXTERNAL_OBJECTS = + +test_project: CMakeFiles/test_project.dir/main.cpp.o +test_project: CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o +test_project: CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o +test_project: CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o +test_project: CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o +test_project: CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o +test_project: CMakeFiles/test_project.dir/build.make +test_project: CMakeFiles/test_project.dir/link.txt + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --bold --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles --progress-num=$(CMAKE_PROGRESS_7) "Linking CXX executable test_project" + $(CMAKE_COMMAND) -E cmake_link_script CMakeFiles/test_project.dir/link.txt --verbose=$(VERBOSE) + +# Rule to build all files generated by this target. +CMakeFiles/test_project.dir/build: test_project +.PHONY : CMakeFiles/test_project.dir/build + +CMakeFiles/test_project.dir/clean: + $(CMAKE_COMMAND) -P CMakeFiles/test_project.dir/cmake_clean.cmake +.PHONY : CMakeFiles/test_project.dir/clean + +CMakeFiles/test_project.dir/depend: + cd /home/lobov/workspace/ccs12.5/cmake_test/build && $(CMAKE_COMMAND) -E cmake_depends "Unix Makefiles" /home/lobov/workspace/ccs12.5/cmake_test /home/lobov/workspace/ccs12.5/cmake_test /home/lobov/workspace/ccs12.5/cmake_test/build /home/lobov/workspace/ccs12.5/cmake_test/build /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles/test_project.dir/DependInfo.cmake --color=$(COLOR) +.PHONY : CMakeFiles/test_project.dir/depend + diff --git a/build/CMakeFiles/test_project.dir/cmake_clean.cmake b/build/CMakeFiles/test_project.dir/cmake_clean.cmake new file mode 100644 index 0000000..f70d891 --- /dev/null +++ b/build/CMakeFiles/test_project.dir/cmake_clean.cmake @@ -0,0 +1,15 @@ +file(REMOVE_RECURSE + "CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o" + "CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o" + "CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o" + "CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o" + "CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o" + "CMakeFiles/test_project.dir/main.cpp.o" + "test_project" + "test_project.pdb" +) + +# Per-language clean rules from dependency scanning. +foreach(lang C CXX) + include(CMakeFiles/test_project.dir/cmake_clean_${lang}.cmake OPTIONAL) +endforeach() diff --git a/build/CMakeFiles/test_project.dir/compiler_depend.make b/build/CMakeFiles/test_project.dir/compiler_depend.make new file mode 100644 index 0000000..bbcff8b --- /dev/null +++ b/build/CMakeFiles/test_project.dir/compiler_depend.make @@ -0,0 +1,2 @@ +# Empty compiler generated dependencies file for test_project. +# This may be replaced when dependencies are built. diff --git a/build/CMakeFiles/test_project.dir/compiler_depend.ts b/build/CMakeFiles/test_project.dir/compiler_depend.ts new file mode 100644 index 0000000..0e5a7fe --- /dev/null +++ b/build/CMakeFiles/test_project.dir/compiler_depend.ts @@ -0,0 +1,2 @@ +# CMAKE generated file: DO NOT EDIT! +# Timestamp file for compiler generated dependencies management for test_project. diff --git a/build/CMakeFiles/test_project.dir/depend.make b/build/CMakeFiles/test_project.dir/depend.make new file mode 100644 index 0000000..6afafca --- /dev/null +++ b/build/CMakeFiles/test_project.dir/depend.make @@ -0,0 +1,2 @@ +# Empty dependencies file for test_project. +# This may be replaced when dependencies are built. diff --git a/build/CMakeFiles/test_project.dir/flags.make b/build/CMakeFiles/test_project.dir/flags.make new file mode 100644 index 0000000..a8b2b22 --- /dev/null +++ b/build/CMakeFiles/test_project.dir/flags.make @@ -0,0 +1,17 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# compile C with /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 +# compile CXX with /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 +C_DEFINES = + +C_INCLUDES = --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include + +C_FLAGS = -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE "--define=bmin='0.397824735f'" "--define=amax='0.960433870f'" --float_operations_allowed=32 --printf_support=minimal --include_path=\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\" --include_path=\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\" + +CXX_DEFINES = + +CXX_INCLUDES = --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include + +CXX_FLAGS = -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE "--define=bmin='0.397824735f'" "--define=amax='0.960433870f'" --float_operations_allowed=32 --printf_support=minimal --include_path=\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\" --include_path=\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\" + diff --git a/build/CMakeFiles/test_project.dir/link.txt b/build/CMakeFiles/test_project.dir/link.txt new file mode 100644 index 0000000..b01a999 --- /dev/null +++ b/build/CMakeFiles/test_project.dir/link.txt @@ -0,0 +1 @@ +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=test_project --map_file=test_project.map CMakeFiles/test_project.dir/main.cpp.o CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o diff --git a/build/CMakeFiles/test_project.dir/progress.make b/build/CMakeFiles/test_project.dir/progress.make new file mode 100644 index 0000000..2f82315 --- /dev/null +++ b/build/CMakeFiles/test_project.dir/progress.make @@ -0,0 +1,8 @@ +CMAKE_PROGRESS_1 = 1 +CMAKE_PROGRESS_2 = 2 +CMAKE_PROGRESS_3 = 3 +CMAKE_PROGRESS_4 = 4 +CMAKE_PROGRESS_5 = 5 +CMAKE_PROGRESS_6 = 6 +CMAKE_PROGRESS_7 = 7 + diff --git a/build/Debug/CMakeCache.txt b/build/Debug/CMakeCache.txt new file mode 100644 index 0000000..4886eda --- /dev/null +++ b/build/Debug/CMakeCache.txt @@ -0,0 +1,332 @@ +# This is the CMakeCache file. +# For build in directory: /home/lobov/workspace/ccs12.5/cmake_test/build/Debug +# It was generated by CMake: /usr/bin/cmake +# You can edit this file to change values found and used by cmake. +# If you do not want to change any of the values, simply exit the editor. +# If you do want to change a value, simply edit, save, and exit the editor. +# The syntax for the file is as follows: +# KEY:TYPE=VALUE +# KEY is the name of a variable in the cache. +# TYPE is a hint to GUIs for the type of VALUE, DO NOT EDIT TYPE!. +# VALUE is the current value for the KEY. + +######################## +# EXTERNAL cache entries +######################## + +//Path to a program. +CMAKE_ADDR2LINE:FILEPATH=/usr/bin/addr2line + +//Path to a program. +CMAKE_AR:FILEPATH=/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/ar2000 + +//No help, variable specified on the command line. +CMAKE_BUILD_TYPE:STRING=Debug + +//Enable/Disable color output during build. +CMAKE_COLOR_MAKEFILE:BOOL=ON + +//Flags used by the CXX compiler during all build types. +CMAKE_CXX_FLAGS:STRING= + +//Flags used by the CXX compiler during DEBUG builds. +CMAKE_CXX_FLAGS_DEBUG:STRING= + +//Flags used by the CXX compiler during MINSIZEREL builds. +CMAKE_CXX_FLAGS_MINSIZEREL:STRING= + +//Flags used by the CXX compiler during RELEASE builds. +CMAKE_CXX_FLAGS_RELEASE:STRING= + +//Flags used by the CXX compiler during RELWITHDEBINFO builds. +CMAKE_CXX_FLAGS_RELWITHDEBINFO:STRING= + +//Flags used by the C compiler during all build types. +CMAKE_C_FLAGS:STRING= + +//Flags used by the C compiler during DEBUG builds. +CMAKE_C_FLAGS_DEBUG:STRING= + +//Flags used by the C compiler during MINSIZEREL builds. +CMAKE_C_FLAGS_MINSIZEREL:STRING= + +//Flags used by the C compiler during RELEASE builds. +CMAKE_C_FLAGS_RELEASE:STRING= + +//Flags used by the C compiler during RELWITHDEBINFO builds. +CMAKE_C_FLAGS_RELWITHDEBINFO:STRING= + +//Path to a program. +CMAKE_DLLTOOL:FILEPATH=CMAKE_DLLTOOL-NOTFOUND + +//Flags used by the linker during all build types. +CMAKE_EXE_LINKER_FLAGS:STRING= + +//Flags used by the linker during DEBUG builds. +CMAKE_EXE_LINKER_FLAGS_DEBUG:STRING= + +//Flags used by the linker during MINSIZEREL builds. +CMAKE_EXE_LINKER_FLAGS_MINSIZEREL:STRING= + +//Flags used by the linker during RELEASE builds. +CMAKE_EXE_LINKER_FLAGS_RELEASE:STRING= + +//Flags used by the linker during RELWITHDEBINFO builds. +CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO:STRING= + +//No help, variable specified on the command line. +CMAKE_EXPORT_COMPILE_COMMANDS:BOOL=ON + +//Install path prefix, prepended onto install directories. +CMAKE_INSTALL_PREFIX:PATH=/usr/local + +//Path to a program. +CMAKE_LINKER:FILEPATH=/usr/bin/ld + +//Path to a program. +CMAKE_MAKE_PROGRAM:FILEPATH=/usr/bin/gmake + +//Flags used by the linker during the creation of modules during +// all build types. +CMAKE_MODULE_LINKER_FLAGS:STRING= + +//Flags used by the linker during the creation of modules during +// DEBUG builds. +CMAKE_MODULE_LINKER_FLAGS_DEBUG:STRING= + +//Flags used by the linker during the creation of modules during +// MINSIZEREL builds. +CMAKE_MODULE_LINKER_FLAGS_MINSIZEREL:STRING= + +//Flags used by the linker during the creation of modules during +// RELEASE builds. +CMAKE_MODULE_LINKER_FLAGS_RELEASE:STRING= + +//Flags used by the linker during the creation of modules during +// RELWITHDEBINFO builds. +CMAKE_MODULE_LINKER_FLAGS_RELWITHDEBINFO:STRING= + +//Path to a program. +CMAKE_NM:FILEPATH=/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/nm2000 + +//Path to a program. +CMAKE_OBJCOPY:FILEPATH=/usr/bin/objcopy + +//Path to a program. +CMAKE_OBJDUMP:FILEPATH=/usr/bin/objdump + +//Value Computed by CMake +CMAKE_PROJECT_DESCRIPTION:STATIC= + +//Value Computed by CMake +CMAKE_PROJECT_HOMEPAGE_URL:STATIC= + +//Value Computed by CMake +CMAKE_PROJECT_NAME:STATIC=cmake_test + +//Path to a program. +CMAKE_RANLIB:FILEPATH=/usr/bin/ranlib + +//Path to a program. +CMAKE_READELF:FILEPATH=/usr/bin/readelf + +//Flags used by the linker during the creation of shared libraries +// during all build types. +CMAKE_SHARED_LINKER_FLAGS:STRING= + +//Flags used by the linker during the creation of shared libraries +// during DEBUG builds. +CMAKE_SHARED_LINKER_FLAGS_DEBUG:STRING= + +//Flags used by the linker during the creation of shared libraries +// during MINSIZEREL builds. +CMAKE_SHARED_LINKER_FLAGS_MINSIZEREL:STRING= + +//Flags used by the linker during the creation of shared libraries +// during RELEASE builds. +CMAKE_SHARED_LINKER_FLAGS_RELEASE:STRING= + +//Flags used by the linker during the creation of shared libraries +// during RELWITHDEBINFO builds. +CMAKE_SHARED_LINKER_FLAGS_RELWITHDEBINFO:STRING= + +//If set, runtime paths are not added when installing shared libraries, +// but are added when building. +CMAKE_SKIP_INSTALL_RPATH:BOOL=NO + +//If set, runtime paths are not added when using shared libraries. +CMAKE_SKIP_RPATH:BOOL=NO + +//Flags used by the linker during the creation of static libraries +// during all build types. +CMAKE_STATIC_LINKER_FLAGS:STRING= + +//Flags used by the linker during the creation of static libraries +// during DEBUG builds. +CMAKE_STATIC_LINKER_FLAGS_DEBUG:STRING= + +//Flags used by the linker during the creation of static libraries +// during MINSIZEREL builds. +CMAKE_STATIC_LINKER_FLAGS_MINSIZEREL:STRING= + +//Flags used by the linker during the creation of static libraries +// during RELEASE builds. +CMAKE_STATIC_LINKER_FLAGS_RELEASE:STRING= + +//Flags used by the linker during the creation of static libraries +// during RELWITHDEBINFO builds. +CMAKE_STATIC_LINKER_FLAGS_RELWITHDEBINFO:STRING= + +//Path to a program. +CMAKE_STRIP:FILEPATH=/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/strip2000 + +//If this value is on, makefiles will be generated without the +// .SILENT directive, and all commands will be echoed to the console +// during the make. This is useful for debugging only. With Visual +// Studio IDE projects all commands are done without /nologo. +CMAKE_VERBOSE_MAKEFILE:BOOL=FALSE + +//Value Computed by CMake +cmake_test_BINARY_DIR:STATIC=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug + +//Value Computed by CMake +cmake_test_IS_TOP_LEVEL:STATIC=ON + +//Value Computed by CMake +cmake_test_SOURCE_DIR:STATIC=/home/lobov/workspace/ccs12.5/cmake_test + + +######################## +# INTERNAL cache entries +######################## + +//ADVANCED property for variable: CMAKE_ADDR2LINE +CMAKE_ADDR2LINE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_AR +CMAKE_AR-ADVANCED:INTERNAL=1 +//This is the directory where this CMakeCache.txt was created +CMAKE_CACHEFILE_DIR:INTERNAL=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug +//Major version of cmake used to create the current loaded cache +CMAKE_CACHE_MAJOR_VERSION:INTERNAL=3 +//Minor version of cmake used to create the current loaded cache +CMAKE_CACHE_MINOR_VERSION:INTERNAL=22 +//Patch version of cmake used to create the current loaded cache +CMAKE_CACHE_PATCH_VERSION:INTERNAL=1 +//ADVANCED property for variable: CMAKE_COLOR_MAKEFILE +CMAKE_COLOR_MAKEFILE-ADVANCED:INTERNAL=1 +//Path to CMake executable. +CMAKE_COMMAND:INTERNAL=/usr/bin/cmake +//Path to cpack program executable. +CMAKE_CPACK_COMMAND:INTERNAL=/usr/bin/cpack +//Path to ctest program executable. +CMAKE_CTEST_COMMAND:INTERNAL=/usr/bin/ctest +//ADVANCED property for variable: CMAKE_CXX_FLAGS +CMAKE_CXX_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_CXX_FLAGS_DEBUG +CMAKE_CXX_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_CXX_FLAGS_MINSIZEREL +CMAKE_CXX_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_CXX_FLAGS_RELEASE +CMAKE_CXX_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_CXX_FLAGS_RELWITHDEBINFO +CMAKE_CXX_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS +CMAKE_C_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS_DEBUG +CMAKE_C_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS_MINSIZEREL +CMAKE_C_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS_RELEASE +CMAKE_C_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_C_FLAGS_RELWITHDEBINFO +CMAKE_C_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_DLLTOOL +CMAKE_DLLTOOL-ADVANCED:INTERNAL=1 +//Executable file format +CMAKE_EXECUTABLE_FORMAT:INTERNAL=Unknown +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS +CMAKE_EXE_LINKER_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS_DEBUG +CMAKE_EXE_LINKER_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS_MINSIZEREL +CMAKE_EXE_LINKER_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS_RELEASE +CMAKE_EXE_LINKER_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO +CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//Name of external makefile project generator. +CMAKE_EXTRA_GENERATOR:INTERNAL= +//Name of generator. +CMAKE_GENERATOR:INTERNAL=Unix Makefiles +//Generator instance identifier. +CMAKE_GENERATOR_INSTANCE:INTERNAL= +//Name of generator platform. +CMAKE_GENERATOR_PLATFORM:INTERNAL= +//Name of generator toolset. +CMAKE_GENERATOR_TOOLSET:INTERNAL= +//Source directory with the top level CMakeLists.txt file for this +// project +CMAKE_HOME_DIRECTORY:INTERNAL=/home/lobov/workspace/ccs12.5/cmake_test +//Install .so files without execute permission. +CMAKE_INSTALL_SO_NO_EXE:INTERNAL=1 +//ADVANCED property for variable: CMAKE_LINKER +CMAKE_LINKER-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MAKE_PROGRAM +CMAKE_MAKE_PROGRAM-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS +CMAKE_MODULE_LINKER_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS_DEBUG +CMAKE_MODULE_LINKER_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS_MINSIZEREL +CMAKE_MODULE_LINKER_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS_RELEASE +CMAKE_MODULE_LINKER_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_MODULE_LINKER_FLAGS_RELWITHDEBINFO +CMAKE_MODULE_LINKER_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_NM +CMAKE_NM-ADVANCED:INTERNAL=1 +//number of local generators +CMAKE_NUMBER_OF_MAKEFILES:INTERNAL=1 +//ADVANCED property for variable: CMAKE_OBJCOPY +CMAKE_OBJCOPY-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_OBJDUMP +CMAKE_OBJDUMP-ADVANCED:INTERNAL=1 +//Platform information initialized +CMAKE_PLATFORM_INFO_INITIALIZED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_RANLIB +CMAKE_RANLIB-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_READELF +CMAKE_READELF-ADVANCED:INTERNAL=1 +//Path to CMake installation. +CMAKE_ROOT:INTERNAL=/usr/share/cmake-3.22 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS +CMAKE_SHARED_LINKER_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS_DEBUG +CMAKE_SHARED_LINKER_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS_MINSIZEREL +CMAKE_SHARED_LINKER_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS_RELEASE +CMAKE_SHARED_LINKER_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SHARED_LINKER_FLAGS_RELWITHDEBINFO +CMAKE_SHARED_LINKER_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SKIP_INSTALL_RPATH +CMAKE_SKIP_INSTALL_RPATH-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_SKIP_RPATH +CMAKE_SKIP_RPATH-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS +CMAKE_STATIC_LINKER_FLAGS-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS_DEBUG +CMAKE_STATIC_LINKER_FLAGS_DEBUG-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS_MINSIZEREL +CMAKE_STATIC_LINKER_FLAGS_MINSIZEREL-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS_RELEASE +CMAKE_STATIC_LINKER_FLAGS_RELEASE-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STATIC_LINKER_FLAGS_RELWITHDEBINFO +CMAKE_STATIC_LINKER_FLAGS_RELWITHDEBINFO-ADVANCED:INTERNAL=1 +//ADVANCED property for variable: CMAKE_STRIP +CMAKE_STRIP-ADVANCED:INTERNAL=1 +//uname command +CMAKE_UNAME:INTERNAL=/usr/bin/uname +//ADVANCED property for variable: CMAKE_VERBOSE_MAKEFILE +CMAKE_VERBOSE_MAKEFILE-ADVANCED:INTERNAL=1 + diff --git a/build/Debug/CMakeFiles/3.22.1/CMakeCCompiler.cmake b/build/Debug/CMakeFiles/3.22.1/CMakeCCompiler.cmake new file mode 100644 index 0000000..e5e1cb6 --- /dev/null +++ b/build/Debug/CMakeFiles/3.22.1/CMakeCCompiler.cmake @@ -0,0 +1,72 @@ +set(CMAKE_C_COMPILER "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000") +set(CMAKE_C_COMPILER_ARG1 "") +set(CMAKE_C_COMPILER_ID "TI") +set(CMAKE_C_COMPILER_VERSION "22.6.1") +set(CMAKE_C_COMPILER_VERSION_INTERNAL "") +set(CMAKE_C_COMPILER_WRAPPER "") +set(CMAKE_C_STANDARD_COMPUTED_DEFAULT "90") +set(CMAKE_C_EXTENSIONS_COMPUTED_DEFAULT "ON") +set(CMAKE_C_COMPILE_FEATURES "c_std_90;c_std_99;c_std_11") +set(CMAKE_C90_COMPILE_FEATURES "c_std_90") +set(CMAKE_C99_COMPILE_FEATURES "c_std_99") +set(CMAKE_C11_COMPILE_FEATURES "c_std_11") +set(CMAKE_C17_COMPILE_FEATURES "") +set(CMAKE_C23_COMPILE_FEATURES "") + +set(CMAKE_C_PLATFORM_ID "") +set(CMAKE_C_SIMULATE_ID "") +set(CMAKE_C_COMPILER_FRONTEND_VARIANT "") +set(CMAKE_C_SIMULATE_VERSION "") +set(CMAKE_C_COMPILER_ARCHITECTURE_ID TMS320C28x) + +set(MSVC_C_ARCHITECTURE_ID TMS320C28x) + +set(CMAKE_AR "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/ar2000") +set(CMAKE_C_COMPILER_AR "") +set(CMAKE_RANLIB "/usr/bin/ranlib") +set(CMAKE_C_COMPILER_RANLIB "") +set(CMAKE_LINKER "/usr/bin/ld") +set(CMAKE_MT "") +set(CMAKE_COMPILER_IS_GNUCC ) +set(CMAKE_C_COMPILER_LOADED 1) +set(CMAKE_C_COMPILER_WORKS TRUE) +set(CMAKE_C_ABI_COMPILED TRUE) + +set(CMAKE_C_COMPILER_ENV_VAR "CC") + +set(CMAKE_C_COMPILER_ID_RUN 1) +set(CMAKE_C_SOURCE_FILE_EXTENSIONS c;m) +set(CMAKE_C_IGNORE_EXTENSIONS h;H;o;O;obj;OBJ;def;DEF;rc;RC) +set(CMAKE_C_LINKER_PREFERENCE 10) + +# Save compiler ABI information. +set(CMAKE_C_SIZEOF_DATA_PTR "") +set(CMAKE_C_COMPILER_ABI "") +set(CMAKE_C_BYTE_ORDER "") +set(CMAKE_C_LIBRARY_ARCHITECTURE "") + +if(CMAKE_C_SIZEOF_DATA_PTR) + set(CMAKE_SIZEOF_VOID_P "${CMAKE_C_SIZEOF_DATA_PTR}") +endif() + +if(CMAKE_C_COMPILER_ABI) + set(CMAKE_INTERNAL_PLATFORM_ABI "${CMAKE_C_COMPILER_ABI}") +endif() + +if(CMAKE_C_LIBRARY_ARCHITECTURE) + set(CMAKE_LIBRARY_ARCHITECTURE "") +endif() + +set(CMAKE_C_CL_SHOWINCLUDES_PREFIX "") +if(CMAKE_C_CL_SHOWINCLUDES_PREFIX) + set(CMAKE_CL_SHOWINCLUDES_PREFIX "${CMAKE_C_CL_SHOWINCLUDES_PREFIX}") +endif() + + + + + +set(CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES "/usr/include") +set(CMAKE_C_IMPLICIT_LINK_LIBRARIES "") +set(CMAKE_C_IMPLICIT_LINK_DIRECTORIES "") +set(CMAKE_C_IMPLICIT_LINK_FRAMEWORK_DIRECTORIES "") diff --git a/build/Debug/CMakeFiles/3.22.1/CMakeCXXCompiler.cmake b/build/Debug/CMakeFiles/3.22.1/CMakeCXXCompiler.cmake new file mode 100644 index 0000000..aa0c3b3 --- /dev/null +++ b/build/Debug/CMakeFiles/3.22.1/CMakeCXXCompiler.cmake @@ -0,0 +1,83 @@ +set(CMAKE_CXX_COMPILER "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000") +set(CMAKE_CXX_COMPILER_ARG1 "") +set(CMAKE_CXX_COMPILER_ID "TI") +set(CMAKE_CXX_COMPILER_VERSION "22.6.1") +set(CMAKE_CXX_COMPILER_VERSION_INTERNAL "") +set(CMAKE_CXX_COMPILER_WRAPPER "") +set(CMAKE_CXX_STANDARD_COMPUTED_DEFAULT "98") +set(CMAKE_CXX_EXTENSIONS_COMPUTED_DEFAULT "ON") +set(CMAKE_CXX_COMPILE_FEATURES "cxx_std_98") +set(CMAKE_CXX98_COMPILE_FEATURES "cxx_std_98") +set(CMAKE_CXX11_COMPILE_FEATURES "") +set(CMAKE_CXX14_COMPILE_FEATURES "") +set(CMAKE_CXX17_COMPILE_FEATURES "") +set(CMAKE_CXX20_COMPILE_FEATURES "") +set(CMAKE_CXX23_COMPILE_FEATURES "") + +set(CMAKE_CXX_PLATFORM_ID "") +set(CMAKE_CXX_SIMULATE_ID "") +set(CMAKE_CXX_COMPILER_FRONTEND_VARIANT "") +set(CMAKE_CXX_SIMULATE_VERSION "") +set(CMAKE_CXX_COMPILER_ARCHITECTURE_ID TMS320C28x) + +set(MSVC_CXX_ARCHITECTURE_ID TMS320C28x) + +set(CMAKE_AR "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/ar2000") +set(CMAKE_CXX_COMPILER_AR "") +set(CMAKE_RANLIB "/usr/bin/ranlib") +set(CMAKE_CXX_COMPILER_RANLIB "") +set(CMAKE_LINKER "/usr/bin/ld") +set(CMAKE_MT "") +set(CMAKE_COMPILER_IS_GNUCXX ) +set(CMAKE_CXX_COMPILER_LOADED 1) +set(CMAKE_CXX_COMPILER_WORKS TRUE) +set(CMAKE_CXX_ABI_COMPILED TRUE) + +set(CMAKE_CXX_COMPILER_ENV_VAR "CXX") + +set(CMAKE_CXX_COMPILER_ID_RUN 1) +set(CMAKE_CXX_SOURCE_FILE_EXTENSIONS C;M;c++;cc;cpp;cxx;m;mm;mpp;CPP;ixx;cppm) +set(CMAKE_CXX_IGNORE_EXTENSIONS inl;h;hpp;HPP;H;o;O;obj;OBJ;def;DEF;rc;RC) + +foreach (lang C OBJC OBJCXX) + if (CMAKE_${lang}_COMPILER_ID_RUN) + foreach(extension IN LISTS CMAKE_${lang}_SOURCE_FILE_EXTENSIONS) + list(REMOVE_ITEM CMAKE_CXX_SOURCE_FILE_EXTENSIONS ${extension}) + endforeach() + endif() +endforeach() + +set(CMAKE_CXX_LINKER_PREFERENCE 30) +set(CMAKE_CXX_LINKER_PREFERENCE_PROPAGATES 1) + +# Save compiler ABI information. +set(CMAKE_CXX_SIZEOF_DATA_PTR "") +set(CMAKE_CXX_COMPILER_ABI "") +set(CMAKE_CXX_BYTE_ORDER "") +set(CMAKE_CXX_LIBRARY_ARCHITECTURE "") + +if(CMAKE_CXX_SIZEOF_DATA_PTR) + set(CMAKE_SIZEOF_VOID_P "${CMAKE_CXX_SIZEOF_DATA_PTR}") +endif() + +if(CMAKE_CXX_COMPILER_ABI) + set(CMAKE_INTERNAL_PLATFORM_ABI "${CMAKE_CXX_COMPILER_ABI}") +endif() + +if(CMAKE_CXX_LIBRARY_ARCHITECTURE) + set(CMAKE_LIBRARY_ARCHITECTURE "") +endif() + +set(CMAKE_CXX_CL_SHOWINCLUDES_PREFIX "") +if(CMAKE_CXX_CL_SHOWINCLUDES_PREFIX) + set(CMAKE_CL_SHOWINCLUDES_PREFIX "${CMAKE_CXX_CL_SHOWINCLUDES_PREFIX}") +endif() + + + + + +set(CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES "/usr/include") +set(CMAKE_CXX_IMPLICIT_LINK_LIBRARIES "") +set(CMAKE_CXX_IMPLICIT_LINK_DIRECTORIES "") +set(CMAKE_CXX_IMPLICIT_LINK_FRAMEWORK_DIRECTORIES "") diff --git a/build/Debug/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_C.bin b/build/Debug/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_C.bin new file mode 100644 index 0000000..8e08ea7 Binary files /dev/null and b/build/Debug/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_C.bin differ diff --git a/build/Debug/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_CXX.bin b/build/Debug/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_CXX.bin new file mode 100644 index 0000000..36680e3 Binary files /dev/null and b/build/Debug/CMakeFiles/3.22.1/CMakeDetermineCompilerABI_CXX.bin differ diff --git a/build/Debug/CMakeFiles/3.22.1/CMakeSystem.cmake b/build/Debug/CMakeFiles/3.22.1/CMakeSystem.cmake new file mode 100644 index 0000000..21d50c5 --- /dev/null +++ b/build/Debug/CMakeFiles/3.22.1/CMakeSystem.cmake @@ -0,0 +1,15 @@ +set(CMAKE_HOST_SYSTEM "Linux-6.2.0-39-generic") +set(CMAKE_HOST_SYSTEM_NAME "Linux") +set(CMAKE_HOST_SYSTEM_VERSION "6.2.0-39-generic") +set(CMAKE_HOST_SYSTEM_PROCESSOR "x86_64") + + + +set(CMAKE_SYSTEM "Linux-6.2.0-39-generic") +set(CMAKE_SYSTEM_NAME "Linux") +set(CMAKE_SYSTEM_VERSION "6.2.0-39-generic") +set(CMAKE_SYSTEM_PROCESSOR "x86_64") + +set(CMAKE_CROSSCOMPILING "FALSE") + +set(CMAKE_SYSTEM_LOADED 1) diff --git a/build/Debug/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.c b/build/Debug/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.c new file mode 100644 index 0000000..41b99d7 --- /dev/null +++ b/build/Debug/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.c @@ -0,0 +1,803 @@ +#ifdef __cplusplus +# error "A C++ compiler has been selected for C." +#endif + +#if defined(__18CXX) +# define ID_VOID_MAIN +#endif +#if defined(__CLASSIC_C__) +/* cv-qualifiers did not exist in K&R C */ +# define const +# define volatile +#endif + +#if !defined(__has_include) +/* If the compiler does not have __has_include, pretend the answer is + always no. */ +# define __has_include(x) 0 +#endif + + +/* Version number components: V=Version, R=Revision, P=Patch + Version date components: YYYY=Year, MM=Month, DD=Day */ + +#if defined(__INTEL_COMPILER) || defined(__ICC) +# define COMPILER_ID "Intel" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# if defined(__GNUC__) +# define SIMULATE_ID "GNU" +# endif + /* __INTEL_COMPILER = VRP prior to 2021, and then VVVV for 2021 and later, + except that a few beta releases use the old format with V=2021. */ +# if __INTEL_COMPILER < 2021 || __INTEL_COMPILER == 202110 || __INTEL_COMPILER == 202111 +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER/10 % 10) +# if defined(__INTEL_COMPILER_UPDATE) +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER_UPDATE) +# else +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER % 10) +# endif +# else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER_UPDATE) + /* The third version component from --version is an update index, + but no macro is provided for it. */ +# define COMPILER_VERSION_PATCH DEC(0) +# endif +# if defined(__INTEL_COMPILER_BUILD_DATE) + /* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */ +# define COMPILER_VERSION_TWEAK DEC(__INTEL_COMPILER_BUILD_DATE) +# endif +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif (defined(__clang__) && defined(__INTEL_CLANG_COMPILER)) || defined(__INTEL_LLVM_COMPILER) +# define COMPILER_ID "IntelLLVM" +#if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +#endif +#if defined(__GNUC__) +# define SIMULATE_ID "GNU" +#endif +/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and + * later. Look for 6 digit vs. 8 digit version number to decide encoding. + * VVVV is no smaller than the current year when a version is released. + */ +#if __INTEL_LLVM_COMPILER < 1000000L +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 10) +#else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 100) +#endif +#if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +#endif +#if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +#elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +#endif +#if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +#endif +#if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +#endif + +#elif defined(__PATHCC__) +# define COMPILER_ID "PathScale" +# define COMPILER_VERSION_MAJOR DEC(__PATHCC__) +# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__) +# if defined(__PATHCC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__) +# endif + +#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__) +# define COMPILER_ID "Embarcadero" +# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF) +# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF) +# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF) + +#elif defined(__BORLANDC__) +# define COMPILER_ID "Borland" + /* __BORLANDC__ = 0xVRR */ +# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8) +# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF) + +#elif defined(__WATCOMC__) && __WATCOMC__ < 1200 +# define COMPILER_ID "Watcom" + /* __WATCOMC__ = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__WATCOMC__) +# define COMPILER_ID "OpenWatcom" + /* __WATCOMC__ = VVRP + 1100 */ +# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__SUNPRO_C) +# define COMPILER_ID "SunPro" +# if __SUNPRO_C >= 0x5100 + /* __SUNPRO_C = 0xVRRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>12) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF) +# else + /* __SUNPRO_CC = 0xVRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>8) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF) +# endif + +#elif defined(__HP_cc) +# define COMPILER_ID "HP" + /* __HP_cc = VVRRPP */ +# define COMPILER_VERSION_MAJOR DEC(__HP_cc/10000) +# define COMPILER_VERSION_MINOR DEC(__HP_cc/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__HP_cc % 100) + +#elif defined(__DECC) +# define COMPILER_ID "Compaq" + /* __DECC_VER = VVRRTPPPP */ +# define COMPILER_VERSION_MAJOR DEC(__DECC_VER/10000000) +# define COMPILER_VERSION_MINOR DEC(__DECC_VER/100000 % 100) +# define COMPILER_VERSION_PATCH DEC(__DECC_VER % 10000) + +#elif defined(__IBMC__) && defined(__COMPILER_VER__) +# define COMPILER_ID "zOS" + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) + +#elif defined(__ibmxl__) && defined(__clang__) +# define COMPILER_ID "XLClang" +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) + + +#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ >= 800 +# define COMPILER_ID "XL" + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) + +#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ < 800 +# define COMPILER_ID "VisualAge" + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) + +#elif defined(__NVCOMPILER) +# define COMPILER_ID "NVHPC" +# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__) +# if defined(__NVCOMPILER_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__) +# endif + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif defined(_CRAYC) +# define COMPILER_ID "Cray" +# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) +# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) + +#elif defined(__TI_COMPILER_VERSION__) +# define COMPILER_ID "TI" + /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ +# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) +# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) +# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) + +#elif defined(__CLANG_FUJITSU) +# define COMPILER_ID "FujitsuClang" +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(__FUJITSU) +# define COMPILER_ID "Fujitsu" +# if defined(__FCC_version__) +# define COMPILER_VERSION __FCC_version__ +# elif defined(__FCC_major__) +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# endif +# if defined(__fcc_version) +# define COMPILER_VERSION_INTERNAL DEC(__fcc_version) +# elif defined(__FCC_VERSION) +# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION) +# endif + + +#elif defined(__ghs__) +# define COMPILER_ID "GHS" +/* __GHS_VERSION_NUMBER = VVVVRP */ +# ifdef __GHS_VERSION_NUMBER +# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100) +# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10) +# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10) +# endif + +#elif defined(__TINYC__) +# define COMPILER_ID "TinyCC" + +#elif defined(__BCC__) +# define COMPILER_ID "Bruce" + +#elif defined(__SCO_VERSION__) +# define COMPILER_ID "SCO" + +#elif defined(__ARMCC_VERSION) && !defined(__clang__) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(__clang__) && defined(__apple_build_version__) +# define COMPILER_ID "AppleClang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) + +#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION) +# define COMPILER_ID "ARMClang" + # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION % 10000) +# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__GNUC__) +# define COMPILER_ID "GNU" +# define COMPILER_VERSION_MAJOR DEC(__GNUC__) +# if defined(__GNUC_MINOR__) +# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif defined(_MSC_VER) +# define COMPILER_ID "MSVC" + /* _MSC_VER = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) +# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) +# if defined(_MSC_FULL_VER) +# if _MSC_VER >= 1400 + /* _MSC_FULL_VER = VVRRPPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) +# else + /* _MSC_FULL_VER = VVRRPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) +# endif +# endif +# if defined(_MSC_BUILD) +# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) +# endif + +#elif defined(__VISUALDSPVERSION__) || defined(__ADSPBLACKFIN__) || defined(__ADSPTS__) || defined(__ADSP21000__) +# define COMPILER_ID "ADSP" +#if defined(__VISUALDSPVERSION__) + /* __VISUALDSPVERSION__ = 0xVVRRPP00 */ +# define COMPILER_VERSION_MAJOR HEX(__VISUALDSPVERSION__>>24) +# define COMPILER_VERSION_MINOR HEX(__VISUALDSPVERSION__>>16 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__VISUALDSPVERSION__>>8 & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) && defined(__ICCARM__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) +# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) +# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + +#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC) +# define COMPILER_ID "SDCC" +# if defined(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR) +# define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH) +# else + /* SDCC = VRP */ +# define COMPILER_VERSION_MAJOR DEC(SDCC/100) +# define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10) +# define COMPILER_VERSION_PATCH DEC(SDCC % 10) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__MSYS__) +# define PLATFORM_ID "MSYS" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# elif defined(__VXWORKS__) +# define PLATFORM_ID "VxWorks" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#elif defined(__INTEGRITY) +# if defined(INT_178B) +# define PLATFORM_ID "Integrity178" + +# else /* regular Integrity */ +# define PLATFORM_ID "Integrity" +# endif + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_ARM64EC) +# define ARCHITECTURE_ID "ARM64EC" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCRX__) +# define ARCHITECTURE_ID "RX" + +# elif defined(__ICCRH850__) +# define ARCHITECTURE_ID "RH850" + +# elif defined(__ICCRL78__) +# define ARCHITECTURE_ID "RL78" + +# elif defined(__ICCRISCV__) +# define ARCHITECTURE_ID "RISCV" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# elif defined(__ICC430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__ICCV850__) +# define ARCHITECTURE_ID "V850" + +# elif defined(__ICC8051__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__ICCSTM8__) +# define ARCHITECTURE_ID "STM8" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__ghs__) +# if defined(__PPC64__) +# define ARCHITECTURE_ID "PPC64" + +# elif defined(__ppc__) +# define ARCHITECTURE_ID "PPC" + +# elif defined(__ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__x86_64__) +# define ARCHITECTURE_ID "x64" + +# elif defined(__i386__) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__TI_COMPILER_VERSION__) +# if defined(__TI_ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__MSP430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__TMS320C28XX__) +# define ARCHITECTURE_ID "TMS320C28x" + +# elif defined(__TMS320C6X__) || defined(_TMS320C6X) +# define ARCHITECTURE_ID "TMS320C6x" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number. */ +#ifdef COMPILER_VERSION +char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; + +/* Construct a string literal encoding the version number components. */ +#elif defined(COMPILER_VERSION_MAJOR) +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#elif defined(COMPILER_VERSION_INTERNAL_STR) +char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + +#if !defined(__STDC__) && !defined(__clang__) +# if defined(_MSC_VER) || defined(__ibmxl__) || defined(__IBMC__) +# define C_VERSION "90" +# else +# define C_VERSION +# endif +#elif __STDC_VERSION__ > 201710L +# define C_VERSION "23" +#elif __STDC_VERSION__ >= 201710L +# define C_VERSION "17" +#elif __STDC_VERSION__ >= 201000L +# define C_VERSION "11" +#elif __STDC_VERSION__ >= 199901L +# define C_VERSION "99" +#else +# define C_VERSION "90" +#endif +const char* info_language_standard_default = + "INFO" ":" "standard_default[" C_VERSION "]"; + +const char* info_language_extensions_default = "INFO" ":" "extensions_default[" +/* !defined(_MSC_VER) to exclude Clang's MSVC compatibility mode. */ +#if (defined(__clang__) || defined(__GNUC__) || \ + defined(__TI_COMPILER_VERSION__)) && \ + !defined(__STRICT_ANSI__) && !defined(_MSC_VER) + "ON" +#else + "OFF" +#endif +"]"; + +/*--------------------------------------------------------------------------*/ + +#ifdef ID_VOID_MAIN +void main() {} +#else +# if defined(__CLASSIC_C__) +int main(argc, argv) int argc; char *argv[]; +# else +int main(int argc, char* argv[]) +# endif +{ + int require = 0; + require += info_compiler[argc]; + require += info_platform[argc]; + require += info_arch[argc]; +#ifdef COMPILER_VERSION_MAJOR + require += info_version[argc]; +#endif +#ifdef COMPILER_VERSION_INTERNAL + require += info_version_internal[argc]; +#endif +#ifdef SIMULATE_ID + require += info_simulate[argc]; +#endif +#ifdef SIMULATE_VERSION_MAJOR + require += info_simulate_version[argc]; +#endif +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) + require += info_cray[argc]; +#endif + require += info_language_standard_default[argc]; + require += info_language_extensions_default[argc]; + (void)argv; + return require; +} +#endif diff --git a/build/Debug/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.obj b/build/Debug/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.obj new file mode 100644 index 0000000..442c377 Binary files /dev/null and b/build/Debug/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.obj differ diff --git a/build/Debug/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.cpp b/build/Debug/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.cpp new file mode 100644 index 0000000..25c62a8 --- /dev/null +++ b/build/Debug/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.cpp @@ -0,0 +1,791 @@ +/* This source file must have a .cpp extension so that all C++ compilers + recognize the extension without flags. Borland does not know .cxx for + example. */ +#ifndef __cplusplus +# error "A C compiler has been selected for C++." +#endif + +#if !defined(__has_include) +/* If the compiler does not have __has_include, pretend the answer is + always no. */ +# define __has_include(x) 0 +#endif + + +/* Version number components: V=Version, R=Revision, P=Patch + Version date components: YYYY=Year, MM=Month, DD=Day */ + +#if defined(__COMO__) +# define COMPILER_ID "Comeau" + /* __COMO_VERSION__ = VRR */ +# define COMPILER_VERSION_MAJOR DEC(__COMO_VERSION__ / 100) +# define COMPILER_VERSION_MINOR DEC(__COMO_VERSION__ % 100) + +#elif defined(__INTEL_COMPILER) || defined(__ICC) +# define COMPILER_ID "Intel" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# if defined(__GNUC__) +# define SIMULATE_ID "GNU" +# endif + /* __INTEL_COMPILER = VRP prior to 2021, and then VVVV for 2021 and later, + except that a few beta releases use the old format with V=2021. */ +# if __INTEL_COMPILER < 2021 || __INTEL_COMPILER == 202110 || __INTEL_COMPILER == 202111 +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER/10 % 10) +# if defined(__INTEL_COMPILER_UPDATE) +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER_UPDATE) +# else +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER % 10) +# endif +# else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER_UPDATE) + /* The third version component from --version is an update index, + but no macro is provided for it. */ +# define COMPILER_VERSION_PATCH DEC(0) +# endif +# if defined(__INTEL_COMPILER_BUILD_DATE) + /* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */ +# define COMPILER_VERSION_TWEAK DEC(__INTEL_COMPILER_BUILD_DATE) +# endif +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif (defined(__clang__) && defined(__INTEL_CLANG_COMPILER)) || defined(__INTEL_LLVM_COMPILER) +# define COMPILER_ID "IntelLLVM" +#if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +#endif +#if defined(__GNUC__) +# define SIMULATE_ID "GNU" +#endif +/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and + * later. Look for 6 digit vs. 8 digit version number to decide encoding. + * VVVV is no smaller than the current year when a version is released. + */ +#if __INTEL_LLVM_COMPILER < 1000000L +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 10) +#else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 100) +#endif +#if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +#endif +#if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +#elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +#endif +#if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +#endif +#if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +#endif + +#elif defined(__PATHCC__) +# define COMPILER_ID "PathScale" +# define COMPILER_VERSION_MAJOR DEC(__PATHCC__) +# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__) +# if defined(__PATHCC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__) +# endif + +#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__) +# define COMPILER_ID "Embarcadero" +# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF) +# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF) +# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF) + +#elif defined(__BORLANDC__) +# define COMPILER_ID "Borland" + /* __BORLANDC__ = 0xVRR */ +# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8) +# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF) + +#elif defined(__WATCOMC__) && __WATCOMC__ < 1200 +# define COMPILER_ID "Watcom" + /* __WATCOMC__ = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__WATCOMC__) +# define COMPILER_ID "OpenWatcom" + /* __WATCOMC__ = VVRP + 1100 */ +# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__SUNPRO_CC) +# define COMPILER_ID "SunPro" +# if __SUNPRO_CC >= 0x5100 + /* __SUNPRO_CC = 0xVRRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>12) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# else + /* __SUNPRO_CC = 0xVRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>8) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# endif + +#elif defined(__HP_aCC) +# define COMPILER_ID "HP" + /* __HP_aCC = VVRRPP */ +# define COMPILER_VERSION_MAJOR DEC(__HP_aCC/10000) +# define COMPILER_VERSION_MINOR DEC(__HP_aCC/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__HP_aCC % 100) + +#elif defined(__DECCXX) +# define COMPILER_ID "Compaq" + /* __DECCXX_VER = VVRRTPPPP */ +# define COMPILER_VERSION_MAJOR DEC(__DECCXX_VER/10000000) +# define COMPILER_VERSION_MINOR DEC(__DECCXX_VER/100000 % 100) +# define COMPILER_VERSION_PATCH DEC(__DECCXX_VER % 10000) + +#elif defined(__IBMCPP__) && defined(__COMPILER_VER__) +# define COMPILER_ID "zOS" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__ibmxl__) && defined(__clang__) +# define COMPILER_ID "XLClang" +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) + + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ >= 800 +# define COMPILER_ID "XL" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ < 800 +# define COMPILER_ID "VisualAge" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__NVCOMPILER) +# define COMPILER_ID "NVHPC" +# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__) +# if defined(__NVCOMPILER_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__) +# endif + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif defined(_CRAYC) +# define COMPILER_ID "Cray" +# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) +# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) + +#elif defined(__TI_COMPILER_VERSION__) +# define COMPILER_ID "TI" + /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ +# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) +# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) +# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) + +#elif defined(__CLANG_FUJITSU) +# define COMPILER_ID "FujitsuClang" +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(__FUJITSU) +# define COMPILER_ID "Fujitsu" +# if defined(__FCC_version__) +# define COMPILER_VERSION __FCC_version__ +# elif defined(__FCC_major__) +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# endif +# if defined(__fcc_version) +# define COMPILER_VERSION_INTERNAL DEC(__fcc_version) +# elif defined(__FCC_VERSION) +# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION) +# endif + + +#elif defined(__ghs__) +# define COMPILER_ID "GHS" +/* __GHS_VERSION_NUMBER = VVVVRP */ +# ifdef __GHS_VERSION_NUMBER +# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100) +# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10) +# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10) +# endif + +#elif defined(__SCO_VERSION__) +# define COMPILER_ID "SCO" + +#elif defined(__ARMCC_VERSION) && !defined(__clang__) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(__clang__) && defined(__apple_build_version__) +# define COMPILER_ID "AppleClang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) + +#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION) +# define COMPILER_ID "ARMClang" + # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION % 10000) +# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__GNUC__) || defined(__GNUG__) +# define COMPILER_ID "GNU" +# if defined(__GNUC__) +# define COMPILER_VERSION_MAJOR DEC(__GNUC__) +# else +# define COMPILER_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif defined(_MSC_VER) +# define COMPILER_ID "MSVC" + /* _MSC_VER = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) +# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) +# if defined(_MSC_FULL_VER) +# if _MSC_VER >= 1400 + /* _MSC_FULL_VER = VVRRPPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) +# else + /* _MSC_FULL_VER = VVRRPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) +# endif +# endif +# if defined(_MSC_BUILD) +# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) +# endif + +#elif defined(__VISUALDSPVERSION__) || defined(__ADSPBLACKFIN__) || defined(__ADSPTS__) || defined(__ADSP21000__) +# define COMPILER_ID "ADSP" +#if defined(__VISUALDSPVERSION__) + /* __VISUALDSPVERSION__ = 0xVVRRPP00 */ +# define COMPILER_VERSION_MAJOR HEX(__VISUALDSPVERSION__>>24) +# define COMPILER_VERSION_MINOR HEX(__VISUALDSPVERSION__>>16 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__VISUALDSPVERSION__>>8 & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) && defined(__ICCARM__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) +# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) +# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__MSYS__) +# define PLATFORM_ID "MSYS" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# elif defined(__VXWORKS__) +# define PLATFORM_ID "VxWorks" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#elif defined(__INTEGRITY) +# if defined(INT_178B) +# define PLATFORM_ID "Integrity178" + +# else /* regular Integrity */ +# define PLATFORM_ID "Integrity" +# endif + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_ARM64EC) +# define ARCHITECTURE_ID "ARM64EC" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCRX__) +# define ARCHITECTURE_ID "RX" + +# elif defined(__ICCRH850__) +# define ARCHITECTURE_ID "RH850" + +# elif defined(__ICCRL78__) +# define ARCHITECTURE_ID "RL78" + +# elif defined(__ICCRISCV__) +# define ARCHITECTURE_ID "RISCV" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# elif defined(__ICC430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__ICCV850__) +# define ARCHITECTURE_ID "V850" + +# elif defined(__ICC8051__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__ICCSTM8__) +# define ARCHITECTURE_ID "STM8" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__ghs__) +# if defined(__PPC64__) +# define ARCHITECTURE_ID "PPC64" + +# elif defined(__ppc__) +# define ARCHITECTURE_ID "PPC" + +# elif defined(__ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__x86_64__) +# define ARCHITECTURE_ID "x64" + +# elif defined(__i386__) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__TI_COMPILER_VERSION__) +# if defined(__TI_ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__MSP430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__TMS320C28XX__) +# define ARCHITECTURE_ID "TMS320C28x" + +# elif defined(__TMS320C6X__) || defined(_TMS320C6X) +# define ARCHITECTURE_ID "TMS320C6x" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number. */ +#ifdef COMPILER_VERSION +char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; + +/* Construct a string literal encoding the version number components. */ +#elif defined(COMPILER_VERSION_MAJOR) +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#elif defined(COMPILER_VERSION_INTERNAL_STR) +char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + +#if defined(__INTEL_COMPILER) && defined(_MSVC_LANG) && _MSVC_LANG < 201403L +# if defined(__INTEL_CXX11_MODE__) +# if defined(__cpp_aggregate_nsdmi) +# define CXX_STD 201402L +# else +# define CXX_STD 201103L +# endif +# else +# define CXX_STD 199711L +# endif +#elif defined(_MSC_VER) && defined(_MSVC_LANG) +# define CXX_STD _MSVC_LANG +#else +# define CXX_STD __cplusplus +#endif + +const char* info_language_standard_default = "INFO" ":" "standard_default[" +#if CXX_STD > 202002L + "23" +#elif CXX_STD > 201703L + "20" +#elif CXX_STD >= 201703L + "17" +#elif CXX_STD >= 201402L + "14" +#elif CXX_STD >= 201103L + "11" +#else + "98" +#endif +"]"; + +const char* info_language_extensions_default = "INFO" ":" "extensions_default[" +/* !defined(_MSC_VER) to exclude Clang's MSVC compatibility mode. */ +#if (defined(__clang__) || defined(__GNUC__) || \ + defined(__TI_COMPILER_VERSION__)) && \ + !defined(__STRICT_ANSI__) && !defined(_MSC_VER) + "ON" +#else + "OFF" +#endif +"]"; + +/*--------------------------------------------------------------------------*/ + +int main(int argc, char* argv[]) +{ + int require = 0; + require += info_compiler[argc]; + require += info_platform[argc]; +#ifdef COMPILER_VERSION_MAJOR + require += info_version[argc]; +#endif +#ifdef COMPILER_VERSION_INTERNAL + require += info_version_internal[argc]; +#endif +#ifdef SIMULATE_ID + require += info_simulate[argc]; +#endif +#ifdef SIMULATE_VERSION_MAJOR + require += info_simulate_version[argc]; +#endif +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) + require += info_cray[argc]; +#endif + require += info_language_standard_default[argc]; + require += info_language_extensions_default[argc]; + (void)argv; + return require; +} diff --git a/build/Debug/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.obj b/build/Debug/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.obj new file mode 100644 index 0000000..2567a26 Binary files /dev/null and b/build/Debug/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.obj differ diff --git a/build/Debug/CMakeFiles/CMakeDirectoryInformation.cmake b/build/Debug/CMakeFiles/CMakeDirectoryInformation.cmake new file mode 100644 index 0000000..722d2d2 --- /dev/null +++ b/build/Debug/CMakeFiles/CMakeDirectoryInformation.cmake @@ -0,0 +1,16 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# Relative path conversion top directories. +set(CMAKE_RELATIVE_PATH_TOP_SOURCE "/home/lobov/workspace/ccs12.5/cmake_test") +set(CMAKE_RELATIVE_PATH_TOP_BINARY "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug") + +# Force unix paths in dependencies. +set(CMAKE_FORCE_UNIX_PATHS 1) + + +# The C and CXX include file regular expressions for this directory. +set(CMAKE_C_INCLUDE_REGEX_SCAN "^.*$") +set(CMAKE_C_INCLUDE_REGEX_COMPLAIN "^$") +set(CMAKE_CXX_INCLUDE_REGEX_SCAN ${CMAKE_C_INCLUDE_REGEX_SCAN}) +set(CMAKE_CXX_INCLUDE_REGEX_COMPLAIN ${CMAKE_C_INCLUDE_REGEX_COMPLAIN}) diff --git a/build/Debug/CMakeFiles/CMakeOutput.log b/build/Debug/CMakeFiles/CMakeOutput.log new file mode 100644 index 0000000..4a84b7d --- /dev/null +++ b/build/Debug/CMakeFiles/CMakeOutput.log @@ -0,0 +1,125 @@ +The system is: Linux - 6.2.0-39-generic - x86_64 +Compiling the C compiler identification source file "CMakeCCompilerId.c" succeeded. +Compiler: /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 +Build flags: +Id flags: + +The output was: +0 + + +Compilation of the C compiler identification source "CMakeCCompilerId.c" produced "CMakeCCompilerId.obj" + +The C compiler identification is TI, found in "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/3.22.1/CompilerIdC/CMakeCCompilerId.obj" + +Compiling the CXX compiler identification source file "CMakeCXXCompilerId.cpp" succeeded. +Compiler: /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 +Build flags: +Id flags: + +The output was: +0 + + +Compilation of the CXX compiler identification source "CMakeCXXCompilerId.cpp" produced "CMakeCXXCompilerId.obj" + +The CXX compiler identification is TI, found in "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/3.22.1/CompilerIdCXX/CMakeCXXCompilerId.obj" + +Detecting C compiler ABI info compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_041c8/fast && /usr/bin/gmake -f CMakeFiles/cmTC_041c8.dir/build.make CMakeFiles/cmTC_041c8.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' +Building C object CMakeFiles/cmTC_041c8.dir/CMakeCCompilerABI.c.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/usr/share/cmake-3.22/Modules/CMakeCCompilerABI.c --output_file=CMakeFiles/cmTC_041c8.dir/CMakeCCompilerABI.c.o +Linking C executable cmTC_041c8 +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_041c8.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_041c8 --map_file=cmTC_041c8.map CMakeFiles/cmTC_041c8.dir/CMakeCCompilerABI.c.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' + + + + + +Detecting C [--c11;--strict_ansi] compiler features compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_3d78d/fast && /usr/bin/gmake -f CMakeFiles/cmTC_3d78d.dir/build.make CMakeFiles/cmTC_3d78d.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' +Building C object CMakeFiles/cmTC_3d78d.dir/feature_tests.c.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/feature_tests.c --c11 --strict_ansi --output_file=CMakeFiles/cmTC_3d78d.dir/feature_tests.c.o +Linking C executable cmTC_3d78d +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_3d78d.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_3d78d --map_file=cmTC_3d78d.map CMakeFiles/cmTC_3d78d.dir/feature_tests.c.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' + + + + + +Detecting C [--c99;--strict_ansi] compiler features compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_d1251/fast && /usr/bin/gmake -f CMakeFiles/cmTC_d1251.dir/build.make CMakeFiles/cmTC_d1251.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' +Building C object CMakeFiles/cmTC_d1251.dir/feature_tests.c.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/feature_tests.c --c99 --strict_ansi --output_file=CMakeFiles/cmTC_d1251.dir/feature_tests.c.o +Linking C executable cmTC_d1251 +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_d1251.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_d1251 --map_file=cmTC_d1251.map CMakeFiles/cmTC_d1251.dir/feature_tests.c.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' + + + + + +Detecting C [--c89;--strict_ansi] compiler features compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_16d3b/fast && /usr/bin/gmake -f CMakeFiles/cmTC_16d3b.dir/build.make CMakeFiles/cmTC_16d3b.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' +Building C object CMakeFiles/cmTC_16d3b.dir/feature_tests.c.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/feature_tests.c --c89 --strict_ansi --output_file=CMakeFiles/cmTC_16d3b.dir/feature_tests.c.o +Linking C executable cmTC_16d3b +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_16d3b.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_16d3b --map_file=cmTC_16d3b.map CMakeFiles/cmTC_16d3b.dir/feature_tests.c.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' + + + +Detecting CXX compiler ABI info compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_0b44b/fast && /usr/bin/gmake -f CMakeFiles/cmTC_0b44b.dir/build.make CMakeFiles/cmTC_0b44b.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' +Building CXX object CMakeFiles/cmTC_0b44b.dir/CMakeCXXCompilerABI.cpp.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --cpp_file=/usr/share/cmake-3.22/Modules/CMakeCXXCompilerABI.cpp --output_file=CMakeFiles/cmTC_0b44b.dir/CMakeCXXCompilerABI.cpp.o +Linking CXX executable cmTC_0b44b +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_0b44b.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_0b44b --map_file=cmTC_0b44b.map CMakeFiles/cmTC_0b44b.dir/CMakeCXXCompilerABI.cpp.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' + + + + + +Detecting CXX [--c++03;--strict_ansi] compiler features compiled with the following output: +Change Dir: /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp + +Run Build Command(s):/usr/bin/gmake -f Makefile cmTC_6dd94/fast && /usr/bin/gmake -f CMakeFiles/cmTC_6dd94.dir/build.make CMakeFiles/cmTC_6dd94.dir/build +gmake[1]: Entering directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' +Building CXX object CMakeFiles/cmTC_6dd94.dir/feature_tests.cxx.o +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/feature_tests.cxx --c++03 --strict_ansi --output_file=CMakeFiles/cmTC_6dd94.dir/feature_tests.cxx.o +Linking CXX executable cmTC_6dd94 +/usr/bin/cmake -E cmake_link_script CMakeFiles/cmTC_6dd94.dir/link.txt --verbose=1 +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=cmTC_6dd94 --map_file=cmTC_6dd94.map CMakeFiles/cmTC_6dd94.dir/feature_tests.cxx.o + +gmake[1]: Leaving directory '/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/CMakeTmp' + + + diff --git a/build/Debug/CMakeFiles/Makefile.cmake b/build/Debug/CMakeFiles/Makefile.cmake new file mode 100644 index 0000000..3157b0a --- /dev/null +++ b/build/Debug/CMakeFiles/Makefile.cmake @@ -0,0 +1,44 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# The generator used is: +set(CMAKE_DEPENDS_GENERATOR "Unix Makefiles") + +# The top level Makefile was generated from the following files: +set(CMAKE_MAKEFILE_DEPENDS + "CMakeCache.txt" + "../../CMakeLists.txt" + "CMakeFiles/3.22.1/CMakeCCompiler.cmake" + "CMakeFiles/3.22.1/CMakeCXXCompiler.cmake" + "CMakeFiles/3.22.1/CMakeSystem.cmake" + "/usr/share/cmake-3.22/Modules/CMakeCInformation.cmake" + "/usr/share/cmake-3.22/Modules/CMakeCXXInformation.cmake" + "/usr/share/cmake-3.22/Modules/CMakeCommonLanguageInclude.cmake" + "/usr/share/cmake-3.22/Modules/CMakeGenericSystem.cmake" + "/usr/share/cmake-3.22/Modules/CMakeInitializeConfigs.cmake" + "/usr/share/cmake-3.22/Modules/CMakeLanguageInformation.cmake" + "/usr/share/cmake-3.22/Modules/CMakeSystemSpecificInformation.cmake" + "/usr/share/cmake-3.22/Modules/CMakeSystemSpecificInitialize.cmake" + "/usr/share/cmake-3.22/Modules/Compiler/CMakeCommonCompilerMacros.cmake" + "/usr/share/cmake-3.22/Modules/Compiler/TI-C.cmake" + "/usr/share/cmake-3.22/Modules/Compiler/TI-CXX.cmake" + "/usr/share/cmake-3.22/Modules/Compiler/TI.cmake" + "/usr/share/cmake-3.22/Modules/Platform/Linux.cmake" + "/usr/share/cmake-3.22/Modules/Platform/UnixPaths.cmake" + ) + +# The corresponding makefile is: +set(CMAKE_MAKEFILE_OUTPUTS + "Makefile" + "CMakeFiles/cmake.check_cache" + ) + +# Byproducts of CMake generate step: +set(CMAKE_MAKEFILE_PRODUCTS + "CMakeFiles/CMakeDirectoryInformation.cmake" + ) + +# Dependency information for all targets: +set(CMAKE_DEPEND_INFO_FILES + "CMakeFiles/test_project.dir/DependInfo.cmake" + ) diff --git a/build/Debug/CMakeFiles/Makefile2 b/build/Debug/CMakeFiles/Makefile2 new file mode 100644 index 0000000..770c81a --- /dev/null +++ b/build/Debug/CMakeFiles/Makefile2 @@ -0,0 +1,112 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# Default target executed when no arguments are given to make. +default_target: all +.PHONY : default_target + +#============================================================================= +# Special targets provided by cmake. + +# Disable implicit rules so canonical targets will work. +.SUFFIXES: + +# Disable VCS-based implicit rules. +% : %,v + +# Disable VCS-based implicit rules. +% : RCS/% + +# Disable VCS-based implicit rules. +% : RCS/%,v + +# Disable VCS-based implicit rules. +% : SCCS/s.% + +# Disable VCS-based implicit rules. +% : s.% + +.SUFFIXES: .hpux_make_needs_suffix_list + +# Command-line flag to silence nested $(MAKE). +$(VERBOSE)MAKESILENT = -s + +#Suppress display of executed commands. +$(VERBOSE).SILENT: + +# A target that is always out of date. +cmake_force: +.PHONY : cmake_force + +#============================================================================= +# Set environment variables for the build. + +# The shell in which to execute make rules. +SHELL = /bin/sh + +# The CMake executable. +CMAKE_COMMAND = /usr/bin/cmake + +# The command to remove a file. +RM = /usr/bin/cmake -E rm -f + +# Escaping for special characters. +EQUALS = = + +# The top-level source directory on which CMake was run. +CMAKE_SOURCE_DIR = /home/lobov/workspace/ccs12.5/cmake_test + +# The top-level build directory on which CMake was run. +CMAKE_BINARY_DIR = /home/lobov/workspace/ccs12.5/cmake_test/build/Debug + +#============================================================================= +# Directory level rules for the build root directory + +# The main recursive "all" target. +all: CMakeFiles/test_project.dir/all +.PHONY : all + +# The main recursive "preinstall" target. +preinstall: +.PHONY : preinstall + +# The main recursive "clean" target. +clean: CMakeFiles/test_project.dir/clean +.PHONY : clean + +#============================================================================= +# Target rules for target CMakeFiles/test_project.dir + +# All Build rule for target. +CMakeFiles/test_project.dir/all: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/depend + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/build + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles --progress-num=1,2,3,4,5,6,7 "Built target test_project" +.PHONY : CMakeFiles/test_project.dir/all + +# Build rule for subdir invocation for target. +CMakeFiles/test_project.dir/rule: cmake_check_build_system + $(CMAKE_COMMAND) -E cmake_progress_start /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles 7 + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 CMakeFiles/test_project.dir/all + $(CMAKE_COMMAND) -E cmake_progress_start /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles 0 +.PHONY : CMakeFiles/test_project.dir/rule + +# Convenience name for target. +test_project: CMakeFiles/test_project.dir/rule +.PHONY : test_project + +# clean rule for target. +CMakeFiles/test_project.dir/clean: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/clean +.PHONY : CMakeFiles/test_project.dir/clean + +#============================================================================= +# Special targets to cleanup operation of make. + +# Special rule to run CMake to check the build system integrity. +# No rule that depends on this can have commands that come from listfiles +# because they might be regenerated. +cmake_check_build_system: + $(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 0 +.PHONY : cmake_check_build_system + diff --git a/build/Debug/CMakeFiles/ShowIncludes/foo.h b/build/Debug/CMakeFiles/ShowIncludes/foo.h new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/build/Debug/CMakeFiles/ShowIncludes/foo.h @@ -0,0 +1 @@ + diff --git a/build/Debug/CMakeFiles/ShowIncludes/main.c b/build/Debug/CMakeFiles/ShowIncludes/main.c new file mode 100644 index 0000000..cd3cbc1 --- /dev/null +++ b/build/Debug/CMakeFiles/ShowIncludes/main.c @@ -0,0 +1,2 @@ +#include "foo.h" +int main(){} diff --git a/build/Debug/CMakeFiles/TargetDirectories.txt b/build/Debug/CMakeFiles/TargetDirectories.txt new file mode 100644 index 0000000..7a8cbec --- /dev/null +++ b/build/Debug/CMakeFiles/TargetDirectories.txt @@ -0,0 +1,3 @@ +/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/test_project.dir +/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/edit_cache.dir +/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/rebuild_cache.dir diff --git a/build/Debug/CMakeFiles/cmake.check_cache b/build/Debug/CMakeFiles/cmake.check_cache new file mode 100644 index 0000000..3dccd73 --- /dev/null +++ b/build/Debug/CMakeFiles/cmake.check_cache @@ -0,0 +1 @@ +# This file is generated by cmake for dependency checking of the CMakeCache.txt file diff --git a/build/Debug/CMakeFiles/feature_tests.bin b/build/Debug/CMakeFiles/feature_tests.bin new file mode 100644 index 0000000..640c06d Binary files /dev/null and b/build/Debug/CMakeFiles/feature_tests.bin differ diff --git a/build/Debug/CMakeFiles/feature_tests.c b/build/Debug/CMakeFiles/feature_tests.c new file mode 100644 index 0000000..29f0da9 --- /dev/null +++ b/build/Debug/CMakeFiles/feature_tests.c @@ -0,0 +1,6 @@ + + const char features[] = {"\n" + +}; + +int main(int argc, char** argv) { (void)argv; return features[argc]; } diff --git a/build/Debug/CMakeFiles/feature_tests.cxx b/build/Debug/CMakeFiles/feature_tests.cxx new file mode 100644 index 0000000..29f0da9 --- /dev/null +++ b/build/Debug/CMakeFiles/feature_tests.cxx @@ -0,0 +1,6 @@ + + const char features[] = {"\n" + +}; + +int main(int argc, char** argv) { (void)argv; return features[argc]; } diff --git a/build/Debug/CMakeFiles/progress.marks b/build/Debug/CMakeFiles/progress.marks new file mode 100644 index 0000000..7f8f011 --- /dev/null +++ b/build/Debug/CMakeFiles/progress.marks @@ -0,0 +1 @@ +7 diff --git a/build/Debug/CMakeFiles/test_project.dir/C.includecache b/build/Debug/CMakeFiles/test_project.dir/C.includecache new file mode 100644 index 0000000..c6f2b2b --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/C.includecache @@ -0,0 +1,132 @@ +#IncludeRegexLine: ^[ ]*[#%][ ]*(include|import)[ ]*[<"]([^">]+)([">]) + +#IncludeRegexScan: ^.*$ + +#IncludeRegexComplain: ^$ + +#IncludeRegexTransform: + +../../f2833x/common/include/DSP2833x_DefaultIsr.h + +../../f2833x/common/include/DSP2833x_Dma_defines.h + +../../f2833x/common/include/DSP2833x_EPwm_defines.h + +../../f2833x/common/include/DSP2833x_Examples.h +DSP2833x_GlobalPrototypes.h +../../f2833x/common/include/DSP2833x_GlobalPrototypes.h +DSP2833x_EPwm_defines.h +../../f2833x/common/include/DSP2833x_EPwm_defines.h +DSP2833x_Dma_defines.h +../../f2833x/common/include/DSP2833x_Dma_defines.h +DSP2833x_I2c_defines.h +../../f2833x/common/include/DSP2833x_I2c_defines.h +DSP2833x_DefaultIsr.h +../../f2833x/common/include/DSP2833x_DefaultIsr.h + +../../f2833x/common/include/DSP2833x_GlobalPrototypes.h + +../../f2833x/common/include/DSP2833x_I2c_defines.h + +../../f2833x/headers/include/DSP2833x_Adc.h + +../../f2833x/headers/include/DSP2833x_CpuTimers.h + +../../f2833x/headers/include/DSP2833x_DMA.h + +../../f2833x/headers/include/DSP2833x_DevEmu.h + +../../f2833x/headers/include/DSP2833x_Device.h +DSP2833x_Adc.h +../../f2833x/headers/include/DSP2833x_Adc.h +DSP2833x_DevEmu.h +../../f2833x/headers/include/DSP2833x_DevEmu.h +DSP2833x_CpuTimers.h +../../f2833x/headers/include/DSP2833x_CpuTimers.h +DSP2833x_ECan.h +../../f2833x/headers/include/DSP2833x_ECan.h +DSP2833x_ECap.h +../../f2833x/headers/include/DSP2833x_ECap.h +DSP2833x_DMA.h +../../f2833x/headers/include/DSP2833x_DMA.h +DSP2833x_EPwm.h +../../f2833x/headers/include/DSP2833x_EPwm.h +DSP2833x_EQep.h +../../f2833x/headers/include/DSP2833x_EQep.h +DSP2833x_Gpio.h +../../f2833x/headers/include/DSP2833x_Gpio.h +DSP2833x_I2c.h +../../f2833x/headers/include/DSP2833x_I2c.h +DSP2833x_Mcbsp.h +../../f2833x/headers/include/DSP2833x_Mcbsp.h +DSP2833x_PieCtrl.h +../../f2833x/headers/include/DSP2833x_PieCtrl.h +DSP2833x_PieVect.h +../../f2833x/headers/include/DSP2833x_PieVect.h +DSP2833x_Spi.h +../../f2833x/headers/include/DSP2833x_Spi.h +DSP2833x_Sci.h +../../f2833x/headers/include/DSP2833x_Sci.h +DSP2833x_SysCtrl.h +../../f2833x/headers/include/DSP2833x_SysCtrl.h +DSP2833x_XIntrupt.h +../../f2833x/headers/include/DSP2833x_XIntrupt.h +DSP2833x_Xintf.h +../../f2833x/headers/include/DSP2833x_Xintf.h + +../../f2833x/headers/include/DSP2833x_ECan.h + +../../f2833x/headers/include/DSP2833x_ECap.h + +../../f2833x/headers/include/DSP2833x_EPwm.h + +../../f2833x/headers/include/DSP2833x_EQep.h + +../../f2833x/headers/include/DSP2833x_Gpio.h + +../../f2833x/headers/include/DSP2833x_I2c.h + +../../f2833x/headers/include/DSP2833x_Mcbsp.h + +../../f2833x/headers/include/DSP2833x_PieCtrl.h + +../../f2833x/headers/include/DSP2833x_PieVect.h + +../../f2833x/headers/include/DSP2833x_Sci.h + +../../f2833x/headers/include/DSP2833x_Spi.h + +../../f2833x/headers/include/DSP2833x_SysCtrl.h + +../../f2833x/headers/include/DSP2833x_XIntrupt.h + +../../f2833x/headers/include/DSP2833x_Xintf.h + +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c +DSP2833x_Device.h +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_Device.h +DSP2833x_Examples.h +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_Examples.h + +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c +DSP2833x_Device.h +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_Device.h +DSP2833x_Examples.h +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_Examples.h + +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c +DSP2833x_Device.h +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_Device.h +DSP2833x_Examples.h +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_Examples.h + +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c +DSP2833x_Device.h +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_Device.h +DSP2833x_Examples.h +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_Examples.h + +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c +DSP2833x_Device.h +/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_Device.h + diff --git a/build/Debug/CMakeFiles/test_project.dir/CXX.includecache b/build/Debug/CMakeFiles/test_project.dir/CXX.includecache new file mode 100644 index 0000000..78ac703 --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/CXX.includecache @@ -0,0 +1,114 @@ +#IncludeRegexLine: ^[ ]*[#%][ ]*(include|import)[ ]*[<"]([^">]+)([">]) + +#IncludeRegexScan: ^.*$ + +#IncludeRegexComplain: ^$ + +#IncludeRegexTransform: + +../../f2833x/common/include/DSP2833x_DefaultIsr.h + +../../f2833x/common/include/DSP2833x_Dma_defines.h + +../../f2833x/common/include/DSP2833x_EPwm_defines.h + +../../f2833x/common/include/DSP2833x_Examples.h +DSP2833x_GlobalPrototypes.h +../../f2833x/common/include/DSP2833x_GlobalPrototypes.h +DSP2833x_EPwm_defines.h +../../f2833x/common/include/DSP2833x_EPwm_defines.h +DSP2833x_Dma_defines.h +../../f2833x/common/include/DSP2833x_Dma_defines.h +DSP2833x_I2c_defines.h +../../f2833x/common/include/DSP2833x_I2c_defines.h +DSP2833x_DefaultIsr.h +../../f2833x/common/include/DSP2833x_DefaultIsr.h + +../../f2833x/common/include/DSP2833x_GlobalPrototypes.h + +../../f2833x/common/include/DSP2833x_I2c_defines.h + +../../f2833x/common/include/DSP28x_Project.h +DSP2833x_Device.h +../../f2833x/common/include/DSP2833x_Device.h +DSP2833x_Examples.h +../../f2833x/common/include/DSP2833x_Examples.h + +../../f2833x/headers/include/DSP2833x_Adc.h + +../../f2833x/headers/include/DSP2833x_CpuTimers.h + +../../f2833x/headers/include/DSP2833x_DMA.h + +../../f2833x/headers/include/DSP2833x_DevEmu.h + +../../f2833x/headers/include/DSP2833x_Device.h +DSP2833x_Adc.h +../../f2833x/headers/include/DSP2833x_Adc.h +DSP2833x_DevEmu.h +../../f2833x/headers/include/DSP2833x_DevEmu.h +DSP2833x_CpuTimers.h +../../f2833x/headers/include/DSP2833x_CpuTimers.h +DSP2833x_ECan.h +../../f2833x/headers/include/DSP2833x_ECan.h +DSP2833x_ECap.h +../../f2833x/headers/include/DSP2833x_ECap.h +DSP2833x_DMA.h +../../f2833x/headers/include/DSP2833x_DMA.h +DSP2833x_EPwm.h +../../f2833x/headers/include/DSP2833x_EPwm.h +DSP2833x_EQep.h +../../f2833x/headers/include/DSP2833x_EQep.h +DSP2833x_Gpio.h +../../f2833x/headers/include/DSP2833x_Gpio.h +DSP2833x_I2c.h +../../f2833x/headers/include/DSP2833x_I2c.h +DSP2833x_Mcbsp.h +../../f2833x/headers/include/DSP2833x_Mcbsp.h +DSP2833x_PieCtrl.h +../../f2833x/headers/include/DSP2833x_PieCtrl.h +DSP2833x_PieVect.h +../../f2833x/headers/include/DSP2833x_PieVect.h +DSP2833x_Spi.h +../../f2833x/headers/include/DSP2833x_Spi.h +DSP2833x_Sci.h +../../f2833x/headers/include/DSP2833x_Sci.h +DSP2833x_SysCtrl.h +../../f2833x/headers/include/DSP2833x_SysCtrl.h +DSP2833x_XIntrupt.h +../../f2833x/headers/include/DSP2833x_XIntrupt.h +DSP2833x_Xintf.h +../../f2833x/headers/include/DSP2833x_Xintf.h + +../../f2833x/headers/include/DSP2833x_ECan.h + +../../f2833x/headers/include/DSP2833x_ECap.h + +../../f2833x/headers/include/DSP2833x_EPwm.h + +../../f2833x/headers/include/DSP2833x_EQep.h + +../../f2833x/headers/include/DSP2833x_Gpio.h + +../../f2833x/headers/include/DSP2833x_I2c.h + +../../f2833x/headers/include/DSP2833x_Mcbsp.h + +../../f2833x/headers/include/DSP2833x_PieCtrl.h + +../../f2833x/headers/include/DSP2833x_PieVect.h + +../../f2833x/headers/include/DSP2833x_Sci.h + +../../f2833x/headers/include/DSP2833x_Spi.h + +../../f2833x/headers/include/DSP2833x_SysCtrl.h + +../../f2833x/headers/include/DSP2833x_XIntrupt.h + +../../f2833x/headers/include/DSP2833x_Xintf.h + +/home/lobov/workspace/ccs12.5/cmake_test/main.cpp +DSP28x_Project.h +/home/lobov/workspace/ccs12.5/cmake_test/DSP28x_Project.h + diff --git a/build/Debug/CMakeFiles/test_project.dir/DependInfo.cmake b/build/Debug/CMakeFiles/test_project.dir/DependInfo.cmake new file mode 100644 index 0000000..cdf4f56 --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/DependInfo.cmake @@ -0,0 +1,49 @@ + +# Consider dependencies only in project. +set(CMAKE_DEPENDS_IN_PROJECT_ONLY OFF) + +# The set of languages for which implicit dependencies are needed: +set(CMAKE_DEPENDS_LANGUAGES + "C" + "CXX" + ) +# The set of files for implicit dependencies of each language: +set(CMAKE_DEPENDS_CHECK_C + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o" + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o" + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o" + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o" + "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c" "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o" + ) +set(CMAKE_C_COMPILER_ID "TI") + +# The include file search paths: +set(CMAKE_C_TARGET_INCLUDE_PATH + "." + "../.././f2833x" + "../.././f2833x/common/include" + "../.././f2833x/headers/include" + ) +set(CMAKE_DEPENDS_CHECK_CXX + "/home/lobov/workspace/ccs12.5/cmake_test/main.cpp" "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/test_project.dir/main.cpp.o" + ) +set(CMAKE_CXX_COMPILER_ID "TI") + +# The include file search paths: +set(CMAKE_CXX_TARGET_INCLUDE_PATH + "." + "../.././f2833x" + "../.././f2833x/common/include" + "../.././f2833x/headers/include" + ) + +# The set of dependency files which are needed: +set(CMAKE_DEPENDS_DEPENDENCY_FILES + ) + +# Targets to which this target links. +set(CMAKE_TARGET_LINKED_INFO_FILES + ) + +# Fortran module output directory. +set(CMAKE_Fortran_TARGET_MODULE_DIR "") diff --git a/build/Debug/CMakeFiles/test_project.dir/build.make b/build/Debug/CMakeFiles/test_project.dir/build.make new file mode 100644 index 0000000..19ad1b3 --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/build.make @@ -0,0 +1,184 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# Delete rule output on recipe failure. +.DELETE_ON_ERROR: + +#============================================================================= +# Special targets provided by cmake. + +# Disable implicit rules so canonical targets will work. +.SUFFIXES: + +# Disable VCS-based implicit rules. +% : %,v + +# Disable VCS-based implicit rules. +% : RCS/% + +# Disable VCS-based implicit rules. +% : RCS/%,v + +# Disable VCS-based implicit rules. +% : SCCS/s.% + +# Disable VCS-based implicit rules. +% : s.% + +.SUFFIXES: .hpux_make_needs_suffix_list + +# Command-line flag to silence nested $(MAKE). +$(VERBOSE)MAKESILENT = -s + +#Suppress display of executed commands. +$(VERBOSE).SILENT: + +# A target that is always out of date. +cmake_force: +.PHONY : cmake_force + +#============================================================================= +# Set environment variables for the build. + +# The shell in which to execute make rules. +SHELL = /bin/sh + +# The CMake executable. +CMAKE_COMMAND = /usr/bin/cmake + +# The command to remove a file. +RM = /usr/bin/cmake -E rm -f + +# Escaping for special characters. +EQUALS = = + +# The top-level source directory on which CMake was run. +CMAKE_SOURCE_DIR = /home/lobov/workspace/ccs12.5/cmake_test + +# The top-level build directory on which CMake was run. +CMAKE_BINARY_DIR = /home/lobov/workspace/ccs12.5/cmake_test/build/Debug + +# Include any dependencies generated for this target. +include CMakeFiles/test_project.dir/depend.make +# Include any dependencies generated by the compiler for this target. +include CMakeFiles/test_project.dir/compiler_depend.make + +# Include the progress variables for this target. +include CMakeFiles/test_project.dir/progress.make + +# Include the compile flags for this target's objects. +include CMakeFiles/test_project.dir/flags.make + +CMakeFiles/test_project.dir/main.cpp.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/main.cpp.o: ../../main.cpp + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles --progress-num=$(CMAKE_PROGRESS_1) "Building CXX object CMakeFiles/test_project.dir/main.cpp.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/main.cpp $(CXX_DEFINES) $(CXX_INCLUDES) $(CXX_FLAGS) --output_file=CMakeFiles/test_project.dir/main.cpp.o + +CMakeFiles/test_project.dir/main.cpp.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing CXX source to CMakeFiles/test_project.dir/main.cpp.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/main.cpp $(CXX_DEFINES) $(CXX_INCLUDES) $(CXX_FLAGS) --output_file=CMakeFiles/test_project.dir/main.cpp.i + +CMakeFiles/test_project.dir/main.cpp.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling CXX source to assembly CMakeFiles/test_project.dir/main.cpp.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/main.cpp $(CXX_DEFINES) $(CXX_INCLUDES) $(CXX_FLAGS) --output_file=CMakeFiles/test_project.dir/main.cpp.s + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o: ../../f2833x/common/source/DSP2833x_DefaultIsr.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles --progress-num=$(CMAKE_PROGRESS_2) "Building C object CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.i + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.s + +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o: ../../f2833x/headers/source/DSP2833x_GlobalVariableDefs.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles --progress-num=$(CMAKE_PROGRESS_3) "Building C object CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o + +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i + +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o: ../../f2833x/common/source/DSP2833x_PieCtrl.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles --progress-num=$(CMAKE_PROGRESS_4) "Building C object CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.i + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.s + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o: ../../f2833x/common/source/DSP2833x_PieVect.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles --progress-num=$(CMAKE_PROGRESS_5) "Building C object CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.i + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.s + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o: CMakeFiles/test_project.dir/flags.make +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o: ../../f2833x/common/source/DSP2833x_SysCtrl.c + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles --progress-num=$(CMAKE_PROGRESS_6) "Building C object CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.i: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Preprocessing C source to CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.i" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --preproc_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.i + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.s: cmake_force + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green "Compiling C source to assembly CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.s" + /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --skip_assembler --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c $(C_DEFINES) $(C_INCLUDES) $(C_FLAGS) --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.s + +# Object files for target test_project +test_project_OBJECTS = \ +"CMakeFiles/test_project.dir/main.cpp.o" \ +"CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o" \ +"CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o" \ +"CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o" \ +"CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o" \ +"CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o" + +# External object files for target test_project +test_project_EXTERNAL_OBJECTS = + +test_project: CMakeFiles/test_project.dir/main.cpp.o +test_project: CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o +test_project: CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o +test_project: CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o +test_project: CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o +test_project: CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o +test_project: CMakeFiles/test_project.dir/build.make +test_project: CMakeFiles/test_project.dir/link.txt + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --bold --progress-dir=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles --progress-num=$(CMAKE_PROGRESS_7) "Linking CXX executable test_project" + $(CMAKE_COMMAND) -E cmake_link_script CMakeFiles/test_project.dir/link.txt --verbose=$(VERBOSE) + +# Rule to build all files generated by this target. +CMakeFiles/test_project.dir/build: test_project +.PHONY : CMakeFiles/test_project.dir/build + +CMakeFiles/test_project.dir/clean: + $(CMAKE_COMMAND) -P CMakeFiles/test_project.dir/cmake_clean.cmake +.PHONY : CMakeFiles/test_project.dir/clean + +CMakeFiles/test_project.dir/depend: + cd /home/lobov/workspace/ccs12.5/cmake_test/build/Debug && $(CMAKE_COMMAND) -E cmake_depends "Unix Makefiles" /home/lobov/workspace/ccs12.5/cmake_test /home/lobov/workspace/ccs12.5/cmake_test /home/lobov/workspace/ccs12.5/cmake_test/build/Debug /home/lobov/workspace/ccs12.5/cmake_test/build/Debug /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles/test_project.dir/DependInfo.cmake --color=$(COLOR) +.PHONY : CMakeFiles/test_project.dir/depend + diff --git a/build/Debug/CMakeFiles/test_project.dir/cmake_clean.cmake b/build/Debug/CMakeFiles/test_project.dir/cmake_clean.cmake new file mode 100644 index 0000000..f70d891 --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/cmake_clean.cmake @@ -0,0 +1,15 @@ +file(REMOVE_RECURSE + "CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o" + "CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o" + "CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o" + "CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o" + "CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o" + "CMakeFiles/test_project.dir/main.cpp.o" + "test_project" + "test_project.pdb" +) + +# Per-language clean rules from dependency scanning. +foreach(lang C CXX) + include(CMakeFiles/test_project.dir/cmake_clean_${lang}.cmake OPTIONAL) +endforeach() diff --git a/build/Debug/CMakeFiles/test_project.dir/compiler_depend.make b/build/Debug/CMakeFiles/test_project.dir/compiler_depend.make new file mode 100644 index 0000000..bbcff8b --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/compiler_depend.make @@ -0,0 +1,2 @@ +# Empty compiler generated dependencies file for test_project. +# This may be replaced when dependencies are built. diff --git a/build/Debug/CMakeFiles/test_project.dir/compiler_depend.ts b/build/Debug/CMakeFiles/test_project.dir/compiler_depend.ts new file mode 100644 index 0000000..0e5a7fe --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/compiler_depend.ts @@ -0,0 +1,2 @@ +# CMAKE generated file: DO NOT EDIT! +# Timestamp file for compiler generated dependencies management for test_project. diff --git a/build/Debug/CMakeFiles/test_project.dir/depend.internal b/build/Debug/CMakeFiles/test_project.dir/depend.internal new file mode 100644 index 0000000..bd5a632 --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/depend.internal @@ -0,0 +1,160 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o + ../../f2833x/common/include/DSP2833x_DefaultIsr.h + ../../f2833x/common/include/DSP2833x_Dma_defines.h + ../../f2833x/common/include/DSP2833x_EPwm_defines.h + ../../f2833x/common/include/DSP2833x_Examples.h + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h + ../../f2833x/common/include/DSP2833x_I2c_defines.h + ../../f2833x/headers/include/DSP2833x_Adc.h + ../../f2833x/headers/include/DSP2833x_CpuTimers.h + ../../f2833x/headers/include/DSP2833x_DMA.h + ../../f2833x/headers/include/DSP2833x_DevEmu.h + ../../f2833x/headers/include/DSP2833x_Device.h + ../../f2833x/headers/include/DSP2833x_ECan.h + ../../f2833x/headers/include/DSP2833x_ECap.h + ../../f2833x/headers/include/DSP2833x_EPwm.h + ../../f2833x/headers/include/DSP2833x_EQep.h + ../../f2833x/headers/include/DSP2833x_Gpio.h + ../../f2833x/headers/include/DSP2833x_I2c.h + ../../f2833x/headers/include/DSP2833x_Mcbsp.h + ../../f2833x/headers/include/DSP2833x_PieCtrl.h + ../../f2833x/headers/include/DSP2833x_PieVect.h + ../../f2833x/headers/include/DSP2833x_Sci.h + ../../f2833x/headers/include/DSP2833x_Spi.h + ../../f2833x/headers/include/DSP2833x_SysCtrl.h + ../../f2833x/headers/include/DSP2833x_XIntrupt.h + ../../f2833x/headers/include/DSP2833x_Xintf.h + /home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o + ../../f2833x/common/include/DSP2833x_DefaultIsr.h + ../../f2833x/common/include/DSP2833x_Dma_defines.h + ../../f2833x/common/include/DSP2833x_EPwm_defines.h + ../../f2833x/common/include/DSP2833x_Examples.h + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h + ../../f2833x/common/include/DSP2833x_I2c_defines.h + ../../f2833x/headers/include/DSP2833x_Adc.h + ../../f2833x/headers/include/DSP2833x_CpuTimers.h + ../../f2833x/headers/include/DSP2833x_DMA.h + ../../f2833x/headers/include/DSP2833x_DevEmu.h + ../../f2833x/headers/include/DSP2833x_Device.h + ../../f2833x/headers/include/DSP2833x_ECan.h + ../../f2833x/headers/include/DSP2833x_ECap.h + ../../f2833x/headers/include/DSP2833x_EPwm.h + ../../f2833x/headers/include/DSP2833x_EQep.h + ../../f2833x/headers/include/DSP2833x_Gpio.h + ../../f2833x/headers/include/DSP2833x_I2c.h + ../../f2833x/headers/include/DSP2833x_Mcbsp.h + ../../f2833x/headers/include/DSP2833x_PieCtrl.h + ../../f2833x/headers/include/DSP2833x_PieVect.h + ../../f2833x/headers/include/DSP2833x_Sci.h + ../../f2833x/headers/include/DSP2833x_Spi.h + ../../f2833x/headers/include/DSP2833x_SysCtrl.h + ../../f2833x/headers/include/DSP2833x_XIntrupt.h + ../../f2833x/headers/include/DSP2833x_Xintf.h + /home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o + ../../f2833x/common/include/DSP2833x_DefaultIsr.h + ../../f2833x/common/include/DSP2833x_Dma_defines.h + ../../f2833x/common/include/DSP2833x_EPwm_defines.h + ../../f2833x/common/include/DSP2833x_Examples.h + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h + ../../f2833x/common/include/DSP2833x_I2c_defines.h + ../../f2833x/headers/include/DSP2833x_Adc.h + ../../f2833x/headers/include/DSP2833x_CpuTimers.h + ../../f2833x/headers/include/DSP2833x_DMA.h + ../../f2833x/headers/include/DSP2833x_DevEmu.h + ../../f2833x/headers/include/DSP2833x_Device.h + ../../f2833x/headers/include/DSP2833x_ECan.h + ../../f2833x/headers/include/DSP2833x_ECap.h + ../../f2833x/headers/include/DSP2833x_EPwm.h + ../../f2833x/headers/include/DSP2833x_EQep.h + ../../f2833x/headers/include/DSP2833x_Gpio.h + ../../f2833x/headers/include/DSP2833x_I2c.h + ../../f2833x/headers/include/DSP2833x_Mcbsp.h + ../../f2833x/headers/include/DSP2833x_PieCtrl.h + ../../f2833x/headers/include/DSP2833x_PieVect.h + ../../f2833x/headers/include/DSP2833x_Sci.h + ../../f2833x/headers/include/DSP2833x_Spi.h + ../../f2833x/headers/include/DSP2833x_SysCtrl.h + ../../f2833x/headers/include/DSP2833x_XIntrupt.h + ../../f2833x/headers/include/DSP2833x_Xintf.h + /home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o + ../../f2833x/common/include/DSP2833x_DefaultIsr.h + ../../f2833x/common/include/DSP2833x_Dma_defines.h + ../../f2833x/common/include/DSP2833x_EPwm_defines.h + ../../f2833x/common/include/DSP2833x_Examples.h + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h + ../../f2833x/common/include/DSP2833x_I2c_defines.h + ../../f2833x/headers/include/DSP2833x_Adc.h + ../../f2833x/headers/include/DSP2833x_CpuTimers.h + ../../f2833x/headers/include/DSP2833x_DMA.h + ../../f2833x/headers/include/DSP2833x_DevEmu.h + ../../f2833x/headers/include/DSP2833x_Device.h + ../../f2833x/headers/include/DSP2833x_ECan.h + ../../f2833x/headers/include/DSP2833x_ECap.h + ../../f2833x/headers/include/DSP2833x_EPwm.h + ../../f2833x/headers/include/DSP2833x_EQep.h + ../../f2833x/headers/include/DSP2833x_Gpio.h + ../../f2833x/headers/include/DSP2833x_I2c.h + ../../f2833x/headers/include/DSP2833x_Mcbsp.h + ../../f2833x/headers/include/DSP2833x_PieCtrl.h + ../../f2833x/headers/include/DSP2833x_PieVect.h + ../../f2833x/headers/include/DSP2833x_Sci.h + ../../f2833x/headers/include/DSP2833x_Spi.h + ../../f2833x/headers/include/DSP2833x_SysCtrl.h + ../../f2833x/headers/include/DSP2833x_XIntrupt.h + ../../f2833x/headers/include/DSP2833x_Xintf.h + /home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o + ../../f2833x/headers/include/DSP2833x_Adc.h + ../../f2833x/headers/include/DSP2833x_CpuTimers.h + ../../f2833x/headers/include/DSP2833x_DMA.h + ../../f2833x/headers/include/DSP2833x_DevEmu.h + ../../f2833x/headers/include/DSP2833x_Device.h + ../../f2833x/headers/include/DSP2833x_ECan.h + ../../f2833x/headers/include/DSP2833x_ECap.h + ../../f2833x/headers/include/DSP2833x_EPwm.h + ../../f2833x/headers/include/DSP2833x_EQep.h + ../../f2833x/headers/include/DSP2833x_Gpio.h + ../../f2833x/headers/include/DSP2833x_I2c.h + ../../f2833x/headers/include/DSP2833x_Mcbsp.h + ../../f2833x/headers/include/DSP2833x_PieCtrl.h + ../../f2833x/headers/include/DSP2833x_PieVect.h + ../../f2833x/headers/include/DSP2833x_Sci.h + ../../f2833x/headers/include/DSP2833x_Spi.h + ../../f2833x/headers/include/DSP2833x_SysCtrl.h + ../../f2833x/headers/include/DSP2833x_XIntrupt.h + ../../f2833x/headers/include/DSP2833x_Xintf.h + /home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c +CMakeFiles/test_project.dir/main.cpp.o + ../../f2833x/common/include/DSP2833x_DefaultIsr.h + ../../f2833x/common/include/DSP2833x_Dma_defines.h + ../../f2833x/common/include/DSP2833x_EPwm_defines.h + ../../f2833x/common/include/DSP2833x_Examples.h + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h + ../../f2833x/common/include/DSP2833x_I2c_defines.h + ../../f2833x/common/include/DSP28x_Project.h + ../../f2833x/headers/include/DSP2833x_Adc.h + ../../f2833x/headers/include/DSP2833x_CpuTimers.h + ../../f2833x/headers/include/DSP2833x_DMA.h + ../../f2833x/headers/include/DSP2833x_DevEmu.h + ../../f2833x/headers/include/DSP2833x_Device.h + ../../f2833x/headers/include/DSP2833x_ECan.h + ../../f2833x/headers/include/DSP2833x_ECap.h + ../../f2833x/headers/include/DSP2833x_EPwm.h + ../../f2833x/headers/include/DSP2833x_EQep.h + ../../f2833x/headers/include/DSP2833x_Gpio.h + ../../f2833x/headers/include/DSP2833x_I2c.h + ../../f2833x/headers/include/DSP2833x_Mcbsp.h + ../../f2833x/headers/include/DSP2833x_PieCtrl.h + ../../f2833x/headers/include/DSP2833x_PieVect.h + ../../f2833x/headers/include/DSP2833x_Sci.h + ../../f2833x/headers/include/DSP2833x_Spi.h + ../../f2833x/headers/include/DSP2833x_SysCtrl.h + ../../f2833x/headers/include/DSP2833x_XIntrupt.h + ../../f2833x/headers/include/DSP2833x_Xintf.h + /home/lobov/workspace/ccs12.5/cmake_test/main.cpp diff --git a/build/Debug/CMakeFiles/test_project.dir/depend.make b/build/Debug/CMakeFiles/test_project.dir/depend.make new file mode 100644 index 0000000..af1fff4 --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/depend.make @@ -0,0 +1,160 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o: \ + ../../f2833x/common/include/DSP2833x_DefaultIsr.h \ + ../../f2833x/common/include/DSP2833x_Dma_defines.h \ + ../../f2833x/common/include/DSP2833x_EPwm_defines.h \ + ../../f2833x/common/include/DSP2833x_Examples.h \ + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h \ + ../../f2833x/common/include/DSP2833x_I2c_defines.h \ + ../../f2833x/headers/include/DSP2833x_Adc.h \ + ../../f2833x/headers/include/DSP2833x_CpuTimers.h \ + ../../f2833x/headers/include/DSP2833x_DMA.h \ + ../../f2833x/headers/include/DSP2833x_DevEmu.h \ + ../../f2833x/headers/include/DSP2833x_Device.h \ + ../../f2833x/headers/include/DSP2833x_ECan.h \ + ../../f2833x/headers/include/DSP2833x_ECap.h \ + ../../f2833x/headers/include/DSP2833x_EPwm.h \ + ../../f2833x/headers/include/DSP2833x_EQep.h \ + ../../f2833x/headers/include/DSP2833x_Gpio.h \ + ../../f2833x/headers/include/DSP2833x_I2c.h \ + ../../f2833x/headers/include/DSP2833x_Mcbsp.h \ + ../../f2833x/headers/include/DSP2833x_PieCtrl.h \ + ../../f2833x/headers/include/DSP2833x_PieVect.h \ + ../../f2833x/headers/include/DSP2833x_Sci.h \ + ../../f2833x/headers/include/DSP2833x_Spi.h \ + ../../f2833x/headers/include/DSP2833x_SysCtrl.h \ + ../../f2833x/headers/include/DSP2833x_XIntrupt.h \ + ../../f2833x/headers/include/DSP2833x_Xintf.h \ + ../../f2833x/common/source/DSP2833x_DefaultIsr.c +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o: \ + ../../f2833x/common/include/DSP2833x_DefaultIsr.h \ + ../../f2833x/common/include/DSP2833x_Dma_defines.h \ + ../../f2833x/common/include/DSP2833x_EPwm_defines.h \ + ../../f2833x/common/include/DSP2833x_Examples.h \ + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h \ + ../../f2833x/common/include/DSP2833x_I2c_defines.h \ + ../../f2833x/headers/include/DSP2833x_Adc.h \ + ../../f2833x/headers/include/DSP2833x_CpuTimers.h \ + ../../f2833x/headers/include/DSP2833x_DMA.h \ + ../../f2833x/headers/include/DSP2833x_DevEmu.h \ + ../../f2833x/headers/include/DSP2833x_Device.h \ + ../../f2833x/headers/include/DSP2833x_ECan.h \ + ../../f2833x/headers/include/DSP2833x_ECap.h \ + ../../f2833x/headers/include/DSP2833x_EPwm.h \ + ../../f2833x/headers/include/DSP2833x_EQep.h \ + ../../f2833x/headers/include/DSP2833x_Gpio.h \ + ../../f2833x/headers/include/DSP2833x_I2c.h \ + ../../f2833x/headers/include/DSP2833x_Mcbsp.h \ + ../../f2833x/headers/include/DSP2833x_PieCtrl.h \ + ../../f2833x/headers/include/DSP2833x_PieVect.h \ + ../../f2833x/headers/include/DSP2833x_Sci.h \ + ../../f2833x/headers/include/DSP2833x_Spi.h \ + ../../f2833x/headers/include/DSP2833x_SysCtrl.h \ + ../../f2833x/headers/include/DSP2833x_XIntrupt.h \ + ../../f2833x/headers/include/DSP2833x_Xintf.h \ + ../../f2833x/common/source/DSP2833x_PieCtrl.c +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o: \ + ../../f2833x/common/include/DSP2833x_DefaultIsr.h \ + ../../f2833x/common/include/DSP2833x_Dma_defines.h \ + ../../f2833x/common/include/DSP2833x_EPwm_defines.h \ + ../../f2833x/common/include/DSP2833x_Examples.h \ + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h \ + ../../f2833x/common/include/DSP2833x_I2c_defines.h \ + ../../f2833x/headers/include/DSP2833x_Adc.h \ + ../../f2833x/headers/include/DSP2833x_CpuTimers.h \ + ../../f2833x/headers/include/DSP2833x_DMA.h \ + ../../f2833x/headers/include/DSP2833x_DevEmu.h \ + ../../f2833x/headers/include/DSP2833x_Device.h \ + ../../f2833x/headers/include/DSP2833x_ECan.h \ + ../../f2833x/headers/include/DSP2833x_ECap.h \ + ../../f2833x/headers/include/DSP2833x_EPwm.h \ + ../../f2833x/headers/include/DSP2833x_EQep.h \ + ../../f2833x/headers/include/DSP2833x_Gpio.h \ + ../../f2833x/headers/include/DSP2833x_I2c.h \ + ../../f2833x/headers/include/DSP2833x_Mcbsp.h \ + ../../f2833x/headers/include/DSP2833x_PieCtrl.h \ + ../../f2833x/headers/include/DSP2833x_PieVect.h \ + ../../f2833x/headers/include/DSP2833x_Sci.h \ + ../../f2833x/headers/include/DSP2833x_Spi.h \ + ../../f2833x/headers/include/DSP2833x_SysCtrl.h \ + ../../f2833x/headers/include/DSP2833x_XIntrupt.h \ + ../../f2833x/headers/include/DSP2833x_Xintf.h \ + ../../f2833x/common/source/DSP2833x_PieVect.c +CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o: \ + ../../f2833x/common/include/DSP2833x_DefaultIsr.h \ + ../../f2833x/common/include/DSP2833x_Dma_defines.h \ + ../../f2833x/common/include/DSP2833x_EPwm_defines.h \ + ../../f2833x/common/include/DSP2833x_Examples.h \ + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h \ + ../../f2833x/common/include/DSP2833x_I2c_defines.h \ + ../../f2833x/headers/include/DSP2833x_Adc.h \ + ../../f2833x/headers/include/DSP2833x_CpuTimers.h \ + ../../f2833x/headers/include/DSP2833x_DMA.h \ + ../../f2833x/headers/include/DSP2833x_DevEmu.h \ + ../../f2833x/headers/include/DSP2833x_Device.h \ + ../../f2833x/headers/include/DSP2833x_ECan.h \ + ../../f2833x/headers/include/DSP2833x_ECap.h \ + ../../f2833x/headers/include/DSP2833x_EPwm.h \ + ../../f2833x/headers/include/DSP2833x_EQep.h \ + ../../f2833x/headers/include/DSP2833x_Gpio.h \ + ../../f2833x/headers/include/DSP2833x_I2c.h \ + ../../f2833x/headers/include/DSP2833x_Mcbsp.h \ + ../../f2833x/headers/include/DSP2833x_PieCtrl.h \ + ../../f2833x/headers/include/DSP2833x_PieVect.h \ + ../../f2833x/headers/include/DSP2833x_Sci.h \ + ../../f2833x/headers/include/DSP2833x_Spi.h \ + ../../f2833x/headers/include/DSP2833x_SysCtrl.h \ + ../../f2833x/headers/include/DSP2833x_XIntrupt.h \ + ../../f2833x/headers/include/DSP2833x_Xintf.h \ + ../../f2833x/common/source/DSP2833x_SysCtrl.c +CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o: \ + ../../f2833x/headers/include/DSP2833x_Adc.h \ + ../../f2833x/headers/include/DSP2833x_CpuTimers.h \ + ../../f2833x/headers/include/DSP2833x_DMA.h \ + ../../f2833x/headers/include/DSP2833x_DevEmu.h \ + ../../f2833x/headers/include/DSP2833x_Device.h \ + ../../f2833x/headers/include/DSP2833x_ECan.h \ + ../../f2833x/headers/include/DSP2833x_ECap.h \ + ../../f2833x/headers/include/DSP2833x_EPwm.h \ + ../../f2833x/headers/include/DSP2833x_EQep.h \ + ../../f2833x/headers/include/DSP2833x_Gpio.h \ + ../../f2833x/headers/include/DSP2833x_I2c.h \ + ../../f2833x/headers/include/DSP2833x_Mcbsp.h \ + ../../f2833x/headers/include/DSP2833x_PieCtrl.h \ + ../../f2833x/headers/include/DSP2833x_PieVect.h \ + ../../f2833x/headers/include/DSP2833x_Sci.h \ + ../../f2833x/headers/include/DSP2833x_Spi.h \ + ../../f2833x/headers/include/DSP2833x_SysCtrl.h \ + ../../f2833x/headers/include/DSP2833x_XIntrupt.h \ + ../../f2833x/headers/include/DSP2833x_Xintf.h \ + ../../f2833x/headers/source/DSP2833x_GlobalVariableDefs.c +CMakeFiles/test_project.dir/main.cpp.o: \ + ../../f2833x/common/include/DSP2833x_DefaultIsr.h \ + ../../f2833x/common/include/DSP2833x_Dma_defines.h \ + ../../f2833x/common/include/DSP2833x_EPwm_defines.h \ + ../../f2833x/common/include/DSP2833x_Examples.h \ + ../../f2833x/common/include/DSP2833x_GlobalPrototypes.h \ + ../../f2833x/common/include/DSP2833x_I2c_defines.h \ + ../../f2833x/common/include/DSP28x_Project.h \ + ../../f2833x/headers/include/DSP2833x_Adc.h \ + ../../f2833x/headers/include/DSP2833x_CpuTimers.h \ + ../../f2833x/headers/include/DSP2833x_DMA.h \ + ../../f2833x/headers/include/DSP2833x_DevEmu.h \ + ../../f2833x/headers/include/DSP2833x_Device.h \ + ../../f2833x/headers/include/DSP2833x_ECan.h \ + ../../f2833x/headers/include/DSP2833x_ECap.h \ + ../../f2833x/headers/include/DSP2833x_EPwm.h \ + ../../f2833x/headers/include/DSP2833x_EQep.h \ + ../../f2833x/headers/include/DSP2833x_Gpio.h \ + ../../f2833x/headers/include/DSP2833x_I2c.h \ + ../../f2833x/headers/include/DSP2833x_Mcbsp.h \ + ../../f2833x/headers/include/DSP2833x_PieCtrl.h \ + ../../f2833x/headers/include/DSP2833x_PieVect.h \ + ../../f2833x/headers/include/DSP2833x_Sci.h \ + ../../f2833x/headers/include/DSP2833x_Spi.h \ + ../../f2833x/headers/include/DSP2833x_SysCtrl.h \ + ../../f2833x/headers/include/DSP2833x_XIntrupt.h \ + ../../f2833x/headers/include/DSP2833x_Xintf.h \ + ../../main.cpp diff --git a/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o b/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o new file mode 100644 index 0000000..3d3615f Binary files /dev/null and b/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o differ diff --git a/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o b/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o new file mode 100644 index 0000000..62a436d Binary files /dev/null and b/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o differ diff --git a/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o b/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o new file mode 100644 index 0000000..e886b1b Binary files /dev/null and b/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o differ diff --git a/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o b/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o new file mode 100644 index 0000000..b66ce7f Binary files /dev/null and b/build/Debug/CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o differ diff --git a/build/Debug/CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o b/build/Debug/CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o new file mode 100644 index 0000000..cb21b4d Binary files /dev/null and b/build/Debug/CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o differ diff --git a/build/Debug/CMakeFiles/test_project.dir/flags.make b/build/Debug/CMakeFiles/test_project.dir/flags.make new file mode 100644 index 0000000..74807ee --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/flags.make @@ -0,0 +1,17 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# compile C with /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 +# compile CXX with /home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 +C_DEFINES = + +C_INCLUDES = --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include + +C_FLAGS = -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE "--define=bmin='0.397824735f'" "--define=amax='0.960433870f'" --float_operations_allowed=32 --printf_support=minimal --include_path=\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\" --include_path=\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\" + +CXX_DEFINES = + +CXX_INCLUDES = --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include + +CXX_FLAGS = -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE "--define=bmin='0.397824735f'" "--define=amax='0.960433870f'" --float_operations_allowed=32 --printf_support=minimal --include_path=\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\" --include_path=\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\" + diff --git a/build/Debug/CMakeFiles/test_project.dir/link.txt b/build/Debug/CMakeFiles/test_project.dir/link.txt new file mode 100644 index 0000000..b01a999 --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/link.txt @@ -0,0 +1 @@ +/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --run_linker --output_file=test_project --map_file=test_project.map CMakeFiles/test_project.dir/main.cpp.o CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o diff --git a/build/Debug/CMakeFiles/test_project.dir/main.cpp.o b/build/Debug/CMakeFiles/test_project.dir/main.cpp.o new file mode 100644 index 0000000..6783657 Binary files /dev/null and b/build/Debug/CMakeFiles/test_project.dir/main.cpp.o differ diff --git a/build/Debug/CMakeFiles/test_project.dir/progress.make b/build/Debug/CMakeFiles/test_project.dir/progress.make new file mode 100644 index 0000000..2f82315 --- /dev/null +++ b/build/Debug/CMakeFiles/test_project.dir/progress.make @@ -0,0 +1,8 @@ +CMAKE_PROGRESS_1 = 1 +CMAKE_PROGRESS_2 = 2 +CMAKE_PROGRESS_3 = 3 +CMAKE_PROGRESS_4 = 4 +CMAKE_PROGRESS_5 = 5 +CMAKE_PROGRESS_6 = 6 +CMAKE_PROGRESS_7 = 7 + diff --git a/build/Debug/Makefile b/build/Debug/Makefile new file mode 100644 index 0000000..4862d00 --- /dev/null +++ b/build/Debug/Makefile @@ -0,0 +1,316 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# Default target executed when no arguments are given to make. +default_target: all +.PHONY : default_target + +# Allow only one "make -f Makefile2" at a time, but pass parallelism. +.NOTPARALLEL: + +#============================================================================= +# Special targets provided by cmake. + +# Disable implicit rules so canonical targets will work. +.SUFFIXES: + +# Disable VCS-based implicit rules. +% : %,v + +# Disable VCS-based implicit rules. +% : RCS/% + +# Disable VCS-based implicit rules. +% : RCS/%,v + +# Disable VCS-based implicit rules. +% : SCCS/s.% + +# Disable VCS-based implicit rules. +% : s.% + +.SUFFIXES: .hpux_make_needs_suffix_list + +# Command-line flag to silence nested $(MAKE). +$(VERBOSE)MAKESILENT = -s + +#Suppress display of executed commands. +$(VERBOSE).SILENT: + +# A target that is always out of date. +cmake_force: +.PHONY : cmake_force + +#============================================================================= +# Set environment variables for the build. + +# The shell in which to execute make rules. +SHELL = /bin/sh + +# The CMake executable. +CMAKE_COMMAND = /usr/bin/cmake + +# The command to remove a file. +RM = /usr/bin/cmake -E rm -f + +# Escaping for special characters. +EQUALS = = + +# The top-level source directory on which CMake was run. +CMAKE_SOURCE_DIR = /home/lobov/workspace/ccs12.5/cmake_test + +# The top-level build directory on which CMake was run. +CMAKE_BINARY_DIR = /home/lobov/workspace/ccs12.5/cmake_test/build/Debug + +#============================================================================= +# Targets provided globally by CMake. + +# Special rule for the target edit_cache +edit_cache: + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --cyan "No interactive CMake dialog available..." + /usr/bin/cmake -E echo No\ interactive\ CMake\ dialog\ available. +.PHONY : edit_cache + +# Special rule for the target edit_cache +edit_cache/fast: edit_cache +.PHONY : edit_cache/fast + +# Special rule for the target rebuild_cache +rebuild_cache: + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --cyan "Running CMake to regenerate build system..." + /usr/bin/cmake --regenerate-during-build -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) +.PHONY : rebuild_cache + +# Special rule for the target rebuild_cache +rebuild_cache/fast: rebuild_cache +.PHONY : rebuild_cache/fast + +# The main all target +all: cmake_check_build_system + $(CMAKE_COMMAND) -E cmake_progress_start /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles /home/lobov/workspace/ccs12.5/cmake_test/build/Debug//CMakeFiles/progress.marks + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 all + $(CMAKE_COMMAND) -E cmake_progress_start /home/lobov/workspace/ccs12.5/cmake_test/build/Debug/CMakeFiles 0 +.PHONY : all + +# The main clean target +clean: + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 clean +.PHONY : clean + +# The main clean target +clean/fast: clean +.PHONY : clean/fast + +# Prepare targets for installation. +preinstall: all + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 preinstall +.PHONY : preinstall + +# Prepare targets for installation. +preinstall/fast: + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 preinstall +.PHONY : preinstall/fast + +# clear depends +depend: + $(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 1 +.PHONY : depend + +#============================================================================= +# Target rules for targets named test_project + +# Build rule for target. +test_project: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 test_project +.PHONY : test_project + +# fast build rule for target. +test_project/fast: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/build +.PHONY : test_project/fast + +f2833x/common/source/DSP2833x_DefaultIsr.o: f2833x/common/source/DSP2833x_DefaultIsr.c.o +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.o + +# target to build an object file +f2833x/common/source/DSP2833x_DefaultIsr.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.c.o + +f2833x/common/source/DSP2833x_DefaultIsr.i: f2833x/common/source/DSP2833x_DefaultIsr.c.i +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.i + +# target to preprocess a source file +f2833x/common/source/DSP2833x_DefaultIsr.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.i +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.c.i + +f2833x/common/source/DSP2833x_DefaultIsr.s: f2833x/common/source/DSP2833x_DefaultIsr.c.s +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.s + +# target to generate assembly for a file +f2833x/common/source/DSP2833x_DefaultIsr.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.s +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.c.s + +f2833x/common/source/DSP2833x_PieCtrl.o: f2833x/common/source/DSP2833x_PieCtrl.c.o +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.o + +# target to build an object file +f2833x/common/source/DSP2833x_PieCtrl.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.c.o + +f2833x/common/source/DSP2833x_PieCtrl.i: f2833x/common/source/DSP2833x_PieCtrl.c.i +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.i + +# target to preprocess a source file +f2833x/common/source/DSP2833x_PieCtrl.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.i +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.c.i + +f2833x/common/source/DSP2833x_PieCtrl.s: f2833x/common/source/DSP2833x_PieCtrl.c.s +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.s + +# target to generate assembly for a file +f2833x/common/source/DSP2833x_PieCtrl.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.s +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.c.s + +f2833x/common/source/DSP2833x_PieVect.o: f2833x/common/source/DSP2833x_PieVect.c.o +.PHONY : f2833x/common/source/DSP2833x_PieVect.o + +# target to build an object file +f2833x/common/source/DSP2833x_PieVect.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o +.PHONY : f2833x/common/source/DSP2833x_PieVect.c.o + +f2833x/common/source/DSP2833x_PieVect.i: f2833x/common/source/DSP2833x_PieVect.c.i +.PHONY : f2833x/common/source/DSP2833x_PieVect.i + +# target to preprocess a source file +f2833x/common/source/DSP2833x_PieVect.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.i +.PHONY : f2833x/common/source/DSP2833x_PieVect.c.i + +f2833x/common/source/DSP2833x_PieVect.s: f2833x/common/source/DSP2833x_PieVect.c.s +.PHONY : f2833x/common/source/DSP2833x_PieVect.s + +# target to generate assembly for a file +f2833x/common/source/DSP2833x_PieVect.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.s +.PHONY : f2833x/common/source/DSP2833x_PieVect.c.s + +f2833x/common/source/DSP2833x_SysCtrl.o: f2833x/common/source/DSP2833x_SysCtrl.c.o +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.o + +# target to build an object file +f2833x/common/source/DSP2833x_SysCtrl.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.c.o + +f2833x/common/source/DSP2833x_SysCtrl.i: f2833x/common/source/DSP2833x_SysCtrl.c.i +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.i + +# target to preprocess a source file +f2833x/common/source/DSP2833x_SysCtrl.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.i +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.c.i + +f2833x/common/source/DSP2833x_SysCtrl.s: f2833x/common/source/DSP2833x_SysCtrl.c.s +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.s + +# target to generate assembly for a file +f2833x/common/source/DSP2833x_SysCtrl.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.s +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.c.s + +f2833x/headers/source/DSP2833x_GlobalVariableDefs.o: f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.o + +# target to build an object file +f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o + +f2833x/headers/source/DSP2833x_GlobalVariableDefs.i: f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.i + +# target to preprocess a source file +f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i + +f2833x/headers/source/DSP2833x_GlobalVariableDefs.s: f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.s + +# target to generate assembly for a file +f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s + +main.o: main.cpp.o +.PHONY : main.o + +# target to build an object file +main.cpp.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/main.cpp.o +.PHONY : main.cpp.o + +main.i: main.cpp.i +.PHONY : main.i + +# target to preprocess a source file +main.cpp.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/main.cpp.i +.PHONY : main.cpp.i + +main.s: main.cpp.s +.PHONY : main.s + +# target to generate assembly for a file +main.cpp.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/main.cpp.s +.PHONY : main.cpp.s + +# Help Target +help: + @echo "The following are some of the valid targets for this Makefile:" + @echo "... all (the default if no target is provided)" + @echo "... clean" + @echo "... depend" + @echo "... edit_cache" + @echo "... rebuild_cache" + @echo "... test_project" + @echo "... f2833x/common/source/DSP2833x_DefaultIsr.o" + @echo "... f2833x/common/source/DSP2833x_DefaultIsr.i" + @echo "... f2833x/common/source/DSP2833x_DefaultIsr.s" + @echo "... f2833x/common/source/DSP2833x_PieCtrl.o" + @echo "... f2833x/common/source/DSP2833x_PieCtrl.i" + @echo "... f2833x/common/source/DSP2833x_PieCtrl.s" + @echo "... f2833x/common/source/DSP2833x_PieVect.o" + @echo "... f2833x/common/source/DSP2833x_PieVect.i" + @echo "... f2833x/common/source/DSP2833x_PieVect.s" + @echo "... f2833x/common/source/DSP2833x_SysCtrl.o" + @echo "... f2833x/common/source/DSP2833x_SysCtrl.i" + @echo "... f2833x/common/source/DSP2833x_SysCtrl.s" + @echo "... f2833x/headers/source/DSP2833x_GlobalVariableDefs.o" + @echo "... f2833x/headers/source/DSP2833x_GlobalVariableDefs.i" + @echo "... f2833x/headers/source/DSP2833x_GlobalVariableDefs.s" + @echo "... main.o" + @echo "... main.i" + @echo "... main.s" +.PHONY : help + + + +#============================================================================= +# Special targets to cleanup operation of make. + +# Special rule to run CMake to check the build system integrity. +# No rule that depends on this can have commands that come from listfiles +# because they might be regenerated. +cmake_check_build_system: + $(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 0 +.PHONY : cmake_check_build_system + diff --git a/build/Debug/cmake_install.cmake b/build/Debug/cmake_install.cmake new file mode 100644 index 0000000..6ccc0b4 --- /dev/null +++ b/build/Debug/cmake_install.cmake @@ -0,0 +1,54 @@ +# Install script for directory: /home/lobov/workspace/ccs12.5/cmake_test + +# Set the install prefix +if(NOT DEFINED CMAKE_INSTALL_PREFIX) + set(CMAKE_INSTALL_PREFIX "/usr/local") +endif() +string(REGEX REPLACE "/$" "" CMAKE_INSTALL_PREFIX "${CMAKE_INSTALL_PREFIX}") + +# Set the install configuration name. +if(NOT DEFINED CMAKE_INSTALL_CONFIG_NAME) + if(BUILD_TYPE) + string(REGEX REPLACE "^[^A-Za-z0-9_]+" "" + CMAKE_INSTALL_CONFIG_NAME "${BUILD_TYPE}") + else() + set(CMAKE_INSTALL_CONFIG_NAME "Debug") + endif() + message(STATUS "Install configuration: \"${CMAKE_INSTALL_CONFIG_NAME}\"") +endif() + +# Set the component getting installed. +if(NOT CMAKE_INSTALL_COMPONENT) + if(COMPONENT) + message(STATUS "Install component: \"${COMPONENT}\"") + set(CMAKE_INSTALL_COMPONENT "${COMPONENT}") + else() + set(CMAKE_INSTALL_COMPONENT) + endif() +endif() + +# Install shared libraries without execute permission? +if(NOT DEFINED CMAKE_INSTALL_SO_NO_EXE) + set(CMAKE_INSTALL_SO_NO_EXE "1") +endif() + +# Is this installation the result of a crosscompile? +if(NOT DEFINED CMAKE_CROSSCOMPILING) + set(CMAKE_CROSSCOMPILING "FALSE") +endif() + +# Set default install directory permissions. +if(NOT DEFINED CMAKE_OBJDUMP) + set(CMAKE_OBJDUMP "/usr/bin/objdump") +endif() + +if(CMAKE_INSTALL_COMPONENT) + set(CMAKE_INSTALL_MANIFEST "install_manifest_${CMAKE_INSTALL_COMPONENT}.txt") +else() + set(CMAKE_INSTALL_MANIFEST "install_manifest.txt") +endif() + +string(REPLACE ";" "\n" CMAKE_INSTALL_MANIFEST_CONTENT + "${CMAKE_INSTALL_MANIFEST_FILES}") +file(WRITE "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug/${CMAKE_INSTALL_MANIFEST}" + "${CMAKE_INSTALL_MANIFEST_CONTENT}") diff --git a/build/Debug/compile_commands.json b/build/Debug/compile_commands.json new file mode 100644 index 0000000..436af6e --- /dev/null +++ b/build/Debug/compile_commands.json @@ -0,0 +1,32 @@ +[ +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/main.cpp --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/main.cpp.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/main.cpp" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build/Debug", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build/Debug --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c" +} +] \ No newline at end of file diff --git a/build/Debug/test_project b/build/Debug/test_project new file mode 100644 index 0000000..cf9c3a3 Binary files /dev/null and b/build/Debug/test_project differ diff --git a/build/Debug/test_project.map b/build/Debug/test_project.map new file mode 100644 index 0000000..fccd6b9 --- /dev/null +++ b/build/Debug/test_project.map @@ -0,0 +1,650 @@ +****************************************************************************** + TMS320C2000 Linker Unix v22.6.1 +****************************************************************************** +>> Linked Fri Jan 19 11:29:33 2024 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_main" address: 00000000 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- +PAGE 0: + PROG 00000040 003fffc0 00000316 003ffcaa RWIX + +PAGE 1: + DATA 00000000 00010000 00000a77 0000f589 RW + DATA1 00010000 003f0000 00000000 003f0000 RW + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.text 0 00000040 00000316 + 00000040 00000316 DSP2833x_DefaultIsr.c.o (.text:retain) + +.data 0 00000040 00000000 UNINITIALIZED + +.bss 1 00000000 00000000 UNINITIALIZED + +ECanaMboxesFile +* 1 00000000 00000100 UNINITIALIZED + 00000000 00000100 DSP2833x_GlobalVariableDefs.c.o (ECanaMboxesFile) + +ECanbMboxesFile +* 1 00000100 00000100 UNINITIALIZED + 00000100 00000100 DSP2833x_GlobalVariableDefs.c.o (ECanbMboxesFile) + +PieVectTableFile +* 1 00000200 00000100 UNINITIALIZED + 00000200 00000100 DSP2833x_GlobalVariableDefs.c.o (PieVectTableFile) + +DmaRegsFile +* 1 00000300 000000e0 UNINITIALIZED + 00000300 000000e0 DSP2833x_GlobalVariableDefs.c.o (DmaRegsFile) + +ECap1RegsFile +* 1 000003e0 00000020 UNINITIALIZED + 000003e0 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap1RegsFile) + +DevEmuRegsFile +* 1 00000400 000000d0 UNINITIALIZED + 00000400 000000d0 DSP2833x_GlobalVariableDefs.c.o (DevEmuRegsFile) + +GpioCtrlRegsFile +* 1 000004d0 0000002e UNINITIALIZED + 000004d0 0000002e DSP2833x_GlobalVariableDefs.c.o (GpioCtrlRegsFile) + +PartIdRegsFile +* 1 000004fe 00000001 UNINITIALIZED + 000004fe 00000001 DSP2833x_GlobalVariableDefs.c.o (PartIdRegsFile) + +ECanaLAMRegsFile +* 1 00000500 00000040 UNINITIALIZED + 00000500 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanaLAMRegsFile) + +ECanaMOTORegsFile +* 1 00000540 00000040 UNINITIALIZED + 00000540 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanaMOTORegsFile) + +ECanaMOTSRegsFile +* 1 00000580 00000040 UNINITIALIZED + 00000580 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanaMOTSRegsFile) + +ECanbLAMRegsFile +* 1 000005c0 00000040 UNINITIALIZED + 000005c0 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanbLAMRegsFile) + +ECanbMOTORegsFile +* 1 00000600 00000040 UNINITIALIZED + 00000600 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanbMOTORegsFile) + +ECanbMOTSRegsFile +* 1 00000640 00000040 UNINITIALIZED + 00000640 00000040 DSP2833x_GlobalVariableDefs.c.o (ECanbMOTSRegsFile) + +EQep1RegsFile +* 1 00000680 00000040 UNINITIALIZED + 00000680 00000040 DSP2833x_GlobalVariableDefs.c.o (EQep1RegsFile) + +EQep2RegsFile +* 1 000006c0 00000040 UNINITIALIZED + 000006c0 00000040 DSP2833x_GlobalVariableDefs.c.o (EQep2RegsFile) + +ECanaRegsFile +* 1 00000700 00000034 UNINITIALIZED + 00000700 00000034 DSP2833x_GlobalVariableDefs.c.o (ECanaRegsFile) + +GpioIntRegsFile +* 1 00000734 0000000a UNINITIALIZED + 00000734 0000000a DSP2833x_GlobalVariableDefs.c.o (GpioIntRegsFile) + +ECanbRegsFile +* 1 00000740 00000034 UNINITIALIZED + 00000740 00000034 DSP2833x_GlobalVariableDefs.c.o (ECanbRegsFile) + +CpuTimer0RegsFile +* 1 00000774 00000008 UNINITIALIZED + 00000774 00000008 DSP2833x_GlobalVariableDefs.c.o (CpuTimer0RegsFile) + +McbspaRegsFile +* 1 00000780 00000025 UNINITIALIZED + 00000780 00000025 DSP2833x_GlobalVariableDefs.c.o (McbspaRegsFile) + +PieCtrlRegsFile +* 1 000007a5 0000001a UNINITIALIZED + 000007a5 0000001a DSP2833x_GlobalVariableDefs.c.o (PieCtrlRegsFile) + +McbspbRegsFile +* 1 000007c0 00000025 UNINITIALIZED + 000007c0 00000025 DSP2833x_GlobalVariableDefs.c.o (McbspbRegsFile) + +AdcMirrorFile +* 1 000007e5 00000010 UNINITIALIZED + 000007e5 00000010 DSP2833x_GlobalVariableDefs.c.o (AdcMirrorFile) + +CpuTimer1RegsFile +* 1 000007f6 00000008 UNINITIALIZED + 000007f6 00000008 DSP2833x_GlobalVariableDefs.c.o (CpuTimer1RegsFile) + +EPwm1RegsFile +* 1 00000800 00000022 UNINITIALIZED + 00000800 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm1RegsFile) + +AdcRegsFile +* 1 00000822 0000001e UNINITIALIZED + 00000822 0000001e DSP2833x_GlobalVariableDefs.c.o (AdcRegsFile) + +EPwm2RegsFile +* 1 00000840 00000022 UNINITIALIZED + 00000840 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm2RegsFile) + +XintfRegsFile +* 1 00000862 0000001e UNINITIALIZED + 00000862 0000001e DSP2833x_GlobalVariableDefs.c.o (XintfRegsFile) + +EPwm3RegsFile +* 1 00000880 00000022 UNINITIALIZED + 00000880 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm3RegsFile) + +CsmRegsFile +* 1 000008a2 00000010 UNINITIALIZED + 000008a2 00000010 DSP2833x_GlobalVariableDefs.c.o (CsmRegsFile) + +CpuTimer2RegsFile +* 1 000008b2 00000008 UNINITIALIZED + 000008b2 00000008 DSP2833x_GlobalVariableDefs.c.o (CpuTimer2RegsFile) + +EPwm4RegsFile +* 1 000008c0 00000022 UNINITIALIZED + 000008c0 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm4RegsFile) + +SciaRegsFile +* 1 000008e2 00000010 UNINITIALIZED + 000008e2 00000010 DSP2833x_GlobalVariableDefs.c.o (SciaRegsFile) + +CsmPwlFile +* 1 000008f2 00000008 UNINITIALIZED + 000008f2 00000008 DSP2833x_GlobalVariableDefs.c.o (CsmPwlFile) + +EPwm5RegsFile +* 1 00000900 00000022 UNINITIALIZED + 00000900 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm5RegsFile) + +ScibRegsFile +* 1 00000922 00000010 UNINITIALIZED + 00000922 00000010 DSP2833x_GlobalVariableDefs.c.o (ScibRegsFile) + +FlashRegsFile +* 1 00000932 00000008 UNINITIALIZED + 00000932 00000008 DSP2833x_GlobalVariableDefs.c.o (FlashRegsFile) + +EPwm6RegsFile +* 1 00000940 00000022 UNINITIALIZED + 00000940 00000022 DSP2833x_GlobalVariableDefs.c.o (EPwm6RegsFile) + +ScicRegsFile +* 1 00000962 00000010 UNINITIALIZED + 00000962 00000010 DSP2833x_GlobalVariableDefs.c.o (ScicRegsFile) + +I2caRegsFile +* 1 00000980 00000022 UNINITIALIZED + 00000980 00000022 DSP2833x_GlobalVariableDefs.c.o (I2caRegsFile) + +SpiaRegsFile +* 1 000009a2 00000010 UNINITIALIZED + 000009a2 00000010 DSP2833x_GlobalVariableDefs.c.o (SpiaRegsFile) + +ECap2RegsFile +* 1 000009c0 00000020 UNINITIALIZED + 000009c0 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap2RegsFile) + +ECap3RegsFile +* 1 000009e0 00000020 UNINITIALIZED + 000009e0 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap3RegsFile) + +ECap4RegsFile +* 1 00000a00 00000020 UNINITIALIZED + 00000a00 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap4RegsFile) + +ECap5RegsFile +* 1 00000a20 00000020 UNINITIALIZED + 00000a20 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap5RegsFile) + +ECap6RegsFile +* 1 00000a40 00000020 UNINITIALIZED + 00000a40 00000020 DSP2833x_GlobalVariableDefs.c.o (ECap6RegsFile) + +GpioDataRegsFile +* 1 00000a60 00000020 UNINITIALIZED + 00000a60 00000020 DSP2833x_GlobalVariableDefs.c.o (GpioDataRegsFile) + +SysCtrlRegsFile +* 1 00000a80 00000020 UNINITIALIZED + 00000a80 00000020 DSP2833x_GlobalVariableDefs.c.o (SysCtrlRegsFile) + +XIntruptRegsFile +* 1 00000aa0 00000010 UNINITIALIZED + 00000aa0 00000010 DSP2833x_GlobalVariableDefs.c.o (XIntruptRegsFile) + +MODULE SUMMARY + + Module code initialized data uninitialized data + ------ ---- ---------------- ------------------ + CMakeFiles/test_project.dir/f2833x/common/source/ + DSP2833x_DefaultIsr.c.o 790 0 0 + +--+---------------------------------+------+------------------+--------------------+ + Total: 790 0 0 + + CMakeFiles/test_project.dir/f2833x/headers/source/ + DSP2833x_GlobalVariableDefs.c.o 0 0 2679 + +--+---------------------------------+------+------------------+--------------------+ + Total: 0 0 2679 + + +--+---------------------------------+------+------------------+--------------------+ + Grand Total: 790 0 2679 + + +GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE + +address data page name +-------- ---------------- ---- +00000000 0 (00000000) _ECanaMboxes + +00000100 4 (00000100) _ECanbMboxes + +00000200 8 (00000200) _PieVectTable + +00000300 c (00000300) _DmaRegs + +000003e0 f (000003c0) _ECap1Regs + +00000400 10 (00000400) _DevEmuRegs + +000004d0 13 (000004c0) _GpioCtrlRegs +000004fe 13 (000004c0) _PartIdRegs + +00000500 14 (00000500) _ECanaLAMRegs + +00000540 15 (00000540) _ECanaMOTORegs + +00000580 16 (00000580) _ECanaMOTSRegs + +000005c0 17 (000005c0) _ECanbLAMRegs + +00000600 18 (00000600) _ECanbMOTORegs + +00000640 19 (00000640) _ECanbMOTSRegs + +00000680 1a (00000680) _EQep1Regs + +000006c0 1b (000006c0) _EQep2Regs + +00000700 1c (00000700) _ECanaRegs +00000734 1c (00000700) _GpioIntRegs + +00000740 1d (00000740) _ECanbRegs +00000774 1d (00000740) _CpuTimer0Regs + +00000780 1e (00000780) _McbspaRegs +000007a5 1e (00000780) _PieCtrlRegs + +000007c0 1f (000007c0) _McbspbRegs +000007e5 1f (000007c0) _AdcMirror +000007f6 1f (000007c0) _CpuTimer1Regs + +00000800 20 (00000800) _EPwm1Regs +00000822 20 (00000800) _AdcRegs + +00000840 21 (00000840) _EPwm2Regs +00000862 21 (00000840) _XintfRegs + +00000880 22 (00000880) _EPwm3Regs +000008a2 22 (00000880) _CsmRegs +000008b2 22 (00000880) _CpuTimer2Regs + +000008c0 23 (000008c0) _EPwm4Regs +000008e2 23 (000008c0) _SciaRegs +000008f2 23 (000008c0) _CsmPwl + +00000900 24 (00000900) _EPwm5Regs +00000922 24 (00000900) _ScibRegs +00000932 24 (00000900) _FlashRegs + +00000940 25 (00000940) _EPwm6Regs +00000962 25 (00000940) _ScicRegs + +00000980 26 (00000980) _I2caRegs +000009a2 26 (00000980) _SpiaRegs + +000009c0 27 (000009c0) _ECap2Regs +000009e0 27 (000009c0) _ECap3Regs + +00000a00 28 (00000a00) _ECap4Regs +00000a20 28 (00000a00) _ECap5Regs + +00000a40 29 (00000a40) _ECap6Regs +00000a60 29 (00000a40) _GpioDataRegs + +00000a80 2a (00000a80) _SysCtrlRegs +00000aa0 2a (00000a80) _XIntruptRegs + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +page address name +---- ------- ---- +1 00000000 .bss +0 00000040 .data +0 00000040 .text +0 00000126 _ADCINT_ISR +1 000007e5 _AdcMirror +1 00000822 _AdcRegs +1 00000774 _CpuTimer0Regs +1 000007f6 _CpuTimer1Regs +1 000008b2 _CpuTimer2Regs +1 000008f2 _CsmPwl +1 000008a2 _CsmRegs +0 00000054 _DATALOG_ISR +0 00000248 _DINTCH1_ISR +0 00000252 _DINTCH2_ISR +0 0000025c _DINTCH3_ISR +0 00000266 _DINTCH4_ISR +0 00000270 _DINTCH5_ISR +0 0000027a _DINTCH6_ISR +1 00000400 _DevEmuRegs +1 00000300 _DmaRegs +0 000002d4 _ECAN0INTA_ISR +0 000002e8 _ECAN0INTB_ISR +0 000002de _ECAN1INTA_ISR +0 000002f2 _ECAN1INTB_ISR +0 000001bc _ECAP1_INT_ISR +0 000001c6 _ECAP2_INT_ISR +0 000001d0 _ECAP3_INT_ISR +0 000001da _ECAP4_INT_ISR +0 000001e4 _ECAP5_INT_ISR +0 000001ee _ECAP6_INT_ISR +1 00000500 _ECanaLAMRegs +1 00000540 _ECanaMOTORegs +1 00000580 _ECanaMOTSRegs +1 00000000 _ECanaMboxes +1 00000700 _ECanaRegs +1 000005c0 _ECanbLAMRegs +1 00000600 _ECanbMOTORegs +1 00000640 _ECanbMOTSRegs +1 00000100 _ECanbMboxes +1 00000740 _ECanbRegs +1 000003e0 _ECap1Regs +1 000009c0 _ECap2Regs +1 000009e0 _ECap3Regs +1 00000a00 _ECap4Regs +1 00000a20 _ECap5Regs +1 00000a40 _ECap6Regs +0 00000068 _EMUINT_ISR +0 00000180 _EPWM1_INT_ISR +0 00000144 _EPWM1_TZINT_ISR +0 0000018a _EPWM2_INT_ISR +0 0000014e _EPWM2_TZINT_ISR +0 00000194 _EPWM3_INT_ISR +0 00000158 _EPWM3_TZINT_ISR +0 0000019e _EPWM4_INT_ISR +0 00000162 _EPWM4_TZINT_ISR +0 000001a8 _EPWM5_INT_ISR +0 0000016c _EPWM5_TZINT_ISR +0 000001b2 _EPWM6_INT_ISR +0 00000176 _EPWM6_TZINT_ISR +1 00000800 _EPwm1Regs +1 00000840 _EPwm2Regs +1 00000880 _EPwm3Regs +1 000008c0 _EPwm4Regs +1 00000900 _EPwm5Regs +1 00000940 _EPwm6Regs +0 000001f8 _EQEP1_INT_ISR +0 00000202 _EQEP2_INT_ISR +1 00000680 _EQep1Regs +1 000006c0 _EQep2Regs +1 00000932 _FlashRegs +1 000004d0 _GpioCtrlRegs +1 00000a60 _GpioDataRegs +1 00000734 _GpioIntRegs +0 00000284 _I2CINT1A_ISR +0 0000028e _I2CINT2A_ISR +1 00000980 _I2caRegs +0 0000007c _ILLEGAL_ISR +0 00000040 _INT13_ISR +0 0000004a _INT14_ISR +0 00000338 _LUF_ISR +0 0000032e _LVF_ISR +0 00000234 _MRINTA_ISR +0 00000220 _MRINTB_ISR +0 0000023e _MXINTA_ISR +0 0000022a _MXINTB_ISR +1 00000780 _McbspaRegs +1 000007c0 _McbspbRegs +0 00000072 _NMI_ISR +0 00000342 _PIE_RESERVED +1 000004fe _PartIdRegs +1 000007a5 _PieCtrlRegs +1 00000200 _PieVectTable +0 0000005e _RTOSINT_ISR +0 000002ac _SCIRXINTA_ISR +0 000002c0 _SCIRXINTB_ISR +0 00000298 _SCIRXINTC_ISR +0 000002b6 _SCITXINTA_ISR +0 000002ca _SCITXINTB_ISR +0 000002a2 _SCITXINTC_ISR +0 000000fe _SEQ1INT_ISR +0 00000108 _SEQ2INT_ISR +0 0000020c _SPIRXINTA_ISR +0 00000216 _SPITXINTA_ISR +1 000008e2 _SciaRegs +1 00000922 _ScibRegs +1 00000962 _ScicRegs +1 000009a2 _SpiaRegs +1 00000a80 _SysCtrlRegs +0 00000130 _TINT0_ISR +0 000000e0 _USER10_ISR +0 000000ea _USER11_ISR +0 000000f4 _USER12_ISR +0 00000086 _USER1_ISR +0 00000090 _USER2_ISR +0 0000009a _USER3_ISR +0 000000a4 _USER4_ISR +0 000000ae _USER5_ISR +0 000000b8 _USER6_ISR +0 000000c2 _USER7_ISR +0 000000cc _USER8_ISR +0 000000d6 _USER9_ISR +0 0000013a _WAKEINT_ISR +0 00000112 _XINT1_ISR +0 0000011c _XINT2_ISR +0 000002fc _XINT3_ISR +0 00000306 _XINT4_ISR +0 00000310 _XINT5_ISR +0 0000031a _XINT6_ISR +0 00000324 _XINT7_ISR +1 00000aa0 _XIntruptRegs +1 00000862 _XintfRegs +abs ffffffff ___TI_pprof_out_hndl +abs ffffffff ___TI_prof_data_size +abs ffffffff ___TI_prof_data_start +abs ffffffff ___binit__ +1 00000000 ___bss__ +abs ffffffff ___c_args__ +abs ffffffff ___cinit__ +0 00000040 ___data__ +0 00000040 ___edata__ +1 00000000 ___end__ +0 00000356 ___etext__ +abs ffffffff ___pinit__ +0 00000040 ___text__ +0 0000034c _rsvd_ISR +abs ffffffff binit +abs ffffffff cinit +0 00000040 edata +1 00000000 end +0 00000356 etext +abs ffffffff pinit + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +page address name +---- ------- ---- +0 00000040 .data +0 00000040 .text +0 00000040 _INT13_ISR +0 00000040 ___data__ +0 00000040 ___edata__ +0 00000040 ___text__ +0 00000040 edata +0 0000004a _INT14_ISR +0 00000054 _DATALOG_ISR +0 0000005e _RTOSINT_ISR +0 00000068 _EMUINT_ISR +0 00000072 _NMI_ISR +0 0000007c _ILLEGAL_ISR +0 00000086 _USER1_ISR +0 00000090 _USER2_ISR +0 0000009a _USER3_ISR +0 000000a4 _USER4_ISR +0 000000ae _USER5_ISR +0 000000b8 _USER6_ISR +0 000000c2 _USER7_ISR +0 000000cc _USER8_ISR +0 000000d6 _USER9_ISR +0 000000e0 _USER10_ISR +0 000000ea _USER11_ISR +0 000000f4 _USER12_ISR +0 000000fe _SEQ1INT_ISR +0 00000108 _SEQ2INT_ISR +0 00000112 _XINT1_ISR +0 0000011c _XINT2_ISR +0 00000126 _ADCINT_ISR +0 00000130 _TINT0_ISR +0 0000013a _WAKEINT_ISR +0 00000144 _EPWM1_TZINT_ISR +0 0000014e _EPWM2_TZINT_ISR +0 00000158 _EPWM3_TZINT_ISR +0 00000162 _EPWM4_TZINT_ISR +0 0000016c _EPWM5_TZINT_ISR +0 00000176 _EPWM6_TZINT_ISR +0 00000180 _EPWM1_INT_ISR +0 0000018a _EPWM2_INT_ISR +0 00000194 _EPWM3_INT_ISR +0 0000019e _EPWM4_INT_ISR +0 000001a8 _EPWM5_INT_ISR +0 000001b2 _EPWM6_INT_ISR +0 000001bc _ECAP1_INT_ISR +0 000001c6 _ECAP2_INT_ISR +0 000001d0 _ECAP3_INT_ISR +0 000001da _ECAP4_INT_ISR +0 000001e4 _ECAP5_INT_ISR +0 000001ee _ECAP6_INT_ISR +0 000001f8 _EQEP1_INT_ISR +0 00000202 _EQEP2_INT_ISR +0 0000020c _SPIRXINTA_ISR +0 00000216 _SPITXINTA_ISR +0 00000220 _MRINTB_ISR +0 0000022a _MXINTB_ISR +0 00000234 _MRINTA_ISR +0 0000023e _MXINTA_ISR +0 00000248 _DINTCH1_ISR +0 00000252 _DINTCH2_ISR +0 0000025c _DINTCH3_ISR +0 00000266 _DINTCH4_ISR +0 00000270 _DINTCH5_ISR +0 0000027a _DINTCH6_ISR +0 00000284 _I2CINT1A_ISR +0 0000028e _I2CINT2A_ISR +0 00000298 _SCIRXINTC_ISR +0 000002a2 _SCITXINTC_ISR +0 000002ac _SCIRXINTA_ISR +0 000002b6 _SCITXINTA_ISR +0 000002c0 _SCIRXINTB_ISR +0 000002ca _SCITXINTB_ISR +0 000002d4 _ECAN0INTA_ISR +0 000002de _ECAN1INTA_ISR +0 000002e8 _ECAN0INTB_ISR +0 000002f2 _ECAN1INTB_ISR +0 000002fc _XINT3_ISR +0 00000306 _XINT4_ISR +0 00000310 _XINT5_ISR +0 0000031a _XINT6_ISR +0 00000324 _XINT7_ISR +0 0000032e _LVF_ISR +0 00000338 _LUF_ISR +0 00000342 _PIE_RESERVED +0 0000034c _rsvd_ISR +0 00000356 ___etext__ +0 00000356 etext +1 00000000 .bss +1 00000000 _ECanaMboxes +1 00000000 ___bss__ +1 00000000 ___end__ +1 00000000 end +1 00000100 _ECanbMboxes +1 00000200 _PieVectTable +1 00000300 _DmaRegs +1 000003e0 _ECap1Regs +1 00000400 _DevEmuRegs +1 000004d0 _GpioCtrlRegs +1 000004fe _PartIdRegs +1 00000500 _ECanaLAMRegs +1 00000540 _ECanaMOTORegs +1 00000580 _ECanaMOTSRegs +1 000005c0 _ECanbLAMRegs +1 00000600 _ECanbMOTORegs +1 00000640 _ECanbMOTSRegs +1 00000680 _EQep1Regs +1 000006c0 _EQep2Regs +1 00000700 _ECanaRegs +1 00000734 _GpioIntRegs +1 00000740 _ECanbRegs +1 00000774 _CpuTimer0Regs +1 00000780 _McbspaRegs +1 000007a5 _PieCtrlRegs +1 000007c0 _McbspbRegs +1 000007e5 _AdcMirror +1 000007f6 _CpuTimer1Regs +1 00000800 _EPwm1Regs +1 00000822 _AdcRegs +1 00000840 _EPwm2Regs +1 00000862 _XintfRegs +1 00000880 _EPwm3Regs +1 000008a2 _CsmRegs +1 000008b2 _CpuTimer2Regs +1 000008c0 _EPwm4Regs +1 000008e2 _SciaRegs +1 000008f2 _CsmPwl +1 00000900 _EPwm5Regs +1 00000922 _ScibRegs +1 00000932 _FlashRegs +1 00000940 _EPwm6Regs +1 00000962 _ScicRegs +1 00000980 _I2caRegs +1 000009a2 _SpiaRegs +1 000009c0 _ECap2Regs +1 000009e0 _ECap3Regs +1 00000a00 _ECap4Regs +1 00000a20 _ECap5Regs +1 00000a40 _ECap6Regs +1 00000a60 _GpioDataRegs +1 00000a80 _SysCtrlRegs +1 00000aa0 _XIntruptRegs +abs ffffffff ___TI_pprof_out_hndl +abs ffffffff ___TI_prof_data_size +abs ffffffff ___TI_prof_data_start +abs ffffffff ___binit__ +abs ffffffff ___c_args__ +abs ffffffff ___cinit__ +abs ffffffff ___pinit__ +abs ffffffff binit +abs ffffffff cinit +abs ffffffff pinit + +[151 symbols] diff --git a/build/Makefile b/build/Makefile new file mode 100644 index 0000000..1517fbe --- /dev/null +++ b/build/Makefile @@ -0,0 +1,316 @@ +# CMAKE generated file: DO NOT EDIT! +# Generated by "Unix Makefiles" Generator, CMake Version 3.22 + +# Default target executed when no arguments are given to make. +default_target: all +.PHONY : default_target + +# Allow only one "make -f Makefile2" at a time, but pass parallelism. +.NOTPARALLEL: + +#============================================================================= +# Special targets provided by cmake. + +# Disable implicit rules so canonical targets will work. +.SUFFIXES: + +# Disable VCS-based implicit rules. +% : %,v + +# Disable VCS-based implicit rules. +% : RCS/% + +# Disable VCS-based implicit rules. +% : RCS/%,v + +# Disable VCS-based implicit rules. +% : SCCS/s.% + +# Disable VCS-based implicit rules. +% : s.% + +.SUFFIXES: .hpux_make_needs_suffix_list + +# Command-line flag to silence nested $(MAKE). +$(VERBOSE)MAKESILENT = -s + +#Suppress display of executed commands. +$(VERBOSE).SILENT: + +# A target that is always out of date. +cmake_force: +.PHONY : cmake_force + +#============================================================================= +# Set environment variables for the build. + +# The shell in which to execute make rules. +SHELL = /bin/sh + +# The CMake executable. +CMAKE_COMMAND = /usr/bin/cmake + +# The command to remove a file. +RM = /usr/bin/cmake -E rm -f + +# Escaping for special characters. +EQUALS = = + +# The top-level source directory on which CMake was run. +CMAKE_SOURCE_DIR = /home/lobov/workspace/ccs12.5/cmake_test + +# The top-level build directory on which CMake was run. +CMAKE_BINARY_DIR = /home/lobov/workspace/ccs12.5/cmake_test/build + +#============================================================================= +# Targets provided globally by CMake. + +# Special rule for the target edit_cache +edit_cache: + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --cyan "No interactive CMake dialog available..." + /usr/bin/cmake -E echo No\ interactive\ CMake\ dialog\ available. +.PHONY : edit_cache + +# Special rule for the target edit_cache +edit_cache/fast: edit_cache +.PHONY : edit_cache/fast + +# Special rule for the target rebuild_cache +rebuild_cache: + @$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --cyan "Running CMake to regenerate build system..." + /usr/bin/cmake --regenerate-during-build -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) +.PHONY : rebuild_cache + +# Special rule for the target rebuild_cache +rebuild_cache/fast: rebuild_cache +.PHONY : rebuild_cache/fast + +# The main all target +all: cmake_check_build_system + $(CMAKE_COMMAND) -E cmake_progress_start /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles /home/lobov/workspace/ccs12.5/cmake_test/build//CMakeFiles/progress.marks + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 all + $(CMAKE_COMMAND) -E cmake_progress_start /home/lobov/workspace/ccs12.5/cmake_test/build/CMakeFiles 0 +.PHONY : all + +# The main clean target +clean: + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 clean +.PHONY : clean + +# The main clean target +clean/fast: clean +.PHONY : clean/fast + +# Prepare targets for installation. +preinstall: all + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 preinstall +.PHONY : preinstall + +# Prepare targets for installation. +preinstall/fast: + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 preinstall +.PHONY : preinstall/fast + +# clear depends +depend: + $(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 1 +.PHONY : depend + +#============================================================================= +# Target rules for targets named test_project + +# Build rule for target. +test_project: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 test_project +.PHONY : test_project + +# fast build rule for target. +test_project/fast: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/build +.PHONY : test_project/fast + +f2833x/common/source/DSP2833x_DefaultIsr.o: f2833x/common/source/DSP2833x_DefaultIsr.c.o +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.o + +# target to build an object file +f2833x/common/source/DSP2833x_DefaultIsr.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.c.o + +f2833x/common/source/DSP2833x_DefaultIsr.i: f2833x/common/source/DSP2833x_DefaultIsr.c.i +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.i + +# target to preprocess a source file +f2833x/common/source/DSP2833x_DefaultIsr.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.i +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.c.i + +f2833x/common/source/DSP2833x_DefaultIsr.s: f2833x/common/source/DSP2833x_DefaultIsr.c.s +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.s + +# target to generate assembly for a file +f2833x/common/source/DSP2833x_DefaultIsr.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.s +.PHONY : f2833x/common/source/DSP2833x_DefaultIsr.c.s + +f2833x/common/source/DSP2833x_PieCtrl.o: f2833x/common/source/DSP2833x_PieCtrl.c.o +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.o + +# target to build an object file +f2833x/common/source/DSP2833x_PieCtrl.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.c.o + +f2833x/common/source/DSP2833x_PieCtrl.i: f2833x/common/source/DSP2833x_PieCtrl.c.i +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.i + +# target to preprocess a source file +f2833x/common/source/DSP2833x_PieCtrl.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.i +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.c.i + +f2833x/common/source/DSP2833x_PieCtrl.s: f2833x/common/source/DSP2833x_PieCtrl.c.s +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.s + +# target to generate assembly for a file +f2833x/common/source/DSP2833x_PieCtrl.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.s +.PHONY : f2833x/common/source/DSP2833x_PieCtrl.c.s + +f2833x/common/source/DSP2833x_PieVect.o: f2833x/common/source/DSP2833x_PieVect.c.o +.PHONY : f2833x/common/source/DSP2833x_PieVect.o + +# target to build an object file +f2833x/common/source/DSP2833x_PieVect.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o +.PHONY : f2833x/common/source/DSP2833x_PieVect.c.o + +f2833x/common/source/DSP2833x_PieVect.i: f2833x/common/source/DSP2833x_PieVect.c.i +.PHONY : f2833x/common/source/DSP2833x_PieVect.i + +# target to preprocess a source file +f2833x/common/source/DSP2833x_PieVect.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.i +.PHONY : f2833x/common/source/DSP2833x_PieVect.c.i + +f2833x/common/source/DSP2833x_PieVect.s: f2833x/common/source/DSP2833x_PieVect.c.s +.PHONY : f2833x/common/source/DSP2833x_PieVect.s + +# target to generate assembly for a file +f2833x/common/source/DSP2833x_PieVect.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.s +.PHONY : f2833x/common/source/DSP2833x_PieVect.c.s + +f2833x/common/source/DSP2833x_SysCtrl.o: f2833x/common/source/DSP2833x_SysCtrl.c.o +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.o + +# target to build an object file +f2833x/common/source/DSP2833x_SysCtrl.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.c.o + +f2833x/common/source/DSP2833x_SysCtrl.i: f2833x/common/source/DSP2833x_SysCtrl.c.i +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.i + +# target to preprocess a source file +f2833x/common/source/DSP2833x_SysCtrl.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.i +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.c.i + +f2833x/common/source/DSP2833x_SysCtrl.s: f2833x/common/source/DSP2833x_SysCtrl.c.s +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.s + +# target to generate assembly for a file +f2833x/common/source/DSP2833x_SysCtrl.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.s +.PHONY : f2833x/common/source/DSP2833x_SysCtrl.c.s + +f2833x/headers/source/DSP2833x_GlobalVariableDefs.o: f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.o + +# target to build an object file +f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o + +f2833x/headers/source/DSP2833x_GlobalVariableDefs.i: f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.i + +# target to preprocess a source file +f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.i + +f2833x/headers/source/DSP2833x_GlobalVariableDefs.s: f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.s + +# target to generate assembly for a file +f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s +.PHONY : f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.s + +main.o: main.cpp.o +.PHONY : main.o + +# target to build an object file +main.cpp.o: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/main.cpp.o +.PHONY : main.cpp.o + +main.i: main.cpp.i +.PHONY : main.i + +# target to preprocess a source file +main.cpp.i: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/main.cpp.i +.PHONY : main.cpp.i + +main.s: main.cpp.s +.PHONY : main.s + +# target to generate assembly for a file +main.cpp.s: + $(MAKE) $(MAKESILENT) -f CMakeFiles/test_project.dir/build.make CMakeFiles/test_project.dir/main.cpp.s +.PHONY : main.cpp.s + +# Help Target +help: + @echo "The following are some of the valid targets for this Makefile:" + @echo "... all (the default if no target is provided)" + @echo "... clean" + @echo "... depend" + @echo "... edit_cache" + @echo "... rebuild_cache" + @echo "... test_project" + @echo "... f2833x/common/source/DSP2833x_DefaultIsr.o" + @echo "... f2833x/common/source/DSP2833x_DefaultIsr.i" + @echo "... f2833x/common/source/DSP2833x_DefaultIsr.s" + @echo "... f2833x/common/source/DSP2833x_PieCtrl.o" + @echo "... f2833x/common/source/DSP2833x_PieCtrl.i" + @echo "... f2833x/common/source/DSP2833x_PieCtrl.s" + @echo "... f2833x/common/source/DSP2833x_PieVect.o" + @echo "... f2833x/common/source/DSP2833x_PieVect.i" + @echo "... f2833x/common/source/DSP2833x_PieVect.s" + @echo "... f2833x/common/source/DSP2833x_SysCtrl.o" + @echo "... f2833x/common/source/DSP2833x_SysCtrl.i" + @echo "... f2833x/common/source/DSP2833x_SysCtrl.s" + @echo "... f2833x/headers/source/DSP2833x_GlobalVariableDefs.o" + @echo "... f2833x/headers/source/DSP2833x_GlobalVariableDefs.i" + @echo "... f2833x/headers/source/DSP2833x_GlobalVariableDefs.s" + @echo "... main.o" + @echo "... main.i" + @echo "... main.s" +.PHONY : help + + + +#============================================================================= +# Special targets to cleanup operation of make. + +# Special rule to run CMake to check the build system integrity. +# No rule that depends on this can have commands that come from listfiles +# because they might be regenerated. +cmake_check_build_system: + $(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 0 +.PHONY : cmake_check_build_system + diff --git a/build/cmake_install.cmake b/build/cmake_install.cmake new file mode 100644 index 0000000..eed54d0 --- /dev/null +++ b/build/cmake_install.cmake @@ -0,0 +1,54 @@ +# Install script for directory: /home/lobov/workspace/ccs12.5/cmake_test + +# Set the install prefix +if(NOT DEFINED CMAKE_INSTALL_PREFIX) + set(CMAKE_INSTALL_PREFIX "/usr/local") +endif() +string(REGEX REPLACE "/$" "" CMAKE_INSTALL_PREFIX "${CMAKE_INSTALL_PREFIX}") + +# Set the install configuration name. +if(NOT DEFINED CMAKE_INSTALL_CONFIG_NAME) + if(BUILD_TYPE) + string(REGEX REPLACE "^[^A-Za-z0-9_]+" "" + CMAKE_INSTALL_CONFIG_NAME "${BUILD_TYPE}") + else() + set(CMAKE_INSTALL_CONFIG_NAME "Debug") + endif() + message(STATUS "Install configuration: \"${CMAKE_INSTALL_CONFIG_NAME}\"") +endif() + +# Set the component getting installed. +if(NOT CMAKE_INSTALL_COMPONENT) + if(COMPONENT) + message(STATUS "Install component: \"${COMPONENT}\"") + set(CMAKE_INSTALL_COMPONENT "${COMPONENT}") + else() + set(CMAKE_INSTALL_COMPONENT) + endif() +endif() + +# Install shared libraries without execute permission? +if(NOT DEFINED CMAKE_INSTALL_SO_NO_EXE) + set(CMAKE_INSTALL_SO_NO_EXE "1") +endif() + +# Is this installation the result of a crosscompile? +if(NOT DEFINED CMAKE_CROSSCOMPILING) + set(CMAKE_CROSSCOMPILING "FALSE") +endif() + +# Set default install directory permissions. +if(NOT DEFINED CMAKE_OBJDUMP) + set(CMAKE_OBJDUMP "/usr/bin/objdump") +endif() + +if(CMAKE_INSTALL_COMPONENT) + set(CMAKE_INSTALL_MANIFEST "install_manifest_${CMAKE_INSTALL_COMPONENT}.txt") +else() + set(CMAKE_INSTALL_MANIFEST "install_manifest.txt") +endif() + +string(REPLACE ";" "\n" CMAKE_INSTALL_MANIFEST_CONTENT + "${CMAKE_INSTALL_MANIFEST_FILES}") +file(WRITE "/home/lobov/workspace/ccs12.5/cmake_test/build/${CMAKE_INSTALL_MANIFEST}" + "${CMAKE_INSTALL_MANIFEST_CONTENT}") diff --git a/build/compile_commands.json b/build/compile_commands.json new file mode 100644 index 0000000..377559d --- /dev/null +++ b/build/compile_commands.json @@ -0,0 +1,32 @@ +[ +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --cpp_file=/home/lobov/workspace/ccs12.5/cmake_test/main.cpp --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/main.cpp.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/main.cpp" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_DefaultIsr.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_DefaultIsr.c" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieCtrl.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieCtrl.c" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_PieVect.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_PieVect.c" +}, +{ + "directory": "/home/lobov/workspace/ccs12.5/cmake_test/build", + "command": "/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/bin/cl2000 --compile_only --c_file=/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c --include_path=/home/lobov/workspace/ccs12.5/cmake_test/build --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/common/include --include_path=/home/lobov/workspace/ccs12.5/cmake_test/./f2833x/headers/include -v28 -ml -mt --float_support=fpu32 -Ooff --opt_for_speed=5 --fp_mode=relaxed -advice:performance=all --define=_INLINE \"--define=bmin='0.397824735f'\" \"--define=amax='0.960433870f'\" --float_operations_allowed=32 --printf_support=minimal --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/lib/\\\" --include_path=\\\"/home/lobov/ti/ccs1250/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/\\\" --output_file=CMakeFiles/test_project.dir/f2833x/common/source/DSP2833x_SysCtrl.c.o", + "file": "/home/lobov/workspace/ccs12.5/cmake_test/f2833x/common/source/DSP2833x_SysCtrl.c" +} +] \ No newline at end of file diff --git a/f2833x/.vscode/settings.json b/f2833x/.vscode/settings.json new file mode 100644 index 0000000..907176f --- /dev/null +++ b/f2833x/.vscode/settings.json @@ -0,0 +1,6 @@ +{ + "files.associations": { + "dsp28x_project.h": "c", + "dsp2833x_device.h": "c" + } +} \ No newline at end of file diff --git a/f2833x/common/cmd/28332_RAM_lnk.cmd b/f2833x/common/cmd/28332_RAM_lnk.cmd new file mode 100644 index 0000000..8e73e5e --- /dev/null +++ b/f2833x/common/cmd/28332_RAM_lnk.cmd @@ -0,0 +1,216 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: April 15, 2009 09:57:22 $ +//########################################################################### +// +// FILE: 28332_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28332 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28332 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28332 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28332 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + + + +PAGE 1 : + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : > RAML0, PAGE = 0 + #else + ramfuncs : > RAML0, PAGE = 0 + #endif +#endif + + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/f2833x/common/cmd/28333_RAM_lnk.cmd b/f2833x/common/cmd/28333_RAM_lnk.cmd new file mode 100644 index 0000000..2aa0a75 --- /dev/null +++ b/f2833x/common/cmd/28333_RAM_lnk.cmd @@ -0,0 +1,216 @@ +/* +// TI File $Revision: /main/11 $ +// Checkin $Date: April 15, 2009 09:57:28 $ +//########################################################################### +// +// FILE: 28333_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28333 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28333 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28333 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28333 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : > RAML0, PAGE = 0 + #else + ramfuncs : > RAML0, PAGE = 0 + #endif +#endif + + .text : > RAML1, PAGE = 0 + .InitBoot : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/f2833x/common/cmd/28334_RAM_lnk.cmd b/f2833x/common/cmd/28334_RAM_lnk.cmd new file mode 100644 index 0000000..507f893 --- /dev/null +++ b/f2833x/common/cmd/28334_RAM_lnk.cmd @@ -0,0 +1,218 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: April 15, 2009 09:57:24 $ +//########################################################################### +// +// FILE: 28334_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28334 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28334 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28334 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28334 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + + +PAGE 1 : + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : > RAML0, PAGE = 0 + #else + ramfuncs : > RAML0, PAGE = 0 + #endif +#endif + + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/f2833x/common/cmd/28335_RAM_lnk.cmd b/f2833x/common/cmd/28335_RAM_lnk.cmd new file mode 100644 index 0000000..a120d0f --- /dev/null +++ b/f2833x/common/cmd/28335_RAM_lnk.cmd @@ -0,0 +1,216 @@ +/* +// TI File $Revision: /main/11 $ +// Checkin $Date: April 15, 2009 09:57:28 $ +//########################################################################### +// +// FILE: 28335_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28335 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28335 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : > RAML0, PAGE = 0 + #else + ramfuncs : > RAML0, PAGE = 0 + #endif +#endif + + .text : >> RAML1 | RAML2, PAGE = 0 + .InitBoot : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/f2833x/common/cmd/F28332.cmd b/f2833x/common/cmd/F28332.cmd new file mode 100644 index 0000000..e61364f --- /dev/null +++ b/f2833x/common/cmd/F28332.cmd @@ -0,0 +1,241 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: July 9, 2008 13:43:41 $ +//########################################################################### +// +// FILE: F28332.cmd +// +// TITLE: Linker Command File For F28332 Device +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28332 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28332 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x100000, length = 0x100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */ + FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */ + FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x0000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */ + +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + LOAD_SIZE(_RamfuncsLoadSize), + PAGE = 0 + #else + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + LOAD_SIZE(_RamfuncsLoadSize), + PAGE = 0 + #endif +#endif + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/f2833x/common/cmd/F28333.cmd b/f2833x/common/cmd/F28333.cmd new file mode 100644 index 0000000..d5bd6f5 --- /dev/null +++ b/f2833x/common/cmd/F28333.cmd @@ -0,0 +1,245 @@ +/* +//########################################################################### +// +// FILE: F28333.cmd +// +// TITLE: Linker Command File For F28333 Device +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28333 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28333 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ + FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ + FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ + FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ + FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ + FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ + FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ + RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + LOAD_SIZE(_RamfuncsLoadSize), + PAGE = 0 + #else + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + LOAD_SIZE(_RamfuncsLoadSize), + PAGE = 0 + #endif +#endif + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/f2833x/common/cmd/F28334.cmd b/f2833x/common/cmd/F28334.cmd new file mode 100644 index 0000000..c2832f9 --- /dev/null +++ b/f2833x/common/cmd/F28334.cmd @@ -0,0 +1,247 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: July 9, 2008 13:43:49 $ +//########################################################################### +// +// FILE: F28334.cmd +// +// TITLE: Linker Command File For F28334 Device +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28334 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28334 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x100000, length = 0x0100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x200000, length = 0x000FC00 /* XINTF zone 7 - program space */ + FLASHH : origin = 0x320000, length = 0x004000 /* on-chip FLASH */ + FLASHG : origin = 0x324000, length = 0x004000 /* on-chip FLASH */ + FLASHF : origin = 0x328000, length = 0x004000 /* on-chip FLASH */ + FLASHE : origin = 0x32C000, length = 0x004000 /* on-chip FLASH */ + FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */ + FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */ + FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ + RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + LOAD_SIZE(_RamfuncsLoadSize), + PAGE = 0 + #else + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + LOAD_SIZE(_RamfuncsLoadSize), + PAGE = 0 + #endif +#endif + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/f2833x/common/cmd/F28335.cmd b/f2833x/common/cmd/F28335.cmd new file mode 100644 index 0000000..29cd7a5 --- /dev/null +++ b/f2833x/common/cmd/F28335.cmd @@ -0,0 +1,247 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: July 9, 2008 13:43:56 $ +//########################################################################### +// +// FILE: F28335.cmd +// +// TITLE: Linker Command File For F28335 Device +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ + FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ + FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ + FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ + FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ + FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ + FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ + RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + LOAD_SIZE(_RamfuncsLoadSize), + PAGE = 0 + #else + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + LOAD_SIZE(_RamfuncsLoadSize), + PAGE = 0 + #endif +#endif + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/f2833x/common/include/DSP2833x_DefaultIsr.h b/f2833x/common/include/DSP2833x_DefaultIsr.h new file mode 100644 index 0000000..3245a1d --- /dev/null +++ b/f2833x/common/include/DSP2833x_DefaultIsr.h @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/f2833x/common/include/DSP2833x_Dma_defines.h b/f2833x/common/include/DSP2833x_Dma_defines.h new file mode 100644 index 0000000..410cdc7 --- /dev/null +++ b/f2833x/common/include/DSP2833x_Dma_defines.h @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/f2833x/common/include/DSP2833x_EPwm_defines.h b/f2833x/common/include/DSP2833x_EPwm_defines.h new file mode 100644 index 0000000..a37d398 --- /dev/null +++ b/f2833x/common/include/DSP2833x_EPwm_defines.h @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/f2833x/common/include/DSP2833x_Examples.h b/f2833x/common/include/DSP2833x_Examples.h new file mode 100644 index 0000000..0bb89df --- /dev/null +++ b/f2833x/common/include/DSP2833x_Examples.h @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/f2833x/common/include/DSP2833x_GlobalPrototypes.h b/f2833x/common/include/DSP2833x_GlobalPrototypes.h new file mode 100644 index 0000000..c497fb2 --- /dev/null +++ b/f2833x/common/include/DSP2833x_GlobalPrototypes.h @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/f2833x/common/include/DSP2833x_I2c_defines.h b/f2833x/common/include/DSP2833x_I2c_defines.h new file mode 100644 index 0000000..5193241 --- /dev/null +++ b/f2833x/common/include/DSP2833x_I2c_defines.h @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/f2833x/common/include/DSP2833x_SWPrioritizedIsrLevels.h b/f2833x/common/include/DSP2833x_SWPrioritizedIsrLevels.h new file mode 100644 index 0000000..ef51e37 --- /dev/null +++ b/f2833x/common/include/DSP2833x_SWPrioritizedIsrLevels.h @@ -0,0 +1,5999 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 4, 2007 14:25:21 $ +//########################################################################### +// +// FILE: DSP2833x_SWPrioritizedIsrLevels.h +// +// TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine +// Level definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SW_PRIORITZIED_ISR_H +#define DSP2833x_SW_PRIORITZIED_ISR_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Interrupt Enable Register Allocation For 2833x Devices: +// +// Interrupts can be enabled/disabled using the CPU interrupt enable register +// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12). +// +// +// Set "Global" Interrupt Priority Level (IER register): +// +// The user must set the appropriate priority level for each of the CPU +// interrupts. This is termed as the "global" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used. +// +// Note: The priority levels below are used to calculate the IER register +// interrupt masks MINT1 to MINT16. +// +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +// +#define INT1PL 2 // Group1 Interrupts (PIEIER1) +#define INT2PL 1 // Group2 Interrupts (PIEIER2) +#define INT3PL 4 // Group3 Interrupts (PIEIER3) +#define INT4PL 2 // Group4 Interrupts (PIEIER4) +#define INT5PL 2 // Group5 Interrupts (PIEIER5) +#define INT6PL 3 // Group6 Interrupts (PIEIER6) +#define INT7PL 0 // reserved +#define INT8PL 0 // reserved +#define INT9PL 3 // Group9 Interrupts (PIEIER9) +#define INT10PL 0 // reserved +#define INT11PL 0 // reserved +#define INT12PL 0 // reserved +#define INT13PL 4 // XINT13 +#define INT14PL 4 // INT14 (TINT2) +#define INT15PL 4 // DATALOG +#define INT16PL 4 // RTOSINT + +// +// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers): +// +// The user must set the appropriate priority level for each of the PIE +// interrupts. This is termed as the "group" priority. The priority level +// must be a number between 1 (highest) to 8 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used: +// +// Note: The priority levels below are used to calculate the following +// PIEIER register interrupt masks: +// MG11 to MG18 +// MG21 to MG28 +// MG31 to MG38 +// MG41 to MG48 +// MG51 to MG58 +// MG61 to MG68 +// MG71 to MG78 +// MG81 to MG88 +// MG91 to MG98 +// MG101 to MG108 +// MG111 to MG118 +// MG121 to MG128 +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 8 = lowest priority +// +#define G11PL 7 // SEQ1INT (ADC) +#define G12PL 6 // SEQ2INT (ADC) +#define G13PL 0 // reserved +#define G14PL 1 // XINT1 (External) +#define G15PL 3 // XINT2 (External) +#define G16PL 2 // ADCINT (ADC) +#define G17PL 1 // TINT0 (CPU Timer 0) +#define G18PL 5 // WAKEINT (WD/LPM) + +#define G21PL 4 // EPWM1_TZINT (ePWM1 Trip) +#define G22PL 3 // EPWM2_TZINT (ePWM2 Trip) +#define G23PL 2 // EPWM3_TZINT (ePWM3 Trip) +#define G24PL 1 // EPWM4_TZINT (ePWM4 Trip) +#define G25PL 5 // EPWM5_TZINT (ePWM5 Trip) +#define G26PL 6 // EPWM6_TZINT (ePWM6 Trip) +#define G27PL 0 // reserved +#define G28PL 0 // reserved + +#define G31PL 4 // EPWM1_INT (ePWM1 Int) +#define G32PL 1 // EPWM2_INT (ePWM2 Int) +#define G33PL 1 // EPWM3_INT (ePWM3 Int) +#define G34PL 2 // EPWM4_INT (ePWM4 Int) +#define G35PL 2 // EPWM5_INT (ePWM5 Int) +#define G36PL 1 // EPWM6_INT (ePWM6 Int) +#define G37PL 0 // reserved +#define G38PL 0 // reserved + +#define G41PL 2 // ECAP1_INT (eCAP1 Int) +#define G42PL 1 // ECAP2_INT (eCAP2 Int) +#define G43PL 3 // ECAP3_INT (eCAP3 Int) +#define G44PL 3 // ECAP4_INT (eCAP4 Int) +#define G45PL 5 // ECAP5_INT (eCAP5 Int) +#define G46PL 5 // ECAP6_INT (eCAP6 Int) +#define G47PL 0 // reserved +#define G48PL 0 // reserved + +#define G51PL 2 // EQEP1_INT (eQEP1 Int) +#define G52PL 1 // EQEP2_INT (eQEP2 Int) +#define G53PL 0 // reserved +#define G54PL 0 // reserved +#define G55PL 0 // reserved +#define G56PL 0 // reserved +#define G57PL 0 // reserved +#define G58PL 0 // reserved + +#define G61PL 3 // SPIRXINTA (SPI-A) +#define G62PL 1 // SPITXINTA (SPI-A) +#define G63PL 4 // MRINTB (McBSP-B) +#define G64PL 6 // MXINTB (McBSP-B) +#define G65PL 2 // MRINTA (McBSP-A) +#define G66PL 1 // MXINTA (McBSP-A) +#define G67PL 0 // reserved +#define G68PL 0 // reserved + +#define G71PL 5 // DINTCH1 (DMA) +#define G72PL 4 // DINTCH2 (DMA) +#define G73PL 4 // DINTCH3 (DMA) +#define G74PL 2 // DINTCH4 (DMA) +#define G75PL 3 // DINTCH5 (DMA) +#define G76PL 1 // DINTCH6 (DMA) +#define G77PL 0 // reserved +#define G78PL 0 // reserved + +#define G81PL 1 // I2CINT1A (I2C-A) +#define G82PL 2 // I2CINT2A (I2C-A) +#define G83PL 0 // reserved +#define G84PL 0 // reserved +#define G85PL 4 // SCIRXINTC (SCI-C) +#define G86PL 3 // SCITXINTC (SCI-C) +#define G87PL 0 // reserved +#define G88PL 0 // reserved + +#define G91PL 1 // SCIRXINTA (SCI-A) +#define G92PL 5 // SCITXINTA (SCI-A) +#define G93PL 3 // SCIRXINTB (SCI-B) +#define G94PL 4 // SCITXINTB (SCI-B) +#define G95PL 1 // ECAN0INTA (ECAN-A) +#define G96PL 1 // ECAN1INTA (ECAN-A) +#define G97PL 2 // ECAN0INTB (ECAN-B) +#define G98PL 4 // ECAN1INTB (ECAN-B) + +#define G101PL 0 // reserved +#define G102PL 0 // reserved +#define G103PL 0 // reserved +#define G104PL 0 // reserved +#define G105PL 0 // reserved +#define G106PL 0 // reserved +#define G107PL 0 // reserved +#define G108PL 0 // reserved + +#define G111PL 0 // reserved +#define G112PL 0 // reserved +#define G113PL 0 // reserved +#define G114PL 0 // reserved +#define G115PL 0 // reserved +#define G116PL 0 // reserved +#define G117PL 0 // reserved +#define G118PL 0 // reserved + +#define G121PL 5 // XINT3 (External) +#define G122PL 3 // XINT4 (External) +#define G123PL 2 // XINT5 (External) +#define G124PL 2 // XINT6 (External) +#define G125PL 1 // XINT7 (External) +#define G126PL 0 // reserved +#define G127PL 6 // LVF (FPA32) +#define G128PL 1 // LUF (FPA32) + +// +// There should be no need to modify code below this line +// +// Automatically generate IER interrupt masks MINT1 to MINT16: +// + +// +// Beginning of MINT1: +// +#if (INT1PL == 0) +#define MINT1_1PL ~(1 << 0) +#else +#define MINT1_1PL 0xFFFF +#endif + +#if (INT2PL >= INT1PL) || (INT2PL == 0) +#define MINT1_2PL ~(1 << 1) +#else +#define MINT1_2PL 0xFFFF +#endif + +#if (INT3PL >= INT1PL) || (INT3PL == 0) +#define MINT1_3PL ~(1 << 2) +#else +#define MINT1_3PL 0xFFFF +#endif + +#if (INT4PL >= INT1PL) || (INT4PL == 0) +#define MINT1_4PL ~(1 << 3) +#else +#define MINT1_4PL 0xFFFF +#endif + +#if (INT5PL >= INT1PL) || (INT5PL == 0) +#define MINT1_5PL ~(1 << 4) +#else +#define MINT1_5PL 0xFFFF +#endif + +#if (INT6PL >= INT1PL) || (INT6PL == 0) +#define MINT1_6PL ~(1 << 5) +#else +#define MINT1_6PL 0xFFFF +#endif + +#if (INT7PL >= INT1PL) || (INT7PL == 0) +#define MINT1_7PL ~(1 << 6) +#else +#define MINT1_7PL 0xFFFF +#endif + +#if (INT8PL >= INT1PL) || (INT8PL == 0) +#define MINT1_8PL ~(1 << 7) +#else +#define MINT1_8PL 0xFFFF +#endif + +#if (INT9PL >= INT1PL) || (INT9PL == 0) +#define MINT1_9PL ~(1 << 8) +#else +#define MINT1_9PL 0xFFFF +#endif + +#if (INT10PL >= INT1PL) || (INT10PL == 0) +#define MINT1_10PL ~(1 << 9) +#else +#define MINT1_10PL 0xFFFF +#endif + +#if (INT11PL >= INT1PL) || (INT11PL == 0) +#define MINT1_11PL ~(1 << 10) +#else +#define MINT1_11PL 0xFFFF +#endif + +#if (INT12PL >= INT1PL) || (INT12PL == 0) +#define MINT1_12PL ~(1 << 11) +#else +#define MINT1_12PL 0xFFFF +#endif + +#if (INT13PL >= INT1PL) || (INT13PL == 0) +#define MINT1_13PL ~(1 << 12) +#else +#define MINT1_13PL 0xFFFF +#endif + +#if (INT14PL >= INT1PL) || (INT14PL == 0) +#define MINT1_14PL ~(1 << 13) +#else +#define MINT1_14PL 0xFFFF +#endif + +#if (INT15PL >= INT1PL) || (INT15PL == 0) +#define MINT1_15PL ~(1 << 14) +#else +#define MINT1_15PL 0xFFFF +#endif + +#if (INT16PL >= INT1PL) || (INT16PL == 0) +#define MINT1_16PL ~(1 << 15) +#else +#define MINT1_16PL 0xFFFF +#endif + +#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \ + MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \ + MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \ + MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL) + +// +// Beginning of MINT2: +// +#if (INT1PL >= INT2PL) || (INT1PL == 0) +#define MINT2_1PL ~(1 << 0) +#else +#define MINT2_1PL 0xFFFF +#endif + +#if (INT2PL == 0) +#define MINT2_2PL ~(1 << 1) +#else +#define MINT2_2PL 0xFFFF +#endif + +#if (INT3PL >= INT2PL) || (INT3PL == 0) +#define MINT2_3PL ~(1 << 2) +#else +#define MINT2_3PL 0xFFFF +#endif + +#if (INT4PL >= INT2PL) || (INT4PL == 0) +#define MINT2_4PL ~(1 << 3) +#else +#define MINT2_4PL 0xFFFF +#endif + +#if (INT5PL >= INT2PL) || (INT5PL == 0) +#define MINT2_5PL ~(1 << 4) +#else +#define MINT2_5PL 0xFFFF +#endif + +#if (INT6PL >= INT2PL) || (INT6PL == 0) +#define MINT2_6PL ~(1 << 5) +#else +#define MINT2_6PL 0xFFFF +#endif + +#if (INT7PL >= INT2PL) || (INT7PL == 0) +#define MINT2_7PL ~(1 << 6) +#else +#define MINT2_7PL 0xFFFF +#endif + +#if (INT8PL >= INT2PL) || (INT8PL == 0) +#define MINT2_8PL ~(1 << 7) +#else +#define MINT2_8PL 0xFFFF +#endif + +#if (INT9PL >= INT2PL) || (INT9PL == 0) +#define MINT2_9PL ~(1 << 8) +#else +#define MINT2_9PL 0xFFFF +#endif + +#if (INT10PL >= INT2PL) || (INT10PL == 0) +#define MINT2_10PL ~(1 << 9) +#else +#define MINT2_10PL 0xFFFF +#endif + +#if (INT11PL >= INT2PL) || (INT11PL == 0) +#define MINT2_11PL ~(1 << 10) +#else +#define MINT2_11PL 0xFFFF +#endif + +#if (INT12PL >= INT2PL) || (INT12PL == 0) +#define MINT2_12PL ~(1 << 11) +#else +#define MINT2_12PL 0xFFFF +#endif + +#if (INT13PL >= INT2PL) || (INT13PL == 0) +#define MINT2_13PL ~(1 << 12) +#else +#define MINT2_13PL 0xFFFF +#endif + +#if (INT14PL >= INT2PL) || (INT14PL == 0) +#define MINT2_14PL ~(1 << 13) +#else +#define MINT2_14PL 0xFFFF +#endif + +#if (INT15PL >= INT2PL) || (INT15PL == 0) +#define MINT2_15PL ~(1 << 14) +#else +#define MINT2_15PL 0xFFFF +#endif + +#if (INT16PL >= INT2PL) || (INT16PL == 0) +#define MINT2_16PL ~(1 << 15) +#else +#define MINT2_16PL 0xFFFF +#endif + +#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \ + MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \ + MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \ + MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL) + +// +// Beginning of MINT3: +// +#if (INT1PL >= INT3PL) || (INT1PL == 0) +#define MINT3_1PL ~(1 << 0) +#else +#define MINT3_1PL 0xFFFF +#endif + +#if (INT2PL >= INT3PL) || (INT2PL == 0) +#define MINT3_2PL ~(1 << 1) +#else +#define MINT3_2PL 0xFFFF +#endif + +#if (INT3PL == 0) +#define MINT3_3PL ~(1 << 2) +#else +#define MINT3_3PL 0xFFFF +#endif + +#if (INT4PL >= INT3PL) || (INT4PL == 0) +#define MINT3_4PL ~(1 << 3) +#else +#define MINT3_4PL 0xFFFF +#endif + +#if (INT5PL >= INT3PL) || (INT5PL == 0) +#define MINT3_5PL ~(1 << 4) +#else +#define MINT3_5PL 0xFFFF +#endif + +#if (INT6PL >= INT3PL) || (INT6PL == 0) +#define MINT3_6PL ~(1 << 5) +#else +#define MINT3_6PL 0xFFFF +#endif + +#if (INT7PL >= INT3PL) || (INT7PL == 0) +#define MINT3_7PL ~(1 << 6) +#else +#define MINT3_7PL 0xFFFF +#endif + +#if (INT8PL >= INT3PL) || (INT8PL == 0) +#define MINT3_8PL ~(1 << 7) +#else +#define MINT3_8PL 0xFFFF +#endif + +#if (INT9PL >= INT3PL) || (INT9PL == 0) +#define MINT3_9PL ~(1 << 8) +#else +#define MINT3_9PL 0xFFFF +#endif + +#if (INT10PL >= INT3PL) || (INT10PL == 0) +#define MINT3_10PL ~(1 << 9) +#else +#define MINT3_10PL 0xFFFF +#endif + +#if (INT11PL >= INT3PL) || (INT11PL == 0) +#define MINT3_11PL ~(1 << 10) +#else +#define MINT3_11PL 0xFFFF +#endif + +#if (INT12PL >= INT3PL) || (INT12PL == 0) +#define MINT3_12PL ~(1 << 11) +#else +#define MINT3_12PL 0xFFFF +#endif + +#if (INT13PL >= INT3PL) || (INT13PL == 0) +#define MINT3_13PL ~(1 << 12) +#else +#define MINT3_13PL 0xFFFF +#endif + +#if (INT14PL >= INT3PL) || (INT14PL == 0) +#define MINT3_14PL ~(1 << 13) +#else +#define MINT3_14PL 0xFFFF +#endif + +#if (INT15PL >= INT3PL) || (INT15PL == 0) +#define MINT3_15PL ~(1 << 14) +#else +#define MINT3_15PL 0xFFFF +#endif + +#if (INT16PL >= INT3PL) || (INT16PL == 0) +#define MINT3_16PL ~(1 << 15) +#else +#define MINT3_16PL 0xFFFF +#endif + +#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \ + MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \ + MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \ + MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL) + +// +// Beginning of MINT4: +// +#if (INT1PL >= INT4PL) || (INT1PL == 0) +#define MINT4_1PL ~(1 << 0) +#else +#define MINT4_1PL 0xFFFF +#endif + +#if (INT2PL >= INT4PL) || (INT2PL == 0) +#define MINT4_2PL ~(1 << 1) +#else +#define MINT4_2PL 0xFFFF +#endif + +#if (INT3PL >= INT4PL) || (INT3PL == 0) +#define MINT4_3PL ~(1 << 2) +#else +#define MINT4_3PL 0xFFFF +#endif + +#if (INT4PL == 0) +#define MINT4_4PL ~(1 << 3) +#else +#define MINT4_4PL 0xFFFF +#endif + +#if (INT5PL >= INT4PL) || (INT5PL == 0) +#define MINT4_5PL ~(1 << 4) +#else +#define MINT4_5PL 0xFFFF +#endif + +#if (INT6PL >= INT4PL) || (INT6PL == 0) +#define MINT4_6PL ~(1 << 5) +#else +#define MINT4_6PL 0xFFFF +#endif + +#if (INT7PL >= INT4PL) || (INT7PL == 0) +#define MINT4_7PL ~(1 << 6) +#else +#define MINT4_7PL 0xFFFF +#endif + +#if (INT8PL >= INT4PL) || (INT8PL == 0) +#define MINT4_8PL ~(1 << 7) +#else +#define MINT4_8PL 0xFFFF +#endif + +#if (INT9PL >= INT4PL) || (INT9PL == 0) +#define MINT4_9PL ~(1 << 8) +#else +#define MINT4_9PL 0xFFFF +#endif + +#if (INT10PL >= INT4PL) || (INT10PL == 0) +#define MINT4_10PL ~(1 << 9) +#else +#define MINT4_10PL 0xFFFF +#endif + +#if (INT11PL >= INT4PL) || (INT11PL == 0) +#define MINT4_11PL ~(1 << 10) +#else +#define MINT4_11PL 0xFFFF +#endif + +#if (INT12PL >= INT4PL) || (INT12PL == 0) +#define MINT4_12PL ~(1 << 11) +#else +#define MINT4_12PL 0xFFFF +#endif + +#if (INT13PL >= INT4PL) || (INT13PL == 0) +#define MINT4_13PL ~(1 << 12) +#else +#define MINT4_13PL 0xFFFF +#endif + +#if (INT14PL >= INT4PL) || (INT14PL == 0) +#define MINT4_14PL ~(1 << 13) +#else +#define MINT4_14PL 0xFFFF +#endif + +#if (INT15PL >= INT4PL) || (INT15PL == 0) +#define MINT4_15PL ~(1 << 14) +#else +#define MINT4_15PL 0xFFFF +#endif + +#if (INT16PL >= INT4PL) || (INT16PL == 0) +#define MINT4_16PL ~(1 << 15) +#else +#define MINT4_16PL 0xFFFF +#endif + +#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \ + MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \ + MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \ + MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL) + +// +// Beginning of MINT5: +// +#if (INT1PL >= INT5PL) || (INT1PL == 0) +#define MINT5_1PL ~(1 << 0) +#else +#define MINT5_1PL 0xFFFF +#endif + +#if (INT2PL >= INT5PL) || (INT2PL == 0) +#define MINT5_2PL ~(1 << 1) +#else +#define MINT5_2PL 0xFFFF +#endif + +#if (INT3PL >= INT5PL) || (INT3PL == 0) +#define MINT5_3PL ~(1 << 2) +#else +#define MINT5_3PL 0xFFFF +#endif + +#if (INT4PL >= INT5PL) || (INT4PL == 0) +#define MINT5_4PL ~(1 << 3) +#else +#define MINT5_4PL 0xFFFF +#endif + +#if (INT5PL == 0) +#define MINT5_5PL ~(1 << 4) +#else +#define MINT5_5PL 0xFFFF +#endif + +#if (INT6PL >= INT5PL) || (INT6PL == 0) +#define MINT5_6PL ~(1 << 5) +#else +#define MINT5_6PL 0xFFFF +#endif + +#if (INT7PL >= INT5PL) || (INT7PL == 0) +#define MINT5_7PL ~(1 << 6) +#else +#define MINT5_7PL 0xFFFF +#endif + +#if (INT8PL >= INT5PL) || (INT8PL == 0) +#define MINT5_8PL ~(1 << 7) +#else +#define MINT5_8PL 0xFFFF +#endif + +#if (INT9PL >= INT5PL) || (INT9PL == 0) +#define MINT5_9PL ~(1 << 8) +#else +#define MINT5_9PL 0xFFFF +#endif + +#if (INT10PL >= INT5PL) || (INT10PL == 0) +#define MINT5_10PL ~(1 << 9) +#else +#define MINT5_10PL 0xFFFF +#endif + +#if (INT11PL >= INT5PL) || (INT11PL == 0) +#define MINT5_11PL ~(1 << 10) +#else +#define MINT5_11PL 0xFFFF +#endif + +#if (INT12PL >= INT5PL) || (INT12PL == 0) +#define MINT5_12PL ~(1 << 11) +#else +#define MINT5_12PL 0xFFFF +#endif + +#if (INT13PL >= INT5PL) || (INT13PL == 0) +#define MINT5_13PL ~(1 << 12) +#else +#define MINT5_13PL 0xFFFF +#endif + +#if (INT14PL >= INT5PL) || (INT14PL == 0) +#define MINT5_14PL ~(1 << 13) +#else +#define MINT5_14PL 0xFFFF +#endif + +#if (INT15PL >= INT5PL) || (INT15PL == 0) +#define MINT5_15PL ~(1 << 14) +#else +#define MINT5_15PL 0xFFFF +#endif + +#if (INT16PL >= INT5PL) || (INT16PL == 0) +#define MINT5_16PL ~(1 << 15) +#else +#define MINT5_16PL 0xFFFF +#endif + +#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \ + MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \ + MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \ + MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL) + +// +// Beginning of MINT6: +// +#if (INT1PL >= INT6PL) || (INT1PL == 0) +#define MINT6_1PL ~(1 << 0) +#else +#define MINT6_1PL 0xFFFF +#endif + +#if (INT2PL >= INT6PL) || (INT2PL == 0) +#define MINT6_2PL ~(1 << 1) +#else +#define MINT6_2PL 0xFFFF +#endif + +#if (INT3PL >= INT6PL) || (INT3PL == 0) +#define MINT6_3PL ~(1 << 2) +#else +#define MINT6_3PL 0xFFFF +#endif + +#if (INT4PL >= INT6PL) || (INT4PL == 0) +#define MINT6_4PL ~(1 << 3) +#else +#define MINT6_4PL 0xFFFF +#endif + +#if (INT5PL >= INT6PL) || (INT5PL == 0) +#define MINT6_5PL ~(1 << 4) +#else +#define MINT6_5PL 0xFFFF +#endif + +#if (INT6PL == 0) +#define MINT6_6PL ~(1 << 5) +#else +#define MINT6_6PL 0xFFFF +#endif + +#if (INT7PL >= INT6PL) || (INT7PL == 0) +#define MINT6_7PL ~(1 << 6) +#else +#define MINT6_7PL 0xFFFF +#endif + +#if (INT8PL >= INT6PL) || (INT8PL == 0) +#define MINT6_8PL ~(1 << 7) +#else +#define MINT6_8PL 0xFFFF +#endif + +#if (INT9PL >= INT6PL) || (INT9PL == 0) +#define MINT6_9PL ~(1 << 8) +#else +#define MINT6_9PL 0xFFFF +#endif + +#if (INT10PL >= INT6PL) || (INT10PL == 0) +#define MINT6_10PL ~(1 << 9) +#else +#define MINT6_10PL 0xFFFF +#endif + +#if (INT11PL >= INT6PL) || (INT11PL == 0) +#define MINT6_11PL ~(1 << 10) +#else +#define MINT6_11PL 0xFFFF +#endif + +#if (INT12PL >= INT6PL) || (INT12PL == 0) +#define MINT6_12PL ~(1 << 11) +#else +#define MINT6_12PL 0xFFFF +#endif + +#if (INT13PL >= INT6PL) || (INT13PL == 0) +#define MINT6_13PL ~(1 << 12) +#else +#define MINT6_13PL 0xFFFF +#endif + +#if (INT14PL >= INT6PL) || (INT14PL == 0) +#define MINT6_14PL ~(1 << 13) +#else +#define MINT6_14PL 0xFFFF +#endif + +#if (INT15PL >= INT6PL) || (INT15PL == 0) +#define MINT6_15PL ~(1 << 14) +#else +#define MINT6_15PL 0xFFFF +#endif + +#if (INT16PL >= INT6PL) || (INT16PL == 0) +#define MINT6_16PL ~(1 << 15) +#else +#define MINT6_16PL 0xFFFF +#endif + +#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \ + MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \ + MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \ + MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL) + +// +// Beginning of MINT7: +// +#if (INT1PL >= INT7PL) || (INT1PL == 0) +#define MINT7_1PL ~(1 << 0) +#else +#define MINT7_1PL 0xFFFF +#endif + +#if (INT2PL >= INT7PL) || (INT2PL == 0) +#define MINT7_2PL ~(1 << 1) +#else +#define MINT7_2PL 0xFFFF +#endif + +#if (INT3PL >= INT7PL) || (INT3PL == 0) +#define MINT7_3PL ~(1 << 2) +#else +#define MINT7_3PL 0xFFFF +#endif + +#if (INT4PL >= INT7PL) || (INT4PL == 0) +#define MINT7_4PL ~(1 << 3) +#else +#define MINT7_4PL 0xFFFF +#endif + +#if (INT5PL >= INT7PL) || (INT5PL == 0) +#define MINT7_5PL ~(1 << 4) +#else +#define MINT7_5PL 0xFFFF +#endif + +#if (INT6PL >= INT7PL) || (INT6PL == 0) +#define MINT7_6PL ~(1 << 5) +#else +#define MINT7_6PL 0xFFFF +#endif + +#if (INT7PL == 0) +#define MINT7_7PL ~(1 << 6) +#else +#define MINT7_7PL 0xFFFF +#endif + +#if (INT8PL >= INT7PL) || (INT8PL == 0) +#define MINT7_8PL ~(1 << 7) +#else +#define MINT7_8PL 0xFFFF +#endif + +#if (INT9PL >= INT7PL) || (INT9PL == 0) +#define MINT7_9PL ~(1 << 8) +#else +#define MINT7_9PL 0xFFFF +#endif + +#if (INT10PL >= INT7PL) || (INT10PL == 0) +#define MINT7_10PL ~(1 << 9) +#else +#define MINT7_10PL 0xFFFF +#endif + +#if (INT11PL >= INT7PL) || (INT11PL == 0) +#define MINT7_11PL ~(1 << 10) +#else +#define MINT7_11PL 0xFFFF +#endif + +#if (INT12PL >= INT7PL) || (INT12PL == 0) +#define MINT7_12PL ~(1 << 11) +#else +#define MINT7_12PL 0xFFFF +#endif + +#if (INT13PL >= INT7PL) || (INT13PL == 0) +#define MINT7_13PL ~(1 << 12) +#else +#define MINT7_13PL 0xFFFF +#endif + +#if (INT14PL >= INT7PL) || (INT14PL == 0) +#define MINT7_14PL ~(1 << 13) +#else +#define MINT7_14PL 0xFFFF +#endif + +#if (INT15PL >= INT7PL) || (INT15PL == 0) +#define MINT7_15PL ~(1 << 14) +#else +#define MINT7_15PL 0xFFFF +#endif + +#if (INT16PL >= INT7PL) || (INT16PL == 0) +#define MINT7_16PL ~(1 << 15) +#else +#define MINT7_16PL 0xFFFF +#endif + +#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \ + MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \ + MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \ + MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL) + +// +// Beginning of MINT8: +// +#if (INT1PL >= INT8PL) || (INT1PL == 0) +#define MINT8_1PL ~(1 << 0) +#else +#define MINT8_1PL 0xFFFF +#endif + +#if (INT2PL >= INT8PL) || (INT2PL == 0) +#define MINT8_2PL ~(1 << 1) +#else +#define MINT8_2PL 0xFFFF +#endif + +#if (INT3PL >= INT8PL) || (INT3PL == 0) +#define MINT8_3PL ~(1 << 2) +#else +#define MINT8_3PL 0xFFFF +#endif + +#if (INT4PL >= INT8PL) || (INT4PL == 0) +#define MINT8_4PL ~(1 << 3) +#else +#define MINT8_4PL 0xFFFF +#endif + +#if (INT5PL >= INT8PL) || (INT5PL == 0) +#define MINT8_5PL ~(1 << 4) +#else +#define MINT8_5PL 0xFFFF +#endif + +#if (INT6PL >= INT8PL) || (INT6PL == 0) +#define MINT8_6PL ~(1 << 5) +#else +#define MINT8_6PL 0xFFFF +#endif + +#if (INT7PL >= INT8PL) || (INT7PL == 0) +#define MINT8_7PL ~(1 << 6) +#else +#define MINT8_7PL 0xFFFF +#endif + +#if (INT8PL == 0) +#define MINT8_8PL ~(1 << 7) +#else +#define MINT8_8PL 0xFFFF +#endif + +#if (INT9PL >= INT8PL) || (INT9PL == 0) +#define MINT8_9PL ~(1 << 8) +#else +#define MINT8_9PL 0xFFFF +#endif + +#if (INT10PL >= INT8PL) || (INT10PL == 0) +#define MINT8_10PL ~(1 << 9) +#else +#define MINT8_10PL 0xFFFF +#endif + +#if (INT11PL >= INT8PL) || (INT11PL == 0) +#define MINT8_11PL ~(1 << 10) +#else +#define MINT8_11PL 0xFFFF +#endif + +#if (INT12PL >= INT8PL) || (INT12PL == 0) +#define MINT8_12PL ~(1 << 11) +#else +#define MINT8_12PL 0xFFFF +#endif + +#if (INT13PL >= INT8PL) || (INT13PL == 0) +#define MINT8_13PL ~(1 << 12) +#else +#define MINT8_13PL 0xFFFF +#endif + +#if (INT14PL >= INT8PL) || (INT14PL == 0) +#define MINT8_14PL ~(1 << 13) +#else +#define MINT8_14PL 0xFFFF +#endif + +#if (INT15PL >= INT8PL) || (INT15PL == 0) +#define MINT8_15PL ~(1 << 14) +#else +#define MINT8_15PL 0xFFFF +#endif + +#if (INT16PL >= INT8PL) || (INT16PL == 0) +#define MINT8_16PL ~(1 << 15) +#else +#define MINT8_16PL 0xFFFF +#endif + +#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \ + MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \ + MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \ + MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL) + +// +// Beginning of MINT9: +// +#if (INT1PL >= INT9PL) || (INT1PL == 0) +#define MINT9_1PL ~(1 << 0) +#else +#define MINT9_1PL 0xFFFF +#endif + +#if (INT2PL >= INT9PL) || (INT2PL == 0) +#define MINT9_2PL ~(1 << 1) +#else +#define MINT9_2PL 0xFFFF +#endif + +#if (INT3PL >= INT9PL) || (INT3PL == 0) +#define MINT9_3PL ~(1 << 2) +#else +#define MINT9_3PL 0xFFFF +#endif + +#if (INT4PL >= INT9PL) || (INT4PL == 0) +#define MINT9_4PL ~(1 << 3) +#else +#define MINT9_4PL 0xFFFF +#endif + +#if (INT5PL >= INT9PL) || (INT5PL == 0) +#define MINT9_5PL ~(1 << 4) +#else +#define MINT9_5PL 0xFFFF +#endif + +#if (INT6PL >= INT9PL) || (INT6PL == 0) +#define MINT9_6PL ~(1 << 5) +#else +#define MINT9_6PL 0xFFFF +#endif + +#if (INT7PL >= INT9PL) || (INT7PL == 0) +#define MINT9_7PL ~(1 << 6) +#else +#define MINT9_7PL 0xFFFF +#endif + +#if (INT8PL >= INT9PL) || (INT8PL == 0) +#define MINT9_8PL ~(1 << 7) +#else +#define MINT9_8PL 0xFFFF +#endif + +#if (INT9PL == 0) +#define MINT9_9PL ~(1 << 8) +#else +#define MINT9_9PL 0xFFFF +#endif + +#if (INT10PL >= INT9PL) || (INT10PL == 0) +#define MINT9_10PL ~(1 << 9) +#else +#define MINT9_10PL 0xFFFF +#endif + +#if (INT11PL >= INT9PL) || (INT11PL == 0) +#define MINT9_11PL ~(1 << 10) +#else +#define MINT9_11PL 0xFFFF +#endif + +#if (INT12PL >= INT9PL) || (INT12PL == 0) +#define MINT9_12PL ~(1 << 11) +#else +#define MINT9_12PL 0xFFFF +#endif + +#if (INT13PL >= INT9PL) || (INT13PL == 0) +#define MINT9_13PL ~(1 << 12) +#else +#define MINT9_13PL 0xFFFF +#endif + +#if (INT14PL >= INT9PL) || (INT14PL == 0) +#define MINT9_14PL ~(1 << 13) +#else +#define MINT9_14PL 0xFFFF +#endif + +#if (INT15PL >= INT9PL) || (INT15PL == 0) +#define MINT9_15PL ~(1 << 14) +#else +#define MINT9_15PL 0xFFFF +#endif + +#if (INT16PL >= INT9PL) || (INT16PL == 0) +#define MINT9_16PL ~(1 << 15) +#else +#define MINT9_16PL 0xFFFF +#endif + +#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \ + MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \ + MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \ + MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL) + +// +// Beginning of MINT10: +// +#if (INT1PL >= INT10PL) || (INT1PL == 0) +#define MINT10_1PL ~(1 << 0) +#else +#define MINT10_1PL 0xFFFF +#endif + +#if (INT2PL >= INT10PL) || (INT2PL == 0) +#define MINT10_2PL ~(1 << 1) +#else +#define MINT10_2PL 0xFFFF +#endif + +#if (INT3PL >= INT10PL) || (INT3PL == 0) +#define MINT10_3PL ~(1 << 2) +#else +#define MINT10_3PL 0xFFFF +#endif + +#if (INT4PL >= INT10PL) || (INT4PL == 0) +#define MINT10_4PL ~(1 << 3) +#else +#define MINT10_4PL 0xFFFF +#endif + +#if (INT5PL >= INT10PL) || (INT5PL == 0) +#define MINT10_5PL ~(1 << 4) +#else +#define MINT10_5PL 0xFFFF +#endif + +#if (INT6PL >= INT10PL) || (INT6PL == 0) +#define MINT10_6PL ~(1 << 5) +#else +#define MINT10_6PL 0xFFFF +#endif + +#if (INT7PL >= INT10PL) || (INT7PL == 0) +#define MINT10_7PL ~(1 << 6) +#else +#define MINT10_7PL 0xFFFF +#endif + +#if (INT8PL >= INT10PL) || (INT8PL == 0) +#define MINT10_8PL ~(1 << 7) +#else +#define MINT10_8PL 0xFFFF +#endif + +#if (INT9PL >= INT10PL) || (INT9PL == 0) +#define MINT10_9PL ~(1 << 8) +#else +#define MINT10_9PL 0xFFFF +#endif + +#if (INT10PL == 0) +#define MINT10_10PL ~(1 << 9) +#else +#define MINT10_10PL 0xFFFF +#endif + +#if (INT11PL >= INT10PL) || (INT11PL == 0) +#define MINT10_11PL ~(1 << 10) +#else +#define MINT10_11PL 0xFFFF +#endif + +#if (INT12PL >= INT10PL) || (INT12PL == 0) +#define MINT10_12PL ~(1 << 11) +#else +#define MINT10_12PL 0xFFFF +#endif + +#if (INT13PL >= INT10PL) || (INT13PL == 0) +#define MINT10_13PL ~(1 << 12) +#else +#define MINT10_13PL 0xFFFF +#endif + +#if (INT14PL >= INT10PL) || (INT14PL == 0) +#define MINT10_14PL ~(1 << 13) +#else +#define MINT10_14PL 0xFFFF +#endif + +#if (INT15PL >= INT10PL) || (INT15PL == 0) +#define MINT10_15PL ~(1 << 14) +#else +#define MINT10_15PL 0xFFFF +#endif + +#if (INT16PL >= INT10PL) || (INT16PL == 0) +#define MINT10_16PL ~(1 << 15) +#else +#define MINT10_16PL 0xFFFF +#endif + +#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \ + MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \ + MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \ + MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL) + +// +// Beginning of MINT11: +// +#if (INT1PL >= INT11PL) || (INT1PL == 0) +#define MINT11_1PL ~(1 << 0) +#else +#define MINT11_1PL 0xFFFF +#endif + +#if (INT2PL >= INT11PL) || (INT2PL == 0) +#define MINT11_2PL ~(1 << 1) +#else +#define MINT11_2PL 0xFFFF +#endif + +#if (INT3PL >= INT11PL) || (INT3PL == 0) +#define MINT11_3PL ~(1 << 2) +#else +#define MINT11_3PL 0xFFFF +#endif + +#if (INT4PL >= INT11PL) || (INT4PL == 0) +#define MINT11_4PL ~(1 << 3) +#else +#define MINT11_4PL 0xFFFF +#endif + +#if (INT5PL >= INT11PL) || (INT5PL == 0) +#define MINT11_5PL ~(1 << 4) +#else +#define MINT11_5PL 0xFFFF +#endif + +#if (INT6PL >= INT11PL) || (INT6PL == 0) +#define MINT11_6PL ~(1 << 5) +#else +#define MINT11_6PL 0xFFFF +#endif + +#if (INT7PL >= INT11PL) || (INT7PL == 0) +#define MINT11_7PL ~(1 << 6) +#else +#define MINT11_7PL 0xFFFF +#endif + +#if (INT8PL >= INT11PL) || (INT8PL == 0) +#define MINT11_8PL ~(1 << 7) +#else +#define MINT11_8PL 0xFFFF +#endif + +#if (INT9PL >= INT11PL) || (INT9PL == 0) +#define MINT11_9PL ~(1 << 8) +#else +#define MINT11_9PL 0xFFFF +#endif + +#if (INT10PL >= INT11PL) || (INT10PL == 0) +#define MINT11_10PL ~(1 << 9) +#else +#define MINT11_10PL 0xFFFF +#endif + +#if (INT11PL == 0) +#define MINT11_11PL ~(1 << 10) +#else +#define MINT11_11PL 0xFFFF +#endif + +#if (INT12PL >= INT11PL) || (INT12PL == 0) +#define MINT11_12PL ~(1 << 11) +#else +#define MINT11_12PL 0xFFFF +#endif + +#if (INT13PL >= INT11PL) || (INT13PL == 0) +#define MINT11_13PL ~(1 << 12) +#else +#define MINT11_13PL 0xFFFF +#endif + +#if (INT14PL >= INT11PL) || (INT14PL == 0) +#define MINT11_14PL ~(1 << 13) +#else +#define MINT11_14PL 0xFFFF +#endif + +#if (INT15PL >= INT11PL) || (INT15PL == 0) +#define MINT11_15PL ~(1 << 14) +#else +#define MINT11_15PL 0xFFFF +#endif + +#if (INT16PL >= INT11PL) || (INT16PL == 0) +#define MINT11_16PL ~(1 << 15) +#else +#define MINT11_16PL 0xFFFF +#endif + +#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \ + MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \ + MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \ + MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL) + +// +// Beginning of MINT12: +// +#if (INT1PL >= INT12PL) || (INT1PL == 0) +#define MINT12_1PL ~(1 << 0) +#else +#define MINT12_1PL 0xFFFF +#endif + +#if (INT2PL >= INT12PL) || (INT2PL == 0) +#define MINT12_2PL ~(1 << 1) +#else +#define MINT12_2PL 0xFFFF +#endif + +#if (INT3PL >= INT12PL) || (INT3PL == 0) +#define MINT12_3PL ~(1 << 2) +#else +#define MINT12_3PL 0xFFFF +#endif + +#if (INT4PL >= INT12PL) || (INT4PL == 0) +#define MINT12_4PL ~(1 << 3) +#else +#define MINT12_4PL 0xFFFF +#endif + +#if (INT5PL >= INT12PL) || (INT5PL == 0) +#define MINT12_5PL ~(1 << 4) +#else +#define MINT12_5PL 0xFFFF +#endif + +#if (INT6PL >= INT12PL) || (INT6PL == 0) +#define MINT12_6PL ~(1 << 5) +#else +#define MINT12_6PL 0xFFFF +#endif + +#if (INT7PL >= INT12PL) || (INT7PL == 0) +#define MINT12_7PL ~(1 << 6) +#else +#define MINT12_7PL 0xFFFF +#endif + +#if (INT8PL >= INT12PL) || (INT8PL == 0) +#define MINT12_8PL ~(1 << 7) +#else +#define MINT12_8PL 0xFFFF +#endif + +#if (INT9PL >= INT12PL) || (INT9PL == 0) +#define MINT12_9PL ~(1 << 8) +#else +#define MINT12_9PL 0xFFFF +#endif + +#if (INT10PL >= INT12PL) || (INT10PL == 0) +#define MINT12_10PL ~(1 << 9) +#else +#define MINT12_10PL 0xFFFF +#endif + +#if (INT11PL >= INT12PL) || (INT11PL == 0) +#define MINT12_11PL ~(1 << 10) +#else +#define MINT12_11PL 0xFFFF +#endif + +#if (INT12PL == 0) +#define MINT12_12PL ~(1 << 11) +#else +#define MINT12_12PL 0xFFFF +#endif + +#if (INT13PL >= INT12PL) || (INT13PL == 0) +#define MINT12_13PL ~(1 << 12) +#else +#define MINT12_13PL 0xFFFF +#endif + +#if (INT14PL >= INT12PL) || (INT14PL == 0) +#define MINT12_14PL ~(1 << 13) +#else +#define MINT12_14PL 0xFFFF +#endif + +#if (INT15PL >= INT12PL) || (INT15PL == 0) +#define MINT12_15PL ~(1 << 14) +#else +#define MINT12_15PL 0xFFFF +#endif + +#if (INT16PL >= INT12PL) || (INT16PL == 0) +#define MINT12_16PL ~(1 << 15) +#else +#define MINT12_16PL 0xFFFF +#endif + +#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \ + MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \ + MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \ + MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL) + +// +// Beginning of MINT13: +// +#if (INT1PL >= INT13PL) || (INT1PL == 0) +#define MINT13_1PL ~(1 << 0) +#else +#define MINT13_1PL 0xFFFF +#endif + +#if (INT2PL >= INT13PL) || (INT2PL == 0) +#define MINT13_2PL ~(1 << 1) +#else +#define MINT13_2PL 0xFFFF +#endif + +#if (INT3PL >= INT13PL) || (INT3PL == 0) +#define MINT13_3PL ~(1 << 2) +#else +#define MINT13_3PL 0xFFFF +#endif + +#if (INT4PL >= INT13PL) || (INT4PL == 0) +#define MINT13_4PL ~(1 << 3) +#else +#define MINT13_4PL 0xFFFF +#endif + +#if (INT5PL >= INT13PL) || (INT5PL == 0) +#define MINT13_5PL ~(1 << 4) +#else +#define MINT13_5PL 0xFFFF +#endif + +#if (INT6PL >= INT13PL) || (INT6PL == 0) +#define MINT13_6PL ~(1 << 5) +#else +#define MINT13_6PL 0xFFFF +#endif + +#if (INT7PL >= INT13PL) || (INT7PL == 0) +#define MINT13_7PL ~(1 << 6) +#else +#define MINT13_7PL 0xFFFF +#endif + +#if (INT8PL >= INT13PL) || (INT8PL == 0) +#define MINT13_8PL ~(1 << 7) +#else +#define MINT13_8PL 0xFFFF +#endif + +#if (INT9PL >= INT13PL) || (INT9PL == 0) +#define MINT13_9PL ~(1 << 8) +#else +#define MINT13_9PL 0xFFFF +#endif + +#if (INT10PL >= INT13PL) || (INT10PL == 0) +#define MINT13_10PL ~(1 << 9) +#else +#define MINT13_10PL 0xFFFF +#endif + +#if (INT11PL >= INT13PL) || (INT11PL == 0) +#define MINT13_11PL ~(1 << 10) +#else +#define MINT13_11PL 0xFFFF +#endif + +#define MINT13_12PL ~(1 << 11) + +#if (INT13PL == 0) +#define MINT13_13PL ~(1 << 12) +#else +#define MINT13_13PL 0xFFFF +#endif + +#if (INT14PL >= INT13PL) || (INT14PL == 0) +#define MINT13_14PL ~(1 << 13) +#else +#define MINT13_14PL 0xFFFF +#endif + +#if (INT15PL >= INT13PL) || (INT15PL == 0) +#define MINT13_15PL ~(1 << 14) +#else +#define MINT13_15PL 0xFFFF +#endif + +#if (INT16PL >= INT13PL) || (INT16PL == 0) +#define MINT13_16PL ~(1 << 15) +#else +#define MINT13_16PL 0xFFFF +#endif + +#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \ + MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \ + MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \ + MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL) + +// +// Beginning of MINT14: +// +#if (INT1PL >= INT14PL) || (INT1PL == 0) +#define MINT14_1PL ~(1 << 0) +#else +#define MINT14_1PL 0xFFFF +#endif + +#if (INT2PL >= INT14PL) || (INT2PL == 0) +#define MINT14_2PL ~(1 << 1) +#else +#define MINT14_2PL 0xFFFF +#endif + +#if (INT3PL >= INT14PL) || (INT3PL == 0) +#define MINT14_3PL ~(1 << 2) +#else +#define MINT14_3PL 0xFFFF +#endif + +#if (INT4PL >= INT14PL) || (INT4PL == 0) +#define MINT14_4PL ~(1 << 3) +#else +#define MINT14_4PL 0xFFFF +#endif + +#if (INT5PL >= INT14PL) || (INT5PL == 0) +#define MINT14_5PL ~(1 << 4) +#else +#define MINT14_5PL 0xFFFF +#endif + +#if (INT6PL >= INT14PL) || (INT6PL == 0) +#define MINT14_6PL ~(1 << 5) +#else +#define MINT14_6PL 0xFFFF +#endif + +#if (INT7PL >= INT14PL) || (INT7PL == 0) +#define MINT14_7PL ~(1 << 6) +#else +#define MINT14_7PL 0xFFFF +#endif + +#if (INT8PL >= INT14PL) || (INT8PL == 0) +#define MINT14_8PL ~(1 << 7) +#else +#define MINT14_8PL 0xFFFF +#endif + +#if (INT9PL >= INT14PL) || (INT9PL == 0) +#define MINT14_9PL ~(1 << 8) +#else +#define MINT14_9PL 0xFFFF +#endif + +#if (INT10PL >= INT14PL) || (INT10PL == 0) +#define MINT14_10PL ~(1 << 9) +#else +#define MINT14_10PL 0xFFFF +#endif + +#if (INT11PL >= INT14PL) || (INT11PL == 0) +#define MINT14_11PL ~(1 << 10) +#else +#define MINT14_11PL 0xFFFF +#endif + +#if (INT12PL >= INT14PL) || (INT12PL == 0) +#define MINT14_12PL ~(1 << 11) +#else +#define MINT14_12PL 0xFFFF +#endif + +#if (INT13PL >= INT14PL) || (INT13PL == 0) +#define MINT14_13PL ~(1 << 12) +#else +#define MINT14_13PL 0xFFFF +#endif + +#define MINT14_14PL ~(1 << 13) + +#if (INT15PL >= INT14PL) || (INT15PL == 0) +#define MINT14_15PL ~(1 << 14) +#else +#define MINT14_15PL 0xFFFF +#endif + +#if (INT16PL >= INT14PL) || (INT16PL == 0) +#define MINT14_16PL ~(1 << 15) +#else +#define MINT14_16PL 0xFFFF +#endif + +#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \ + MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \ + MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \ + MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL) + +// +// Beginning of MINT15: +// +#if (INT1PL >= INT15PL) || (INT1PL == 0) +#define MINT15_1PL ~(1 << 0) +#else +#define MINT15_1PL 0xFFFF +#endif + +#if (INT2PL >= INT15PL) || (INT2PL == 0) +#define MINT15_2PL ~(1 << 1) +#else +#define MINT15_2PL 0xFFFF +#endif + +#if (INT3PL >= INT15PL) || (INT3PL == 0) +#define MINT15_3PL ~(1 << 2) +#else +#define MINT15_3PL 0xFFFF +#endif + +#if (INT4PL >= INT15PL) || (INT4PL == 0) +#define MINT15_4PL ~(1 << 3) +#else +#define MINT15_4PL 0xFFFF +#endif + +#if (INT5PL >= INT15PL) || (INT5PL == 0) +#define MINT15_5PL ~(1 << 4) +#else +#define MINT15_5PL 0xFFFF +#endif + +#if (INT6PL >= INT15PL) || (INT6PL == 0) +#define MINT15_6PL ~(1 << 5) +#else +#define MINT15_6PL 0xFFFF +#endif + +#if (INT7PL >= INT15PL) || (INT7PL == 0) +#define MINT15_7PL ~(1 << 6) +#else +#define MINT15_7PL 0xFFFF +#endif + +#if (INT8PL >= INT15PL) || (INT8PL == 0) +#define MINT15_8PL ~(1 << 7) +#else +#define MINT15_8PL 0xFFFF +#endif + +#if (INT9PL >= INT15PL) || (INT9PL == 0) +#define MINT15_9PL ~(1 << 8) +#else +#define MINT15_9PL 0xFFFF +#endif + +#if (INT10PL >= INT15PL) || (INT10PL == 0) +#define MINT15_10PL ~(1 << 9) +#else +#define MINT15_10PL 0xFFFF +#endif + +#if (INT11PL >= INT15PL) || (INT11PL == 0) +#define MINT15_11PL ~(1 << 10) +#else +#define MINT15_11PL 0xFFFF +#endif + +#if (INT12PL >= INT15PL) || (INT12PL == 0) +#define MINT15_12PL ~(1 << 11) +#else +#define MINT15_12PL 0xFFFF +#endif + +#if (INT13PL >= INT15PL) || (INT13PL == 0) +#define MINT15_13PL ~(1 << 12) +#else +#define MINT15_13PL 0xFFFF +#endif + +#if (INT14PL >= INT15PL) || (INT14PL == 0) +#define MINT15_14PL ~(1 << 13) +#else +#define MINT15_14PL 0xFFFF +#endif + +#define MINT15_15PL ~(1 << 14) + +#if (INT16PL >= INT15PL) || (INT16PL == 0) +#define MINT15_16PL ~(1 << 15) +#else +#define MINT15_16PL 0xFFFF +#endif + +#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \ + MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \ + MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \ + MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL) + +// +// Beginning of MINT16: +// +#if (INT1PL >= INT16PL) || (INT1PL == 0) +#define MINT16_1PL ~(1 << 0) +#else +#define MINT16_1PL 0xFFFF +#endif + +#if (INT2PL >= INT16PL) || (INT2PL == 0) +#define MINT16_2PL ~(1 << 1) +#else +#define MINT16_2PL 0xFFFF +#endif + +#if (INT3PL >= INT16PL) || (INT3PL == 0) +#define MINT16_3PL ~(1 << 2) +#else +#define MINT16_3PL 0xFFFF +#endif + +#if (INT4PL >= INT16PL) || (INT4PL == 0) +#define MINT16_4PL ~(1 << 3) +#else +#define MINT16_4PL 0xFFFF +#endif + +#if (INT5PL >= INT16PL) || (INT5PL == 0) +#define MINT16_5PL ~(1 << 4) +#else +#define MINT16_5PL 0xFFFF +#endif + +#if (INT6PL >= INT16PL) || (INT6PL == 0) +#define MINT16_6PL ~(1 << 5) +#else +#define MINT16_6PL 0xFFFF +#endif + +#if (INT7PL >= INT16PL) || (INT7PL == 0) +#define MINT16_7PL ~(1 << 6) +#else +#define MINT16_7PL 0xFFFF +#endif + +#if (INT8PL >= INT16PL) || (INT8PL == 0) +#define MINT16_8PL ~(1 << 7) +#else +#define MINT16_8PL 0xFFFF +#endif + +#if (INT9PL >= INT16PL) || (INT9PL == 0) +#define MINT16_9PL ~(1 << 8) +#else +#define MINT16_9PL 0xFFFF +#endif + +#if (INT10PL >= INT16PL) || (INT10PL == 0) +#define MINT16_10PL ~(1 << 9) +#else +#define MINT16_10PL 0xFFFF +#endif + +#if (INT11PL >= INT16PL) || (INT11PL == 0) +#define MINT16_11PL ~(1 << 10) +#else +#define MINT16_11PL 0xFFFF +#endif + +#if (INT12PL >= INT16PL) || (INT12PL == 0) +#define MINT16_12PL ~(1 << 11) +#else +#define MINT16_12PL 0xFFFF +#endif + +#if (INT13PL >= INT16PL) || (INT13PL == 0) +#define MINT16_13PL ~(1 << 12) +#else +#define MINT16_13PL 0xFFFF +#endif + +#if (INT14PL >= INT16PL) || (INT14PL == 0) +#define MINT16_14PL ~(1 << 13) +#else +#define MINT16_14PL 0xFFFF +#endif + +#if (INT15PL >= INT16PL) || (INT15PL == 0) +#define MINT16_15PL ~(1 << 14) +#else +#define MINT16_15PL 0xFFFF +#endif + +#define MINT16_16PL ~(1 << 15) + +#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \ + MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \ + MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \ + MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL) + +// +// Automatically generate PIEIER1 interrupt masks MG11 to MG18: +// + +// +// Beginning of MG11: +// +#if (G12PL >= G11PL) || (G12PL == 0) +#define MG11_12PL ~(1 << 1) +#else +#define MG11_12PL 0xFFFF +#endif + +#if (G13PL >= G11PL) || (G13PL == 0) +#define MG11_13PL ~(1 << 2) +#else +#define MG11_13PL 0xFFFF +#endif + +#if (G14PL >= G11PL) || (G14PL == 0) +#define MG11_14PL ~(1 << 3) +#else +#define MG11_14PL 0xFFFF +#endif + +#if (G15PL >= G11PL) || (G15PL == 0) +#define MG11_15PL ~(1 << 4) +#else +#define MG11_15PL 0xFFFF +#endif + +#if (G16PL >= G11PL) || (G16PL == 0) +#define MG11_16PL ~(1 << 5) +#else +#define MG11_16PL 0xFFFF +#endif + +#if (G17PL >= G11PL) || (G17PL == 0) +#define MG11_17PL ~(1 << 6) +#else +#define MG11_17PL 0xFFFF +#endif + +#if (G18PL >= G11PL) || (G18PL == 0) +#define MG11_18PL ~(1 << 7) +#else +#define MG11_18PL 0xFFFF +#endif + +#define MG11_11PL 0x00FE +#define MG11 (MG11_11PL & MG11_12PL & MG11_13PL & MG11_14PL & \ + MG11_15PL & MG11_16PL & MG11_17PL & MG11_18PL) + +// +// Beginning of MG12: +// +#if (G11PL >= G12PL) || (G11PL == 0) +#define MG12_11PL ~(1) +#else +#define MG12_11PL 0xFFFF +#endif +#if (G13PL >= G12PL) || (G13PL == 0) +#define MG12_13PL ~(1 << 2) +#else +#define MG12_13PL 0xFFFF +#endif +#if (G14PL >= G12PL) || (G14PL == 0) +#define MG12_14PL ~(1 << 3) +#else +#define MG12_14PL 0xFFFF +#endif +#if (G15PL >= G12PL) || (G15PL == 0) +#define MG12_15PL ~(1 << 4) +#else +#define MG12_15PL 0xFFFF +#endif +#if (G16PL >= G12PL) || (G16PL == 0) +#define MG12_16PL ~(1 << 5) +#else +#define MG12_16PL 0xFFFF +#endif +#if (G17PL >= G12PL) || (G17PL == 0) +#define MG12_17PL ~(1 << 6) +#else +#define MG12_17PL 0xFFFF +#endif +#if (G18PL >= G12PL) || (G18PL == 0) +#define MG12_18PL ~(1 << 7) +#else +#define MG12_18PL 0xFFFF +#endif +#define MG12_12PL 0x00FD +#define MG12 (MG12_11PL & MG12_12PL & MG12_13PL & MG12_14PL & \ + MG12_15PL & MG12_16PL & MG12_17PL & MG12_18PL) + +// +// End of MG12: +// + +// +// Beginning of MG13: +// +#if (G11PL >= G13PL) || (G11PL == 0) +#define MG13_11PL ~(1) +#else +#define MG13_11PL 0xFFFF +#endif +#if (G12PL >= G13PL) || (G12PL == 0) +#define MG13_12PL ~(1 << 1) +#else +#define MG13_12PL 0xFFFF +#endif +#if (G14PL >= G13PL) || (G14PL == 0) +#define MG13_14PL ~(1 << 3) +#else +#define MG13_14PL 0xFFFF +#endif +#if (G15PL >= G13PL) || (G15PL == 0) +#define MG13_15PL ~(1 << 4) +#else +#define MG13_15PL 0xFFFF +#endif +#if (G16PL >= G13PL) || (G16PL == 0) +#define MG13_16PL ~(1 << 5) +#else +#define MG13_16PL 0xFFFF +#endif +#if (G17PL >= G13PL) || (G17PL == 0) +#define MG13_17PL ~(1 << 6) +#else +#define MG13_17PL 0xFFFF +#endif +#if (G18PL >= G13PL) || (G18PL == 0) +#define MG13_18PL ~(1 << 7) +#else +#define MG13_18PL 0xFFFF +#endif +#define MG13_13PL 0x00FB +#define MG13 (MG13_11PL & MG13_12PL & MG13_13PL & MG13_14PL & \ + MG13_15PL & MG13_16PL & MG13_17PL & MG13_18PL) + +// +// Beginning of MG14: +// +#if (G11PL >= G14PL) || (G11PL == 0) +#define MG14_11PL ~(1) +#else +#define MG14_11PL 0xFFFF +#endif +#if (G12PL >= G14PL) || (G12PL == 0) +#define MG14_12PL ~(1 << 1) +#else +#define MG14_12PL 0xFFFF +#endif +#if (G13PL >= G14PL) || (G13PL == 0) +#define MG14_13PL ~(1 << 2) +#else +#define MG14_13PL 0xFFFF +#endif +#if (G15PL >= G14PL) || (G15PL == 0) +#define MG14_15PL ~(1 << 4) +#else +#define MG14_15PL 0xFFFF +#endif +#if (G16PL >= G14PL) || (G16PL == 0) +#define MG14_16PL ~(1 << 5) +#else +#define MG14_16PL 0xFFFF +#endif +#if (G17PL >= G14PL) || (G17PL == 0) +#define MG14_17PL ~(1 << 6) +#else +#define MG14_17PL 0xFFFF +#endif +#if (G18PL >= G14PL) || (G18PL == 0) +#define MG14_18PL ~(1 << 7) +#else +#define MG14_18PL 0xFFFF +#endif +#define MG14_14PL 0x00F7 +#define MG14 (MG14_11PL & MG14_12PL & MG14_13PL & MG14_14PL & \ + MG14_15PL & MG14_16PL & MG14_17PL & MG14_18PL) + +// +// Beginning of MG15: +// +#if (G11PL >= G15PL) || (G11PL == 0) +#define MG15_11PL ~(1) +#else +#define MG15_11PL 0xFFFF +#endif +#if (G12PL >= G15PL) || (G12PL == 0) +#define MG15_12PL ~(1 << 1) +#else +#define MG15_12PL 0xFFFF +#endif +#if (G13PL >= G15PL) || (G13PL == 0) +#define MG15_13PL ~(1 << 2) +#else +#define MG15_13PL 0xFFFF +#endif +#if (G14PL >= G15PL) || (G14PL == 0) +#define MG15_14PL ~(1 << 3) +#else +#define MG15_14PL 0xFFFF +#endif +#if (G16PL >= G15PL) || (G16PL == 0) +#define MG15_16PL ~(1 << 5) +#else +#define MG15_16PL 0xFFFF +#endif +#if (G17PL >= G15PL) || (G17PL == 0) +#define MG15_17PL ~(1 << 6) +#else +#define MG15_17PL 0xFFFF +#endif +#if (G18PL >= G15PL) || (G18PL == 0) +#define MG15_18PL ~(1 << 7) +#else +#define MG15_18PL 0xFFFF +#endif +#define MG15_15PL 0x00EF +#define MG15 (MG15_11PL & MG15_12PL & MG15_13PL & MG15_14PL & \ + MG15_15PL & MG15_16PL & MG15_17PL & MG15_18PL) + +// +// Beginning of MG16: +// +#if (G11PL >= G16PL) || (G11PL == 0) +#define MG16_11PL ~(1) +#else +#define MG16_11PL 0xFFFF +#endif +#if (G12PL >= G16PL) || (G12PL == 0) +#define MG16_12PL ~(1 << 1) +#else +#define MG16_12PL 0xFFFF +#endif +#if (G13PL >= G16PL) || (G13PL == 0) +#define MG16_13PL ~(1 << 2) +#else +#define MG16_13PL 0xFFFF +#endif +#if (G14PL >= G16PL) || (G14PL == 0) +#define MG16_14PL ~(1 << 3) +#else +#define MG16_14PL 0xFFFF +#endif +#if (G15PL >= G16PL) || (G15PL == 0) +#define MG16_15PL ~(1 << 4) +#else +#define MG16_15PL 0xFFFF +#endif +#if (G17PL >= G16PL) || (G17PL == 0) +#define MG16_17PL ~(1 << 6) +#else +#define MG16_17PL 0xFFFF +#endif +#if (G18PL >= G16PL) || (G18PL == 0) +#define MG16_18PL ~(1 << 7) +#else +#define MG16_18PL 0xFFFF +#endif +#define MG16_16PL 0x00DF +#define MG16 (MG16_11PL & MG16_12PL & MG16_13PL & MG16_14PL & \ + MG16_15PL & MG16_16PL & MG16_17PL & MG16_18PL) + +// +// Beginning of MG17: +// +#if (G11PL >= G17PL) || (G11PL == 0) +#define MG17_11PL ~(1) +#else +#define MG17_11PL 0xFFFF +#endif +#if (G12PL >= G17PL) || (G12PL == 0) +#define MG17_12PL ~(1 << 1) +#else +#define MG17_12PL 0xFFFF +#endif +#if (G13PL >= G17PL) || (G13PL == 0) +#define MG17_13PL ~(1 << 2) +#else +#define MG17_13PL 0xFFFF +#endif +#if (G14PL >= G17PL) || (G14PL == 0) +#define MG17_14PL ~(1 << 3) +#else +#define MG17_14PL 0xFFFF +#endif +#if (G15PL >= G17PL) || (G15PL == 0) +#define MG17_15PL ~(1 << 4) +#else +#define MG17_15PL 0xFFFF +#endif +#if (G16PL >= G17PL) || (G16PL == 0) +#define MG17_16PL ~(1 << 5) +#else +#define MG17_16PL 0xFFFF +#endif +#if (G18PL >= G17PL) || (G18PL == 0) +#define MG17_18PL ~(1 << 7) +#else +#define MG17_18PL 0xFFFF +#endif +#define MG17_17PL 0x00BF +#define MG17 (MG17_11PL & MG17_12PL & MG17_13PL & MG17_14PL & \ + MG17_15PL & MG17_16PL & MG17_17PL & MG17_18PL) + +// +// Beginning of MG18: +// +#if (G11PL >= G18PL) || (G11PL == 0) +#define MG18_11PL ~(1) +#else +#define MG18_11PL 0xFFFF +#endif +#if (G12PL >= G18PL) || (G12PL == 0) +#define MG18_12PL ~(1 << 1) +#else +#define MG18_12PL 0xFFFF +#endif +#if (G13PL >= G18PL) || (G13PL == 0) +#define MG18_13PL ~(1 << 2) +#else +#define MG18_13PL 0xFFFF +#endif +#if (G14PL >= G18PL) || (G14PL == 0) +#define MG18_14PL ~(1 << 3) +#else +#define MG18_14PL 0xFFFF +#endif +#if (G15PL >= G18PL) || (G15PL == 0) +#define MG18_15PL ~(1 << 4) +#else +#define MG18_15PL 0xFFFF +#endif +#if (G16PL >= G18PL) || (G16PL == 0) +#define MG18_16PL ~(1 << 5) +#else +#define MG18_16PL 0xFFFF +#endif +#if (G17PL >= G18PL) || (G17PL == 0) +#define MG18_17PL ~(1 << 6) +#else +#define MG18_17PL 0xFFFF +#endif +#define MG18_18PL 0x007F +#define MG18 (MG18_11PL & MG18_12PL & MG18_13PL & MG18_14PL & \ + MG18_15PL & MG18_16PL & MG18_17PL & MG18_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG21 to MG28: +// + +// +// Beginning of MG21: +// +#if (G22PL >= G21PL) || (G22PL == 0) +#define MG21_12PL ~(1 << 1) +#else +#define MG21_12PL 0xFFFF +#endif +#if (G23PL >= G21PL) || (G23PL == 0) +#define MG21_13PL ~(1 << 2) +#else +#define MG21_13PL 0xFFFF +#endif +#if (G24PL >= G21PL) || (G24PL == 0) +#define MG21_14PL ~(1 << 3) +#else +#define MG21_14PL 0xFFFF +#endif +#if (G25PL >= G21PL) || (G25PL == 0) +#define MG21_15PL ~(1 << 4) +#else +#define MG21_15PL 0xFFFF +#endif +#if (G26PL >= G21PL) || (G26PL == 0) +#define MG21_16PL ~(1 << 5) +#else +#define MG21_16PL 0xFFFF +#endif +#if (G27PL >= G21PL) || (G27PL == 0) +#define MG21_17PL ~(1 << 6) +#else +#define MG21_17PL 0xFFFF +#endif +#if (G28PL >= G21PL) || (G28PL == 0) +#define MG21_18PL ~(1 << 7) +#else +#define MG21_18PL 0xFFFF +#endif +#define MG21_11PL 0x00FE +#define MG21 (MG21_11PL & MG21_12PL & MG21_13PL & MG21_14PL & \ + MG21_15PL & MG21_16PL & MG21_17PL & MG21_18PL) + +// +// Beginning of MG22: +// +#if (G21PL >= G22PL) || (G21PL == 0) +#define MG22_11PL ~(1) +#else +#define MG22_11PL 0xFFFF +#endif +#if (G23PL >= G22PL) || (G23PL == 0) +#define MG22_13PL ~(1 << 2) +#else +#define MG22_13PL 0xFFFF +#endif +#if (G24PL >= G22PL) || (G24PL == 0) +#define MG22_14PL ~(1 << 3) +#else +#define MG22_14PL 0xFFFF +#endif +#if (G25PL >= G22PL) || (G25PL == 0) +#define MG22_15PL ~(1 << 4) +#else +#define MG22_15PL 0xFFFF +#endif +#if (G26PL >= G22PL) || (G26PL == 0) +#define MG22_16PL ~(1 << 5) +#else +#define MG22_16PL 0xFFFF +#endif +#if (G27PL >= G22PL) || (G27PL == 0) +#define MG22_17PL ~(1 << 6) +#else +#define MG22_17PL 0xFFFF +#endif +#if (G28PL >= G22PL) || (G28PL == 0) +#define MG22_18PL ~(1 << 7) +#else +#define MG22_18PL 0xFFFF +#endif +#define MG22_12PL 0x00FD +#define MG22 (MG22_11PL & MG22_12PL & MG22_13PL & MG22_14PL & \ + MG22_15PL & MG22_16PL & MG22_17PL & MG22_18PL) + +// +// Beginning of MG23: +// +#if (G21PL >= G23PL) || (G21PL == 0) +#define MG23_11PL ~(1) +#else +#define MG23_11PL 0xFFFF +#endif +#if (G22PL >= G23PL) || (G22PL == 0) +#define MG23_12PL ~(1 << 1) +#else +#define MG23_12PL 0xFFFF +#endif +#if (G24PL >= G23PL) || (G24PL == 0) +#define MG23_14PL ~(1 << 3) +#else +#define MG23_14PL 0xFFFF +#endif +#if (G25PL >= G23PL) || (G25PL == 0) +#define MG23_15PL ~(1 << 4) +#else +#define MG23_15PL 0xFFFF +#endif +#if (G26PL >= G23PL) || (G26PL == 0) +#define MG23_16PL ~(1 << 5) +#else +#define MG23_16PL 0xFFFF +#endif +#if (G27PL >= G23PL) || (G27PL == 0) +#define MG23_17PL ~(1 << 6) +#else +#define MG23_17PL 0xFFFF +#endif +#if (G28PL >= G23PL) || (G28PL == 0) +#define MG23_18PL ~(1 << 7) +#else +#define MG23_18PL 0xFFFF +#endif +#define MG23_13PL 0x00FB +#define MG23 (MG23_11PL & MG23_12PL & MG23_13PL & MG23_14PL & \ + MG23_15PL & MG23_16PL & MG23_17PL & MG23_18PL) + +// +// Beginning of MG24: +// +#if (G21PL >= G24PL) || (G21PL == 0) +#define MG24_11PL ~(1) +#else +#define MG24_11PL 0xFFFF +#endif +#if (G22PL >= G24PL) || (G22PL == 0) +#define MG24_12PL ~(1 << 1) +#else +#define MG24_12PL 0xFFFF +#endif +#if (G23PL >= G24PL) || (G23PL == 0) +#define MG24_13PL ~(1 << 2) +#else +#define MG24_13PL 0xFFFF +#endif +#if (G25PL >= G24PL) || (G25PL == 0) +#define MG24_15PL ~(1 << 4) +#else +#define MG24_15PL 0xFFFF +#endif +#if (G26PL >= G24PL) || (G26PL == 0) +#define MG24_16PL ~(1 << 5) +#else +#define MG24_16PL 0xFFFF +#endif +#if (G27PL >= G24PL) || (G27PL == 0) +#define MG24_17PL ~(1 << 6) +#else +#define MG24_17PL 0xFFFF +#endif +#if (G28PL >= G24PL) || (G28PL == 0) +#define MG24_18PL ~(1 << 7) +#else +#define MG24_18PL 0xFFFF +#endif +#define MG24_14PL 0x00F7 +#define MG24 (MG24_11PL & MG24_12PL & MG24_13PL & MG24_14PL & \ + MG24_15PL & MG24_16PL & MG24_17PL & MG24_18PL) + +// +// Beginning of MG25: +// +#if (G21PL >= G25PL) || (G21PL == 0) +#define MG25_11PL ~(1) +#else +#define MG25_11PL 0xFFFF +#endif +#if (G22PL >= G25PL) || (G22PL == 0) +#define MG25_12PL ~(1 << 1) +#else +#define MG25_12PL 0xFFFF +#endif +#if (G23PL >= G25PL) || (G23PL == 0) +#define MG25_13PL ~(1 << 2) +#else +#define MG25_13PL 0xFFFF +#endif +#if (G24PL >= G25PL) || (G24PL == 0) +#define MG25_14PL ~(1 << 3) +#else +#define MG25_14PL 0xFFFF +#endif +#if (G26PL >= G25PL) || (G26PL == 0) +#define MG25_16PL ~(1 << 5) +#else +#define MG25_16PL 0xFFFF +#endif +#if (G27PL >= G25PL) || (G27PL == 0) +#define MG25_17PL ~(1 << 6) +#else +#define MG25_17PL 0xFFFF +#endif +#if (G28PL >= G25PL) || (G28PL == 0) +#define MG25_18PL ~(1 << 7) +#else +#define MG25_18PL 0xFFFF +#endif +#define MG25_15PL 0x00EF +#define MG25 (MG25_11PL & MG25_12PL & MG25_13PL & MG25_14PL & \ + MG25_15PL & MG25_16PL & MG25_17PL & MG25_18PL) + +// +// Beginning of MG26: +// +#if (G21PL >= G26PL) || (G21PL == 0) +#define MG26_11PL ~(1) +#else +#define MG26_11PL 0xFFFF +#endif +#if (G22PL >= G26PL) || (G22PL == 0) +#define MG26_12PL ~(1 << 1) +#else +#define MG26_12PL 0xFFFF +#endif +#if (G23PL >= G26PL) || (G23PL == 0) +#define MG26_13PL ~(1 << 2) +#else +#define MG26_13PL 0xFFFF +#endif +#if (G24PL >= G26PL) || (G24PL == 0) +#define MG26_14PL ~(1 << 3) +#else +#define MG26_14PL 0xFFFF +#endif +#if (G25PL >= G26PL) || (G25PL == 0) +#define MG26_15PL ~(1 << 4) +#else +#define MG26_15PL 0xFFFF +#endif +#if (G27PL >= G26PL) || (G27PL == 0) +#define MG26_17PL ~(1 << 6) +#else +#define MG26_17PL 0xFFFF +#endif +#if (G28PL >= G26PL) || (G28PL == 0) +#define MG26_18PL ~(1 << 7) +#else +#define MG26_18PL 0xFFFF +#endif +#define MG26_16PL 0x00DF +#define MG26 (MG26_11PL & MG26_12PL & MG26_13PL & MG26_14PL & \ + MG26_15PL & MG26_16PL & MG26_17PL & MG26_18PL) + +// +// Beginning of MG27: +// +#if (G21PL >= G27PL) || (G21PL == 0) +#define MG27_11PL ~(1) +#else +#define MG27_11PL 0xFFFF +#endif +#if (G22PL >= G27PL) || (G22PL == 0) +#define MG27_12PL ~(1 << 1) +#else +#define MG27_12PL 0xFFFF +#endif +#if (G23PL >= G27PL) || (G23PL == 0) +#define MG27_13PL ~(1 << 2) +#else +#define MG27_13PL 0xFFFF +#endif +#if (G24PL >= G27PL) || (G24PL == 0) +#define MG27_14PL ~(1 << 3) +#else +#define MG27_14PL 0xFFFF +#endif +#if (G25PL >= G27PL) || (G25PL == 0) +#define MG27_15PL ~(1 << 4) +#else +#define MG27_15PL 0xFFFF +#endif +#if (G26PL >= G27PL) || (G26PL == 0) +#define MG27_16PL ~(1 << 5) +#else +#define MG27_16PL 0xFFFF +#endif +#if (G28PL >= G27PL) || (G28PL == 0) +#define MG27_18PL ~(1 << 7) +#else +#define MG27_18PL 0xFFFF +#endif +#define MG27_17PL 0x00BF +#define MG27 (MG27_11PL & MG27_12PL & MG27_13PL & MG27_14PL & \ + MG27_15PL & MG27_16PL & MG27_17PL & MG27_18PL) + +// +// Beginning of MG28: +// +#if (G21PL >= G28PL) || (G21PL == 0) +#define MG28_11PL ~(1) +#else +#define MG28_11PL 0xFFFF +#endif +#if (G22PL >= G28PL) || (G22PL == 0) +#define MG28_12PL ~(1 << 1) +#else +#define MG28_12PL 0xFFFF +#endif +#if (G23PL >= G28PL) || (G23PL == 0) +#define MG28_13PL ~(1 << 2) +#else +#define MG28_13PL 0xFFFF +#endif +#if (G24PL >= G28PL) || (G24PL == 0) +#define MG28_14PL ~(1 << 3) +#else +#define MG28_14PL 0xFFFF +#endif +#if (G25PL >= G28PL) || (G25PL == 0) +#define MG28_15PL ~(1 << 4) +#else +#define MG28_15PL 0xFFFF +#endif +#if (G26PL >= G28PL) || (G26PL == 0) +#define MG28_16PL ~(1 << 5) +#else +#define MG28_16PL 0xFFFF +#endif +#if (G27PL >= G28PL) || (G27PL == 0) +#define MG28_17PL ~(1 << 6) +#else +#define MG28_17PL 0xFFFF +#endif +#define MG28_18PL 0x007F +#define MG28 (MG28_11PL & MG28_12PL & MG28_13PL & MG28_14PL & \ + MG28_15PL & MG28_16PL & MG28_17PL & MG28_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG31 to MG38: +// + +// +// Beginning of MG31: +// +#if (G32PL >= G31PL) || (G32PL == 0) +#define MG31_12PL ~(1 << 1) +#else +#define MG31_12PL 0xFFFF +#endif +#if (G33PL >= G31PL) || (G33PL == 0) +#define MG31_13PL ~(1 << 2) +#else +#define MG31_13PL 0xFFFF +#endif +#if (G34PL >= G31PL) || (G34PL == 0) +#define MG31_14PL ~(1 << 3) +#else +#define MG31_14PL 0xFFFF +#endif +#if (G35PL >= G31PL) || (G35PL == 0) +#define MG31_15PL ~(1 << 4) +#else +#define MG31_15PL 0xFFFF +#endif +#if (G36PL >= G31PL) || (G36PL == 0) +#define MG31_16PL ~(1 << 5) +#else +#define MG31_16PL 0xFFFF +#endif +#if (G37PL >= G31PL) || (G37PL == 0) +#define MG31_17PL ~(1 << 6) +#else +#define MG31_17PL 0xFFFF +#endif +#if (G38PL >= G31PL) || (G38PL == 0) +#define MG31_18PL ~(1 << 7) +#else +#define MG31_18PL 0xFFFF +#endif +#define MG31_11PL 0x00FE +#define MG31 (MG31_11PL & MG31_12PL & MG31_13PL & MG31_14PL & \ + MG31_15PL & MG31_16PL & MG31_17PL & MG31_18PL) + +// +// Beginning of MG32: +// +#if (G31PL >= G32PL) || (G31PL == 0) +#define MG32_11PL ~(1) +#else +#define MG32_11PL 0xFFFF +#endif +#if (G33PL >= G32PL) || (G33PL == 0) +#define MG32_13PL ~(1 << 2) +#else +#define MG32_13PL 0xFFFF +#endif +#if (G34PL >= G32PL) || (G34PL == 0) +#define MG32_14PL ~(1 << 3) +#else +#define MG32_14PL 0xFFFF +#endif +#if (G35PL >= G32PL) || (G35PL == 0) +#define MG32_15PL ~(1 << 4) +#else +#define MG32_15PL 0xFFFF +#endif +#if (G36PL >= G32PL) || (G36PL == 0) +#define MG32_16PL ~(1 << 5) +#else +#define MG32_16PL 0xFFFF +#endif +#if (G37PL >= G32PL) || (G37PL == 0) +#define MG32_17PL ~(1 << 6) +#else +#define MG32_17PL 0xFFFF +#endif +#if (G38PL >= G32PL) || (G38PL == 0) +#define MG32_18PL ~(1 << 7) +#else +#define MG32_18PL 0xFFFF +#endif +#define MG32_12PL 0x00FD +#define MG32 (MG32_11PL & MG32_12PL & MG32_13PL & MG32_14PL & \ + MG32_15PL & MG32_16PL & MG32_17PL & MG32_18PL) + +// +// Beginning of MG33: +// +#if (G31PL >= G33PL) || (G31PL == 0) +#define MG33_11PL ~(1) +#else +#define MG33_11PL 0xFFFF +#endif +#if (G32PL >= G33PL) || (G32PL == 0) +#define MG33_12PL ~(1 << 1) +#else +#define MG33_12PL 0xFFFF +#endif +#if (G34PL >= G33PL) || (G34PL == 0) +#define MG33_14PL ~(1 << 3) +#else +#define MG33_14PL 0xFFFF +#endif +#if (G35PL >= G33PL) || (G35PL == 0) +#define MG33_15PL ~(1 << 4) +#else +#define MG33_15PL 0xFFFF +#endif +#if (G36PL >= G33PL) || (G36PL == 0) +#define MG33_16PL ~(1 << 5) +#else +#define MG33_16PL 0xFFFF +#endif +#if (G37PL >= G33PL) || (G37PL == 0) +#define MG33_17PL ~(1 << 6) +#else +#define MG33_17PL 0xFFFF +#endif +#if (G38PL >= G33PL) || (G38PL == 0) +#define MG33_18PL ~(1 << 7) +#else +#define MG33_18PL 0xFFFF +#endif +#define MG33_13PL 0x00FB +#define MG33 (MG33_11PL & MG33_12PL & MG33_13PL & MG33_14PL & \ + MG33_15PL & MG33_16PL & MG33_17PL & MG33_18PL) + +// +// Beginning of MG34: +// +#if (G31PL >= G34PL) || (G31PL == 0) +#define MG34_11PL ~(1) +#else +#define MG34_11PL 0xFFFF +#endif +#if (G32PL >= G34PL) || (G32PL == 0) +#define MG34_12PL ~(1 << 1) +#else +#define MG34_12PL 0xFFFF +#endif +#if (G33PL >= G34PL) || (G33PL == 0) +#define MG34_13PL ~(1 << 2) +#else +#define MG34_13PL 0xFFFF +#endif +#if (G35PL >= G34PL) || (G35PL == 0) +#define MG34_15PL ~(1 << 4) +#else +#define MG34_15PL 0xFFFF +#endif +#if (G36PL >= G34PL) || (G36PL == 0) +#define MG34_16PL ~(1 << 5) +#else +#define MG34_16PL 0xFFFF +#endif +#if (G37PL >= G34PL) || (G37PL == 0) +#define MG34_17PL ~(1 << 6) +#else +#define MG34_17PL 0xFFFF +#endif +#if (G38PL >= G34PL) || (G38PL == 0) +#define MG34_18PL ~(1 << 7) +#else +#define MG34_18PL 0xFFFF +#endif +#define MG34_14PL 0x00F7 +#define MG34 (MG34_11PL & MG34_12PL & MG34_13PL & MG34_14PL & \ + MG34_15PL & MG34_16PL & MG34_17PL & MG34_18PL) + +// +// Beginning of MG35: +// +#if (G31PL >= G35PL) || (G31PL == 0) +#define MG35_11PL ~(1) +#else +#define MG35_11PL 0xFFFF +#endif +#if (G32PL >= G35PL) || (G32PL == 0) +#define MG35_12PL ~(1 << 1) +#else +#define MG35_12PL 0xFFFF +#endif +#if (G33PL >= G35PL) || (G33PL == 0) +#define MG35_13PL ~(1 << 2) +#else +#define MG35_13PL 0xFFFF +#endif +#if (G34PL >= G35PL) || (G34PL == 0) +#define MG35_14PL ~(1 << 3) +#else +#define MG35_14PL 0xFFFF +#endif +#if (G36PL >= G35PL) || (G36PL == 0) +#define MG35_16PL ~(1 << 5) +#else +#define MG35_16PL 0xFFFF +#endif +#if (G37PL >= G35PL) || (G37PL == 0) +#define MG35_17PL ~(1 << 6) +#else +#define MG35_17PL 0xFFFF +#endif +#if (G38PL >= G35PL) || (G38PL == 0) +#define MG35_18PL ~(1 << 7) +#else +#define MG35_18PL 0xFFFF +#endif +#define MG35_15PL 0x00EF +#define MG35 (MG35_11PL & MG35_12PL & MG35_13PL & MG35_14PL & \ + MG35_15PL & MG35_16PL & MG35_17PL & MG35_18PL) + +// +// Beginning of MG36: +// +#if (G31PL >= G36PL) || (G31PL == 0) +#define MG36_11PL ~(1) +#else +#define MG36_11PL 0xFFFF +#endif +#if (G32PL >= G36PL) || (G32PL == 0) +#define MG36_12PL ~(1 << 1) +#else +#define MG36_12PL 0xFFFF +#endif +#if (G33PL >= G36PL) || (G33PL == 0) +#define MG36_13PL ~(1 << 2) +#else +#define MG36_13PL 0xFFFF +#endif +#if (G34PL >= G36PL) || (G34PL == 0) +#define MG36_14PL ~(1 << 3) +#else +#define MG36_14PL 0xFFFF +#endif +#if (G35PL >= G36PL) || (G35PL == 0) +#define MG36_15PL ~(1 << 4) +#else +#define MG36_15PL 0xFFFF +#endif +#if (G37PL >= G36PL) || (G37PL == 0) +#define MG36_17PL ~(1 << 6) +#else +#define MG36_17PL 0xFFFF +#endif +#if (G38PL >= G36PL) || (G38PL == 0) +#define MG36_18PL ~(1 << 7) +#else +#define MG36_18PL 0xFFFF +#endif +#define MG36_16PL 0x00DF +#define MG36 (MG36_11PL & MG36_12PL & MG36_13PL & MG36_14PL & \ + MG36_15PL & MG36_16PL & MG36_17PL & MG36_18PL) + +// +// Beginning of MG37: +// +#if (G31PL >= G37PL) || (G31PL == 0) +#define MG37_11PL ~(1) +#else +#define MG37_11PL 0xFFFF +#endif +#if (G32PL >= G37PL) || (G32PL == 0) +#define MG37_12PL ~(1 << 1) +#else +#define MG37_12PL 0xFFFF +#endif +#if (G33PL >= G37PL) || (G33PL == 0) +#define MG37_13PL ~(1 << 2) +#else +#define MG37_13PL 0xFFFF +#endif +#if (G34PL >= G37PL) || (G34PL == 0) +#define MG37_14PL ~(1 << 3) +#else +#define MG37_14PL 0xFFFF +#endif +#if (G35PL >= G37PL) || (G35PL == 0) +#define MG37_15PL ~(1 << 4) +#else +#define MG37_15PL 0xFFFF +#endif +#if (G36PL >= G37PL) || (G36PL == 0) +#define MG37_16PL ~(1 << 5) +#else +#define MG37_16PL 0xFFFF +#endif +#if (G38PL >= G37PL) || (G38PL == 0) +#define MG37_18PL ~(1 << 7) +#else +#define MG37_18PL 0xFFFF +#endif +#define MG37_17PL 0x00BF +#define MG37 (MG37_11PL & MG37_12PL & MG37_13PL & MG37_14PL & \ + MG37_15PL & MG37_16PL & MG37_17PL & MG37_18PL) + +// +// Beginning of MG38: +// +#if (G31PL >= G38PL) || (G31PL == 0) +#define MG38_11PL ~(1) +#else +#define MG38_11PL 0xFFFF +#endif +#if (G32PL >= G38PL) || (G32PL == 0) +#define MG38_12PL ~(1 << 1) +#else +#define MG38_12PL 0xFFFF +#endif +#if (G33PL >= G38PL) || (G33PL == 0) +#define MG38_13PL ~(1 << 2) +#else +#define MG38_13PL 0xFFFF +#endif +#if (G34PL >= G38PL) || (G34PL == 0) +#define MG38_14PL ~(1 << 3) +#else +#define MG38_14PL 0xFFFF +#endif +#if (G35PL >= G38PL) || (G35PL == 0) +#define MG38_15PL ~(1 << 4) +#else +#define MG38_15PL 0xFFFF +#endif +#if (G36PL >= G38PL) || (G36PL == 0) +#define MG38_16PL ~(1 << 5) +#else +#define MG38_16PL 0xFFFF +#endif +#if (G37PL >= G38PL) || (G37PL == 0) +#define MG38_17PL ~(1 << 6) +#else +#define MG38_17PL 0xFFFF +#endif +#define MG38_18PL 0x007F +#define MG38 (MG38_11PL & MG38_12PL & MG38_13PL & MG38_14PL & \ + MG38_15PL & MG38_16PL & MG38_17PL & MG38_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG41 to MG48: +// + +// +// Beginning of MG41: +// +#if (G42PL >= G41PL) || (G42PL == 0) +#define MG41_12PL ~(1 << 1) +#else +#define MG41_12PL 0xFFFF +#endif +#if (G43PL >= G41PL) || (G43PL == 0) +#define MG41_13PL ~(1 << 2) +#else +#define MG41_13PL 0xFFFF +#endif +#if (G44PL >= G41PL) || (G44PL == 0) +#define MG41_14PL ~(1 << 3) +#else +#define MG41_14PL 0xFFFF +#endif +#if (G45PL >= G41PL) || (G45PL == 0) +#define MG41_15PL ~(1 << 4) +#else +#define MG41_15PL 0xFFFF +#endif +#if (G46PL >= G41PL) || (G46PL == 0) +#define MG41_16PL ~(1 << 5) +#else +#define MG41_16PL 0xFFFF +#endif +#if (G47PL >= G41PL) || (G47PL == 0) +#define MG41_17PL ~(1 << 6) +#else +#define MG41_17PL 0xFFFF +#endif +#if (G48PL >= G41PL) || (G48PL == 0) +#define MG41_18PL ~(1 << 7) +#else +#define MG41_18PL 0xFFFF +#endif +#define MG41_11PL 0x00FE +#define MG41 (MG41_11PL & MG41_12PL & MG41_13PL & MG41_14PL & \ + MG41_15PL & MG41_16PL & MG41_17PL & MG41_18PL) + +// +// Beginning of MG42: +// +#if (G41PL >= G42PL) || (G41PL == 0) +#define MG42_11PL ~(1) +#else +#define MG42_11PL 0xFFFF +#endif +#if (G43PL >= G42PL) || (G43PL == 0) +#define MG42_13PL ~(1 << 2) +#else +#define MG42_13PL 0xFFFF +#endif +#if (G44PL >= G42PL) || (G44PL == 0) +#define MG42_14PL ~(1 << 3) +#else +#define MG42_14PL 0xFFFF +#endif +#if (G45PL >= G42PL) || (G45PL == 0) +#define MG42_15PL ~(1 << 4) +#else +#define MG42_15PL 0xFFFF +#endif +#if (G46PL >= G42PL) || (G46PL == 0) +#define MG42_16PL ~(1 << 5) +#else +#define MG42_16PL 0xFFFF +#endif +#if (G47PL >= G42PL) || (G47PL == 0) +#define MG42_17PL ~(1 << 6) +#else +#define MG42_17PL 0xFFFF +#endif +#if (G48PL >= G42PL) || (G48PL == 0) +#define MG42_18PL ~(1 << 7) +#else +#define MG42_18PL 0xFFFF +#endif +#define MG42_12PL 0x00FD +#define MG42 (MG42_11PL & MG42_12PL & MG42_13PL & MG42_14PL & \ + MG42_15PL & MG42_16PL & MG42_17PL & MG42_18PL) + +// +// Beginning of MG43: +// +#if (G41PL >= G43PL) || (G41PL == 0) +#define MG43_11PL ~(1) +#else +#define MG43_11PL 0xFFFF +#endif +#if (G42PL >= G43PL) || (G42PL == 0) +#define MG43_12PL ~(1 << 1) +#else +#define MG43_12PL 0xFFFF +#endif +#if (G44PL >= G43PL) || (G44PL == 0) +#define MG43_14PL ~(1 << 3) +#else +#define MG43_14PL 0xFFFF +#endif +#if (G45PL >= G43PL) || (G45PL == 0) +#define MG43_15PL ~(1 << 4) +#else +#define MG43_15PL 0xFFFF +#endif +#if (G46PL >= G43PL) || (G46PL == 0) +#define MG43_16PL ~(1 << 5) +#else +#define MG43_16PL 0xFFFF +#endif +#if (G47PL >= G43PL) || (G47PL == 0) +#define MG43_17PL ~(1 << 6) +#else +#define MG43_17PL 0xFFFF +#endif +#if (G48PL >= G43PL) || (G48PL == 0) +#define MG43_18PL ~(1 << 7) +#else +#define MG43_18PL 0xFFFF +#endif +#define MG43_13PL 0x00FB +#define MG43 (MG43_11PL & MG43_12PL & MG43_13PL & MG43_14PL & \ + MG43_15PL & MG43_16PL & MG43_17PL & MG43_18PL) + +// +// Beginning of MG44: +// +#if (G41PL >= G44PL) || (G41PL == 0) +#define MG44_11PL ~(1) +#else +#define MG44_11PL 0xFFFF +#endif +#if (G42PL >= G44PL) || (G42PL == 0) +#define MG44_12PL ~(1 << 1) +#else +#define MG44_12PL 0xFFFF +#endif +#if (G43PL >= G44PL) || (G43PL == 0) +#define MG44_13PL ~(1 << 2) +#else +#define MG44_13PL 0xFFFF +#endif +#if (G45PL >= G44PL) || (G45PL == 0) +#define MG44_15PL ~(1 << 4) +#else +#define MG44_15PL 0xFFFF +#endif +#if (G46PL >= G44PL) || (G46PL == 0) +#define MG44_16PL ~(1 << 5) +#else +#define MG44_16PL 0xFFFF +#endif +#if (G47PL >= G44PL) || (G47PL == 0) +#define MG44_17PL ~(1 << 6) +#else +#define MG44_17PL 0xFFFF +#endif +#if (G48PL >= G44PL) || (G48PL == 0) +#define MG44_18PL ~(1 << 7) +#else +#define MG44_18PL 0xFFFF +#endif +#define MG44_14PL 0x00F7 +#define MG44 (MG44_11PL & MG44_12PL & MG44_13PL & MG44_14PL & \ + MG44_15PL & MG44_16PL & MG44_17PL & MG44_18PL) + +// +// Beginning of MG45: +// +#if (G41PL >= G45PL) || (G41PL == 0) +#define MG45_11PL ~(1) +#else +#define MG45_11PL 0xFFFF +#endif +#if (G42PL >= G45PL) || (G42PL == 0) +#define MG45_12PL ~(1 << 1) +#else +#define MG45_12PL 0xFFFF +#endif +#if (G43PL >= G45PL) || (G43PL == 0) +#define MG45_13PL ~(1 << 2) +#else +#define MG45_13PL 0xFFFF +#endif +#if (G44PL >= G45PL) || (G44PL == 0) +#define MG45_14PL ~(1 << 3) +#else +#define MG45_14PL 0xFFFF +#endif +#if (G46PL >= G45PL) || (G46PL == 0) +#define MG45_16PL ~(1 << 5) +#else +#define MG45_16PL 0xFFFF +#endif +#if (G47PL >= G45PL) || (G47PL == 0) +#define MG45_17PL ~(1 << 6) +#else +#define MG45_17PL 0xFFFF +#endif +#if (G48PL >= G45PL) || (G48PL == 0) +#define MG45_18PL ~(1 << 7) +#else +#define MG45_18PL 0xFFFF +#endif +#define MG45_15PL 0x00EF +#define MG45 (MG45_11PL & MG45_12PL & MG45_13PL & MG45_14PL & \ + MG45_15PL & MG45_16PL & MG45_17PL & MG45_18PL) + +// +// Beginning of MG46: +// +#if (G41PL >= G46PL) || (G41PL == 0) +#define MG46_11PL ~(1) +#else +#define MG46_11PL 0xFFFF +#endif +#if (G42PL >= G46PL) || (G42PL == 0) +#define MG46_12PL ~(1 << 1) +#else +#define MG46_12PL 0xFFFF +#endif +#if (G43PL >= G46PL) || (G43PL == 0) +#define MG46_13PL ~(1 << 2) +#else +#define MG46_13PL 0xFFFF +#endif +#if (G44PL >= G46PL) || (G44PL == 0) +#define MG46_14PL ~(1 << 3) +#else +#define MG46_14PL 0xFFFF +#endif +#if (G45PL >= G46PL) || (G45PL == 0) +#define MG46_15PL ~(1 << 4) +#else +#define MG46_15PL 0xFFFF +#endif +#if (G47PL >= G46PL) || (G47PL == 0) +#define MG46_17PL ~(1 << 6) +#else +#define MG46_17PL 0xFFFF +#endif +#if (G48PL >= G46PL) || (G48PL == 0) +#define MG46_18PL ~(1 << 7) +#else +#define MG46_18PL 0xFFFF +#endif +#define MG46_16PL 0x00DF +#define MG46 (MG46_11PL & MG46_12PL & MG46_13PL & MG46_14PL & \ + MG46_15PL & MG46_16PL & MG46_17PL & MG46_18PL) + +// +// Beginning of MG47: +// +#if (G41PL >= G47PL) || (G41PL == 0) +#define MG47_11PL ~(1) +#else +#define MG47_11PL 0xFFFF +#endif +#if (G42PL >= G47PL) || (G42PL == 0) +#define MG47_12PL ~(1 << 1) +#else +#define MG47_12PL 0xFFFF +#endif +#if (G43PL >= G47PL) || (G43PL == 0) +#define MG47_13PL ~(1 << 2) +#else +#define MG47_13PL 0xFFFF +#endif +#if (G44PL >= G47PL) || (G44PL == 0) +#define MG47_14PL ~(1 << 3) +#else +#define MG47_14PL 0xFFFF +#endif +#if (G45PL >= G47PL) || (G45PL == 0) +#define MG47_15PL ~(1 << 4) +#else +#define MG47_15PL 0xFFFF +#endif +#if (G46PL >= G47PL) || (G46PL == 0) +#define MG47_16PL ~(1 << 5) +#else +#define MG47_16PL 0xFFFF +#endif +#if (G48PL >= G47PL) || (G48PL == 0) +#define MG47_18PL ~(1 << 7) +#else +#define MG47_18PL 0xFFFF +#endif +#define MG47_17PL 0x00BF +#define MG47 (MG47_11PL & MG47_12PL & MG47_13PL & MG47_14PL & \ + MG47_15PL & MG47_16PL & MG47_17PL & MG47_18PL) + +// +// Beginning of MG48: +// +#if (G41PL >= G48PL) || (G41PL == 0) +#define MG48_11PL ~(1) +#else +#define MG48_11PL 0xFFFF +#endif +#if (G42PL >= G48PL) || (G42PL == 0) +#define MG48_12PL ~(1 << 1) +#else +#define MG48_12PL 0xFFFF +#endif +#if (G43PL >= G48PL) || (G43PL == 0) +#define MG48_13PL ~(1 << 2) +#else +#define MG48_13PL 0xFFFF +#endif +#if (G44PL >= G48PL) || (G44PL == 0) +#define MG48_14PL ~(1 << 3) +#else +#define MG48_14PL 0xFFFF +#endif +#if (G45PL >= G48PL) || (G45PL == 0) +#define MG48_15PL ~(1 << 4) +#else +#define MG48_15PL 0xFFFF +#endif +#if (G46PL >= G48PL) || (G46PL == 0) +#define MG48_16PL ~(1 << 5) +#else +#define MG48_16PL 0xFFFF +#endif +#if (G47PL >= G48PL) || (G47PL == 0) +#define MG48_17PL ~(1 << 6) +#else +#define MG48_17PL 0xFFFF +#endif +#define MG48_18PL 0x007F +#define MG48 (MG48_11PL & MG48_12PL & MG48_13PL & MG48_14PL & \ + MG48_15PL & MG48_16PL & MG48_17PL & MG48_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG51 to MG58: +// + +// +// Beginning of MG51: +// +#if (G52PL >= G51PL) || (G52PL == 0) +#define MG51_12PL ~(1 << 1) +#else +#define MG51_12PL 0xFFFF +#endif +#if (G53PL >= G51PL) || (G53PL == 0) +#define MG51_13PL ~(1 << 2) +#else +#define MG51_13PL 0xFFFF +#endif +#if (G54PL >= G51PL) || (G54PL == 0) +#define MG51_14PL ~(1 << 3) +#else +#define MG51_14PL 0xFFFF +#endif +#if (G55PL >= G51PL) || (G55PL == 0) +#define MG51_15PL ~(1 << 4) +#else +#define MG51_15PL 0xFFFF +#endif +#if (G56PL >= G51PL) || (G56PL == 0) +#define MG51_16PL ~(1 << 5) +#else +#define MG51_16PL 0xFFFF +#endif +#if (G57PL >= G51PL) || (G57PL == 0) +#define MG51_17PL ~(1 << 6) +#else +#define MG51_17PL 0xFFFF +#endif +#if (G58PL >= G51PL) || (G58PL == 0) +#define MG51_18PL ~(1 << 7) +#else +#define MG51_18PL 0xFFFF +#endif +#define MG51_11PL 0x00FE +#define MG51 (MG51_11PL & MG51_12PL & MG51_13PL & MG51_14PL & \ + MG51_15PL & MG51_16PL & MG51_17PL & MG51_18PL) + +// +// Beginning of MG52: +// +#if (G51PL >= G52PL) || (G51PL == 0) +#define MG52_11PL ~(1) +#else +#define MG52_11PL 0xFFFF +#endif +#if (G53PL >= G52PL) || (G53PL == 0) +#define MG52_13PL ~(1 << 2) +#else +#define MG52_13PL 0xFFFF +#endif +#if (G54PL >= G52PL) || (G54PL == 0) +#define MG52_14PL ~(1 << 3) +#else +#define MG52_14PL 0xFFFF +#endif +#if (G55PL >= G52PL) || (G55PL == 0) +#define MG52_15PL ~(1 << 4) +#else +#define MG52_15PL 0xFFFF +#endif +#if (G56PL >= G52PL) || (G56PL == 0) +#define MG52_16PL ~(1 << 5) +#else +#define MG52_16PL 0xFFFF +#endif +#if (G57PL >= G52PL) || (G57PL == 0) +#define MG52_17PL ~(1 << 6) +#else +#define MG52_17PL 0xFFFF +#endif +#if (G58PL >= G52PL) || (G58PL == 0) +#define MG52_18PL ~(1 << 7) +#else +#define MG52_18PL 0xFFFF +#endif +#define MG52_12PL 0x00FD +#define MG52 (MG52_11PL & MG52_12PL & MG52_13PL & MG52_14PL & \ + MG52_15PL & MG52_16PL & MG52_17PL & MG52_18PL) + +// +// Beginning of MG53: +// +#if (G51PL >= G53PL) || (G51PL == 0) +#define MG53_11PL ~(1) +#else +#define MG53_11PL 0xFFFF +#endif +#if (G52PL >= G53PL) || (G52PL == 0) +#define MG53_12PL ~(1 << 1) +#else +#define MG53_12PL 0xFFFF +#endif +#if (G54PL >= G53PL) || (G54PL == 0) +#define MG53_14PL ~(1 << 3) +#else +#define MG53_14PL 0xFFFF +#endif +#if (G55PL >= G53PL) || (G55PL == 0) +#define MG53_15PL ~(1 << 4) +#else +#define MG53_15PL 0xFFFF +#endif +#if (G56PL >= G53PL) || (G56PL == 0) +#define MG53_16PL ~(1 << 5) +#else +#define MG53_16PL 0xFFFF +#endif +#if (G57PL >= G53PL) || (G57PL == 0) +#define MG53_17PL ~(1 << 6) +#else +#define MG53_17PL 0xFFFF +#endif +#if (G58PL >= G53PL) || (G58PL == 0) +#define MG53_18PL ~(1 << 7) +#else +#define MG53_18PL 0xFFFF +#endif +#define MG53_13PL 0x00FB +#define MG53 (MG53_11PL & MG53_12PL & MG53_13PL & MG53_14PL & \ + MG53_15PL & MG53_16PL & MG53_17PL & MG53_18PL) + +// +// Beginning of MG54: +// +#if (G51PL >= G54PL) || (G51PL == 0) +#define MG54_11PL ~(1) +#else +#define MG54_11PL 0xFFFF +#endif +#if (G52PL >= G54PL) || (G52PL == 0) +#define MG54_12PL ~(1 << 1) +#else +#define MG54_12PL 0xFFFF +#endif +#if (G53PL >= G54PL) || (G53PL == 0) +#define MG54_13PL ~(1 << 2) +#else +#define MG54_13PL 0xFFFF +#endif +#if (G55PL >= G54PL) || (G55PL == 0) +#define MG54_15PL ~(1 << 4) +#else +#define MG54_15PL 0xFFFF +#endif +#if (G56PL >= G54PL) || (G56PL == 0) +#define MG54_16PL ~(1 << 5) +#else +#define MG54_16PL 0xFFFF +#endif +#if (G57PL >= G54PL) || (G57PL == 0) +#define MG54_17PL ~(1 << 6) +#else +#define MG54_17PL 0xFFFF +#endif +#if (G58PL >= G54PL) || (G58PL == 0) +#define MG54_18PL ~(1 << 7) +#else +#define MG54_18PL 0xFFFF +#endif +#define MG54_14PL 0x00F7 +#define MG54 (MG54_11PL & MG54_12PL & MG54_13PL & MG54_14PL & \ + MG54_15PL & MG54_16PL & MG54_17PL & MG54_18PL) + +// +// Beginning of MG55: +// +#if (G51PL >= G55PL) || (G51PL == 0) +#define MG55_11PL ~(1) +#else +#define MG55_11PL 0xFFFF +#endif +#if (G52PL >= G55PL) || (G52PL == 0) +#define MG55_12PL ~(1 << 1) +#else +#define MG55_12PL 0xFFFF +#endif +#if (G53PL >= G55PL) || (G53PL == 0) +#define MG55_13PL ~(1 << 2) +#else +#define MG55_13PL 0xFFFF +#endif +#if (G54PL >= G55PL) || (G54PL == 0) +#define MG55_14PL ~(1 << 3) +#else +#define MG55_14PL 0xFFFF +#endif +#if (G56PL >= G55PL) || (G56PL == 0) +#define MG55_16PL ~(1 << 5) +#else +#define MG55_16PL 0xFFFF +#endif +#if (G57PL >= G55PL) || (G57PL == 0) +#define MG55_17PL ~(1 << 6) +#else +#define MG55_17PL 0xFFFF +#endif +#if (G58PL >= G55PL) || (G58PL == 0) +#define MG55_18PL ~(1 << 7) +#else +#define MG55_18PL 0xFFFF +#endif +#define MG55_15PL 0x00EF +#define MG55 (MG55_11PL & MG55_12PL & MG55_13PL & MG55_14PL & \ + MG55_15PL & MG55_16PL & MG55_17PL & MG55_18PL) + +// +// Beginning of MG56: +// +#if (G51PL >= G56PL) || (G51PL == 0) +#define MG56_11PL ~(1) +#else +#define MG56_11PL 0xFFFF +#endif +#if (G52PL >= G56PL) || (G52PL == 0) +#define MG56_12PL ~(1 << 1) +#else +#define MG56_12PL 0xFFFF +#endif +#if (G53PL >= G56PL) || (G53PL == 0) +#define MG56_13PL ~(1 << 2) +#else +#define MG56_13PL 0xFFFF +#endif +#if (G54PL >= G56PL) || (G54PL == 0) +#define MG56_14PL ~(1 << 3) +#else +#define MG56_14PL 0xFFFF +#endif +#if (G55PL >= G56PL) || (G55PL == 0) +#define MG56_15PL ~(1 << 4) +#else +#define MG56_15PL 0xFFFF +#endif +#if (G57PL >= G56PL) || (G57PL == 0) +#define MG56_17PL ~(1 << 6) +#else +#define MG56_17PL 0xFFFF +#endif +#if (G58PL >= G56PL) || (G58PL == 0) +#define MG56_18PL ~(1 << 7) +#else +#define MG56_18PL 0xFFFF +#endif +#define MG56_16PL 0x00DF +#define MG56 (MG56_11PL & MG56_12PL & MG56_13PL & MG56_14PL & \ + MG56_15PL & MG56_16PL & MG56_17PL & MG56_18PL) + +// +// Beginning of MG57: +// +#if (G51PL >= G57PL) || (G51PL == 0) +#define MG57_11PL ~(1) +#else +#define MG57_11PL 0xFFFF +#endif +#if (G52PL >= G57PL) || (G52PL == 0) +#define MG57_12PL ~(1 << 1) +#else +#define MG57_12PL 0xFFFF +#endif +#if (G53PL >= G57PL) || (G53PL == 0) +#define MG57_13PL ~(1 << 2) +#else +#define MG57_13PL 0xFFFF +#endif +#if (G54PL >= G57PL) || (G54PL == 0) +#define MG57_14PL ~(1 << 3) +#else +#define MG57_14PL 0xFFFF +#endif +#if (G55PL >= G57PL) || (G55PL == 0) +#define MG57_15PL ~(1 << 4) +#else +#define MG57_15PL 0xFFFF +#endif +#if (G56PL >= G57PL) || (G56PL == 0) +#define MG57_16PL ~(1 << 5) +#else +#define MG57_16PL 0xFFFF +#endif +#if (G58PL >= G57PL) || (G58PL == 0) +#define MG57_18PL ~(1 << 7) +#else +#define MG57_18PL 0xFFFF +#endif +#define MG57_17PL 0x00BF +#define MG57 (MG57_11PL & MG57_12PL & MG57_13PL & MG57_14PL & \ + MG57_15PL & MG57_16PL & MG57_17PL & MG57_18PL) + +// +// Beginning of MG58: +// +#if (G51PL >= G58PL) || (G51PL == 0) +#define MG58_11PL ~(1) +#else +#define MG58_11PL 0xFFFF +#endif +#if (G52PL >= G58PL) || (G52PL == 0) +#define MG58_12PL ~(1 << 1) +#else +#define MG58_12PL 0xFFFF +#endif +#if (G53PL >= G58PL) || (G53PL == 0) +#define MG58_13PL ~(1 << 2) +#else +#define MG58_13PL 0xFFFF +#endif +#if (G54PL >= G58PL) || (G54PL == 0) +#define MG58_14PL ~(1 << 3) +#else +#define MG58_14PL 0xFFFF +#endif +#if (G55PL >= G58PL) || (G55PL == 0) +#define MG58_15PL ~(1 << 4) +#else +#define MG58_15PL 0xFFFF +#endif +#if (G56PL >= G58PL) || (G56PL == 0) +#define MG58_16PL ~(1 << 5) +#else +#define MG58_16PL 0xFFFF +#endif +#if (G57PL >= G58PL) || (G57PL == 0) +#define MG58_17PL ~(1 << 6) +#else +#define MG58_17PL 0xFFFF +#endif +#define MG58_18PL 0x007F +#define MG58 (MG58_11PL & MG58_12PL & MG58_13PL & MG58_14PL & \ + MG58_15PL & MG58_16PL & MG58_17PL & MG58_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG61 to MG68: +// + +// +// Beginning of MG61: +// +#if (G62PL >= G61PL) || (G62PL == 0) +#define MG61_12PL ~(1 << 1) +#else +#define MG61_12PL 0xFFFF +#endif +#if (G63PL >= G61PL) || (G63PL == 0) +#define MG61_13PL ~(1 << 2) +#else +#define MG61_13PL 0xFFFF +#endif +#if (G64PL >= G61PL) || (G64PL == 0) +#define MG61_14PL ~(1 << 3) +#else +#define MG61_14PL 0xFFFF +#endif +#if (G65PL >= G61PL) || (G65PL == 0) +#define MG61_15PL ~(1 << 4) +#else +#define MG61_15PL 0xFFFF +#endif +#if (G66PL >= G61PL) || (G66PL == 0) +#define MG61_16PL ~(1 << 5) +#else +#define MG61_16PL 0xFFFF +#endif +#if (G67PL >= G61PL) || (G67PL == 0) +#define MG61_17PL ~(1 << 6) +#else +#define MG61_17PL 0xFFFF +#endif +#if (G68PL >= G61PL) || (G68PL == 0) +#define MG61_18PL ~(1 << 7) +#else +#define MG61_18PL 0xFFFF +#endif +#define MG61_11PL 0x00FE +#define MG61 (MG61_11PL & MG61_12PL & MG61_13PL & MG61_14PL & \ + MG61_15PL & MG61_16PL & MG61_17PL & MG61_18PL) + +// +// Beginning of MG62: +// +#if (G61PL >= G62PL) || (G61PL == 0) +#define MG62_11PL ~(1) +#else +#define MG62_11PL 0xFFFF +#endif +#if (G63PL >= G62PL) || (G63PL == 0) +#define MG62_13PL ~(1 << 2) +#else +#define MG62_13PL 0xFFFF +#endif +#if (G64PL >= G62PL) || (G64PL == 0) +#define MG62_14PL ~(1 << 3) +#else +#define MG62_14PL 0xFFFF +#endif +#if (G65PL >= G62PL) || (G65PL == 0) +#define MG62_15PL ~(1 << 4) +#else +#define MG62_15PL 0xFFFF +#endif +#if (G66PL >= G62PL) || (G66PL == 0) +#define MG62_16PL ~(1 << 5) +#else +#define MG62_16PL 0xFFFF +#endif +#if (G67PL >= G62PL) || (G67PL == 0) +#define MG62_17PL ~(1 << 6) +#else +#define MG62_17PL 0xFFFF +#endif +#if (G68PL >= G62PL) || (G68PL == 0) +#define MG62_18PL ~(1 << 7) +#else +#define MG62_18PL 0xFFFF +#endif +#define MG62_12PL 0x00FD +#define MG62 (MG62_11PL & MG62_12PL & MG62_13PL & MG62_14PL & \ + MG62_15PL & MG62_16PL & MG62_17PL & MG62_18PL) + +// +// Beginning of MG63: +// +#if (G61PL >= G63PL) || (G61PL == 0) +#define MG63_11PL ~(1) +#else +#define MG63_11PL 0xFFFF +#endif +#if (G62PL >= G63PL) || (G62PL == 0) +#define MG63_12PL ~(1 << 1) +#else +#define MG63_12PL 0xFFFF +#endif +#if (G64PL >= G63PL) || (G64PL == 0) +#define MG63_14PL ~(1 << 3) +#else +#define MG63_14PL 0xFFFF +#endif +#if (G65PL >= G63PL) || (G65PL == 0) +#define MG63_15PL ~(1 << 4) +#else +#define MG63_15PL 0xFFFF +#endif +#if (G66PL >= G63PL) || (G66PL == 0) +#define MG63_16PL ~(1 << 5) +#else +#define MG63_16PL 0xFFFF +#endif +#if (G67PL >= G63PL) || (G67PL == 0) +#define MG63_17PL ~(1 << 6) +#else +#define MG63_17PL 0xFFFF +#endif +#if (G68PL >= G63PL) || (G68PL == 0) +#define MG63_18PL ~(1 << 7) +#else +#define MG63_18PL 0xFFFF +#endif +#define MG63_13PL 0x00FB +#define MG63 (MG63_11PL & MG63_12PL & MG63_13PL & MG63_14PL & \ + MG63_15PL & MG63_16PL & MG63_17PL & MG63_18PL) + +// +// Beginning of MG64: +// +#if (G61PL >= G64PL) || (G61PL == 0) +#define MG64_11PL ~(1) +#else +#define MG64_11PL 0xFFFF +#endif +#if (G62PL >= G64PL) || (G62PL == 0) +#define MG64_12PL ~(1 << 1) +#else +#define MG64_12PL 0xFFFF +#endif +#if (G63PL >= G64PL) || (G63PL == 0) +#define MG64_13PL ~(1 << 2) +#else +#define MG64_13PL 0xFFFF +#endif +#if (G65PL >= G64PL) || (G65PL == 0) +#define MG64_15PL ~(1 << 4) +#else +#define MG64_15PL 0xFFFF +#endif +#if (G66PL >= G64PL) || (G66PL == 0) +#define MG64_16PL ~(1 << 5) +#else +#define MG64_16PL 0xFFFF +#endif +#if (G67PL >= G64PL) || (G67PL == 0) +#define MG64_17PL ~(1 << 6) +#else +#define MG64_17PL 0xFFFF +#endif +#if (G68PL >= G64PL) || (G68PL == 0) +#define MG64_18PL ~(1 << 7) +#else +#define MG64_18PL 0xFFFF +#endif +#define MG64_14PL 0x00F7 +#define MG64 (MG64_11PL & MG64_12PL & MG64_13PL & MG64_14PL & \ + MG64_15PL & MG64_16PL & MG64_17PL & MG64_18PL) + +// +// Beginning of MG65: +// +#if (G61PL >= G65PL) || (G61PL == 0) +#define MG65_11PL ~(1) +#else +#define MG65_11PL 0xFFFF +#endif +#if (G62PL >= G65PL) || (G62PL == 0) +#define MG65_12PL ~(1 << 1) +#else +#define MG65_12PL 0xFFFF +#endif +#if (G63PL >= G65PL) || (G63PL == 0) +#define MG65_13PL ~(1 << 2) +#else +#define MG65_13PL 0xFFFF +#endif +#if (G64PL >= G65PL) || (G64PL == 0) +#define MG65_14PL ~(1 << 3) +#else +#define MG65_14PL 0xFFFF +#endif +#if (G66PL >= G65PL) || (G66PL == 0) +#define MG65_16PL ~(1 << 5) +#else +#define MG65_16PL 0xFFFF +#endif +#if (G67PL >= G65PL) || (G67PL == 0) +#define MG65_17PL ~(1 << 6) +#else +#define MG65_17PL 0xFFFF +#endif +#if (G68PL >= G65PL) || (G68PL == 0) +#define MG65_18PL ~(1 << 7) +#else +#define MG65_18PL 0xFFFF +#endif +#define MG65_15PL 0x00EF +#define MG65 (MG65_11PL & MG65_12PL & MG65_13PL & MG65_14PL & \ + MG65_15PL & MG65_16PL & MG65_17PL & MG65_18PL) + +// +// Beginning of MG66: +// +#if (G61PL >= G66PL) || (G61PL == 0) +#define MG66_11PL ~(1) +#else +#define MG66_11PL 0xFFFF +#endif +#if (G62PL >= G66PL) || (G62PL == 0) +#define MG66_12PL ~(1 << 1) +#else +#define MG66_12PL 0xFFFF +#endif +#if (G63PL >= G66PL) || (G63PL == 0) +#define MG66_13PL ~(1 << 2) +#else +#define MG66_13PL 0xFFFF +#endif +#if (G64PL >= G66PL) || (G64PL == 0) +#define MG66_14PL ~(1 << 3) +#else +#define MG66_14PL 0xFFFF +#endif +#if (G65PL >= G66PL) || (G65PL == 0) +#define MG66_15PL ~(1 << 4) +#else +#define MG66_15PL 0xFFFF +#endif +#if (G67PL >= G66PL) || (G67PL == 0) +#define MG66_17PL ~(1 << 6) +#else +#define MG66_17PL 0xFFFF +#endif +#if (G68PL >= G66PL) || (G68PL == 0) +#define MG66_18PL ~(1 << 7) +#else +#define MG66_18PL 0xFFFF +#endif +#define MG66_16PL 0x00DF +#define MG66 (MG66_11PL & MG66_12PL & MG66_13PL & MG66_14PL & \ + MG66_15PL & MG66_16PL & MG66_17PL & MG66_18PL) + +// +// Beginning of MG67: +// +#if (G61PL >= G67PL) || (G61PL == 0) +#define MG67_11PL ~(1) +#else +#define MG67_11PL 0xFFFF +#endif +#if (G62PL >= G67PL) || (G62PL == 0) +#define MG67_12PL ~(1 << 1) +#else +#define MG67_12PL 0xFFFF +#endif +#if (G63PL >= G67PL) || (G63PL == 0) +#define MG67_13PL ~(1 << 2) +#else +#define MG67_13PL 0xFFFF +#endif +#if (G64PL >= G67PL) || (G64PL == 0) +#define MG67_14PL ~(1 << 3) +#else +#define MG67_14PL 0xFFFF +#endif +#if (G65PL >= G67PL) || (G65PL == 0) +#define MG67_15PL ~(1 << 4) +#else +#define MG67_15PL 0xFFFF +#endif +#if (G66PL >= G67PL) || (G66PL == 0) +#define MG67_16PL ~(1 << 5) +#else +#define MG67_16PL 0xFFFF +#endif +#if (G68PL >= G67PL) || (G68PL == 0) +#define MG67_18PL ~(1 << 7) +#else +#define MG67_18PL 0xFFFF +#endif +#define MG67_17PL 0x00BF +#define MG67 (MG67_11PL & MG67_12PL & MG67_13PL & MG67_14PL & \ + MG67_15PL & MG67_16PL & MG67_17PL & MG67_18PL) + +// +// Beginning of MG68: +// +#if (G61PL >= G68PL) || (G61PL == 0) +#define MG68_11PL ~(1) +#else +#define MG68_11PL 0xFFFF +#endif +#if (G62PL >= G68PL) || (G62PL == 0) +#define MG68_12PL ~(1 << 1) +#else +#define MG68_12PL 0xFFFF +#endif +#if (G63PL >= G68PL) || (G63PL == 0) +#define MG68_13PL ~(1 << 2) +#else +#define MG68_13PL 0xFFFF +#endif +#if (G64PL >= G68PL) || (G64PL == 0) +#define MG68_14PL ~(1 << 3) +#else +#define MG68_14PL 0xFFFF +#endif +#if (G65PL >= G68PL) || (G65PL == 0) +#define MG68_15PL ~(1 << 4) +#else +#define MG68_15PL 0xFFFF +#endif +#if (G66PL >= G68PL) || (G66PL == 0) +#define MG68_16PL ~(1 << 5) +#else +#define MG68_16PL 0xFFFF +#endif +#if (G67PL >= G68PL) || (G67PL == 0) +#define MG68_17PL ~(1 << 6) +#else +#define MG68_17PL 0xFFFF +#endif +#define MG68_18PL 0x007F +#define MG68 (MG68_11PL & MG68_12PL & MG68_13PL & MG68_14PL & \ + MG68_15PL & MG68_16PL & MG68_17PL & MG68_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG71 to MG78: +// + +// +// Beginning of MG71: +// +#if (G72PL >= G71PL) || (G72PL == 0) +#define MG71_12PL ~(1 << 1) +#else +#define MG71_12PL 0xFFFF +#endif +#if (G73PL >= G71PL) || (G73PL == 0) +#define MG71_13PL ~(1 << 2) +#else +#define MG71_13PL 0xFFFF +#endif +#if (G74PL >= G71PL) || (G74PL == 0) +#define MG71_14PL ~(1 << 3) +#else +#define MG71_14PL 0xFFFF +#endif +#if (G75PL >= G71PL) || (G75PL == 0) +#define MG71_15PL ~(1 << 4) +#else +#define MG71_15PL 0xFFFF +#endif +#if (G76PL >= G71PL) || (G76PL == 0) +#define MG71_16PL ~(1 << 5) +#else +#define MG71_16PL 0xFFFF +#endif +#if (G77PL >= G71PL) || (G77PL == 0) +#define MG71_17PL ~(1 << 6) +#else +#define MG71_17PL 0xFFFF +#endif +#if (G78PL >= G71PL) || (G78PL == 0) +#define MG71_18PL ~(1 << 7) +#else +#define MG71_18PL 0xFFFF +#endif +#define MG71_11PL 0x00FE +#define MG71 (MG71_11PL & MG71_12PL & MG71_13PL & MG71_14PL & \ + MG71_15PL & MG71_16PL & MG71_17PL & MG71_18PL) + +// +// Beginning of MG72: +// +#if (G71PL >= G72PL) || (G71PL == 0) +#define MG72_11PL ~(1) +#else +#define MG72_11PL 0xFFFF +#endif +#if (G73PL >= G72PL) || (G73PL == 0) +#define MG72_13PL ~(1 << 2) +#else +#define MG72_13PL 0xFFFF +#endif +#if (G74PL >= G72PL) || (G74PL == 0) +#define MG72_14PL ~(1 << 3) +#else +#define MG72_14PL 0xFFFF +#endif +#if (G75PL >= G72PL) || (G75PL == 0) +#define MG72_15PL ~(1 << 4) +#else +#define MG72_15PL 0xFFFF +#endif +#if (G76PL >= G72PL) || (G76PL == 0) +#define MG72_16PL ~(1 << 5) +#else +#define MG72_16PL 0xFFFF +#endif +#if (G77PL >= G72PL) || (G77PL == 0) +#define MG72_17PL ~(1 << 6) +#else +#define MG72_17PL 0xFFFF +#endif +#if (G78PL >= G72PL) || (G78PL == 0) +#define MG72_18PL ~(1 << 7) +#else +#define MG72_18PL 0xFFFF +#endif +#define MG72_12PL 0x00FD +#define MG72 (MG72_11PL & MG72_12PL & MG72_13PL & MG72_14PL & \ + MG72_15PL & MG72_16PL & MG72_17PL & MG72_18PL) + +// +// Beginning of MG73: +// +#if (G71PL >= G73PL) || (G71PL == 0) +#define MG73_11PL ~(1) +#else +#define MG73_11PL 0xFFFF +#endif +#if (G72PL >= G73PL) || (G72PL == 0) +#define MG73_12PL ~(1 << 1) +#else +#define MG73_12PL 0xFFFF +#endif +#if (G74PL >= G73PL) || (G74PL == 0) +#define MG73_14PL ~(1 << 3) +#else +#define MG73_14PL 0xFFFF +#endif +#if (G75PL >= G73PL) || (G75PL == 0) +#define MG73_15PL ~(1 << 4) +#else +#define MG73_15PL 0xFFFF +#endif +#if (G76PL >= G73PL) || (G76PL == 0) +#define MG73_16PL ~(1 << 5) +#else +#define MG73_16PL 0xFFFF +#endif +#if (G77PL >= G73PL) || (G77PL == 0) +#define MG73_17PL ~(1 << 6) +#else +#define MG73_17PL 0xFFFF +#endif +#if (G78PL >= G73PL) || (G78PL == 0) +#define MG73_18PL ~(1 << 7) +#else +#define MG73_18PL 0xFFFF +#endif +#define MG73_13PL 0x00FB +#define MG73 (MG73_11PL & MG73_12PL & MG73_13PL & MG73_14PL & \ + MG73_15PL & MG73_16PL & MG73_17PL & MG73_18PL) + +// +// Beginning of MG74: +// +#if (G71PL >= G74PL) || (G71PL == 0) +#define MG74_11PL ~(1) +#else +#define MG74_11PL 0xFFFF +#endif +#if (G72PL >= G74PL) || (G72PL == 0) +#define MG74_12PL ~(1 << 1) +#else +#define MG74_12PL 0xFFFF +#endif +#if (G73PL >= G74PL) || (G73PL == 0) +#define MG74_13PL ~(1 << 2) +#else +#define MG74_13PL 0xFFFF +#endif +#if (G75PL >= G74PL) || (G75PL == 0) +#define MG74_15PL ~(1 << 4) +#else +#define MG74_15PL 0xFFFF +#endif +#if (G76PL >= G74PL) || (G76PL == 0) +#define MG74_16PL ~(1 << 5) +#else +#define MG74_16PL 0xFFFF +#endif +#if (G77PL >= G74PL) || (G77PL == 0) +#define MG74_17PL ~(1 << 6) +#else +#define MG74_17PL 0xFFFF +#endif +#if (G78PL >= G74PL) || (G78PL == 0) +#define MG74_18PL ~(1 << 7) +#else +#define MG74_18PL 0xFFFF +#endif +#define MG74_14PL 0x00F7 +#define MG74 (MG74_11PL & MG74_12PL & MG74_13PL & MG74_14PL & \ + MG74_15PL & MG74_16PL & MG74_17PL & MG74_18PL) + +// +// Beginning of MG75: +// +#if (G71PL >= G75PL) || (G71PL == 0) +#define MG75_11PL ~(1) +#else +#define MG75_11PL 0xFFFF +#endif +#if (G72PL >= G75PL) || (G72PL == 0) +#define MG75_12PL ~(1 << 1) +#else +#define MG75_12PL 0xFFFF +#endif +#if (G73PL >= G75PL) || (G73PL == 0) +#define MG75_13PL ~(1 << 2) +#else +#define MG75_13PL 0xFFFF +#endif +#if (G74PL >= G75PL) || (G74PL == 0) +#define MG75_14PL ~(1 << 3) +#else +#define MG75_14PL 0xFFFF +#endif +#if (G76PL >= G75PL) || (G76PL == 0) +#define MG75_16PL ~(1 << 5) +#else +#define MG75_16PL 0xFFFF +#endif +#if (G77PL >= G75PL) || (G77PL == 0) +#define MG75_17PL ~(1 << 6) +#else +#define MG75_17PL 0xFFFF +#endif +#if (G78PL >= G75PL) || (G78PL == 0) +#define MG75_18PL ~(1 << 7) +#else +#define MG75_18PL 0xFFFF +#endif +#define MG75_15PL 0x00EF +#define MG75 (MG75_11PL & MG75_12PL & MG75_13PL & MG75_14PL & \ + MG75_15PL & MG75_16PL & MG75_17PL & MG75_18PL) + +// +// Beginning of MG76: +// +#if (G71PL >= G76PL) || (G71PL == 0) +#define MG76_11PL ~(1) +#else +#define MG76_11PL 0xFFFF +#endif +#if (G72PL >= G76PL) || (G72PL == 0) +#define MG76_12PL ~(1 << 1) +#else +#define MG76_12PL 0xFFFF +#endif +#if (G73PL >= G76PL) || (G73PL == 0) +#define MG76_13PL ~(1 << 2) +#else +#define MG76_13PL 0xFFFF +#endif +#if (G74PL >= G76PL) || (G74PL == 0) +#define MG76_14PL ~(1 << 3) +#else +#define MG76_14PL 0xFFFF +#endif +#if (G75PL >= G76PL) || (G75PL == 0) +#define MG76_15PL ~(1 << 4) +#else +#define MG76_15PL 0xFFFF +#endif +#if (G77PL >= G76PL) || (G77PL == 0) +#define MG76_17PL ~(1 << 6) +#else +#define MG76_17PL 0xFFFF +#endif +#if (G78PL >= G76PL) || (G78PL == 0) +#define MG76_18PL ~(1 << 7) +#else +#define MG76_18PL 0xFFFF +#endif +#define MG76_16PL 0x00DF +#define MG76 (MG76_11PL & MG76_12PL & MG76_13PL & MG76_14PL & \ + MG76_15PL & MG76_16PL & MG76_17PL & MG76_18PL) + +// +// Beginning of MG77: +// +#if (G71PL >= G77PL) || (G71PL == 0) +#define MG77_11PL ~(1) +#else +#define MG77_11PL 0xFFFF +#endif +#if (G72PL >= G77PL) || (G72PL == 0) +#define MG77_12PL ~(1 << 1) +#else +#define MG77_12PL 0xFFFF +#endif +#if (G73PL >= G77PL) || (G73PL == 0) +#define MG77_13PL ~(1 << 2) +#else +#define MG77_13PL 0xFFFF +#endif +#if (G74PL >= G77PL) || (G74PL == 0) +#define MG77_14PL ~(1 << 3) +#else +#define MG77_14PL 0xFFFF +#endif +#if (G75PL >= G77PL) || (G75PL == 0) +#define MG77_15PL ~(1 << 4) +#else +#define MG77_15PL 0xFFFF +#endif +#if (G76PL >= G77PL) || (G76PL == 0) +#define MG77_16PL ~(1 << 5) +#else +#define MG77_16PL 0xFFFF +#endif +#if (G78PL >= G77PL) || (G78PL == 0) +#define MG77_18PL ~(1 << 7) +#else +#define MG77_18PL 0xFFFF +#endif +#define MG77_17PL 0x00BF +#define MG77 (MG77_11PL & MG77_12PL & MG77_13PL & MG77_14PL & \ + MG77_15PL & MG77_16PL & MG77_17PL & MG77_18PL) + +// +// Beginning of MG78: +// +#if (G71PL >= G78PL) || (G71PL == 0) +#define MG78_11PL ~(1) +#else +#define MG78_11PL 0xFFFF +#endif +#if (G72PL >= G78PL) || (G72PL == 0) +#define MG78_12PL ~(1 << 1) +#else +#define MG78_12PL 0xFFFF +#endif +#if (G73PL >= G78PL) || (G73PL == 0) +#define MG78_13PL ~(1 << 2) +#else +#define MG78_13PL 0xFFFF +#endif +#if (G74PL >= G78PL) || (G74PL == 0) +#define MG78_14PL ~(1 << 3) +#else +#define MG78_14PL 0xFFFF +#endif +#if (G75PL >= G78PL) || (G75PL == 0) +#define MG78_15PL ~(1 << 4) +#else +#define MG78_15PL 0xFFFF +#endif +#if (G76PL >= G78PL) || (G76PL == 0) +#define MG78_16PL ~(1 << 5) +#else +#define MG78_16PL 0xFFFF +#endif +#if (G77PL >= G78PL) || (G77PL == 0) +#define MG78_17PL ~(1 << 6) +#else +#define MG78_17PL 0xFFFF +#endif +#define MG78_18PL 0x007F +#define MG78 (MG78_11PL & MG78_12PL & MG78_13PL & MG78_14PL & \ + MG78_15PL & MG78_16PL & MG78_17PL & MG78_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG81 to MG88: +// + +// +// Beginning of MG81: +// +#if (G82PL >= G81PL) || (G82PL == 0) +#define MG81_12PL ~(1 << 1) +#else +#define MG81_12PL 0xFFFF +#endif +#if (G83PL >= G81PL) || (G83PL == 0) +#define MG81_13PL ~(1 << 2) +#else +#define MG81_13PL 0xFFFF +#endif +#if (G84PL >= G81PL) || (G84PL == 0) +#define MG81_14PL ~(1 << 3) +#else +#define MG81_14PL 0xFFFF +#endif +#if (G85PL >= G81PL) || (G85PL == 0) +#define MG81_15PL ~(1 << 4) +#else +#define MG81_15PL 0xFFFF +#endif +#if (G86PL >= G81PL) || (G86PL == 0) +#define MG81_16PL ~(1 << 5) +#else +#define MG81_16PL 0xFFFF +#endif +#if (G87PL >= G81PL) || (G87PL == 0) +#define MG81_17PL ~(1 << 6) +#else +#define MG81_17PL 0xFFFF +#endif +#if (G88PL >= G81PL) || (G88PL == 0) +#define MG81_18PL ~(1 << 7) +#else +#define MG81_18PL 0xFFFF +#endif +#define MG81_11PL 0x00FE +#define MG81 (MG81_11PL & MG81_12PL & MG81_13PL & MG81_14PL & \ + MG81_15PL & MG81_16PL & MG81_17PL & MG81_18PL) + +// +// Beginning of MG82: +// +#if (G81PL >= G82PL) || (G81PL == 0) +#define MG82_11PL ~(1) +#else +#define MG82_11PL 0xFFFF +#endif +#if (G83PL >= G82PL) || (G83PL == 0) +#define MG82_13PL ~(1 << 2) +#else +#define MG82_13PL 0xFFFF +#endif +#if (G84PL >= G82PL) || (G84PL == 0) +#define MG82_14PL ~(1 << 3) +#else +#define MG82_14PL 0xFFFF +#endif +#if (G85PL >= G82PL) || (G85PL == 0) +#define MG82_15PL ~(1 << 4) +#else +#define MG82_15PL 0xFFFF +#endif +#if (G86PL >= G82PL) || (G86PL == 0) +#define MG82_16PL ~(1 << 5) +#else +#define MG82_16PL 0xFFFF +#endif +#if (G87PL >= G82PL) || (G87PL == 0) +#define MG82_17PL ~(1 << 6) +#else +#define MG82_17PL 0xFFFF +#endif +#if (G88PL >= G82PL) || (G88PL == 0) +#define MG82_18PL ~(1 << 7) +#else +#define MG82_18PL 0xFFFF +#endif +#define MG82_12PL 0x00FD +#define MG82 (MG82_11PL & MG82_12PL & MG82_13PL & MG82_14PL & \ + MG82_15PL & MG82_16PL & MG82_17PL & MG82_18PL) + +// +// Beginning of MG83: +// +#if (G81PL >= G83PL) || (G81PL == 0) +#define MG83_11PL ~(1) +#else +#define MG83_11PL 0xFFFF +#endif +#if (G82PL >= G83PL) || (G82PL == 0) +#define MG83_12PL ~(1 << 1) +#else +#define MG83_12PL 0xFFFF +#endif +#if (G84PL >= G83PL) || (G84PL == 0) +#define MG83_14PL ~(1 << 3) +#else +#define MG83_14PL 0xFFFF +#endif +#if (G85PL >= G83PL) || (G85PL == 0) +#define MG83_15PL ~(1 << 4) +#else +#define MG83_15PL 0xFFFF +#endif +#if (G86PL >= G83PL) || (G86PL == 0) +#define MG83_16PL ~(1 << 5) +#else +#define MG83_16PL 0xFFFF +#endif +#if (G87PL >= G83PL) || (G87PL == 0) +#define MG83_17PL ~(1 << 6) +#else +#define MG83_17PL 0xFFFF +#endif +#if (G88PL >= G83PL) || (G88PL == 0) +#define MG83_18PL ~(1 << 7) +#else +#define MG83_18PL 0xFFFF +#endif +#define MG83_13PL 0x00FB +#define MG83 (MG83_11PL & MG83_12PL & MG83_13PL & MG83_14PL & \ + MG83_15PL & MG83_16PL & MG83_17PL & MG83_18PL) + +// +// Beginning of MG84: +// +#if (G81PL >= G84PL) || (G81PL == 0) +#define MG84_11PL ~(1) +#else +#define MG84_11PL 0xFFFF +#endif +#if (G82PL >= G84PL) || (G82PL == 0) +#define MG84_12PL ~(1 << 1) +#else +#define MG84_12PL 0xFFFF +#endif +#if (G83PL >= G84PL) || (G83PL == 0) +#define MG84_13PL ~(1 << 2) +#else +#define MG84_13PL 0xFFFF +#endif +#if (G85PL >= G84PL) || (G85PL == 0) +#define MG84_15PL ~(1 << 4) +#else +#define MG84_15PL 0xFFFF +#endif +#if (G86PL >= G84PL) || (G86PL == 0) +#define MG84_16PL ~(1 << 5) +#else +#define MG84_16PL 0xFFFF +#endif +#if (G87PL >= G84PL) || (G87PL == 0) +#define MG84_17PL ~(1 << 6) +#else +#define MG84_17PL 0xFFFF +#endif +#if (G88PL >= G84PL) || (G88PL == 0) +#define MG84_18PL ~(1 << 7) +#else +#define MG84_18PL 0xFFFF +#endif +#define MG84_14PL 0x00F7 +#define MG84 (MG84_11PL & MG84_12PL & MG84_13PL & MG84_14PL & \ + MG84_15PL & MG84_16PL & MG84_17PL & MG84_18PL) + +// +// Beginning of MG85: +// +#if (G81PL >= G85PL) || (G81PL == 0) +#define MG85_11PL ~(1) +#else +#define MG85_11PL 0xFFFF +#endif +#if (G82PL >= G85PL) || (G82PL == 0) +#define MG85_12PL ~(1 << 1) +#else +#define MG85_12PL 0xFFFF +#endif +#if (G83PL >= G85PL) || (G83PL == 0) +#define MG85_13PL ~(1 << 2) +#else +#define MG85_13PL 0xFFFF +#endif +#if (G84PL >= G85PL) || (G84PL == 0) +#define MG85_14PL ~(1 << 3) +#else +#define MG85_14PL 0xFFFF +#endif +#if (G86PL >= G85PL) || (G86PL == 0) +#define MG85_16PL ~(1 << 5) +#else +#define MG85_16PL 0xFFFF +#endif +#if (G87PL >= G85PL) || (G87PL == 0) +#define MG85_17PL ~(1 << 6) +#else +#define MG85_17PL 0xFFFF +#endif +#if (G88PL >= G85PL) || (G88PL == 0) +#define MG85_18PL ~(1 << 7) +#else +#define MG85_18PL 0xFFFF +#endif +#define MG85_15PL 0x00EF +#define MG85 (MG85_11PL & MG85_12PL & MG85_13PL & MG85_14PL & \ + MG85_15PL & MG85_16PL & MG85_17PL & MG85_18PL) + +// +// Beginning of MG86: +// +#if (G81PL >= G86PL) || (G81PL == 0) +#define MG86_11PL ~(1) +#else +#define MG86_11PL 0xFFFF +#endif +#if (G82PL >= G86PL) || (G82PL == 0) +#define MG86_12PL ~(1 << 1) +#else +#define MG86_12PL 0xFFFF +#endif +#if (G83PL >= G86PL) || (G83PL == 0) +#define MG86_13PL ~(1 << 2) +#else +#define MG86_13PL 0xFFFF +#endif +#if (G84PL >= G86PL) || (G84PL == 0) +#define MG86_14PL ~(1 << 3) +#else +#define MG86_14PL 0xFFFF +#endif +#if (G85PL >= G86PL) || (G85PL == 0) +#define MG86_15PL ~(1 << 4) +#else +#define MG86_15PL 0xFFFF +#endif +#if (G87PL >= G86PL) || (G87PL == 0) +#define MG86_17PL ~(1 << 6) +#else +#define MG86_17PL 0xFFFF +#endif +#if (G88PL >= G86PL) || (G88PL == 0) +#define MG86_18PL ~(1 << 7) +#else +#define MG86_18PL 0xFFFF +#endif +#define MG86_16PL 0x00DF +#define MG86 (MG86_11PL & MG86_12PL & MG86_13PL & MG86_14PL & \ + MG86_15PL & MG86_16PL & MG86_17PL & MG86_18PL) + +// +// Beginning of MG87: +// +#if (G81PL >= G87PL) || (G81PL == 0) +#define MG87_11PL ~(1) +#else +#define MG87_11PL 0xFFFF +#endif +#if (G82PL >= G87PL) || (G82PL == 0) +#define MG87_12PL ~(1 << 1) +#else +#define MG87_12PL 0xFFFF +#endif +#if (G83PL >= G87PL) || (G83PL == 0) +#define MG87_13PL ~(1 << 2) +#else +#define MG87_13PL 0xFFFF +#endif +#if (G84PL >= G87PL) || (G84PL == 0) +#define MG87_14PL ~(1 << 3) +#else +#define MG87_14PL 0xFFFF +#endif +#if (G85PL >= G87PL) || (G85PL == 0) +#define MG87_15PL ~(1 << 4) +#else +#define MG87_15PL 0xFFFF +#endif +#if (G86PL >= G87PL) || (G86PL == 0) +#define MG87_16PL ~(1 << 5) +#else +#define MG87_16PL 0xFFFF +#endif +#if (G88PL >= G87PL) || (G88PL == 0) +#define MG87_18PL ~(1 << 7) +#else +#define MG87_18PL 0xFFFF +#endif +#define MG87_17PL 0x00BF +#define MG87 (MG87_11PL & MG87_12PL & MG87_13PL & MG87_14PL & \ + MG87_15PL & MG87_16PL & MG87_17PL & MG87_18PL) + +// +// Beginning of MG88: +// +#if (G81PL >= G88PL) || (G81PL == 0) +#define MG88_11PL ~(1) +#else +#define MG88_11PL 0xFFFF +#endif +#if (G82PL >= G88PL) || (G82PL == 0) +#define MG88_12PL ~(1 << 1) +#else +#define MG88_12PL 0xFFFF +#endif +#if (G83PL >= G88PL) || (G83PL == 0) +#define MG88_13PL ~(1 << 2) +#else +#define MG88_13PL 0xFFFF +#endif +#if (G84PL >= G88PL) || (G84PL == 0) +#define MG88_14PL ~(1 << 3) +#else +#define MG88_14PL 0xFFFF +#endif +#if (G85PL >= G88PL) || (G85PL == 0) +#define MG88_15PL ~(1 << 4) +#else +#define MG88_15PL 0xFFFF +#endif +#if (G86PL >= G88PL) || (G86PL == 0) +#define MG88_16PL ~(1 << 5) +#else +#define MG88_16PL 0xFFFF +#endif +#if (G87PL >= G88PL) || (G87PL == 0) +#define MG88_17PL ~(1 << 6) +#else +#define MG88_17PL 0xFFFF +#endif +#define MG88_18PL 0x007F +#define MG88 (MG88_11PL & MG88_12PL & MG88_13PL & MG88_14PL & \ + MG88_15PL & MG88_16PL & MG88_17PL & MG88_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG91 to MG98: +// + +// +// Beginning of MG91: +// +#if (G92PL >= G91PL) || (G92PL == 0) +#define MG91_12PL ~(1 << 1) +#else +#define MG91_12PL 0xFFFF +#endif +#if (G93PL >= G91PL) || (G93PL == 0) +#define MG91_13PL ~(1 << 2) +#else +#define MG91_13PL 0xFFFF +#endif +#if (G94PL >= G91PL) || (G94PL == 0) +#define MG91_14PL ~(1 << 3) +#else +#define MG91_14PL 0xFFFF +#endif +#if (G95PL >= G91PL) || (G95PL == 0) +#define MG91_15PL ~(1 << 4) +#else +#define MG91_15PL 0xFFFF +#endif +#if (G96PL >= G91PL) || (G96PL == 0) +#define MG91_16PL ~(1 << 5) +#else +#define MG91_16PL 0xFFFF +#endif +#if (G97PL >= G91PL) || (G97PL == 0) +#define MG91_17PL ~(1 << 6) +#else +#define MG91_17PL 0xFFFF +#endif +#if (G98PL >= G91PL) || (G98PL == 0) +#define MG91_18PL ~(1 << 7) +#else +#define MG91_18PL 0xFFFF +#endif +#define MG91_11PL 0x00FE +#define MG91 (MG91_11PL & MG91_12PL & MG91_13PL & MG91_14PL & \ + MG91_15PL & MG91_16PL & MG91_17PL & MG91_18PL) + +// +// Beginning of MG92: +// +#if (G91PL >= G92PL) || (G91PL == 0) +#define MG92_11PL ~(1) +#else +#define MG92_11PL 0xFFFF +#endif +#if (G93PL >= G92PL) || (G93PL == 0) +#define MG92_13PL ~(1 << 2) +#else +#define MG92_13PL 0xFFFF +#endif +#if (G94PL >= G92PL) || (G94PL == 0) +#define MG92_14PL ~(1 << 3) +#else +#define MG92_14PL 0xFFFF +#endif +#if (G95PL >= G92PL) || (G95PL == 0) +#define MG92_15PL ~(1 << 4) +#else +#define MG92_15PL 0xFFFF +#endif +#if (G96PL >= G92PL) || (G96PL == 0) +#define MG92_16PL ~(1 << 5) +#else +#define MG92_16PL 0xFFFF +#endif +#if (G97PL >= G92PL) || (G97PL == 0) +#define MG92_17PL ~(1 << 6) +#else +#define MG92_17PL 0xFFFF +#endif +#if (G98PL >= G92PL) || (G98PL == 0) +#define MG92_18PL ~(1 << 7) +#else +#define MG92_18PL 0xFFFF +#endif +#define MG92_12PL 0x00FD +#define MG92 (MG92_11PL & MG92_12PL & MG92_13PL & MG92_14PL & \ + MG92_15PL & MG92_16PL & MG92_17PL & MG92_18PL) + +// +// Beginning of MG93: +// +#if (G91PL >= G93PL) || (G91PL == 0) +#define MG93_11PL ~(1) +#else +#define MG93_11PL 0xFFFF +#endif +#if (G92PL >= G93PL) || (G92PL == 0) +#define MG93_12PL ~(1 << 1) +#else +#define MG93_12PL 0xFFFF +#endif +#if (G94PL >= G93PL) || (G94PL == 0) +#define MG93_14PL ~(1 << 3) +#else +#define MG93_14PL 0xFFFF +#endif +#if (G95PL >= G93PL) || (G95PL == 0) +#define MG93_15PL ~(1 << 4) +#else +#define MG93_15PL 0xFFFF +#endif +#if (G96PL >= G93PL) || (G96PL == 0) +#define MG93_16PL ~(1 << 5) +#else +#define MG93_16PL 0xFFFF +#endif +#if (G97PL >= G93PL) || (G97PL == 0) +#define MG93_17PL ~(1 << 6) +#else +#define MG93_17PL 0xFFFF +#endif +#if (G98PL >= G93PL) || (G98PL == 0) +#define MG93_18PL ~(1 << 7) +#else +#define MG93_18PL 0xFFFF +#endif +#define MG93_13PL 0x00FB +#define MG93 (MG93_11PL & MG93_12PL & MG93_13PL & MG93_14PL & \ + MG93_15PL & MG93_16PL & MG93_17PL & MG93_18PL) + +// +// Beginning of MG94: +// +#if (G91PL >= G94PL) || (G91PL == 0) +#define MG94_11PL ~(1) +#else +#define MG94_11PL 0xFFFF +#endif +#if (G92PL >= G94PL) || (G92PL == 0) +#define MG94_12PL ~(1 << 1) +#else +#define MG94_12PL 0xFFFF +#endif +#if (G93PL >= G94PL) || (G93PL == 0) +#define MG94_13PL ~(1 << 2) +#else +#define MG94_13PL 0xFFFF +#endif +#if (G95PL >= G94PL) || (G95PL == 0) +#define MG94_15PL ~(1 << 4) +#else +#define MG94_15PL 0xFFFF +#endif +#if (G96PL >= G94PL) || (G96PL == 0) +#define MG94_16PL ~(1 << 5) +#else +#define MG94_16PL 0xFFFF +#endif +#if (G97PL >= G94PL) || (G97PL == 0) +#define MG94_17PL ~(1 << 6) +#else +#define MG94_17PL 0xFFFF +#endif +#if (G98PL >= G94PL) || (G98PL == 0) +#define MG94_18PL ~(1 << 7) +#else +#define MG94_18PL 0xFFFF +#endif +#define MG94_14PL 0x00F7 +#define MG94 (MG94_11PL & MG94_12PL & MG94_13PL & MG94_14PL & \ + MG94_15PL & MG94_16PL & MG94_17PL & MG94_18PL) + +// +// Beginning of MG95: +// +#if (G91PL >= G95PL) || (G91PL == 0) +#define MG95_11PL ~(1) +#else +#define MG95_11PL 0xFFFF +#endif +#if (G92PL >= G95PL) || (G92PL == 0) +#define MG95_12PL ~(1 << 1) +#else +#define MG95_12PL 0xFFFF +#endif +#if (G93PL >= G95PL) || (G93PL == 0) +#define MG95_13PL ~(1 << 2) +#else +#define MG95_13PL 0xFFFF +#endif +#if (G94PL >= G95PL) || (G94PL == 0) +#define MG95_14PL ~(1 << 3) +#else +#define MG95_14PL 0xFFFF +#endif +#if (G96PL >= G95PL) || (G96PL == 0) +#define MG95_16PL ~(1 << 5) +#else +#define MG95_16PL 0xFFFF +#endif +#if (G97PL >= G95PL) || (G97PL == 0) +#define MG95_17PL ~(1 << 6) +#else +#define MG95_17PL 0xFFFF +#endif +#if (G98PL >= G95PL) || (G98PL == 0) +#define MG95_18PL ~(1 << 7) +#else +#define MG95_18PL 0xFFFF +#endif +#define MG95_15PL 0x00EF +#define MG95 (MG95_11PL & MG95_12PL & MG95_13PL & MG95_14PL & \ + MG95_15PL & MG95_16PL & MG95_17PL & MG95_18PL) + +// +// Beginning of MG96: +// +#if (G91PL >= G96PL) || (G91PL == 0) +#define MG96_11PL ~(1) +#else +#define MG96_11PL 0xFFFF +#endif +#if (G92PL >= G96PL) || (G92PL == 0) +#define MG96_12PL ~(1 << 1) +#else +#define MG96_12PL 0xFFFF +#endif +#if (G93PL >= G96PL) || (G93PL == 0) +#define MG96_13PL ~(1 << 2) +#else +#define MG96_13PL 0xFFFF +#endif +#if (G94PL >= G96PL) || (G94PL == 0) +#define MG96_14PL ~(1 << 3) +#else +#define MG96_14PL 0xFFFF +#endif +#if (G95PL >= G96PL) || (G95PL == 0) +#define MG96_15PL ~(1 << 4) +#else +#define MG96_15PL 0xFFFF +#endif +#if (G97PL >= G96PL) || (G97PL == 0) +#define MG96_17PL ~(1 << 6) +#else +#define MG96_17PL 0xFFFF +#endif +#if (G98PL >= G96PL) || (G98PL == 0) +#define MG96_18PL ~(1 << 7) +#else +#define MG96_18PL 0xFFFF +#endif +#define MG96_16PL 0x00DF +#define MG96 (MG96_11PL & MG96_12PL & MG96_13PL & MG96_14PL & \ + MG96_15PL & MG96_16PL & MG96_17PL & MG96_18PL) + +// +// Beginning of MG97: +// +#if (G91PL >= G97PL) || (G91PL == 0) +#define MG97_11PL ~(1) +#else +#define MG97_11PL 0xFFFF +#endif +#if (G92PL >= G97PL) || (G92PL == 0) +#define MG97_12PL ~(1 << 1) +#else +#define MG97_12PL 0xFFFF +#endif +#if (G93PL >= G97PL) || (G93PL == 0) +#define MG97_13PL ~(1 << 2) +#else +#define MG97_13PL 0xFFFF +#endif +#if (G94PL >= G97PL) || (G94PL == 0) +#define MG97_14PL ~(1 << 3) +#else +#define MG97_14PL 0xFFFF +#endif +#if (G95PL >= G97PL) || (G95PL == 0) +#define MG97_15PL ~(1 << 4) +#else +#define MG97_15PL 0xFFFF +#endif +#if (G96PL >= G97PL) || (G96PL == 0) +#define MG97_16PL ~(1 << 5) +#else +#define MG97_16PL 0xFFFF +#endif +#if (G98PL >= G97PL) || (G98PL == 0) +#define MG97_18PL ~(1 << 7) +#else +#define MG97_18PL 0xFFFF +#endif +#define MG97_17PL 0x00BF +#define MG97 (MG97_11PL & MG97_12PL & MG97_13PL & MG97_14PL & \ + MG97_15PL & MG97_16PL & MG97_17PL & MG97_18PL) + +// +// Beginning of MG98: +// +#if (G91PL >= G98PL) || (G91PL == 0) +#define MG98_11PL ~(1) +#else +#define MG98_11PL 0xFFFF +#endif +#if (G92PL >= G98PL) || (G92PL == 0) +#define MG98_12PL ~(1 << 1) +#else +#define MG98_12PL 0xFFFF +#endif +#if (G93PL >= G98PL) || (G93PL == 0) +#define MG98_13PL ~(1 << 2) +#else +#define MG98_13PL 0xFFFF +#endif +#if (G94PL >= G98PL) || (G94PL == 0) +#define MG98_14PL ~(1 << 3) +#else +#define MG98_14PL 0xFFFF +#endif +#if (G95PL >= G98PL) || (G95PL == 0) +#define MG98_15PL ~(1 << 4) +#else +#define MG98_15PL 0xFFFF +#endif +#if (G96PL >= G98PL) || (G96PL == 0) +#define MG98_16PL ~(1 << 5) +#else +#define MG98_16PL 0xFFFF +#endif +#if (G97PL >= G98PL) || (G97PL == 0) +#define MG98_17PL ~(1 << 6) +#else +#define MG98_17PL 0xFFFF +#endif +#define MG98_18PL 0x007F +#define MG98 (MG98_11PL & MG98_12PL & MG98_13PL & MG98_14PL & \ + MG98_15PL & MG98_16PL & MG98_17PL & MG98_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG101 to MG108: +// + +// +// Beginning of MG101: +// +#if (G102PL >= G101PL) || (G102PL == 0) +#define MG101_12PL ~(1 << 1) +#else +#define MG101_12PL 0xFFFF +#endif +#if (G103PL >= G101PL) || (G103PL == 0) +#define MG101_13PL ~(1 << 2) +#else +#define MG101_13PL 0xFFFF +#endif +#if (G104PL >= G101PL) || (G104PL == 0) +#define MG101_14PL ~(1 << 3) +#else +#define MG101_14PL 0xFFFF +#endif +#if (G105PL >= G101PL) || (G105PL == 0) +#define MG101_15PL ~(1 << 4) +#else +#define MG101_15PL 0xFFFF +#endif +#if (G106PL >= G101PL) || (G106PL == 0) +#define MG101_16PL ~(1 << 5) +#else +#define MG101_16PL 0xFFFF +#endif +#if (G107PL >= G101PL) || (G107PL == 0) +#define MG101_17PL ~(1 << 6) +#else +#define MG101_17PL 0xFFFF +#endif +#if (G108PL >= G101PL) || (G108PL == 0) +#define MG101_18PL ~(1 << 7) +#else +#define MG101_18PL 0xFFFF +#endif +#define MG101_11PL 0x00FE +#define MG101 (MG101_11PL & MG101_12PL & MG101_13PL & MG101_14PL & \ + MG101_15PL & MG101_16PL & MG101_17PL & MG101_18PL) + +// +// Beginning of MG102: +// +#if (G101PL >= G102PL) || (G101PL == 0) +#define MG102_11PL ~(1) +#else +#define MG102_11PL 0xFFFF +#endif +#if (G103PL >= G102PL) || (G103PL == 0) +#define MG102_13PL ~(1 << 2) +#else +#define MG102_13PL 0xFFFF +#endif +#if (G104PL >= G102PL) || (G104PL == 0) +#define MG102_14PL ~(1 << 3) +#else +#define MG102_14PL 0xFFFF +#endif +#if (G105PL >= G102PL) || (G105PL == 0) +#define MG102_15PL ~(1 << 4) +#else +#define MG102_15PL 0xFFFF +#endif +#if (G106PL >= G102PL) || (G106PL == 0) +#define MG102_16PL ~(1 << 5) +#else +#define MG102_16PL 0xFFFF +#endif +#if (G107PL >= G102PL) || (G107PL == 0) +#define MG102_17PL ~(1 << 6) +#else +#define MG102_17PL 0xFFFF +#endif +#if (G108PL >= G102PL) || (G108PL == 0) +#define MG102_18PL ~(1 << 7) +#else +#define MG102_18PL 0xFFFF +#endif +#define MG102_12PL 0x00FD +#define MG102 (MG102_11PL & MG102_12PL & MG102_13PL & MG102_14PL & \ + MG102_15PL & MG102_16PL & MG102_17PL & MG102_18PL) + +// +// Beginning of MG103: +// +#if (G101PL >= G103PL) || (G101PL == 0) +#define MG103_11PL ~(1) +#else +#define MG103_11PL 0xFFFF +#endif +#if (G102PL >= G103PL) || (G102PL == 0) +#define MG103_12PL ~(1 << 1) +#else +#define MG103_12PL 0xFFFF +#endif +#if (G104PL >= G103PL) || (G104PL == 0) +#define MG103_14PL ~(1 << 3) +#else +#define MG103_14PL 0xFFFF +#endif +#if (G105PL >= G103PL) || (G105PL == 0) +#define MG103_15PL ~(1 << 4) +#else +#define MG103_15PL 0xFFFF +#endif +#if (G106PL >= G103PL) || (G106PL == 0) +#define MG103_16PL ~(1 << 5) +#else +#define MG103_16PL 0xFFFF +#endif +#if (G107PL >= G103PL) || (G107PL == 0) +#define MG103_17PL ~(1 << 6) +#else +#define MG103_17PL 0xFFFF +#endif +#if (G108PL >= G103PL) || (G108PL == 0) +#define MG103_18PL ~(1 << 7) +#else +#define MG103_18PL 0xFFFF +#endif +#define MG103_13PL 0x00FB +#define MG103 (MG103_11PL & MG103_12PL & MG103_13PL & MG103_14PL & \ + MG103_15PL & MG103_16PL & MG103_17PL & MG103_18PL) + +// +// Beginning of MG104: +// +#if (G101PL >= G104PL) || (G101PL == 0) +#define MG104_11PL ~(1) +#else +#define MG104_11PL 0xFFFF +#endif +#if (G102PL >= G104PL) || (G102PL == 0) +#define MG104_12PL ~(1 << 1) +#else +#define MG104_12PL 0xFFFF +#endif +#if (G103PL >= G104PL) || (G103PL == 0) +#define MG104_13PL ~(1 << 2) +#else +#define MG104_13PL 0xFFFF +#endif +#if (G105PL >= G104PL) || (G105PL == 0) +#define MG104_15PL ~(1 << 4) +#else +#define MG104_15PL 0xFFFF +#endif +#if (G106PL >= G104PL) || (G106PL == 0) +#define MG104_16PL ~(1 << 5) +#else +#define MG104_16PL 0xFFFF +#endif +#if (G107PL >= G104PL) || (G107PL == 0) +#define MG104_17PL ~(1 << 6) +#else +#define MG104_17PL 0xFFFF +#endif +#if (G108PL >= G104PL) || (G108PL == 0) +#define MG104_18PL ~(1 << 7) +#else +#define MG104_18PL 0xFFFF +#endif +#define MG104_14PL 0x00F7 +#define MG104 (MG104_11PL & MG104_12PL & MG104_13PL & MG104_14PL & \ + MG104_15PL & MG104_16PL & MG104_17PL & MG104_18PL) + +// +// Beginning of MG105: +// +#if (G101PL >= G105PL) || (G101PL == 0) +#define MG105_11PL ~(1) +#else +#define MG105_11PL 0xFFFF +#endif +#if (G102PL >= G105PL) || (G102PL == 0) +#define MG105_12PL ~(1 << 1) +#else +#define MG105_12PL 0xFFFF +#endif +#if (G103PL >= G105PL) || (G103PL == 0) +#define MG105_13PL ~(1 << 2) +#else +#define MG105_13PL 0xFFFF +#endif +#if (G104PL >= G105PL) || (G104PL == 0) +#define MG105_14PL ~(1 << 3) +#else +#define MG105_14PL 0xFFFF +#endif +#if (G106PL >= G105PL) || (G106PL == 0) +#define MG105_16PL ~(1 << 5) +#else +#define MG105_16PL 0xFFFF +#endif +#if (G107PL >= G105PL) || (G107PL == 0) +#define MG105_17PL ~(1 << 6) +#else +#define MG105_17PL 0xFFFF +#endif +#if (G108PL >= G105PL) || (G108PL == 0) +#define MG105_18PL ~(1 << 7) +#else +#define MG105_18PL 0xFFFF +#endif +#define MG105_15PL 0x00EF +#define MG105 (MG105_11PL & MG105_12PL & MG105_13PL & MG105_14PL & \ + MG105_15PL & MG105_16PL & MG105_17PL & MG105_18PL) + +// +// Beginning of MG106: +// +#if (G101PL >= G106PL) || (G101PL == 0) +#define MG106_11PL ~(1) +#else +#define MG106_11PL 0xFFFF +#endif +#if (G102PL >= G106PL) || (G102PL == 0) +#define MG106_12PL ~(1 << 1) +#else +#define MG106_12PL 0xFFFF +#endif +#if (G103PL >= G106PL) || (G103PL == 0) +#define MG106_13PL ~(1 << 2) +#else +#define MG106_13PL 0xFFFF +#endif +#if (G104PL >= G106PL) || (G104PL == 0) +#define MG106_14PL ~(1 << 3) +#else +#define MG106_14PL 0xFFFF +#endif +#if (G105PL >= G106PL) || (G105PL == 0) +#define MG106_15PL ~(1 << 4) +#else +#define MG106_15PL 0xFFFF +#endif +#if (G107PL >= G106PL) || (G107PL == 0) +#define MG106_17PL ~(1 << 6) +#else +#define MG106_17PL 0xFFFF +#endif +#if (G108PL >= G106PL) || (G108PL == 0) +#define MG106_18PL ~(1 << 7) +#else +#define MG106_18PL 0xFFFF +#endif +#define MG106_16PL 0x00DF +#define MG106 (MG106_11PL & MG106_12PL & MG106_13PL & MG106_14PL & \ + MG106_15PL & MG106_16PL & MG106_17PL & MG106_18PL) + +// +// Beginning of MG107: +// +#if (G101PL >= G107PL) || (G101PL == 0) +#define MG107_11PL ~(1) +#else +#define MG107_11PL 0xFFFF +#endif +#if (G102PL >= G107PL) || (G102PL == 0) +#define MG107_12PL ~(1 << 1) +#else +#define MG107_12PL 0xFFFF +#endif +#if (G103PL >= G107PL) || (G103PL == 0) +#define MG107_13PL ~(1 << 2) +#else +#define MG107_13PL 0xFFFF +#endif +#if (G104PL >= G107PL) || (G104PL == 0) +#define MG107_14PL ~(1 << 3) +#else +#define MG107_14PL 0xFFFF +#endif +#if (G105PL >= G107PL) || (G105PL == 0) +#define MG107_15PL ~(1 << 4) +#else +#define MG107_15PL 0xFFFF +#endif +#if (G106PL >= G107PL) || (G106PL == 0) +#define MG107_16PL ~(1 << 5) +#else +#define MG107_16PL 0xFFFF +#endif +#if (G108PL >= G107PL) || (G108PL == 0) +#define MG107_18PL ~(1 << 7) +#else +#define MG107_18PL 0xFFFF +#endif +#define MG107_17PL 0x00BF +#define MG107 (MG107_11PL & MG107_12PL & MG107_13PL & MG107_14PL & \ + MG107_15PL & MG107_16PL & MG107_17PL & MG107_18PL) + +// +// Beginning of MG108: +// +#if (G101PL >= G108PL) || (G101PL == 0) +#define MG108_11PL ~(1) +#else +#define MG108_11PL 0xFFFF +#endif +#if (G102PL >= G108PL) || (G102PL == 0) +#define MG108_12PL ~(1 << 1) +#else +#define MG108_12PL 0xFFFF +#endif +#if (G103PL >= G108PL) || (G103PL == 0) +#define MG108_13PL ~(1 << 2) +#else +#define MG108_13PL 0xFFFF +#endif +#if (G104PL >= G108PL) || (G104PL == 0) +#define MG108_14PL ~(1 << 3) +#else +#define MG108_14PL 0xFFFF +#endif +#if (G105PL >= G108PL) || (G105PL == 0) +#define MG108_15PL ~(1 << 4) +#else +#define MG108_15PL 0xFFFF +#endif +#if (G106PL >= G108PL) || (G106PL == 0) +#define MG108_16PL ~(1 << 5) +#else +#define MG108_16PL 0xFFFF +#endif +#if (G107PL >= G108PL) || (G107PL == 0) +#define MG108_17PL ~(1 << 6) +#else +#define MG108_17PL 0xFFFF +#endif +#define MG108_18PL 0x007F +#define MG108 (MG108_11PL & MG108_12PL & MG108_13PL & MG108_14PL & \ + MG108_15PL & MG108_16PL & MG108_17PL & MG108_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG111 to MG118: +// + +// +// Beginning of MG111: +// +#if (G112PL >= G111PL) || (G112PL == 0) +#define MG111_12PL ~(1 << 1) +#else +#define MG111_12PL 0xFFFF +#endif +#if (G113PL >= G111PL) || (G113PL == 0) +#define MG111_13PL ~(1 << 2) +#else +#define MG111_13PL 0xFFFF +#endif +#if (G114PL >= G111PL) || (G114PL == 0) +#define MG111_14PL ~(1 << 3) +#else +#define MG111_14PL 0xFFFF +#endif +#if (G115PL >= G111PL) || (G115PL == 0) +#define MG111_15PL ~(1 << 4) +#else +#define MG111_15PL 0xFFFF +#endif +#if (G116PL >= G111PL) || (G116PL == 0) +#define MG111_16PL ~(1 << 5) +#else +#define MG111_16PL 0xFFFF +#endif +#if (G117PL >= G111PL) || (G117PL == 0) +#define MG111_17PL ~(1 << 6) +#else +#define MG111_17PL 0xFFFF +#endif +#if (G118PL >= G111PL) || (G118PL == 0) +#define MG111_18PL ~(1 << 7) +#else +#define MG111_18PL 0xFFFF +#endif +#define MG111_11PL 0x00FE +#define MG111 (MG111_11PL & MG111_12PL & MG111_13PL & MG111_14PL & \ + MG111_15PL & MG111_16PL & MG111_17PL & MG111_18PL) + +// +// Beginning of MG112: +// +#if (G111PL >= G112PL) || (G111PL == 0) +#define MG112_11PL ~(1) +#else +#define MG112_11PL 0xFFFF +#endif +#if (G113PL >= G112PL) || (G113PL == 0) +#define MG112_13PL ~(1 << 2) +#else +#define MG112_13PL 0xFFFF +#endif +#if (G114PL >= G112PL) || (G114PL == 0) +#define MG112_14PL ~(1 << 3) +#else +#define MG112_14PL 0xFFFF +#endif +#if (G115PL >= G112PL) || (G115PL == 0) +#define MG112_15PL ~(1 << 4) +#else +#define MG112_15PL 0xFFFF +#endif +#if (G116PL >= G112PL) || (G116PL == 0) +#define MG112_16PL ~(1 << 5) +#else +#define MG112_16PL 0xFFFF +#endif +#if (G117PL >= G112PL) || (G117PL == 0) +#define MG112_17PL ~(1 << 6) +#else +#define MG112_17PL 0xFFFF +#endif +#if (G118PL >= G112PL) || (G118PL == 0) +#define MG112_18PL ~(1 << 7) +#else +#define MG112_18PL 0xFFFF +#endif +#define MG112_12PL 0x00FD +#define MG112 (MG112_11PL & MG112_12PL & MG112_13PL & MG112_14PL & \ + MG112_15PL & MG112_16PL & MG112_17PL & MG112_18PL) + +// +// Beginning of MG113: +// +#if (G111PL >= G113PL) || (G111PL == 0) +#define MG113_11PL ~(1) +#else +#define MG113_11PL 0xFFFF +#endif +#if (G112PL >= G113PL) || (G112PL == 0) +#define MG113_12PL ~(1 << 1) +#else +#define MG113_12PL 0xFFFF +#endif +#if (G114PL >= G113PL) || (G114PL == 0) +#define MG113_14PL ~(1 << 3) +#else +#define MG113_14PL 0xFFFF +#endif +#if (G115PL >= G113PL) || (G115PL == 0) +#define MG113_15PL ~(1 << 4) +#else +#define MG113_15PL 0xFFFF +#endif +#if (G116PL >= G113PL) || (G116PL == 0) +#define MG113_16PL ~(1 << 5) +#else +#define MG113_16PL 0xFFFF +#endif +#if (G117PL >= G113PL) || (G117PL == 0) +#define MG113_17PL ~(1 << 6) +#else +#define MG113_17PL 0xFFFF +#endif +#if (G118PL >= G113PL) || (G118PL == 0) +#define MG113_18PL ~(1 << 7) +#else +#define MG113_18PL 0xFFFF +#endif +#define MG113_13PL 0x00FB +#define MG113 (MG113_11PL & MG113_12PL & MG113_13PL & MG113_14PL & \ + MG113_15PL & MG113_16PL & MG113_17PL & MG113_18PL) + +// +// Beginning of MG114: +// +#if (G111PL >= G114PL) || (G111PL == 0) +#define MG114_11PL ~(1) +#else +#define MG114_11PL 0xFFFF +#endif +#if (G112PL >= G114PL) || (G112PL == 0) +#define MG114_12PL ~(1 << 1) +#else +#define MG114_12PL 0xFFFF +#endif +#if (G113PL >= G114PL) || (G113PL == 0) +#define MG114_13PL ~(1 << 2) +#else +#define MG114_13PL 0xFFFF +#endif +#if (G115PL >= G114PL) || (G115PL == 0) +#define MG114_15PL ~(1 << 4) +#else +#define MG114_15PL 0xFFFF +#endif +#if (G116PL >= G114PL) || (G116PL == 0) +#define MG114_16PL ~(1 << 5) +#else +#define MG114_16PL 0xFFFF +#endif +#if (G117PL >= G114PL) || (G117PL == 0) +#define MG114_17PL ~(1 << 6) +#else +#define MG114_17PL 0xFFFF +#endif +#if (G118PL >= G114PL) || (G118PL == 0) +#define MG114_18PL ~(1 << 7) +#else +#define MG114_18PL 0xFFFF +#endif +#define MG114_14PL 0x00F7 +#define MG114 (MG114_11PL & MG114_12PL & MG114_13PL & MG114_14PL & \ + MG114_15PL & MG114_16PL & MG114_17PL & MG114_18PL) + +// +// Beginning of MG115: +// +#if (G111PL >= G115PL) || (G111PL == 0) +#define MG115_11PL ~(1) +#else +#define MG115_11PL 0xFFFF +#endif +#if (G112PL >= G115PL) || (G112PL == 0) +#define MG115_12PL ~(1 << 1) +#else +#define MG115_12PL 0xFFFF +#endif +#if (G113PL >= G115PL) || (G113PL == 0) +#define MG115_13PL ~(1 << 2) +#else +#define MG115_13PL 0xFFFF +#endif +#if (G114PL >= G115PL) || (G114PL == 0) +#define MG115_14PL ~(1 << 3) +#else +#define MG115_14PL 0xFFFF +#endif +#if (G116PL >= G115PL) || (G116PL == 0) +#define MG115_16PL ~(1 << 5) +#else +#define MG115_16PL 0xFFFF +#endif +#if (G117PL >= G115PL) || (G117PL == 0) +#define MG115_17PL ~(1 << 6) +#else +#define MG115_17PL 0xFFFF +#endif +#if (G118PL >= G115PL) || (G118PL == 0) +#define MG115_18PL ~(1 << 7) +#else +#define MG115_18PL 0xFFFF +#endif +#define MG115_15PL 0x00EF +#define MG115 (MG115_11PL & MG115_12PL & MG115_13PL & MG115_14PL & \ + MG115_15PL & MG115_16PL & MG115_17PL & MG115_18PL) + +// +// Beginning of MG116: +// +#if (G111PL >= G116PL) || (G111PL == 0) +#define MG116_11PL ~(1) +#else +#define MG116_11PL 0xFFFF +#endif +#if (G112PL >= G116PL) || (G112PL == 0) +#define MG116_12PL ~(1 << 1) +#else +#define MG116_12PL 0xFFFF +#endif +#if (G113PL >= G116PL) || (G113PL == 0) +#define MG116_13PL ~(1 << 2) +#else +#define MG116_13PL 0xFFFF +#endif +#if (G114PL >= G116PL) || (G114PL == 0) +#define MG116_14PL ~(1 << 3) +#else +#define MG116_14PL 0xFFFF +#endif +#if (G115PL >= G116PL) || (G115PL == 0) +#define MG116_15PL ~(1 << 4) +#else +#define MG116_15PL 0xFFFF +#endif +#if (G117PL >= G116PL) || (G117PL == 0) +#define MG116_17PL ~(1 << 6) +#else +#define MG116_17PL 0xFFFF +#endif +#if (G118PL >= G116PL) || (G118PL == 0) +#define MG116_18PL ~(1 << 7) +#else +#define MG116_18PL 0xFFFF +#endif +#define MG116_16PL 0x00DF +#define MG116 (MG116_11PL & MG116_12PL & MG116_13PL & MG116_14PL & \ + MG116_15PL & MG116_16PL & MG116_17PL & MG116_18PL) + +// +// Beginning of MG117: +// +#if (G111PL >= G117PL) || (G111PL == 0) +#define MG117_11PL ~(1) +#else +#define MG117_11PL 0xFFFF +#endif +#if (G112PL >= G117PL) || (G112PL == 0) +#define MG117_12PL ~(1 << 1) +#else +#define MG117_12PL 0xFFFF +#endif +#if (G113PL >= G117PL) || (G113PL == 0) +#define MG117_13PL ~(1 << 2) +#else +#define MG117_13PL 0xFFFF +#endif +#if (G114PL >= G117PL) || (G114PL == 0) +#define MG117_14PL ~(1 << 3) +#else +#define MG117_14PL 0xFFFF +#endif +#if (G115PL >= G117PL) || (G115PL == 0) +#define MG117_15PL ~(1 << 4) +#else +#define MG117_15PL 0xFFFF +#endif +#if (G116PL >= G117PL) || (G116PL == 0) +#define MG117_16PL ~(1 << 5) +#else +#define MG117_16PL 0xFFFF +#endif +#if (G118PL >= G117PL) || (G118PL == 0) +#define MG117_18PL ~(1 << 7) +#else +#define MG117_18PL 0xFFFF +#endif +#define MG117_17PL 0x00BF +#define MG117 (MG117_11PL & MG117_12PL & MG117_13PL & MG117_14PL & \ + MG117_15PL & MG117_16PL & MG117_17PL & MG117_18PL) + +// +// Beginning of MG118: +// +#if (G111PL >= G118PL) || (G111PL == 0) +#define MG118_11PL ~(1) +#else +#define MG118_11PL 0xFFFF +#endif +#if (G112PL >= G118PL) || (G112PL == 0) +#define MG118_12PL ~(1 << 1) +#else +#define MG118_12PL 0xFFFF +#endif +#if (G113PL >= G118PL) || (G113PL == 0) +#define MG118_13PL ~(1 << 2) +#else +#define MG118_13PL 0xFFFF +#endif +#if (G114PL >= G118PL) || (G114PL == 0) +#define MG118_14PL ~(1 << 3) +#else +#define MG118_14PL 0xFFFF +#endif +#if (G115PL >= G118PL) || (G115PL == 0) +#define MG118_15PL ~(1 << 4) +#else +#define MG118_15PL 0xFFFF +#endif +#if (G116PL >= G118PL) || (G116PL == 0) +#define MG118_16PL ~(1 << 5) +#else +#define MG118_16PL 0xFFFF +#endif +#if (G117PL >= G118PL) || (G117PL == 0) +#define MG118_17PL ~(1 << 6) +#else +#define MG118_17PL 0xFFFF +#endif +#define MG118_18PL 0x007F +#define MG118 (MG118_11PL & MG118_12PL & MG118_13PL & MG118_14PL & \ + MG118_15PL & MG118_16PL & MG118_17PL & MG118_18PL) + +// +// Automatically generate PIEIER1 interrupt masks MG121 to MG128: +// + +// +// Beginning of MG121: +// +#if (G122PL >= G121PL) || (G122PL == 0) +#define MG121_12PL ~(1 << 1) +#else +#define MG121_12PL 0xFFFF +#endif +#if (G123PL >= G121PL) || (G123PL == 0) +#define MG121_13PL ~(1 << 2) +#else +#define MG121_13PL 0xFFFF +#endif +#if (G124PL >= G121PL) || (G124PL == 0) +#define MG121_14PL ~(1 << 3) +#else +#define MG121_14PL 0xFFFF +#endif +#if (G125PL >= G121PL) || (G125PL == 0) +#define MG121_15PL ~(1 << 4) +#else +#define MG121_15PL 0xFFFF +#endif +#if (G126PL >= G121PL) || (G126PL == 0) +#define MG121_16PL ~(1 << 5) +#else +#define MG121_16PL 0xFFFF +#endif +#if (G127PL >= G121PL) || (G127PL == 0) +#define MG121_17PL ~(1 << 6) +#else +#define MG121_17PL 0xFFFF +#endif +#if (G128PL >= G121PL) || (G128PL == 0) +#define MG121_18PL ~(1 << 7) +#else +#define MG121_18PL 0xFFFF +#endif +#define MG121_11PL 0x00FE +#define MG121 (MG121_11PL & MG121_12PL & MG121_13PL & MG121_14PL & \ + MG121_15PL & MG121_16PL & MG121_17PL & MG121_18PL) + +// +// Beginning of MG121: +// +#if (G121PL >= G122PL) || (G121PL == 0) +#define MG122_11PL ~(1) +#else +#define MG122_11PL 0xFFFF +#endif +#if (G123PL >= G122PL) || (G123PL == 0) +#define MG122_13PL ~(1 << 2) +#else +#define MG122_13PL 0xFFFF +#endif +#if (G124PL >= G122PL) || (G124PL == 0) +#define MG122_14PL ~(1 << 3) +#else +#define MG122_14PL 0xFFFF +#endif +#if (G125PL >= G122PL) || (G125PL == 0) +#define MG122_15PL ~(1 << 4) +#else +#define MG122_15PL 0xFFFF +#endif +#if (G126PL >= G122PL) || (G126PL == 0) +#define MG122_16PL ~(1 << 5) +#else +#define MG122_16PL 0xFFFF +#endif +#if (G127PL >= G122PL) || (G127PL == 0) +#define MG122_17PL ~(1 << 6) +#else +#define MG122_17PL 0xFFFF +#endif +#if (G128PL >= G122PL) || (G128PL == 0) +#define MG122_18PL ~(1 << 7) +#else +#define MG122_18PL 0xFFFF +#endif +#define MG122_12PL 0x00FD +#define MG122 (MG122_11PL & MG122_12PL & MG122_13PL & MG122_14PL & \ + MG122_15PL & MG122_16PL & MG122_17PL & MG122_18PL) + +// +// Beginning of MG123: +// +#if (G121PL >= G123PL) || (G121PL == 0) +#define MG123_11PL ~(1) +#else +#define MG123_11PL 0xFFFF +#endif +#if (G122PL >= G123PL) || (G122PL == 0) +#define MG123_12PL ~(1 << 1) +#else +#define MG123_12PL 0xFFFF +#endif +#if (G124PL >= G123PL) || (G124PL == 0) +#define MG123_14PL ~(1 << 3) +#else +#define MG123_14PL 0xFFFF +#endif +#if (G125PL >= G123PL) || (G125PL == 0) +#define MG123_15PL ~(1 << 4) +#else +#define MG123_15PL 0xFFFF +#endif +#if (G126PL >= G123PL) || (G126PL == 0) +#define MG123_16PL ~(1 << 5) +#else +#define MG123_16PL 0xFFFF +#endif +#if (G127PL >= G123PL) || (G127PL == 0) +#define MG123_17PL ~(1 << 6) +#else +#define MG123_17PL 0xFFFF +#endif +#if (G128PL >= G123PL) || (G128PL == 0) +#define MG123_18PL ~(1 << 7) +#else +#define MG123_18PL 0xFFFF +#endif +#define MG123_13PL 0x00FB +#define MG123 (MG123_11PL & MG123_12PL & MG123_13PL & MG123_14PL & \ + MG123_15PL & MG123_16PL & MG123_17PL & MG123_18PL) + +// +// Beginning of MG124: +// +#if (G121PL >= G124PL) || (G121PL == 0) +#define MG124_11PL ~(1) +#else +#define MG124_11PL 0xFFFF +#endif +#if (G122PL >= G124PL) || (G122PL == 0) +#define MG124_12PL ~(1 << 1) +#else +#define MG124_12PL 0xFFFF +#endif +#if (G123PL >= G124PL) || (G123PL == 0) +#define MG124_13PL ~(1 << 2) +#else +#define MG124_13PL 0xFFFF +#endif +#if (G125PL >= G124PL) || (G125PL == 0) +#define MG124_15PL ~(1 << 4) +#else +#define MG124_15PL 0xFFFF +#endif +#if (G126PL >= G124PL) || (G126PL == 0) +#define MG124_16PL ~(1 << 5) +#else +#define MG124_16PL 0xFFFF +#endif +#if (G127PL >= G124PL) || (G127PL == 0) +#define MG124_17PL ~(1 << 6) +#else +#define MG124_17PL 0xFFFF +#endif +#if (G128PL >= G124PL) || (G128PL == 0) +#define MG124_18PL ~(1 << 7) +#else +#define MG124_18PL 0xFFFF +#endif +#define MG124_14PL 0x00F7 +#define MG124 (MG124_11PL & MG124_12PL & MG124_13PL & MG124_14PL & \ + MG124_15PL & MG124_16PL & MG124_17PL & MG124_18PL) + +// +// Beginning of MG125: +// +#if (G121PL >= G125PL) || (G121PL == 0) +#define MG125_11PL ~(1) +#else +#define MG125_11PL 0xFFFF +#endif +#if (G122PL >= G125PL) || (G122PL == 0) +#define MG125_12PL ~(1 << 1) +#else +#define MG125_12PL 0xFFFF +#endif +#if (G123PL >= G125PL) || (G123PL == 0) +#define MG125_13PL ~(1 << 2) +#else +#define MG125_13PL 0xFFFF +#endif +#if (G124PL >= G125PL) || (G124PL == 0) +#define MG125_14PL ~(1 << 3) +#else +#define MG125_14PL 0xFFFF +#endif +#if (G126PL >= G125PL) || (G126PL == 0) +#define MG125_16PL ~(1 << 5) +#else +#define MG125_16PL 0xFFFF +#endif +#if (G127PL >= G125PL) || (G127PL == 0) +#define MG125_17PL ~(1 << 6) +#else +#define MG125_17PL 0xFFFF +#endif +#if (G128PL >= G125PL) || (G128PL == 0) +#define MG125_18PL ~(1 << 7) +#else +#define MG125_18PL 0xFFFF +#endif +#define MG125_15PL 0x00EF +#define MG125 (MG125_11PL & MG125_12PL & MG125_13PL & MG125_14PL & \ + MG125_15PL & MG125_16PL & MG125_17PL & MG125_18PL) + +// +// Beginning of MG126: +// +#if (G121PL >= G126PL) || (G121PL == 0) +#define MG126_11PL ~(1) +#else +#define MG126_11PL 0xFFFF +#endif +#if (G122PL >= G126PL) || (G122PL == 0) +#define MG126_12PL ~(1 << 1) +#else +#define MG126_12PL 0xFFFF +#endif +#if (G123PL >= G126PL) || (G123PL == 0) +#define MG126_13PL ~(1 << 2) +#else +#define MG126_13PL 0xFFFF +#endif +#if (G124PL >= G126PL) || (G124PL == 0) +#define MG126_14PL ~(1 << 3) +#else +#define MG126_14PL 0xFFFF +#endif +#if (G125PL >= G126PL) || (G125PL == 0) +#define MG126_15PL ~(1 << 4) +#else +#define MG126_15PL 0xFFFF +#endif +#if (G127PL >= G126PL) || (G127PL == 0) +#define MG126_17PL ~(1 << 6) +#else +#define MG126_17PL 0xFFFF +#endif +#if (G128PL >= G126PL) || (G128PL == 0) +#define MG126_18PL ~(1 << 7) +#else +#define MG126_18PL 0xFFFF +#endif +#define MG126_16PL 0x00DF +#define MG126 (MG126_11PL & MG126_12PL & MG126_13PL & MG126_14PL & \ + MG126_15PL & MG126_16PL & MG126_17PL & MG126_18PL) + +// +// Beginning of MG127: +// +#if (G121PL >= G127PL) || (G121PL == 0) +#define MG127_11PL ~(1) +#else +#define MG127_11PL 0xFFFF +#endif +#if (G122PL >= G127PL) || (G122PL == 0) +#define MG127_12PL ~(1 << 1) +#else +#define MG127_12PL 0xFFFF +#endif +#if (G123PL >= G127PL) || (G123PL == 0) +#define MG127_13PL ~(1 << 2) +#else +#define MG127_13PL 0xFFFF +#endif +#if (G124PL >= G127PL) || (G124PL == 0) +#define MG127_14PL ~(1 << 3) +#else +#define MG127_14PL 0xFFFF +#endif +#if (G125PL >= G127PL) || (G125PL == 0) +#define MG127_15PL ~(1 << 4) +#else +#define MG127_15PL 0xFFFF +#endif +#if (G126PL >= G127PL) || (G126PL == 0) +#define MG127_16PL ~(1 << 5) +#else +#define MG127_16PL 0xFFFF +#endif +#if (G128PL >= G127PL) || (G128PL == 0) +#define MG127_18PL ~(1 << 7) +#else +#define MG127_18PL 0xFFFF +#endif +#define MG127_17PL 0x00BF +#define MG127 (MG127_11PL & MG127_12PL & MG127_13PL & MG127_14PL & \ + MG127_15PL & MG127_16PL & MG127_17PL & MG127_18PL) + +// +// Beginning of MG128: +// +#if (G121PL >= G128PL) || (G121PL == 0) +#define MG128_11PL ~(1) +#else +#define MG128_11PL 0xFFFF +#endif +#if (G122PL >= G128PL) || (G122PL == 0) +#define MG128_12PL ~(1 << 1) +#else +#define MG128_12PL 0xFFFF +#endif +#if (G123PL >= G128PL) || (G123PL == 0) +#define MG128_13PL ~(1 << 2) +#else +#define MG128_13PL 0xFFFF +#endif +#if (G124PL >= G128PL) || (G124PL == 0) +#define MG128_14PL ~(1 << 3) +#else +#define MG128_14PL 0xFFFF +#endif +#if (G125PL >= G128PL) || (G125PL == 0) +#define MG128_15PL ~(1 << 4) +#else +#define MG128_15PL 0xFFFF +#endif +#if (G126PL >= G128PL) || (G126PL == 0) +#define MG128_16PL ~(1 << 5) +#else +#define MG128_16PL 0xFFFF +#endif +#if (G127PL >= G128PL) || (G127PL == 0) +#define MG128_17PL ~(1 << 6) +#else +#define MG128_17PL 0xFFFF +#endif +#define MG128_18PL 0x007F +#define MG128 (MG128_11PL & MG128_12PL & MG128_13PL & MG128_14PL & \ + MG128_15PL & MG128_16PL & MG128_17PL & MG128_18PL) + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // eof + +// +// End of File +// + diff --git a/f2833x/common/include/DSP28x_Project.h b/f2833x/common/include/DSP28x_Project.h new file mode 100644 index 0000000..a369808 --- /dev/null +++ b/f2833x/common/include/DSP28x_Project.h @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/f2833x/common/source/DSP2833x_ADC_cal.asm b/f2833x/common/source/DSP2833x_ADC_cal.asm new file mode 100644 index 0000000..1082e83 --- /dev/null +++ b/f2833x/common/source/DSP2833x_ADC_cal.asm @@ -0,0 +1,74 @@ +;; TI File $Revision: /main/1 $ +;; Checkin $Date: July 30, 2007 10:29:23 $ +;;########################################################################### +;; +;; FILE: ADC_cal.asm +;; +;; TITLE: 2833x Boot Rom ADC Cal routine. +;; +;; Functions: +;; +;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and +;; ADCOFFTRIM registers +;; Notes: +;; +;;########################################################################### +;; $TI Release: 2833x/2823x Header Files V1.32 $ +;; $Release Date: June 28, 2010 $ +;; $Copyright: +;// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;;########################################################################### + + .def _ADC_cal + .asg "0x711C", ADCREFSEL_LOC + +;----------------------------------------------- +; _ADC_cal +;----------------------------------------------- +;----------------------------------------------- +; This is the ADC cal routine.This routine is programmed into +; reserved memory by the factory. 0xAAAA and 0xBBBB are place- +; holders for calibration data. +;The actual values programmed by TI are device specific. +; +; This function assumes that the clocks have been +; enabled to the ADC module. +;----------------------------------------------- + + .sect ".adc_cal" + +_ADC_cal + MOVW DP, #ADCREFSEL_LOC >> 6 + MOV @28, #0xAAAA ; actual value may not be 0xAAAA + MOV @29, #0xBBBB ; actual value may not be 0xBBBB + LRETR +;eof ---------- diff --git a/f2833x/common/source/DSP2833x_Adc.c b/f2833x/common/source/DSP2833x_Adc.c new file mode 100644 index 0000000..746bd7a --- /dev/null +++ b/f2833x/common/source/DSP2833x_Adc.c @@ -0,0 +1,99 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: October 23, 2007 13:34:09 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.c +// +// TITLE: DSP2833x ADC Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// Defines +// +#define ADC_usDELAY 5000L + +// +// InitAdc - This function initializes ADC to a known state. +// +void +InitAdc(void) +{ + extern void DSP28x_usDelay(Uint32 Count); + + // + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from + // TI reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC to + // function according to specification. The clocks to the ADC MUST be + // enabled before calling this function. See the device data manual and/or + // the ADC Reference Manual for more information. + // + EALLOW; + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; + ADC_cal(); + EDIS; + + // + // To powerup the ADC the ADCENCLK bit should be set first to enable + // clocks, followed by powering up the bandgap, reference circuitry, and + // ADC core. Before the first conversion is performed a 5ms delay must be + // observed after power up to give all analog circuits time to power up + // and settle + // + + // + // Please note that for the delay function below to operate correctly the + // CPU_RATE define statement in the DSP2833x_Examples.h file must + // contain the correct CPU clock period in nanoseconds. + // + AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits + DELAY_US(ADC_usDELAY); // Delay before converting ADC channels +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_CSMPasswords.asm b/f2833x/common/source/DSP2833x_CSMPasswords.asm new file mode 100644 index 0000000..67ab428 --- /dev/null +++ b/f2833x/common/source/DSP2833x_CSMPasswords.asm @@ -0,0 +1,95 @@ +;// TI File $Revision: /main/3 $ +;// Checkin $Date: June 26, 2007 16:41:07 $ +;//########################################################################### +;// +;// FILE: DSP2833x_CSMPasswords.asm +;// +;// TITLE: DSP2833x Code Security Module Passwords. +;// +;// DESCRIPTION: +;// +;// This file is used to specify password values to +;// program into the CSM password locations in Flash +;// at 0x33FFF8 - 0x33FFFF. +;// +;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are +;// all programmed to 0x0000 +;// +;//########################################################################### +;// $TI Release: 2833x/2823x Header Files V1.32 $ +;// $Release Date: June 28, 2010 $ +;// $Copyright: +;// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + +; The "csmpasswords" section contains the actual CSM passwords that will be +; linked and programmed into to the CSM password locations (PWL) in flash. +; These passwords must be known in order to unlock the CSM module. +; All 0xFFFF's (erased) is the default value for the password locations (PWL). + +; It is recommended that all passwords be left as 0xFFFF during code +; development. Passwords of 0xFFFF do not activate code security and dummy +; reads of the CSM PWL registers is all that is required to unlock the CSM. +; When code development is complete, modify the passwords to activate the +; code security module. + + .sect "csmpasswds" + + .int 0xFFFF ;PWL0 (LSW of 128-bit password) + .int 0xFFFF ;PWL1 + .int 0xFFFF ;PWL2 + .int 0xFFFF ;PWL3 + .int 0xFFFF ;PWL4 + .int 0xFFFF ;PWL5 + .int 0xFFFF ;PWL6 + .int 0xFFFF ;PWL7 (MSW of 128-bit password) + +;---------------------------------------------------------------------- + +; For code security operation, all addresses between 0x33FF80 and +; 0X33fff5 cannot be used as program code or data. These locations +; must be programmed to 0x0000 when the code security password locations +; (PWL) are programmed. If security is not a concern, then these addresses +; can be used for code or data. + +; The section "csm_rsvd" can be used to program these locations to 0x0000. + + .sect "csm_rsvd" + .loop (33FFF5h - 33FF80h + 1) + .int 0x0000 + .endloop + +;//=========================================================================== +;// End of file. +;//=========================================================================== + + diff --git a/f2833x/common/source/DSP2833x_CodeStartBranch.asm b/f2833x/common/source/DSP2833x_CodeStartBranch.asm new file mode 100644 index 0000000..9dc0484 --- /dev/null +++ b/f2833x/common/source/DSP2833x_CodeStartBranch.asm @@ -0,0 +1,117 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:45:55 $ +;//########################################################################### +;// +;// FILE: DSP2833x_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example DSP2833x projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// $TI Release: 2833x/2823x Header Files V1.32 $ +;// $Release Date: June 28, 2010 $ +;// $Copyright: +;// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + + +*********************************************************************** + +WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot.asm in RTS library + .endif + +;end codestart section + + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot.asm in RTS library + + .endif + +;end wd_disable + + + + .end + +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/f2833x/common/source/DSP2833x_CpuTimers.c b/f2833x/common/source/DSP2833x_CpuTimers.c new file mode 100644 index 0000000..9224da6 --- /dev/null +++ b/f2833x/common/source/DSP2833x_CpuTimers.c @@ -0,0 +1,199 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 9, 2009 10:51:59 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +// NOTES: CpuTimer2 is reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these this timer in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// Defines +// +struct CPUTIMER_VARS CpuTimer0; + +// +// When using DSP BIOS & other RTOS, comment out CPU Timer 2 code. +// +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +// +// InitCpuTimers - This function initializes all three CPU timers to a known +// state. +// +void +InitCpuTimers(void) +{ + // + // CPU Timer 0 - Initialize address pointers to respective timer registers + // + CpuTimer0.RegsAddr = &CpuTimer0Regs; + + // + // Initialize timer period to maximum + // + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) + // + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + + // + // Make sure timer is stopped + // + CpuTimer0Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value + // + CpuTimer0Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters + // + CpuTimer0.InterruptCount = 0; + + // + // CpuTimer2 is reserved for DSP BIOS & other RTOS + // Do not use this timer if you ever plan on integrating + // DSP-BIOS or another realtime OS. + // + + // + // Initialize address pointers to respective timer registers + // + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + + // + // Initialize timer period to maximum + // + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + + // + // Make sure timers are stopped + // + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value + // + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters + // + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; +} + +// +// ConfigCpuTimer - This function initializes the selected timer to the period +// specified by the "Freq" and "Period" parameters. The "Freq" is entered as +// "MHz" and the period in "uSeconds". The timer is held in the stopped state +// after configuration. +// +void +ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // + // Initialize timer period + // + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + + // + // Counter decrements PRD+1 times each period + // + Timer->RegsAddr->PRD.all = temp - 1; + + // + // Set pre-scale counter to divide by 1 (SYSCLKOUT) + // + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // + // Initialize timer control register + // + + // + // 1 = Stop timer, 0 = Start/Restart Timer + // + Timer->RegsAddr->TCR.bit.TSS = 1; + + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 1; + Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run + + // + // 0 = Disable/ 1 = Enable Timer Interrupt + // + Timer->RegsAddr->TCR.bit.TIE = 1; + + // + // Reset interrupt counter + // + Timer->InterruptCount = 0; +} + +// +// End of File +// + diff --git a/f2833x/common/source/DSP2833x_DBGIER.asm b/f2833x/common/source/DSP2833x_DBGIER.asm new file mode 100644 index 0000000..6b6a391 --- /dev/null +++ b/f2833x/common/source/DSP2833x_DBGIER.asm @@ -0,0 +1,59 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:46:03 $ +;//########################################################################### +;// +;// FILE: DSP2833x_DBGIER.asm +;// +;// TITLE: Set the DBGIER register +;// +;// DESCRIPTION: +;// +;// Function to set the DBGIER register (for realtime emulation). +;// Function Prototype: void SetDBGIER(Uint16) +;// Useage: SetDBGIER(value); +;// Input Parameters: Uint16 value = value to put in DBGIER register. +;// Return Value: none +;// +;//########################################################################### +;// $TI Release: 2833x/2823x Header Files V1.32 $ +;// $Release Date: June 28, 2010 $ +;// $Copyright: +;// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + .global _SetDBGIER + .text + +_SetDBGIER: + MOV *SP++,AL + POP DBGIER + LRETR + diff --git a/f2833x/common/source/DSP2833x_DMA.c b/f2833x/common/source/DSP2833x_DMA.c new file mode 100644 index 0000000..d1645a8 --- /dev/null +++ b/f2833x/common/source/DSP2833x_DMA.c @@ -0,0 +1,1316 @@ +//########################################################################### +// +// FILE: DSP2833x_DMA.c +// +// TITLE: DSP2833x Device DMA Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// DMAInitialize - This function initializes the DMA to a known state. +// +void +DMAInitialize(void) +{ + EALLOW; + + // + // Perform a hard reset on DMA + // + DmaRegs.DMACTRL.bit.HARDRESET = 1; + asm (" nop"); // one NOP required after HARDRESET + + // + // Allow DMA to run free on emulation suspend + // + DmaRegs.DEBUGCTRL.bit.FREE = 1; + + EDIS; +} + +// +// DMACH1AddrConfig - +// +void +DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH1BurstConfig - +// +void +DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH1.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH1.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH1.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH1TransferConfig - +// +void +DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after + // completed transfer + // + DmaRegs.CH1.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH1.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH1WrapConfig - +// +void +DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 + deswstep) +{ + EALLOW; + + // + // Set up WRAP registers + // + DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH1.DST_WRAP_SIZE = deswsize; + + DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH1ModeConfig - +// +void +DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH1.MODE.bit.PERINTSEL = persel; + + DmaRegs.CH1.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH1.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH1.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH1.MODE.bit.DATASIZE = datasize; // 16/32-bit data size transfers + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH1.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;// Clear any spurious interrupt flags + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE + + EDIS; +} + +// +// StartDMACH1 - This function starts DMA Channel 1. +// +void +StartDMACH1(void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH2AddrConfig - +// +void +DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2BurstConfig - +// +void +DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH2.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH2.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH2.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH2TransferConfig - +// +void +DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur + // after completed transfer + // + DmaRegs.CH2.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH2.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH2WrapConfig - +// +void +DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + + // + // Wrap source address after N bursts + // + DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; + + // + // Step for source wrap + // + DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; + + // + // Wrap destination address after N bursts + // + DmaRegs.CH2.DST_WRAP_SIZE = deswsize; + + // + // Step for destination wrap + // + DmaRegs.CH2.DST_WRAP_STEP = deswstep; + + EDIS; +} + +// +// DMACH2ModeConfig - +// +void +DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH2.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH2.MODE.bit.PERINTE = perinte; + + // + // Oneshot enable + // + DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; + + // + // Continous enable + // + DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; + + // + // Peripheral sync enable/disable + // + DmaRegs.CH2.MODE.bit.SYNCE = synce; + + // + // Sync effects source or destination + // + DmaRegs.CH2.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH2.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH2.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; + + // + // Clear any spurious sync flags + // + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; + + // + // Clear any spurious sync error flags + // + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt + // + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable DMA CH2 interrupt in PIE + + EDIS; +} + +// +// StartDMACH2 - This function starts DMA Channel 2. +// +void +StartDMACH2(void) +{ + EALLOW; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH3AddrConfig - +// +void +DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3BurstConfig - +// +void +DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH3.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH3.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH3.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH3TransferConfig - +// +void +DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after + // completed transfer + // + DmaRegs.CH3.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH3.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH3WrapConfig - +// +void +DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH3.DST_WRAP_SIZE = deswsize; + + // + // Step for destination wrap + // + DmaRegs.CH3.DST_WRAP_STEP = deswstep; + + EDIS; +} + +// +// DMACH3ModeConfig - +// +void +DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH3.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH3.MODE.bit.PERINTE = perinte; + + DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH3.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + + // + // Sync effects source or destination + // + DmaRegs.CH3.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH3.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH3.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; + + DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + + // + // Clear any spurious sync error flags + // + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx3 = 1; // Enable DMA CH3 interrupt in PIE + + EDIS; +} + +// +// StartDMACH3 - This function starts DMA Channel 3. +// +void +StartDMACH3(void) +{ + EALLOW; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH4AddrConfig - +// +void +DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4BurstConfig - +// +void +DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH4.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH4.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH4.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH4TransferConfig - +// +void +DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after completed + // transfer + // + DmaRegs.CH4.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH4.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH4WrapConfig - +// +void +DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize;// Wrap source address after N bursts + DmaRegs.CH4.SRC_WRAP_STEP = srcwstep;// Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH4.DST_WRAP_SIZE = deswsize; + + DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH4ModeConfig - +// +void +DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH4.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH4.MODE.bit.PERINTE = perinte; + + DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH4.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + + // + // Sync effects source or destination + // + DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH4.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH4.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; + + DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + + // + // Clear any spurious sync error flags + // + DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx4 = 1; // Enable DMA CH4 interrupt in PIE + + EDIS; +} + +// +// StartDMACH4 - This function starts DMA Channel 4. +// +void +StartDMACH4(void) +{ + EALLOW; + DmaRegs.CH4.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH5AddrConfig - +// +void +DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5BurstConfig - +// +void +DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH5.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH5.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH5.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH5TransferConfig - +// +void +DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after completed + // transfer + // + DmaRegs.CH5.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH5.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH5WrapConfig - +// +void +DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize;// Wrap source address after N bursts + DmaRegs.CH5.SRC_WRAP_STEP = srcwstep;// Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH5.DST_WRAP_SIZE = deswsize; + + DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH5ModeConfig - +// +void +DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH5.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH5.MODE.bit.PERINTE = perinte; + + DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH5.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + + // + // Sync effects source or destination + // + DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH5.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH5.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; + + DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + + // + // Clear any spurious sync error flags + // + DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable DMA CH5 interrupt in PIE + + EDIS; +} + +// +// StartDMACH5 - This function starts DMA Channel 5. +// +void +StartDMACH5(void) +{ + EALLOW; + DmaRegs.CH5.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH6AddrConfig - +// +void +DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6BurstConfig - +// +void +DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH6.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH6.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH6.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH6TransferConfig - +// +void +DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after completed + // transfer + // + DmaRegs.CH6.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH6.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH6WrapConfig - +// +void +DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize;// Wrap source address after N bursts + DmaRegs.CH6.SRC_WRAP_STEP = srcwstep;// Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH6.DST_WRAP_SIZE = deswsize; + + DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH6ModeConfig - +// +void +DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH6.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH6.MODE.bit.PERINTE = perinte; + + DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH6.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + + // + // Sync effects source or destination + // + DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH6.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH6.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; + + DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + + // + // Clear any spurious sync error flags + // + DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable DMA CH6 interrupt in PIE + + EDIS; +} + +// +// StartDMACH6 - This function starts DMA Channel 6. +// +void +StartDMACH6(void) +{ + EALLOW; + DmaRegs.CH6.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// End of File +// + diff --git a/f2833x/common/source/DSP2833x_DefaultIsr.c b/f2833x/common/source/DSP2833x_DefaultIsr.c new file mode 100644 index 0000000..3a04b4b --- /dev/null +++ b/f2833x/common/source/DSP2833x_DefaultIsr.c @@ -0,0 +1,2024 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: January 14, 2008 11:17:46 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.c +// +// TITLE: DSP2833x Device Default Interrupt Service Routines. +// +// This file contains shell ISR routines for the 2833x PIE vector table. +// Typically these shell ISR routines can be used to populate the entire PIE +// vector table during device debug. In this manner if an interrupt is taken +// during firmware development, there will always be an ISR to catch it. +// +// As development progresses, these ISR routines can be eliminated and replaced +// with the user's own ISR routines for each interrupt. Since these shell ISRs +// include infinite loops they will typically not be included as-is in the final +// production firmware. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// INT13_ISR - Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +// +interrupt void +INT13_ISR(void) // INT13 or CPU-Timer1 +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT14_ISR - Note CPU-Timer2 is reserved for TI use. +// +interrupt void +INT14_ISR(void) // CPU-Timer2 +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DATALOG_ISR - Datalogging interrupt +// +interrupt void +DATALOG_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// RTOSINT_ISR - RTOS interrupt +// +interrupt void +RTOSINT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EMUINT_ISR - Emulation interrupt +// +interrupt void +EMUINT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// NMI_ISR - Non-maskable interrupt +// +interrupt void +NMI_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ILLEGAL_ISR - Illegal operation TRAP +// +interrupt void +ILLEGAL_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER1_ISR - User Defined trap 1 +// +interrupt void +USER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER2_ISR - User Defined trap 2 +// +interrupt void +USER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER3_ISR - User Defined trap 3 +// +interrupt void +USER3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER4_ISR - User Defined trap 4 +// +interrupt void +USER4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER5_ISR - User Defined trap 5 +// +interrupt void +USER5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER6_ISR - User Defined trap 6 +// +interrupt void +USER6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER7_ISR - User Defined trap 7 +// +interrupt void +USER7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER8_ISR - User Defined trap 8 +// +interrupt void +USER8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER9_ISR - User Defined trap 9 +// +interrupt void +USER9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER10_ISR - User Defined trap 10 +// +interrupt void +USER10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER11_ISR - User Defined trap 11 +// +interrupt void +USER11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER12_ISR - User Defined trap 12 +// +interrupt void +USER12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 1 - MUXed into CPU INT1 +// + +// +// SEQ1INT_ISR - INT1.1 +// +interrupt void +SEQ1INT_ISR(void) //SEQ1 ADC +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SEQ2INT_ISR - INT1.2 +// +interrupt void +SEQ2INT_ISR(void) //SEQ2 ADC +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + + asm(" ESTOP0"); + for(;;); +} + +// +// INT1.3 - Reserved +// + +// +// XINT1_ISR - INT1.4 +// +interrupt void +XINT1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT2_ISR - INT1.5 +// +interrupt void +XINT2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ADCINT_ISR - INT1.6 +// +interrupt void +ADCINT_ISR(void) // ADC +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// TINT0_ISR - INT1.7 +// +interrupt void +TINT0_ISR(void) // CPU-Timer 0 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// WAKEINT_ISR - INT1.8 +// +interrupt void +WAKEINT_ISR(void) // WD, LOW Power +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 2 - MUXed into CPU INT2 +// + +// +// EPWM1_TZINT_ISR - INT2.1 +// +interrupt void +EPWM1_TZINT_ISR(void) // EPWM-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM2_TZINT_ISR - INT2.2 +// +interrupt void +EPWM2_TZINT_ISR(void) // EPWM-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM3_TZINT_ISR - INT2.3 +// +interrupt void +EPWM3_TZINT_ISR(void) // EPWM-3 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge + // this interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM4_TZINT_ISR - INT2.4 +// +interrupt void +EPWM4_TZINT_ISR(void) // EPWM-4 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM5_TZINT_ISR - INT2.5 +// +interrupt void +EPWM5_TZINT_ISR(void) // EPWM-5 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM6_TZINT_ISR - INT2.6 +// +interrupt void +EPWM6_TZINT_ISR(void) // EPWM-6 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT2.7 - Reserved +// + +// +// INT2.8 - Reserved +// + +// +// PIE Group 3 - MUXed into CPU INT3 +// + +// +// EPWM1_INT_ISR - INT 3.1 +// +interrupt void +EPWM1_INT_ISR(void) // EPWM-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM2_INT_ISR - INT3.2 +// +interrupt void +EPWM2_INT_ISR(void) // EPWM-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM3_INT_ISR - INT3.3 +// +interrupt void +EPWM3_INT_ISR(void) // EPWM-3 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM4_INT_ISR - INT3.4 +// +interrupt void +EPWM4_INT_ISR(void) // EPWM-4 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM5_INT_ISR - INT3.5 +// +interrupt void +EPWM5_INT_ISR(void) // EPWM-5 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM6_INT_ISR - INT3.6 +// +interrupt void +EPWM6_INT_ISR(void) // EPWM-6 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT3.7 - Reserved +// + +// +// INT3.8 - Reserved +// + +// +// PIE Group 4 - MUXed into CPU INT4 +// + +// +// ECAP1_INT_ISR - INT 4.1 +// +interrupt void +ECAP1_INT_ISR(void) // ECAP-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP2_INT_ISR - INT4.2 +// +interrupt void +ECAP2_INT_ISR(void) // ECAP-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP3_INT_ISR - INT4.3 +// +interrupt void +ECAP3_INT_ISR(void) // ECAP-3 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP4_INT_ISR - INT4.4 +// +interrupt void +ECAP4_INT_ISR(void) // ECAP-4 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP5_INT_ISR - INT4.5 +// +interrupt void +ECAP5_INT_ISR(void) // ECAP-5 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP6_INT_ISR - INT4.6 +// +interrupt void +ECAP6_INT_ISR(void) // ECAP-6 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT4.7 - Reserved +// + +// +// INT4.8 - Reserved +// + +// +// PIE Group 5 - MUXed into CPU INT5 +// + +// +// EQEP1_INT_ISR - INT 5.1 +// +interrupt void +EQEP1_INT_ISR(void) // EQEP-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EQEP2_INT_ISR - INT5.2 +// +interrupt void +EQEP2_INT_ISR(void) // EQEP-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT5.3 - Reserved +// + +// +// INT5.4 - Reserved +// + +// +// INT5.5 - Reserved +// + +// +// INT5.6 - Reserved +// + +// +// INT5.7 - Reserved +// + +// +// INT5.8 - Reserved +// + +// +// PIE Group 6 - MUXed into CPU INT6 +// + +// +// SPIRXINTA_ISR - INT6.1 +// +interrupt void +SPIRXINTA_ISR(void) // SPI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SPITXINTA_ISR - INT6.2 +// +interrupt void +SPITXINTA_ISR(void) // SPI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MRINTB_ISR - INT6.3 +// +interrupt void +MRINTB_ISR(void) // McBSP-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MXINTB_ISR - INT6.4 +// +interrupt void +MXINTB_ISR(void) // McBSP-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MRINTA_ISR - INT6.5 +// +interrupt void +MRINTA_ISR(void) // McBSP-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MXINTA_ISR - INT6.6 +// +interrupt void +MXINTA_ISR(void) // McBSP-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT6.7 - Reserved +// + +// +// INT6.8 - Reserved +// + +// +// PIE Group 7 - MUXed into CPU INT7 +// + +// +// DINTCH1_ISR - INT7.1 +// +interrupt void +DINTCH1_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH2_ISR - INT7.2 +// +interrupt void +DINTCH2_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH3_ISR - INT7.3 +// +interrupt void +DINTCH3_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH4_ISR - INT7.4 +// +interrupt void +DINTCH4_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH5_ISR - INT7.5 +// +interrupt void +DINTCH5_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH6_ISR - INT7.6 +// +interrupt void +DINTCH6_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT7.7 - Reserved +// + +// +// INT7.8 - Reserved +// + +// +// PIE Group 8 - MUXed into CPU INT8 +// + +// +// I2CINT1A_ISR - INT8.1 +// +interrupt void +I2CINT1A_ISR(void) // I2C-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// I2CINT2A_ISR - INT8.2 +// +interrupt void +I2CINT2A_ISR(void) // I2C-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT8.3 - Reserved +// + +// +// INT8.4 - Reserved +// + +// +// SCIRXINTC_ISR - INT8.5 +// +interrupt void +SCIRXINTC_ISR(void) // SCI-C +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCITXINTC_ISR - INT8.6 +// +interrupt void +SCITXINTC_ISR(void) // SCI-C +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT8.7 - Reserved +// + +// +// INT8.8 - Reserved +// + +// +// PIE Group 9 - MUXed into CPU INT9 +// + +// +// SCIRXINTA_ISR - INT9.1 +// +interrupt void +SCIRXINTA_ISR(void) // SCI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCITXINTA_ISR - INT9.2 +// +interrupt void +SCITXINTA_ISR(void) // SCI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCIRXINTB_ISR - INT9.3 +// +interrupt void +SCIRXINTB_ISR(void) // SCI-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCITXINTB_ISR - INT9.4 +// +interrupt void +SCITXINTB_ISR(void) // SCI-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN0INTA_ISR - INT9.5 +// +interrupt void +ECAN0INTA_ISR(void) // eCAN-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN1INTA_ISR - INT9.6 +// +interrupt void +ECAN1INTA_ISR(void) // eCAN-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN0INTB_ISR - INT9.7 +// +interrupt void +ECAN0INTB_ISR(void) // eCAN-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN1INTB_ISR - INT9.8 +// +interrupt void +ECAN1INTB_ISR(void) // eCAN-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 10 - MUXed into CPU INT10 +// + +// +// INT10.1 - Reserved +// + +// +// INT10.2 - Reserved +// + +// +// INT10.3 - Reserved +// + +// +// INT10.4 - Reserved +// + +// +// INT10.5 - Reserved +// + +// +// INT10.6 - Reserved +// + +// +// INT10.7 - Reserved +// + +// +// INT10.8 - Reserved +// + +// +// PIE Group 11 - MUXed into CPU INT11 +// + +// +// INT11.1 - Reserved +// + +// +// INT11.2 - Reserved +// + +// +// INT11.3 - Reserved +// + +// +// INT11.4 - Reserved +// + +// +// INT11.5 - Reserved +// + +// +// INT11.6 - Reserved +// + +// +// INT11.7 - Reserved +// + +// +// INT11.8 - Reserved +// + +// +// PIE Group 12 - MUXed into CPU INT12 +// + +// +// XINT3_ISR - INT12.1 +// +interrupt void +XINT3_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT4_ISR - INT12.2 +// +interrupt void +XINT4_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT5_ISR - INT12.3 +// +interrupt void +XINT5_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT6_ISR - INT12.4 +// +interrupt void +XINT6_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT7_ISR - INT12.5 +// +interrupt void +XINT7_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT12.6 - Reserved +// + +// +// LVF_ISR - INT12.7 +// +interrupt void +LVF_ISR(void) // Latched overflow +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// LUF_ISR - INT12.8 +// +interrupt void +LUF_ISR(void) // Latched underflow +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Catch All Default ISRs: +// + +// +// PIE_RESERVED - Reserved space. For test. +// +interrupt void +PIE_RESERVED(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// rsvd_ISR - For test +// +interrupt void +rsvd_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_DisInt.asm b/f2833x/common/source/DSP2833x_DisInt.asm new file mode 100644 index 0000000..4bcb833 --- /dev/null +++ b/f2833x/common/source/DSP2833x_DisInt.asm @@ -0,0 +1,96 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:46:09 $ +;//########################################################################### +;// +;// FILE: DSP2833x_DisInt.asm +;// +;// TITLE: Disable and Restore INTM and DBGM +;// +;// Function Prototypes: +;// +;// Uint16 DSP28x_DisableInt(); +;// and void DSP28x_RestoreInt(Uint16 Stat0); +;// +;// Usage: +;// +;// DSP28x_DisableInt() sets both the INTM and DBGM +;// bits to disable maskable interrupts. Before doing +;// this, the current value of ST1 is stored on the stack +;// so that the values can be restored later. The value +;// of ST1 before the masks are set is returned to the +;// user in AL. This is then used to restore their state +;// via the DSP28x_RestoreInt(Uint16 ST1) function. +;// +;// Example +;// +;// Uint16 StatusReg1 +;// StatusReg1 = DSP28x_DisableInt(); +;// +;// ... May also want to disable INTM here +;// +;// ... code here +;// +;// DSP28x_RestoreInt(StatusReg1); +;// +;// ... Restore INTM enable +;// +;//########################################################################### +;// $TI Release: 2833x/2823x Header Files V1.32 $ +;// $Release Date: June 28, 2010 $ +;// $Copyright: +;// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + + + + + .def _DSP28x_DisableInt + .def _DSP28x_RestoreInt + + +_DSP28x_DisableInt: + PUSH ST1 + SETC INTM,DBGM + MOV AL, *--SP + LRETR + +_DSP28x_RestoreInt: + MOV *SP++, AL + POP ST1 + LRETR + + +;//=========================================================================== +;// End of file. +;//=========================================================================== + + diff --git a/f2833x/common/source/DSP2833x_ECan.c b/f2833x/common/source/DSP2833x_ECan.c new file mode 100644 index 0000000..94efdb9 --- /dev/null +++ b/f2833x/common/source/DSP2833x_ECan.c @@ -0,0 +1,495 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: June 25, 2008 15:19:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.c +// +// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitECan - This function initializes the eCAN module to a known state. +// +void +InitECan(void) +{ + InitECana(); +#if DSP28_ECANB + InitECanb(); +#endif // if DSP28_ECANB +} + +// +// InitECana - Initialize eCAN-A module +// +void +InitECana(void) +{ + // + // Create a shadow register structure for the CAN control registers. This + // is needed, since only 32-bit access is allowed to these registers. + // 16-bit access to these registers could potentially corrupt the register + // contents or return false data. This is especially true while writing + // to/reading from a bit (or group of bits) among bits 16 - 31 + // + struct ECAN_REGS ECanaShadow; + + EALLOW; // EALLOW enables access to protected bits + + // + // Configure eCAN RX and TX pins for CAN operation using eCAN regs + // + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + // + // Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) + // HECC mode also enables time-stamping feature + // + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // + // Initialize all bits of 'Master Control Field' to zero + // Some bits of MSGCTRL register come up in an unknown state. For proper + // operation, all bits (including reserved bits) of MSGCTRL must be + // initialized to zero + // + ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000; + + // + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + // + ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits + + ECanaRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits + + ECanaRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits + ECanaRegs.CANGIF1.all = 0xFFFFFFFF; + + // + // Configure bit timing parameters for eCANA + // + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set + + ECanaShadow.CANBTC.all = 0; + + // + // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h + // + #if (CPU_FRQ_150MHZ) + // + // The following block for all 150 MHz SYSCLKOUT + // (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at End of File + // + ECanaShadow.CANBTC.bit.BRPREG = 4; + ECanaShadow.CANBTC.bit.TSEG2REG = 2; + ECanaShadow.CANBTC.bit.TSEG1REG = 10; + #endif + + // + // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h + // + #if (CPU_FRQ_100MHZ) + // + // The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). + // Bit rate = 1 Mbps See Note at End of File + // + ECanaShadow.CANBTC.bit.BRPREG = 4; + ECanaShadow.CANBTC.bit.TSEG2REG = 1; + ECanaShadow.CANBTC.bit.TSEG1REG = 6; + #endif + + ECanaShadow.CANBTC.bit.SAM = 1; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared + + // + // Disable all Mailboxes + // + ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs + + EDIS; +} + +#if (DSP28_ECANB) +// +// Initialize eCAN-B module +// +void +InitECanb(void) +{ + // + // Create a shadow register structure for the CAN control registers. This + // is needed, since only 32-bit access is allowed to these registers. + // 16-bit access to these registers could potentially corrupt the register + // contents or return false data. This is especially true while writing + // to/reading from a bit (or group of bits) among bits 16 - 31 + // + struct ECAN_REGS ECanbShadow; + + EALLOW; // EALLOW enables access to protected bits + + // + // Configure eCAN RX and TX pins for CAN operation using eCAN regs + // + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + // + // Configure eCAN for HECC mode - (read to access mailboxes 16 thru 31) + // + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // + // Initialize all bits of 'Master Control Field' to zero + // Some bits of MSGCTRL register come up in an unknown state. For proper + // operation, all bits (including reserved bits) of MSGCTRL must be + // initialized to zero + // + ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000; + + // + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + // + ECanbRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits + + ECanbRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits + + ECanbRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits + ECanbRegs.CANGIF1.all = 0xFFFFFFFF; + + // + // Configure bit timing parameters for eCANB + // + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1); // Wait for CCE bit to be cleared + + ECanbShadow.CANBTC.all = 0; + + // + // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h + // + #if (CPU_FRQ_150MHZ) + // + // The following block for all 150 MHz SYSCLKOUT + // (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at end of file + // + ECanbShadow.CANBTC.bit.BRPREG = 4; + ECanbShadow.CANBTC.bit.TSEG2REG = 2; + ECanbShadow.CANBTC.bit.TSEG1REG = 10; + #endif + + // + // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h + // + #if (CPU_FRQ_100MHZ) + // + // The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). + // Bit rate = 1 Mbps See Note at end of file + // + ECanbShadow.CANBTC.bit.BRPREG = 4; + ECanbShadow.CANBTC.bit.TSEG2REG = 1; + ECanbShadow.CANBTC.bit.TSEG1REG = 6; + #endif + + ECanbShadow.CANBTC.bit.SAM = 1; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared + + // + // Disable all Mailboxes + // + ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs + + EDIS; +} +#endif // if DSP28_ECANB + +// +// InitECanGpio - This function initializes GPIO pins to function as eCAN pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for CANTXA/B operation. +// Only one GPIO pin shoudl be enabled for CANRXA/B operation. +// Comment out other unwanted lines. +// +void +InitECanGpio(void) +{ + InitECanaGpio(); +#if (DSP28_ECANB) + InitECanbGpio(); +#endif // if DSP28_ECANB +} + +// +// InitECanaGpio - This function initializes GPIO pins to function as eCAN- A +// +void +InitECanaGpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected CAN pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA) + //GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA) + + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; //Enable pull-up for GPIO31 (CANTXA) + //GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up for GPIO19 (CANTXA) + + // + // Set qualification for selected CAN pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA) + + // + // Configure eCAN-A pins using GPIO regs + // This specifies which of the possible GPIO pins will be eCAN functional + // pins. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA + //GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA + //GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA + + EDIS; +} + +#if (DSP28_ECANB) +// +// InitECanbGpio - This function initializes GPIO pins to function as eCAN-B +// +void +InitECanbGpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected CAN pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; //Enable pull-up for GPIO8 (CANTXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; //Enable pull-up for GPIO12(CANTXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; //Enable pull-up for GPIO16(CANTXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; //Enable pull-up for GPIO20(CANTXB) + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10(CANRXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13(CANRXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17(CANRXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21(CANRXB) + + // + // Set qualification for selected CAN pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB) + + // + // Configure eCAN-B pins using GPIO regs + // This specifies which of the possible GPIO pins will be eCAN functional + // pins. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB + //GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB + //GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB + //GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB + //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB + //GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB + //GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB + + EDIS; +} +#endif // if DSP28_ECANB + +// +// Note: Bit timing parameters must be chosen based on the network parameters +// such as the sampling point desired and the propagation delay of the network. +// The propagation delay is a function of length of the cable, delay introduced +// by the transceivers and opto/galvanic-isolators (if any). +// +// The parameters used in this file must be changed taking into account the +// above mentioned factors in order to arrive at the bit-timing parameters +// suitable for a network. +// + +// +// End of File +// + diff --git a/f2833x/common/source/DSP2833x_ECap.c b/f2833x/common/source/DSP2833x_ECap.c new file mode 100644 index 0000000..f8349dc --- /dev/null +++ b/f2833x/common/source/DSP2833x_ECap.c @@ -0,0 +1,304 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 15, 2007 16:54:36 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.c +// +// TITLE: DSP2833x eCAP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitECap - This function initializes the eCAP(s) to a known state. +// +void +InitECap(void) +{ + // + // Initialize eCAP1/2/3 + // +} + +// +// InitECapGpio - This function initializes GPIO pins to function as ECAP pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each eCAP peripheral +// Only one GPIO pin should be enabled for ECAP operation. +// Comment out other unwanted lines. +// +void +InitECapGpio() +{ + InitECap1Gpio(); +#if (DSP28_ECAP2) + InitECap2Gpio(); +#endif // endif DSP28_ECAP2 +#if (DSP28_ECAP3) + InitECap3Gpio(); +#endif // endif DSP28_ECAP3 +#if (DSP28_ECAP4) + InitECap4Gpio(); +#endif // endif DSP28_ECAP4 +#if (DSP28_ECAP5) + InitECap5Gpio(); +#endif // endif DSP28_ECAP5 +#if (DSP28_ECAP6) + InitECap6Gpio(); +#endif // endif DSP28_ECAP6 +} + +// +// InitECap1Gpio - +// +void +InitECap1Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (CAP1) + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1) + //GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO34 (CAP1) + + // + // Inputs are synchronized to SYSCLKOUT by default. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0; //Synch to SYSCLKOUT GPIO5 (CAP1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; //Synch to SYSCLKOUT GPIO24 (CAP1) + //GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; //Synch to SYSCLKOUT GPIO34 (CAP1) + + // + // Configure eCAP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be eCAP1 functional pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Configure GPIO5 as CAP1 + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1 + //GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1; // Configure GPIO24 as CAP1 + + EDIS; +} + +#if DSP28_ECAP2 +// +// InitECap2Gpio - +// +void +InitECap2Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (CAP2) + //GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (CAP2) + //GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pull-up on GPIO37 (CAP2) + + // + // Inputs are synchronized to SYSCLKOUT by default. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; //Synch to SYSCLKOUT GPIO7 (CAP2) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; //Synch to SYSCLKOUT GPIO25 (CAP2) + //GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; //Synch to SYSCLKOUT GPIO37 (CAP2) + + // + // Configure eCAP-2 pins using GPIO regs + // This specifies which of the possible GPIO pins will be eCAP2 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // Configure GPIO7 as CAP2 + //GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as CAP2 + //GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // Configure GPIO37 as CAP2 + + EDIS; +} +#endif // endif DSP28_ECAP2 + +#if DSP28_ECAP3 +// +// InitECap3Gpio - +// +void +InitECap3Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (CAP3) +// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (CAP3) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Synch to SYSCLKOUT GPIO9 (CAP3) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Synch to SYSCLKOUT GPIO26 (CAP3) + +/* Configure eCAP-3 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP3 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3; // Configure GPIO9 as CAP3 +// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as CAP3 + + EDIS; +} +#endif // endif DSP28_ECAP3 + + +#if DSP28_ECAP4 +void InitECap4Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (CAP4) +// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (CAP4) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4) + +/* Configure eCAP-4 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP4 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as CAP4 +// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO27 as CAP4 + + EDIS; +} +#endif // endif DSP28_ECAP4 + + +#if DSP28_ECAP5 +void InitECap5Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (CAP5) +// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (CAP5) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Synch to SYSCLKOUT GPIO3 (CAP5) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5) + +/* Configure eCAP-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP5 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as CAP5 +// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1; // Configure GPIO48 as CAP5 + + EDIS; +} +#endif // endif DSP28_ECAP5 + + +#if DSP28_ECAP6 +void InitECap6Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (CAP6) +// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (CAP6) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Synch to SYSCLKOUT GPIO1 (CAP6) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6) + +/* Configure eCAP-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP6 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; // Configure GPIO1 as CAP6 +// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1; // Configure GPIO49 as CAP6 + + EDIS; +} +#endif // endif DSP28_ECAP6 + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/f2833x/common/source/DSP2833x_EPwm.c b/f2833x/common/source/DSP2833x_EPwm.c new file mode 100644 index 0000000..934e54a --- /dev/null +++ b/f2833x/common/source/DSP2833x_EPwm.c @@ -0,0 +1,407 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:19 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.c +// +// TITLE: DSP2833x ePWM Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitEPwm - This function initializes the ePWM(s) to a known state. +// +void +InitEPwm(void) +{ + // + // Initialize ePWM1/2/3/4/5/6 + // +} + +// +// InitEPwmGpio - This function initializes GPIO pins to function as ePWM pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +void +InitEPwmGpio(void) +{ + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); +#if DSP28_EPWM4 + InitEPwm4Gpio(); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 + InitEPwm5Gpio(); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 + InitEPwm6Gpio(); +#endif // endif DSP28_EPWM6 +} + +// +// InitEPwm1Gpio - This function initializes GPIO pins to function as ePWM1 +// +void +InitEPwm1Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B) + + // + // Configure ePWM-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM1 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B + + EDIS; +} + +// +// InitEPwm2Gpio - This function initializes GPIO pins to function as ePWM2 +// +void +InitEPwm2Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pull-up on GPIO2 (EPWM2A) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (EPWM3B) + + // + // Configure ePWM-2 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM2 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B + + EDIS; +} + +// +// InitEPwm3Gpio - This function initializes GPIO pins to function as ePWM3 +// +void +InitEPwm3Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pull-up on GPIO4 (EPWM3A) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (EPWM3B) + + // + // Configure ePWM-3 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM3 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B + + EDIS; +} + +#if DSP28_EPWM4 +// +// InitEPwm4Gpio - This function initializes GPIO pins to function as ePWM4 +// +void +InitEPwm4Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (EPWM4B) + + // + // Configure ePWM-4 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM4 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B + + EDIS; +} +#endif // endif DSP28_EPWM4 + +#if DSP28_EPWM5 +// +// InitEPwm5Gpio - This function initializes GPIO pins to function as ePWM5 +// +void +InitEPwm5Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A) + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (EPWM5B) + + // + // Configure ePWM-5 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM5 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B + + EDIS; +} +#endif // endif DSP28_EPWM5 + +#if DSP28_EPWM6 +// +// InitEPwm6Gpio - This function initializes GPIO pins to function as ePWM6 +// +void +InitEPwm6Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up on GPIO10 (EPWM6A) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (EPWM6B) + + // + // Configure ePWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM6 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B + + EDIS; +} +#endif // endif DSP28_EPWM6 + +// +// InitEPwmSyncGpio - This function initializes GPIO pins to function as ePWM +// Synch pins +// +void +InitEPwmSyncGpio(void) +{ + EALLOW; + + // + // Configure EPWMSYNCI + // + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; //Enable pull-up on GPIO6 (EPWMSYNCI) + //GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;//Enable pull-up on GPIO32 (EPWMSYNCI) + + // + // Set qualification for selected pins to asynch only + // This will select synch to SYSCLKOUT for the selected pins. + // Comment out other unwanted lines. + // + + // + // Synch to SYSCLKOUT GPIO6 (EPWMSYNCI) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; + + // + //Synch to SYSCLKOUT GPIO32 (EPWMSYNCI) + // + //GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0; + + // + // Configure EPwmSync pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPwmSync + // functional pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2; //Enable pull-up on GPIO6(EPWMSYNCI) + //GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2;//Enable pull-up on GPIO32(EPWMSYNCI) + + // + // Configure EPWMSYNC0 + // + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + + // + // Enable pull-up on GPIO6 (EPWMSYNC0) + // + //GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; + + // + // Enable pull-up on GPIO33 (EPWMSYNC0) + // + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; + + // + // Enable pull-up on GPIO6 (EPWMSYNC0) + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3; + + // + // Enable pull-up on GPIO33 (EPWMSYNC0) + // + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2; +} + +// +// InitTzGpio - This function initializes GPIO pins to function as Trip Zone +// (TZ) pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +void +InitTzGpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (TZ3) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ4) + + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (TZ5) + //GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up on GPIO28 (TZ5) + + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ6) + //GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up on GPIO29 (TZ6) + + // + // Set qualification for selected pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1) + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2) + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (TZ3) + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ4) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ5) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (TZ5) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ6) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3; // Asynch input GPIO29 (TZ6) + + // + // Configure TZ pins using GPIO regs + // This specifies which of the possible GPIO pins will be TZ functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1 + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as TZ2 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as TZ3 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as TZ4 + + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ5 + //GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // Configure GPIO28 as TZ5 + + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as TZ6 + //GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // Configure GPIO29 as TZ6 + + EDIS; +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_EQep.c b/f2833x/common/source/DSP2833x_EQep.c new file mode 100644 index 0000000..c245f8e --- /dev/null +++ b/f2833x/common/source/DSP2833x_EQep.c @@ -0,0 +1,191 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: July 27, 2007 11:55:20 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.c +// +// TITLE: DSP2833x eQEP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitEQep - This function initializes the eQEP(s) to a known state. +// +void +InitEQep(void) +{ + // + // Initialize eQEP1/2 + // +} + +// +// InitEQepGpio - This function initializes GPIO pins to function as eQEP pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. +// +void +InitEQepGpio() +{ +#if DSP28_EQEP1 + InitEQep1Gpio(); +#endif // endif DSP28_EQEP1 +#if DSP28_EQEP2 + InitEQep2Gpio(); +#endif // endif DSP28_EQEP2 +} + +// +// InitEQep1Gpio - This function initializes GPIO pins to function as eQEP1 +// +#if DSP28_EQEP1 +void +InitEQep1Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (EQEP1I) + //GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (EQEP1A) + //GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (EQEP1B) + //GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0; // Enable pull-up on GPIO52 (EQEP1S) + //GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0; // Enable pull-up on GPIO53 (EQEP1I) + + // + // Inputs are synchronized to SYSCLKOUT by default. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync to SYSCLKOUT GPIO23 (EQEP1I) + + //GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; //Sync to SYSCLKOUT GPIO50(EQEP1A) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; //Sync to SYSCLKOUT GPIO51(EQEP1B) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; //Sync to SYSCLKOUT GPIO52(EQEP1S) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; //Sync to SYSCLKOUT GPIO53(EQEP1I) + + // + // Configure eQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be eQEP1 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I + + //GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A + //GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B + //GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S + //GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I + + EDIS; +} +#endif // if DSP28_EQEP1 + +// +// InitEQep2Gpio - This function initializes GPIO pins to function as eQEP2 +// +#if DSP28_EQEP2 +void +InitEQep2Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (EQEP2A) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (EQEP2B) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (EQEP2I) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (EQEP2S) + + // + // Inputs are synchronized to SYSCLKOUT by default. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S) + + // + // Configure eQEP-2 pins using GPIO regs + // This specifies which of the possible GPIO pins will be eQEP2 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S + + EDIS; +} +#endif // endif DSP28_EQEP2 + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_Gpio.c b/f2833x/common/source/DSP2833x_Gpio.c new file mode 100644 index 0000000..d7d80de --- /dev/null +++ b/f2833x/common/source/DSP2833x_Gpio.c @@ -0,0 +1,108 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:25 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.c +// +// TITLE: DSP2833x General Purpose I/O Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitGpio - This function initializes the Gpio to a known (default) state. +// +// For more details on configuring GPIO's as peripheral functions, +// refer to the individual peripheral examples and/or GPIO setup example. +// +void +InitGpio(void) +{ + EALLOW; + + // + // Each GPIO pin can be: + // a) a GPIO input/output + // b) peripheral function 1 + // c) peripheral function 2 + // d) peripheral function 3 + // By default, all are GPIO Inputs + // + GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15 + GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31 + GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39 + GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63 + GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79 + GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95 + + GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs + GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs + GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs + + // + // Each input can have different qualification + // a) input synchronized to SYSCLKOUT + // b) input qualified by a sampling window + // c) input sent asynchronously (valid for peripheral inputs only) + // + GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT + + // + // Pull-ups can be enabled or disabled + // + GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31 + GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63 + GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79 + //GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31 + //GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34 + //GpioCtrlRegs.GPCPUD.all = 0xFFFF; // Pullup's disabled GPIO64-GPIO79 + + EDIS; +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_I2C.c b/f2833x/common/source/DSP2833x_I2C.c new file mode 100644 index 0000000..d819afa --- /dev/null +++ b/f2833x/common/source/DSP2833x_I2C.c @@ -0,0 +1,110 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:27 $ +//########################################################################### +// +// FILE: DSP2833x_I2C.c +// +// TITLE: DSP2833x SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitI2C - This function initializes the I2C to a known state. +// +void +InitI2C(void) +{ + // + // Initialize I2C-A + // +} + +// +// InitI2CGpio - This function initializes GPIO pins to function as I2C pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for SDAA operation. +// Only one GPIO pin shoudl be enabled for SCLA operation. +// Comment out other unwanted lines. +// +void +InitI2CGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA) + + // + // Set qualification for selected pins to asynch only + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA) + + // + // Configure SCI pins using GPIO regs + // This specifies which of the possible GPIO pins will be I2C functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 to SDAA + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 to SCLA + + EDIS; +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_Mcbsp.c b/f2833x/common/source/DSP2833x_Mcbsp.c new file mode 100644 index 0000000..6b2c90a --- /dev/null +++ b/f2833x/common/source/DSP2833x_Mcbsp.c @@ -0,0 +1,552 @@ +// TI File $Revision: /main/16 $ +// Checkin $Date: October 3, 2007 14:50:19 $ +//########################################################################### +// +// FILE: DSP2833x_McBSP.c +// +// TITLE: DSP2833x Device McBSP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate +// generator (SRG) cycles required for the Mcbsp initialization routine. +// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock +// generator (CLKG) cycles required for the Mcbsp initialization routine. +// For the functions defined in Mcbsp.c, MCBSP_INIT_DELAY and MCBSP_CLKG_DELAY +// are based off of either a 150 MHz SYSCLKOUT (default) or a 100 MHz SYSCLKOUT +// + +// +// CPU_FRQ_100MHZ and CPU_FRQ_150MHZ are defined in DSP2833x_Examples.h +// + +// +// For 150 MHz SYSCLKOUT(default) +// +#if CPU_FRQ_150MHZ + #define CPU_SPD 150E6 + + // + // SRG input is LSPCLK (SYSCLKOUT/4) for examples + // + #define MCBSP_SRG_FREQ CPU_SPD/4 +#endif + +// +// For 100 MHz SYSCLKOUT +// +#if CPU_FRQ_100MHZ + #define CPU_SPD 100E6 + + // + // SRG input is LSPCLK (SYSCLKOUT/4) for examples + // + #define MCBSP_SRG_FREQ CPU_SPD/4 +#endif + +#define CLKGDV_VAL 1 + +// +// # of CPU cycles in 2 SRG cycles-init delay +// +#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) + +// +// # of CPU cycles in 2 CLKG cycles-init delay +// +#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) + +// +// Function Prototypes +// +void delay_loop(void); // Delay function used for SRG initialization +void clkg_delay_loop(void); // Delay function used for CLKG initialization + +// +// InitMcbsp - This function initializes the McBSP to a known state. +// +void InitMcbsp(void) +{ + InitMcbspa(); +#if DSP28_MCBSPB + InitMcbspb(); +#endif // end DSP28_MCBSPB +} + +// +// InitMcbspa - This function initializes McBSPa to a known state. +// +void +InitMcbspa(void) +{ + // + // McBSP-A register settings + // + + // + // Reset FS generator, sample rate generator & transmitter + // + McbspaRegs.SPCR2.all=0x0000; + + McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + + // + // Enable loopback mode for test. + // Comment out for normal McBSP transfer mode. + // + McbspaRegs.SPCR1.bit.DLB = 1; + + McbspaRegs.MFFINT.all=0x0; // Disable all interrupts + + // + // Single-phase frame, 1 word/frame, No companding (Receive) + // + McbspaRegs.RCR2.all=0x0; + McbspaRegs.RCR1.all=0x0; + + // + // Single-phase frame, 1 word/frame, No companding (Transmit) + // + McbspaRegs.XCR2.all=0x0; + McbspaRegs.XCR1.all=0x0; + + // + // FSX generated internally, FSR derived from an external source + // + McbspaRegs.PCR.bit.FSXM = 1; + + // + // CLKX generated internally, CLKR derived from an external source + // + McbspaRegs.PCR.bit.CLKXM = 1; + + // + // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + // + McbspaRegs.SRGR2.bit.CLKSM = 1; + + McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + + // + // CLKG frequency = LSPCLK/(CLKGDV+1) + // + McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; + + delay_loop(); // Wait at least 2 SRG clock cycles + + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + clkg_delay_loop(); // Wait at least 2 CLKG cycles + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset +} + +// +// InitMcbspb - This function initializes McBSPb to a known state. +// +#if (DSP28_MCBSPB) +void +InitMcbspb(void) +{ + // + // McBSP-B register settings + // + + // + // Reset FS generator, sample rate generator & transmitter + // + McbspbRegs.SPCR2.all=0x0000; + + McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + + // + // Enable loopback mode for test. + // Comment out for normal McBSP transfer mode. + // + McbspbRegs.SPCR1.bit.DLB = 1; + + McbspbRegs.MFFINT.all=0x0; // Disable all interrupts + + // + // Single-phase frame, 1 word/frame, No companding (Receive) + // + McbspbRegs.RCR2.all=0x0; + McbspbRegs.RCR1.all=0x0; + + // + // Single-phase frame, 1 word/frame, No companding (Transmit) + // + McbspbRegs.XCR2.all=0x0; + McbspbRegs.XCR1.all=0x0; + + // + // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + // + McbspbRegs.SRGR2.bit.CLKSM = 1; + McbspbRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspbRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + + // + // CLKG frequency = LSPCLK/(CLKGDV+1) + // + McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; + + // + // FSX generated internally, FSR derived from an external source + // + McbspbRegs.PCR.bit.FSXM = 1; + + // + // CLKX generated internally, CLKR derived from an external source + // + McbspbRegs.PCR.bit.CLKXM = 1; + + delay_loop(); // Wait at least 2 SRG clock cycles + McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + clkg_delay_loop(); // Wait at least 2 CLKG cycles + McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset +} +#endif // end DSP28_MCBSPB + +// +// InitMcbspa8bit - McBSP-A 8-bit Length +// +void +InitMcbspa8bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=0; // 8-bit word + McbspaRegs.XCR1.bit.XWDLEN1=0; // 8-bit word +} + +// +// InitMcbspa12bit - McBSP-A 12 bit Length +// +void +InitMcbspa12bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=1; // 12-bit word + McbspaRegs.XCR1.bit.XWDLEN1=1; // 12-bit word +} + +// +// InitMcbspa16bit - McBSP-A 16 bit Length +// +void +InitMcbspa16bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=2; // 16-bit word + McbspaRegs.XCR1.bit.XWDLEN1=2; // 16-bit word +} + +// +// InitMcbspa20bit - McBSP-A 20 bit Length +// +void +InitMcbspa20bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=3; // 20-bit word + McbspaRegs.XCR1.bit.XWDLEN1=3; // 20-bit word +} + +// +// InitMcbspa24bit - McBSP-A 24 bit Length +// +void +InitMcbspa24bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=4; // 24-bit word + McbspaRegs.XCR1.bit.XWDLEN1=4; // 24-bit word +} + +// +// InitMcbspa32bit - McBSP-A 32 bit Length +// +void +InitMcbspa32bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word + McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word +} + +// +// McBSP-B Data Lengths +// +#if (DSP28_MCBSPB) +// +// InitMcbspb8bit - McBSP-B 8-bit Length +// +void +InitMcbspb8bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=0; // 8-bit word + McbspbRegs.XCR1.bit.XWDLEN1=0; // 8-bit word +} + +// +// InitMcbspb12bit - McBSP-B 12 bit Length +// +void +InitMcbspb12bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=1; // 12-bit word + McbspbRegs.XCR1.bit.XWDLEN1=1; // 12-bit word +} + +// +// InitMcbspb16bit - McBSP-B 16 bit Length +// +void +InitMcbspb16bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=2; // 16-bit word + McbspbRegs.XCR1.bit.XWDLEN1=2; // 16-bit word +} + +// +// InitMcbspb20bit - McBSP-B 20 bit Length +// +void +InitMcbspb20bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=3; // 20-bit word + McbspbRegs.XCR1.bit.XWDLEN1=3; // 20-bit word +} + +// +// InitMcbspb24bit - McBSP-B 24 bit Length +// +void +InitMcbspb24bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=4; // 24-bit word + McbspbRegs.XCR1.bit.XWDLEN1=4; // 24-bit word +} + +// +// InitMcbspb32bit - McBSP-B 32 bit Length +// +void +InitMcbspb32bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1=5; // 32-bit word + McbspbRegs.XCR1.bit.XWDLEN1=5; // 32-bit word +} + +#endif //end DSP28_MCBSPB + +// +// InitMcbspGpio - +// +void +InitMcbspGpio(void) +{ + InitMcbspaGpio(); +#if DSP28_MCBSPB + InitMcbspbGpio(); +#endif // end DSP28_MCBSPB +} + +// +// InitMcbspaGpio - This function initializes GPIO pins to function as McBSP-A +// +void +InitMcbspaGpio(void) +{ + EALLOW; + + // + // Configure McBSP-A pins using GPIO regs + // This specifies which of the possible GPIO pins will be McBSP functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // GPIO20 is MDXA pin + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // GPIO21 is MDRA pin + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 is MCLKXA pin + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; // GPIO7 is MCLKRA pin + //GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; // GPIO58 is MCLKRA pin + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // GPIO23 is MFSXA pin + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // GPIO5 is MFSRA pin + //GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; // GPIO59 is MFSRA pin + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (MDXA) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (MDRA) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (MCLKXA) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (MCLKRA) + //GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (MCLKRA) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (MFSXA) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (MFSRA) + //GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (MFSRA) + + // + // Set qualification for selected input pins to asynch only + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch input GPIO21 (MDRA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // Asynch input GPIO22 (MCLKXA) + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; // Asynch input GPIO7 (MCLKRA) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58(MCLKRA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (MFSXA) + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (MFSRA) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (MFSRA) + + EDIS; +} + +// +// InitMcbspbGpio - This function initializes GPIO pins to function as McBSP-B +// +#if DSP28_MCBSPB +void +InitMcbspbGpio(void) +{ + EALLOW; + + // + // Configure McBSP-A pins using GPIO regs + // This specifies which of the possible GPIO pins will be McBSP functional + // pins. + // Comment out other unwanted lines. + //GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 is MDXB pin + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // GPIO24 is MDXB pin + //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 is MDRB pin + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; // GPIO25 is MDRB pin + //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 is MCLKXB pin + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; // GPIO26 is MCLKXB pin + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; // GPIO3 is MCLKRB pin + //GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; // GPIO60 is MCLKRB pin + //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 is MFSXB pin + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; // GPIO27 is MFSXB pin + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; // GPIO1 is MFSRB pin + //GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; // GPIO61 is MFSRB pin + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; //Enable pull-up on GPIO24 (MDXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; //Enable pull-up on GPIO12 (MDXB) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; //Enable pull-up on GPIO25 (MDRB) + //GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; //Enable pull-up on GPIO13 (MDRB) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; //Enable pull-up on GPIO26 (MCLKXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; //Enable pull-up on GPIO14 (MCLKXB) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; //Enable pull-up on GPIO3 (MCLKRB) + //GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; //Enable pull-up on GPIO60 (MCLKRB) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; //Enable pull-up on GPIO27 (MFSXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; //Enable pull-up on GPIO15 (MFSXB) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; //Enable pull-up on GPIO1 (MFSRB) + //GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; //Enable pull-up on GPIO61 (MFSRB) + + // + // Set qualification for selected input pins to asynch only + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO25 (MDRB) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (MDRB) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO26(MCLKXB) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (MCLKXB) + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (MCLKRB) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (MCLKRB) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO27 (MFSXB) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (MFSXB) + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; // Asynch input GPIO1 (MFSRB) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (MFSRB) + + EDIS; +} +#endif // end DSP28_MCBSPB + +// +// delay_loop - +// +void +delay_loop(void) +{ + long i; + + // + // delay in McBsp init. must be at least 2 SRG cycles + // + for (i = 0; i < MCBSP_INIT_DELAY; i++) + { + + } +} + +// +// clkg_delay_loop - +// +void +clkg_delay_loop(void) +{ + long i; + + // + // delay in McBsp init. must be at least 2 SRG cycles + // + for (i = 0; i < MCBSP_CLKG_DELAY; i++) + { + + } +} + +// +// End of File +// + diff --git a/f2833x/common/source/DSP2833x_MemCopy.c b/f2833x/common/source/DSP2833x_MemCopy.c new file mode 100644 index 0000000..c7aafe5 --- /dev/null +++ b/f2833x/common/source/DSP2833x_MemCopy.c @@ -0,0 +1,81 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:33 $ +//########################################################################### +// +// FILE: DSP2833x_MemCopy.c +// +// TITLE: Memory Copy Utility +// +// ASSUMPTIONS: +// +// DESCRIPTION: +// +// This function will copy the specified memory contents from +// one location to another. +// +// Uint16 *SourceAddr Pointer to the first word to be moved +// SourceAddr < SourceEndAddr +// Uint16* SourceEndAddr Pointer to the last word to be moved +// Uint16* DestAddr Pointer to the first destination word +// +// No checks are made for invalid memory locations or that the +// end address is > then the first start address. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" + +// +// MemCopy - +// +void +MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr) +{ + while(SourceAddr < SourceEndAddr) + { + *DestAddr++ = *SourceAddr++; + } + return; +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_PieCtrl.c b/f2833x/common/source/DSP2833x_PieCtrl.c new file mode 100644 index 0000000..2b8303c --- /dev/null +++ b/f2833x/common/source/DSP2833x_PieCtrl.c @@ -0,0 +1,126 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:35 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.c +// +// TITLE: DSP2833x Device PIE Control Register Initialization Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitPieCtrl - This function initializes the PIE control registers to a known +// state. +// +void +InitPieCtrl(void) +{ + // + // Disable Interrupts at the CPU level + // + DINT; + + // + // Disable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // + // Clear all PIEIER registers + // + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // + // Clear all PIEIFR registers + // + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; +} + +// +// EnableInterrupts - This function enables the PIE module and CPU interrupts +// +void +EnableInterrupts() +{ + // + // Enable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enables PIE to drive a pulse into the CPU + // + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // + // Enable Interrupts at the CPU level + // + EINT; +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_PieVect.c b/f2833x/common/source/DSP2833x_PieVect.c new file mode 100644 index 0000000..d61c542 --- /dev/null +++ b/f2833x/common/source/DSP2833x_PieVect.c @@ -0,0 +1,262 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:38 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.c +// +// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +const struct PIE_VECT_TABLE PieVectTableInit = +{ + PIE_RESERVED, // 0 Reserved space + PIE_RESERVED, // 1 Reserved space + PIE_RESERVED, // 2 Reserved space + PIE_RESERVED, // 3 Reserved space + PIE_RESERVED, // 4 Reserved space + PIE_RESERVED, // 5 Reserved space + PIE_RESERVED, // 6 Reserved space + PIE_RESERVED, // 7 Reserved space + PIE_RESERVED, // 8 Reserved space + PIE_RESERVED, // 9 Reserved space + PIE_RESERVED, // 10 Reserved space + PIE_RESERVED, // 11 Reserved space + PIE_RESERVED, // 12 Reserved space + + // + // Non-Peripheral Interrupts + // + INT13_ISR, // XINT13 or CPU-Timer 1 + INT14_ISR, // CPU-Timer2 + DATALOG_ISR, // Datalogging interrupt + RTOSINT_ISR, // RTOS interrupt + EMUINT_ISR, // Emulation interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + + // + // Group 1 PIE Vectors + // + SEQ1INT_ISR, // 1.1 ADC + SEQ2INT_ISR, // 1.2 ADC + rsvd_ISR, // 1.3 + XINT1_ISR, // 1.4 + XINT2_ISR, // 1.5 + ADCINT_ISR, // 1.6 ADC + TINT0_ISR, // 1.7 Timer 0 + WAKEINT_ISR, // 1.8 WD, Low Power + + // + // Group 2 PIE Vectors + // + EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone + EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone + EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone + EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone + EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone + EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone + rsvd_ISR, // 2.7 + rsvd_ISR, // 2.8 + + // + // Group 3 PIE Vectors + // + EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt + EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt + EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt + EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt + EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt + EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt + rsvd_ISR, // 3.7 + rsvd_ISR, // 3.8 + + // + // Group 4 PIE Vectors + // + ECAP1_INT_ISR, // 4.1 ECAP-1 + ECAP2_INT_ISR, // 4.2 ECAP-2 + ECAP3_INT_ISR, // 4.3 ECAP-3 + ECAP4_INT_ISR, // 4.4 ECAP-4 + ECAP5_INT_ISR, // 4.5 ECAP-5 + ECAP6_INT_ISR, // 4.6 ECAP-6 + rsvd_ISR, // 4.7 + rsvd_ISR, // 4.8 + + // + // Group 5 PIE Vectors + // + EQEP1_INT_ISR, // 5.1 EQEP-1 + EQEP2_INT_ISR, // 5.2 EQEP-2 + rsvd_ISR, // 5.3 + rsvd_ISR, // 5.4 + rsvd_ISR, // 5.5 + rsvd_ISR, // 5.6 + rsvd_ISR, // 5.7 + rsvd_ISR, // 5.8 + + // + // Group 6 PIE Vectors + // + SPIRXINTA_ISR, // 6.1 SPI-A + SPITXINTA_ISR, // 6.2 SPI-A + MRINTA_ISR, // 6.3 McBSP-A + MXINTA_ISR, // 6.4 McBSP-A + MRINTB_ISR, // 6.5 McBSP-B + MXINTB_ISR, // 6.6 McBSP-B + rsvd_ISR, // 6.7 + rsvd_ISR, // 6.8 + + // + // Group 7 PIE Vectors + // + DINTCH1_ISR, // 7.1 DMA channel 1 + DINTCH2_ISR, // 7.2 DMA channel 2 + DINTCH3_ISR, // 7.3 DMA channel 3 + DINTCH4_ISR, // 7.4 DMA channel 4 + DINTCH5_ISR, // 7.5 DMA channel 5 + DINTCH6_ISR, // 7.6 DMA channel 6 + rsvd_ISR, // 7.7 + rsvd_ISR, // 7.8 + + // + // Group 8 PIE Vectors + // + I2CINT1A_ISR, // 8.1 I2C + I2CINT2A_ISR, // 8.2 I2C + rsvd_ISR, // 8.3 + rsvd_ISR, // 8.4 + SCIRXINTC_ISR, // 8.5 SCI-C + SCITXINTC_ISR, // 8.6 SCI-C + rsvd_ISR, // 8.7 + rsvd_ISR, // 8.8 + + // + // Group 9 PIE Vectors + // + SCIRXINTA_ISR, // 9.1 SCI-A + SCITXINTA_ISR, // 9.2 SCI-A + SCIRXINTB_ISR, // 9.3 SCI-B + SCITXINTB_ISR, // 9.4 SCI-B + ECAN0INTA_ISR, // 9.5 eCAN-A + ECAN1INTA_ISR, // 9.6 eCAN-A + ECAN0INTB_ISR, // 9.7 eCAN-B + ECAN1INTB_ISR, // 9.8 eCAN-B + + // + // Group 10 PIE Vectors + // + rsvd_ISR, // 10.1 + rsvd_ISR, // 10.2 + rsvd_ISR, // 10.3 + rsvd_ISR, // 10.4 + rsvd_ISR, // 10.5 + rsvd_ISR, // 10.6 + rsvd_ISR, // 10.7 + rsvd_ISR, // 10.8 + + // + // Group 11 PIE Vectors + // + rsvd_ISR, // 11.1 + rsvd_ISR, // 11.2 + rsvd_ISR, // 11.3 + rsvd_ISR, // 11.4 + rsvd_ISR, // 11.5 + rsvd_ISR, // 11.6 + rsvd_ISR, // 11.7 + rsvd_ISR, // 11.8 + + // + // Group 12 PIE Vectors + // + XINT3_ISR, // 12.1 + XINT4_ISR, // 12.2 + XINT5_ISR, // 12.3 + XINT6_ISR, // 12.4 + XINT7_ISR, // 12.5 + rsvd_ISR, // 12.6 + LVF_ISR, // 12.7 + LUF_ISR, // 12.8 +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a known +// state. This function must be executed after boot time. +// +void +InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + volatile Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) + { + *Dest++ = *Source++; + } + EDIS; + + // + // Enable the PIE Vector Table + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_SWPrioritizedDefaultIsr.c b/f2833x/common/source/DSP2833x_SWPrioritizedDefaultIsr.c new file mode 100644 index 0000000..bd5b623 --- /dev/null +++ b/f2833x/common/source/DSP2833x_SWPrioritizedDefaultIsr.c @@ -0,0 +1,2670 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 14, 2008 11:28:12 $ +//########################################################################### +// +// FILE: DSP2833x_SWPrioritizedDefaultIsr.c +// +// TITLE: DSP2833x Device Default Software Prioritized Interrupt +// Service Routines. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +// +// INT13_ISR - Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +// +#if (INT13PL != 0) +interrupt void +INT13_ISR(void) // INT13 or CPU-Timer1 +{ + IER |= MINT13; // Set "global" priority + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// INT14_ISR - Connected to INT14 of CPU (use MINT14 mask): +// +#if (INT14PL != 0) +interrupt void +INT14_ISR(void) // CPU-Timer2 +{ + IER |= MINT14; // Set "global" priority + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// DATALOG_ISR - Connected to INT15 of CPU (use MINT15 mask): +// +#if (INT15PL != 0) +interrupt void +DATALOG_ISR(void) // Datalogging interrupt +{ + IER |= MINT15; // Set "global" priority + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// RTOSINT_ISR - Connected to INT16 of CPU (use MINT16 mask): +// +#if (INT16PL != 0) +interrupt void +RTOSINT_ISR(void) // RTOS interrupt +{ + IER |= MINT16; // Set "global" priority + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EMUINT_ISR - Emulation interrupt is connected to EMUINT of CPU(non-maskable) +// +interrupt void +EMUINT_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// NMI_ISR - Non-maskable interrupt is connected to NMI of CPU (non-maskable): +// +interrupt void +NMI_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;);; +} + +// +// ILLEGAL_ISR - Illegal operation TRAP +// +interrupt void +ILLEGAL_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER1_ISR - User Defined trap 1 +// +interrupt void +USER1_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER2_ISR - User Defined trap 2 +// +interrupt void +USER2_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER3_ISR - User Defined trap 3 +// +interrupt void +USER3_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER4_ISR - User Defined trap 4 +// +interrupt void +USER4_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER5_ISR - User Defined trap 5 +// +interrupt void +USER5_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER6_ISR - User Defined trap 6 +// +interrupt void +USER6_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER7_ISR - User Defined trap 7 +// +interrupt void +USER7_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER8_ISR - User Defined trap 8 +// +interrupt void +USER8_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER9_ISR - User Defined trap 9 +// +interrupt void +USER9_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER10_ISR - User Defined trap 10 +// +interrupt void +USER10_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER11_ISR - User Defined trap 11 +// +interrupt void +USER11_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER12_ISR - User Defined trap 12 +// +interrupt void +USER12_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 1 - MUXed into CPU INT1 +// + +// +// EQ1INT_ISR - Connected to PIEIER1_1 (use MINT1 and MG11 masks): +// +#if (G11PL != 0) +interrupt void +EQ1INT_ISR( void ) // ADC +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// SEQ2INT_ISR - Connected to PIEIER1_2 (use MINT1 and MG12 masks): +// +#if (G12PL != 0) +interrupt void +SEQ2INT_ISR( void ) // ADC +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// XINT1_ISR - Connected to PIEIER1_4 (use MINT1 and MG14 masks): +// +#if (G14PL != 0) +interrupt void +XINT1_ISR(void) +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// XINT2_ISR - Connected to PIEIER1_5 (use MINT1 and MG15 masks): +// +#if (G15PL != 0) +interrupt void +XINT2_ISR(void) +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// ADCINT_ISR - Connected to PIEIER1_6 (use MINT1 and MG16 masks): +// +#if (G16PL != 0) +interrupt void +ADCINT_ISR(void) // ADC +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// TINT0_ISR - Connected to PIEIER1_7 (use MINT1 and MG17 masks): +// +#if (G17PL != 0) +interrupt void +TINT0_ISR(void) // CPU-Timer 0 +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// WAKEINT_ISR - Connected to PIEIER1_8 (use MINT1 and MG18 masks): +// +#if (G18PL != 0) +interrupt void +WAKEINT_ISR(void) // WD/LPM +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// PIE Group 2 - MUXed into CPU INT2 +// + +// +// EPWM1_TZINT_ISR - Connected to PIEIER2_1 (use MINT2 and MG21 masks): +// +#if (G21PL != 0) +interrupt void +EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EPWM2_TZINT_ISR - Connected to PIEIER2_2 (use MINT2 and MG22 masks): +// +#if (G22PL != 0) +interrupt void +EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EPWM3_TZINT_ISR - Connected to PIEIER2_3 (use MINT2 and MG23 masks): +// +#if (G23PL != 0) +interrupt void +EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EPWM4_TZINT_ISR - Connected to PIEIER2_4 (use MINT2 and MG24 masks): +// +#if (G24PL != 0) +interrupt void +EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EPWM5_TZINT_ISR - Connected to PIEIER2_5 (use MINT2 and MG25 masks) +// +#if (G25PL != 0) +interrupt void +EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EPWM6_TZINT_ISR - Connected to PIEIER2_6 (use MINT2 and MG26 masks) +// +#if (G26PL != 0) +interrupt void +EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// PIE Group 3 - MUXed into CPU INT3 +// + +// +// EPWM1_INT_ISR - Connected to PIEIER3_1 (use MINT3 and MG31 masks) +// +#if (G31PL != 0) +interrupt void +EPWM1_INT_ISR(void) // ePWM1 Interrupt +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EPWM2_INT_ISR - Connected to PIEIER3_2 (use MINT3 and MG32 masks) +// +#if (G32PL != 0) +interrupt void +EPWM2_INT_ISR(void) // ePWM2 Interrupt +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EPWM3_INT_ISR - Connected to PIEIER3_3 (use MINT3 and MG33 masks) +// +#if (G33PL != 0) +interrupt void +EPWM3_INT_ISR(void) // ePWM3 Interrupt +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// Connected to PIEIER3_4 (use MINT3 and MG34 masks) +// +#if (G34PL != 0) +interrupt void +EPWM4_INT_ISR(void) // ePWM4 Interrupt +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EPWM5_INT_ISR - Connected to PIEIER3_5 (use MINT3 and MG35 masks) +// +#if (G35PL != 0) +interrupt void +EPWM5_INT_ISR(void) // ePWM5 Interrupt +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EPWM6_INT_ISR - Connected to PIEIER3_6 (use MINT3 and MG36 masks) +// +#if (G36PL != 0) +interrupt void +EPWM6_INT_ISR(void) // ePWM6 Interrupt +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// PIE Group 4 - MUXed into CPU INT4 +// + +// +// ECAP1_INT_ISR - Connected to PIEIER4_1 (use MINT4 and MG41 masks) +// +#if (G41PL != 0) +interrupt void +ECAP1_INT_ISR(void) // eCAP1 Interrupt +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// Connected to PIEIER4_2 (use MINT4 and MG42 masks): +// +#if (G42PL != 0) +interrupt void +ECAP2_INT_ISR(void) // eCAP2 Interrupt +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// ECAP3_INT_ISR - Connected to PIEIER4_3 (use MINT4 and MG43 masks) +// +#if (G43PL != 0) +interrupt void +ECAP3_INT_ISR(void) // eCAP3 Interrupt +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// ECAP4_INT_ISR - Connected to PIEIER4_4 (use MINT4 and MG44 masks) +// +#if (G44PL != 0) +interrupt void +ECAP4_INT_ISR(void) // eCAP4 Interrupt +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here. + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// ECAP5_INT_ISR - Connected to PIEIER4_5 (use MINT4 and MG45 masks): +// +#if (G45PL != 0) +interrupt void +ECAP5_INT_ISR(void) // eCAP5 Interrupt +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// ECAP6_INT_ISR - Connected to PIEIER4_6 (use MINT4 and MG46 masks): +// +#if (G46PL != 0) +interrupt void +ECAP6_INT_ISR(void) // eCAP6 Interrupt +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// PIE Group 5 - MUXed into CPU INT5 +// + +// +// Connected to PIEIER5_1 (use MINT5 and MG51 masks) +// +#if (G51PL != 0) +interrupt void +EQEP1_INT_ISR(void) // eQEP1 Interrupt +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // Insert ISR Code here....... + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EQEP2_INT_ISR - Connected to PIEIER5_2 (use MINT5 and MG52 masks) +// +#if (G52PL != 0) +interrupt void +EQEP2_INT_ISR(void) // eQEP2 Interrupt +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// PIE Group 6 - MUXed into CPU INT6 +// + +// +// SPIRXINTA_ISR - Connected to PIEIER6_1 (use MINT6 and MG61 masks) +// +#if (G61PL != 0) +interrupt void +SPIRXINTA_ISR(void) // SPI-A +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// SPITXINTA_ISR - Connected to PIEIER6_2 (use MINT6 and MG62 masks) +// +#if (G62PL != 0) +interrupt void +SPITXINTA_ISR(void) // SPI-A +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// MRINTB_ISR - Connected to PIEIER6_3 (use MINT6 and MG63 masks) +// +#if (G63PL != 0) +interrupt void +MRINTB_ISR(void) // McBSP-B +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// MXINTB_ISR - Connected to PIEIER6_4 (use MINT6 and MG64 masks) +// +#if (G64PL != 0) +interrupt void +MXINTB_ISR(void) // McBSP-B +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// MRINTA_ISR - Connected to PIEIER6_5 (use MINT6 and MG65 masks) +// +#if (G65PL != 0) +interrupt void +MRINTA_ISR(void) // McBSP-A +{ + // + // Set interrupt priority: + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// MXINTA_ISR - Connected to PIEIER6_6 (use MINT6 and MG66 masks) +// +#if (G66PL != 0) +interrupt void +MXINTA_ISR(void) // McBSP-A +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// PIE Group 7 - MUXed into CPU INT7 +// + +// +// DINTCH1_ISR - Connected to PIEIER7_1 (use MINT7 and MG71 masks) +// +#if (G71PL != 0) +interrupt void +DINTCH1_ISR(void) // DMA +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// DINTCH2_ISR - Connected to PIEIER7_2 (use MINT7 and MG72 masks) +// +#if (G72PL != 0) +interrupt void +DINTCH2_ISR(void) // DMA +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// DINTCH3_ISR - Connected to PIEIER7_3 (use MINT7 and MG73 masks) +// +#if (G73PL != 0) +interrupt void +DINTCH3_ISR(void) // DMA +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// DINTCH4_ISR - Connected to PIEIER7_4 (use MINT7 and MG74 masks) +// +#if (G74PL != 0) +interrupt void +DINTCH4_ISR(void) // DMA +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved: + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// DINTCH5_ISR - Connected to PIEIER7_5 (use MINT7 and MG75 masks): +// +#if (G75PL != 0) +interrupt void +DINTCH5_ISR(void) // DMA +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// DINTCH6_ISR - Connected to PIEIER7_6 (use MINT7 and MG76 masks) +// +#if (G76PL != 0) +interrupt void +DINTCH6_ISR(void) // DMA +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// PIE Group 8 - MUXed into CPU INT8 +// + +// +// I2CINT1A_ISR - Connected to PIEIER8_1 (use MINT8 and MG81 masks) +// +#if (G81PL != 0) +interrupt void +I2CINT1A_ISR(void) // I2C-A +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// I2CINT2A_ISR - Connected to PIEIER8_2 (use MINT8 and MG82 masks) +// +#if (G82PL != 0) +interrupt void +I2CINT2A_ISR(void) // I2C-A +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// SCIRXINTC_ISR - Connected to PIEIER8_5 (use MINT8 and MG85 masks) +// +#if (G85PL != 0) +interrupt void +SCIRXINTC_ISR(void) // SCI-C +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// SCITXINTC_ISR - Connected to PIEIER8_6 (use MINT8 and MG86 masks) +// +#if (G82PL != 0) +interrupt void +SCITXINTC_ISR(void) // SCI-C +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// PIE Group 9 - MUXed into CPU INT9 +// + +// +// SCIRXINTA_ISR - Connected to PIEIER9_1 (use MINT9 and MG91 masks) +// +#if (G91PL != 0) +interrupt void +SCIRXINTA_ISR(void) // SCI-A +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// SCITXINTA_ISR - Connected to PIEIER9_2 (use MINT9 and MG92 masks) +// +#if (G92PL != 0) +interrupt void +SCITXINTA_ISR(void) // SCI-A +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// SCIRXINTB_ISR - Connected to PIEIER9_3 (use MINT9 and MG93 masks) +// +#if (G93PL != 0) +interrupt void +SCIRXINTB_ISR(void) // SCI-B +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// SCITXINTB_ISR - Connected to PIEIER9_4 (use MINT9 and MG94 masks) +// +#if (G94PL != 0) +interrupt void +SCITXINTB_ISR(void) // SCI-B +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// ECAN0INTA_ISR - Connected to PIEIER9_5 (use MINT9 and MG95 masks) +// +#if (G95PL != 0) +interrupt void +ECAN0INTA_ISR(void) // eCAN-A +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// ECAN1INTA_ISR - Connected to PIEIER9_6 (use MINT9 and MG96 masks) +// +#if (G96PL != 0) +interrupt void +ECAN1INTA_ISR(void) // eCAN-A +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// ECAN0INTB_ISR - Connected to PIEIER9_7 (use MINT9 and MG97 masks) +// +#if (G97PL != 0) +interrupt void +ECAN0INTB_ISR(void) // eCAN-B +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// ECAN1INTB_ISR - Connected to PIEIER9_8 (use MINT9 and MG98 masks) +// +#if (G98PL != 0) +interrupt void +ECAN1INTB_ISR(void) // eCAN-B +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// PIE Group 10 - MUXed into CPU INT10 +// + +// +// PIE Group 11 - MUXed into CPU INT11 +// + +// +// PIE Group 12 - MUXed into CPU INT12 +// + +// +// XINT3_ISR - Connected to PIEIER9_1 (use MINT12 and MG121 masks) +// +#if (G121PL != 0) +interrupt void +XINT3_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// XINT4_ISR - Connected to PIEIER12_2 (use MINT12 and MG122 masks) +// +#if (G122PL != 0) +interrupt void +XINT4_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// XINT5_ISR - Connected to PIEIER12_3 (use MINT12 and MG123 masks) +// +#if (G123PL != 0) +interrupt void +XINT5_ISR(void) // SCI-B +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// XINT6_ISR - Connected to PIEIER12_4 (use MINT12 and MG124 masks) +// +#if (G124PL != 0) +interrupt void +XINT6_ISR(void) // SCI-B +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// XINT7_ISR - Connected to PIEIER12_5 (use MINT12 and MG125 masks) +// +#if (G125PL != 0) +interrupt void +XINT7_ISR(void) // eCAN-A +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// LVF_ISR - Connected to PIEIER12_7 (use MINT12 and MG127 masks) +// +#if (G127PL != 0) +interrupt void +LVF_ISR(void) // FPU +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// LUF_ISR - Connected to PIEIER12_8 (use MINT12 and MG128 masks) +// +#if (G128PL != 0) +interrupt void +LUF_ISR(void) // FPU +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} +#endif + +// +// Catch All Default ISRs +// + +// +// PIE_RESERVED - Reserved space. For test. +// +interrupt void +PIE_RESERVED(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// INT_NOTUSED_ISR - Reserved space. For test. +// +interrupt void +INT_NOTUSED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// rsvd_ISR - For test +// +interrupt void +rsvd_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// End of File +// + diff --git a/f2833x/common/source/DSP2833x_SWPrioritizedPieVect.c b/f2833x/common/source/DSP2833x_SWPrioritizedPieVect.c new file mode 100644 index 0000000..ac247dd --- /dev/null +++ b/f2833x/common/source/DSP2833x_SWPrioritizedPieVect.c @@ -0,0 +1,568 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 4, 2007 14:25:31 $ +//########################################################################### +// +// FILE: DSP2833x_SWPiroritizedPieVect.c +// +// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +const struct PIE_VECT_TABLE PieVectTableInit = +{ + PIE_RESERVED, // Reserved space + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + + // + // Non-Peripheral Interrupts: + // + #if (INT13PL != 0) + INT13_ISR, // XINT13 + #else + INT_NOTUSED_ISR, + #endif + + #if (INT14PL != 0) + INT14_ISR, // CPU-Timer2 + #else + INT_NOTUSED_ISR, + #endif + + #if (INT15PL != 0) + DATALOG_ISR, // Datalogging interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT16PL != 0) + RTOSINT_ISR, // RTOS interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, // reserved interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + + // + // Group 1 PIE Vectors: + // + #if (G11PL != 0) + SEQ1INT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + #if (G12PL != 0) + SEQ2INT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + + #if (G14PL != 0) + XINT1_ISR, // External + #else + INT_NOTUSED_ISR, + #endif + + #if (G15PL != 0) + XINT2_ISR, // External + #else + INT_NOTUSED_ISR, + #endif + + #if (G16PL != 0) + ADCINT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + #if (G17PL != 0) + TINT0_ISR, // Timer 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G18PL != 0) + WAKEINT_ISR, // WD & Low Power + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 2 PIE Vectors: + // + #if (G21PL != 0) + EPWM1_TZINT_ISR, // ePWM1 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G22PL != 0) + EPWM2_TZINT_ISR, // ePWM2 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G23PL != 0) + EPWM3_TZINT_ISR, // ePWM3 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G24PL != 0) + EPWM4_TZINT_ISR, // ePWM4 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G25PL != 0) + EPWM5_TZINT_ISR, // ePWM5 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G26PL != 0) + EPWM6_TZINT_ISR, // ePWM6 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + // + // Group 3 PIE Vectors: + // + #if (G31PL != 0) + EPWM1_INT_ISR, // ePWM1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G32PL != 0) + EPWM2_INT_ISR, // ePWM2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G33PL != 0) + EPWM3_INT_ISR, // ePWM3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G34PL != 0) + EPWM4_INT_ISR, // ePWM4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G35PL != 0) + EPWM5_INT_ISR, // ePWM5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G36PL != 0) + EPWM6_INT_ISR, // ePWM6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + // + // Group 4 PIE Vectors: + // + #if (G41PL != 0) + ECAP1_INT_ISR, // eCAP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G42PL != 0) + ECAP2_INT_ISR, // eCAP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G43PL != 0) + ECAP3_INT_ISR, // eCAP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G44PL != 0) + ECAP4_INT_ISR, // eCAP4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G45PL != 0) + ECAP5_INT_ISR, // eCAP5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G46PL != 0) + ECAP6_INT_ISR, // eCAP6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + // + // Group 5 PIE Vectors: + // + #if (G51PL != 0) + EQEP1_INT_ISR, // eQEP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G52PL != 0) + EQEP2_INT_ISR, // eQEP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + + // + // Group 6 PIE Vectors: + // + #if (G61PL != 0) + SPIRXINTA_ISR, // SPI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G62PL != 0) + SPITXINTA_ISR, // SPI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G63PL != 0) + MRINTB_ISR, // McBSP-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G64PL != 0) + MXINTB_ISR, // McBSP-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G65PL != 0) + MRINTA_ISR, // McBSP-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G66PL != 0) + MXINTA_ISR, // McBSP-A + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + // + // Group 7 PIE Vectors: + // + #if (G71PL != 0) + DINTCH1_ISR, // DMA-Channel 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G72PL != 0) + DINTCH2_ISR, // DMA-Channel 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G73PL != 0) + DINTCH3_ISR, // DMA-Channel 3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G74PL != 0) + DINTCH4_ISR, // DMA-Channel 4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G75PL != 0) + DINTCH5_ISR, // DMA-Channel 5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G76PL != 0) + DINTCH6_ISR, // DMA-Channel 6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + // + // Group 8 PIE Vectors: + // + #if (G81PL != 0) + I2CINT1A_ISR, // I2C-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G82PL != 0) + I2CINT2A_ISR, // I2C-A + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + #if (G85PL != 0) + SCIRXINTC_ISR, // SCI-C + #else + INT_NOTUSED_ISR, + #endif + + #if (G86PL != 0) + SCITXINTC_ISR, // SCI-C + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + // + // Group 9 PIE Vectors: + // + #if (G91PL != 0) + SCIRXINTA_ISR, // SCI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G92PL != 0) + SCITXINTA_ISR, // SCI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G93PL != 0) + SCIRXINTB_ISR, // SCI-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G94PL != 0) + SCITXINTB_ISR, // SCI-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G95PL != 0) + ECAN0INTA_ISR, // eCAN-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G96PL != 0) + ECAN1INTA_ISR, // eCAN-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G97PL != 0) + ECAN0INTB_ISR, // eCAN-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G98PL != 0) + ECAN1INTB_ISR, // eCAN-B + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 10 PIE Vectors + // + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + + // + // Group 11 PIE Vectors + // + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + + // + // Group 12 PIE Vectors + // + #if (G121PL != 0) + XINT3_ISR, // External interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G122PL != 0) + XINT4_ISR, // External interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G123PL != 0) + XINT5_ISR, // External interrupt 5 + #else + INT_NOTUSED_ISR, + #endif + + #if (G124PL != 0) + XINT6_ISR, // External interrupt 6 + #else + INT_NOTUSED_ISR, + #endif + + #if (G125PL != 0) + XINT7_ISR, // External interrupt 7 + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + + #if (G127PL != 0) + LVF_ISR, // Latched overflow flag + #else + INT_NOTUSED_ISR, + #endif + + #if (G128PL != 0) + LUF_ISR, // Latched underflow flag + #else + INT_NOTUSED_ISR, + #endif +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a known +// state. This function must be executed after boot time. +// +void +InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) + { + *Dest++ = *Source++; + } + EDIS; +} + +// +// End of File +// + diff --git a/f2833x/common/source/DSP2833x_Sci.c b/f2833x/common/source/DSP2833x_Sci.c new file mode 100644 index 0000000..29d5b7f --- /dev/null +++ b/f2833x/common/source/DSP2833x_Sci.c @@ -0,0 +1,224 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 16:06:07 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.c +// +// TITLE: DSP2833x SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitSci - This function initializes the SCI(s) to a known state. +// +void +InitSci(void) +{ + // + // Initialize SCI-A + // + + // + // Initialize SCI-B + // + + // + // Initialize SCI-C + // +} + +// +// InitSciGpio - This function initializes GPIO to function as SCI-A, SCI-B, or +// SCI-C +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for SCITXDA/B operation. +// Only one GPIO pin shoudl be enabled for SCIRXDA/B operation. +// Comment out other unwanted lines. +// +void +InitSciGpio() +{ + InitSciaGpio(); +#if DSP28_SCIB + InitScibGpio(); +#endif // if DSP28_SCIB + +#if DSP28_SCIC + InitScicGpio(); +#endif // if DSP28_SCIC +} + +// +// InitSciaGpio - This function initializes GPIO pins to function as SCI-A pins +// +void +InitSciaGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled disabled by the user. + // This will enable the pullups for the specified pins. + // + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA) + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA) + + // + // Set qualification for selected pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA) + + // + // Configure SCI-A pins using GPIO regs + // This specifies which of the possible GPIO pins will be SCI functional + // pins. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 to SCIRXDA + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 to SCITXDA + + EDIS; +} + +#if DSP28_SCIB +// +// InitScibGpio - This function initializes GPIO pins to function as SCI-B pins +// +void +InitScibGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; //Enable pull-up for GPIO9 (SCITXDB) + //GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; //Enable pull-up for GPIO14 (SCITXDB) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; //Enable pull-up for GPIO18 (SCITXDB) + //GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; //Enable pull-up for GPIO22 (SCITXDB) + + //GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; //Enable pull-up for GPIO11 (SCIRXDB) + //GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; //Enable pull-up for GPIO15 (SCIRXDB) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up for GPIO19 (SCIRXDB) + //GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; //Enable pull-up for GPIO23 (SCIRXDB) + + // + // Set qualification for selected pins to asynch only + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB) + + // + // Configure SCI-B pins using GPIO regs + // This specifies which of the possible GPIO pins will be SCI functional + // pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; //Configure GPIO9 to SCITXDB + //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; //Configure GPIO14 to SCITXDB + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; //Configure GPIO18 to SCITXDB + //GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; //Configure GPIO22 to SCITXDB + + //GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; //Configure GPIO11 for SCIRXDB + //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; //Configure GPIO15 for SCIRXDB + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; //Configure GPIO19 for SCIRXDB + //GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; //Configure GPIO23 for SCIRXDB + + EDIS; +} +#endif // if DSP28_SCIB + +#if DSP28_SCIC +// +// InitScicGpio - This function initializes GPIO pins to function as SCI-C pins +// +void +InitScicGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled disabled by the user. + // This will enable the pullups for the specified pins. + // + GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC) + GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC) + + // + // Set qualification for selected pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC) + + // + // Configure SCI-C pins using GPIO regs + // This specifies which of the possible GPIO pins will be SCI functional + // pins. + // + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 to SCIRXDC + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 to SCITXDC + + EDIS; +} +#endif // if DSP28_SCIC + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_Spi.c b/f2833x/common/source/DSP2833x_Spi.c new file mode 100644 index 0000000..b9fb3bf --- /dev/null +++ b/f2833x/common/source/DSP2833x_Spi.c @@ -0,0 +1,144 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:44 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.c +// +// TITLE: DSP2833x SPI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitSPI - This function initializes the SPI(s) to a known state. +// +void +InitSpi(void) +{ + // + // Initialize SPI-A/B/C/D + // +} + +// +// InitSpiGpio - This function initializes GPIO pins to function as SPI pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each SPI peripheral +// Only one GPIO pin should be enabled for SPISOMO operation. +// Only one GPIO pin should be enabled for SPISOMI operation. +// Only one GPIO pin should be enabled for SPICLKA operation. +// Only one GPIO pin should be enabled for SPISTEA operation. +// Comment out other unwanted lines. +// +void +InitSpiGpio() +{ + InitSpiaGpio(); +} + +// +// InitSpiaGpio - This function initializes GPIO poins to function as SPI pins +// +void +InitSpiaGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; //Enable pull-up on GPIO16 (SPISIMOA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; //Enable pull-up on GPIO17 (SPISOMIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; //Enable pull-up on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up on GPIO19 (SPISTEA) + + //GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; //Enable pull-up on GPIO54 (SPISIMOA) + //GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; //Enable pull-up on GPIO55 (SPISOMIA) + //GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; //Enable pull-up on GPIO56 (SPICLKA) + //GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; //Enable pull-up on GPIO57 (SPISTEA) + + // + // Set qualification for selected pins to asynch only + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) + + //GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA) + + // + // Configure SPI-A pins using GPIO regs + // This specifies which of the possible GPIO pins will be SPI + // functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA + + //GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA + //GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA + //GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA + //GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA + + EDIS; +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_SysCtrl.c b/f2833x/common/source/DSP2833x_SysCtrl.c new file mode 100644 index 0000000..0616399 --- /dev/null +++ b/f2833x/common/source/DSP2833x_SysCtrl.c @@ -0,0 +1,459 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 15, 2009 09:54:05 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.c +// +// TITLE: DSP2833x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: Example initialization of system resources. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped to a load and +// run address using the linker cmd file. +// +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); + #else + #pragma CODE_SECTION(InitFlash, "ramfuncs"); + #endif +#endif + +// +// InitSysCtrl - This function initializes the System Control registers to a +// known state. +// - Disables the watchdog +// - Set the PLLCR for proper SYSCLKOUT frequency +// - Set the pre-scaler for the high and low frequency peripheral clocks +// - Enable the clocks to the peripherals +// +void +InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + + // + // Initialize the PLL control: PLLCR and DIVSEL + // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h + // + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + // + // Initialize the peripheral clocks + // + InitPeripheralClocks(); +} + +// +// InitFlash - This function initializes the Flash Control registers +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +void +InitFlash(void) +{ + EALLOW; + + // + // Enable Flash Pipeline mode to improve performance + // of code executed from Flash. + // + FlashRegs.FOPT.bit.ENPIPE = 1; + + // + // CAUTION + // Minimum waitstates required for the flash operating + // at a given CPU rate must be characterized by TI. + // Refer to the datasheet for the latest information. + // +#if CPU_FRQ_150MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; +#endif + +#if CPU_FRQ_100MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; +#endif + // + // CAUTION + // ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED + // + FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; + FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; + EDIS; + + // + // Force a pipeline flush to ensure that the write to + // the last register configured occurs before returning. + // + asm(" RPT #7 || NOP"); +} + +// +// ServiceDog - This function resets the watchdog timer. +// Enable this function for using ServiceDog in the application +// +void +ServiceDog(void) +{ + EALLOW; + SysCtrlRegs.WDKEY = 0x0055; + SysCtrlRegs.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void +DisableDog(void) +{ + EALLOW; + SysCtrlRegs.WDCR= 0x0068; + EDIS; +} + +// +// InitPll - This function initializes the PLLCR register. +// +void +InitPll(Uint16 val, Uint16 divsel) +{ + // + // Make sure the PLL is not running in limp mode + // + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0) + { + // + // Missing external clock has been detected + // Replace this line with a call to an appropriate + // SystemShutdown(); function. + // + asm(" ESTOP0"); + } + + // + // DIVSEL MUST be 0 before PLLCR can be changed from + // 0x0000. It is set to 0 by an external reset XRSn + // This puts us in 1/4 + // + if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; + EDIS; + } + + // + // Change the PLLCR + // + if (SysCtrlRegs.PLLCR.bit.DIV != val) + { + EALLOW; + + // + // Before setting PLLCR turn off missing clock detect logic + // + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; + SysCtrlRegs.PLLCR.bit.DIV = val; + EDIS; + + // + // Optional: Wait for PLL to lock. + // During this time the CPU will switch to OSCCLK/2 until + // the PLL is stable. Once the PLL is stable the CPU will + // switch to the new PLL value. + // + // This time-to-lock is monitored by a PLL lock counter. + // + // Code is not required to sit and wait for the PLL to lock. + // However, if the code does anything that is timing critical, + // and requires the correct clock be locked, then it is best to + // wait until this switching has completed. + // + + // + // Wait for the PLL lock bit to be set. + // + + // + // The watchdog should be disabled before this loop, or fed within + // the loop via ServiceDog(). + // + + // + // Uncomment to disable the watchdog + // + DisableDog(); + + while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) + { + // + // Uncomment to service the watchdog + // + //ServiceDog(); + } + + EALLOW; + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; + EDIS; + } + + // + // If switching to 1/2 + // + if((divsel == 1)||(divsel == 2)) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel; + EDIS; + } + + // + // NOTE: ONLY USE THIS SETTING IF PLL IS BYPASSED (I.E. PLLCR = 0) OR OFF + // If switching to 1/1 + // * First go to 1/2 and let the power settle + // The time required will depend on the system, this is only an example + // * Then switch to 1/1 + // + if(divsel == 3) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 2; + DELAY_US(50L); + SysCtrlRegs.PLLSTS.bit.DIVSEL = 3; + EDIS; + } +} + +// +// InitPeripheralClocks - This function initializes the clocks to the +// peripheral modules. First the high and low clock prescalers are set +// Second the clocks are enabled to each peripheral. To reduce power, leave +// clocks to unused peripherals disabled +// +// Note: If a peripherals clock is not enabled then you cannot +// read or write to the registers for that peripheral +// +void +InitPeripheralClocks(void) +{ + EALLOW; + + // + // HISPCP/LOSPCP prescale register settings, normally it will be set to + // default values + // + SysCtrlRegs.HISPCP.all = 0x0001; + SysCtrlRegs.LOSPCP.all = 0x0002; + + // + // XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT + // XTIMCLK = SYSCLKOUT/2 + // + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + + // + // XCLKOUT = XTIMCLK/2 + // + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + // + // Enable XCLKOUT + // + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + + // + // Peripheral clock enables set for the selected peripherals. + // If you are not using a peripheral leave the clock off + // to save on power. + // + // Note: not all peripherals are available on all 2833x derivates. + // Refer to the datasheet for your particular device. + // + // This function is not written to be an example of efficient code. + // + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC + + // + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI + // reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC to + // function according to specification. The clocks to the ADC MUST be + // enabled before calling this function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + // + ADC_cal(); + + SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C + SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A + SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B + SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C + SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A + SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A + SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A + SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B + + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM + SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 + SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2 + SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3 + SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4 + SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5 + SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6 + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM + + SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3 + SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4 + SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5 + SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6 + SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1 + SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2 + SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1 + SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2 + + SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2 + + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK + SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock + + EDIS; +} + +// +// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with +// current password for the DSP. Returns 1 if unlock is successful. +// +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 +Uint16 +CsmUnlock() +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the + // DSP. + // + EALLOW; + CsmRegs.KEY0 = 0xFFFF; + CsmRegs.KEY1 = 0xFFFF; + CsmRegs.KEY2 = 0xFFFF; + CsmRegs.KEY3 = 0xFFFF; + CsmRegs.KEY4 = 0xFFFF; + CsmRegs.KEY5 = 0xFFFF; + CsmRegs.KEY6 = 0xFFFF; + CsmRegs.KEY7 = 0xFFFF; + EDIS; + + // + // Perform a dummy read of the password locations if they match the key + // values, the CSM will unlock + // + temp = CsmPwl.PSWD0; + temp = CsmPwl.PSWD1; + temp = CsmPwl.PSWD2; + temp = CsmPwl.PSWD3; + temp = CsmPwl.PSWD4; + temp = CsmPwl.PSWD5; + temp = CsmPwl.PSWD6; + temp = CsmPwl.PSWD7; + + // + // If the CSM unlocked, return succes, otherwise return failure. + // + if (CsmRegs.CSMSCR.bit.SECURE == 0) + { + return STATUS_SUCCESS; + } + else + { + return STATUS_FAIL; + } +} + +// +// End of file +// + diff --git a/f2833x/common/source/DSP2833x_Xintf.c b/f2833x/common/source/DSP2833x_Xintf.c new file mode 100644 index 0000000..aae1bc4 --- /dev/null +++ b/f2833x/common/source/DSP2833x_Xintf.c @@ -0,0 +1,334 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: August 16, 2007 11:06:26 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.c +// +// TITLE: DSP2833x Device External Interface Init & Support Functions. +// +// DESCRIPTION: +// +// Example initialization function for the external interface (XINTF). +// This example configures the XINTF to its default state. For an +// example of how this function being used refer to the +// examples/run_from_xintf project. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitXINTF - This function initializes the External Interface the default +// reset state. +// +// Do not modify the timings of the XINTF while running from the XINTF. Doing +// so can yield unpredictable results +// +void +InitXintf(void) +{ + // + // This shows how to write to the XINTF registers. The + // values used here are the default state after reset. + // Different hardware will require a different configuration. + // + + // + // For an example of an XINTF configuration used with the + // F28335 eZdsp, refer to the examples/run_from_xintf project. + // + + // + // Any changes to XINTF timing should only be made by code + // running outside of the XINTF. + // + + // + // All Zones + // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT + // + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + + // + // No write buffering + // + XintfRegs.XINTCNF2.bit.WRBUFF = 0; + + // + // XCLKOUT is enabled + // + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + + // + // XCLKOUT = XTIMCLK/2 + // + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + // + // Zone 0 + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + // + XintfRegs.XTIMING0.bit.XWRLEAD = 3; + XintfRegs.XTIMING0.bit.XWRACTIVE = 7; + XintfRegs.XTIMING0.bit.XWRTRAIL = 3; + + // + // Zone read timing + // + XintfRegs.XTIMING0.bit.XRDLEAD = 3; + XintfRegs.XTIMING0.bit.XRDACTIVE = 7; + XintfRegs.XTIMING0.bit.XRDTRAIL = 3; + + // + // double all Zone read/write lead/active/trail timing + // + XintfRegs.XTIMING0.bit.X2TIMING = 1; + + // + // Zone will sample XREADY signal + // + XintfRegs.XTIMING0.bit.USEREADY = 1; + XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous + + // + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + // + XintfRegs.XTIMING0.bit.XSIZE = 3; + + // + // Zone 6 + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + // + XintfRegs.XTIMING6.bit.XWRLEAD = 3; + XintfRegs.XTIMING6.bit.XWRACTIVE = 7; + XintfRegs.XTIMING6.bit.XWRTRAIL = 3; + + // + // Zone read timing + // + XintfRegs.XTIMING6.bit.XRDLEAD = 3; + XintfRegs.XTIMING6.bit.XRDACTIVE = 7; + XintfRegs.XTIMING6.bit.XRDTRAIL = 3; + + // + // double all Zone read/write lead/active/trail timing + // + XintfRegs.XTIMING6.bit.X2TIMING = 1; + + // + // Zone will sample XREADY signal + // + XintfRegs.XTIMING6.bit.USEREADY = 1; + XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous + + // + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + // + XintfRegs.XTIMING6.bit.XSIZE = 3; + + // + // Zone 7 + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + // + XintfRegs.XTIMING7.bit.XWRLEAD = 3; + XintfRegs.XTIMING7.bit.XWRACTIVE = 7; + XintfRegs.XTIMING7.bit.XWRTRAIL = 3; + + // + // Zone read timing + // + XintfRegs.XTIMING7.bit.XRDLEAD = 3; + XintfRegs.XTIMING7.bit.XRDACTIVE = 7; + XintfRegs.XTIMING7.bit.XRDTRAIL = 3; + + // + // double all Zone read/write lead/active/trail timing + // + XintfRegs.XTIMING7.bit.X2TIMING = 1; + + // + // Zone will sample XREADY signal + // + XintfRegs.XTIMING7.bit.USEREADY = 1; + XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous + + // + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + // + XintfRegs.XTIMING7.bit.XSIZE = 3; + + // + // Bank switching + // Assume Zone 7 is slow, so add additional BCYC cycles + // when ever switching from Zone 7 to another Zone. + // This will help avoid bus contention. + // + XintfRegs.XBANK.bit.BANK = 7; + XintfRegs.XBANK.bit.BCYC = 7; + EDIS; + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + InitXintf16Gpio(); + //InitXintf32Gpio(); + + asm(" RPT #7 || NOP"); +} + +// +// InitXintf32Gpio - +// +void +InitXintf32Gpio() +{ + EALLOW; + GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31 + GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30 + GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29 + GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28 + GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27 + GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26 + GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25 + GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24 + GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23 + GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22 + GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21 + GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20 + GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19 + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18 + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17 + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16 + + GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input + + InitXintf16Gpio(); +} + +// +// InitXintf16Gpio - +// +void +InitXintf16Gpio() +{ + EALLOW; + GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15 + GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14 + GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13 + GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12 + GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11 + GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10 + GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19 + GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0 + + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n + GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1 + GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2 + GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3 + GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4 + GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5 + GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6 + GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7 + + GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8 + GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9 + GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10 + GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11 + GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12 + GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13 + GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14 + GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15 + GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16 + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19 + + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY + GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0 + + GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0 + GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7 + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 + EDIS; +} + +// +// End of File +// + diff --git a/f2833x/common/source/DSP2833x_usDelay.asm b/f2833x/common/source/DSP2833x_usDelay.asm new file mode 100644 index 0000000..cf2d6ec --- /dev/null +++ b/f2833x/common/source/DSP2833x_usDelay.asm @@ -0,0 +1,118 @@ +;// TI File $Revision: /main/4 $ +;// Checkin $Date: July 30, 2007 10:28:57 $ +;//########################################################################### +;// +;// FILE: DSP2833x_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// +;// To use this function: +;// +;// 1 - update the CPU clock speed in the DSP2833x_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed +;// +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the DSP2833x_Examples.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// +;// extern void Delay(long LoopCount); +;// +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// +;// Or as follows (if count is less then 16-bits): +;// +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;// +;//########################################################################### +;// $TI Release: 2833x/2823x Header Files V1.32 $ +;// $Release Date: June 28, 2010 $ +;// $Copyright: +;// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + + .def _DSP28x_usDelay + + .cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro + %{ + %} + + .if __TI_COMPILER_VERSION__ + .if __TI_COMPILER_VERSION__ >= 15009000 + .sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer + .else + .sect "ramfuncs" ;;Used with compilers older than v15.9.0 + .endif + .endif + + .global __DSP28x_usDelay +_DSP28x_usDelay: + SUB ACC,#1 + BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/f2833x/common/targetConfigs/TMS320F28335.ccxml b/f2833x/common/targetConfigs/TMS320F28335.ccxml new file mode 100644 index 0000000..5081425 --- /dev/null +++ b/f2833x/common/targetConfigs/TMS320F28335.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/f2833x/docs/F2833x_DEV_USER_GUIDE.pdf b/f2833x/docs/F2833x_DEV_USER_GUIDE.pdf new file mode 100644 index 0000000..561e937 Binary files /dev/null and b/f2833x/docs/F2833x_DEV_USER_GUIDE.pdf differ diff --git a/f2833x/examples/adc_dma/.ccsproject b/f2833x/examples/adc_dma/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/adc_dma/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/adc_dma/.cproject b/f2833x/examples/adc_dma/.cproject new file mode 100644 index 0000000..4b4eb68 --- /dev/null +++ b/f2833x/examples/adc_dma/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/adc_dma/.project b/f2833x/examples/adc_dma/.project new file mode 100644 index 0000000..1eb5b72 --- /dev/null +++ b/f2833x/examples/adc_dma/.project @@ -0,0 +1,103 @@ + + + Example_2833xAdcToDMA + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_Adc.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Adc.c + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DMA.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DMA.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/adc_dma/Example_2833xAdcToDMA.c b/f2833x/examples/adc_dma/Example_2833xAdcToDMA.c new file mode 100644 index 0000000..0a777fd --- /dev/null +++ b/f2833x/examples/adc_dma/Example_2833xAdcToDMA.c @@ -0,0 +1,283 @@ +//########################################################################### +// +// FILE: Example_2833xAdcToDMA.c +// +// TITLE: ADC to DMA Example +// +//! \addtogroup f2833x_example_list +//!

ADC to DMA (adc_dma)

+//! +//! This ADC example uses ADC to convert 4 channels for each SOC received, +//! with total of 10 SOCs. +//! Each SOC initiates 4 conversions. +//! DMA is used to capture the data on each SEQ1_INT. DMA will re-sort +//! the data by channel sequentially, i.e. all channel0 data will be +//! together and all channel1 data will be together. +//! +//! \b Watch \b Variables \n +//! - DMABuf1 - DMA Buffer +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines for ADC start parameters +// +#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + // + // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + // + #define ADC_MODCLK 0x3 +#endif +#if (CPU_FRQ_100MHZ) + // + // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + // + #define ADC_MODCLK 0x2 +#endif + +// +// ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz +// +#define ADC_CKPS 0x1 + +#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks +#define AVG 1000 // Average sample limit +#define ZOFFSET 0x00 // Average Zero offset +#define BUF_SIZE 40 // Sample buffer size + +// +// Globals +// +Uint16 j=0; + +#pragma DATA_SECTION(DMABuf1,"DMARAML4"); +volatile Uint16 DMABuf1[40]; + +volatile Uint16 *DMADest; +volatile Uint16 *DMASource; +__interrupt void local_DINTCH1_ISR(void); + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Specific clock setting for this example + // + EALLOW; + SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK + EDIS; + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_DINTCH1_ISR; + EDIS; // Disable access to EALLOW protected registers + + IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1) + EnableInterrupts(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + + // + // Specific ADC setup for this example: + // + AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; + AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; // 0 Non-Cascaded Mode + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1; + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x0; + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x1; + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x2; + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x3; + + // + // Set up ADC to perform 4 conversions for every SOC + // + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3; + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Initialize DMA + // + DMAInitialize(); + + // + // Clear Table + // + for (i=0; i + + + + + diff --git a/f2833x/examples/adc_seq_ovd_test/.cproject b/f2833x/examples/adc_seq_ovd_test/.cproject new file mode 100644 index 0000000..78d24b6 --- /dev/null +++ b/f2833x/examples/adc_seq_ovd_test/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/adc_seq_ovd_test/.project b/f2833x/examples/adc_seq_ovd_test/.project new file mode 100644 index 0000000..9ae3915 --- /dev/null +++ b/f2833x/examples/adc_seq_ovd_test/.project @@ -0,0 +1,98 @@ + + + Example_2833xAdcSeq_ovdTest + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_Adc.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Adc.c + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.c b/f2833x/examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.c new file mode 100644 index 0000000..d4f8dad --- /dev/null +++ b/f2833x/examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.c @@ -0,0 +1,339 @@ +//########################################################################### +// +// FILE: Example_2833xAdcSeq_ovdTest.c +// +// TITLE: ADC Seq Override Mode Test Example +// +//! \addtogroup f2833x_example_list +//!

ADC Seq Override Mode Test (add_seq_ovd_test)

+//! +//! In this example, channel A0 is converted forever and logged in a buffer +//! (SampleTable) using sequencer1 in sequence override mode. Sequencer is +//! Sequential mode with sample rate of 1/(3*40ns) = 8.3 MHZ. +//! +//! \b Watch \b Variables \n +//! - SampleTable - Log of converted values. +//! - GPIO34 - Toggles on every ADC sequencer flag +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines +// + +// +// Determine when the shift to right justify the data takes place +// Only one of these should be defined as 1. +// The other two should be defined as 0. +// +#define POST_SHIFT 0 // Shift results after the entire sample table is full + +// +// Shift results as the data is taken from the results regsiter +// +#define INLINE_SHIFT 1 + +#define NO_SHIFT 0 // Do not shift the results + +// +// ADC start parameters +// +#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + // + // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + // + #define ADC_MODCLK 0x3 +#endif +#if (CPU_FRQ_100MHZ) + // + // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + // + #define ADC_MODCLK 0x2 +#endif + +// +// ADC module clock = HSPCLK/1 = 25.5MHz/(1) = 25.0 MHz +// +#define ADC_CKPS 0x0 + +// +// S/H width in ADC module periods = 2 ADC cycle +// +#define ADC_SHCLK 0x1 + +#define AVG 1000 // Average sample limit +#define ZOFFSET 0x00 // Average Zero offset +#define BUF_SIZE 1024 // Sample buffer size + +// +// Globals +// +Uint16 SampleTable[BUF_SIZE]; + +// +// Main +// +void main(void) +{ + Uint16 i; + Uint16 array_index; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Specific clock setting for this example: + // + EALLOW; + SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK + EDIS; + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Enable the pin GPIO34 as output + // + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO pin + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // Output pin + EDIS; + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + + // + // Specific ADC setup for this example: + // + + // + // Sequential mode: Sample rate = 1/[(2+ACQ_PS)*ADC clock in ns] + // = 1/(3*40ns) =8.3MHz (for 150 MHz SYSCLKOUT) + // = 1/(3*80ns) =4.17MHz (for 100 MHz SYSCLKOUT) + // If Simultaneous mode enabled: Sample rate=1/[(3+ACQ_PS)*ADC clock in ns] + // + AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; + + AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; + AdcRegs.ADCTRL1.bit.CONT_RUN = 1; // Setup continuous run + + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 1; // Enable Sequencer override feature + AdcRegs.ADCCHSELSEQ1.all = 0x0; // Initialize all ADC channel selects to A0 + AdcRegs.ADCCHSELSEQ2.all = 0x0; + AdcRegs.ADCCHSELSEQ3.all = 0x0; + AdcRegs.ADCCHSELSEQ4.all = 0x0; + + // + // convert and store in 8 results registers + // + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x7; + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Clear SampleTable + // + for (i=0; i>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT1)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT2)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT3)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT4)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT5)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT6)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT7)>>4); + + #endif //-- INLINE_SHIFT + + #if NO_SHIFT || POST_SHIFT + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT0)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT1)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT2)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT3)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT4)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT5)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT6)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT7)); + #endif //-- NO_SHIFT || POST_SHIFT + + while (AdcRegs.ADCST.bit.INT_SEQ1== 0) + { + + } + + // + // Clear GPIO34 for monitoring -optional + // + GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1; + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; + + #if INLINE_SHIFT + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT8)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT9)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT10)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT11)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT12)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT13)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT14)>>4); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT15)>>4); + + #endif //-- INLINE_SHIFT + + #if NO_SHIFT || POST_SHIFT + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT8)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT9)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT10)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT11)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT12)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT13)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT14)); + SampleTable[array_index++]= ( (AdcRegs.ADCRESULT15)); + #endif // -- NO_SHIFT || POST_SHIFT + } + + #if POST_SHIFT + // + // For post shifting, shift the ADC results + // in the SampleTable buffer after the buffer is full. + // + for (i=0; i>4); + } + #endif // -- POST_SHIFT + + // + // Clear GPIO34 for monitoring -optional + // + GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1; + } +} + +// +// End of File +// + diff --git a/f2833x/examples/adc_seqmode_test/.ccsproject b/f2833x/examples/adc_seqmode_test/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/adc_seqmode_test/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/adc_seqmode_test/.cproject b/f2833x/examples/adc_seqmode_test/.cproject new file mode 100644 index 0000000..1f5945a --- /dev/null +++ b/f2833x/examples/adc_seqmode_test/.cproject @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/adc_seqmode_test/.project b/f2833x/examples/adc_seqmode_test/.project new file mode 100644 index 0000000..3959b4d --- /dev/null +++ b/f2833x/examples/adc_seqmode_test/.project @@ -0,0 +1,98 @@ + + + Example_2833xAdcSeqModeTest + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_Adc.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Adc.c + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c b/f2833x/examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c new file mode 100644 index 0000000..529cb18 --- /dev/null +++ b/f2833x/examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c @@ -0,0 +1,202 @@ +//########################################################################### +// +// FILE: Example_2833xAdcSeqModeTest.c +// +// TITLE: ADC Seq Mode Test Example +// +//! \addtogroup f2833x_example_list +//!

ADC Seq Mode Test (adc_seqmode_test)

+//! +//! In this example, channel A0 is converted forever and logged in a buffer +//! (SampleTable) +//! +//! \b Watch \b Variables \n +//! - SampleTable - Log of converted values +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines for ADC start parameters +// +#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + // + // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + // + #define ADC_MODCLK 0x3 +#endif +#if (CPU_FRQ_100MHZ) + // + // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + // + #define ADC_MODCLK 0x2 +#endif + +// +// ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz +// +#define ADC_CKPS 0x1 + +#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks +#define AVG 1000 // Average sample limit +#define ZOFFSET 0x00 // Average Zero offset +#define BUF_SIZE 2048 // Sample buffer size + +// +// Globals +// +Uint16 SampleTable[BUF_SIZE]; + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Specific clock setting for this example + // + EALLOW; + SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK + EDIS; + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + + // + // Specific ADC setup for this example: + // + AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; + AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; + AdcRegs.ADCTRL1.bit.CONT_RUN = 1; // Setup continuous run + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Clear SampleTable + // + for (i=0; i>4) ); + } + } +} + +// +// End of File +// + diff --git a/f2833x/examples/adc_soc/.ccsproject b/f2833x/examples/adc_soc/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/adc_soc/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/adc_soc/.cproject b/f2833x/examples/adc_soc/.cproject new file mode 100644 index 0000000..3153b5f --- /dev/null +++ b/f2833x/examples/adc_soc/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/adc_soc/.project b/f2833x/examples/adc_soc/.project new file mode 100644 index 0000000..5758a33 --- /dev/null +++ b/f2833x/examples/adc_soc/.project @@ -0,0 +1,98 @@ + + + Example_2833xAdcSoc + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_Adc.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Adc.c + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/adc_soc/Example_2833xAdcSoc.c b/f2833x/examples/adc_soc/Example_2833xAdcSoc.c new file mode 100644 index 0000000..9f5b413 --- /dev/null +++ b/f2833x/examples/adc_soc/Example_2833xAdcSoc.c @@ -0,0 +1,242 @@ +//########################################################################### +// +// FILE: Example_2833xAdcSoc.c +// +// TITLE: ADC Start of Conversion Example +// +//! \addtogroup f2833x_example_list +//!

ADC Start of Conversion (adc_soc)

+//! +//! This ADC example uses ePWM1 to generate a periodic ADC SOC on SEQ1. +//! Two channels are converted, ADCINA3 and ADCINA2. +//! +//! \b Watch \b Variables \n +//! - Voltage1[10] - Last 10 ADCRESULT0 values +//! - Voltage2[10] - Last 10 ADCRESULT1 values +//! - ConversionCount - Current result number 0-9 +//! - LoopCount - Idle loop counter +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +__interrupt void adc_isr(void); + +// +// Globals +// +Uint16 LoopCount; +Uint16 ConversionCount; +Uint16 Voltage1[10]; +Uint16 Voltage2[10]; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + EALLOW; + #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + // + // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + // + #define ADC_MODCLK 0x3 + #endif + #if (CPU_FRQ_100MHZ) + // + // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + // + #define ADC_MODCLK 0x2 + #endif + EDIS; + + // + // Define ADCCLK clock frequency ( less than or equal to 25 MHz ) + // Assuming InitSysCtrl() has set SYSCLKOUT to 150 MHz + // + EALLOW; + SysCtrlRegs.HISPCP.all = ADC_MODCLK; + EDIS; + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected register + PieVectTable.ADCINT = &adc_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + InitAdc(); // For this example, init the ADC + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Enable ADCINT in PIE + // + PieCtrlRegs.PIEIER1.bit.INTx6 = 1; + IER |= M_INT1; // Enable CPU Interrupt 1 + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + LoopCount = 0; + ConversionCount = 0; + + // + // Configure ADC + // + AdcRegs.ADCMAXCONV.all = 0x0001; // Setup 2 conv's on SEQ1 + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x3; // Setup ADCINA3 as 1st SEQ1 conv. + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x2; // Setup ADCINA2 as 2nd SEQ1 conv. + + // + // Enable SOCA from ePWM to start SEQ1 + // + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; + + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS) + + // + // Assumes ePWM1 clock is already enabled in InitSysCtrl(); + // + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event + EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value + EPwm1Regs.TBPRD = 0xFFFF; // Set period for ePWM1 + EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start + + // + // Wait for ADC interrupt + // + for(;;) + { + LoopCount++; + } +} + +// +// adc_isr - +// +__interrupt void +adc_isr(void) +{ + Voltage1[ConversionCount] = AdcRegs.ADCRESULT0 >>4; + Voltage2[ConversionCount] = AdcRegs.ADCRESULT1 >>4; + + // + // If 40 conversions have been logged, start over + // + if(ConversionCount == 9) + { + ConversionCount = 0; + } + else + { + ConversionCount++; + } + + // + // Reinitialize for next ADC sequence + // + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + + return; +} + +// +// End of File +// + diff --git a/f2833x/examples/cpu_timer/.ccsproject b/f2833x/examples/cpu_timer/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/cpu_timer/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/cpu_timer/.cproject b/f2833x/examples/cpu_timer/.cproject new file mode 100644 index 0000000..c428324 --- /dev/null +++ b/f2833x/examples/cpu_timer/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/cpu_timer/.project b/f2833x/examples/cpu_timer/.project new file mode 100644 index 0000000..75b508e --- /dev/null +++ b/f2833x/examples/cpu_timer/.project @@ -0,0 +1,98 @@ + + + Example_2833xCpuTimer + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/cpu_timer/Example_2833xCpuTimer.c b/f2833x/examples/cpu_timer/Example_2833xCpuTimer.c new file mode 100644 index 0000000..a207b5a --- /dev/null +++ b/f2833x/examples/cpu_timer/Example_2833xCpuTimer.c @@ -0,0 +1,237 @@ +//########################################################################### +// +// FILE: Example_2833xCpuTimer.c +// +// TITLE: Cpu Timer Example +// +//! \addtogroup f2833x_example_list +//!

Cpu Timer (cpu_timer)

+//! +//! This example configures CPU Timer0, 1, and 2 and increments +//! a counter each time the timers asserts an interrupt. +//! +//! \b Watch \b Variables \n +//! - CputTimer0.InterruptCount +//! - CpuTimer1.InterruptCount +//! - CpuTimer2.InterruptCount +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototype statements +// +__interrupt void cpu_timer0_isr(void); +__interrupt void cpu_timer1_isr(void); +__interrupt void cpu_timer2_isr(void); + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT0 = &cpu_timer0_isr; + PieVectTable.XINT13 = &cpu_timer1_isr; + PieVectTable.TINT2 = &cpu_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize the Device Peripheral. This function can be + // found in DSP2833x_CpuTimers.c + // + InitCpuTimers(); // For this example, only initialize the Cpu Timers + + #if (CPU_FRQ_150MHZ) + // + // Configure CPU-Timer 0, 1, and 2 to interrupt every second: + // 150MHz CPU Freq, 1 second Period (in uSeconds) + // + ConfigCpuTimer(&CpuTimer0, 150, 1000000); + ConfigCpuTimer(&CpuTimer1, 150, 1000000); + ConfigCpuTimer(&CpuTimer2, 150, 1000000); + #endif + + #if (CPU_FRQ_100MHZ) + // + // Configure CPU-Timer 0, 1, and 2 to interrupt every second: + // 100MHz CPU Freq, 1 second Period (in uSeconds) + // + ConfigCpuTimer(&CpuTimer0, 100, 1000000); + ConfigCpuTimer(&CpuTimer1, 100, 1000000); + ConfigCpuTimer(&CpuTimer2, 100, 1000000); + #endif + + // + // To ensure precise timing, use write-only instructions to write to the + // entire register. Therefore, if any of the configuration bits are changed + // in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the + // below settings must also be updated. + // + CpuTimer0Regs.TCR.all = 0x4000; //write-only instruction to set TSS bit = 0 + CpuTimer1Regs.TCR.all = 0x4000; //write-only instruction to set TSS bit = 0 + CpuTimer2Regs.TCR.all = 0x4000; //write-only instruction to set TSS bit = 0 + + // + // Step 5. User specific code, enable interrupts + // + + // + // Enable CPU int1 which is connected to CPU-Timer 0, CPU int13 + // which is connected to CPU-Timer 1, and CPU int 14, which is connected + // to CPU-Timer 2: + // + IER |= M_INT1; + IER |= M_INT13; + IER |= M_INT14; + + // + // Enable TINT0 in the PIE: Group 1 interrupt 7 + // + PieCtrlRegs.PIEIER1.bit.INTx7 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events: + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional): + // + for(;;); +} + +// +// cpu_timer0_isr - +// +__interrupt void +cpu_timer0_isr(void) +{ + CpuTimer0.InterruptCount++; + + // + // Acknowledge this interrupt to receive more interrupts from group 1 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +// +// cpu_timer1_isr - +// +__interrupt void +cpu_timer1_isr(void) +{ + CpuTimer1.InterruptCount++; + + // + // The CPU acknowledges the interrupt. + // + EDIS; +} + +// +// cpu_timer2_isr - +// +__interrupt void +cpu_timer2_isr(void) +{ + EALLOW; + CpuTimer2.InterruptCount++; + + // + // The CPU acknowledges the interrupt. + // + EDIS; +} + +// +// End of File +// + diff --git a/f2833x/examples/dma_ram_to_ram/.ccsproject b/f2833x/examples/dma_ram_to_ram/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/dma_ram_to_ram/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/dma_ram_to_ram/.cproject b/f2833x/examples/dma_ram_to_ram/.cproject new file mode 100644 index 0000000..9e030c9 --- /dev/null +++ b/f2833x/examples/dma_ram_to_ram/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/dma_ram_to_ram/.project b/f2833x/examples/dma_ram_to_ram/.project new file mode 100644 index 0000000..be5e749 --- /dev/null +++ b/f2833x/examples/dma_ram_to_ram/.project @@ -0,0 +1,103 @@ + + + Example_2833xDMA_ram_to_ram + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_Adc.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Adc.c + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DMA.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DMA.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/dma_ram_to_ram/Example_2833xDMA_ram_to_ram.c b/f2833x/examples/dma_ram_to_ram/Example_2833xDMA_ram_to_ram.c new file mode 100644 index 0000000..5cfc577 --- /dev/null +++ b/f2833x/examples/dma_ram_to_ram/Example_2833xDMA_ram_to_ram.c @@ -0,0 +1,235 @@ +//########################################################################### +// +// FILE: Example_2833xDMA_ram_to_ram.c +// +// TITLE: DMA Ram to Ram Example +// +//! \addtogroup f2833x_example_list +//!

DMA Ram to Ram (dma_ram_to_ram)

+//! +//! This example will perform a block copy from L5 SARAM to L4 SARAM of 1024 +//! words. Transfer will be started by Timer0. Will use 32-bit data size to +//! decrease the transfer time. +//! +//! \b Watch \b Variables \n +//! - DMABuf1 +//! - DMABuf2 +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines +// +#define BUF_SIZE 1024 // Sample buffer size + +// +// DMA Defines +// +#define CH1_TOTAL DATA_POINTS_PER_CHANNEL +#define CH1_WORDS_PER_BURST ADC_CHANNELS_TO_CONVERT + +#pragma DATA_SECTION(DMABuf1,"DMARAML4"); +#pragma DATA_SECTION(DMABuf2,"DMARAML5"); + +volatile Uint16 DMABuf1[1024]; +volatile Uint16 DMABuf2[1024]; + +volatile Uint16 *DMADest; +volatile Uint16 *DMASource; + +// +// Function Prototypes +// +__interrupt void local_DINTCH1_ISR(void); + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_DINTCH1_ISR; + EDIS; // Disable access to EALLOW protected registers + + IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1) + EnableInterrupts(); + CpuTimer0Regs.TCR.bit.TSS = 1; //Stop Timer0 for now + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Initialize DMA + // + DMAInitialize(); + + // + // Initialize Tables + // + for (i=0; i + + + + + diff --git a/f2833x/examples/dma_xintf_to_ram/.cproject b/f2833x/examples/dma_xintf_to_ram/.cproject new file mode 100644 index 0000000..38c8296 --- /dev/null +++ b/f2833x/examples/dma_xintf_to_ram/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/dma_xintf_to_ram/.project b/f2833x/examples/dma_xintf_to_ram/.project new file mode 100644 index 0000000..f160f44 --- /dev/null +++ b/f2833x/examples/dma_xintf_to_ram/.project @@ -0,0 +1,108 @@ + + + Example_2833xDMA_xintf_to_ram + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_Adc.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Adc.c + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DMA.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DMA.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_Xintf.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Xintf.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/dma_xintf_to_ram/Example_2833xDMA_xintf_to_ram.c b/f2833x/examples/dma_xintf_to_ram/Example_2833xDMA_xintf_to_ram.c new file mode 100644 index 0000000..c428f0f --- /dev/null +++ b/f2833x/examples/dma_xintf_to_ram/Example_2833xDMA_xintf_to_ram.c @@ -0,0 +1,326 @@ +//########################################################################### +// +// FILE: Example_2833xDMA_xintf_to_ram.c +// +// TITLE: DMA XINTF to RAM Example +// +//! \addtogroup f2833x_example_list +//!

DMA XINTF to RAM (dma_xintf_to_ram)

+//! +//! This example will perform a block copy of 1024 words from Zone 7 XINTF +//! (DMABuf2) to L4 SARAM (DMABuf1). +//! Transfer will be started by Timer0. +//! We will use 32-bit DMA datasize. Note this is independent from the XINTF +//! data width which is x16. +//! +//! \b Watch \b Variables \n +//! - DMABuf1 +//! - DMABuf2 +// +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines +// +#define BUF_SIZE 1024 // Sample buffer size + +#pragma DATA_SECTION(DMABuf1,"DMARAML4"); +#pragma DATA_SECTION(DMABuf2,"ZONE7DATA"); + +volatile Uint16 DMABuf1[BUF_SIZE]; +volatile Uint16 DMABuf2[BUF_SIZE]; + +volatile Uint16 *DMADest; +volatile Uint16 *DMASource; + +// +// Functions Prototypes +// +__interrupt void local_DINTCH1_ISR(void); +void init_zone7(void); + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_DINTCH1_ISR; + EDIS; // Disable access to EALLOW protected registers + + IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1) + EnableInterrupts(); + CpuTimer0Regs.TCR.bit.TSS = 1; //Stop Timer0 for now + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Initialize DMA + // + DMAInitialize(); + init_zone7(); + + // + // Initialize Tables + // + for (i=0; i + + + + + diff --git a/f2833x/examples/ecan_a_to_b_xmit/.cproject b/f2833x/examples/ecan_a_to_b_xmit/.cproject new file mode 100644 index 0000000..c6fbd92 --- /dev/null +++ b/f2833x/examples/ecan_a_to_b_xmit/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/ecan_a_to_b_xmit/.project b/f2833x/examples/ecan_a_to_b_xmit/.project new file mode 100644 index 0000000..a4c72b6 --- /dev/null +++ b/f2833x/examples/ecan_a_to_b_xmit/.project @@ -0,0 +1,98 @@ + + + Example_2833xEcanA_to_B_Xmit + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_ECan.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ECan.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/ecan_a_to_b_xmit/Example_2833xEcanA_to_B_Xmit.c b/f2833x/examples/ecan_a_to_b_xmit/Example_2833xEcanA_to_B_Xmit.c new file mode 100644 index 0000000..9380bf2 --- /dev/null +++ b/f2833x/examples/ecan_a_to_b_xmit/Example_2833xEcanA_to_B_Xmit.c @@ -0,0 +1,220 @@ +//########################################################################### +// +// FILE: Example_2833xEcanA_to_B_Xmit.c +// +// TITLE: eCAN-A to eCAN-B Transmit Loop Example +// +//! \addtogroup f2833x_example_list +//!

eCAN-A to eCAN-B Transmit Loop (ecan_a_to_b_xmit)

+//! +//! This example TRANSMITS data to another CAN module using MAILBOX5 +//! This program could either loop forever or transmit "n" # of times, +//! where "n" is the TXCOUNT value. \n +//! +//! This example can be used to check CAN-A and CAN-B. Since CAN-B is +//! initialized in DSP2833x_ECan.c, it will acknowledge all frames +//! transmitted by the node on which this code runs. Both CAN ports of +//! the 2833x DSP need to be connected to each other (via CAN transceivers) +//! +//! \b External \b Connections \n +//! - eCANA is on GPIO31 (CANTXA) and GPIO30 (CANRXA) +//! - eCANB is on GPIO8 (CANTXB) and GPIO10 (CANRXB) +//! - Connect eCANA to eCANB via CAN transceivers +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines +// +#define TXCOUNT 100 // Transmission will take place (TXCOUNT) times + +// +// Globals +// +long i; +long loopcount = 0; + +// +// Main +// +void main(void) +{ + // + // Create a shadow register structure for the CAN control registers. + // This is needed, since only 32-bit access is allowed to these registers. + // 16-bit access to these registers could potentially corrupt the register + // contents or return false data. + // + struct ECAN_REGS ECanaShadow; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Just initialize eCAN pins for this example + // This function is in DSP2833x_ECan.c + // + InitECanGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + + // + // No interrupts used in this example. + // + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // In this case just initialize eCAN-A and eCAN-B + // This function is in DSP2833x_ECan.c + // + InitECan(); + + // + // Step 5. User specific code + // + + // + // Write to the MSGID field + // + ECanaMboxes.MBOX25.MSGID.all = 0x95555555; // Extended Identifier + + // + // Configure Mailbox under test as a Transmit mailbox + // + ECanaShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanaShadow.CANMD.bit.MD25 = 0; + ECanaRegs.CANMD.all = ECanaShadow.CANMD.all; + + // + // Enable Mailbox under test + // + ECanaShadow.CANME.all = ECanaRegs.CANME.all; + ECanaShadow.CANME.bit.ME25 = 1; + ECanaRegs.CANME.all = ECanaShadow.CANME.all; + + // + // Write to DLC field in Master Control reg + // + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8; + + // + // Write to the mailbox RAM field + // + ECanaMboxes.MBOX25.MDL.all = 0x55555555; + ECanaMboxes.MBOX25.MDH.all = 0x55555555; + + // + // Begin transmitting + // + for(i=0; i < TXCOUNT; i++) + { + ECanaShadow.CANTRS.all = 0; + ECanaShadow.CANTRS.bit.TRS25 = 1; // Set TRS for mailbox under test + ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all; + + do + { + ECanaShadow.CANTA.all = ECanaRegs.CANTA.all; + } while(ECanaShadow.CANTA.bit.TA25 == 0 );// Wait for TA5 bit to be set + + ECanaShadow.CANTA.all = 0; + ECanaShadow.CANTA.bit.TA25 = 1; // Clear TA5 + ECanaRegs.CANTA.all = ECanaShadow.CANTA.all; + + loopcount ++; + } + __asm(" ESTOP0"); // Stop here +} + +// +// End of File +// + diff --git a/f2833x/examples/ecan_back2back/.ccsproject b/f2833x/examples/ecan_back2back/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/ecan_back2back/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/ecan_back2back/.cproject b/f2833x/examples/ecan_back2back/.cproject new file mode 100644 index 0000000..777ae5e --- /dev/null +++ b/f2833x/examples/ecan_back2back/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/ecan_back2back/.project b/f2833x/examples/ecan_back2back/.project new file mode 100644 index 0000000..7249263 --- /dev/null +++ b/f2833x/examples/ecan_back2back/.project @@ -0,0 +1,98 @@ + + + Example_2833xECanBack2Back + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_ECan.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ECan.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/ecan_back2back/Example_2833xECanBack2Back.c b/f2833x/examples/ecan_back2back/Example_2833xECanBack2Back.c new file mode 100644 index 0000000..13fc6b1 --- /dev/null +++ b/f2833x/examples/ecan_back2back/Example_2833xECanBack2Back.c @@ -0,0 +1,378 @@ +//########################################################################### +// +// FILE: Example_2833xECanBack2Back.c +// +// TITLE: eCAN back to back Example +// +//! \addtogroup f2833x_example_list +//!

eCAN back to back (ecan_back2back)

+//! +//! This example tests eCAN by transmitting data back-to-back at high speed +//! without stopping. The received data is verified. Any error is flagged. +//! MBX0 transmits to MBX16, MBX1 transmits to MBX17 and so on.... \n +//! This program illustrates the use of self-test mode +//! +//! This example uses the self-test mode of the CAN module. i.e. the +//! transmission/reception happens within the module itself (even the required +//! ACKnowldege is generated internally in the module). Therefore, there is no +//! need for a CAN transceiver to run this particular test case and no activity +//! will be seen in the CAN pins/bus. Because everything is internal, there is +//! no need for a 120-ohm termination resistor. Note that a real-world CAN +//! application needs a CAN transceiver and termination resistors on both ends +//! of the bus. +//! +//! \b Watch \b Variables \n +//! - PassCount +//! - ErrorCount +//! - MessageReceivedCount +// +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +void mailbox_check(int32 T1, int32 T2, int32 T3); +void mailbox_read(int16 i); + +// +// Globals +// +Uint32 ErrorCount; +Uint32 PassCount; +Uint32 MessageReceivedCount; + +Uint32 TestMbox1 = 0; +Uint32 TestMbox2 = 0; +Uint32 TestMbox3 = 0; + +// +// Main +// +void main(void) +{ + Uint16 j; + + // + // eCAN control registers require read/write access using 32-bits. Thus we + // will create a set of shadow registers for this example. These shadow + // registers will be used to make sure the access is 32-bits and not 16. + // + struct ECAN_REGS ECanaShadow; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this example, configure CAN pins using GPIO regs here + // This function is found in DSP2833x_ECan.c + // + InitECanGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code, enable interrupts: + // + MessageReceivedCount = 0; + ErrorCount = 0; + PassCount = 0; + + // + // Initialize eCAN-A module + // + InitECana(); + + // + // Mailboxes can be written to 16-bits or 32-bits at a time + // Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 15 + // + ECanaMboxes.MBOX0.MSGID.all = 0x9555AAA0; + ECanaMboxes.MBOX1.MSGID.all = 0x9555AAA1; + ECanaMboxes.MBOX2.MSGID.all = 0x9555AAA2; + ECanaMboxes.MBOX3.MSGID.all = 0x9555AAA3; + ECanaMboxes.MBOX4.MSGID.all = 0x9555AAA4; + ECanaMboxes.MBOX5.MSGID.all = 0x9555AAA5; + ECanaMboxes.MBOX6.MSGID.all = 0x9555AAA6; + ECanaMboxes.MBOX7.MSGID.all = 0x9555AAA7; + ECanaMboxes.MBOX8.MSGID.all = 0x9555AAA8; + ECanaMboxes.MBOX9.MSGID.all = 0x9555AAA9; + ECanaMboxes.MBOX10.MSGID.all = 0x9555AAAA; + ECanaMboxes.MBOX11.MSGID.all = 0x9555AAAB; + ECanaMboxes.MBOX12.MSGID.all = 0x9555AAAC; + ECanaMboxes.MBOX13.MSGID.all = 0x9555AAAD; + ECanaMboxes.MBOX14.MSGID.all = 0x9555AAAE; + ECanaMboxes.MBOX15.MSGID.all = 0x9555AAAF; + + // + // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31 + // + ECanaMboxes.MBOX16.MSGID.all = 0x9555AAA0; + ECanaMboxes.MBOX17.MSGID.all = 0x9555AAA1; + ECanaMboxes.MBOX18.MSGID.all = 0x9555AAA2; + ECanaMboxes.MBOX19.MSGID.all = 0x9555AAA3; + ECanaMboxes.MBOX20.MSGID.all = 0x9555AAA4; + ECanaMboxes.MBOX21.MSGID.all = 0x9555AAA5; + ECanaMboxes.MBOX22.MSGID.all = 0x9555AAA6; + ECanaMboxes.MBOX23.MSGID.all = 0x9555AAA7; + ECanaMboxes.MBOX24.MSGID.all = 0x9555AAA8; + ECanaMboxes.MBOX25.MSGID.all = 0x9555AAA9; + ECanaMboxes.MBOX26.MSGID.all = 0x9555AAAA; + ECanaMboxes.MBOX27.MSGID.all = 0x9555AAAB; + ECanaMboxes.MBOX28.MSGID.all = 0x9555AAAC; + ECanaMboxes.MBOX29.MSGID.all = 0x9555AAAD; + ECanaMboxes.MBOX30.MSGID.all = 0x9555AAAE; + ECanaMboxes.MBOX31.MSGID.all = 0x9555AAAF; + + // + // Configure Mailboxes 0-15 as Tx, 16-31 as Rx + // Since this write is to the entire register (instead of a bit field) + // a shadow register is not required. + // + ECanaRegs.CANMD.all = 0xFFFF0000; + + // + // Enable all Mailboxes + // Since this write is to the entire register (instead of a bit field) + // a shadow register is not required. + // + ECanaRegs.CANME.all = 0xFFFFFFFF; + + // + // Specify that 8 bits will be sent/received + // + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8; + + // + // Write to the mailbox RAM field of MBOX0 - 15 + // + ECanaMboxes.MBOX0.MDL.all = 0x9555AAA0; + ECanaMboxes.MBOX0.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX1.MDL.all = 0x9555AAA1; + ECanaMboxes.MBOX1.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX2.MDL.all = 0x9555AAA2; + ECanaMboxes.MBOX2.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX3.MDL.all = 0x9555AAA3; + ECanaMboxes.MBOX3.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX4.MDL.all = 0x9555AAA4; + ECanaMboxes.MBOX4.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX5.MDL.all = 0x9555AAA5; + ECanaMboxes.MBOX5.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX6.MDL.all = 0x9555AAA6; + ECanaMboxes.MBOX6.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX7.MDL.all = 0x9555AAA7; + ECanaMboxes.MBOX7.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX8.MDL.all = 0x9555AAA8; + ECanaMboxes.MBOX8.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX9.MDL.all = 0x9555AAA9; + ECanaMboxes.MBOX9.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX10.MDL.all = 0x9555AAAA; + ECanaMboxes.MBOX10.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX11.MDL.all = 0x9555AAAB; + ECanaMboxes.MBOX11.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX12.MDL.all = 0x9555AAAC; + ECanaMboxes.MBOX12.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX13.MDL.all = 0x9555AAAD; + ECanaMboxes.MBOX13.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX14.MDL.all = 0x9555AAAE; + ECanaMboxes.MBOX14.MDH.all = 0x89ABCDEF; + + ECanaMboxes.MBOX15.MDL.all = 0x9555AAAF; + ECanaMboxes.MBOX15.MDH.all = 0x89ABCDEF; + + // + // Since this write is to the entire register (instead of a bit field) + // a shadow register is not required. + // + EALLOW; + ECanaRegs.CANMIM.all = 0xFFFFFFFF; + + // + // Configure the eCAN for self test mode + // Enable the enhanced features of the eCAN. + // + EALLOW; + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.STM = 1; // Configure CAN for self-test mode + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + EDIS; + + // + // Begin transmitting + // + for(;;) + { + ECanaRegs.CANTRS.all = 0x0000FFFF; //Set TRS for all transmit mailboxes + while(ECanaRegs.CANTA.all != 0x0000FFFF ) + { + + } // Wait for all TAn bits to be set + + ECanaRegs.CANTA.all = 0x0000FFFF; // Clear all TAn + MessageReceivedCount++; + + // + // Read from Receive mailboxes and begin checking for data + // + for(j=16; j<32; j++) // Read & check 16 mailboxes + { + // + // This func reads the indicated mailbox data + // + mailbox_read(j); + + // + // Checks the received data + // + mailbox_check(TestMbox1,TestMbox2,TestMbox3); + } + } +} + +// +// mailbox_read - This function reads out the contents of the indicated +// by the Mailbox number (MBXnbr). +// +void +mailbox_read(int16 MBXnbr) +{ + volatile struct MBOX *Mailbox; + Mailbox = &ECanaMboxes.MBOX0 + MBXnbr; + TestMbox1 = Mailbox->MDL.all; // = 0x9555AAAn (n is the MBX number) + TestMbox2 = Mailbox->MDH.all; // = 0x89ABCDEF (a constant) + TestMbox3 = Mailbox->MSGID.all; // = 0x9555AAAn (n is the MBX number) +} // MSGID of a rcv MBX is transmitted as the MDL data. + +// +// mailbox_check - +// +void +mailbox_check(int32 T1, int32 T2, int32 T3) +{ + if((T1 != T3) || ( T2 != 0x89ABCDEF)) + { + ErrorCount++; + } + else + { + PassCount++; + } +} + +// +// End of File +// + diff --git a/f2833x/examples/ecap_apwm/.ccsproject b/f2833x/examples/ecap_apwm/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/ecap_apwm/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/ecap_apwm/.cproject b/f2833x/examples/ecap_apwm/.cproject new file mode 100644 index 0000000..74c3981 --- /dev/null +++ b/f2833x/examples/ecap_apwm/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/ecap_apwm/.project b/f2833x/examples/ecap_apwm/.project new file mode 100644 index 0000000..712c163 --- /dev/null +++ b/f2833x/examples/ecap_apwm/.project @@ -0,0 +1,103 @@ + + + Example_2833xECap_apwm + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_ECap.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ECap.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/ecap_apwm/Example_2833xECap_apwm.c b/f2833x/examples/ecap_apwm/Example_2833xECap_apwm.c new file mode 100644 index 0000000..f092042 --- /dev/null +++ b/f2833x/examples/ecap_apwm/Example_2833xECap_apwm.c @@ -0,0 +1,232 @@ +//########################################################################### +// +// FILE: Example_2833xECap_apwm.c +// +// TITLE: eCAP APWM Example +// +//! \addtogroup f2833x_example_list +//!

eCAP APWM (ecap_epwm)

+//! +//! This program sets up eCAP pins in the APWM mode. +//! This program runs at 150 MHz SYSCLKOUT assuming a 30 MHz +//! XCLKIN or 100 MHz SYSCLKOUT assuming a 20 MHz XCLKIN. \n +//! For 150 MHz devices: \n +//! - eCAP1 will come out on the GPIO24 pin. +//! This pin is configured to vary between 7.5 Hz and 15 Hz using +//! the shadow registers to load the next period/compare values. \n +//! - eCAP2 will come out on the GPIO7 pin. +//! This pin is configured as a 7.5 Hz output. \n +//! - eCAP3 will come out on the GPIO9 pin. +//! This pin is configured as a 1.5 Hz output. \n +//! - eCAP4 will come out on the GPIO11 pin. +//! This pin is configured as a 30 kHz output. \n +//! - All frequencies assume a 30 Mhz input clock. The XCLKOUT pin +//! should show 150Mhz. \n +//! +//! For 100 MHz devices: \n +//! - eCAP1 will come out on the GPIO24 pin. +//! This pin is configured to vary between 5 Hz and 10 Hz using +//! the shadow registers to load the next period/compare values. \n +//! - eCAP2 will come out on the GPIO7 pin. +//! This pin is configured as a 5 Hz output. \n +//! - eCAP3 will come out on the GPIO9 pin. +//! This pin is configured as a 1 Hz output. \n +//! - eCAP4 will come out on the GPIO11 pin. +//! This pin is configured as a 20kHz output. \n +//! - All frequencies assume a 20 Mhz input clock. The XCLKOUT pin +//! should show 100Mhz. +// +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Globals +// +Uint16 direction = 0; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Initialize the GPIO pins for eCAP. + // This function is found in the DSP2833x_ECap.c file + // + InitECapGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // No interrupts used for this example. + // + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code + // Setup APWM mode on CAP1, set period and compare registers + // + ECap1Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap1Regs.CAP1 = 0x01312D00; // Set Period value + ECap1Regs.CAP2 = 0x00989680; // Set Compare value + ECap1Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // + // Setup APWM mode on CAP2, set period and compare registers + // + ECap2Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap2Regs.CAP1 = 0x01312D00; // Set Period value + ECap2Regs.CAP2 = 0x00989680; // Set Compare value + ECap2Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // + // Setup APWM mode on CAP3, set period and compare registers + // + ECap3Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap3Regs.CAP1 = 0x05F5E100; // Set Period value + ECap3Regs.CAP2 = 0x02FAF080; // Set Compare value + ECap3Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // + // Setup APWM mode on CAP4, set period and compare registers + // + ECap4Regs.ECCTL2.bit.CAP_APWM = 1; // Enable APWM mode + ECap4Regs.CAP1 = 0x00001388; // Set Period value + ECap4Regs.CAP2 = 0x000009C4; // Set Compare value + ECap4Regs.ECCLR.all = 0x0FF; // Clear pending interrupts + ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 1; // enable Compare Equal Int + + // + // Start counters + // + ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; + ECap2Regs.ECCTL2.bit.TSCTRSTOP = 1; + ECap3Regs.ECCTL2.bit.TSCTRSTOP = 1; + ECap4Regs.ECCTL2.bit.TSCTRSTOP = 1; + + for(;;) + { + // + // set next duty cycle to 50% + // + ECap1Regs.CAP4 = ECap1Regs.CAP1 >> 1; + + // + // vary freq between 7.5 Hz and 15 Hz (for 150MHz SYSCLKOUT) + // 5 Hz and 10 Hz (for 100 MHz SYSCLKOUT) + // + if(ECap1Regs.CAP1 >= 0x01312D00) + { + direction = 0; + } + else if (ECap1Regs.CAP1 <= 0x00989680) + { + direction = 1; + } + + if(direction == 0) + { + ECap1Regs.CAP3 = ECap1Regs.CAP1 - 500000; + } + else + { + ECap1Regs.CAP3 = ECap1Regs.CAP1 + 500000; + } + } +} + +// +// End of File +// + diff --git a/f2833x/examples/ecap_capture_pwm/.ccsproject b/f2833x/examples/ecap_capture_pwm/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/ecap_capture_pwm/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/ecap_capture_pwm/.cproject b/f2833x/examples/ecap_capture_pwm/.cproject new file mode 100644 index 0000000..3b2798b --- /dev/null +++ b/f2833x/examples/ecap_capture_pwm/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/ecap_capture_pwm/.project b/f2833x/examples/ecap_capture_pwm/.project new file mode 100644 index 0000000..b34820c --- /dev/null +++ b/f2833x/examples/ecap_capture_pwm/.project @@ -0,0 +1,108 @@ + + + Example_2833xECap_Capture_Pwm + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_ECap.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ECap.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.c b/f2833x/examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.c new file mode 100644 index 0000000..345eadb --- /dev/null +++ b/f2833x/examples/ecap_capture_pwm/Example_2833xECap_Capture_Pwm.c @@ -0,0 +1,338 @@ +//########################################################################### +// +// FILE: Example_2833xECap_Capture_Pwm.c +// +// TITLE: eCap capture PWM Example +// +//! \addtogroup f2833x_example_list +//!

eCap capture PWM (ecap_capture_pwm)

+//! +//! This example configures ePWM3A for: +//! - Up count +//! - Period starts at 2 and goes up to 1000 +//! - Toggle output on PRD +//! +//! eCAP1 is configured to capture the time between rising +//! and falling edge of the ePWM3A output. +//! +//! \b External \b Connections \n +//! - eCap1 is on GPIO24 +//! - ePWM3A is on GPIO4 +//! - Connect GPIO4 to GPIO24. +//! +//! \b Watch \b Variables \n +//! - ECap1IntCount - Successful captures +//! - ECap1PassCount - Interrupt counts +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines to configure the start/end period for the timer +// +#define PWM3_TIMER_MIN 10 +#define PWM3_TIMER_MAX 8000 + +// +// Function Prototypes +// +__interrupt void ecap1_isr(void); +void InitECapture(void); +void InitEPwmTimer(void); +void Fail(void); + +// +// Globals +// +Uint32 ECap1IntCount; +Uint32 ECap1PassCount; +Uint32 EPwm3TimerDirection; + +// +// Defines to keep track of which way the timer value is moving +// +#define EPWM_TIMER_UP 1 +#define EPWM_TIMER_DOWN 0 + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + InitEPwm3Gpio(); + InitECap1Gpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.ECAP1_INT = &ecap1_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + InitEPwmTimer(); // For this example, only initialize the ePWM Timers + InitECapture(); + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Initialize counters + // + ECap1IntCount = 0; + ECap1PassCount = 0; + + // + // Enable CPU INT4 which is connected to ECAP1-4 INT + // + IER |= M_INT4; + + // + // Enable eCAP INTn in the PIE: Group 3 interrupt 1-6 + // + PieCtrlRegs.PIEIER4.bit.INTx1 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;) + { + __asm(" NOP"); + } +} + +// +// InitEPwmTimer - +// +void +InitEPwmTimer() +{ + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.TBPRD = PWM3_TIMER_MIN; + EPwm3Regs.TBPHS.all = 0x00000000; + EPwm3Regs.AQCTLA.bit.PRD = AQ_TOGGLE; // Toggle on PRD + + // + // TBCLK = SYSCLKOUT + // + EPwm3Regs.TBCTL.bit.HSPCLKDIV = 1; + EPwm3Regs.TBCTL.bit.CLKDIV = 0; + + EPwm3TimerDirection = EPWM_TIMER_UP; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; +} + +// +// InitECapture - +// +void +InitECapture() +{ + ECap1Regs.ECEINT.all = 0x0000; // Disable all capture interrupts + ECap1Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags + ECap1Regs.ECCTL1.bit.CAPLDEN = 0; // Disable CAP1-CAP4 register loads + ECap1Regs.ECCTL2.bit.TSCTRSTOP = 0; // Make sure the counter is stopped + + // + // Configure peripheral registers + // + ECap1Regs.ECCTL2.bit.CONT_ONESHT = 1; // One-shot + ECap1Regs.ECCTL2.bit.STOP_WRAP = 3; // Stop at 4 events + ECap1Regs.ECCTL1.bit.CAP1POL = 1; // Falling edge + ECap1Regs.ECCTL1.bit.CAP2POL = 0; // Rising edge + ECap1Regs.ECCTL1.bit.CAP3POL = 1; // Falling edge + ECap1Regs.ECCTL1.bit.CAP4POL = 0; // Rising edge + ECap1Regs.ECCTL1.bit.CTRRST1 = 1; // Difference operation + ECap1Regs.ECCTL1.bit.CTRRST2 = 1; // Difference operation + ECap1Regs.ECCTL1.bit.CTRRST3 = 1; // Difference operation + ECap1Regs.ECCTL1.bit.CTRRST4 = 1; // Difference operation + ECap1Regs.ECCTL2.bit.SYNCI_EN = 1; // Enable sync in + ECap1Regs.ECCTL2.bit.SYNCO_SEL = 0; // Pass through + ECap1Regs.ECCTL1.bit.CAPLDEN = 1; // Enable capture units + + ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; // Start Counter + ECap1Regs.ECCTL2.bit.REARM = 1; // arm one-shot + ECap1Regs.ECCTL1.bit.CAPLDEN = 1; // Enable CAP1-CAP4 register loads + ECap1Regs.ECEINT.bit.CEVT4 = 1; // 4 events = interrupt +} + +// +// ecap1_isr - +// +__interrupt void +ecap1_isr(void) +{ + // + // Cap input is syc'ed to SYSCLKOUT so there may be + // a +/- 1 cycle variation + // + if(ECap1Regs.CAP2 > EPwm3Regs.TBPRD*2+1 || + ECap1Regs.CAP2 < EPwm3Regs.TBPRD*2-1) + { + Fail(); + } + + if(ECap1Regs.CAP3 > EPwm3Regs.TBPRD*2+1 || + ECap1Regs.CAP3 < EPwm3Regs.TBPRD*2-1) + { + Fail(); + } + + if(ECap1Regs.CAP4 > EPwm3Regs.TBPRD*2+1 || + ECap1Regs.CAP4 < EPwm3Regs.TBPRD*2-1) + { + Fail(); + } + + ECap1IntCount++; + + if(EPwm3TimerDirection == EPWM_TIMER_UP) + { + if(EPwm3Regs.TBPRD < PWM3_TIMER_MAX) + { + EPwm3Regs.TBPRD++; + } + else + { + EPwm3TimerDirection = EPWM_TIMER_DOWN; + EPwm3Regs.TBPRD--; + } + } + else + { + if(EPwm3Regs.TBPRD > PWM3_TIMER_MIN) + { + EPwm3Regs.TBPRD--; + } + else + { + EPwm3TimerDirection = EPWM_TIMER_UP; + EPwm3Regs.TBPRD++; + } + } + + ECap1PassCount++; + + ECap1Regs.ECCLR.bit.CEVT4 = 1; + ECap1Regs.ECCLR.bit.INT = 1; + ECap1Regs.ECCTL2.bit.REARM = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 4 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; +} + +// +// Fail - +// +void +Fail() +{ + __asm(" ESTOP0"); +} + +// +// End of File +// + diff --git a/f2833x/examples/epwm_deadband/.ccsproject b/f2833x/examples/epwm_deadband/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/epwm_deadband/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/epwm_deadband/.cproject b/f2833x/examples/epwm_deadband/.cproject new file mode 100644 index 0000000..ad7d2a1 --- /dev/null +++ b/f2833x/examples/epwm_deadband/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/epwm_deadband/.project b/f2833x/examples/epwm_deadband/.project new file mode 100644 index 0000000..fb28cb3 --- /dev/null +++ b/f2833x/examples/epwm_deadband/.project @@ -0,0 +1,103 @@ + + + Example_2833xEPwmDeadBand + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/epwm_deadband/Example_2833xEPwmDeadBand.c b/f2833x/examples/epwm_deadband/Example_2833xEPwmDeadBand.c new file mode 100644 index 0000000..0a30626 --- /dev/null +++ b/f2833x/examples/epwm_deadband/Example_2833xEPwmDeadBand.c @@ -0,0 +1,533 @@ +//########################################################################### +// +// FILE: Example_2833xEPwmDeadBand.c +// +// TITLE: ePWM Deadband Generation Example +// +//! \addtogroup f2833x_example_list +//!

ePWM Deadband Generation (epwm_deadband)

+//! +//! This example configures ePWM1, ePWM2 and ePWM3 for: +//! - Count up/down +//! - Deadband +//! 3 Examples are included: +//! - ePWM1: Active low PWMs +//! - ePWM2: Active low complementary PWMs +//! - ePWM3: Active high complementary PWMs +//! +//! Each ePWM is configured to interrupt on the 3rd zero event +//! when this happens the deadband is modified such that +//! 0 <= DB <= DB_MAX. That is, the deadband will move up and +//! down between 0 and the maximum value. +//! +//! \b External \b Connections \n +//! - EPWM1A is on GPIO0 +//! - EPWM1B is on GPIO1 +//! - EPWM2A is on GPIO2 +//! - EPWM2B is on GPIO3 +//! - EPWM3A is on GPIO4 +//! - EPWM3B is on GPIO5 +// +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +void InitEPwm1Example(void); +void InitEPwm2Example(void); +void InitEPwm3Example(void); +__interrupt void epwm1_isr(void); +__interrupt void epwm2_isr(void); +__interrupt void epwm3_isr(void); + +// +// Globals +// +Uint32 EPwm1TimerIntCount; +Uint32 EPwm2TimerIntCount; +Uint32 EPwm3TimerIntCount; +Uint16 EPwm1_DB_Direction; +Uint16 EPwm2_DB_Direction; +Uint16 EPwm3_DB_Direction; + +// +// Defines for the Maximum Dead Band values +// +#define EPWM1_MAX_DB 0x03FF +#define EPWM2_MAX_DB 0x03FF +#define EPWM3_MAX_DB 0x03FF + +#define EPWM1_MIN_DB 0 +#define EPWM2_MIN_DB 0 +#define EPWM3_MIN_DB 0 + +// +// Defines to keep track of which way the Dead Band is moving +// +#define DB_UP 1 +#define DB_DOWN 0 + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 + // These functions are in the DSP2833x_EPwm.c file + // + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_isr; + PieVectTable.EPWM2_INT = &epwm2_isr; + PieVectTable.EPWM3_INT = &epwm3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + InitEPwm3Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + // + // Step 5. User specific code, enable interrupts + // + + // + // Initialize counters: + // + EPwm1TimerIntCount = 0; + EPwm2TimerIntCount = 0; + EPwm3TimerIntCount = 0; + + // + // Enable CPU INT3 which is connected to EPWM1-3 INT + // + IER |= M_INT3; + + // + // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + // + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;) + { + __asm(" NOP"); + } +} + +// +// epwm1_isr - +// +__interrupt void +epwm1_isr(void) +{ + if(EPwm1_DB_Direction == DB_UP) + { + if(EPwm1Regs.DBFED < EPWM1_MAX_DB) + { + EPwm1Regs.DBFED++; + EPwm1Regs.DBRED++; + } + else + { + EPwm1_DB_Direction = DB_DOWN; + EPwm1Regs.DBFED--; + EPwm1Regs.DBRED--; + } + } + else + { + if(EPwm1Regs.DBFED == EPWM1_MIN_DB) + { + EPwm1_DB_Direction = DB_UP; + EPwm1Regs.DBFED++; + EPwm1Regs.DBRED++; + } + else + { + EPwm1Regs.DBFED--; + EPwm1Regs.DBRED--; + } + } + EPwm1TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm1Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm2_isr - +// +__interrupt void +epwm2_isr(void) +{ + if(EPwm2_DB_Direction == DB_UP) + { + if(EPwm2Regs.DBFED < EPWM2_MAX_DB) + { + EPwm2Regs.DBFED++; + EPwm2Regs.DBRED++; + } + else + { + EPwm2_DB_Direction = DB_DOWN; + EPwm2Regs.DBFED--; + EPwm2Regs.DBRED--; + } + } + else + { + if(EPwm2Regs.DBFED == EPWM2_MIN_DB) + { + EPwm2_DB_Direction = DB_UP; + EPwm2Regs.DBFED++; + EPwm2Regs.DBRED++; + } + else + { + EPwm2Regs.DBFED--; + EPwm2Regs.DBRED--; + } + } + + EPwm2TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm2Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm3_isr - +// +__interrupt void +epwm3_isr(void) +{ + if(EPwm3_DB_Direction == DB_UP) + { + if(EPwm3Regs.DBFED < EPWM3_MAX_DB) + { + EPwm3Regs.DBFED++; + EPwm3Regs.DBRED++; + } + else + { + EPwm3_DB_Direction = DB_DOWN; + EPwm3Regs.DBFED--; + EPwm3Regs.DBRED--; + } + } + else + { + if(EPwm3Regs.DBFED == EPWM3_MIN_DB) + { + EPwm3_DB_Direction = DB_UP; + EPwm3Regs.DBFED++; + EPwm3Regs.DBRED++; + } + else + { + EPwm3Regs.DBFED--; + EPwm3Regs.DBRED--; + } + } + + EPwm3TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm3Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// InitEPwm1Example - +// +void +InitEPwm1Example() +{ + EPwm1Regs.TBPRD = 6000; // Set timer period + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + + // + // Setup TBCLK + // + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4; + + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // + // Setup compare + // + EPwm1Regs.CMPA.half.CMPA = 3000; + + // + // Set actions + // + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero + EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; + + // + // Active Low PWMs - Setup Deadband + // + EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO; + EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; + EPwm1Regs.DBRED = EPWM1_MIN_DB; + EPwm1Regs.DBFED = EPWM1_MIN_DB; + EPwm1_DB_Direction = DB_UP; + + // + // Interrupt where we will change the Deadband + // + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event +} + +// +// InitEPwm2Example - +// +void +InitEPwm2Example() +{ + EPwm2Regs.TBPRD = 6000; // Set timer period + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + + // + // Setup TBCLK + // + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on the scope + + // + // Setup compare + // + EPwm2Regs.CMPA.half.CMPA = 3000; + + // + // Set actions + // + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero + EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero + EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; + + // + // Active Low complementary PWMs - setup the deadband + // + EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; + EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; + EPwm2Regs.DBRED = EPWM2_MIN_DB; + EPwm2Regs.DBFED = EPWM2_MIN_DB; + EPwm2_DB_Direction = DB_UP; + + // + // Interrupt where we will modify the deadband + // + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event +} + +// +// InitEPwm3Example - +// +void +InitEPwm3Example() +{ + EPwm3Regs.TBPRD = 6000; // Set timer period + EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm3Regs.TBCTR = 0x0000; // Clear counter + + // + // Setup TBCLK + // + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV4;// Slow so we can observe on the scope + + // + // Setup compare + // + EPwm3Regs.CMPA.half.CMPA = 3000; + + // + // Set actions + // + EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero + EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero + EPwm3Regs.AQCTLB.bit.CAD = AQ_SET; + + // + // Active high complementary PWMs - Setup the deadband + // + EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; + EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; + EPwm3Regs.DBRED = EPWM3_MIN_DB; + EPwm3Regs.DBFED = EPWM3_MIN_DB; + EPwm3_DB_Direction = DB_UP; + + // + // Interrupt where we will change the deadband + // + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event +} + +// +// End of File +// + diff --git a/f2833x/examples/epwm_dma/.ccsproject b/f2833x/examples/epwm_dma/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/epwm_dma/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/epwm_dma/.cproject b/f2833x/examples/epwm_dma/.cproject new file mode 100644 index 0000000..9e7ebd7 --- /dev/null +++ b/f2833x/examples/epwm_dma/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/epwm_dma/.project b/f2833x/examples/epwm_dma/.project new file mode 100644 index 0000000..167bcaf --- /dev/null +++ b/f2833x/examples/epwm_dma/.project @@ -0,0 +1,98 @@ + + + Example_2833xEPwm_DMA + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_Adc.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Adc.c + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/epwm_dma/Example_2833xEPwm_DMA.c b/f2833x/examples/epwm_dma/Example_2833xEPwm_DMA.c new file mode 100644 index 0000000..15679ea --- /dev/null +++ b/f2833x/examples/epwm_dma/Example_2833xEPwm_DMA.c @@ -0,0 +1,625 @@ +//########################################################################### +// +// FILE: Example_2833xEPwm_DMA.c +// +// TITLE: ePWM to DMA Example +// +//! \addtogroup f2833x_example_list +//!

ePWM to DMA (epwm_dma)

+//! +//! This example demonstrates several cases where the DMA is triggered from +//! SOC signals generated by ePWM modules. +//! +//! \b Watch \b Variables \n +//! - EPwm1Regs.TBPRD +//! - EPwm1Regs.CMPA.all +//! - ADCbuffer +//! - InterruptCount +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototype statements +// +void delay_loop(void); +void DMAInitialize(void); +void DMACH1Config(void); +void DMACH2Config(void); +void DMACH3Config(void); +void ConfigAdc(void); +void config_ePWM1_to_generate_ADCSOCA(void); +void config_ePWM2_to_generate_ADCSOCB(void); +__interrupt void local_DINTCH1_ISR(void); + +// +// Globals +// +#pragma DATA_SECTION(ADCbuffer,"DMARAML4"); +volatile Uint32 ADCbuffer[3]; + +Uint16 VarA; +Uint32 VarB; + +volatile Uint16 *MAPCNF = (Uint16 *)0x00702E; + +Uint16 InterruptCount; + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this example use the following configuration: + // + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + EALLOW; + + // + // Initialize PIE vector for CPU interrupt: + // + PieVectTable.DINTCH1 = &local_DINTCH1_ISR; // Point to DMA CH1 ISR + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE + EDIS; + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code: + // + InterruptCount = 0; + + EALLOW; + GpioCtrlRegs.GPADIR.all = 0xFFFFFFFF; // All outputs + SysCtrlRegs.MAPCNF.bit.MAPEPWM = 1; // Remap ePWMs for DMA access + EDIS; + + GpioDataRegs.GPASET.all = 0xFFFFFFFF; + delay_loop(); + GpioDataRegs.GPACLEAR.all = 0x00000002; + + for(i=0; i<3; i++) + { + ADCbuffer[i] = ((Uint32)i*0x00011000) + 0x00044000; + } + + VarA = 75; + VarB = 0x652000; + + // + // Enable and configure clocks to peripherals: + // + EALLOW; + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // Enable SYSCLK to DMA + EDIS; + + DMAInitialize(); + DMACH1Config(); + DMACH2Config(); + DMACH3Config(); + + // + // Enable all interrupts: + // + IER = M_INT7; // Enable INT7 (7.1 DMA Ch1) + EINT; + + InitAdc(); + ConfigAdc(); + + config_ePWM1_to_generate_ADCSOCA(); + config_ePWM2_to_generate_ADCSOCB(); + + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + __asm(" NOP"); + EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Up count mode + EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Up count mode + EDIS; + + for(;;) + { + + } +} + +// +// DMA Functions +// +void +DMAInitialize(void) +{ + EALLOW; + + // + // Perform a hard reset on DMA + // + DmaRegs.DMACTRL.bit.HARDRESET = 1; + + // + // always perform one NOP after a HARDRESET + // + __asm(" NOP"); + + // + // Stop DMA on emulation suspend + // + DmaRegs.DEBUGCTRL.bit.FREE = 0; + + EDIS; +} + +// +// DMACH1Config - +// +void +DMACH1Config(void) +{ + EALLOW; + + // + // Configure CH1: + // + + // + // Reset selected channel via CONTROL Register: + // + + // + // Perform SOFT reset on channel (clears all counters) + // + //DmaRegs.CH1.CONTROL.bit.SOFTRESET = 1; + + // + // Set up MODE Register: + // + + // + // ePWM1 SOCA as peripheral interrupt source + // + DmaRegs.CH1.MODE.bit.PERINTSEL = 18; + + DmaRegs.CH1.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled + DmaRegs.CH1.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt + DmaRegs.CH1.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer + DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH1.MODE.bit.DATASIZE = 0; // 16-bit data size transfers + + // + // Generate interrupt to CPU at the beg of transfer + // + DmaRegs.CH1.MODE.bit.CHINTMODE = 0; + + DmaRegs.CH1.MODE.bit.CHINTE = 1; // Channel Interrupt to CPU enabled + + // + // Set up BURST registers + // + + // + // Number (N-1) of 16-bit words transferred in a burst + // + DmaRegs.CH1.BURST_SIZE.all = 0; + DmaRegs.CH1.SRC_BURST_STEP = 0; // Not needed since BURST_SIZE = 0 + DmaRegs.CH1.DST_BURST_STEP = 0; // Not needed since BURST_SIZE = 0 + + // + // Set up TRANSFER registers + // + DmaRegs.CH1.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer + DmaRegs.CH1.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + + // + // Set up WRAP registers + // + DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around + DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around + DmaRegs.CH1.SRC_WRAP_STEP = 0; + DmaRegs.CH1.DST_WRAP_STEP = 0; + + // + // Set up SOURCE address + // + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &VarA; // Point to variable in RAM + + // + // Set up DESTINATION address + // + + // + // Point to ePWM1 TBPRD register remapped for DMA need to make sure + // .cmd file has ePWMs remapped + // + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.TBPRD; + + // + // Clear any spurious flags + // + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; //Clear any spurious interrupt flags + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; //Clear any spurious sync error flags + + EDIS; +} + +// +// DMACH2Config - +// +void +DMACH2Config(void) +{ + EALLOW; + + // + // Configure CH2 + // + + // + // Reset selected channel via CONTROL Register + // + + // + // Perform SOFT reset on channel (clears all counters) + // + //DmaRegs.CH2.CONTROL.bit.SOFTRESET = 1; + + // + // Set up MODE Register + // + + // + // ePWM2 SOCB as peripheral interrupt source + // + DmaRegs.CH2.MODE.bit.PERINTSEL = 21; + + DmaRegs.CH2.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled + DmaRegs.CH2.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt + DmaRegs.CH2.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer + DmaRegs.CH2.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH2.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH2.MODE.bit.DATASIZE = 1; // 32-bit data size transfers + DmaRegs.CH2.MODE.bit.CHINTMODE = 0; + DmaRegs.CH2.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled + + // + // Set up BURST registers + // + + // + // Number (N-1) of 16-bit words transferred in a burst + // + DmaRegs.CH2.BURST_SIZE.all = 1; + + // + // Not needed since only 1 32-bit move per burst + // + DmaRegs.CH2.SRC_BURST_STEP = 0x0000; + + // + // Not needed since only 1 32-bit move per burst + // + DmaRegs.CH2.DST_BURST_STEP = 0x0000; + + // + // Set up TRANSFER registers + // + DmaRegs.CH2.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + DmaRegs.CH2.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + + // + // Set up WRAP registers + // + DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around + DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around + DmaRegs.CH2.SRC_WRAP_STEP = 0; + DmaRegs.CH2.DST_WRAP_STEP = 0; + + // + // Set up SOURCE address + // + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &VarB; // Point to variable in RAM + + // + // Set up DESTINATION address + // + + // + // Point to ePWM1 CMPAHR/CMPA registers + // + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.CMPA.all; + + // + // Clear any spurious flags + // + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; //Clear any spurious interrupt flags + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; //Clear any spurious sync flags + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; //Clear any spurious sync error flags + + EDIS; +} + +void DMACH3Config(void) +{ + EALLOW; + + // + // Configure CH3 + // + + // + // Set up MODE Register + // + + // + // ADC SEQ1INT as peripheral interrupt source + // + DmaRegs.CH3.MODE.bit.PERINTSEL = 1; + + DmaRegs.CH3.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled + DmaRegs.CH3.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt + DmaRegs.CH3.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer + DmaRegs.CH3.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH3.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH3.MODE.bit.DATASIZE = 1; // 32-bit data size transfers + DmaRegs.CH3.MODE.bit.CHINTMODE = 0; + DmaRegs.CH3.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled + + // + // Set up BURST registers + // + + // + // Number (N-1) of 16-bit words transferred in a burst + // + DmaRegs.CH3.BURST_SIZE.all = 5; + + // + // Increment source burst address by 2 (32-bit) + // + DmaRegs.CH3.SRC_BURST_STEP = 2; + + // + // Increment destination burst address by 2 (32-bit) + // + DmaRegs.CH3.DST_BURST_STEP = 2; + + // + // Set up TRANSFER registers + // + DmaRegs.CH3.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer + DmaRegs.CH3.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + DmaRegs.CH3.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0 + + // + // Set up WRAP registers + // + DmaRegs.CH3.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around + DmaRegs.CH3.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around + DmaRegs.CH3.SRC_WRAP_STEP = 0; + DmaRegs.CH3.DST_WRAP_STEP = 0; + + // + // Set up SOURCE address + // + + // + // Point to first RESULT reg + // + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32) &AdcMirror.ADCRESULT0; + + // + // Set up DESTINATION address + // + + // + // Point to beginning of ADCbuffer + // + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32) &ADCbuffer[0]; + + // + // Clear any spurious flags + // + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; //Clear any spurious interrupt flags + DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; //Clear any spurious sync flags + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; //Clear any spurious sync error flags + + EDIS; +} + +// +// local_DINTCH1_ISR - +// +__interrupt void +local_DINTCH1_ISR(void) // DMA INT7.1 +{ + GpioDataRegs.GPATOGGLE.all = 0x00000001; // Toggle GPIOA0 + + InterruptCount++; + + if((DmaRegs.CH1.CONTROL.bit.OVRFLG == 1) || + (DmaRegs.CH2.CONTROL.bit.OVRFLG == 1) || + (DmaRegs.CH3.CONTROL.bit.OVRFLG == 1)) + { + __asm(" ESTOP0"); + } + + PieCtrlRegs.PIEACK.bit.ACK7 = 1; // Clear PIEIFR bit +} + +// +// ConfigAdc - +// +void +ConfigAdc(void) +{ + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 7; + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0; // ADCINA0 + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1; // ADCINA1 + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2; // ADCINA2 + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 3; // ADCINA3 + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 4; // ADCINA4 + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 5; // ADCINA5 + + // + // Enable ADC to accept ePWM_SOCA trigger + // + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; + + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear interrupt flag + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt +} + +// +// config_ePWM1_to_generate_ADCSOCA - +// +void +config_ePWM1_to_generate_ADCSOCA(void) +{ + // + // Configure ePWM1 Timer + // Interrupt triggers ADCSOCA + // + EALLOW; + + // + // Setup period (one off so DMA transfer will be obvious) + // + EPwm1Regs.TBPRD = 74; + + EPwm1Regs.CMPA.all = 0x501000; + EPwm1Regs.ETSEL.bit.SOCASEL = 2; // ADCSOCA on TBCTR=TBPRD + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate SOCA on 1st event + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA generation + EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode + EDIS; +} + +// +// config_ePWM2_to_generate_ADCSOCB - +// +void +config_ePWM2_to_generate_ADCSOCB(void) +{ + // + // Configure ePWM2 Timer + // Interrupt triggers ADCSOCB + // + EALLOW; + EPwm2Regs.TBPRD = 150; // Setup periodSetup period + EPwm2Regs.CMPA.all = 0x200000; + EPwm2Regs.ETSEL.bit.SOCBSEL = 2; // ADCSOCB on TBCTR=TBPRD + EPwm2Regs.ETPS.bit.SOCBPRD = 1; // Generate SOCB on 1st event + EPwm2Regs.ETSEL.bit.SOCBEN = 1; // Enable SOCB generation + EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode + EDIS; +} + +void delay_loop() +{ + short i; + for (i = 0; i < 1000; i++) + { + + } +} + +// +// End of File +// + diff --git a/f2833x/examples/epwm_timer_interrupts/.ccsproject b/f2833x/examples/epwm_timer_interrupts/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/epwm_timer_interrupts/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/epwm_timer_interrupts/.cproject b/f2833x/examples/epwm_timer_interrupts/.cproject new file mode 100644 index 0000000..341af94 --- /dev/null +++ b/f2833x/examples/epwm_timer_interrupts/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/epwm_timer_interrupts/.project b/f2833x/examples/epwm_timer_interrupts/.project new file mode 100644 index 0000000..f59be4c --- /dev/null +++ b/f2833x/examples/epwm_timer_interrupts/.project @@ -0,0 +1,98 @@ + + + Example_2833xEPwmTimerInt + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.c b/f2833x/examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.c new file mode 100644 index 0000000..efa3eef --- /dev/null +++ b/f2833x/examples/epwm_timer_interrupts/Example_2833xEPwmTimerInt.c @@ -0,0 +1,430 @@ +//########################################################################### +// +// FILE: Example_2833xEPwmTimerInt.c +// +// TITLE: ePWM Timer Interrupt Example +// +//! \addtogroup f2833x_example_list +//!

ePWM Timer Interrupt (epwm_timer_interrupts)

+//! +//! This example configures the ePWM Timers and increments a counter each +//! time an interrupt is taken. \n +//! In this example: +//! - All ePWM's are initialized. +//! - All timers have the same period. +//! - The timers are started sync'ed. +//! - An interrupt is taken on a zero event for each ePWM timer. +//! - ePWM1: takes an interrupt every event. +//! - ePWM2: takes an interrupt every 2nd event. +//! - ePWM3: takes an interrupt every 3rd event. +//! - ePWM4-ePWM6: takes an interrupt every event. +//! +//! Thus the Interrupt count for ePWM1, ePWM4, ePWM5, and ePWM6 should be +//! equal.The interrupt count for ePWM2 should be about half that of ePWM1 +//! and the interrupt count for ePWM3 should be about 1/3 that of ePWM1. +//! +//! \b Watch \b Variables \n +//! - EPwm1TimerIntCount +//! - EPwm2TimerIntCount +//! - EPwm3TimerIntCount +//! - EPwm4TimerIntCount +//! - EPwm5TimerIntCount +//! - EPwm6TimerIntCount +// +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines that configure which ePWM timer interrupts are enabled at the +// PIE level: 1 = enabled, 0 = disabled +// +#define PWM1_INT_ENABLE 1 +#define PWM2_INT_ENABLE 1 +#define PWM3_INT_ENABLE 1 +#define PWM4_INT_ENABLE 1 +#define PWM5_INT_ENABLE 1 +#define PWM6_INT_ENABLE 1 + +// +// Defines that configure the period for each timer +// +#define PWM1_TIMER_TBPRD 0x1FFF +#define PWM2_TIMER_TBPRD 0x1FFF +#define PWM3_TIMER_TBPRD 0x1FFF +#define PWM4_TIMER_TBPRD 0x1FFF +#define PWM5_TIMER_TBPRD 0x1FFF +#define PWM6_TIMER_TBPRD 0x1FFF + +// +// Function Prototypes +// +__interrupt void epwm1_timer_isr(void); +__interrupt void epwm2_timer_isr(void); +__interrupt void epwm3_timer_isr(void); +__interrupt void epwm4_timer_isr(void); +__interrupt void epwm5_timer_isr(void); +__interrupt void epwm6_timer_isr(void); +void InitEPwmTimer(void); + +// +// Globals +// +Uint32 EPwm1TimerIntCount; +Uint32 EPwm2TimerIntCount; +Uint32 EPwm3TimerIntCount; +Uint32 EPwm4TimerIntCount; +Uint32 EPwm5TimerIntCount; +Uint32 EPwm6TimerIntCount; + +void main(void) +{ + int i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_timer_isr; + PieVectTable.EPWM2_INT = &epwm2_timer_isr; + PieVectTable.EPWM3_INT = &epwm3_timer_isr; + PieVectTable.EPWM4_INT = &epwm4_timer_isr; + PieVectTable.EPWM5_INT = &epwm5_timer_isr; + PieVectTable.EPWM6_INT = &epwm6_timer_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + InitEPwmTimer(); // For this example, only initialize the ePWM Timers + + // + // Step 5. User specific code, enable interrupts + // + + // + // Initialize counters + // + EPwm1TimerIntCount = 0; + EPwm2TimerIntCount = 0; + EPwm3TimerIntCount = 0; + EPwm4TimerIntCount = 0; + EPwm5TimerIntCount = 0; + EPwm6TimerIntCount = 0; + + // + // Enable CPU INT3 which is connected to EPWM1-6 INT + // + IER |= M_INT3; + + // + // Enable EPWM INTn in the PIE: Group 3 interrupt 1-6 + // + PieCtrlRegs.PIEIER3.bit.INTx1 = PWM1_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx2 = PWM2_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx3 = PWM3_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx4 = PWM4_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx5 = PWM5_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx6 = PWM6_INT_ENABLE; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;) + { + __asm(" NOP"); + for(i=1;i<=10;i++) + { + + } + } +} + +// +// InitEPwmTimer - +// +void +InitEPwmTimer() +{ + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks + EDIS; + + // + // Setup Sync + // + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + + // + // Allow each timer to be sync'ed + // + EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; + + EPwm1Regs.TBPHS.half.TBPHS = 100; + EPwm2Regs.TBPHS.half.TBPHS = 200; + EPwm3Regs.TBPHS.half.TBPHS = 300; + EPwm4Regs.TBPHS.half.TBPHS = 400; + EPwm5Regs.TBPHS.half.TBPHS = 500; + EPwm6Regs.TBPHS.half.TBPHS = 600; + + EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD; + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + EPwm2Regs.TBPRD = PWM2_TIMER_TBPRD; + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = PWM2_INT_ENABLE; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_2ND; // Generate INT on 2nd event + + EPwm3Regs.TBPRD = PWM3_TIMER_TBPRD; + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = PWM3_INT_ENABLE; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + EPwm4Regs.TBPRD = PWM4_TIMER_TBPRD; + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm4Regs.ETSEL.bit.INTEN = PWM4_INT_ENABLE; // Enable INT + EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + EPwm5Regs.TBPRD = PWM5_TIMER_TBPRD; + EPwm5Regs.TBCTL.bit.CTRMODE= TB_COUNT_UP; // Count up + EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm5Regs.ETSEL.bit.INTEN = PWM5_INT_ENABLE; // Enable INT + EPwm5Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm6Regs.TBPRD = PWM6_TIMER_TBPRD; + EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm6Regs.ETSEL.bit.INTEN = PWM6_INT_ENABLE; // Enable INT + EPwm6Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced + EDIS; +} + +// +// epwm1_timer_isr - Interrupt routines uses in this example +// +__interrupt void +epwm1_timer_isr(void) +{ + EPwm1TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm1Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm2_timer_isr - +// +__interrupt void +epwm2_timer_isr(void) +{ + EPwm2TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm2Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm3_timer_isr - +// +__interrupt void +epwm3_timer_isr(void) +{ + EPwm3TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm3Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm4_timer_isr - +// +__interrupt void +epwm4_timer_isr(void) +{ + EPwm4TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm4Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm5_timer_isr - +// +__interrupt void +epwm5_timer_isr(void) +{ + EPwm5TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm5Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm6_timer_isr - +// +__interrupt void +epwm6_timer_isr(void) +{ + EPwm6TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm6Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// End of File +// + diff --git a/f2833x/examples/epwm_trip_zone/.ccsproject b/f2833x/examples/epwm_trip_zone/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/epwm_trip_zone/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/epwm_trip_zone/.cproject b/f2833x/examples/epwm_trip_zone/.cproject new file mode 100644 index 0000000..278b3de --- /dev/null +++ b/f2833x/examples/epwm_trip_zone/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/epwm_trip_zone/.project b/f2833x/examples/epwm_trip_zone/.project new file mode 100644 index 0000000..a58573d --- /dev/null +++ b/f2833x/examples/epwm_trip_zone/.project @@ -0,0 +1,103 @@ + + + Example_2833xEPwmTripZone + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/epwm_trip_zone/Example_2833xEPwmTripZone.c b/f2833x/examples/epwm_trip_zone/Example_2833xEPwmTripZone.c new file mode 100644 index 0000000..3d232cd --- /dev/null +++ b/f2833x/examples/epwm_trip_zone/Example_2833xEPwmTripZone.c @@ -0,0 +1,349 @@ +//########################################################################### +// +// FILE: Example_2833xEPwmTripZone.c +// +// TITLE: ePWM Trip Zone Example +// +//! \addtogroup f2833x_example_list +//!

ePWM Trip Zone (epwm_trip_zone)

+//! +//! This example configures ePWM1 and ePWM2 as follows +//! - ePWM1 has TZ1 and TZ2 as one shot trip sources +//! - ePWM2 has TZ1 and TZ2 as cycle by cycle trip sources +//! +//! Initially tie TZ1 and TZ2 high. During the test, monitor ePWM1 or ePWM2 +//! outputs on a scope. Pull TZ1 or TZ2 low to see the effect. +//! +//! \b External \b Connections \n +//! - EPWM1A is on GPIO0 +//! - EPWM1B is on GPIO1 +//! - EPWM2A is on GPIO2 +//! - EPWM2B is on GPIO3 +//! - TZ1 is on GPIO12 +//! - TZ2 is on GPIO13 +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +void InitEPwm1Example(void); +void InitEPwm2Example(void); +__interrupt void epwm1_tzint_isr(void); +__interrupt void epwm2_tzint_isr(void); + +// +// Globals +// +Uint32 EPwm1TZIntCount; +Uint32 EPwm2TZIntCount; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this case just init GPIO pins for ePWM1, ePWM2, and TZ pins + // + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitTzGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_TZINT = &epwm1_tzint_isr; + PieVectTable.EPWM2_TZINT = &epwm2_tzint_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + // + // Step 5. User specific code, enable interrupts + // + + // + // Initialize counters + // + EPwm1TZIntCount = 0; + EPwm2TZIntCount = 0; + + // + // Enable CPU INT3 which is connected to EPWM1-3 INT + // + IER |= M_INT2; + + // + // Enable EPWM INTn in the PIE: Group 2 interrupt 1-3 + // + PieCtrlRegs.PIEIER2.bit.INTx1 = 1; + PieCtrlRegs.PIEIER2.bit.INTx2 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;) + { + __asm(" NOP"); + } +} + +// +// epwm1_tzint_isr +// +__interrupt void +epwm1_tzint_isr(void) +{ + EPwm1TZIntCount++; + + // + // Leave these flags set so we only take this + // interrupt once + // + // EALLOW; + // EPwm1Regs.TZCLR.bit.OST = 1; + // EPwm1Regs.TZCLR.bit.INT = 1; + // EDIS; + + // + // Acknowledge this interrupt to receive more interrupts from group 2 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; +} + +// +// epwm2_tzint_isr - +// +__interrupt void +epwm2_tzint_isr(void) +{ + EPwm2TZIntCount++; + + // + // Clear the flags - we will continue to take this interrupt until the + // TZ pin goes high + // + EALLOW; + EPwm2Regs.TZCLR.bit.CBC = 1; + EPwm2Regs.TZCLR.bit.INT = 1; + EDIS; + + // + // Acknowledge this interrupt to receive more interrupts from group 2 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; +} + +// +// InitEPwm1Example - +// +void +InitEPwm1Example() +{ + // + // Enable TZ1 and TZ2 as one shot trip sources + // + EALLOW; + EPwm1Regs.TZSEL.bit.OSHT1 = 1; + EPwm1Regs.TZSEL.bit.OSHT2 = 1; + + EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_HI; + EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; + + // + // Enable TZ interrupt + // + EPwm1Regs.TZEINT.bit.OST = 1; + EDIS; + + EPwm1Regs.TBPRD = 6000; // Set timer period + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + + // + // Setup TBCLK + // + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4; + + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // + // Setup compare + // + EPwm1Regs.CMPA.half.CMPA = 3000; + + // + // Set actions + // + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero + EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; +} + +// +// InitEPwm2Example - +// +void +InitEPwm2Example() +{ + // + // Enable TZ1 and TZ2 as one cycle-by-cycle trip sources + // + EALLOW; + EPwm2Regs.TZSEL.bit.CBC1 = 1; + EPwm2Regs.TZSEL.bit.CBC2 = 1; + + EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_HI; + EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; + + // + // Enable TZ interrupt + // + EPwm2Regs.TZEINT.bit.CBC = 1; + EDIS; + + EPwm2Regs.TBPRD = 6000; // Set timer period + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + + // + // Setup TBCLK + // + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; //Slow just to observe on the scope + + // + // Setup compare + // + EPwm2Regs.CMPA.half.CMPA = 3000; + + // + // Set actions + // + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero + EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; + + EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero + EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; +} + +// +// End of File +// + diff --git a/f2833x/examples/epwm_up_aq/.ccsproject b/f2833x/examples/epwm_up_aq/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/epwm_up_aq/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/epwm_up_aq/.cproject b/f2833x/examples/epwm_up_aq/.cproject new file mode 100644 index 0000000..d1d92f3 --- /dev/null +++ b/f2833x/examples/epwm_up_aq/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/epwm_up_aq/.project b/f2833x/examples/epwm_up_aq/.project new file mode 100644 index 0000000..50cd2d7 --- /dev/null +++ b/f2833x/examples/epwm_up_aq/.project @@ -0,0 +1,103 @@ + + + Example_2833xEPwmUpAQ + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/epwm_up_aq/Example_2833xEPwmUpAQ.c b/f2833x/examples/epwm_up_aq/Example_2833xEPwmUpAQ.c new file mode 100644 index 0000000..00d0a7d --- /dev/null +++ b/f2833x/examples/epwm_up_aq/Example_2833xEPwmUpAQ.c @@ -0,0 +1,598 @@ +//########################################################################### +// +// FILE: Example_2833xEPwmUpAQ.c +// +// TITLE: ePWM Action Qualifier Module using Upcount mode Example +// +//! \addtogroup f2833x_example_list +//!

ePWM Action Qualifier Module using Upcount mode (epwm_up_aq)

+//! +//! This example configures ePWM1, ePWM2, ePWM3 to produce a waveform with +//! independent modulation on EPWMxA and EPWMxB. The compare values CMPA +//! and CMPB are modified within the ePWM's ISR. The TB counter is in upmode. +//! +//! Monitor the ePWM1 - ePWM3 pins on an oscilloscope. +//! +//! \b External \b Connections \n +//! - EPWM1A is on GPIO0 +//! - EPWM1B is on GPIO1 +//! - EPWM2A is on GPIO2 +//! - EPWM2B is on GPIO3 +//! - EPWM3A is on GPIO4 +//! - EPWM3B is on GPIO5 +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Typedefs +// +typedef struct +{ + volatile struct EPWM_REGS *EPwmRegHandle; + Uint16 EPwm_CMPA_Direction; + Uint16 EPwm_CMPB_Direction; + Uint16 EPwmTimerIntCount; + Uint16 EPwmMaxCMPA; + Uint16 EPwmMinCMPA; + Uint16 EPwmMaxCMPB; + Uint16 EPwmMinCMPB; +} EPWM_INFO; + +// +// Function Prototypes +// +void InitEPwm1Example(void); +void InitEPwm2Example(void); +void InitEPwm3Example(void); +__interrupt void epwm1_isr(void); +__interrupt void epwm2_isr(void); +__interrupt void epwm3_isr(void); +void update_compare(EPWM_INFO*); + +// +// Globals +// +EPWM_INFO epwm1_info; +EPWM_INFO epwm2_info; +EPWM_INFO epwm3_info; + +// +// Defines that configure the period for each timer +// +#define EPWM1_TIMER_TBPRD 2000 // Period register +#define EPWM1_MAX_CMPA 1950 +#define EPWM1_MIN_CMPA 50 +#define EPWM1_MAX_CMPB 1950 +#define EPWM1_MIN_CMPB 50 + +#define EPWM2_TIMER_TBPRD 2000 // Period register +#define EPWM2_MAX_CMPA 1950 +#define EPWM2_MIN_CMPA 50 +#define EPWM2_MAX_CMPB 1950 +#define EPWM2_MIN_CMPB 50 + +#define EPWM3_TIMER_TBPRD 2000 // Period register +#define EPWM3_MAX_CMPA 950 +#define EPWM3_MIN_CMPA 50 +#define EPWM3_MAX_CMPB 1950 +#define EPWM3_MIN_CMPB 1050 + +// +// Defines that keep track of which way the compare value is moving +// +#define EPWM_CMP_UP 1 +#define EPWM_CMP_DOWN 0 + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 + // These functions are in the DSP2833x_EPwm.c file + // + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_isr; + PieVectTable.EPWM2_INT = &epwm2_isr; + PieVectTable.EPWM3_INT = &epwm3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // For this example, only initialize the ePWM + // + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + InitEPwm3Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + // + // Step 5. User specific code, enable interrupts + // + + // + // Enable CPU INT3 which is connected to EPWM1-3 INT + // + IER |= M_INT3; + + // + // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + // + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;) + { + __asm(" NOP"); + } +} + +// +// epwm1_isr - +// +__interrupt void +epwm1_isr(void) +{ + // + // Update the CMPA and CMPB values + // + update_compare(&epwm1_info); + + // + // Clear INT flag for this timer + // + EPwm1Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm2_isr - +// +__interrupt void +epwm2_isr(void) +{ + // + // Update the CMPA and CMPB values + // + update_compare(&epwm2_info); + + // + // Clear INT flag for this timer + // + EPwm2Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm3_isr - +// +__interrupt void +epwm3_isr(void) +{ + // + // Update the CMPA and CMPB values + // + update_compare(&epwm3_info); + + // + // Clear INT flag for this timer + // + EPwm3Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// InitEPwm1Example - +// +void +InitEPwm1Example() +{ + // + // Setup TBCLK + // + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2; + + // + // Setup shadow register load on ZERO + // + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // + // Set Compare values + // + EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value + EPwm1Regs.CMPB = EPWM1_MIN_CMPB; // Set Compare B value + + // + // Set actions + // + EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero + EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event A, up count + + EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero + EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, up count + + // + // Interrupt where we will change the Compare Values + // + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // + // Information this example uses to keep track of the direction the + // CMPA/CMPB values are moving, the min and max allowed values and + // a pointer to the correct ePWM registers + // + + // + // Start by increasing CMPA & CMPB + // + epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_UP; + + epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm1_info.EPwmRegHandle = &EPwm1Regs; //Set the pointer to the ePWM module + epwm1_info.EPwmMaxCMPA = EPWM1_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA; + epwm1_info.EPwmMaxCMPB = EPWM1_MAX_CMPB; + epwm1_info.EPwmMinCMPB = EPWM1_MIN_CMPB; +} + +// +// InitEPwm2Example - +// +void +InitEPwm2Example() +{ + // + // Setup TBCLK + // + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2; + + // + // Setup shadow register load on ZERO + // + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // + // Set Compare values + // + EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value + EPwm2Regs.CMPB = EPWM2_MAX_CMPB; // Set Compare B value + + // + // Set actions + // + EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count + + EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM2B on Period + EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM2B on event B, up count + + // + // Interrupt where we will change the Compare Values + // + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // + // Information this example uses to keep track of the direction the + // CMPA/CMPB values are moving, the min and max allowed values and + // a pointer to the correct ePWM registers + // + epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA + epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // and decreasing CMPB + epwm2_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm2_info.EPwmRegHandle = &EPwm2Regs; //Set the pointer to the ePWM module + epwm2_info.EPwmMaxCMPA = EPWM2_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm2_info.EPwmMinCMPA = EPWM2_MIN_CMPA; + epwm2_info.EPwmMaxCMPB = EPWM2_MAX_CMPB; + epwm2_info.EPwmMinCMPB = EPWM2_MIN_CMPB; +} + +// +// InitEPwm3Example - +// +void +InitEPwm3Example(void) +{ + // + // Setup TBCLK + // + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm3Regs.TBCTR = 0x0000; // Clear counter + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // + // Setup shadow register load on ZERO + // + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // + // Set Compare values + // + EPwm3Regs.CMPA.half.CMPA = EPWM3_MIN_CMPA; // Set compare A value + EPwm3Regs.CMPB = EPWM3_MAX_CMPB; // Set Compare B value + + // + // Set Actions + // + EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on event B, up count + EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR; // Clear PWM3A on event B, up count + + EPwm3Regs.AQCTLB.bit.ZRO = AQ_TOGGLE; // Toggle EPWM3B on Zero + + // + // Interrupt where we will change the Compare Values + // + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // + // Start by increasing the compare A and decreasing compare B + // + epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; + + // + // Start the count at 0 + // + epwm3_info.EPwmTimerIntCount = 0; + + epwm3_info.EPwmRegHandle = &EPwm3Regs; + epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA; + epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA; + epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB; + epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB; +} + +// +// update_compare - +// +void +update_compare(EPWM_INFO *epwm_info) +{ + // + // Every 10'th interrupt, change the CMPA/CMPB values + // + if(epwm_info->EPwmTimerIntCount == 10) + { + epwm_info->EPwmTimerIntCount = 0; + + // + // If we were increasing CMPA, check to see if we reached the max value + // If not, increase CMPA else, change directions and decrease CMPA + // + if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < + epwm_info->EPwmMaxCMPA) + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // + // If we were decreasing CMPA, check to see if we reached the min value + // If not, decrease CMPA else, change directions and increase CMPA + // + else + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA == + epwm_info->EPwmMinCMPA) + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // + // If we were increasing CMPB, check to see if we reached the max value + // If not, increase CMPB else, change directions and decrease CMPB + // + if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) + { + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPB--; + } + } + + // + // If we were decreasing CMPB, check to see if we reached the min value + // If not, decrease CMPB else, change directions and increase CMPB + // + else + { + if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwmRegHandle->CMPB--; + } + } + } + + else + { + epwm_info->EPwmTimerIntCount++; + } + + return; +} + +// +// End of File +// + diff --git a/f2833x/examples/epwm_updown_aq/.ccsproject b/f2833x/examples/epwm_updown_aq/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/epwm_updown_aq/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/epwm_updown_aq/.cproject b/f2833x/examples/epwm_updown_aq/.cproject new file mode 100644 index 0000000..c8e8793 --- /dev/null +++ b/f2833x/examples/epwm_updown_aq/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/epwm_updown_aq/.project b/f2833x/examples/epwm_updown_aq/.project new file mode 100644 index 0000000..9f0afd8 --- /dev/null +++ b/f2833x/examples/epwm_updown_aq/.project @@ -0,0 +1,103 @@ + + + Example_2833xEPwmUpDownAQ + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.c b/f2833x/examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.c new file mode 100644 index 0000000..619ebfc --- /dev/null +++ b/f2833x/examples/epwm_updown_aq/Example_2833xEPwmUpDownAQ.c @@ -0,0 +1,601 @@ +//########################################################################### +// +// FILE: Example_2833xEPwmUpDownAQ.c +// +// TITLE: ePWM Action Qualifier Module using up/down count Example +// +//! \addtogroup f2833x_example_list +//!

ePWM Action Qualifier Module using up/down count (epwm_updown_aq)

+//! +//! This example configures ePWM1, ePWM2, ePWM3 to produce an waveform with +//! independent modulation on EPWMxA and EPWMxB. The compare values CMPA +//! and CMPB are modified within the ePWM's ISR. The TB counter is in up/down +//! count mode for this example. +//! +//! Monitor ePWM1-ePWM3 pins on an oscilloscope as described +//! +//! \b External \b Connections \n +//! - EPWM1A is on GPIO0 +//! - EPWM1B is on GPIO1 +//! - EPWM2A is on GPIO2 +//! - EPWM2B is on GPIO3 +//! - EPWM3A is on GPIO4 +//! - EPWM3B is on GPIO5 +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Typedefs +// +typedef struct +{ + volatile struct EPWM_REGS *EPwmRegHandle; + Uint16 EPwm_CMPA_Direction; + Uint16 EPwm_CMPB_Direction; + Uint16 EPwmTimerIntCount; + Uint16 EPwmMaxCMPA; + Uint16 EPwmMinCMPA; + Uint16 EPwmMaxCMPB; + Uint16 EPwmMinCMPB; +} EPWM_INFO; + +// +// Function Prototypes +// +void InitEPwm1Example(void); +void InitEPwm2Example(void); +void InitEPwm3Example(void); +__interrupt void epwm1_isr(void); +__interrupt void epwm2_isr(void); +__interrupt void epwm3_isr(void); +void update_compare(EPWM_INFO*); + +// +// Globals +// +EPWM_INFO epwm1_info; +EPWM_INFO epwm2_info; +EPWM_INFO epwm3_info; + +// +// Defines that configure the period for each timer +// +#define EPWM1_TIMER_TBPRD 2000 // Period register +#define EPWM1_MAX_CMPA 1950 +#define EPWM1_MIN_CMPA 50 +#define EPWM1_MAX_CMPB 1950 +#define EPWM1_MIN_CMPB 50 + +#define EPWM2_TIMER_TBPRD 2000 // Period register +#define EPWM2_MAX_CMPA 1950 +#define EPWM2_MIN_CMPA 50 +#define EPWM2_MAX_CMPB 1950 +#define EPWM2_MIN_CMPB 50 + +#define EPWM3_TIMER_TBPRD 2000 // Period register +#define EPWM3_MAX_CMPA 950 +#define EPWM3_MIN_CMPA 50 +#define EPWM3_MAX_CMPB 1950 +#define EPWM3_MIN_CMPB 1050 + +// +// Defines to keep track of which way the compare value is moving +// +#define EPWM_CMP_UP 1 +#define EPWM_CMP_DOWN 0 + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 + // These functions are in the DSP2833x_EPwm.c file + // + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_isr; + PieVectTable.EPWM2_INT = &epwm2_isr; + PieVectTable.EPWM3_INT = &epwm3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // For this example, only initialize the ePWM + // + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + InitEPwm1Example(); + InitEPwm2Example(); + InitEPwm3Example(); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + // + // Step 5. User specific code, enable interrupts + // + + // + // Enable CPU INT3 which is connected to EPWM1-3 INT + // + IER |= M_INT3; + + // + // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + // + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;) + { + __asm(" NOP"); + } +} + +// +// epwm1_isr - +// +__interrupt void +epwm1_isr(void) +{ + // + // Update the CMPA and CMPB values + // + update_compare(&epwm1_info); + + // + // Clear INT flag for this timer + // + EPwm1Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm2_isr - +// +__interrupt void +epwm2_isr(void) +{ + // + // Update the CMPA and CMPB values + // + update_compare(&epwm2_info); + + // + // Clear INT flag for this timer + // + EPwm2Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm3_isr - +// +__interrupt void +epwm3_isr(void) +{ + // + // Update the CMPA and CMPB values + // + update_compare(&epwm3_info); + + // + // Clear INT flag for this timer + // + EPwm3Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// InitEPwm1Example - +// +void +InitEPwm1Example() +{ + // + // Setup TBCLK + // + EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs + EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm1Regs.TBCTR = 0x0000; // Clear counter + + // + // Set Compare values + // + EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value + EPwm1Regs.CMPB = EPWM1_MAX_CMPB; // Set Compare B value + + // + // Setup counter mode + // + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // + // Setup shadowing + // + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // + // Set actions + // + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; //Clear PWM1A on event A, down count + + EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event B, up count + EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM1B on event B, down count + + // + // Interrupt where we will change the Compare Values + // + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // + // Information this example uses to keep track of the direction the + // CMPA/CMPB values are moving, the min and max allowed values and + // a pointer to the correct ePWM registers + // + epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & + epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // decreasing CMPB + + epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm1_info.EPwmRegHandle = &EPwm1Regs; //Set the pointer to the ePWM module + epwm1_info.EPwmMaxCMPA = EPWM1_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA; + epwm1_info.EPwmMaxCMPB = EPWM1_MAX_CMPB; + epwm1_info.EPwmMinCMPB = EPWM1_MIN_CMPB; +} + +// +// InitEPwm2Example - +// +void +InitEPwm2Example() +{ + // + // Setup TBCLK + // + EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period 801 TBCLKs + EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm2Regs.TBCTR = 0x0000; // Clear counter + + // + // Set Compare values + // + EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value + EPwm2Regs.CMPB = EPWM2_MIN_CMPB; // Set Compare B value + + // + // Setup counter mode + // + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // + // Setup shadowing + // + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // + // Set actions + // + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count + EPwm2Regs.AQCTLA.bit.CBD = AQ_CLEAR; // Clear PWM2A on event B, down count + + EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Clear PWM2B on zero + EPwm2Regs.AQCTLB.bit.PRD = AQ_SET ; // Set PWM2B on period + + // + // Interrupt where we will change the Compare Values + // + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // + // Information this example uses to keep track of the direction the + // CMPA/CMPB values are moving, the min and max allowed values and a + // pointer to the correct ePWM registers + // + epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & + epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_UP; // increasing CMPB + epwm2_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm2_info.EPwmRegHandle = &EPwm2Regs; //Set the pointer to the ePWM module + epwm2_info.EPwmMaxCMPA = EPWM2_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm2_info.EPwmMinCMPA = EPWM2_MIN_CMPA; + epwm2_info.EPwmMaxCMPB = EPWM2_MAX_CMPB; + epwm2_info.EPwmMinCMPB = EPWM2_MIN_CMPB; +} + +// +// InitEPwm3Example - +// +void +InitEPwm3Example(void) +{ + // + // Setup TBCLK + // + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count up/down + EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading + EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 + EPwm3Regs.TBCTR = 0x0000; // Clear counter + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + // + // Setup shadow register load on ZERO + // + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + + // + // Set Compare values + // + EPwm3Regs.CMPA.half.CMPA = EPWM3_MIN_CMPA; // Set compare A value + EPwm3Regs.CMPB = EPWM3_MAX_CMPB; // Set Compare B value + + // + // Set Actions + // + EPwm3Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM3A on period + EPwm3Regs.AQCTLA.bit.CBD = AQ_CLEAR; // Clear PWM3A on event B, down count + + EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM3A on period + EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM3A on event A, up count + + // + // Interrupt where we will change the Compare Values + // + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + // + // Information this example uses to keep track of the direction the + // CMPA/CMPB values are moving, the min and max allowed values and + // a pointer to the correct ePWM registers + // + epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & + epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // decreasing CMPB + epwm3_info.EPwmTimerIntCount = 0; // Zero the interrupt counter + epwm3_info.EPwmRegHandle = &EPwm3Regs; //Set the pointer to the ePWM module + epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA; // Setup min/max CMPA/CMPB values + epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA; + epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB; + epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB; +} + +// +// update_compare - +// +void +update_compare(EPWM_INFO *epwm_info) +{ + // + // Every 10'th interrupt, change the CMPA/CMPB values + // + if(epwm_info->EPwmTimerIntCount == 10) + { + epwm_info->EPwmTimerIntCount = 0; + + // + // If we were increasing CMPA, check to see if we reached the max value + // If not, increase CMPA else, change directions and decrease CMPA + // + if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < + epwm_info->EPwmMaxCMPA) + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // + // If we were decreasing CMPA, check to see if we reached the min value + // If not, decrease CMPA else, change directions and increase CMPA + // + else + { + if(epwm_info->EPwmRegHandle->CMPA.half.CMPA == + epwm_info->EPwmMinCMPA) + { + epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPA.half.CMPA++; + } + else + { + epwm_info->EPwmRegHandle->CMPA.half.CMPA--; + } + } + + // + // If we were increasing CMPB, check to see if we reached the max value + // If not, increase CMPB else, change directions and decrease CMPB + // + if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) + { + if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) + { + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; + epwm_info->EPwmRegHandle->CMPB--; + } + } + + // + // If we were decreasing CMPB, check to see if we reached the min value + // If not, decrease CMPB else, change directions and increase CMPB + // + else + { + if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) + { + epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; + epwm_info->EPwmRegHandle->CMPB++; + } + else + { + epwm_info->EPwmRegHandle->CMPB--; + } + } + } + + else + { + epwm_info->EPwmTimerIntCount++; + } + + return; +} + +// +// End of File +// + diff --git a/f2833x/examples/eqep_freqcal/.ccsproject b/f2833x/examples/eqep_freqcal/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/eqep_freqcal/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/eqep_freqcal/.cproject b/f2833x/examples/eqep_freqcal/.cproject new file mode 100644 index 0000000..c678440 --- /dev/null +++ b/f2833x/examples/eqep_freqcal/.cproject @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/eqep_freqcal/.project b/f2833x/examples/eqep_freqcal/.project new file mode 100644 index 0000000..94c5172 --- /dev/null +++ b/f2833x/examples/eqep_freqcal/.project @@ -0,0 +1,103 @@ + + + Example_2833xEqep_freqcal + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_EQep.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EQep.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/eqep_freqcal/Example_2833xEqep_freqcal.c b/f2833x/examples/eqep_freqcal/Example_2833xEqep_freqcal.c new file mode 100644 index 0000000..fd37a65 --- /dev/null +++ b/f2833x/examples/eqep_freqcal/Example_2833xEqep_freqcal.c @@ -0,0 +1,230 @@ +//########################################################################### +// +// FILE: Example_2833xEqep_freqcal.c +// +// TITLE: eQEP, Frequency measurement Example +// +//! \addtogroup f2833x_example_list +//!

eQEP, Frequency measurement (eqep_freqcal)

+//! +//! This test will calculate the frequency and period of an input signal +//! using eQEP module. +//! +//! EPWM1A is configured to generate a frequency of 5 kHz. +//! \sa section on Frequency Calculation for more details on the frequency +//! calculation performed in this example. +//! +//! In addition to the main example file, the following files must be included +//! in this project: +//! - \b Example_freqcal.c , includes all eQEP functions +//! - \b Example_EPwmSetup.c , sets up EPWM1A for use with this example +//! - \b Example_freqcal.h , includes initialization values for frequency +//! structure. +//! +//! The configuration for this example is as follows +//! - Maximum frequency is configured to 10KHz (BaseFreq) +//! - Minimum frequency is assumed at 50Hz for capture pre-scalar selection +//! +//! \b SPEED_FR: High Frequency Measurement is obtained by counting the +//! external input pulses for 10ms (unit timer set to 100Hz). +//! \f[ SPEED\_FR = \frac{Count\ Delta}{10ms} \f] +//! +//! \b SPEED_PR: Low Frequency Measurement is obtained by measuring time +//! period of input edges. +//! Time measurement is averaged over 64edges for better results and +//! capture unit performs the time measurement using pre-scaled SYSCLK +//! +//! Note that pre-scaler for capture unit clock is selected such that +//! capture timer does not overflow at the required minimum frequency +//! This example runs forever until the user stops it. +//! +//! \b External \b Connections \n +//! - Connect GPIO20/EQEP1A to GPIO0/EPWM1A +//! +//! \b Watch \b Variables \n +//! - \b freq.freqhz_fr , Frequency measurement using position counter/unit +//! time out +//! - \b freq.freqhz_pr , Frequency measurement using capture unit +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_freqcal.h" // Example specific include file + +// +// Function Prototypes +// +void EPwmSetup(void); +__interrupt void prdTick(void); + +// +// Globals +// +FREQCAL freq=FREQCAL_DEFAULTS; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Only init the GPIO for EQep1 and EPwm1 in this case + // This function is found in DSP2833x_EQep.c + // + InitEQep1Gpio(); + InitEPwm1Gpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT= &prdTick; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // + + // + // Example specific ePWM setup. This function is found in + // Example_EPwmSetup.c + // + EPwmSetup(); + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Enable CPU INT1 which is connected to CPU-Timer 0: + // + IER |= M_INT3; + + // + // Enable TINT0 in the PIE: Group 3 interrupt 1 + // + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Initializes eQEP for frequency calculation in FREQCAL_Init(void)function + // in Example_EPwmSetup.c + // + freq.init(&freq); + + for(;;) + { + + } +} + +// +// prdTick - Interrupts once per ePWM period +// +__interrupt void +prdTick(void) +{ + // + // Checks for event and calculates frequency in FREQCAL_Calc(FREQCAL *p) + // function in Example_EPwmSetup.c + // + freq.calc(&freq); + + // + // Acknowledge this interrupt to receive more interrupts from group 1 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + EPwm1Regs.ETCLR.bit.INT=1; +} + +// +// End of File +// + diff --git a/f2833x/examples/eqep_freqcal/Example_EPwmSetup.c b/f2833x/examples/eqep_freqcal/Example_EPwmSetup.c new file mode 100644 index 0000000..82b731a --- /dev/null +++ b/f2833x/examples/eqep_freqcal/Example_EPwmSetup.c @@ -0,0 +1,116 @@ +//########################################################################### +// +// FILE: Example_EpwmSetup.c +// +// TITLE: EXAMPLE_EPWMSETUP_C EPWM Setup Example +// +//! \addtogroup f2833x_example_list +//! \section EXAMPLE_EPWMSETUP_C EPWM Setup (Example_EPwmSetup.c) +//! +//! This file contains source for the ePWM initialization for the +//! freq calculation module. EPWM1 is set to operate in up-down count +//! mode at a frequency of 5KHz +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_freqcal.h" // Example specific include file + +// +// Defines +// +#if (CPU_FRQ_150MHZ) + #define CPU_CLK 150e6 +#endif +#if (CPU_FRQ_100MHZ) + #define CPU_CLK 100e6 +#endif +#define PWM_CLK 5e3 // If a diff frequency is desired, change freq here +#define SP CPU_CLK/(2*PWM_CLK) +#define TBCTLVAL 0x200E // Up-down cnt, timebase = SYSCLKOUT + +// +// EPwmSetup +// +void +EPwmSetup() +{ + InitEPwm1Gpio(); + EPwm1Regs.TBSTS.all=0; + EPwm1Regs.TBPHS.half.TBPHS=0; + EPwm1Regs.TBCTR=0; + + EPwm1Regs.CMPCTL.all=0x50; // Immediate mode for CMPA and CMPB + EPwm1Regs.CMPA.half.CMPA =SP/2; + EPwm1Regs.CMPB=0; + + EPwm1Regs.AQCTLA.all=0x60; // EPWMxA = 1 when CTR=CMPA and counter inc + // EPWMxA = 0 when CTR=CMPA and counter dec + EPwm1Regs.AQCTLB.all=0; + EPwm1Regs.AQSFRC.all=0; + EPwm1Regs.AQCSFRC.all=0; + + EPwm1Regs.DBCTL.all=0xb; // EPWMxB is inverted + EPwm1Regs.DBRED=0; + EPwm1Regs.DBFED=0; + + EPwm1Regs.TZSEL.all=0; + EPwm1Regs.TZCTL.all=0; + EPwm1Regs.TZEINT.all=0; + EPwm1Regs.TZFLG.all=0; + EPwm1Regs.TZCLR.all=0; + EPwm1Regs.TZFRC.all=0; + + EPwm1Regs.ETSEL.all=9; // Interrupt when TBCTR = 0x0000 + EPwm1Regs.ETPS.all=1; // Interrupt on first event + EPwm1Regs.ETFLG.all=0; + EPwm1Regs.ETCLR.all=0; + EPwm1Regs.ETFRC.all=0; + + EPwm1Regs.PCCTL.all=0; + + EPwm1Regs.TBCTL.all=0x0010+TBCTLVAL; // Enable Timer + EPwm1Regs.TBPRD=SP; +} + +// +// End of File +// + diff --git a/f2833x/examples/eqep_freqcal/Example_freqcal.c b/f2833x/examples/eqep_freqcal/Example_freqcal.c new file mode 100644 index 0000000..7ea2fd0 --- /dev/null +++ b/f2833x/examples/eqep_freqcal/Example_freqcal.c @@ -0,0 +1,271 @@ +//########################################################################### +// +// FILE: Example_freqcal.c +// +// TITLE: EXAMPLE_FREQCAL_C Frequency Calculation +// +//! \addtogroup f2833x_example_list +//! \section EXAMPLE_FREQCAL_C Frequency Calculation (Example_freqal.c) +//! +//! This file includes the EQEP initialization and frequency calculation +//! functions called by \b Example_2833xEqep_freqcal.c. +//! The frequency calculation steps performed by FREQCAL_Calc()at +//! SYSCLKOUT = 150 MHz and 100 MHZ are described below: +//! +//! -# This program calculates: \b **freqhz_fr** for SYSCLKOUT = 150MHz \n +//! \f[ freqhz\_fr\ or\ v = \frac{x_{2}-x_{1}}{T} .......... 1 \f] \n +//! If \f[ \frac{max}{base}\ freq = 10kHz => 10kHz = \ +\frac{x_{2}-x_{1}}{(2/100Hz)} .......... 2\f] \n +//! \f[ max (x_{2}-x_{1}) = 200 counts = freqScaler\_fr \f] +//! +//! \note \f$ T = \frac{2}{100Hz} \f$ . 2 is from \f$ \frac{x_{2}-x_{1}}{2}\f$ +//! because QPOSCNT counts 2 edges per cycle (rising and falling) +//! +//! If both sides of Equation 2 are divided by 10 kHz, then: \n +//! \f[ 1 = \frac{x_{2}-x_{1}}{10kHz*(2/100Hz)}\f]\n where, +//! \f[ [10kHz*\frac{2}{100Hz}] = 200 \f]\n +//! Because \f[ x_{2}-x_{1} < 200 (max)\f] +//! \f[ \frac{x_{2}-x_{1}}{200} < 1 \f]\n for all frequencies less than max\n +//! \f[ freq\_fr = \frac{x_{2}-x_{1}}{200}\ or\ \ +\frac{x_{2}-x_{1}}{10kHz*(2/100Hz)} .......... 3\f] \n +//! +//! To get back to original velocity equation, Equation 1, multiply +//! Equation 3 by 10 kHz\n +//! \f[ freqhz\_fr(or\ velocity) = \ +10kHz*\frac{x_{2}-x_{1}}{10kHz*(2/100Hz)}\f]\n +//! \f[ = \frac{x_{2}-x_{1}}{(2/100Hz)} .......... final\ equation\f] \n +//! +//! -# \b **min \b freq** \f$ = \frac{1\ count}{(2/100Hz)} = 50 Hz\f$ +//! -# \b **freqhz_pr** \n +//! \f[ freqhz\_pr\ or\ v = \frac{X}{t_{2}-t_{1}} .......... 4\f] \n +//! If \f[ \frac{max}{base}\ freq = 10kHz => 10kHz = \frac{(4/2)}{T} = \ +\frac{4}{2T} \f] \n +//! where, +//! - 4 = QCAPCTL [UPPS] (Unit timeout - once every 4 edges) +//! - 2 = divide by 2 because QPOSCNT counts 2 edges per cycle +//! (rising and falling) +//! - T = time in seconds +//! = \f$ \frac{t_{2}-t_{1}}{(150MHz/128)}, t_{2}-t_{1} \f$ = +//! # of QCAPCLK cycles, +//! \n and \f$ 1\ QCAPCLK\ cycle = \frac{1}{(150MHz/128)} = QCPRDLAT \f$ +//! +//! So: \f[ 10 kHz = 4*\frac{(150MHz/128)}{2*(t_{2}-t_{1})} \f] \n +//! \f[ t_{2}-t_{1} = 4*\frac{(150MHz/128)}{10kHz*2} = \ +\frac{(150MHz/128)}{((2*10KHz)/4)} .......... 5\f] \n +//! \f[ = 234\ QCAPCLK\ cycles = maximum (t_{2}-t_{1}) = freqScaler\_pr \f] +//! Divide both sides by \f$ (t_{2}-t_{1}) \f$, and:\n +//! \f[ 1 = \frac{234}{t_{2}-t_{1}} = \ +\frac{(150MHz/128)/((2*10KHz)/4)}{t_{2}-t_{1}} \f]\n +//! Because \f$ (t_{2}-t_{1}) < 234 (max) \f$, +//! \f$ \frac{234}{t_{2}-t_{1}} < 1 \f$ for all frequencies less than max \n +//! \f[ freq\_pr = \frac{234}{t_{2}-t_{1}}\ or\ \ +\frac{(150MHz/128)/((2*10KHz)/4)}{t_{2}-t_{1}} .......... 6\f] \n +//! Now within velocity limits, to get back to original velocity equation, +//! Equation 1, multiply Equation 6 by 10 kHz: \n +//! \f[ freqhz\_fr(or\ velocity) = \ +10kHz*\frac{(150MHz/128)/((2*10KHz)/4)}{t_{2}-t_{1}}\f]\n +//! \f[ = \frac{(150MHz/128)*4}{2*(t_{2}-t_{1})} \f]\n +//! or +//! \f[ \frac{4}{2*(t_{2}-t_{1})*(QCPRDLAT)} .......... final\ equation\f] \n +//! +//! For 100 MHz Operation: +//! +//! The same calculations as above are performed, but with 100 MHz +//! instead of 150MHz when calculating freqhz_pr, and at UPPS of 8 +//! instead of 4. The value for freqScaler_pr becomes: +//! (100MHz/128)/(2*10kHz/8) = 313 +//! +//! More detailed calculation results can be found in the Example_freqcal.xls +//! spreadsheet included in the example folder. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_freqcal.h" // Example specific include file + +// +// FREQCAL_Init - +// +void +FREQCAL_Init(void) +{ +#if (CPU_FRQ_150MHZ) + EQep1Regs.QUPRD=1500000; // Unit Timer for 100Hz at 150MHz SYSCLKOUT +#endif +#if (CPU_FRQ_100MHZ) + EQep1Regs.QUPRD=1000000; // Unit Timer for 100Hz at 100MHz SYSCLKOUT +#endif + + EQep1Regs.QDECCTL.bit.QSRC=2; // Up count mode (freq. measurement) + EQep1Regs.QDECCTL.bit.XCR=0; + + EQep1Regs.QEPCTL.bit.FREE_SOFT=2; + EQep1Regs.QEPCTL.bit.PCRM=00; // QPOSCNT reset on index evnt + EQep1Regs.QEPCTL.bit.UTE=1; // Unit Timer Enable + EQep1Regs.QEPCTL.bit.QCLM=1; // Latch on unit time out + EQep1Regs.QPOSMAX=0xffffffff; + EQep1Regs.QEPCTL.bit.QPEN=1; // QEP enable + +#if (CPU_FRQ_150MHZ) + EQep1Regs.QCAPCTL.bit.UPPS=2; // 1/4 for unit position at 150MHz SYSCLKOUT +#endif +#if (CPU_FRQ_100MHZ) + EQep1Regs.QCAPCTL.bit.UPPS=3; // 1/8 for unit position at 100MHz SYSCLKOUT +#endif + + EQep1Regs.QCAPCTL.bit.CCPS=7; // 1/128 for CAP clock + EQep1Regs.QCAPCTL.bit.CEN=1; // QEP Capture Enable +} + +// +// FREQCAL_Calc - +// +void +FREQCAL_Calc(FREQCAL *p) +{ + unsigned long tmp; + _iq newp,oldp; + + // + // Freq Calculation using QEP position counter + // Check unit Time out-event for speed calculation + // + + // + // Unit Timer is configured for 100Hz in INIT function + // + + // + // For a more detailed explanation of the calculation, read + // the description at the top of this file + // + if(EQep1Regs.QFLG.bit.UTO==1) // Unit Timeout event + { + // + // Differentiator + // + newp=EQep1Regs.QPOSLAT; // Latched POSCNT value + oldp=p->oldpos; + + if (newp>oldp) + { + tmp = newp - oldp; // x2-x1 in v=(x2-x1)/T equation + } + else + { + tmp = (0xFFFFFFFF-oldp)+newp; + } + + // + // p->freq_fr = (x2-x1)/(T*10KHz) + // + p->freq_fr = _IQdiv(tmp,p->freqScaler_fr); + tmp=p->freq_fr; + + if (tmp>=_IQ(1)) + { + p->freq_fr = _IQ(1); + } + else + { + p->freq_fr = tmp; + } + + // + // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + // p->freqhz_fr = (p->freq_fr)*10kHz = (x2-x1)/T + // + p->freqhz_fr = _IQmpy(p->BaseFreq,p->freq_fr); + + // + // Update position counter + // + p->oldpos = newp; + + EQep1Regs.QCLR.bit.UTO=1; // Clear interrupt flag + } + + // + // Freq Calculation using QEP capture counter + // + if(EQep1Regs.QEPSTS.bit.UPEVNT==1) // Unit Position Event + { + if(EQep1Regs.QEPSTS.bit.COEF==0) // No Capture overflow + { + tmp=(unsigned long)EQep1Regs.QCPRDLAT; + } + else // Capture overflow, saturate the result + { + tmp=0xFFFF; + } + + // + // p->freq_pr = X/[(t2-t1)*10KHz] + // + p->freq_pr = _IQdiv(p->freqScaler_pr,tmp); + tmp=p->freq_pr; + + if (tmp>_IQ(1)) + { + p->freq_pr = _IQ(1); + } + else + { + p->freq_pr = tmp; + } + + // + // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + // p->freqhz_pr =( p->freq_pr)*10kHz = X/(t2-t1) + // + p->freqhz_pr = _IQmpy(p->BaseFreq,p->freq_pr); + + // + // Clear Unit position event flag + // Clear overflow error flag + // + EQep1Regs.QEPSTS.all=0x88; + } +} + +// +// End of File +// + diff --git a/f2833x/examples/eqep_freqcal/Example_freqcal.h b/f2833x/examples/eqep_freqcal/Example_freqcal.h new file mode 100644 index 0000000..bae1766 --- /dev/null +++ b/f2833x/examples/eqep_freqcal/Example_freqcal.h @@ -0,0 +1,153 @@ +//########################################################################### +// +// FILE: Example_freqcal.h +// +// TITLE: Frequency measurement using EQEP peripheral +// +// DESCRIPTION: Header file containing data type and object definitions and +// initializers. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __FREQCAL__ +#define __FREQCAL__ + +// +// Included Files +// +#include "IQmathLib.h" // Include header for IQmath library + +// +// Typedef structure of the FREQCAL Object +// +typedef struct +{ + // + // Scaler converting 1/N cycles to a GLOBAL_Q freq (Q0) + // independently with global Q + // + Uint32 freqScaler_pr; + + // + // Scaler converting 1/N cycles to a GLOBAL_Q freq (Q0) + // independently with global Q + // + Uint32 freqScaler_fr; + Uint32 BaseFreq; // Parameter : Maximum Freq + _iq freq_pr; // Output : Freq in per-unit using capture unit + int32 freqhz_pr; // Output: Freq in Hz, measured using Capture unit + Uint32 oldpos; + _iq freq_fr; // Output : Freq in per-unit using position counter + int32 freqhz_fr; // Output: Freq in Hz, measured using Capture unit + void (*init)(); // Pointer to the init function + void (*calc)(); // Pointer to the calc function +} FREQCAL; + +// +// Define for a QEP_handle +// +typedef FREQCAL *FREQCAL_handle; + +// +// Default initializer for the FREQCAL Object +// +#if (CPU_FRQ_150MHZ) + #define FREQCAL_DEFAULTS {\ + 234,200,10000,0,0,\ + 0,0,0,\ + (void (*)(long))FREQCAL_Init,\ + (void (*)(long))FREQCAL_Calc } +#endif +#if (CPU_FRQ_100MHZ) + #define FREQCAL_DEFAULTS {\ + 313,200,10000,0,0,\ + 0,0,0,\ + (void (*)(long))FREQCAL_Init,\ + (void (*)(long))FREQCAL_Calc } +#endif + +// +// Function Prototypes +// +void FREQCAL_Init(void); +void FREQCAL_Calc(FREQCAL_handle); + +#endif /* __FREQCAL__ */ + +// +// For 150 MHz Operation: +// +// 1. freqScaler_fr +// v = (x2-x1)/T - Equation 1 +// +// If max/base freq = 10kHz: 10kHz = (x2-x1)/(2/100Hz) - Equation 2 +// max (x2-x1) = 200 counts = freqScaler_fr +// Note: T = 2/100Hz. 2 is from (x2-x1)/2 - because QPOSCNT counts +// 2 edges per cycle (rising and falling) +// freqhz_fr = 200 default +// +// 2. min freq = 1 count/(2/100Hz) = 50 Hz +// +// 3. freqScaler_pr +// v = X/(t2-t1) - Equation 4 +// +// If max/base freq = 10kHz: 10kHz = 8/(2T) +// where 4 = QCAPCTL [UPPS] (Unit timeout - once every 4 edges) +// T = time in seconds = t2-t1/(150MHz/128), +// t2-t1= # of QCAPCLK cycles, and +// 1 QCAPCLK cycle = 1/(150MHz/128) = QCPRDLAT +// +// So: 10 kHz = 4(150MHz/128)/2(t2-t1) +// Equation 5 +// t2-t1 = 4(150MHz/128)/(10kHz*2) = (150MHz/128)/(2*10kHz/4) +// = 234 seconds = maximum (t2-t1) = freqScaler_pr +// freqhz_pr = 234 default +// +// +// For 100 MHz Operation: +// +// The same calculations as above are performed, but with 100 MHz +// instead of 150MHz when calculation freqhr_pr, and at UPPS of 8 instead +// of 4. The value for freqScaler_pr becomes: (100MHz/128)/(2*10kHz/8) = 313 +// More detailed calculation results can be found in the Example_freqcal.xls +// spreadsheet included in the example folder. +// + +// +// End of File +// + diff --git a/f2833x/examples/eqep_freqcal/Example_freqcal.xls b/f2833x/examples/eqep_freqcal/Example_freqcal.xls new file mode 100644 index 0000000..a7128d2 Binary files /dev/null and b/f2833x/examples/eqep_freqcal/Example_freqcal.xls differ diff --git a/f2833x/examples/eqep_pos_speed/.ccsproject b/f2833x/examples/eqep_pos_speed/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/eqep_pos_speed/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/eqep_pos_speed/.cproject b/f2833x/examples/eqep_pos_speed/.cproject new file mode 100644 index 0000000..f8e2a4c --- /dev/null +++ b/f2833x/examples/eqep_pos_speed/.cproject @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/eqep_pos_speed/.project b/f2833x/examples/eqep_pos_speed/.project new file mode 100644 index 0000000..682096d --- /dev/null +++ b/f2833x/examples/eqep_pos_speed/.project @@ -0,0 +1,103 @@ + + + Example_2833xEqep_pos_speed + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_EQep.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EQep.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/eqep_pos_speed/Example_2833xEqep_pos_speed.c b/f2833x/examples/eqep_pos_speed/Example_2833xEqep_pos_speed.c new file mode 100644 index 0000000..48e983a --- /dev/null +++ b/f2833x/examples/eqep_pos_speed/Example_2833xEqep_pos_speed.c @@ -0,0 +1,272 @@ +//########################################################################### +// +// FILE: Example_2833xEqep_pos_speed.c +// +// TITLE: eQEP Speed and Position measurement Example +// +//! \addtogroup f2833x_example_list +//!

eQEP Speed and Position measurement (eqep_pos_speed)

+//! +//! This example provides position measurement,speed measurement using the +//! capture unit, and speed measurement using unit time out. This example +//! uses the IQMath library. It is used merely to simplify high-precision +//! calculations. \n +//! The example requires the following hardware connections from EPWM1 and +//! GPIO pins (simulating QEP sensor) to QEP peripheral. +//! - eQEP1A <- ePWM1A (simulates eQEP Phase A signal) +//! - eQEP1B <- ePWM1B (simulates eQEP Phase B signal) +//! - eQEP1I <- GPIO4 (simulates eQEP Index Signal) +//! +//! See DESCRIPTION in Example_posspeed.c for more details on the calculations +//! performed in this example. +//! In addition to this file, the following files must be included in this +//! project: +//! - Example_posspeed.c - includes all eQEP functions +//! - Example_EPwmSetup.c - sets up ePWM1A and ePWM1B as simulated QA and QB +//! encoder signals +//! - Example_posspeed.h - includes initialization values for pos and speed +//! structure +//! +//! Note: +//! - Maximum speed is configured to 6000rpm(BaseRpm) +//! - Minimum speed is assumed at 10rpm for capture pre-scalar selection +//! - Pole pair is configured to 2 (pole_pairs) +//! - QEP Encoder resolution is configured to 4000counts/revolution +//! (mech_scaler) +//! - which means: 4000/4 = 1000 line/revolution quadrature encoder +//! (simulated by EPWM1) +//! - EPWM1 (simulating QEP encoder signals) is configured for 5kHz +//! frequency or 300 rpm (=4*5000 cnts/sec * 60 sec/min)/4000 cnts/rev) +//! - SPEEDRPM_FR: High Speed Measurement is obtained by counting the QEP +//! input pulses for 10ms (unit timer set to 100Hz). +//! - SPEEDRPM_FR = (Position Delta/10ms) * 60 rpm +//! - SPEEDRPM_PR: Low Speed Measurement is obtained by measuring time +//! period of QEP edges. Time measurement is averaged over +//! 64edges for better results and capture unit performs the +//! time measurement using pre-scaled SYSCLK +//! - pre-scaler for capture unit clock is selected such that capture timer +//! does not overflow at the required minimum RPM speed. +//! +//! \b External \b Connections \n +//! - Connect eQEP1A(GPIO20) to ePWM1A(GPIO0)(simulates eQEP Phase A signal) +//! - Connect eQEP1B(GPIO21) to ePWM1B(GPIO1)(simulates eQEP Phase B signal) +//! - Connect eQEP1I(GPIO23) to GPIO4 (simulates eQEP Index Signal) +//! +//! \b Watch \b Variables \n +//! - qep_posspeed.SpeedRpm_fr - Speed meas. in rpm using QEP position counter +//! - qep_posspeed.SpeedRpm_pr - Speed meas. in rpm using capture unit +//! - qep_posspeed.theta_mech - Motor mechanical angle (Q15) +//! - qep_posspeed.theta_elec - Motor electrical angle (Q15) +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_posspeed.h" // Example specific Include file + +// +// Function Prototypes +// +void initEpwm(); +__interrupt void prdTick(void); + +// +// Globals +// +POSSPEED qep_posspeed=POSSPEED_DEFAULTS; +Uint16 Interrupt_Count = 0; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this case only init GPIO for eQEP1 and ePWM1 + // This function is found in DSP2833x_EQep.c + // + InitEQep1Gpio(); + InitEPwm1Gpio(); + EALLOW; + + // + // GPIO4 as output simulates Index signal + // + GpioCtrlRegs.GPADIR.bit.GPIO4 = 1; + + GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; // Normally low + EDIS; + + // + // Step 3. Clear all interrupts and initialize PIE vector table + // + + // + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT= &prdTick; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals + // + initEpwm(); // This function exists in Example_EPwmSetup.c + + // + // Step 5. User specific code, enable interrupts + // + + // + // Enable CPU INT1 which is connected to CPU-Timer 0 + // + IER |= M_INT3; + + // + // Enable TINT0 in the PIE: Group 3 interrupt 1 + // + PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + qep_posspeed.init(&qep_posspeed); + + for(;;) + { + + } +} + +// +// prdTick - EPWM1 Interrupts once every 4 QCLK counts (one period) +// +__interrupt void +prdTick(void) +{ + Uint16 i; + + // + // Position and Speed measurement + // + qep_posspeed.calc(&qep_posspeed); + + // + // Control loop code for position control & Speed control + // + Interrupt_Count++; + + // + // Every 1000 interrupts(4000 QCLK counts or 1 rev.) + // + if (Interrupt_Count==1000) + { + EALLOW; + + // + // Pulse Index signal (1 pulse/rev.) + // + GpioDataRegs.GPASET.bit.GPIO4 = 1; + for (i=0; i<700; i++) + { + + } + GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; + Interrupt_Count = 0; // Reset count + EDIS; + } + + // + // Acknowledge this interrupt to receive more interrupts from group 1 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + EPwm1Regs.ETCLR.bit.INT=1; +} + +// +// End of File +// + diff --git a/f2833x/examples/eqep_pos_speed/Example_EPwmSetup.c b/f2833x/examples/eqep_pos_speed/Example_EPwmSetup.c new file mode 100644 index 0000000..2529109 --- /dev/null +++ b/f2833x/examples/eqep_pos_speed/Example_EPwmSetup.c @@ -0,0 +1,118 @@ +//########################################################################### +// +// FILE: Example_EPwmSetup.c +// +// TITLE: EXAMPLE_EPWMSETUP_C EPWM Setup Example +// +//! \addtogroup f2833x_example_list +//! \section EXAMPLE_EPWMSETUP_C EPWM Setup (Example_EPwmSetup.c) +//! +//! This file contains source for the ePWM initialization for the +//! freq calculation module. EPWM1 is set to operate in up-down count +//! mode at a frequency of 5KHz +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_posspeed.h" // Example specific Include file + +// +// Defines +// +#if (CPU_FRQ_150MHZ) + #define CPU_CLK 150e6 +#endif +#if (CPU_FRQ_100MHZ) + #define CPU_CLK 100e6 +#endif + +// +// 5kHz (300rpm) EPWM1 frequency. Frequency can be changed here +// +#define PWM_CLK 5e3 +#define SP CPU_CLK/(2*PWM_CLK) +#define TBCTLVAL 0x200E // up-down count, timebase=SYSCLKOUT + +// +// initEpwm - +// +void +initEpwm() +{ + EPwm1Regs.TBSTS.all=0; + EPwm1Regs.TBPHS.half.TBPHS =0; + EPwm1Regs.TBCTR=0; + + EPwm1Regs.CMPCTL.all=0x50; // immediate mode for CMPA and CMPB + EPwm1Regs.CMPA.half.CMPA=SP/2; + EPwm1Regs.CMPB=0; + + // + // CTR=CMPA when inc->EPWM1A=1, when dec->EPWM1A=0 + // + EPwm1Regs.AQCTLA.all=0x60; + + EPwm1Regs.AQCTLB.all=0x09; // CTR=PRD ->EPWM1B=1, CTR=0 ->EPWM1B=0 + EPwm1Regs.AQSFRC.all=0; + EPwm1Regs.AQCSFRC.all=0; + + EPwm1Regs.TZSEL.all=0; + EPwm1Regs.TZCTL.all=0; + EPwm1Regs.TZEINT.all=0; + EPwm1Regs.TZFLG.all=0; + EPwm1Regs.TZCLR.all=0; + EPwm1Regs.TZFRC.all=0; + + EPwm1Regs.ETSEL.all=0x0A; // Interrupt on PRD + EPwm1Regs.ETPS.all=1; + EPwm1Regs.ETFLG.all=0; + EPwm1Regs.ETCLR.all=0; + EPwm1Regs.ETFRC.all=0; + + EPwm1Regs.PCCTL.all=0; + + EPwm1Regs.TBCTL.all=0x0010+TBCTLVAL; // Enable Timer + EPwm1Regs.TBPRD=SP; +} + +// +// End of File +// + diff --git a/f2833x/examples/eqep_pos_speed/Example_posspeed.c b/f2833x/examples/eqep_pos_speed/Example_posspeed.c new file mode 100644 index 0000000..be32110 --- /dev/null +++ b/f2833x/examples/eqep_pos_speed/Example_posspeed.c @@ -0,0 +1,347 @@ +//########################################################################### +// +// FILE: Example_posspeed.c +// +// TITLE: EXAMPLE_POSSPEED_C Position/Speed Calculation +// +//! \addtogroup f2833x_example_list +//! \section EXAMPLE_POSSPEED_C Position/Speed Calculation (Example_posspeed.c) +//! This file includes the EQEP initialization and position and speed +//! calculation functions called by Example_2833xEqep_posspeed.c. The position +//! and speed calculation steps performed by POSSPEED_Calc() at +//! SYSCLKOUT = 150 MHz and 100 MHz are described below: +//! +//! -# This program calculates: \b **theta_mech** for SYSCLKOUT = 150Mhz \n +//! \f[ theta\_mech\ = \frac{QPOSCNT}{mech\_scaler}= \frac {QPOSCNT}{4000} \f] +//! where 4000 is the number of +//! counts in 1 revolution.(4000/4 = 1000 line/rev. quadrature encoder) +//! -# This program calculates: \b **theta_elec** for SYSCLKOUT = 150MHz \n +//! \f[ theta\_elec\ = (# pole pairs) * theta\_mech\ = \ +\frac {2*QPOSCNT}{4000} \f] +//! -# This program calculates: \b **SpeedRpm_fr** for SYSCLKOUT = 150Mhz \n +//! \f[ SpeedRpm\_fr\ = \frac {x_{2}-x_{1}}{4000*T}........1 \f] +//! +//! \note \f$ x_{2}-x_{1} \f$ is the difference in number of QPOSCNT counts. +//! Dividing \f$ x_{2}-x_{1} \f$ by +//! \f$ 4000 \f$ gives position relative to Index in one revolution. \n +//! +//! If \f$ base RPM = 6000 rpm \f$ : +//! \f[ 6000 rpm = \frac {x_{2}-x_{1}}{4000*10ms}........2 \f] +//! \f[ = \frac {\frac{x_{2}-x_{1}}{4000}}{\frac {.01s*1 min}{60 sec}} \f] +//! \f[ = \frac {\frac {x_{2}-x_{1}}{4000}}{\frac {1}{6000} min} \f] +//! max \f$ x_{2}-x_{1} = 4000 \f$ counts, or 1 revolution in 10 ms +//! +//! If both sides of Equation 2 are divided by 6000 rpm, then: +//! \f[ 1 =\frac {\frac {x_{2}-x_{1}}{4000}rev.}{\frac {1}{6000}min*6000rpm}\f] +//! Because \f$ x_{2}-x_{1} \f$ must be \f$ <4000 (max) \f$ for +//! QPOSCNT increment, \f$ \frac {x_{2}-x_{1}}{4000} < 1 \f$ for CW rotation \n +//! And because \f$ x_{2}-x_{1} \f$ must be \f$ >-4000 \f$ for +//! QPOSCNT decrement, \f$ \frac {x_{2}-x_{1}}{4000}>-1 \f$ for CCW rotation +//! \f[ speed\_fr\ = \ +\frac {\frac {x_{2}-x_{1}}{4000}}{\frac{1}{6000} min * 6000rpm} = \ +\frac {x_{2}-x{1}}{4000}........3 \f] +//! +//! To convert speed_fr to RPM, multiply Equation 3 by 6000 rpm +//! \f[ SpeedRpm\_fr\ = 6000rpm * \frac {x_{2}-x_{1}}{4000}.........final \f]\n +//! +//! -# **min rpm ** = selected at 10 rpm based on CCPS prescaler options +//! available (128 is greatest) +//! -# **SpeedRpm_pr** +//! \f[ SpeedRpm\_pr\ = \frac {X}{t_2-t_1}.........4 \f] +//! where X = QCAPCTL [UPPS]/4000 rev. +//! (position relative to Index in 1 revolution) +//! +//! If \f$ \frac {max}{base}speed= 6000 rpm: 6000 = \ +\frac {\frac {32}{4000}}{\frac {t_2-t_1}{\frac {150MHz}{128}}} \f$ +//! where, +//! - 32 = QCAPCTL [UPPS] (Unit timeout - once every 32 edges) +//! - \f$ \frac {32}{4000} = \f$ position in 1 revolution +//! (position as a fraction of 1 revolution) +//! +//! - \f$ \frac {t_2-t_1}{\frac{150MHz}{128}}, t_2-t_1 =\f$ # of QCAPCLK cycles +//! - 1 QCAPCLK cycle = \f$ \frac {1}{\frac {150MHz}{128}} \f$ = QCPRDLAT +//! +//! So:\f[ 6000 rpm = \frac{32 \frac {150MHz}{128}* 60s/min}{4000(t_2-t_1)} \f] +//! \f[ t_2-t_1 = \ +\frac {32 \frac {150MHz}{128}*60 s/min}{4000*6000rpm}..........5 \f] +//! \f[ = 94 CAPCLK cycles = maximum (t2-t1) = SpeedScaler \f] +//! Divide both sides by \f$ t_2-t_1 \f$, and: \n +//! \f[ 1 = \frac {94}{t_2-t_1} = \ +\frac {\frac {32 \frac {150MHz}{128}*60 s/min}{4000*6000rpm}}{t_2-t_1} \f] +//! Because \f$ t_2-t_1 \f$ must be \f$ < 94 \f$ for QPOSCNT increment: +//! \f$ \frac {94}{t_2-t_1} < 1 \f$ for CW rotation \n +//! And because \f$ t_2-t_1 \f$ must be \f$ >-94 \f$ for QPOSCNT decrement: +//! \f$ \frac {94}{t_2-t_1}> -1 \f$ for CCW rotation +//! \f[ speed_pr = \frac {94}{t_2-t_1} \f] or \f[ \ +\frac {\frac {32 \frac {150MHz}{128}*60 s/min}{(4000*6000rpm)}}{t_2-t_1}........6\f] +//! +//! To convert speed_pr to RPM: \n +//! Multiply Equation 6 by 6000rpm: +//! \f[ SpeedRpm\_fr = 6000rpm * \ +\frac {\frac {32 \frac {150MHz}{128}*60 s/min}{(4000*6000rpm)}}{t_2-t_1} \f] +//! \f[ = \frac {32 \frac {150MHz}{128}*60 s/min}{4000*(t_2-t_1)} \f] +//! or \f[ \frac {\frac {32}{4000rev} * 60 s/min}{(t_2-t_1)(QCPRDLAT)}\ +............Final Equation \f] +//! +//! For 100 MHz Operation: +//! The same calculations as above are performed, but with 100 MHz +//! instead of 150MHz when calculating SpeedRpm_pr. \n +//! The value for freqScaler_pr becomes: +//! [32*(100MHz/128)*60s/min]/(4000*6000rpm) = 63 \n +//! More detailed calculation results can be found in the Example_freqcal.xls +//! spreadsheet included in the example folder. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "Example_posspeed.h" // Example specific Include file + +// +// POSSPEED_Init - +// +void +POSSPEED_Init(void) +{ + #if (CPU_FRQ_150MHZ) + EQep1Regs.QUPRD=1500000; // Unit Timer for 100Hz at 150 MHz SYSCLKOUT + #endif + #if (CPU_FRQ_100MHZ) + EQep1Regs.QUPRD=1000000; // Unit Timer for 100Hz at 100 MHz SYSCLKOUT + #endif + + EQep1Regs.QDECCTL.bit.QSRC=00; // QEP quadrature count mode + + EQep1Regs.QEPCTL.bit.FREE_SOFT=2; + + // + // PCRM=00 mode - QPOSCNT reset on index event + // + EQep1Regs.QEPCTL.bit.PCRM=00; + + EQep1Regs.QEPCTL.bit.UTE=1; // Unit Timeout Enable + EQep1Regs.QEPCTL.bit.QCLM=1; // Latch on unit time out + EQep1Regs.QPOSMAX=0xffffffff; + EQep1Regs.QEPCTL.bit.QPEN=1; // QEP enable + + EQep1Regs.QCAPCTL.bit.UPPS=5; // 1/32 for unit position + EQep1Regs.QCAPCTL.bit.CCPS=7; // 1/128 for CAP clock + EQep1Regs.QCAPCTL.bit.CEN=1; // QEP Capture Enable +} + +// +// POSSPEED_Calc - +// +void +POSSPEED_Calc(POSSPEED *p) +{ + long tmp; + unsigned int pos16bval,temp1; + _iq Tmp1,newp,oldp; + + // + // Position calculation - mechanical and electrical motor angle + // + + // + // Motor direction: 0=CCW/reverse, 1=CW/forward + // + p->DirectionQep = EQep1Regs.QEPSTS.bit.QDF; + + // + // capture position once per QA/QB period + // + pos16bval=(unsigned int)EQep1Regs.QPOSCNT; + + // + // raw theta = current pos. + ang. offset from QA + // + p->theta_raw = pos16bval+ p->cal_angle; + + // + // The following lines calculate p->theta_mech ~= + // QPOSCNT/mech_scaler [current cnt/(total cnt in 1 rev.)] + // where mech_scaler = 4000 cnts/revolution + // + tmp = (long)((long)p->theta_raw*(long)p->mech_scaler); // Q0*Q26 = Q26 + tmp &= 0x03FFF000; + p->theta_mech = (int)(tmp>>11); // Q26 -> Q15 + p->theta_mech &= 0x7FFF; + + // + // The following lines calculate p->elec_mech + // + p->theta_elec = p->pole_pairs*p->theta_mech; // Q0*Q15 = Q15 + p->theta_elec &= 0x7FFF; + + // + // Check an index occurrence + // + if (EQep1Regs.QFLG.bit.IEL == 1) + { + p->index_sync_flag = 0x00F0; + EQep1Regs.QCLR.bit.IEL=1; // Clear interrupt flag + } + + // + // High Speed Calculation using QEP Position counter + // Check unit Time out-event for speed calculation: + // Unit Timer is configured for 100Hz in INIT function + // + if(EQep1Regs.QFLG.bit.UTO==1) // If unit timeout (one 100Hz period) + { + // + // Differentiator + // The following lines calculate position = + // (x2-x1)/4000 (position in 1 revolution) + // + pos16bval=(unsigned int)EQep1Regs.QPOSLAT; // Latched POSCNT value + tmp = (long)((long)pos16bval*(long)p->mech_scaler); // Q0*Q26 = Q26 + tmp &= 0x03FFF000; + tmp = (int)(tmp>>11); // Q26 -> Q15 + tmp &= 0x7FFF; + newp=_IQ15toIQ(tmp); + oldp=p->oldpos; + + if (p->DirectionQep==0) // POSCNT is counting down + { + if (newp>oldp) + { + Tmp1 = - (_IQ(1) - newp + oldp); // x2-x1 should be negative + } + else + { + Tmp1 = newp -oldp; + } + } + else if (p->DirectionQep==1) // POSCNT is counting up + { + if (newp_IQ(1)) + { + p->Speed_fr = _IQ(1); + } + else if (Tmp1<_IQ(-1)) + { + p->Speed_fr = _IQ(-1); + } + else + { + p->Speed_fr = Tmp1; + } + + // + // Update the electrical angle + // + p->oldpos = newp; + + // + // Change motor speed from pu value to rpm value (Q15 -> Q0) + // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + // + p->SpeedRpm_fr = _IQmpy(p->BaseRpm,p->Speed_fr); + + EQep1Regs.QCLR.bit.UTO=1; // Clear interrupt flag + } + + // + // Low-speed computation using QEP capture counter + // + if(EQep1Regs.QEPSTS.bit.UPEVNT==1) // Unit position event + { + if(EQep1Regs.QEPSTS.bit.COEF==0) // No Capture overflow + { + temp1=(unsigned long)EQep1Regs.QCPRDLAT; // temp1 = t2-t1 + } + else // Capture overflow, saturate the result + { + temp1=0xFFFF; + } + + // + // p->Speed_pr = p->SpeedScaler/temp1 + // + p->Speed_pr = _IQdiv(p->SpeedScaler,temp1); + Tmp1=p->Speed_pr; + + if (Tmp1>_IQ(1)) + { + p->Speed_pr = _IQ(1); + } + else + { + p->Speed_pr = Tmp1; + } + + // + // Convert p->Speed_pr to RPM + // + if (p->DirectionQep==0) // Reverse direction = negative + { + // + // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + // + p->SpeedRpm_pr = -_IQmpy(p->BaseRpm,p->Speed_pr); + } + else // Forward direction = positive + { + // + // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q + // + p->SpeedRpm_pr = _IQmpy(p->BaseRpm,p->Speed_pr); + } + + EQep1Regs.QEPSTS.all=0x88; // Clear Unit position event flag + // Clear overflow error flag + } +} + +// +// End of File +// + diff --git a/f2833x/examples/eqep_pos_speed/Example_posspeed.h b/f2833x/examples/eqep_pos_speed/Example_posspeed.h new file mode 100644 index 0000000..5932742 --- /dev/null +++ b/f2833x/examples/eqep_pos_speed/Example_posspeed.h @@ -0,0 +1,141 @@ +//########################################################################### +// +// FILE: Example_posspeed.h +// +// TITLE: Pos/speed measurement using EQEP peripheral +// +// DESCRIPTION: Header file containing data type and object definitions and +// initializers. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __POSSPEED__ +#define __POSSPEED__ + +// +// Included Files +// +#include "IQmathLib.h" // Include header for IQmath library + +// +// Typedef for the structure of the POSSPEED Object +// +typedef struct +{ + int theta_elec; // Output: Motor Electrical angle (Q15) + int theta_mech; // Output: Motor Mechanical Angle (Q15) + int DirectionQep; // Output: Motor rotation direction (Q0) + int QEP_cnt_idx; // Variable: Encoder counter index (Q0) + int theta_raw; // Variable: Raw angle from Timer 2 (Q0) + + // + // Parameter: 0.9999/total count, total count = 4000 (Q26) + // + int mech_scaler; + + int pole_pairs; // Parameter: Number of pole pairs (Q0) + + // + // Parameter: Raw angular offset between encoder and phase a (Q0) + // + int cal_angle; + int index_sync_flag; // Output: Index sync status (Q0) + + // + // Parameter : Scaler converting 1/N cycles to a GLOBAL_Q speed (Q0) + // independently with global Q + // + Uint32 SpeedScaler; + _iq Speed_pr; // Output : speed in per-unit + + // + // Parameter : Scaler converting GLOBAL_Q speed to rpm (Q0) speed + // independently with global Q + // + Uint32 BaseRpm; + + // + // Output : speed in r.p.m. (Q0) - independently with global Q + // + int32 SpeedRpm_pr; + + _iq oldpos; // Input: Electrical angle (pu) + _iq Speed_fr; // Output : speed in per-unit + + // + // Output : Speed in rpm (Q0) - independently with global Q + // + int32 SpeedRpm_fr; + void (*init)(); // Pointer to the init function + void (*calc)(); // Pointer to the calc function +} POSSPEED; + +// +// Typedef for the POSSPEED_handle +// +typedef POSSPEED *POSSPEED_handle; + +// +// Defines for the default initializer for the POSSPEED Object. +// +#if (CPU_FRQ_150MHZ) + #define POSSPEED_DEFAULTS {0x0, 0x0,0x0,0x0,0x0,16776,2,0,0x0,\ + 94,0,6000,0,\ + 0,0,0,\ + (void (*)(long))POSSPEED_Init,\ + (void (*)(long))POSSPEED_Calc } +#endif +#if (CPU_FRQ_100MHZ) + #define POSSPEED_DEFAULTS {0x0, 0x0,0x0,0x0,0x0,16776,2,0,0x0,\ + 63,0,6000,0,\ + 0,0,0,\ + (void (*)(long))POSSPEED_Init,\ + (void (*)(long))POSSPEED_Calc } +#endif + +// +// Function Prototypes +// +void POSSPEED_Init(void); +void POSSPEED_Calc(POSSPEED_handle); + +#endif /* __POSSPEED__ */ + +// +// End of File +// + diff --git a/f2833x/examples/eqep_pos_speed/Example_posspeed.xls b/f2833x/examples/eqep_pos_speed/Example_posspeed.xls new file mode 100644 index 0000000..367b4e9 Binary files /dev/null and b/f2833x/examples/eqep_pos_speed/Example_posspeed.xls differ diff --git a/f2833x/examples/external_interrupt/.ccsproject b/f2833x/examples/external_interrupt/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/external_interrupt/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/external_interrupt/.cproject b/f2833x/examples/external_interrupt/.cproject new file mode 100644 index 0000000..157118c --- /dev/null +++ b/f2833x/examples/external_interrupt/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/external_interrupt/.project b/f2833x/examples/external_interrupt/.project new file mode 100644 index 0000000..dde091a --- /dev/null +++ b/f2833x/examples/external_interrupt/.project @@ -0,0 +1,93 @@ + + + Example_2833xExternalInterrupt + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/external_interrupt/Example_2833xExternalInterrupt.c b/f2833x/examples/external_interrupt/Example_2833xExternalInterrupt.c new file mode 100644 index 0000000..bb35f05 --- /dev/null +++ b/f2833x/examples/external_interrupt/Example_2833xExternalInterrupt.c @@ -0,0 +1,325 @@ +//########################################################################### +// +// FILE: Example_2833xExternalInterrupt.c +// +// TITLE: External Interrupt Example +// +//! \addtogroup f2833x_example_list +//!

External Interrupt (external_interrupt)

+//! +//! This program sets up GPIO0 as XINT1 and GPIO1 as XINT2. Two other +//! GPIO signals are used to trigger the interrupt (GPIO30 triggers +//! XINT1 and GPIO31 triggers XINT2). XINT1 input is synched to SYSCLKOUT +//! XINT2 has a long qualification - 6 samples at 510*SYSCLKOUT each. +//! GPIO34 will go high outside of the interrupts and low within the +//! interrupts. This signal can be monitored on a scope. +//! Each interrupt is fired in sequence - XINT1 first and then XINT2. +//! +//! Monitor GPIO34 with an oscilloscope. GPIO34 will be high outside of +//! the ISRs and low within each ISR. +//! +//! \b External \b Connections \n +//! - Connect GPIO30 to GPIO0. GPIO0 is assigned to XINT1 +//! - Connect GPIO31 to GPIO1. GPIO1 is assigned to XINT2 +//! +//! \b Watch \b Variables \n +//! - Xint1Count - XINT1 interrupt count +//! - Xint2Count - XINT2 interrupt count +//! - LoopCount - Idle loop count +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +__interrupt void xint1_isr(void); +__interrupt void xint2_isr(void); + +// +// Globals +// +volatile Uint32 Xint1Count; +volatile Uint32 Xint2Count; +Uint32 LoopCount; + +// +// Defines +// +#define DELAY 35.700L + +// +// Main +// +void main(void) +{ + Uint32 TempX1Count; + Uint32 TempX2Count; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT1 = &xint1_isr; + PieVectTable.XINT2 = &xint2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code, enable interrupts + // + + // + // Clear the counters + // + Xint1Count = 0; // Count Xint1 interrupts + Xint2Count = 0; // Count XINT2 interrupts + LoopCount = 0; // Count times through idle loop + + // + // Enable Xint1 and XINT2 in the PIE: Group 1 interrupt 4 & 5 + // Enable int1 which is connected to WAKEINT: + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // Enable PIE Group 1 INT4 + PieCtrlRegs.PIEIER1.bit.INTx5 = 1; // Enable PIE Group 1 INT5 + IER |= M_INT1; // Enable CPU int1 + EINT; // Enable Global Interrupts + + // + // GPIO30 & GPIO31 are outputs, start GPIO30 high and GPIO31 low + // + EALLOW; + GpioDataRegs.GPASET.bit.GPIO30 = 1; // Load the output latch + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO30 = 1; // output + + GpioDataRegs.GPACLEAR.bit.GPIO31 = 1; // Load the output latch + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO31 = 1; // output + EDIS; + + // + // GPIO0 and GPIO1 are inputs + // + EALLOW; + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO0 = 0; // input + GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 0; // Xint1 Synch to SYSCLKOUT only + + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; // GPIO + GpioCtrlRegs.GPADIR.bit.GPIO1 = 0; // input + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 2; // XINT2 Qual using 6 samples + + // + // Each sampling window is 510*SYSCLKOUT + // + GpioCtrlRegs.GPACTRL.bit.QUALPRD0 = 0xFF; + EDIS; + + // + // GPIO0 is XINT1, GPIO1 is XINT2 + // + EALLOW; + GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 0; // Xint1 is GPIO0 + GpioIntRegs.GPIOXINT2SEL.bit.GPIOSEL = 1; // XINT2 is GPIO1 + EDIS; + + // + // Configure XINT1 + // + XIntruptRegs.XINT1CR.bit.POLARITY = 0; // Falling edge interrupt + XIntruptRegs.XINT2CR.bit.POLARITY = 1; // Rising edge interrupt + + // + // Enable XINT1 and XINT2 + // + XIntruptRegs.XINT1CR.bit.ENABLE = 1; // Enable Xint1 + XIntruptRegs.XINT2CR.bit.ENABLE = 1; // Enable XINT2 + + // + // GPIO34 will go low inside each interrupt. Monitor this on a scope + // + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // output + EDIS; + + // + // Step 6. IDLE loop + // + for(;;) + { + TempX1Count = Xint1Count; + TempX2Count = Xint2Count; + + // + // Trigger both XINT1 + // + GpioDataRegs.GPBSET.bit.GPIO34 = 1; // GPIO34 is high + GpioDataRegs.GPACLEAR.bit.GPIO30 = 1; // Lower GPIO30, trigger Xint1 + while(Xint1Count == TempX1Count) + { + + } + + // + // Trigger both XINT2 + // + GpioDataRegs.GPBSET.bit.GPIO34 = 1; // GPIO34 is high + DELAY_US(DELAY); // Wait for Qual period + GpioDataRegs.GPASET.bit.GPIO31 = 1; // Raise GPIO31, trigger XINT2 + while(Xint2Count == TempX2Count) + { + + } + + // + // Check that the counts were incremented properly and get ready + // to start over. + // + if(Xint1Count == TempX1Count+1 && Xint2Count == TempX2Count+1) + { + LoopCount++; + GpioDataRegs.GPASET.bit.GPIO30 = 1; // raise GPIO30 + GpioDataRegs.GPACLEAR.bit.GPIO31 = 1; // lower GPIO31 + } + else + { + __asm(" ESTOP0"); // stop here + } + } +} + +// +// Step 7. Insert all local Interrupt Service Routines (ISRs) and +// functions here +// + +// +// Note: If local ISRs are used, reassign vector addresses in vector table as +// shown in Step 5 +// + +// +// xint1_isr - +// +__interrupt void +xint1_isr(void) +{ + GpioDataRegs.GPBCLEAR.all = 0x4; // GPIO34 is low + Xint1Count++; + + // + // Acknowledge this interrupt to get more from group 1 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +// +// xint2_isr - +// +__interrupt void +xint2_isr(void) +{ + GpioDataRegs.GPBCLEAR.all = 0x4; // GPIO34 is low + Xint2Count++; + + // + // Acknowledge this interrupt to get more from group 1 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +// +// End of File +// + diff --git a/f2833x/examples/f28335_can_flash_kernel/.ccsproject b/f2833x/examples/f28335_can_flash_kernel/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/f28335_can_flash_kernel/.cproject b/f2833x/examples/f28335_can_flash_kernel/.cproject new file mode 100644 index 0000000..7596845 --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/.cproject @@ -0,0 +1,129 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/f28335_can_flash_kernel/.project b/f2833x/examples/f28335_can_flash_kernel/.project new file mode 100644 index 0000000..a3b488f --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/.project @@ -0,0 +1,78 @@ + + + f28335_can_flash_kernel + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + INSTALLROOT_2833X_TO_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS + + + INSTALLROOT_2833X_TO_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath + + + diff --git a/f2833x/examples/f28335_can_flash_kernel/Boot.h b/f2833x/examples/f28335_can_flash_kernel/Boot.h new file mode 100644 index 0000000..635fb24 --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/Boot.h @@ -0,0 +1,124 @@ +//########################################################################### +// +// FILE: Boot.h +// +// TITLE: Boot ROM Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $s +//########################################################################### + +#ifndef F2833x_BOOT_H +#define F2833X_BOOT_H + +// +// Included Files +// +#include "DSP2833x_Device.h" // F2833x Headerfile Include File + +// +// Define for the length of the programming buffer +// +#define PROG_BUFFER_LENGTH 0x400 + +// +// Boot Modes Defines +// +// GPIO37 GPIO34 TRSTn +// TDO CMP2OUT +// Mode EMU x x 1 Emulator connected +// Mode 0 0 0 0 Parallel I/O +// Mode 1 0 1 0 SCI +// Mode 2 1 0 0 wait +// Mode 3 1 1 0 "Get Mode" +// +#define OTP_KEY 0x3D7BFE +#define OTP_BMODE 0x3D7BFF +#define KEY_VAL 0x55AA + +#define PARALLEL_BOOT 0x0000 +#define SCI_BOOT 0x0001 +#define WAIT_BOOT 0x0002 +#define GET_BOOT 0x0003 + +#define SPI_BOOT 0x0004 +#define I2C_BOOT 0x0005 +#define OTP_BOOT 0x0006 +#define RAM_BOOT 0x000A +#define FLASH_BOOT 0x000B + +// +// Defines for the fixed boot entry points +// +#define FLASH_ENTRY_POINT 0x3F7FF6 +#define OTP_ENTRY_POINT 0x3D7800 +#define RAM_ENTRY_POINT 0x000000 + +#define DIVSEL_BY_4 0 +#define DIVSEL_BY_2 2 +#define DIVSEL_BY_1 3 + +#define ERROR 1 +#define NO_ERROR 0 +#define EIGHT_BIT 8 +#define SIXTEEN_BIT 16 +#define EIGHT_BIT_HEADER 0x08AA +#define SIXTEEN_BIT_HEADER 0x10AA + +// +// Typedef +// +typedef Uint16 (* uint16fptr)(); + +extern uint16fptr GetWordData,GetOnlyWordData; +extern void (*Flash_CallbackPtr) (void); +extern Uint32 Flash_CPUScaleFactor; +extern Uint16 EmuKey; +extern Uint16 EmuBMode; +extern Uint16 CsmUnlock(); +#define Device_cal (void (*)(void))0x3D7C80 +#define Get_mode (Uint16 (*)(void))0x3D7CC0 + +// +// Defines configured by the boot ROM +// +#define BORTRIM (Uint16 *)0x0986 + +#endif // end of F2833X_BOOT_H definition + +// +// End of File +// + diff --git a/f2833x/examples/f28335_can_flash_kernel/CAN_Boot.c b/f2833x/examples/f28335_can_flash_kernel/CAN_Boot.c new file mode 100644 index 0000000..524744e --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/CAN_Boot.c @@ -0,0 +1,323 @@ +//########################################################################### +// +// FILE: CAN_Boot.c +// +// TITLE: CAN Boot mode routines +// +// Functions: +// +// Uint32 CAN_Boot(void) +// inline void CAN_Init(void) +// Uint32 CAN_GetWordData(void) +// +// Notes: +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "Boot.h" + +// +// Private functions +// +inline void CAN_Init(void); +Uint16 CAN_GetWordData(void); + +// +// External functions +// +extern void CopyData(void); +extern Uint32 GetLongData(void); +extern void ReadReservedFn(void); + +volatile struct ECAN_REGS ECanaShadow; +// +// CAN_Boot - This module is the main CAN boot routine. +// It will load code via the CAN-A port. It will return a entry point address +// back to the InitBoot routine which in turn calls the ExitBoot routine. +// +Uint32 +CAN_Boot() +{ + Uint32 EntryAddr; + + // + // If the missing clock detect bit is set, just + // loop here. + // + if(SysCtrlRegs.PLLSTS.bit.MCLKSTS == 1) + { + for(;;); + } + + CAN_Init(); + // + // Assign GetOnlyWordData to the CAN-A version of the + // function. GetWordData is a pointer to a function. + // + GetOnlyWordData = CAN_GetWordData; + + + // + // If the KeyValue was invalid, abort the load + // and return the flash entry point. + // + if (CAN_GetWordData() != 0x08AA) return FLASH_ENTRY_POINT; + + ReadReservedFn(); + + EntryAddr = GetLongData(); + + CopyData(); + + return EntryAddr; +} + +// +// CAN_Init - Initialize the CAN-A port for communications with the host. +// +inline void +CAN_Init() +{ + + struct ECAN_REGS ECanaShadow; + + EALLOW; + + // + // Enable CAN clock + // + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; + + // + // Configure eCAN-A pins using GPIO regs + // + + // GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GPIO30 is CANRXA + // GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GPIO31 is CANTXA + GpioCtrlRegs.GPAMUX2.all |= 0x50000000; + + // + //Enable internal pullups for the CAN pins + // + + // GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; + // GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; + GpioCtrlRegs.GPAPUD.all &= 0x3FFFFFFF; + + // + // Asynch Qual + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; + + // + // Configure eCAN RX and TX pins for CAN operation using eCAN regs + // + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + // Initialize all bits of 'Message Control Register' to zero + // Some bits of MSGCTRL register come up in an unknown state. For proper operation, + // all bits (including reserved bits) of MSGCTRL must be initialized to zero + // + ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000; + + // + // Clear all RMPn, GIFn bits + // RMPn, GIFn bits are zero upon reset and are cleared again as a precaution. + // + ECanaRegs.CANRMP.all = 0xFFFFFFFF; + + // + // Clear all interrupt flag bits + // + ECanaRegs.CANGIF0.all = 0xFFFFFFFF; + ECanaRegs.CANGIF1.all = 0xFFFFFFFF; + + // + // Configure bit timing parameters for eCANA + // + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1 ; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + // + // Wait for CCE bit to be set.. + // + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1 ); + + ECanaShadow.CANBTC.all = 0; + + // + // Note: These values are modified from the original boot rom CAN_Init() function + // BRP = 10, TSEG2REG = 3, TSEG1REG = 4 + // Values chosen for: SYSCLKOUT = 150 MHz CAN module clock = 75 MHz Bit rate = 100kbps + // + ECanaShadow.CANBTC.bit.BRPREG = 10; + ECanaShadow.CANBTC.bit.TSEG2REG = 3; + ECanaShadow.CANBTC.bit.TSEG1REG = 4; + + ECanaShadow.CANBTC.bit.SAM = 1; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0 ; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + // + // Wait for CCE bit to be cleared.. + // + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 0 ); + + // + // Disable all Mailboxes + // Required before writing the MSGIDs + // + ECanaRegs.CANME.all = 0; + + // + // Assign MSGID to MBOX1 + // Standard ID of 1, Acceptance mask disabled + // + ECanaMboxes.MBOX1.MSGID.all = 0x00040000; + + // + // Configure MBOX1 to be a receive MBOX + // + ECanaRegs.CANMD.all = 0x0002; + + // + // Enable MBOX1 + // + ECanaRegs.CANME.all = 0x0002; + + EDIS; + return; +} + +// +// CAN_GetWordData - This routine fetches two bytes from the CAN-A +// port and puts them together to form a single 16-bit value. +// It is assumed that the host is sending the data in the order LSB followed by +// MSB. +// +Uint16 +CAN_GetWordData() +{ + Uint16 wordData; + Uint16 byteData; + + wordData = 0x0000; + byteData = 0x0000; + + // Fetch the LSB + while(ECanaRegs.CANRMP.all == 0) { } + wordData = (Uint16) ECanaMboxes.MBOX1.MDL.byte.BYTE0; // LS byte + + // Fetch the MSB + byteData = (Uint16)ECanaMboxes.MBOX1.MDL.byte.BYTE1; // MS byte + + // form the wordData from the MSB:LSB + wordData |= (byteData << 8); + + /* Clear all RMPn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFF; + + return wordData; + } + +/* +Data frames with a Standard MSGID of 0x1 should be transmitted to the ECAN-A bootloader. +This data will be received in Mailbox1, whose MSGID is 0x1. No message filtering is employed. + +Transmit only 2 bytes at a time, LSB first and MSB next. For example, to transmit +the word 0x08AA to the 28x device, transmit AA first, followed by 08. Following is the +order in which data should be transmitted: +AA 08 - Keyvalue +00 00 - Part of 8 reserved words stream +00 00 - Part of 8 reserved words stream +00 00 - Part of 8 reserved words stream +00 00 - Part of 8 reserved words stream +00 00 - Part of 8 reserved words stream +00 00 - Part of 8 reserved words stream +00 00 - Part of 8 reserved words stream +00 00 - Part of 8 reserved words stream +bb aa - MS part of 32-bit address (aabb) +dd cc - LS part of 32-bit address (ccdd) - Final Entry-point address = 0xaabbccdd +nn mm - Length of first section (mm nn) +ff ee - MS part of 32-bit address (eeff) +hh gg - LS part of 32-bit address (gghh) - Entry-point address of first section = 0xeeffgghh +xx xx - First word of first section +xx xx - Second word...... +... +... +... +xxx - Last word of first section +nn mm - Length of second section (mm nn) +ff ee - MS part of 32-bit address (eeff) +hh gg - LS part of 32-bit address (gghh) - Entry-point address of second section = 0xeeffgghh +xx xx - First word of second section +xx xx - Second word...... +... +... +... +xxx - Last word of second section +(more sections, if need be) +00 00 - Section length of zero for next section indicates end of data. +*/ + +// +// End of File +// + diff --git a/f2833x/examples/f28335_can_flash_kernel/DSP2833x_SysCtrl.c b/f2833x/examples/f28335_can_flash_kernel/DSP2833x_SysCtrl.c new file mode 100644 index 0000000..29e949b --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/DSP2833x_SysCtrl.c @@ -0,0 +1,453 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 15, 2009 09:54:05 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.c +// +// TITLE: DSP2833x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: Example initialization of system resources. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped to a load and +// run address using the linker cmd file. +// +#pragma CODE_SECTION(InitFlash, "ramfuncs"); + +// +// InitSysCtrl - This function initializes the System Control registers to a +// known state. +// - Disables the watchdog +// - Set the PLLCR for proper SYSCLKOUT frequency +// - Set the pre-scaler for the high and low frequency peripheral clocks +// - Enable the clocks to the peripherals +// +void +InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + + // + // Initialize the PLL control: PLLCR and DIVSEL + // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h + // + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + // + // Initialize the peripheral clocks + // + InitPeripheralClocks(); +} + +// +// InitFlash - This function initializes the Flash Control registers +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +void +InitFlash(void) +{ + EALLOW; + + // + // Enable Flash Pipeline mode to improve performance + // of code executed from Flash. + // + FlashRegs.FOPT.bit.ENPIPE = 1; + + // + // CAUTION + // Minimum waitstates required for the flash operating + // at a given CPU rate must be characterized by TI. + // Refer to the datasheet for the latest information. + // +#if CPU_FRQ_150MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; +#endif + +#if CPU_FRQ_100MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; +#endif + // + // CAUTION + // ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED + // + FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; + FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; + EDIS; + + // + // Force a pipeline flush to ensure that the write to + // the last register configured occurs before returning. + // + asm(" RPT #7 || NOP"); +} + +// +// ServiceDog - This function resets the watchdog timer. +// Enable this function for using ServiceDog in the application +// +void +ServiceDog(void) +{ + EALLOW; + SysCtrlRegs.WDKEY = 0x0055; + SysCtrlRegs.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void +DisableDog(void) +{ + EALLOW; + SysCtrlRegs.WDCR= 0x0068; + EDIS; +} + +// +// InitPll - This function initializes the PLLCR register. +// +void +InitPll(Uint16 val, Uint16 divsel) +{ + // + // Make sure the PLL is not running in limp mode + // + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0) + { + // + // Missing external clock has been detected + // Replace this line with a call to an appropriate + // SystemShutdown(); function. + // + asm(" ESTOP0"); + } + + // + // DIVSEL MUST be 0 before PLLCR can be changed from + // 0x0000. It is set to 0 by an external reset XRSn + // This puts us in 1/4 + // + if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; + EDIS; + } + + // + // Change the PLLCR + // + if (SysCtrlRegs.PLLCR.bit.DIV != val) + { + EALLOW; + + // + // Before setting PLLCR turn off missing clock detect logic + // + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; + SysCtrlRegs.PLLCR.bit.DIV = val; + EDIS; + + // + // Optional: Wait for PLL to lock. + // During this time the CPU will switch to OSCCLK/2 until + // the PLL is stable. Once the PLL is stable the CPU will + // switch to the new PLL value. + // + // This time-to-lock is monitored by a PLL lock counter. + // + // Code is not required to sit and wait for the PLL to lock. + // However, if the code does anything that is timing critical, + // and requires the correct clock be locked, then it is best to + // wait until this switching has completed. + // + + // + // Wait for the PLL lock bit to be set. + // + + // + // The watchdog should be disabled before this loop, or fed within + // the loop via ServiceDog(). + // + + // + // Uncomment to disable the watchdog + // + DisableDog(); + + while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) + { + // + // Uncomment to service the watchdog + // + //ServiceDog(); + } + + EALLOW; + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; + EDIS; + } + + // + // If switching to 1/2 + // + if((divsel == 1)||(divsel == 2)) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel; + EDIS; + } + + // + // NOTE: ONLY USE THIS SETTING IF PLL IS BYPASSED (I.E. PLLCR = 0) OR OFF + // If switching to 1/1 + // * First go to 1/2 and let the power settle + // The time required will depend on the system, this is only an example + // * Then switch to 1/1 + // + if(divsel == 3) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 2; + DELAY_US(50L); + SysCtrlRegs.PLLSTS.bit.DIVSEL = 3; + EDIS; + } +} + +// +// InitPeripheralClocks - This function initializes the clocks to the +// peripheral modules. First the high and low clock prescalers are set +// Second the clocks are enabled to each peripheral. To reduce power, leave +// clocks to unused peripherals disabled +// +// Note: If a peripherals clock is not enabled then you cannot +// read or write to the registers for that peripheral +// +void +InitPeripheralClocks(void) +{ + EALLOW; + + // + // HISPCP/LOSPCP prescale register settings, normally it will be set to + // default values + // + SysCtrlRegs.HISPCP.all = 0x0001; + SysCtrlRegs.LOSPCP.all = 0x0002; + + // + // XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT + // XTIMCLK = SYSCLKOUT/2 + // + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + + // + // XCLKOUT = XTIMCLK/2 + // + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + // + // Enable XCLKOUT + // + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + + // + // Peripheral clock enables set for the selected peripherals. + // If you are not using a peripheral leave the clock off + // to save on power. + // + // Note: not all peripherals are available on all 2833x derivates. + // Refer to the datasheet for your particular device. + // + // This function is not written to be an example of efficient code. + // + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC + + // + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI + // reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC to + // function according to specification. The clocks to the ADC MUST be + // enabled before calling this function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + // + ADC_cal(); + + SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C + SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A + SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B + SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C + SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A + SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A + SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A + SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B + + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM + SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 + SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2 + SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3 + SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4 + SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5 + SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6 + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM + + SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3 + SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4 + SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5 + SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6 + SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1 + SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2 + SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1 + SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2 + + SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2 + + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK + SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock + + EDIS; +} + +// +// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with +// current password for the DSP. Returns 1 if unlock is successful. +// +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 +Uint16 +CsmUnlock() +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the + // DSP. + // + EALLOW; + CsmRegs.KEY0 = 0xFFFF; + CsmRegs.KEY1 = 0xFFFF; + CsmRegs.KEY2 = 0xFFFF; + CsmRegs.KEY3 = 0xFFFF; + CsmRegs.KEY4 = 0xFFFF; + CsmRegs.KEY5 = 0xFFFF; + CsmRegs.KEY6 = 0xFFFF; + CsmRegs.KEY7 = 0xFFFF; + EDIS; + + // + // Perform a dummy read of the password locations if they match the key + // values, the CSM will unlock + // + temp = CsmPwl.PSWD0; + temp = CsmPwl.PSWD1; + temp = CsmPwl.PSWD2; + temp = CsmPwl.PSWD3; + temp = CsmPwl.PSWD4; + temp = CsmPwl.PSWD5; + temp = CsmPwl.PSWD6; + temp = CsmPwl.PSWD7; + + // + // If the CSM unlocked, return succes, otherwise return failure. + // + if (CsmRegs.CSMSCR.bit.SECURE == 0) + { + return STATUS_SUCCESS; + } + else + { + return STATUS_FAIL; + } +} + +// +// End of file +// + diff --git a/f2833x/examples/f28335_can_flash_kernel/Exit_Boot.asm b/f2833x/examples/f28335_can_flash_kernel/Exit_Boot.asm new file mode 100644 index 0000000..53df68c --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/Exit_Boot.asm @@ -0,0 +1,205 @@ +;; TI File $Revision: /main/1 $ +;; Checkin $Date: August 13, 2012 15:28:34 $ +;;########################################################################### +;; +;; FILE: Init_Boot.asm +;; +;; TITLE: Boot Rom Initialization and Exit routines. +;; +;; Functions: +;; +;; _InitBoot +;; _ExitBoot +;; +;; Notes: +;; +;;########################################################################### +;; $TI Release: $ +;; $Release Date: $ +;; $Copyright: +;// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;;########################################################################### + + .global _ExitBoot + .global _InitBoot + .ref _main + + + + .sect ".InitBoot" + +;----------------------------------------------- +; _InitBoot +;----------------------------------------------- +;----------------------------------------------- +; This function performs the initial boot routine +; for the boot ROM. +; +; This module performs the following actions: +; +; 1) Initalizes the stack pointer +; 2) Sets the device for C28x operating mode +; 3) Calls the main boot functions +; 4) Calls an exit routine +;----------------------------------------------- + + +_InitBoot: + +; Initalize the stack pointer. + +__stack: .usect ".stack",0 + MOV SP, #__stack ; Initalize the stack pointer + +; Initalize the device for running in C28x mode. + + C28OBJ ; Select C28x object mode + C28ADDR ; Select C27x/C28x addressing + C28MAP ; Set blocks M0/M1 for C28x mode + CLRC PAGE0 ; Always use stack addressing mode + MOVW DP,#0 ; Initialize DP to point to the low 64 K + CLRC OVM + +; Set PM shift of 0 + + SPM 0 + +; Decide which boot mode to use + LCR _main + +; Cleanup and exit. At this point the EntryAddr +; is located in the ACC register + BF _ExitBoot,UNC + + + +;----------------------------------------------- +; _ExitBoot +;----------------------------------------------- +;----------------------------------------------- +;This module cleans up after the boot loader +; +; 1) Make sure the stack is deallocated. +; SP = 0x400 after exiting the boot +; loader +; 2) Push 0 onto the stack so RPC will be +; 0 after using LRETR to jump to the +; entry point +; 2) Load RPC with the entry point +; 3) Clear all XARn registers +; 4) Clear ACC, P and XT registers +; 5) LRETR - this will also clear the RPC +; register since 0 was on the stack +;----------------------------------------------- + +_ExitBoot: + +;----------------------------------------------- +; Insure that the stack is deallocated +;----------------------------------------------- + + MOV SP,#__stack + +;----------------------------------------------- +; Clear the bottom of the stack. This will endup +; in RPC when we are finished +;----------------------------------------------- + + MOV *SP++,#0 + MOV *SP++,#0 + +;----------------------------------------------- +; Load RPC with the entry point as determined +; by the boot mode. This address will be returned +; in the ACC register. +;----------------------------------------------- + + PUSH ACC + POP RPC + +;----------------------------------------------- +; Put registers back in their reset state. +; +; Clear all the XARn, ACC, XT, and P and DP +; registers +; +; NOTE: Leave the device in C28x operating mode +; (OBJMODE = 1, AMODE = 0) +;----------------------------------------------- + ZAPA + MOVL XT,ACC + MOVZ AR0,AL + MOVZ AR1,AL + MOVZ AR2,AL + MOVZ AR3,AL + MOVZ AR4,AL + MOVZ AR5,AL + MOVZ AR6,AL + MOVZ AR7,AL + MOVW DP, #0 + +;------------------------------------------------ +; Restore ST0 and ST1. Note OBJMODE is +; the only bit not restored to its reset state. +; OBJMODE is left set for C28x object operating +; mode. +; +; ST0 = 0x0000 ST1 = 0x0A0B +; 15:10 OVC = 0 15:13 ARP = 0 +; 9: 7 PM = 0 12 XF = 0 +; 6 V = 0 11 M0M1MAP = 1 +; 5 N = 0 10 reserved +; 4 Z = 0 9 OBJMODE = 1 +; 3 C = 0 8 AMODE = 0 +; 2 TC = 0 7 IDLESTAT = 0 +; 1 OVM = 0 6 EALLOW = 0 +; 0 SXM = 0 5 LOOP = 0 +; 4 SPA = 0 +; 3 VMAP = 1 +; 2 PAGE0 = 0 +; 1 DBGM = 1 +; 0 INTM = 1 +;----------------------------------------------- + + MOV *SP++,#0 + MOV *SP++,#0x0A0B + POP ST1 + POP ST0 + +;------------------------------------------------ +; Jump to the EntryAddr as defined by the +; boot mode selected and continue execution +;----------------------------------------------- + + LRETR + +;eof ---------- diff --git a/f2833x/examples/f28335_can_flash_kernel/Flash28335_API_V210.lib b/f2833x/examples/f28335_can_flash_kernel/Flash28335_API_V210.lib new file mode 100644 index 0000000..9355d03 Binary files /dev/null and b/f2833x/examples/f28335_can_flash_kernel/Flash28335_API_V210.lib differ diff --git a/f2833x/examples/f28335_can_flash_kernel/Flash2833x_API_Config.h b/f2833x/examples/f28335_can_flash_kernel/Flash2833x_API_Config.h new file mode 100644 index 0000000..fa01194 --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/Flash2833x_API_Config.h @@ -0,0 +1,110 @@ +//########################################################################### +// +// FILE: Flash2833x_API_Config.h +// +// TITLE: F2833x Flash Algo's - User Settings +// +// NOTE: This file contains user defined settings that +// are used by the F2833x Flash APIs. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef FLASH2833X_API_CONFIG_H +#define FLASH2833X_API_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Variables that can be configured by the user +// + +// +// 1. Specify the device. +// Define the device to be programmed as "1" (no quotes). +// Define all other devices as "0" (no quotes). +// +#define FLASH_F28335 1 +#define FLASH_F28334 0 +#define FLASH_F28332 0 + +// +// 2. Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// that your application will use. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example: CLKIN is a 30MHz crystal. +// +// If the application will set PLLCR = 0xA then the CPU clock +// will be 150Mhz (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// DO NOT modify the code below this line +// +#define SCALE_FACTOR 1048576.0L*( (200L/CPU_RATE) ) // IQ20 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // -- end FLASH2833X_API_CONFIG_H + +// +// End of File +// + diff --git a/f2833x/examples/f28335_can_flash_kernel/Flash2833x_API_Library.h b/f2833x/examples/f28335_can_flash_kernel/Flash2833x_API_Library.h new file mode 100644 index 0000000..1a531f4 --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/Flash2833x_API_Library.h @@ -0,0 +1,318 @@ +//########################################################################### +// +// FILE: Flash2833x_API_Library.h +// +// TITLE: F2833x Flash Algo's main include file +// +// DESCRIPTION: This file should be included in any project that uses any of +// the F2833x flash APIs. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef FLASH2833X_API_LIBRARY_H +#define FLASH2833X_API_LIBRARY_H + +#include "Flash2833x_API_Config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// +// 28x Datatypes +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16/32/64-Bit Signed/Unsigned Integers and floating point +// variables: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// API Status Messages +// +// The following status values are returned from the API to the calling +// program. These can be used to determine if the API function passed +// or failed. +// + +// +// Defines +// + +// +// Operation passed, no errors were flagged +// +#define STATUS_SUCCESS 0 + +// +// The CSM is preventing the function from performing its operation +// +#define STATUS_FAIL_CSM_LOCKED 10 + +// +// Device REVID does not match that required by the API +// +#define STATUS_FAIL_REVID_INVALID 11 + +// +// Invalid address passed to the API +// +#define STATUS_FAIL_ADDR_INVALID 12 + +// +// Incorrect PARTID +// For example the F2806 API was used on a F2808 device. +// +#define STATUS_FAIL_INCORRECT_PARTID 13 + +// +// API/Silicon missmatch. An old version of the API is being used on silicon +// it is not valid for. Please update to the latest API. +// +#define STATUS_FAIL_API_SILICON_MISMATCH 14 + +// +// Erase Specific errors +// +#define STATUS_FAIL_NO_SECTOR_SPECIFIED 20 +#define STATUS_FAIL_PRECONDITION 21 +#define STATUS_FAIL_ERASE 22 +#define STATUS_FAIL_COMPACT 23 +#define STATUS_FAIL_PRECOMPACT 24 + +// +// Program Specific errors +// +#define STATUS_FAIL_PROGRAM 30 +#define STATUS_FAIL_ZERO_BIT_ERROR 31 + +// +// Verify Specific errors +// +#define STATUS_FAIL_VERIFY 40 + +// +// Busy is set by each API function before it determines a pass or fail +// condition for that operation. The calling function will will not receive +// this status condition back from the API +// +#define STATUS_BUSY 999 + +// +// Flash sector mask definitions +// +// The following macros can be used to form a mask specifying which sectors +// will be erased by the erase API function. +// +// Bit0 = Sector A +// Bit1 = Sector B +// Bit2 = Sector C +// Bit3 = Sector D +// Bit4 = Sector E +// Bit5 = Sector F +// Bit6 = Sector G +// Bit7 = Sector H +// +#define SECTORA (Uint16)0x0001 +#define SECTORB (Uint16)0x0002 +#define SECTORC (Uint16)0x0004 +#define SECTORD (Uint16)0x0008 +#define SECTORE (Uint16)0x0010 +#define SECTORF (Uint16)0x0020 +#define SECTORG (Uint16)0x0040 +#define SECTORH (Uint16)0x0080 + +#if FLASH_F28335 + // + // All sectors on an F28335 - Sectors A - H + // + #define SECTOR_F28335 (SECTORA|SECTORB|SECTORC|SECTORD|SECTORE|SECTORF|\ + SECTORG|SECTORH) +#endif // -- end FLASH_F28335 + +#if FLASH_F28334 + // + // All sectors on an F28334 - Sectors A - H + // + #define SECTOR_F28334 (SECTORA|SECTORB|SECTORC|SECTORD|SECTORE|SECTORF|\ + SECTORG|SECTORH) +#endif // -- end FLASH_F28334 + +#if FLASH_F28332 + // + // All sectors on an F28332 - Sectors A - D + // + #define SECTOR_F28332 (SECTORA|SECTORB|SECTORC|SECTORD) +#endif // -- end FLASH_F28332 + +// +// API Status Structure +// +// This structure is used to pass debug data back to the calling routine. +// Note that the Erase API function has 3 parts: precondition, erase and +// and compaction. Erase and compaction failures will not populate +// the expected and actual data fields. +// +typedef struct +{ + Uint32 FirstFailAddr; + Uint16 ExpectedData; + Uint16 ActualData; +} FLASH_ST; + +// +// Interface Function prototypes +// +// For each 28x Flash API library, the function names are of the form: +// Flash_() +// +// Where is the device: ie 2808, 2806, 2801 +// is the operation such as Erase, Program... +// +// For portability for users who may move between the F2808, F2806 and +// F2801, the following macro definitions are supplied. +// +// Using these macro definitions, the user can use instead make a generic +// call: Flash_ and the macro will map the call to the proper +// device function +// +// Note except for the toggle test function, all of the function prototypes +// are compatible with F281x devices as well. +// +#if FLASH_F28335 +#define Flash_Erase(a,b) Flash28335_Erase(a,b) +#define Flash_Program(a,b,c,d) Flash28335_Program(a,b,c,d) +#define Flash_Verify(a,b,c,d) Flash28335_Verify(a,b,c,d) +#define Flash_ToggleTest(a,b) Flash28335_ToggleTest(a,b) +#define Flash_DepRecover() Flash28335_DepRecover() +#define Flash_APIVersionHex() Flash28335_APIVersionHex() +#define Flash_APIVersion() Flash28335_APIVersion() +#endif + +#if FLASH_F28334 +#define Flash_Erase(a,b) Flash28334_Erase(a,b) +#define Flash_Program(a,b,c,d) Flash28334_Program(a,b,c,d) +#define Flash_Verify(a,b,c,d) Flash28334_Verify(a,b,c,d) +#define Flash_ToggleTest(a,b) Flash28334_ToggleTest(a,b) +#define Flash_DepRecover() Flash28334_DepRecover() +#define Flash_APIVersionHex() Flash28334_APIVersionHex() +#define Flash_APIVersion() Flash28334_APIVersion() +#endif + +#if FLASH_F28332 +#define Flash_Erase(a,b) Flash28332_Erase(a,b) +#define Flash_Program(a,b,c,d) Flash28332_Program(a,b,c,d) +#define Flash_Verify(a,b,c,d) Flash28332_Verify(a,b,c,d) +#define Flash_ToggleTest(a,b) Flash28332_ToggleTest(a,b) +#define Flash_DepRecover() Flash28332_DepRecover() +#define Flash_APIVersionHex() Flash28332_APIVersionHex() +#define Flash_APIVersion() Flash28332_APIVersion() +#endif + +extern Uint16 Flash_Erase(Uint16 SectorMask, FLASH_ST *FEraseStat); +extern Uint16 Flash_Program(Uint16 *FlashAddr, Uint16 *BufAddr, Uint32 Length, + FLASH_ST *FProgStatus); +extern Uint16 Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, + FLASH_ST *FVerifyStat); +extern void Flash_ToggleTest(volatile Uint32 *ToggleReg, Uint32 Mask); +extern Uint16 Flash_DepRecover(); +extern float32 Flash_APIVersion(); +extern Uint16 Flash_APIVersionHex(); + +// +// Frequency Scale factor: The calling program must provide this global +// parameter used for frequency scaling the algo's. +// +extern Uint32 Flash_CPUScaleFactor; + +// +// Callback Function Pointer: +// A callback function can be specified. This function will be called +// at safe times during erase, program and verify. This function can +// then be used to service an external watchdog or send a communications +// packet. +// +// Note: +// THE FLASH AND OTP ARE NOT AVAILABLE DURING THIS FUNCTION CALL. +// THE FLASH/OTP CANNOT BE READ NOR CAN CODE EXECUTE FROM IT DURING THIS CALL +// DO NOT CALL ANY OF THE THE FLASH API FUNCTIONS DURING THIS CALL +// +extern void (*Flash_CallbackPtr) (void); + +// +// API load/run symbols: +// These symbols are defined by the linker during the link. Refer to the +// Flash28_API section in the example .cmd file: +// +// Flash28_API: +// { +// Flash28335_API_Library.lib(.econst) +// Flash28335_API_Library.lib(.text) +// } LOAD = FLASH, +// RUN = SARAM, +// LOAD_START(_Flash28_API_LoadStart), +// LOAD_END(_Flash28_API_LoadEnd), +// RUN_START(_Flash28_API_RunStart), +// PAGE = 0 +// +// These are used to copy the flash API from flash to SARAM +// +extern Uint16 Flash28_API_LoadStart; +extern Uint16 Flash28_API_LoadEnd; +extern Uint16 Flash28_API_RunStart; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // -- end FLASH2833x_API_LIBRARY_H + +// +// End of File +// + diff --git a/f2833x/examples/f28335_can_flash_kernel/Shared_Boot.c b/f2833x/examples/f28335_can_flash_kernel/Shared_Boot.c new file mode 100644 index 0000000..09ffd3c --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/Shared_Boot.c @@ -0,0 +1,321 @@ +//########################################################################### +// +// FILE: Shared_Boot.c +// +// TITLE: Boot loader shared functions +// +// Functions: +// +// void CopyData(void) +// Uint32 GetLongData(void) +// void ReadReservedFn(void) +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "Boot.h" +#include "Flash2833x_API_Library.h" + +// +// Defines +// +#ifndef NULL +#define NULL 0 +#endif +//#pragma DATA_SECTION(EmuKey,"EmuKeyVar"); +//#pragma DATA_SECTION(EmuBMode,"EmuBModeVar"); +//Uint16 EmuKey; +//Uint16 EmuBMode; + +// +// GetWordData is a pointer to the function that interfaces to the peripheral. +// Each loader assigns this pointer to it's particular GetWordData function. +// +uint16fptr GetOnlyWordData; + +// +// Function prototypes +// +Uint32 GetLongData(); +//void CopyData(void); +void ReadReservedFn(void); + +// +// After flash_program, send checksum to PC +// +void SendCheckSum(); + +#pragma CODE_SECTION(CopyData, "ramfuncs"); + +// +// Programming Buffer +// +Uint16 progBuf[PROG_BUFFER_LENGTH]; + +// +// Flash Status Structure +// +FLASH_ST FlashStatus; + +extern Uint32 Flash_CPUScaleFactor; +extern void (*Flash_CallbackPtr) (void); +unsigned int checksum; +Uint32 status1; + +// +// CopyData - This routine copies multiple blocks of data from the host to the +// specified RAM locations. There is no error checking on any of the +// destination addresses. That is it is assumed all addresses and block size +// values are correct. +// +// Multiple blocks of data are copied until a block size of 00 00 is +// encountered. +// +void +CopyData() +{ + struct HEADER + { + Uint16 BlockSize; + Uint32 DestAddr; + Uint32 ProgBuffAddr; + } BlockHeader; + + Uint16 wordData; + Uint16 status; + Uint16 i,j; + + // + // Make sure code security is disabled + // + CsmUnlock(); + + EALLOW; + Flash_CPUScaleFactor = SCALE_FACTOR; + Flash_CallbackPtr = NULL; + EDIS; + + status = Flash_Erase((SECTORA | SECTORB | SECTORC | SECTORD), + &FlashStatus); + status1=status; + if(status != STATUS_SUCCESS) + { + return ; + } + + // + // After Flash Erase, send the checksum to PC program. + // + SendCheckSum(); + + // + // Get the size in words of the first block + // + BlockHeader.BlockSize = (*GetOnlyWordData)(); + + // + // While the block size is > 0 copy the data to the DestAddr. There is no + // error checking as it is assumed the DestAddr is a valid memory location + // + while(BlockHeader.BlockSize != (Uint16)0x0000) + { + if(BlockHeader.BlockSize > PROG_BUFFER_LENGTH) + { + // + // Block is to big to fit into our buffer so we must program + // it in chunks + // + BlockHeader.DestAddr = GetLongData(); + + // + // Program as many full buffers as possible + // + for(j = 0; j < (BlockHeader.BlockSize / PROG_BUFFER_LENGTH); j++) + { + BlockHeader.ProgBuffAddr = (Uint32)progBuf; + for(i = 1; i <= PROG_BUFFER_LENGTH; i++) + { + wordData = (*GetOnlyWordData)(); + *(Uint16 *)BlockHeader.ProgBuffAddr++ = wordData; + } + status = Flash_Program((Uint16 *) BlockHeader.DestAddr, + (Uint16 *)progBuf, PROG_BUFFER_LENGTH, + &FlashStatus); + if(status != STATUS_SUCCESS) + { + return ; + } + BlockHeader.DestAddr += PROG_BUFFER_LENGTH; + + // + // After Flash program, send the checksum to PC program. + // + SendCheckSum(); + } + + // + // Program the leftovers + // + BlockHeader.ProgBuffAddr = (Uint32)progBuf; + for(i = 1; i <= (BlockHeader.BlockSize % PROG_BUFFER_LENGTH); i++) + { + wordData = (*GetOnlyWordData)(); + *(Uint16 *)BlockHeader.ProgBuffAddr++ = wordData; + } + status = Flash_Program((Uint16 *) BlockHeader.DestAddr, + (Uint16 *)progBuf, + (BlockHeader.BlockSize % PROG_BUFFER_LENGTH) + , &FlashStatus); + if(status != STATUS_SUCCESS) + { + return ; + } + + // + // After Flash program, send the checksum to PC program. + // + SendCheckSum(); + } + + else + { + // + // Block will fit into our buffer so we'll program it all at once + // + BlockHeader.DestAddr = GetLongData(); + BlockHeader.ProgBuffAddr = (Uint32)progBuf; + for(i = 1; i <= BlockHeader.BlockSize; i++) + { + wordData = (*GetOnlyWordData)(); + *(Uint16 *)BlockHeader.ProgBuffAddr++ = wordData; + } + status = Flash_Program((Uint16 *) BlockHeader.DestAddr, + (Uint16 *)progBuf, BlockHeader.BlockSize, + &FlashStatus); + if(status != STATUS_SUCCESS) + { + return ; + } + + // + // After Flash program, send the checksum to PC program. + // + SendCheckSum(); + } + + // + // Get the size of the next block + // + BlockHeader.BlockSize = (*GetOnlyWordData)(); + } + return; +} + +// +// GetLongData - This routine fetches a 32-bit value from the peripheral +// input stream. +// +Uint32 +GetLongData() +{ + Uint32 longData; + + // + // Fetch the upper 1/2 of the 32-bit value + // + longData = ( (Uint32)(*GetOnlyWordData)() << 16); + + // + // Fetch the lower 1/2 of the 32-bit value + // + longData |= (Uint32)(*GetOnlyWordData)(); + + return longData; +} + +// +// Read_ReservedFn - This function reads 8 reserved words in the header. +// None of these reserved words are used by the this boot loader at this time, +// they may be used in future devices for enhancements. Loaders that use +// these words use their own read function. +// +void +ReadReservedFn() +{ + Uint16 i; + + // + // Read and discard the 8 reserved words. + // + for(i = 1; i <= 8; i++) + { + GetOnlyWordData(); + } + return; +} + +// +// SendCheckSum - This function sends checksum to PC program. +// After flash memory erases or writes something, this functions will be +// running +// +void +SendCheckSum() +{ + while(!SciaRegs.SCICTL2.bit.TXRDY) + { + + } + SciaRegs.SCITXBUF = checksum & 0xFF; + + while(!SciaRegs.SCICTL2.bit.TXRDY) + { + + } + SciaRegs.SCITXBUF = (checksum >> 8) & 0xFF; + + checksum = 0; + + return; +} + +// +// End of File +// + diff --git a/f2833x/examples/f28335_can_flash_kernel/main.c b/f2833x/examples/f28335_can_flash_kernel/main.c new file mode 100644 index 0000000..e196ae6 --- /dev/null +++ b/f2833x/examples/f28335_can_flash_kernel/main.c @@ -0,0 +1,83 @@ +//########################################################################### +// +// FILE: main.c +// +// TITLE: F28335 CAN Flash Kernel Example +// +//! \addtogroup f2833x_example_list +//!

F28335 Flash Kernel (f28335_flash_kernel)

+//! +//! This example is for use with the CAN Flash Programmer utility. This +//! application is intended to be loaded into the device's RAM via the +//! CAN boot mode. After successfully loaded this program implements a +//! modified version of the CAN boot protocol that allows a user application +//! to be programmed into flash +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +extern Uint32 CAN_Boot(); + +// +// Function Prototypes +// +void (*ApplicationPtr) (void); + +// +// Main +// +Uint32 main(void) +{ + // + // GPIO and SCI are still setup from CAN_Boot() + // Setup sysctl and pll + // + DisableDog(); + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + DELAY_US(100); + + return CAN_Boot(); +} + +// +// End of File +// + diff --git a/f2833x/examples/f28335_flash_kernel/.ccsproject b/f2833x/examples/f28335_flash_kernel/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/f28335_flash_kernel/.cproject b/f2833x/examples/f28335_flash_kernel/.cproject new file mode 100644 index 0000000..9b710f2 --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/.cproject @@ -0,0 +1,120 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/f28335_flash_kernel/.project b/f2833x/examples/f28335_flash_kernel/.project new file mode 100644 index 0000000..b39faa7 --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/.project @@ -0,0 +1,78 @@ + + + f28335_flash_kernel + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_2833X_TO_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS + + + INSTALLROOT_2833X_TO_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/f28335_flash_kernel/Boot.h b/f2833x/examples/f28335_flash_kernel/Boot.h new file mode 100644 index 0000000..33cdc2b --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/Boot.h @@ -0,0 +1,124 @@ +//########################################################################### +// +// FILE: Boot.h +// +// TITLE: Boot ROM Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2833x_BOOT_H +#define F2833X_BOOT_H + +// +// Included Files +// +#include "DSP2833x_Device.h" // F2833x Headerfile Include File + +// +// Define for the length of the programming buffer +// +#define PROG_BUFFER_LENGTH 0x400 + +// +// Boot Modes Defines +// +// GPIO37 GPIO34 TRSTn +// TDO CMP2OUT +// Mode EMU x x 1 Emulator connected +// Mode 0 0 0 0 Parallel I/O +// Mode 1 0 1 0 SCI +// Mode 2 1 0 0 wait +// Mode 3 1 1 0 "Get Mode" +// +#define OTP_KEY 0x3D7BFE +#define OTP_BMODE 0x3D7BFF +#define KEY_VAL 0x55AA + +#define PARALLEL_BOOT 0x0000 +#define SCI_BOOT 0x0001 +#define WAIT_BOOT 0x0002 +#define GET_BOOT 0x0003 + +#define SPI_BOOT 0x0004 +#define I2C_BOOT 0x0005 +#define OTP_BOOT 0x0006 +#define RAM_BOOT 0x000A +#define FLASH_BOOT 0x000B + +// +// Defines for the fixed boot entry points +// +#define FLASH_ENTRY_POINT 0x3F7FF6 +#define OTP_ENTRY_POINT 0x3D7800 +#define RAM_ENTRY_POINT 0x000000 + +#define DIVSEL_BY_4 0 +#define DIVSEL_BY_2 2 +#define DIVSEL_BY_1 3 + +#define ERROR 1 +#define NO_ERROR 0 +#define EIGHT_BIT 8 +#define SIXTEEN_BIT 16 +#define EIGHT_BIT_HEADER 0x08AA +#define SIXTEEN_BIT_HEADER 0x10AA + +// +// Typedef +// +typedef Uint16 (* uint16fptr)(); + +extern uint16fptr GetWordData,GetOnlyWordData; +extern void (*Flash_CallbackPtr) (void); +extern Uint32 Flash_CPUScaleFactor; +extern Uint16 EmuKey; +extern Uint16 EmuBMode; +extern Uint16 CsmUnlock(); +#define Device_cal (void (*)(void))0x3D7C80 +#define Get_mode (Uint16 (*)(void))0x3D7CC0 + +// +// Defines configured by the boot ROM +// +#define BORTRIM (Uint16 *)0x0986 + +#endif // end of F2833X_BOOT_H definition + +// +// End of File +// + diff --git a/f2833x/examples/f28335_flash_kernel/DSP2833x_SysCtrl.c b/f2833x/examples/f28335_flash_kernel/DSP2833x_SysCtrl.c new file mode 100644 index 0000000..0616399 --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/DSP2833x_SysCtrl.c @@ -0,0 +1,459 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 15, 2009 09:54:05 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.c +// +// TITLE: DSP2833x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: Example initialization of system resources. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped to a load and +// run address using the linker cmd file. +// +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); + #else + #pragma CODE_SECTION(InitFlash, "ramfuncs"); + #endif +#endif + +// +// InitSysCtrl - This function initializes the System Control registers to a +// known state. +// - Disables the watchdog +// - Set the PLLCR for proper SYSCLKOUT frequency +// - Set the pre-scaler for the high and low frequency peripheral clocks +// - Enable the clocks to the peripherals +// +void +InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + + // + // Initialize the PLL control: PLLCR and DIVSEL + // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h + // + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + // + // Initialize the peripheral clocks + // + InitPeripheralClocks(); +} + +// +// InitFlash - This function initializes the Flash Control registers +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +void +InitFlash(void) +{ + EALLOW; + + // + // Enable Flash Pipeline mode to improve performance + // of code executed from Flash. + // + FlashRegs.FOPT.bit.ENPIPE = 1; + + // + // CAUTION + // Minimum waitstates required for the flash operating + // at a given CPU rate must be characterized by TI. + // Refer to the datasheet for the latest information. + // +#if CPU_FRQ_150MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; +#endif + +#if CPU_FRQ_100MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; +#endif + // + // CAUTION + // ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED + // + FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; + FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; + EDIS; + + // + // Force a pipeline flush to ensure that the write to + // the last register configured occurs before returning. + // + asm(" RPT #7 || NOP"); +} + +// +// ServiceDog - This function resets the watchdog timer. +// Enable this function for using ServiceDog in the application +// +void +ServiceDog(void) +{ + EALLOW; + SysCtrlRegs.WDKEY = 0x0055; + SysCtrlRegs.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void +DisableDog(void) +{ + EALLOW; + SysCtrlRegs.WDCR= 0x0068; + EDIS; +} + +// +// InitPll - This function initializes the PLLCR register. +// +void +InitPll(Uint16 val, Uint16 divsel) +{ + // + // Make sure the PLL is not running in limp mode + // + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0) + { + // + // Missing external clock has been detected + // Replace this line with a call to an appropriate + // SystemShutdown(); function. + // + asm(" ESTOP0"); + } + + // + // DIVSEL MUST be 0 before PLLCR can be changed from + // 0x0000. It is set to 0 by an external reset XRSn + // This puts us in 1/4 + // + if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; + EDIS; + } + + // + // Change the PLLCR + // + if (SysCtrlRegs.PLLCR.bit.DIV != val) + { + EALLOW; + + // + // Before setting PLLCR turn off missing clock detect logic + // + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; + SysCtrlRegs.PLLCR.bit.DIV = val; + EDIS; + + // + // Optional: Wait for PLL to lock. + // During this time the CPU will switch to OSCCLK/2 until + // the PLL is stable. Once the PLL is stable the CPU will + // switch to the new PLL value. + // + // This time-to-lock is monitored by a PLL lock counter. + // + // Code is not required to sit and wait for the PLL to lock. + // However, if the code does anything that is timing critical, + // and requires the correct clock be locked, then it is best to + // wait until this switching has completed. + // + + // + // Wait for the PLL lock bit to be set. + // + + // + // The watchdog should be disabled before this loop, or fed within + // the loop via ServiceDog(). + // + + // + // Uncomment to disable the watchdog + // + DisableDog(); + + while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) + { + // + // Uncomment to service the watchdog + // + //ServiceDog(); + } + + EALLOW; + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; + EDIS; + } + + // + // If switching to 1/2 + // + if((divsel == 1)||(divsel == 2)) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel; + EDIS; + } + + // + // NOTE: ONLY USE THIS SETTING IF PLL IS BYPASSED (I.E. PLLCR = 0) OR OFF + // If switching to 1/1 + // * First go to 1/2 and let the power settle + // The time required will depend on the system, this is only an example + // * Then switch to 1/1 + // + if(divsel == 3) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 2; + DELAY_US(50L); + SysCtrlRegs.PLLSTS.bit.DIVSEL = 3; + EDIS; + } +} + +// +// InitPeripheralClocks - This function initializes the clocks to the +// peripheral modules. First the high and low clock prescalers are set +// Second the clocks are enabled to each peripheral. To reduce power, leave +// clocks to unused peripherals disabled +// +// Note: If a peripherals clock is not enabled then you cannot +// read or write to the registers for that peripheral +// +void +InitPeripheralClocks(void) +{ + EALLOW; + + // + // HISPCP/LOSPCP prescale register settings, normally it will be set to + // default values + // + SysCtrlRegs.HISPCP.all = 0x0001; + SysCtrlRegs.LOSPCP.all = 0x0002; + + // + // XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT + // XTIMCLK = SYSCLKOUT/2 + // + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + + // + // XCLKOUT = XTIMCLK/2 + // + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + // + // Enable XCLKOUT + // + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + + // + // Peripheral clock enables set for the selected peripherals. + // If you are not using a peripheral leave the clock off + // to save on power. + // + // Note: not all peripherals are available on all 2833x derivates. + // Refer to the datasheet for your particular device. + // + // This function is not written to be an example of efficient code. + // + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC + + // + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI + // reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC to + // function according to specification. The clocks to the ADC MUST be + // enabled before calling this function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + // + ADC_cal(); + + SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C + SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A + SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B + SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C + SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A + SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A + SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A + SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B + + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM + SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 + SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2 + SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3 + SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4 + SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5 + SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6 + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM + + SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3 + SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4 + SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5 + SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6 + SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1 + SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2 + SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1 + SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2 + + SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2 + + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK + SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock + + EDIS; +} + +// +// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with +// current password for the DSP. Returns 1 if unlock is successful. +// +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 +Uint16 +CsmUnlock() +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the + // DSP. + // + EALLOW; + CsmRegs.KEY0 = 0xFFFF; + CsmRegs.KEY1 = 0xFFFF; + CsmRegs.KEY2 = 0xFFFF; + CsmRegs.KEY3 = 0xFFFF; + CsmRegs.KEY4 = 0xFFFF; + CsmRegs.KEY5 = 0xFFFF; + CsmRegs.KEY6 = 0xFFFF; + CsmRegs.KEY7 = 0xFFFF; + EDIS; + + // + // Perform a dummy read of the password locations if they match the key + // values, the CSM will unlock + // + temp = CsmPwl.PSWD0; + temp = CsmPwl.PSWD1; + temp = CsmPwl.PSWD2; + temp = CsmPwl.PSWD3; + temp = CsmPwl.PSWD4; + temp = CsmPwl.PSWD5; + temp = CsmPwl.PSWD6; + temp = CsmPwl.PSWD7; + + // + // If the CSM unlocked, return succes, otherwise return failure. + // + if (CsmRegs.CSMSCR.bit.SECURE == 0) + { + return STATUS_SUCCESS; + } + else + { + return STATUS_FAIL; + } +} + +// +// End of file +// + diff --git a/f2833x/examples/f28335_flash_kernel/Debug/f28335_flash_kernel.txt b/f2833x/examples/f28335_flash_kernel/Debug/f28335_flash_kernel.txt new file mode 100644 index 0000000..91706da --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/Debug/f28335_flash_kernel.txt @@ -0,0 +1,254 @@ + +AA 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 +00 00 00 00 40 00 42 9A +D4 00 00 00 00 80 0C FE 40 76 DA 93 22 76 AA 28 DF 01 AB 28 DB F9 1F 76 +11 03 02 A9 1F 76 11 03 00 02 00 1E 1A 76 69 FF 00 8F 06 C0 0F 9A 40 76 +B5 94 4A 96 1F 76 00 03 4A 0E 04 1E 4A 92 C0 56 97 00 40 76 5F 99 1F 76 +00 03 02 C5 67 3E 48 96 EF FF 8B 00 A9 1B 00 04 5C 69 40 76 3D 99 46 1E +4C 2B 2C 6F 00 8F 40 C0 44 A8 BF 56 4B 01 4B 1B 00 04 10 66 1F 76 00 03 +02 C5 67 3E 49 96 44 8A A9 A8 01 09 44 1E 49 92 C4 96 4B 0A 4B 1B 00 04 +F2 69 00 8F 06 C0 40 8F 40 C0 42 A8 20 FF 00 04 46 8A 40 76 0B 94 4A 96 +00 52 61 ED 20 FF 00 04 46 07 46 1E 40 76 5F 99 4C 0A 48 92 C9 FF 4C 54 +D2 66 00 8F 40 C0 44 A8 BF 56 4B 01 0D 6F 1F 76 00 03 02 C5 67 3E 49 96 +44 8A A9 A8 01 09 44 1E 49 92 C4 96 4B 0A 48 CC FF 03 4B 54 F1 67 00 8F +06 C0 40 8F 40 C0 42 A8 48 CC FF 03 46 8A A9 0E 40 76 0B 94 4A 96 00 52 +32 ED 40 76 5F 99 27 6F 40 76 3D 99 46 1E 00 8F 40 C0 44 A8 BF 56 4B 01 +0D 6F 1F 76 00 03 02 C5 67 3E 49 96 44 8A A9 A8 01 09 44 1E 49 92 C4 96 +4B 0A 48 92 4B 54 F2 67 00 8F 06 C0 40 8F 40 C0 42 A8 48 0E 46 8A 40 76 +0B 94 4A 96 00 52 0B ED 40 76 5F 99 1F 76 00 03 02 C5 67 3E 48 96 00 52 +C0 56 76 FF 8C FE 06 00 22 76 1F 76 2A 00 00 1A 01 00 06 CC FF F0 A9 1A +00 05 06 96 06 CC F0 FF 05 50 06 96 07 CC E0 FF 08 50 07 96 04 1A FF 01 +05 1A FF 01 1A 76 07 F6 00 77 69 FF 06 00 01 19 C3 56 FF FF 06 00 +51 0A 00 00 00 90 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 +F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 +BD 00 30 E6 00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 +00 06 42 29 16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 +16 56 25 76 00 6F 1B 76 F0 FF 00 E2 BD 00 30 E6 00 06 42 29 16 56 25 76 +00 6F 40 76 29 93 0A 9A 02 9B 40 76 31 93 40 76 7F 93 06 00 22 76 1F 76 +C0 01 BF 56 25 55 BF 56 25 AA 1A 76 69 FF 06 00 22 76 1F 76 C0 01 BF 56 +29 68 1A 76 69 FF 06 00 02 FE 42 97 41 96 1F 76 C0 01 11 CC 08 00 C2 FF +02 EC 25 76 11 CC 80 01 C6 FF 05 EC 22 76 11 18 7F FE 1A 76 21 92 0F 90 +41 54 16 EC 22 76 11 1A 40 00 41 92 21 CD F0 FF 0F 90 A8 CA 21 96 1A 76 +69 FF 40 76 29 93 11 92 01 90 01 52 FD ED 22 76 11 18 BF FF 1A 76 42 92 +01 52 03 EC 02 52 09 ED 22 76 11 CD 7F FE 03 90 86 FF A8 CA 11 96 1A 76 +42 92 03 52 11 ED 22 76 11 CC 7F FE A9 1A 00 01 11 96 69 FF 20 FF DA 05 +40 76 D0 80 1F 76 C0 01 11 1A 80 01 1A 76 82 FE 69 FF 06 00 22 76 1F 76 +C0 01 BF 56 1A 01 BF 56 1B 02 1F 76 2C 00 35 CC F8 FF 01 50 35 96 34 1A +04 00 34 18 F7 FF 1F 76 C0 01 1C 1A 08 00 69 FF 78 76 80 00 1F 76 C0 01 +1C 1A 10 00 1C 1A 00 04 1C 1A 00 08 1C 1A 20 00 1C 1A 00 01 1C 1A 00 10 +1C 1A 00 20 1C 1A 00 40 1C 1A 00 80 1C 18 FB FF 1D 1A 01 00 1D 1A 02 00 +1D 1A 04 00 1D 1A 08 00 1D 1A 10 00 1D 1A 20 00 1C 1A 04 00 1D 1A 00 04 +1D 1A 00 08 1D 1A 00 10 1D 1A 00 20 1D 1A 00 01 1D 1A 00 02 1D 1A 00 40 +1D 1A 00 80 20 1A 00 01 20 1A 00 02 20 1A 00 04 20 1A 00 08 20 1A 00 10 +20 1A 00 20 1A 76 69 FF 06 00 02 FE 22 76 1F 76 2B 00 20 28 FF FF 21 28 +FF FF 22 28 FF FF 23 28 FF FF 24 28 FF FF 25 28 FF FF 26 28 FF FF 27 28 +FF FF 1A 76 1F 76 FF CF 38 92 41 96 39 92 41 96 3A 92 41 96 3B 92 41 96 +3C 92 41 96 3D 92 41 96 3E 92 41 96 3F 92 41 96 1F 76 2B 00 2F 40 03 EE +01 9A 02 6F 00 9A 82 FE 69 FF 06 00 12 FE 46 1E 44 A0 42 A8 56 8A 40 76 +AE 99 4D 96 00 52 03 EC EF FF 9E 00 4D 28 E7 03 42 06 46 07 01 19 48 1E +42 C4 30 8F 00 00 A9 A8 A6 0F 0D 66 48 C4 33 8F FF FF A9 A8 A6 0F 07 68 +42 06 0F FF 60 00 4A 1E 4E 2B 16 6F 42 C4 38 8F 00 04 A9 A8 A6 0F 0E 66 +48 C4 38 8F FF 07 A9 A8 A6 0F 08 68 42 06 0A FF 01 0E 4A 1E BF 56 4E 10 +03 6F 0C 9A 70 6F 40 76 95 96 22 76 03 9A A9 F4 8D 0A 1A 76 01 02 50 1E +46 06 50 0F 5C 68 4E 5C 4A 06 69 FF 40 76 0C 97 4B 96 51 2B 51 92 2D 52 +28 67 00 BE 1F 76 11 03 00 06 A6 0F 03 EC 00 C5 67 3E 44 8A 4B 92 A9 1C +FF FF C4 CE B0 56 4D 1F 18 ED 44 8A C4 92 4B 54 14 EC 44 8A 4B 92 5E FF +C4 CA 4C 96 4E 5D 4C 5C 4A 06 40 76 4A 97 4E 5C 4A 06 40 76 0C 97 4B 96 +51 0A 51 92 2D 52 DA 68 44 8A C4 92 4B 54 1C EC 4D 1B E7 03 B1 56 4D 1E +56 8A 4B 92 DC 96 44 C5 56 8A C7 92 D4 96 4E 92 08 ED 56 83 30 8F 00 00 +A9 A8 4A 07 C5 1E 13 6F 56 83 38 8F 00 04 A9 A8 4A 07 C5 1E 0C 6F 01 02 +01 56 44 00 4A 07 4A 1E 01 02 50 07 50 1E 46 06 50 0F A6 67 69 FF 40 76 +88 96 4D 1B E7 03 02 ED 4D 2B 4D 92 92 FE 06 00 06 FE 44 A8 41 96 44 8A +40 76 AE 99 46 96 00 52 03 EC EF FF 95 00 46 28 E7 03 41 18 FF 00 41 92 +04 ED 14 9A EF FF 8C 00 40 76 95 96 22 76 03 9A A9 F4 8D 0A 1A 76 BF 56 +45 07 45 0E 00 8F 00 D0 31 FF 01 56 A4 00 44 83 69 FF 80 9A C4 8A 40 76 +63 98 46 96 00 52 B0 56 46 18 05 ED 45 93 45 0B 00 53 EC ED 46 92 5D ED +45 2B 45 92 07 52 59 66 45 58 00 8F 20 D0 94 92 41 CE 4D EC 45 0E 00 8F +00 D0 40 8F 02 D0 31 FF 01 56 A4 00 45 0E 31 FF 01 56 A5 00 C4 8A C5 92 +44 83 40 76 7B 99 46 96 00 52 13 ED 45 0E 00 8F 00 D0 40 8F 02 D0 31 FF +01 56 A4 00 45 0E 31 FF 01 56 A5 00 C4 8A C5 92 44 83 40 76 09 98 46 96 +00 52 14 ED 45 0E 00 8F 00 D0 40 8F 02 D0 31 FF 01 56 A4 00 45 0E 31 FF +01 56 A5 00 C4 8A C5 92 44 83 40 76 63 98 46 96 12 6F 45 0E 00 8F 00 D0 +40 8F 02 D0 31 FF 01 56 A4 00 45 0E 31 FF 01 56 A5 00 C4 8A C5 92 44 83 +40 76 63 98 46 92 05 ED 45 0A 45 92 07 52 A9 69 46 92 0A EC 45 0E 00 8F +00 D0 31 FF 01 56 A4 00 C4 06 44 8A C4 1E 40 76 88 96 46 92 86 FE 06 00 +08 FE 43 7C 42 1E 40 76 13 9A 47 96 40 76 4A 9A 46 96 42 06 40 76 D9 96 +45 96 03 9A A9 F4 91 0A 0A 9A A9 F4 8C 0A 00 9A 02 9B 40 76 1F 9A 43 92 +A9 1A 0B 0A A9 F4 90 0A 20 FF 99 19 40 76 1F 9A 43 92 A9 1A 0B 02 A9 F4 +90 0A 22 FF 33 33 40 76 1F 9A 45 58 00 8F 9C 0A 94 92 44 96 43 92 A9 1A +0B 0A A9 F4 90 0A 00 9A 01 9B 40 76 1F 9A A9 28 0F 0A A9 F4 90 0A 20 FF +99 19 40 76 1F 9A 1A 76 46 92 40 76 4E 9A 47 F4 77 70 44 92 88 FE 06 00 +08 FE 44 7D 43 7C 42 1E 40 76 13 9A 47 96 40 76 4A 9A 46 96 42 06 40 76 +D9 96 04 9A A9 F4 91 0A 06 9A A9 F4 8B 0A 0B 9A A9 F4 89 0A 03 9A A9 F4 +8C 0A 43 F4 8A 0A 00 9A 02 9B 40 76 1F 9A 44 92 A9 1A 0B 0A A9 F4 90 0A +45 2B 43 92 45 54 09 68 00 9A 02 9B 40 76 1F 9A 45 0A 43 92 45 54 F9 67 +44 92 A9 1A 0B 02 A9 F4 90 0A 2F FF 18 15 40 76 1F 9A 44 92 A9 1A 0B 0A +A9 F4 90 0A 00 9A 28 9B 40 76 1F 9A A9 28 0F 0A A9 F4 90 0A 20 FF 99 19 +40 76 1F 9A 1A 76 46 92 40 76 4E 9A 47 F4 77 70 88 FE 06 00 22 76 1F 76 +C0 01 1C 1A 00 04 BF 56 1B 02 1F 76 C1 01 1A 28 00 80 BF 56 10 07 BF 56 +11 03 14 2B BF 56 11 23 1F 76 BE 01 0D 18 FF CF 09 1A 00 05 05 1A 00 03 +1A 76 69 FF 06 00 02 FE 1F 76 C1 01 BF 56 13 01 1C 1A 00 20 1C 1A 00 40 +1C CC 00 80 CE FF 01 52 FC ED 1C 1A 00 40 1C 18 FF DF 15 CC 40 00 C5 FF +01 52 FC ED 17 C6 41 96 19 96 82 FE 06 00 02 FE 00 8F 69 96 1F 76 00 03 +02 A8 40 76 EF 95 40 76 0C 96 1F 76 00 03 00 2B 40 76 69 96 A9 1B AA 08 +04 EC 3F 8F F6 7F 09 6F 40 76 4F 99 40 76 3D 99 42 1E 40 76 00 80 42 8A +82 FE A9 A8 06 00 02 FE 41 2B 42 2B 1F 76 C1 01 15 CC 40 00 C5 FF 01 52 +FA ED 17 C6 41 96 19 96 15 CC 40 00 C5 FF 01 52 FC ED 17 C6 42 96 19 96 +1F 76 00 03 41 92 00 94 42 94 00 96 03 56 42 08 41 98 41 92 82 FE 06 00 +02 FE 41 2B 42 2B 1F 76 C1 01 15 CC 40 00 C5 FF 01 52 FA ED 17 C6 41 96 +15 CC 40 00 C5 FF 01 52 FC ED 17 C6 42 96 1F 76 00 03 41 92 00 94 42 94 +00 96 03 56 42 08 41 98 41 92 82 FE 06 00 22 76 40 76 BA 96 00 9A A9 F4 +81 0A A9 F5 90 0A 04 F0 A9 F4 90 0A 1A 76 06 00 22 76 00 9A A9 F4 82 0A +40 76 BA 96 A9 28 55 AA A9 F4 81 0A A9 28 0D 0E A9 F4 90 0A 00 9A 03 9B +40 76 1F 9A 1F 76 11 03 00 06 00 BE A6 0F 03 EC 00 C5 67 3E A9 28 0F 0A +A9 F4 90 0A A9 28 CC 4C 03 9B 40 76 1F 9A 1A 76 06 00 00 9A A9 F4 91 0A +A9 F4 94 0A A9 F4 98 0A A9 F4 99 0A A9 F4 9A 0A A9 F4 9B 0A A9 F4 92 0A +A9 F4 89 0A A9 F4 8A 0A A9 F4 8B 0A A9 F4 8C 0A 0A 9A A9 F4 88 0A A9 28 +0C 0C A9 F4 90 0A 06 00 02 FE 42 1E 22 76 A9 28 0F 0A A9 F4 90 0A 00 8F +94 0A 01 29 42 06 41 FF C4 96 42 06 03 90 82 FE 06 00 22 76 00 9A A9 F4 +91 0A A9 28 0F 0A A9 F4 90 0A 00 9A A9 F4 89 0A A9 F4 8A 0A A9 F4 8B 0A +A9 F4 8C 0A 20 FF 99 19 40 76 1F 9A 1A 76 06 00 A9 28 FF FF A9 F4 98 0A +A9 F4 99 0A A9 F4 9A 0A A9 F4 9B 0A 06 00 08 FE 43 7C 42 1E 40 76 13 9A +47 96 40 76 4A 9A 46 96 42 06 40 76 D9 96 44 96 43 92 A9 1A 0B 0A A9 F4 +90 0A 01 9A A9 F4 91 0A 04 9A A9 F4 89 0A 20 FF 99 19 40 76 1F 9A 43 92 +A9 1A 0B 02 A9 F4 90 0A A9 28 66 66 01 9B 40 76 1F 9A 44 58 00 8F 9C 0A +94 92 45 96 43 92 A9 1A 0B 0A A9 F4 90 0A 00 9A 01 9B 40 76 1F 9A 40 76 +EA 96 46 92 40 76 4E 9A 47 F4 77 70 45 92 88 FE 06 00 08 FE 44 7D 43 7C +42 1E 40 76 13 9A 47 96 40 76 4A 9A 46 96 42 06 40 76 D9 96 45 96 40 76 +01 97 45 58 00 8F 98 0A 43 92 94 96 44 92 A9 1A 0B 0A A9 F4 90 0A 02 9A +A9 F4 91 0A 09 9A A9 F4 89 0A 06 9A A9 F4 8B 0A 20 FF 99 19 40 76 1F 9A +44 92 A9 1A 0B 02 A9 F4 90 0A 00 9A 04 9B 40 76 1F 9A 44 92 A9 1A 0B 0A +A9 F4 90 0A 00 9A 01 9B 40 76 1F 9A 40 76 EA 96 46 92 40 76 4E 9A 47 F4 +77 70 88 FE 06 00 08 FE 43 7C 42 1E 40 76 13 9A 47 96 40 76 4A 9A 46 96 +42 06 40 76 D9 96 45 96 43 92 A9 1A 0B 0A A9 F4 90 0A 05 9A A9 F4 91 0A +20 FF 99 19 40 76 1F 9A 43 92 A9 1A 0B 02 A9 F4 90 0A 00 9A 08 9B 40 76 +1F 9A 45 58 00 8F 9C 0A 94 92 44 96 43 92 A9 1A 0B 0A A9 F4 90 0A 20 FF +99 19 40 76 1F 9A 40 76 EA 96 46 92 40 76 4E 9A 47 F4 77 70 44 92 88 FE +06 00 08 FE 44 7D 43 7C 42 1E 40 76 13 9A 47 96 40 76 4A 9A 46 96 42 06 +40 76 D9 96 45 96 40 76 01 97 45 58 00 8F 98 0A 43 92 94 96 44 92 A9 1A +0B 0A A9 F4 90 0A 06 9A A9 F4 91 0A A9 F4 8B 0A A9 F4 89 0A 00 9A A9 F4 +8C 0A 00 9A 0A 9B 40 76 1F 9A 44 92 A9 1A 0B 02 A9 F4 90 0A 2F FF E8 03 +40 76 1F 9A 44 92 A9 1A 0B 0A A9 F4 90 0A 00 9A 01 9B 40 76 1F 9A 40 76 +EA 96 46 92 40 76 4E 9A 47 F4 77 70 88 FE 06 00 10 FE 46 A0 43 96 42 A8 +42 C4 30 8F 00 00 A9 A8 A6 0F 11 66 43 88 42 06 33 8F FF FF A6 0D 01 19 +A6 1E A9 A8 A6 0F 07 68 42 06 0F FF 60 00 50 1E 4D 2B 03 6F 0C 9A 3D 6F +BF 56 49 16 48 2B 4B 2B 4A 2B 4C 2B 50 06 4D 5C 40 76 55 95 47 96 00 BE +1F 76 11 03 00 06 A6 0F 03 EC 00 C5 67 3E 47 1B FF FF 16 EC 4A 1B 88 13 +B7 56 49 16 18 67 50 06 48 5C 4D 5D 40 76 9D 95 4B 0A 4A 0A 48 92 0A 52 +0B 67 4B 92 0F 52 08 68 4B 2B 48 0A 05 6F 4C 0A 01 02 50 07 50 1E 43 92 +4C 54 D5 66 40 76 EA 96 43 92 4C 54 05 ED 47 1B FF FF 02 ED 49 2B 49 92 +90 FE 06 00 10 FE 46 A0 43 96 42 A8 4B 28 E7 03 42 C4 30 8F 00 00 A9 A8 +A6 0F 0D 66 42 C4 33 8F FF FF A9 A8 A6 0F 07 68 42 06 0F FF 60 00 4E 1E +4F 2B 03 6F 0C 9A 38 6F BF 56 48 01 BF 56 4A 17 49 2B 49 1B D0 07 21 66 +4E 06 4F 5C 40 76 8C 97 47 96 00 BE 1F 76 11 03 00 06 A6 0F 03 EC 00 C5 +67 3E 47 92 08 EC 5E FF 4F 5D A9 5C 4E 06 40 76 C6 97 07 6F 4A 2B 01 02 +4E 07 4E 1E 48 0A 05 6F 49 0A 49 1B D0 07 E1 69 4A 92 06 EC 49 1B D0 07 +B6 56 4B 17 04 66 43 92 48 54 D1 67 4B 92 17 52 02 EC 4B 2B 4B 92 90 FE +06 00 AD 28 00 04 69 FF 1F 56 16 56 1A 56 10 E6 00 02 40 29 1F 76 00 00 +02 29 1B 76 22 76 A9 28 D4 80 A8 28 00 00 01 09 1B 61 C0 76 D4 80 04 29 +0F 6F 00 9B A9 24 01 DF 04 6C 04 29 A8 24 01 DF A6 1E A1 F7 86 24 A7 06 +A1 81 01 09 A7 1E A9 24 03 63 5C FF 04 3B A9 59 01 DF 09 00 EC FF 1A 76 +A9 28 FF FF A8 28 FF FF 01 09 0E 61 FF 76 FF FF 06 6F 01 DF BD C3 A7 1E +67 3E BE C5 A9 24 01 DF A8 24 58 FF F7 60 40 76 D7 99 40 76 F4 99 0C FE +46 A8 43 7D 42 1E 4B 28 E7 03 49 28 01 00 43 92 49 54 2D 68 4A 2B 4A 92 +2D 52 1B 67 4F 5C 42 06 40 76 0C 97 47 96 1F 76 11 03 00 06 00 BE A6 0F +03 EC 00 C5 67 3E 47 92 0C EC 5E FF 48 96 48 5C 4F 5D 42 06 40 76 4A 97 +4A 0A 4A 92 2D 52 E7 68 47 92 06 EC 4F 92 04 ED 4B 28 15 00 08 6F 42 06 +01 09 42 1E 49 0A 43 92 49 54 D5 67 4B 92 15 52 05 EC A9 1B E7 03 02 ED +4B 2B 4B 92 8C FE 06 00 02 FE 1F 76 00 03 02 C5 67 3E 01 29 A9 25 42 1E +1F 76 00 03 02 C5 67 3E A9 0E 42 98 41 99 42 06 82 FE 06 00 02 FE BF 56 +41 01 41 92 08 52 09 66 1F 76 00 03 02 C5 67 3E 41 0A 41 92 08 52 F9 69 +82 FE 06 00 1F 76 C1 01 14 CC 80 00 C6 FF FB EC 1F 76 00 03 00 C6 1F 76 +C1 01 19 96 14 CC 80 00 C6 FF FD EC 1F 76 00 03 00 CC 00 FF 1F 76 C1 01 +C7 FF 19 96 1F 76 00 03 00 2B 06 00 0C FE 48 A0 45 96 44 A8 44 C4 30 8F +00 00 A9 A8 A6 0F 10 66 45 88 44 06 33 8F FF FF A6 0D 01 19 A6 1E A9 A8 +A6 0F 06 68 44 06 0F FF 60 00 4C 1E 03 6F 0C 9A 17 6F BF 56 41 40 4C 06 +45 5D 48 8A 40 76 FC 98 BF 56 41 80 40 8F 00 04 48 8A 4C 06 40 76 FC 98 +41 2B 45 5D 48 8A 4C 06 40 76 FC 98 49 96 8C FE 06 00 BD AA A4 86 40 76 +0B 9A A9 AA 08 EC 00 02 A2 8A C4 1E A2 8A D4 2B A2 8A DC 2B 3F 8F B9 FF +C4 1B FE FF 03 EC 0E 9A 14 6F A9 F5 82 08 FA 52 0A EC EF 52 06 ED 38 8F +90 00 C4 92 EF 52 03 EC 0D 9A 07 6F A9 F5 88 0A 03 EC 00 9A 02 6F 0A 9A +BE 86 06 00 A9 28 FF FF AA 28 FF FF AB 28 FF FF A8 28 FF FF AB 0F 04 ED +00 D4 00 BE 0B 6F A9 27 A9 28 FF FF A9 2F A4 A9 C4 88 A9 28 FF FF 02 09 +A9 8A A6 92 40 76 2C 9A 06 00 00 77 00 6F 1F 76 11 03 BD B2 06 C5 A9 59 +67 3E 1F 76 11 03 0A C5 A7 06 03 EC A1 92 67 3E 1F 76 11 03 08 06 03 EC +A7 1E 67 3E 40 76 F2 99 BE 8B 06 00 22 76 A9 F5 29 70 68 50 A9 F4 29 70 +1A 76 06 00 02 FE 41 F5 77 70 A9 F5 77 70 A9 18 FE FF A9 F4 77 70 41 92 +82 FE 06 00 1F 76 11 03 A9 87 63 56 02 00 34 19 C4 56 06 00 43 FF 01 19 +C2 56 FF FF 06 00 40 76 29 93 0A 9A 02 9B 40 76 31 93 20 FF B6 0B 40 76 +D0 80 40 76 28 96 06 00 1F 76 11 03 04 A8 06 00 1F 76 11 03 06 A8 06 00 +06 00 1F 56 22 76 C0 B9 29 28 68 00 1A 76 40 00 B6 98 08 76 30 3B BE 92 +06 00 BD 96 00 76 06 00 +20 00 00 00 D4 80 FE FF 40 C4 00 00 00 00 00 00 FE FF 42 C4 00 00 00 00 +00 00 FE FF 44 C4 00 00 41 9A 00 00 FE FF 46 C4 00 00 41 9A 00 00 FE FF +48 C4 00 00 00 00 00 00 FE FF 4A C4 00 00 00 00 00 00 00 00 00 00 +28 00 00 00 00 D0 00 00 30 00 00 80 00 00 00 80 30 00 00 80 00 00 00 00 +31 00 00 80 00 00 00 80 31 00 00 80 00 00 00 00 32 00 00 80 00 00 00 80 +32 00 00 80 00 00 00 00 33 00 00 80 00 00 00 80 33 00 00 80 00 00 80 00 +40 00 20 00 10 00 08 00 04 00 02 00 01 00 +26 00 00 00 50 00 AD 28 00 04 1F 56 16 56 1A 56 40 29 1F 76 00 00 02 29 +69 FF 40 76 2C 9A CF 56 02 00 AD 28 00 04 BD 2B BD 2B BD 1E 07 00 33 56 +AC 1E A9 58 A9 59 A9 5A A9 5B A9 5C A9 5D A9 88 A9 80 1F 76 00 00 BD 2B +BD 28 0B 0A 00 76 13 76 06 00 00 00 + \ No newline at end of file diff --git a/f2833x/examples/f28335_flash_kernel/Exit_Boot.asm b/f2833x/examples/f28335_flash_kernel/Exit_Boot.asm new file mode 100644 index 0000000..252ff7e --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/Exit_Boot.asm @@ -0,0 +1,205 @@ +;; TI File $Revision: /main/1 $ +;; Checkin $Date: August 13, 2012 15:28:34 $ +;;########################################################################### +;; +;; FILE: Init_Boot.asm +;; +;; TITLE: Boot Rom Initialization and Exit routines. +;; +;; Functions: +;; +;; _InitBoot +;; _ExitBoot +;; +;; Notes: +;; +;;########################################################################### +;; $TI Release: 2802x Boot ROM V2.00 $ +;; $Release Date: December 10, 2009 $ +;// $Copyright: +;// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;;########################################################################### + + .global _ExitBoot + .global _InitBoot + .ref _main + + + + .sect ".InitBoot" + +;----------------------------------------------- +; _InitBoot +;----------------------------------------------- +;----------------------------------------------- +; This function performs the initial boot routine +; for the boot ROM. +; +; This module performs the following actions: +; +; 1) Initalizes the stack pointer +; 2) Sets the device for C28x operating mode +; 3) Calls the main boot functions +; 4) Calls an exit routine +;----------------------------------------------- + + +_InitBoot: + +; Initalize the stack pointer. + +__stack: .usect ".stack",0 + MOV SP, #__stack ; Initalize the stack pointer + +; Initalize the device for running in C28x mode. + + C28OBJ ; Select C28x object mode + C28ADDR ; Select C27x/C28x addressing + C28MAP ; Set blocks M0/M1 for C28x mode + CLRC PAGE0 ; Always use stack addressing mode + MOVW DP,#0 ; Initialize DP to point to the low 64 K + CLRC OVM + +; Set PM shift of 0 + + SPM 0 + +; Decide which boot mode to use + LCR _main + +; Cleanup and exit. At this point the EntryAddr +; is located in the ACC register + BF _ExitBoot,UNC + + + +;----------------------------------------------- +; _ExitBoot +;----------------------------------------------- +;----------------------------------------------- +;This module cleans up after the boot loader +; +; 1) Make sure the stack is deallocated. +; SP = 0x400 after exiting the boot +; loader +; 2) Push 0 onto the stack so RPC will be +; 0 after using LRETR to jump to the +; entry point +; 2) Load RPC with the entry point +; 3) Clear all XARn registers +; 4) Clear ACC, P and XT registers +; 5) LRETR - this will also clear the RPC +; register since 0 was on the stack +;----------------------------------------------- + +_ExitBoot: + +;----------------------------------------------- +; Insure that the stack is deallocated +;----------------------------------------------- + + MOV SP,#__stack + +;----------------------------------------------- +; Clear the bottom of the stack. This will endup +; in RPC when we are finished +;----------------------------------------------- + + MOV *SP++,#0 + MOV *SP++,#0 + +;----------------------------------------------- +; Load RPC with the entry point as determined +; by the boot mode. This address will be returned +; in the ACC register. +;----------------------------------------------- + + PUSH ACC + POP RPC + +;----------------------------------------------- +; Put registers back in their reset state. +; +; Clear all the XARn, ACC, XT, and P and DP +; registers +; +; NOTE: Leave the device in C28x operating mode +; (OBJMODE = 1, AMODE = 0) +;----------------------------------------------- + ZAPA + MOVL XT,ACC + MOVZ AR0,AL + MOVZ AR1,AL + MOVZ AR2,AL + MOVZ AR3,AL + MOVZ AR4,AL + MOVZ AR5,AL + MOVZ AR6,AL + MOVZ AR7,AL + MOVW DP, #0 + +;------------------------------------------------ +; Restore ST0 and ST1. Note OBJMODE is +; the only bit not restored to its reset state. +; OBJMODE is left set for C28x object operating +; mode. +; +; ST0 = 0x0000 ST1 = 0x0A0B +; 15:10 OVC = 0 15:13 ARP = 0 +; 9: 7 PM = 0 12 XF = 0 +; 6 V = 0 11 M0M1MAP = 1 +; 5 N = 0 10 reserved +; 4 Z = 0 9 OBJMODE = 1 +; 3 C = 0 8 AMODE = 0 +; 2 TC = 0 7 IDLESTAT = 0 +; 1 OVM = 0 6 EALLOW = 0 +; 0 SXM = 0 5 LOOP = 0 +; 4 SPA = 0 +; 3 VMAP = 1 +; 2 PAGE0 = 0 +; 1 DBGM = 1 +; 0 INTM = 1 +;----------------------------------------------- + + MOV *SP++,#0 + MOV *SP++,#0x0A0B + POP ST1 + POP ST0 + +;------------------------------------------------ +; Jump to the EntryAddr as defined by the +; boot mode selected and continue execution +;----------------------------------------------- + + LRETR + +;eof ---------- diff --git a/f2833x/examples/f28335_flash_kernel/Flash28335_API_V210.lib b/f2833x/examples/f28335_flash_kernel/Flash28335_API_V210.lib new file mode 100644 index 0000000..9355d03 Binary files /dev/null and b/f2833x/examples/f28335_flash_kernel/Flash28335_API_V210.lib differ diff --git a/f2833x/examples/f28335_flash_kernel/Flash2833x_API_Config.h b/f2833x/examples/f28335_flash_kernel/Flash2833x_API_Config.h new file mode 100644 index 0000000..fa01194 --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/Flash2833x_API_Config.h @@ -0,0 +1,110 @@ +//########################################################################### +// +// FILE: Flash2833x_API_Config.h +// +// TITLE: F2833x Flash Algo's - User Settings +// +// NOTE: This file contains user defined settings that +// are used by the F2833x Flash APIs. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef FLASH2833X_API_CONFIG_H +#define FLASH2833X_API_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Variables that can be configured by the user +// + +// +// 1. Specify the device. +// Define the device to be programmed as "1" (no quotes). +// Define all other devices as "0" (no quotes). +// +#define FLASH_F28335 1 +#define FLASH_F28334 0 +#define FLASH_F28332 0 + +// +// 2. Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// that your application will use. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example: CLKIN is a 30MHz crystal. +// +// If the application will set PLLCR = 0xA then the CPU clock +// will be 150Mhz (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// DO NOT modify the code below this line +// +#define SCALE_FACTOR 1048576.0L*( (200L/CPU_RATE) ) // IQ20 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // -- end FLASH2833X_API_CONFIG_H + +// +// End of File +// + diff --git a/f2833x/examples/f28335_flash_kernel/Flash2833x_API_Library.h b/f2833x/examples/f28335_flash_kernel/Flash2833x_API_Library.h new file mode 100644 index 0000000..e52968b --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/Flash2833x_API_Library.h @@ -0,0 +1,318 @@ +//########################################################################### +// +// FILE: Flash2833x_API_Library.h +// +// TITLE: F2833x Flash Algo's main include file +// +// DESCRIPTION: This file should be included in any project that uses any of +// the F2833x flash APIs. +// +//########################################################################### +// $TI Release:$ +// $Release Date:$ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef FLASH2833X_API_LIBRARY_H +#define FLASH2833X_API_LIBRARY_H + +#include "Flash2833x_API_Config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// +// 28x Datatypes +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16/32/64-Bit Signed/Unsigned Integers and floating point +// variables: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// API Status Messages +// +// The following status values are returned from the API to the calling +// program. These can be used to determine if the API function passed +// or failed. +// + +// +// Defines +// + +// +// Operation passed, no errors were flagged +// +#define STATUS_SUCCESS 0 + +// +// The CSM is preventing the function from performing its operation +// +#define STATUS_FAIL_CSM_LOCKED 10 + +// +// Device REVID does not match that required by the API +// +#define STATUS_FAIL_REVID_INVALID 11 + +// +// Invalid address passed to the API +// +#define STATUS_FAIL_ADDR_INVALID 12 + +// +// Incorrect PARTID +// For example the F2806 API was used on a F2808 device. +// +#define STATUS_FAIL_INCORRECT_PARTID 13 + +// +// API/Silicon missmatch. An old version of the API is being used on silicon +// it is not valid for. Please update to the latest API. +// +#define STATUS_FAIL_API_SILICON_MISMATCH 14 + +// +// Erase Specific errors +// +#define STATUS_FAIL_NO_SECTOR_SPECIFIED 20 +#define STATUS_FAIL_PRECONDITION 21 +#define STATUS_FAIL_ERASE 22 +#define STATUS_FAIL_COMPACT 23 +#define STATUS_FAIL_PRECOMPACT 24 + +// +// Program Specific errors +// +#define STATUS_FAIL_PROGRAM 30 +#define STATUS_FAIL_ZERO_BIT_ERROR 31 + +// +// Verify Specific errors +// +#define STATUS_FAIL_VERIFY 40 + +// +// Busy is set by each API function before it determines a pass or fail +// condition for that operation. The calling function will will not receive +// this status condition back from the API +// +#define STATUS_BUSY 999 + +// +// Flash sector mask definitions +// +// The following macros can be used to form a mask specifying which sectors +// will be erased by the erase API function. +// +// Bit0 = Sector A +// Bit1 = Sector B +// Bit2 = Sector C +// Bit3 = Sector D +// Bit4 = Sector E +// Bit5 = Sector F +// Bit6 = Sector G +// Bit7 = Sector H +// +#define SECTORA (Uint16)0x0001 +#define SECTORB (Uint16)0x0002 +#define SECTORC (Uint16)0x0004 +#define SECTORD (Uint16)0x0008 +#define SECTORE (Uint16)0x0010 +#define SECTORF (Uint16)0x0020 +#define SECTORG (Uint16)0x0040 +#define SECTORH (Uint16)0x0080 + +#if FLASH_F28335 + // + // All sectors on an F28335 - Sectors A - H + // + #define SECTOR_F28335 (SECTORA|SECTORB|SECTORC|SECTORD|SECTORE|SECTORF|\ + SECTORG|SECTORH) +#endif // -- end FLASH_F28335 + +#if FLASH_F28334 + // + // All sectors on an F28334 - Sectors A - H + // + #define SECTOR_F28334 (SECTORA|SECTORB|SECTORC|SECTORD|SECTORE|SECTORF|\ + SECTORG|SECTORH) +#endif // -- end FLASH_F28334 + +#if FLASH_F28332 + // + // All sectors on an F28332 - Sectors A - D + // + #define SECTOR_F28332 (SECTORA|SECTORB|SECTORC|SECTORD) +#endif // -- end FLASH_F28332 + +// +// API Status Structure +// +// This structure is used to pass debug data back to the calling routine. +// Note that the Erase API function has 3 parts: precondition, erase and +// and compaction. Erase and compaction failures will not populate +// the expected and actual data fields. +// +typedef struct +{ + Uint32 FirstFailAddr; + Uint16 ExpectedData; + Uint16 ActualData; +} FLASH_ST; + +// +// Interface Function prototypes +// +// For each 28x Flash API library, the function names are of the form: +// Flash_() +// +// Where is the device: ie 2808, 2806, 2801 +// is the operation such as Erase, Program... +// +// For portability for users who may move between the F2808, F2806 and +// F2801, the following macro definitions are supplied. +// +// Using these macro definitions, the user can use instead make a generic +// call: Flash_ and the macro will map the call to the proper +// device function +// +// Note except for the toggle test function, all of the function prototypes +// are compatible with F281x devices as well. +// +#if FLASH_F28335 +#define Flash_Erase(a,b) Flash28335_Erase(a,b) +#define Flash_Program(a,b,c,d) Flash28335_Program(a,b,c,d) +#define Flash_Verify(a,b,c,d) Flash28335_Verify(a,b,c,d) +#define Flash_ToggleTest(a,b) Flash28335_ToggleTest(a,b) +#define Flash_DepRecover() Flash28335_DepRecover() +#define Flash_APIVersionHex() Flash28335_APIVersionHex() +#define Flash_APIVersion() Flash28335_APIVersion() +#endif + +#if FLASH_F28334 +#define Flash_Erase(a,b) Flash28334_Erase(a,b) +#define Flash_Program(a,b,c,d) Flash28334_Program(a,b,c,d) +#define Flash_Verify(a,b,c,d) Flash28334_Verify(a,b,c,d) +#define Flash_ToggleTest(a,b) Flash28334_ToggleTest(a,b) +#define Flash_DepRecover() Flash28334_DepRecover() +#define Flash_APIVersionHex() Flash28334_APIVersionHex() +#define Flash_APIVersion() Flash28334_APIVersion() +#endif + +#if FLASH_F28332 +#define Flash_Erase(a,b) Flash28332_Erase(a,b) +#define Flash_Program(a,b,c,d) Flash28332_Program(a,b,c,d) +#define Flash_Verify(a,b,c,d) Flash28332_Verify(a,b,c,d) +#define Flash_ToggleTest(a,b) Flash28332_ToggleTest(a,b) +#define Flash_DepRecover() Flash28332_DepRecover() +#define Flash_APIVersionHex() Flash28332_APIVersionHex() +#define Flash_APIVersion() Flash28332_APIVersion() +#endif + +extern Uint16 Flash_Erase(Uint16 SectorMask, FLASH_ST *FEraseStat); +extern Uint16 Flash_Program(Uint16 *FlashAddr, Uint16 *BufAddr, Uint32 Length, + FLASH_ST *FProgStatus); +extern Uint16 Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, + FLASH_ST *FVerifyStat); +extern void Flash_ToggleTest(volatile Uint32 *ToggleReg, Uint32 Mask); +extern Uint16 Flash_DepRecover(); +extern float32 Flash_APIVersion(); +extern Uint16 Flash_APIVersionHex(); + +// +// Frequency Scale factor: The calling program must provide this global +// parameter used for frequency scaling the algo's. +// +extern Uint32 Flash_CPUScaleFactor; + +// +// Callback Function Pointer: +// A callback function can be specified. This function will be called +// at safe times during erase, program and verify. This function can +// then be used to service an external watchdog or send a communications +// packet. +// +// Note: +// THE FLASH AND OTP ARE NOT AVAILABLE DURING THIS FUNCTION CALL. +// THE FLASH/OTP CANNOT BE READ NOR CAN CODE EXECUTE FROM IT DURING THIS CALL +// DO NOT CALL ANY OF THE THE FLASH API FUNCTIONS DURING THIS CALL +// +extern void (*Flash_CallbackPtr) (void); + +// +// API load/run symbols: +// These symbols are defined by the linker during the link. Refer to the +// Flash28_API section in the example .cmd file: +// +// Flash28_API: +// { +// Flash28335_API_Library.lib(.econst) +// Flash28335_API_Library.lib(.text) +// } LOAD = FLASH, +// RUN = SARAM, +// LOAD_START(_Flash28_API_LoadStart), +// LOAD_END(_Flash28_API_LoadEnd), +// RUN_START(_Flash28_API_RunStart), +// PAGE = 0 +// +// These are used to copy the flash API from flash to SARAM +// +extern Uint16 Flash28_API_LoadStart; +extern Uint16 Flash28_API_LoadEnd; +extern Uint16 Flash28_API_RunStart; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // -- end FLASH2833x_API_LIBRARY_H + +// +// End of File +// + diff --git a/f2833x/examples/f28335_flash_kernel/SCI_Boot.c b/f2833x/examples/f28335_flash_kernel/SCI_Boot.c new file mode 100644 index 0000000..e068988 --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/SCI_Boot.c @@ -0,0 +1,300 @@ +//########################################################################### +// +// FILE: SCI_Boot.c +// +// TITLE: SCI Boot mode routines +// +// Functions: +// +// Uint32 SCI_Boot(void) +// inline void SCIA_Init(void) +// inline void SCIA_AutobaudLock(void) +// Uint32 SCIA_GetWordData(void) +// +// Notes: +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "Boot.h" + +// +// Private functions +// +inline void SCIA_Init(void); +inline void SCIA_AutobaudLock(void); +Uint16 SCIA_GetWordData(void); +Uint16 SCIA_GetOnlyWordData(void); + +// +// External functions +// +extern void CopyData(void); +Uint32 GetLongData(void); +extern void ReadReservedFn(void); +extern unsigned int checksum; +extern Uint32 byteData1; + +// +// SCI_Boot - This module is the main SCI boot routine. It will load code via +// the SCI-A port. It will return a entry point address back to the InitBoot +// routine which in turn calls the ExitBoot routine. +// +Uint32 +SCI_Boot() + { + Uint32 EntryAddr; + + // + // Assign GetWordData to the SCI-A version of the function. + // GetOnlyWordData is a pointer to a function. This version doesn't send + // echo back each character. + // + GetOnlyWordData = SCIA_GetOnlyWordData; + + SCIA_Init(); + SCIA_AutobaudLock(); + checksum = 0; + + // + // If the KeyValue was invalid, abort the load and return the flash entry + // point. + // + if (SCIA_GetOnlyWordData() != 0x08AA) + { + return FLASH_ENTRY_POINT; + } + + ReadReservedFn(); + + EntryAddr = GetLongData(); + CopyData(); + + return EntryAddr; +} + +// +// SCIA_Init - Initialize the SCI-A port for communications with the host. +// +inline void +SCIA_Init() +{ + // + // Enable the SCI-A clocks + // + EALLOW; + SysCtrlRegs.PCLKCR0.bit.SCIAENCLK=1; + SysCtrlRegs.LOSPCP.all = 0x0002; + SciaRegs.SCIFFTX.all=0x8000; + + // + // 1 stop bit, No parity, 8-bit character, No loopback + // + SciaRegs.SCICCR.all = 0x0007; + + // + // Enable TX, RX, Use internal SCICLK + // + SciaRegs.SCICTL1.all = 0x0003; + + // + // Disable RxErr, Sleep, TX Wake, Disable Rx Interrupt, Tx Interrupt + // + SciaRegs.SCICTL2.all = 0x0000; + + // + // Relinquish SCI-A from reset + // + SciaRegs.SCICTL1.all = 0x0023; + + // + // Enable pull-ups on SCI-A pins + // + //GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; + //GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; + GpioCtrlRegs.GPAPUD.all &= 0xCFFFFFFF; + + // + // Enable the SCI-A pins + // + //GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; + //GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; + GpioCtrlRegs.GPAMUX2.all |= 0x05000000; + + // + // Input qual for SCI-A RX is asynch + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; + EDIS; + return; +} + +// +// SCIA_AutobaudLock - Perform autobaud lock with the host. +// Note that if autobaud never occurs the program will hang in this routine as +// there is no timeout mechanism included. +// +inline void +SCIA_AutobaudLock() +{ + Uint16 byteData; + + // + // Must prime baud register with >= 1 + // + SciaRegs.SCILBAUD = 1; + + // + // Prepare for autobaud detection. Set the CDC bit to enable autobaud + // detection and clear the ABD bit + // + SciaRegs.SCIFFCT.bit.CDC = 1; + SciaRegs.SCIFFCT.bit.ABDCLR = 1; + + // + // Wait until we correctly read an 'A' or 'a' and lock + // + while(SciaRegs.SCIFFCT.bit.ABD != 1) + { + + } + + // + // After autobaud lock, clear the ABD and CDC bits + // + SciaRegs.SCIFFCT.bit.ABDCLR = 1; + SciaRegs.SCIFFCT.bit.CDC = 0; + + while(SciaRegs.SCIRXST.bit.RXRDY != 1) + { + + } + byteData = SciaRegs.SCIRXBUF.bit.RXDT; + SciaRegs.SCITXBUF = byteData; + + return; +} + +// +// SCIA_GetWordData - This routine fetches two bytes from the SCI-A port and +// puts them together to form a single 16-bit value. It is assumed that the +// host is sending the data in the order LSB followed by MSB. +// +Uint16 +SCIA_GetWordData() +{ + Uint16 wordData; + Uint16 byteData; + + wordData = 0x0000; + byteData = 0x0000; + + // + // Fetch the LSB and verify back to the host + // + while(SciaRegs.SCIRXST.bit.RXRDY != 1) + { + + } + wordData = (Uint16)SciaRegs.SCIRXBUF.bit.RXDT; + SciaRegs.SCITXBUF = wordData; + + // + // Fetch the MSB and verify back to the host + // + while(SciaRegs.SCIRXST.bit.RXRDY != 1) + { + + } + byteData = (Uint16)SciaRegs.SCIRXBUF.bit.RXDT; + SciaRegs.SCITXBUF = byteData; + checksum += wordData + byteData; + + // + // form the wordData from the MSB:LSB + // + wordData |= (byteData << 8); + + return wordData; +} + +// +// SCIA_GetOnlyWordData - +// +Uint16 +SCIA_GetOnlyWordData() +{ + Uint16 wordData; + Uint16 byteData; + + wordData = 0x0000; + byteData = 0x0000; + + // + // Fetch the LSB and verify back to the host + // + while(SciaRegs.SCIRXST.bit.RXRDY != 1) + { + + } + wordData = (Uint16)SciaRegs.SCIRXBUF.bit.RXDT; + //SciaRegs.SCITXBUF = wordData; + + // + // Fetch the MSB and verify back to the host + // + while(SciaRegs.SCIRXST.bit.RXRDY != 1) + { + + } + byteData = (Uint16)SciaRegs.SCIRXBUF.bit.RXDT; + checksum += wordData + byteData; + + // + // form the wordData from the MSB:LSB + // + wordData |= (byteData << 8); + + return wordData; +} + +// +// End of File +// + diff --git a/f2833x/examples/f28335_flash_kernel/Shared_Boot.c b/f2833x/examples/f28335_flash_kernel/Shared_Boot.c new file mode 100644 index 0000000..dd27b72 --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/Shared_Boot.c @@ -0,0 +1,326 @@ +//########################################################################### +// +// FILE: Shared_Boot.c +// +// TITLE: Boot loader shared functions +// +// Functions: +// +// void CopyData(void) +// Uint32 GetLongData(void) +// void ReadReservedFn(void) +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "Boot.h" +#include "Flash2833x_API_Library.h" + +// +// Defines +// +#ifndef NULL +#define NULL 0 +#endif +//#pragma DATA_SECTION(EmuKey,"EmuKeyVar"); +//#pragma DATA_SECTION(EmuBMode,"EmuBModeVar"); +//Uint16 EmuKey; +//Uint16 EmuBMode; + +// +// GetWordData is a pointer to the function that interfaces to the peripheral. +// Each loader assigns this pointer to it's particular GetWordData function. +// +uint16fptr GetOnlyWordData; + +// +// Function prototypes +// +Uint32 GetLongData(); +//void CopyData(void); +void ReadReservedFn(void); + +// +// After flash_program, send checksum to PC +// +void SendCheckSum(); +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(CopyData, ".TI.ramfunc"); + #else + #pragma CODE_SECTION(CopyData, "ramfuncs"); + #endif +#endif + +// +// Programming Buffer +// +Uint16 progBuf[PROG_BUFFER_LENGTH]; + +// +// Flash Status Structure +// +FLASH_ST FlashStatus; + +extern Uint32 Flash_CPUScaleFactor; +extern void (*Flash_CallbackPtr) (void); +unsigned int checksum; +Uint32 status1; + +// +// CopyData - This routine copies multiple blocks of data from the host to the +// specified RAM locations. There is no error checking on any of the +// destination addresses. That is it is assumed all addresses and block size +// values are correct. +// +// Multiple blocks of data are copied until a block size of 00 00 is +// encountered. +// +void +CopyData() +{ + struct HEADER + { + Uint16 BlockSize; + Uint32 DestAddr; + Uint32 ProgBuffAddr; + } BlockHeader; + + Uint16 wordData; + Uint16 status; + Uint16 i,j; + + // + // Make sure code security is disabled + // + CsmUnlock(); + + EALLOW; + Flash_CPUScaleFactor = SCALE_FACTOR; + Flash_CallbackPtr = NULL; + EDIS; + + status = Flash_Erase((SECTORA | SECTORB | SECTORC | SECTORD), + &FlashStatus); + status1=status; + if(status != STATUS_SUCCESS) + { + return ; + } + + // + // After Flash Erase, send the checksum to PC program. + // + SendCheckSum(); + + // + // Get the size in words of the first block + // + BlockHeader.BlockSize = (*GetOnlyWordData)(); + + // + // While the block size is > 0 copy the data to the DestAddr. There is no + // error checking as it is assumed the DestAddr is a valid memory location + // + while(BlockHeader.BlockSize != (Uint16)0x0000) + { + if(BlockHeader.BlockSize > PROG_BUFFER_LENGTH) + { + // + // Block is to big to fit into our buffer so we must program + // it in chunks + // + BlockHeader.DestAddr = GetLongData(); + + // + // Program as many full buffers as possible + // + for(j = 0; j < (BlockHeader.BlockSize / PROG_BUFFER_LENGTH); j++) + { + BlockHeader.ProgBuffAddr = (Uint32)progBuf; + for(i = 1; i <= PROG_BUFFER_LENGTH; i++) + { + wordData = (*GetOnlyWordData)(); + *(Uint16 *)BlockHeader.ProgBuffAddr++ = wordData; + } + status = Flash_Program((Uint16 *) BlockHeader.DestAddr, + (Uint16 *)progBuf, PROG_BUFFER_LENGTH, + &FlashStatus); + if(status != STATUS_SUCCESS) + { + return ; + } + BlockHeader.DestAddr += PROG_BUFFER_LENGTH; + + // + // After Flash program, send the checksum to PC program. + // + SendCheckSum(); + } + + // + // Program the leftovers + // + BlockHeader.ProgBuffAddr = (Uint32)progBuf; + for(i = 1; i <= (BlockHeader.BlockSize % PROG_BUFFER_LENGTH); i++) + { + wordData = (*GetOnlyWordData)(); + *(Uint16 *)BlockHeader.ProgBuffAddr++ = wordData; + } + status = Flash_Program((Uint16 *) BlockHeader.DestAddr, + (Uint16 *)progBuf, + (BlockHeader.BlockSize % PROG_BUFFER_LENGTH) + , &FlashStatus); + if(status != STATUS_SUCCESS) + { + return ; + } + + // + // After Flash program, send the checksum to PC program. + // + SendCheckSum(); + } + + else + { + // + // Block will fit into our buffer so we'll program it all at once + // + BlockHeader.DestAddr = GetLongData(); + BlockHeader.ProgBuffAddr = (Uint32)progBuf; + for(i = 1; i <= BlockHeader.BlockSize; i++) + { + wordData = (*GetOnlyWordData)(); + *(Uint16 *)BlockHeader.ProgBuffAddr++ = wordData; + } + status = Flash_Program((Uint16 *) BlockHeader.DestAddr, + (Uint16 *)progBuf, BlockHeader.BlockSize, + &FlashStatus); + if(status != STATUS_SUCCESS) + { + return ; + } + + // + // After Flash program, send the checksum to PC program. + // + SendCheckSum(); + } + + // + // Get the size of the next block + // + BlockHeader.BlockSize = (*GetOnlyWordData)(); + } + return; +} + +// +// GetLongData - This routine fetches a 32-bit value from the peripheral +// input stream. +// +Uint32 +GetLongData() +{ + Uint32 longData; + + // + // Fetch the upper 1/2 of the 32-bit value + // + longData = ( (Uint32)(*GetOnlyWordData)() << 16); + + // + // Fetch the lower 1/2 of the 32-bit value + // + longData |= (Uint32)(*GetOnlyWordData)(); + + return longData; +} + +// +// Read_ReservedFn - This function reads 8 reserved words in the header. +// None of these reserved words are used by the this boot loader at this time, +// they may be used in future devices for enhancements. Loaders that use +// these words use their own read function. +// +void +ReadReservedFn() +{ + Uint16 i; + + // + // Read and discard the 8 reserved words. + // + for(i = 1; i <= 8; i++) + { + GetOnlyWordData(); + } + return; +} + +// +// SendCheckSum - This function sends checksum to PC program. +// After flash memory erases or writes something, this functions will be +// running +// +void +SendCheckSum() +{ + while(!SciaRegs.SCICTL2.bit.TXRDY) + { + + } + SciaRegs.SCITXBUF = checksum & 0xFF; + + while(!SciaRegs.SCICTL2.bit.TXRDY) + { + + } + SciaRegs.SCITXBUF = (checksum >> 8) & 0xFF; + + checksum = 0; + + return; +} + +// +// End of File +// + diff --git a/f2833x/examples/f28335_flash_kernel/main.c b/f2833x/examples/f28335_flash_kernel/main.c new file mode 100644 index 0000000..e98b4fe --- /dev/null +++ b/f2833x/examples/f28335_flash_kernel/main.c @@ -0,0 +1,83 @@ +//########################################################################### +// +// FILE: main.c +// +// TITLE: F28335 Flash Kernel Example +// +//! \addtogroup f2833x_example_list +//!

F28335 Flash Kernel (f28335_flash_kernel)

+//! +//! This example is for use with the SerialLoader2000 utility. This +//! application is intended to be loaded into the device's RAM via the +//! SCI boot mode. After successfully loaded this program implements a +//! modified version of the SCI boot protocol that allows a user application +//! to be programmed into flash +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +extern Uint32 SCI_Boot(); + +// +// Function Prototypes +// +void (*ApplicationPtr) (void); + +// +// Main +// +Uint32 main(void) +{ + // + // GPIO and SCI are still setup from Sci_Boot() + // Setup sysctl and pll + // + DisableDog(); + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + DELAY_US(100); + + return SCI_Boot(); +} + +// +// End of File +// + diff --git a/f2833x/examples/flash_f28335/.ccsproject b/f2833x/examples/flash_f28335/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/flash_f28335/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/flash_f28335/.cproject b/f2833x/examples/flash_f28335/.cproject new file mode 100644 index 0000000..5e27aba --- /dev/null +++ b/f2833x/examples/flash_f28335/.cproject @@ -0,0 +1,120 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/flash_f28335/.project b/f2833x/examples/flash_f28335/.project new file mode 100644 index 0000000..297b506 --- /dev/null +++ b/f2833x/examples/flash_f28335/.project @@ -0,0 +1,103 @@ + + + Example_28335_Flash + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CSMPasswords.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CSMPasswords.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_MemCopy.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_MemCopy.c + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + F28335.cmd + 1 + INSTALLROOT_2833X/common/cmd/F28335.cmd + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/flash_f28335/Example_2833xFlash.c b/f2833x/examples/flash_f28335/Example_2833xFlash.c new file mode 100644 index 0000000..bebe245 --- /dev/null +++ b/f2833x/examples/flash_f28335/Example_2833xFlash.c @@ -0,0 +1,426 @@ +//########################################################################### +// +// FILE: Example_2833xFlash.c +// +// TITLE: ePWM Timer Interrupt From Flash Example +// +//! \addtogroup f2833x_example_list +//!

ePWM Timer Interrupt From Flash (flash_f28335)

+//! +//! This example runs the ePWM interrupt example from flash. ePwm1 Interrupt +//! will run from RAM and puts the flash into sleep mode. ePwm2 Interrupt +//! will run from RAM and puts the flash into standby mode. ePWM3 Interrupt +//! will run from FLASH. All timers have the same period. The timers are +//! started sync'ed. An interrupt is taken on a zero event for each ePWM +//! timer.GPIO32 is toggled while in the background loop.\n +//! \b Note: \n +//! - ePWM1: takes an interrupt every event +//! - ePWM2: takes an interrupt every 2nd event +//! - ePWM3: takes an interrupt every 3rd event +//! +//! Thus the Interrupt count for ePWM1, ePWM4-ePWM6 should be equal +//! The interrupt count for ePWM2 should be about half that of ePWM1 +//! and the interrupt count for ePWM3 should be about 1/3 that of ePWM1 +//! +//! Follow these steps to run the program. +//! - Build the project +//! - Flash the .out file into the device. +//! - Set the hardware jumpers to boot to Flash +//! - Use the included GEL file to load the project, symbols +//! defined within the project and the variables into the watch +//! window. +//! +//! Steps that were taken to convert the ePWM example from RAM +//! to Flash execution: +//! - Change the linker cmd file to reflect the flash memory map. +//! - Make sure any initialized sections are mapped to Flash. +//! In SDFlash utility this can be checked by the View->Coff/Hex +//! status utility. Any section marked as "load" should be +//! allocated to Flash. +//! - Make sure there is a branch instruction from the entry to Flash +//! at 0x33FFF6 to the beginning of code execution. This example +//! uses the DSP2833x_CodeStartBranch.__asm file to accomplish this. +//! - Set boot mode Jumpers to "boot to Flash" +//! - For best performance from the flash, modify the waitstates +//! and enable the flash pipeline as shown in this example. +//! Note: any code that manipulates the flash waitstate and pipeline +//! control must be run from RAM. Thus these functions are located +//! in their own memory section called ramfuncs. +//! +//! \b Watch \b Variables \n +//! - EPwm1TimerIntCount +//! - EPwm2TimerIntCount +//! - EPwm3TimerIntCount +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include + +// +// Defines that configure which ePWM timer interrupts are enabled at +// the PIE level: 1 = enabled, 0 = disabled +// +#define PWM1_INT_ENABLE 1 +#define PWM2_INT_ENABLE 1 +#define PWM3_INT_ENABLE 1 + +// +// Defines for the period for each timer +// +#define PWM1_TIMER_TBPRD 0x1FFF +#define PWM2_TIMER_TBPRD 0x1FFF +#define PWM3_TIMER_TBPRD 0x1FFF + +// +// Make this long enough so that we can see an LED toggle +// +#define DELAY 1000000L + +// +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped using +// the linker cmd file. +// +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(epwm1_timer_isr, ".TI.ramfunc"); + #pragma CODE_SECTION(epwm2_timer_isr, ".TI.ramfunc"); + #else + #pragma CODE_SECTION(epwm1_timer_isr, "ramfuncs"); + #pragma CODE_SECTION(epwm2_timer_isr, "ramfuncs"); + #endif +#endif + + +// +// Function Prototypes +// +__interrupt void epwm1_timer_isr(void); +__interrupt void epwm2_timer_isr(void); +__interrupt void epwm3_timer_isr(void); +void InitEPwmTimer(void); + +// +// Globals +// +Uint32 EPwm1TimerIntCount; +Uint32 EPwm2TimerIntCount; +Uint32 EPwm3TimerIntCount; +Uint32 LoopCount; + +// +// These are defined by the linker (see F28335.cmd) +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + //InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.EPWM1_INT = &epwm1_timer_isr; + PieVectTable.EPWM2_INT = &epwm2_timer_isr; + PieVectTable.EPWM3_INT = &epwm3_timer_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + //InitPeripherals(); // Not required for this example + InitEPwmTimer(); // For this example, only initialize the ePWM Timers + + // + // Step 5. User specific code, enable interrupts + // + + // + // Copy time critical code and Flash setup code to RAM + // This includes the following ISR functions: epwm1_timer_isr(), + // epwm2_timer_isr(), epwm3_timer_isr and and InitFlash(); + // The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart + // symbols are created by the linker. Refer to the F28335.cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates + // This function must reside in RAM + // + InitFlash(); + + // + // Initialize counters + // + EPwm1TimerIntCount = 0; + EPwm2TimerIntCount = 0; + EPwm3TimerIntCount = 0; + LoopCount = 0; + + // + // Enable CPU INT3 which is connected to EPWM1-3 INT + // + IER |= M_INT3; + + // + // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + // + PieCtrlRegs.PIEIER3.bit.INTx1 = PWM1_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx2 = PWM2_INT_ENABLE; + PieCtrlRegs.PIEIER3.bit.INTx3 = PWM3_INT_ENABLE; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; + GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; + EDIS; + + for(;;) + { + // + // This loop will be interrupted, so the overall + // delay between pin toggles will be longer. + // + DELAY_US(DELAY); + LoopCount++; + GpioDataRegs.GPBTOGGLE.bit.GPIO32 = 1; + } +} + +// +// InitEPwmTimer - +// +void +InitEPwmTimer() +{ + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks + EDIS; + + // + // Setup Sync + // + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through + + // + // Allow each timer to be sync'ed + // + EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; + EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; + + EPwm1Regs.TBPHS.half.TBPHS = 100; + EPwm2Regs.TBPHS.half.TBPHS = 200; + EPwm3Regs.TBPHS.half.TBPHS = 300; + + EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD; + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event + EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // Enable INT + EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event + + + EPwm2Regs.TBPRD = PWM2_TIMER_TBPRD; + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm2Regs.ETSEL.bit.INTEN = PWM2_INT_ENABLE; // Enable INT + EPwm2Regs.ETPS.bit.INTPRD = ET_2ND; // Generate INT on 2nd event + + + EPwm3Regs.TBPRD = PWM3_TIMER_TBPRD; + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up + EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event + EPwm3Regs.ETSEL.bit.INTEN = PWM3_INT_ENABLE; // Enable INT + EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced + EDIS; +} + +// +// epwm1_timer_isr -This ISR MUST be executed from RAM as it will put the Flash +// into Sleep Interrupt routines uses in this example +// +__interrupt void +epwm1_timer_isr(void) +{ + // + // Put the Flash to sleep + // + EALLOW; + FlashRegs.FPWR.bit.PWR = FLASH_SLEEP; + EDIS; + EPwm1TimerIntCount++; + + // + // Clear INT flag for this timer + // + EPwm1Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm2_timer_isr - This ISR MUST be executed from RAM as it will put the +// Flash into Standby +// +__interrupt void +epwm2_timer_isr(void) +{ + EPwm2TimerIntCount++; + + // + // Put the Flash into standby + // + EALLOW; + FlashRegs.FPWR.bit.PWR = FLASH_STANDBY; + EDIS; + + // + // Clear INT flag for this timer + // + EPwm2Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// epwm3_timer_isr - +// +__interrupt void +epwm3_timer_isr(void) +{ + Uint16 i; + + EPwm3TimerIntCount++; + + // + // Short Delay to simulate some ISR Code + // + for(i = 1; i < 0x01FF; i++) + { + + } + + // + // Clear INT flag for this timer + // + EPwm3Regs.ETCLR.bit.INT = 1; + + // + // Acknowledge this interrupt to receive more interrupts from group 3 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +} + +// +// End of File +// + diff --git a/f2833x/examples/fpu_hardware/.ccsproject b/f2833x/examples/fpu_hardware/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/fpu_hardware/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/fpu_hardware/.cproject b/f2833x/examples/fpu_hardware/.cproject new file mode 100644 index 0000000..27099dc --- /dev/null +++ b/f2833x/examples/fpu_hardware/.cproject @@ -0,0 +1,120 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/fpu_hardware/.project b/f2833x/examples/fpu_hardware/.project new file mode 100644 index 0000000..a7c10f5 --- /dev/null +++ b/f2833x/examples/fpu_hardware/.project @@ -0,0 +1,98 @@ + + + Example_2833xFPU_hardware + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/fpu_hardware/Example_2833xFPU_hardware.c b/f2833x/examples/fpu_hardware/Example_2833xFPU_hardware.c new file mode 100644 index 0000000..998bf26 --- /dev/null +++ b/f2833x/examples/fpu_hardware/Example_2833xFPU_hardware.c @@ -0,0 +1,162 @@ +//########################################################################### +// +// FILE: Example_2833xFPU_hardware.c +// +// TITLE: Floating Point Unit Hardware Example +// +//! \addtogroup f2833x_example_list +//!

Floating Point Unit (fpu_hardware)

+//! +//! The code calculates two y=mx+b equations. The variables are all +//! 32-bit floating-point. +//! +//! The compiler will generate floating point instructions to do these +//! calculations. To compile the project for floating point, the following +//! Build Options were used: +//! -# Project->Properties-> C/C++ Build window-> Basic Settings-> +//! C2000 Compiler Vx.x \n +//! In All Options textbox: add "--float_support=fpu32" . \n +//! OR in Runtime Model Options, under "Specify floating point support +//! (--float_support) pull-down menu: Select "fpu32". +//! -# Project->Properties-> C/C++ Build window-> Basic Settings-> +//! C2000 Linker Vx.x-> File Search Path \n +//! In "Include linker file or command file as input (--library, -l)" +//! box, click green plus sign and add rts2800_fpu32.lib +//! (run-time support library). +//! -# Not included in this example: If the project includes any other +//! libraries, they must also be compiled with floating point instructions. +//! +//! \b Watch \b Variables \n +//! - y1 +//! - y2 +//! - FPU registers (optional) +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Globals +// +float y1, y2; +float m1, m2; +float x1, x2; +float b1, b2; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + + // + // Step 5. User specific code, enable interrupts + // + + // + // Calculate two y=mx+b equations. + // + y1 = 0; + y2 = 0; + m1 = .5; + m2 = .6; + x1 = 3.4; + x2 = 7.3; + b1 = 4.2; + b2 = 8.9; + + y1 = m1*x1 + b1; + y2 = m2*x2 + b2; + + ESTOP0; // This is a software breakpoint +} + +// +// End of File +// + diff --git a/f2833x/examples/fpu_software/.ccsproject b/f2833x/examples/fpu_software/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/fpu_software/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/fpu_software/.cproject b/f2833x/examples/fpu_software/.cproject new file mode 100644 index 0000000..0d4ff55 --- /dev/null +++ b/f2833x/examples/fpu_software/.cproject @@ -0,0 +1,120 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/fpu_software/.project b/f2833x/examples/fpu_software/.project new file mode 100644 index 0000000..b1fa95c --- /dev/null +++ b/f2833x/examples/fpu_software/.project @@ -0,0 +1,98 @@ + + + Example_2833xFPU_software + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/fpu_software/Example_2833xFPU_software.c b/f2833x/examples/fpu_software/Example_2833xFPU_software.c new file mode 100644 index 0000000..b67fdd9 --- /dev/null +++ b/f2833x/examples/fpu_software/Example_2833xFPU_software.c @@ -0,0 +1,164 @@ +//########################################################################### +// +// FILE: Example_2833xFPU_software.c +// +// TITLE: Floating Point Unit Software Example +// +//! \addtogroup f2833x_example_list +//!

Floating Point Unit (fpu_software)

+//! +//! The code calculates two y=mx+b equations. The variables are all +//! 32-bit floating-point. +//! +//! The compiler will only used fixed point instructions. This means the +//! runtime support library will be used to emulate floating point. +//! This will also run on C28x devices without the floating point unit. +//! To compile the project for fixed point, the following Build Options were +//! used: +//! -# Project->Properties-> C/C++ Build window-> Basic Settings-> +//! C2000 Compiler Vx.x \n +//! In All Options textbox: "--float_support=fpu32" is removed. \n +//! OR in Runtime Model Options, under "Specify floating point support +//! (--float_support) pull-down menu: Select "None". +//! -# Project->Properties-> C/C++ Build window-> Basic Settings-> +//! C2000 Linker Vx.x-> File Search Path \n +//! In "Include linker file or command file as input (--library, -l)" +//! box, click green plus sign and add rts2800.lib or rts2800_ml.lib +//! (run-time support library). +//! -# Not included in this example: If the project includes any other +//! libraries, they must also be compiled with fixed point instructions. +//! +//! \b Watch \b Variables \n +//! - y1 +//! - y2 +//! - FPU registers (optional) +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Globals +// +float y1, y2; +float m1, m2; +float x1, x2; +float b1, b2; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + + // + // Step 5. User specific code, enable interrupts + // + + // + // Calculate two y=mx+b equations. + // + y1 = 0; + y2 = 0; + m1 = .5; + m2 = .6; + x1 = 3.4; + x2 = 7.3; + b1 = 4.2; + b2 = 8.9; + + y1 = m1*x1 + b1; + y2 = m2*x2 + b2; + + ESTOP0; // This is a software breakpoint +} + +// +// End of File +// + diff --git a/f2833x/examples/gpio_setup/.ccsproject b/f2833x/examples/gpio_setup/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/gpio_setup/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/gpio_setup/.cproject b/f2833x/examples/gpio_setup/.cproject new file mode 100644 index 0000000..301507f --- /dev/null +++ b/f2833x/examples/gpio_setup/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/gpio_setup/.project b/f2833x/examples/gpio_setup/.project new file mode 100644 index 0000000..54c82c2 --- /dev/null +++ b/f2833x/examples/gpio_setup/.project @@ -0,0 +1,93 @@ + + + Example_2833xGpioSetup + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/gpio_setup/Example_2833xGpioSetup.c b/f2833x/examples/gpio_setup/Example_2833xGpioSetup.c new file mode 100644 index 0000000..4ac5407 --- /dev/null +++ b/f2833x/examples/gpio_setup/Example_2833xGpioSetup.c @@ -0,0 +1,549 @@ +//########################################################################### +// +// FILE: Example_2833xGpioSetup.c +// +// TITLE: GPIO Setup Example +// +//! \addtogroup f2833x_example_list +//!

GPIO Setup (gpio_setup)

+//! +//! This example Configures the 2833x GPIO into two different configurations +//! This code is verbose to illustrate how the GPIO could be setup.In a real +//! application, lines of code can be combined for improved code size and +//! efficiency. +//! +//! This example only sets-up the GPIO and nothing is actually done with +//! the pins after setup. +//! +//! In general: +//! - All pullup resistors are enabled. For ePWMs this may not be desired. +//! - Input qual for communication ports (eCAN, SPI, SCI, I2C) is +//! asynchronous +//! - Input qual for Trip pins (TZ) is asynchronous +//! - Input qual for eCAP and eQEP signals is synch to SYSCLKOUT +//! - Input qual for some I/O's and interrupts may have a sampling window +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines that select the example to compile in. Only one example should +// be set as 1 the rest should be set as 0. +// +#define EXAMPLE1 1 // Basic pinout configuration example +#define EXAMPLE2 0 // Communication pinout example + +// +// Function Prototypes +// +void Gpio_setup1(void); +void Gpio_setup2(void); + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code + // + +#if EXAMPLE1 + // + // This example is a basic pinout + // + Gpio_setup1(); + +#endif // - EXAMPLE1 + +#if EXAMPLE2 + // + // This example is a communications pinout + // + Gpio_setup2(); + +#endif +} + +// +// Gpio_setup1 - Example 1: Basic Pinout. +// +void Gpio_setup1(void) +{ + // + // This basic pinout includes: + // PWM1-3, ECAP1, ECAP2, TZ1-TZ4, SPI-A, EQEP1, SCI-A, I2C + // and a number of I/O pins + // + + // + // These can be combined into single statements for improved + // code efficiency. + // + + // + // Enable PWM1-3 on GPIO0-GPIO5 + // + EALLOW; + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0 + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1 + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pullup on GPIO2 + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pullup on GPIO3 + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4 + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO5 + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = PWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = PWM2B + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = PWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = PWM3B + + // + // Enable an GPIO output on GPIO6, set it high + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6 + GpioDataRegs.GPASET.bit.GPIO6 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6 = GPIO6 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO6 = output + + // + // Enable eCAP1 on GPIO7 + // + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pullup on GPIO7 + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLOUT + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // GPIO7 = ECAP2 + + // + // Enable GPIO outputs on GPIO8 - GPIO11, set it high + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8 + GpioDataRegs.GPASET.bit.GPIO8 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8 = GPIO8 + GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // GPIO8 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pullup on GPIO9 + GpioDataRegs.GPASET.bit.GPIO9 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // GPIO9 = GPIO9 + GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // GPIO9 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pullup on GPIO10 + GpioDataRegs.GPASET.bit.GPIO10 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; // GPIO10 = GPIO10 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO10 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pullup on GPIO11 + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // GPIO11 = GPIO11 + GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // GPIO11 = output + + // + // Enable Trip Zone inputs on GPIO12 - GPIO15 + // + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12 + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pullup on GPIO13 + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pullup on GPIO14 + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pullup on GPIO15 + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // asynch input + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // GPIO12 = TZ1 + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // GPIO13 = TZ2 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // GPIO14 = TZ3 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // GPIO15 = TZ4 + + // + // Enable SPI-A on GPIO16 - GPIO19 + // + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16 + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17 + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18 + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19 + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // GPIO16 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // GPIO17 = SPIS0MIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // GPIO18 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // GPIO19 = SPISTEA + + // + // Enable EQEP1 on GPIO20 - GPIO23 + // + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pullup on GPIO20 + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pullup on GPIO21 + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22 + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23 + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // GPIO20 = EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // GPIO21 = EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // GPIO22 = EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // GPIO23 = EQEP1I + + // + // Enable eCAP1 on GPIO24 + // + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO24 + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // GPIO24 = ECAP1 + + // + // Set input qualifcation period for GPIO25 & GPIO26 + // + GpioCtrlRegs.GPACTRL.bit.QUALPRD3=1; // Qual period = SYSCLKOUT/2 + GpioCtrlRegs.GPAQSEL2.bit.GPIO25=2; // 6 samples + GpioCtrlRegs.GPAQSEL2.bit.GPIO26=2; // 6 samples + + // + // Make GPIO25 the input source for Xint1 + // + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // GPIO25 = GPIO25 + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; // GPIO25 = input + GpioIntRegs.GPIOXINT1SEL.all = 25; // Xint1 connected to GPIO25 + + // + // Make GPIO26 the input source for XINT2 + // + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // GPIO26 = GPIO26 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 0; // GPIO26 = input + GpioIntRegs.GPIOXINT2SEL.all = 26; // XINT2 connected to GPIO26 + + // + // Make GPIO27 wakeup from HALT/STANDBY Low Power Modes + // + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = GPIO27 + GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; // GPIO27 = input + GpioIntRegs.GPIOLPMSEL.bit.GPIO27=1; // GPIO27 will wake the device + + // + // Qualify GPIO27 by 2 OSCCLK cycles before waking the device + // from STANDBY + // + SysCtrlRegs.LPMCR0.bit.QUALSTDBY=2; + + // + // Enable SCI-A on GPIO28 - GPIO29 + // + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28 + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // GPIO28 = SCIRXDA + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // GPIO29 = SCITXDA + + // + // Enable CAN-A on GPIO30 - GPIO31 + // + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GPIO30 = CANTXA + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31 + GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // Asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GPIO31 = CANRXA + + // + // Enable I2C-A on GPIO32 - GPIO33 + // + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO32 + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // GPIO32 = SDAA + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33 + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // GPIO33 = SCLA + + // + // Make GPIO34 an input + // + GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pullup on GPIO34 + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = GPIO34 + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = input + EDIS; +} + +// +// Gpio_setup2 - Example 1: Communications Pinout +// +void +Gpio_setup2(void) +{ + // + // This basic communications pinout includes: + // PWM1-3, CAP1, CAP2, SPI-A, SPI-B, CAN-A, SCI-A and I2C + // and a number of I/O pins + // + + // + // Enable PWM1-3 on GPIO0-GPIO5 + // + EALLOW; + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0 + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1 + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pullup on GPIO2 + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pullup on GPIO3 + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4 + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO5 + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = PWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = PWM2B + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = PWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = PWM3B + + // + // Enable an GPIO output on GPIO6 + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6 + GpioDataRegs.GPASET.bit.GPIO6 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6 = GPIO6 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO6 = output + + // + // Enable eCAP1 on GPIO7 + // + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pullup on GPIO7 + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // GPIO7 = ECAP2 + + // + // Enable GPIO outputs on GPIO8 - GPIO11 + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8 + GpioDataRegs.GPASET.bit.GPIO8 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8 = GPIO8 + GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // GPIO8 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pullup on GPIO9 + GpioDataRegs.GPASET.bit.GPIO9 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // GPIO9 = GPIO9 + GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // GPIO9 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pullup on GPIO10 + GpioDataRegs.GPASET.bit.GPIO10 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; // GPIO10 = GPIO10 + GpioCtrlRegs.GPADIR.bit.GPIO10 = 1; // GPIO10 = output + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pullup on GPIO11 + GpioDataRegs.GPASET.bit.GPIO11 = 1; // Load output latch + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // GPIO11 = GPIO11 + GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // GPIO11 = output + + // + // Enable SPI-B on GPIO12 - GPIO15 + // + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12 (SPISIMOB) + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO13 (SPISOMIB) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pullup on GPIO14 (SPICLKB) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pullup on GPIO15 (SPISTEB) + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // asynch input + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // asynch input + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 = SPISIMOB + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 = SPISOMIB + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 = SPICLKB + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 = SPISTEB + + // + // Enable SPI-A on GPIO16 - GPIO19 + // + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17 (SPIS0MIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19 (SPISTEA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // GPIO16 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // GPIO17 = SPIS0MIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // GPIO18 = SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // GPIO19 = SPISTEA + + // + // Enable EQEP1 on GPIO20 - GPIO23 + // + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pullup on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pullup on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23 (EQEP1I) + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // GPIO20 = EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // GPIO21 = EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // GPIO22 = EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // GPIO23 = EQEP1I + + // + // Enable eCAP1 on GPIO24 + // + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO24 (ECAP1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // GPIO24 = ECAP1 + + // + // Set input qualification period for GPIO25 & GPIO26 inputs + // + GpioCtrlRegs.GPACTRL.bit.QUALPRD3=1; // Qual period = SYSCLKOUT/2 + GpioCtrlRegs.GPAQSEL2.bit.GPIO25=2; // 6 samples + GpioCtrlRegs.GPAQSEL2.bit.GPIO26=1; // 3 samples + + // + // Make GPIO25 the input source for Xint1 + // + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // GPIO25 = GPIO25 + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; // GPIO25 = input + GpioIntRegs.GPIOXINT1SEL.all = 25; // Xint1 connected to GPIO25 + + // + // Make GPIO26 the input source for XINT2 + // + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // GPIO26 = GPIO26 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 0; // GPIO26 = input + GpioIntRegs.GPIOXINT2SEL.all = 26; // XINT2 connected to GPIO26 + + // + // Make GPIO27 wakeup from HALT/STANDBY Low Power Modes + // + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = GPIO27 + GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; // GPIO27 = input + GpioIntRegs.GPIOLPMSEL.bit.GPIO27=1; // GPIO27 will wake the device + + // + // Qualify GPIO27 by 2 OSCCLK cycles before waking the device + // from STANDBY + // + SysCtrlRegs.LPMCR0.bit.QUALSTDBY=2; + + // + // Enable SCI-A on GPIO28 - GPIO29 + // + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28 + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // GPIO28 = SCIRXDA + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // GPIO29 = SCITXDA + + // + // Enable CAN-A on GPIO30 - GPIO31 + // + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GPIO30 = CANTXA + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31 + GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GPIO31 = CANRXA + + // + // Enable I2C-A on GPIO32 - GPIO33 + // + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO32 + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33 + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // GPIO32 = SDAA + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // GPIO33 = SCLA + + // + // Make GPIO34 an input + // + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO34 + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = GPIO34 + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = input + + EDIS; +} + +// +// End of File +// + diff --git a/f2833x/examples/gpio_toggle/.ccsproject b/f2833x/examples/gpio_toggle/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/gpio_toggle/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/gpio_toggle/.cproject b/f2833x/examples/gpio_toggle/.cproject new file mode 100644 index 0000000..75a176b --- /dev/null +++ b/f2833x/examples/gpio_toggle/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/gpio_toggle/.project b/f2833x/examples/gpio_toggle/.project new file mode 100644 index 0000000..3347577 --- /dev/null +++ b/f2833x/examples/gpio_toggle/.project @@ -0,0 +1,93 @@ + + + Example_2833xGpioToggle + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/gpio_toggle/.settings/org.eclipse.cdt.codan.core.prefs b/f2833x/examples/gpio_toggle/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/f2833x/examples/gpio_toggle/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/f2833x/examples/gpio_toggle/.settings/org.eclipse.cdt.debug.core.prefs b/f2833x/examples/gpio_toggle/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000..2adc7b1 --- /dev/null +++ b/f2833x/examples/gpio_toggle/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/f2833x/examples/gpio_toggle/Example_2833xGpioToggle.c b/f2833x/examples/gpio_toggle/Example_2833xGpioToggle.c new file mode 100644 index 0000000..713e477 --- /dev/null +++ b/f2833x/examples/gpio_toggle/Example_2833xGpioToggle.c @@ -0,0 +1,283 @@ +//########################################################################### +// +// FILE: Example_2833xGpioToggle.c +// +// TITLE: GPIO Toggle Example +// +//! \addtogroup f2833x_example_list +//! +//!

GPIO Toggle (gpio_toggle)

+//! +//! \note ALL OF THE I/O'S TOGGLE IN THIS PROGRAM. MAKE SURE +//! THIS WILL NOT DAMAGE YOUR HARDWARE BEFORE RUNNING THIS +//! EXAMPLE. +//! +//! Three different examples are included. Select the example +//! (data, set/clear or toggle) to execute before compiling using +//! the macros found at the top of the code. +//! +//! Each example toggles all the GPIOs in a different way, the first +//! through writing values to the GPIO DATA registers, the second through +//! the SET/CLEAR registers and finally the last through the TOGGLE register +//! +//! The pins can be observed using Oscilloscope. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines that select the example to compile in. +// Only one example should be set as 1 the rest should be set as 0. +// +#define EXAMPLE1 1 // Use DATA registers to toggle I/O's +#define EXAMPLE2 0 // Use SET/CLEAR registers to toggle I/O's +#define EXAMPLE3 0 // Use TOGGLE registers to toggle I/O's + +// +// Function Prototypes +// +void delay_loop(void); +void Gpio_select(void); +void Gpio_example1(void); +void Gpio_example2(void); +void Gpio_example3(void); + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this example use the following configuration + // + Gpio_select(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code: + // +#if EXAMPLE1 + // + // This example uses DATA registers to toggle I/O's + // + Gpio_example1(); +#endif // - EXAMPLE1 + +#if EXAMPLE2 + // + // This example uses SET/CLEAR registers to toggle I/O's + // + Gpio_example2(); +#endif + +#if EXAMPLE3 + // + // This example uses TOGGLE registers to toggle I/O's + // + Gpio_example3(); +#endif +} + +// +// delay_loop - +// +void +delay_loop() +{ + volatile long i; + for (i = 0; i < 1000000; i++) + { + + } +} + +// +// Gpio_example1 - +// +void +Gpio_example1(void) +{ + // + // Example 1: Toggle I/Os using DATA registers + // + for(;;) + { + GpioDataRegs.GPADAT.all =0xAAAAAAAA; + GpioDataRegs.GPBDAT.all =0x0000000A; + + delay_loop(); + + GpioDataRegs.GPADAT.all =0x55555555; + GpioDataRegs.GPBDAT.all =0x00000005; + + delay_loop(); + } +} + +// +// Gpio_example2 - +// +void +Gpio_example2(void) +{ + // + // Example 2: Toggle I/Os using SET/CLEAR registers + // + for(;;) + { + GpioDataRegs.GPASET.all =0xAAAAAAAA; + GpioDataRegs.GPACLEAR.all =0x55555555; + + GpioDataRegs.GPBSET.all =0x0000000A; + GpioDataRegs.GPBCLEAR.all =0x00000005; + + delay_loop(); + + GpioDataRegs.GPACLEAR.all =0xAAAAAAAA; + GpioDataRegs.GPASET.all =0x55555555; + + GpioDataRegs.GPBCLEAR.all =0x0000000A; + GpioDataRegs.GPBSET.all =0x00000005; + + delay_loop(); + } +} + +// +// Gpio_example3 - +// +void +Gpio_example3(void) +{ + // + // Example 2: Toggle I/Os using TOGGLE registers + // + + // + // Set pins to a known state + // + GpioDataRegs.GPASET.all =0xAAAAAAAA; + GpioDataRegs.GPACLEAR.all =0x55555555; + + GpioDataRegs.GPBSET.all =0x0000000A; + GpioDataRegs.GPBCLEAR.all =0x00000005; + + // + // Use TOGGLE registers to flip the state of the pins. + // Any bit set to a 1 will flip state (toggle) + // Any bit set to a 0 will not toggle. + // + for(;;) + { + GpioDataRegs.GPATOGGLE.all =0xFFFFFFFF; + GpioDataRegs.GPBTOGGLE.all =0x0000000F; + delay_loop(); + } +} + +// +// Gpio_select - +// +void +Gpio_select(void) +{ + EALLOW; + GpioCtrlRegs.GPAMUX1.all = 0x00000000; // All GPIO + GpioCtrlRegs.GPAMUX2.all = 0x00000000; // All GPIO + GpioCtrlRegs.GPAMUX1.all = 0x00000000; // All GPIO + GpioCtrlRegs.GPADIR.all = 0xFFFFFFFF; // All outputs + GpioCtrlRegs.GPBDIR.all = 0x0000000F; // All outputs + EDIS; +} + +// +// End of File +// + diff --git a/f2833x/examples/hrpwm/.ccsproject b/f2833x/examples/hrpwm/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/hrpwm/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/hrpwm/.cproject b/f2833x/examples/hrpwm/.cproject new file mode 100644 index 0000000..7d1a753 --- /dev/null +++ b/f2833x/examples/hrpwm/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/hrpwm/.project b/f2833x/examples/hrpwm/.project new file mode 100644 index 0000000..885065a --- /dev/null +++ b/f2833x/examples/hrpwm/.project @@ -0,0 +1,98 @@ + + + Example_2833xHRPWM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/hrpwm/Example_2833xHRPWM.c b/f2833x/examples/hrpwm/Example_2833xHRPWM.c new file mode 100644 index 0000000..1672e49 --- /dev/null +++ b/f2833x/examples/hrpwm/Example_2833xHRPWM.c @@ -0,0 +1,434 @@ +//########################################################################### +// +// FILE: Example_2833xHRPWM.c +// +// TITLE: High Resolution PWM Example +// +//! \addtogroup f2833x_example_list +//!

High Resolution PWM (hrpwm)

+//! +//! This example modifies the MEP control registers to show edge displacement +//! due to the HRPWM control extension of the respective EPwm module +//! All EPwm1A,2A,3A,4A channels (GPIO0, GPIO2, GPIO4, GPIO6) will have fine +//! edge movement due to HRPWM logic +//! +//! -# 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),\n +//! ePWM1A toggle low/high with MEP control on rising edge \n +//! ePWM1B toggle low/high with NO HRPWM control +//! -# 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),\n +//! ePWM2A toggle low/high with MEP control on rising edge \n +//! ePWM2B toggle low/high with NO HRPWM control +//! -# 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),\n +//! ePWM3A toggle as high/low with MEP control on falling edge \n +//! ePWM3B toggle low/high with NO HRPWM control +//! -# 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),\n +//! ePWM4A toggle as high/low with MEP control on falling edge \n +//! ePWM4B toggle low/high with NO HRPWM control +//! +//! \b External \b Connections \n +//! Monitor ePWM1-ePWM4 pins on an oscilloscope as described +//! below: +//! - ePWM1A is on GPIO0 +//! - ePWM1B is on GPIO1 +//! - ePWM2A is on GPIO2 +//! - ePWM2B is on GPIO3 +//! - ePWM3A is on GPIO4 +//! - ePWM3B is on GPIO5 +//! - ePWM4A is on GPIO6 +//! - ePWM4B is on GPIO7 +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization + +// +// Function prototypes +// +void HRPWM1_Config(int); +void HRPWM2_Config(int); +void HRPWM3_Config(int); +void HRPWM4_Config(int); + +// +// General System nets - Useful for debug +// +Uint16 i,j, DutyFine, n,update; + +Uint32 temp; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + // In this case, just init GPIO for ePWM1-ePWM4 + + // + // For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4 + // These functions are in the DSP2833x_EPwm.c file + // + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // For this example, only initialize the ePWM + // Step 5. User specific code, enable interrupts + // + update =1; + DutyFine =0; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + // + // Some useful Period vs Frequency values + // SYSCLKOUT = 150MHz 100 MHz + // ----------------------------------------- + // Period Frequency Frequency + // 1000 150 kHz 100 KHz + // 800 187 kHz 125 KHz + // 600 250 kHz 167 KHz + // 500 300 kHz 200 KHz + // 250 600 kHz 400 KHz + // 200 750 kHz 500 KHz + // 100 1.5 MHz 1.0 MHz + // 50 3.0 MHz 2.0 MHz + // 25 6.0 MHz 4.0 MHz + // 20 7.5 MHz 5.0 MHz + // 12 12.5 MHz 8.33 MHz + // 10 15.0 MHz 10.0 MHz + // 9 16.7 MHz 11.1 MHz + // 8 18.8 MHz 12.5 MHz + // 7 21.4 MHz 14.3 MHz + // 6 25.0 MHz 16.7 MHz + // 5 30.0 MHz 20.0 MHz + // + + // + // ePWM and HRPWM register initialization + // + + // + // ePWM1 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + // + HRPWM1_Config(10); + + // + // ePWM2 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + // + HRPWM2_Config(20); + + // + // ePWM3 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + // + HRPWM3_Config(10); + + // + // ePWM4 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + // + HRPWM4_Config(20); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + while (update ==1) + { + for(DutyFine =1; DutyFine <256 ;DutyFine ++) + { + // + // Example, write to the HRPWM extension of CMPA + // + + // + // Left shift by 8 to write into MSB bits + // + EPwm1Regs.CMPA.half.CMPAHR = DutyFine << 8; + + // + // Left shift by 8 to write into MSB bits + // + EPwm2Regs.CMPA.half.CMPAHR = DutyFine << 8; + + // + // Example, 32-bit write to CMPA:CMPAHR + // + EPwm3Regs.CMPA.all = ((Uint32)EPwm3Regs.CMPA.half.CMPA << 16) + + (DutyFine << 8); + EPwm4Regs.CMPA.all = ((Uint32)EPwm4Regs.CMPA.half.CMPA << 16) + + (DutyFine << 8); + + // + // Dummy delay between MEP changes + // + for (i=0;i<10000;i++) + { + + } + } + } +} + +// +// HRPWM1_Config - +// +void +HRPWM1_Config(period) +{ + // + // ePWM1 register configuration with HRPWM + // ePWM1A toggle low/high with MEP control on Rising edge + // + EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.CMPB = period / 2; // set duty 50% initially + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; // MEP control on Rising edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// +// HRPWM2_Config - +// +void +HRPWM2_Config(period) +{ + // + // ePWM2 register configuration with HRPWM + // ePWM2A toggle low/high with MEP control on Rising edge + // + EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm2Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm2Regs.CMPB = period / 2; // set duty 50% initially + EPwm2Regs.TBPHS.all = 0; + EPwm2Regs.TBCTR = 0; + + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm2Regs.HRCNFG.all = 0x0; + EPwm2Regs.HRCNFG.bit.EDGMODE = HR_REP; // MEP control on Rising edge + EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + + EDIS; +} + +// +// HRPWM3_Config - +// +void +HRPWM3_Config(period) +{ + // + // ePWM3 register configuration with HRPWM + // ePWM3A toggle high/low with MEP control on falling edge + // + EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm3Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm3Regs.CMPB = period / 2; // set duty 50% initially + EPwm3Regs.TBPHS.all = 0; + EPwm3Regs.TBCTR = 0; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm3Regs.HRCNFG.all = 0x0; + EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// +// HRPWM4_Config - +// +void +HRPWM4_Config(period) +{ + // + // ePWM4 register configuration with HRPWM + // ePWM4A toggle high/low with MEP control on falling edge + // + EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm4Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm4Regs.CMPB = period / 2; // set duty 50% initially + EPwm4Regs.TBPHS.all = 0; + EPwm4Regs.TBCTR = 0; + + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm4Regs.HRCNFG.all = 0x0; + EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// +// End of File +// + diff --git a/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/.ccsproject b/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/.cproject b/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/.cproject new file mode 100644 index 0000000..6f1de26 --- /dev/null +++ b/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/.cproject @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/.project b/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/.project new file mode 100644 index 0000000..698e76b --- /dev/null +++ b/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/.project @@ -0,0 +1,107 @@ + + + Example_2833xHRPWM_Symmetric_Duty_Cycle_SFO_V5 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + SFO_TI_Build_V5B_fpu.lib + 1 + INSTALLROOT_HRPWM/lib/SFO_TI_Build_V5B_fpu.lib + + + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_HRPWM + $%7BPARENT-4-PROJECT_LOC%7D/libraries/calibration/hrpwm/f2833x + + + diff --git a/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/Example_2833xHRPWM_Symmetric_Duty_Cycle_SFO_V5.c b/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/Example_2833xHRPWM_Symmetric_Duty_Cycle_SFO_V5.c new file mode 100644 index 0000000..ecb787f --- /dev/null +++ b/f2833x/examples/hrpwm_Symmetric_Duty_cycle_sfo_v5/Example_2833xHRPWM_Symmetric_Duty_Cycle_SFO_V5.c @@ -0,0 +1,462 @@ +//########################################################################### +// +// FILE: Example_2833xHRPWM_Symmetric_Duty_Cycle_SFO_V5.c +// +// TITLE: High Resolution PWM Symmetric Duty Cycle SFO V5 Example +// +//! \addtogroup f2833x_example_list +//!

High Resolution PWM Symmetric Duty Cycle SFO V5

+//! +//! This example modifies the MEP control registers to show symmetric edge +//! displacement due to the HRPWM control extension of the respective ePWM +//! module. +//! +//! \note By default, this example project is configured for floating-point +//! math. All included libraries must be pre-compiled for floating-point math. +//! Therefore, SFO_TI_Build_V5B_fpu.lib (compiled for floating-point) is +//! included in the project instead of the SFO_TI_Build_V5B.lib +//! (compiled for fixed-point). +//! To convert the example for fixed-point math, follow the instructions in +//! sfo_readme.txt in the /doc directory of the header files and peripheral +//! examples package. +//! +//! \note This program requires the DSP2833x header files, which include +//! the following files required for this example: +//! SFO_V5.h and SFO_TI_Build_V5B_fpu.lib (or SFO_TI_Build_V5B.lib for +//! fixed point) +//! +//! This example calls the following TI's MEP Scale Factor Optimizer (SFO) +//! software library V5 functions: +//! +//! - \b int \b SFO_MepDis_V5(int i); updates MEP_ScaleFactor[i] when HRPWM +//! is not used +//! - \b Returns +//! - 1 when complete for the specified channel +//! - 0 if not complete for the specified channel +//! +//! +//! Channel ePWM1A will have fine edge movement due to the HRPWM logic when the +//! duty cycle is altered. \n +//! Channel ePWM1B has a fixed 50% duty cycle. +//! +//! - 5MHz PWM (for 150 MHz SYSCLKOUT), ePWM1A toggle high/low with MEP control +//! on rising edge +//! - 3.33MHz PWM (for 100 MHz SYSCLKOUT), ePWM1A toggle high/low with MEP +//! control on rising edge +//! +//! \b Running \b the \b Application \n +//! -# \b **!!IMPORTANT!!** - in SFO_V5.h, set PWM_CH to the max number of +//! HRPWM channels plus one. For example, for the F28335, the +//! maximum number of HRPWM channels is 6. 6+1=7, so set +//! \#define PWM_CH 7 in SFO_V5.h. (Default is 7) +//! -# Run this example at 150/100MHz SYSCLKOUT +//! -# Watch ePWM1 waveforms on a Oscilloscope +//! +//! \b External \b Connections \n +//! Monitor the following pins on an oscilloscope: +//! - ePWM1A is on GPIO0 +//! - ePWM1B is on GPIO1 +//! +//! \b Watch \b Variables \n +//! - MEP_ScaleFactor +//! - EPwm1Regs.CMPA.all +//! - EPwm1Regs.CMPB.all +//! +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization + +// +// SFO V5 library headerfile - required to use SFO library functions +// +#include "SFO_V5.h" + +// +// !!IMPORTANT!! +// UPDATE NUMBER OF HRPWM CHANNELS + 1 USED IN SFO_V5.H +// i.e. #define PWM_CH // F28335 has a maximum of 6 HRPWM channels (7=6+1) +// + +// +// Function Prototypes +// +void HRPWM_Config(int); +void error (void); +__interrupt void FreqCtlISR(void); // frequency modulation & phase sync ISR + +// +// General System variables - useful for debug +// +Uint16 status; +Uint16 CMP_Reg = 20; +Uint16 CMP_HR = 0; +Uint16 PRD_Reg = 40; +Uint16 PRD_HR = 0; +Uint16 update = 0; +Uint16 isr_cnt = 0; +Uint16 change_dir = 1; +Uint16 update_rate = 10000; +Uint16 CMP_Inc = 0; +Uint16 CMP_HR_INC = 0; +Uint32 InputCMPInc = 2621; +int32 CMP_HR_temp = 0; +Uint16 Period = 50; +int16 CMPA_reg_val=0; +int16 CMPAHR_reg_val=0; + +// +// The following declarations are required in order to use the SFO +// library functions: +// + +// +// Global array used by the SFO library +// For n HRPWM channels + 1 for MEP_ScaleFactor[0] +// +int MEP_ScaleFactor[PWM_CH]; + +// +// Array of pointers to EPwm register structures: +// *ePWM[0] is defined as dummy value not used in the example +// +volatile struct EPWM_REGS *ePWM[PWM_CH] = + { &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, + &EPwm4Regs, &EPwm5Regs, &EPwm6Regs}; + +// +// Main +// +void main(void) +{ + int i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this case just init GPIO pins for ePWM1-ePWM6 + // This function is in the DSP2833x_EPwm.c file + // + InitEPwmGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + EALLOW; + PieVectTable.EPWM1_INT = &FreqCtlISR; + EDIS; + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + // + // MEP_ScaleFactor variables initialization for SFO library functions + // + for(i=0;i= update_rate) + { + if (CMP_Reg < (PRD_Reg-4) && change_dir == 1) // Increment CMP + { + CMP_Inc = InputCMPInc >> 16; + CMP_HR_INC = (Uint16) InputCMPInc; + CMP_Reg = CMP_Reg+CMP_Inc; + CMP_HR_temp = (Uint32)CMP_HR + (Uint32)CMP_HR_INC; + + if(CMP_HR_temp>=0x10000) + { + CMP_HR_temp = CMP_HR_temp-0x10000; + CMP_Reg = CMP_Reg+1; + } + + CMP_HR = (Uint16) CMP_HR_temp; + } + + else + { + change_dir = 0; // Decrement CMP + } + + if (CMP_Reg > 4 && change_dir == 0) // Decrement CMP + { + CMP_Inc = InputCMPInc >> 16; + CMP_HR_INC = (Uint16) InputCMPInc; + CMP_Reg = CMP_Reg-CMP_Inc; + CMP_HR_temp = (int32)CMP_HR - (int32)CMP_HR_INC; + + if(CMP_HR_temp < 0) + { + CMP_HR_temp = 0x10000 + CMP_HR_temp; + CMP_Reg = CMP_Reg-1; + } + CMP_HR = (Uint16) CMP_HR_temp; + } + + else + { + change_dir = 1; // Increment CMP + } + update = 1; + isr_cnt = 0; + } + } +} + +// +// HRPWM_Config - Configures all ePWM channels and sets up HRPWM on ePWMxA +// channels +// +void +HRPWM_Config(period) +{ + EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; + EPwm1Regs.TBPRD = period; // PWM frequency = 1 / (2*TBPRD) + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down count mode + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.FREE_SOFT = 0x3; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // PWM toggle high/low + EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR; + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on falling edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = 0x2; + EDIS; +} + +// +// FreqCtlISR - interrupts at ePWM1 TBCTR = 0. This ISR updates the compare and +// period registers for ePWM modules within the same period. +// +__interrupt void +FreqCtlISR(void) +{ + EALLOW; + EPwm2Regs.TBCTL.bit.PHSEN = 0; + EDIS; + + isr_cnt++; + + if (update == 1) + { + EPwm1Regs.CMPA.half.CMPA = CMP_Reg; + CMPAHR_reg_val = (CMP_HR*MEP_ScaleFactor[1])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + EPwm1Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + update = 0; + } + + // + // re-initialise for next PWM interrupt + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // acknowledge PIE interrupt + EPwm1Regs.ETCLR.bit.INT = 1; // clear interrupt bit +} + +// +// error - An error occurs when the MEP_ScaleFactor [n] calculated from +// SFO_MEPEn_V5 differs by > +/- 15 from the Seed Value in MEP_ScaleFactor[0]. +// SFO_MepEn_V5 returned a "2" (SFO_OUTRANGE_ERROR). The user should: +// (1) Re-run SFO_MepDis_V5 to re-calibrate an appropriate seed value. +// (2) Ensure the code is not calling Mep_En_V5 on a different channel when it +// is currently still running on a channel. (Repetitively call Mep_En_V5 on +// current channel until an SFO_COMPLETE ( i.e. 1) is returned. +// (3) If the out-of-range condition is acceptable for the application, ignore +// the "2" and treat it as a "1" or SFO_COMPLETE. +// +void +error (void) +{ + // + // Error - MEP_ScaleFactor out of range of Seed - rerun MepDis calibration. + // + ESTOP0; +} + +// +// End of File +// + diff --git a/f2833x/examples/hrpwm_sfo/.ccsproject b/f2833x/examples/hrpwm_sfo/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/hrpwm_sfo/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/hrpwm_sfo/.cproject b/f2833x/examples/hrpwm_sfo/.cproject new file mode 100644 index 0000000..f259da7 --- /dev/null +++ b/f2833x/examples/hrpwm_sfo/.cproject @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/hrpwm_sfo/.project b/f2833x/examples/hrpwm_sfo/.project new file mode 100644 index 0000000..b8be609 --- /dev/null +++ b/f2833x/examples/hrpwm_sfo/.project @@ -0,0 +1,107 @@ + + + Example_2833xHRPWM_SFO + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + SFO_TI_Build_fpu.lib + 1 + INSTALLROOT_HRPWM/lib/SFO_TI_Build_fpu.lib + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_HRPWM + $%7BPARENT-4-PROJECT_LOC%7D/libraries/calibration/hrpwm/f2833x + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/hrpwm_sfo/Example_2833xHRPWM_SFO.c b/f2833x/examples/hrpwm_sfo/Example_2833xHRPWM_SFO.c new file mode 100644 index 0000000..521292f --- /dev/null +++ b/f2833x/examples/hrpwm_sfo/Example_2833xHRPWM_SFO.c @@ -0,0 +1,643 @@ +//########################################################################### +// +// FILE: Example_2833xHRPWM_SFO.c +// +// TITLE: High Resolution PWM SFO Example +// +//! \addtogroup f2833x_example_list +//!

High Resolution PWM SFO

+//! +//! This example modifies the MEP control registers to show edge displacement +//! due to the HRPWM control extension of the respective ePWM module. +//! +//! \note By default, this example project is configured for floating-point +//! math. All included libraries must be pre-compiled for floating-point math. +//! Therefore, SFO_TI_Build_fpu.lib (compiled for floating-point) is included +//! in the project instead of the SFO_TI_Build.lib (compiled for fixed-point). +//! To convert the example for fixed-point math, follow the instructions in +//! sfo_readme.txt in the /doc directory of the header files and peripheral +//! examples package. +//! +//! This example calls the following TI's MEP Scale Factor Optimizer (SFO) +//! software library functions: +//! +//! - \b void \b SFO_MepEn(int i); initialize MEP_Scalefactor[i] dynamically +//! when HRPWM is in use. +//! +//! - \b void \b SFO_MepDis(int i); initialize MEP_Scalefactor[i] when HRPWM +//! is not used +//! +//! Where MEP_ScaleFactor[5] is a global array variable used by +//! the SFO library. +//! +//! This example is intended to explain the HRPWM capabilities. The code can be +//! optimized for code efficiency. Refer to TI's Digital power application +//! examples and TI Digital Power Supply software libraries for details. +//! +//! All ePWM1A,2A,3A,4A channels (GPIO0, GPIO2, GPIO4, GPIO6) will have fine +//! edge movement due to the HRPWM logic +//! +//! -# 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz), ePWM1A toggle +//! low/high with MEP control on falling edge +//! -# 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM2A toggle +//! low/high with MEP control on falling edge +//! -# 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM3A toggle +//! high/low with MEP control on falling edge +//! -# 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM4A toggle +//! high/low with MEP control on falling edge +//! +//! \b Running \b the \b Application +//! -# Run this example at 150MHz SYSCLKOUT (or 100 MHz SYSCLKOUT for +//! 100 MHz devices) +//! -# Load the Example_2833xHRPWM_SFO.gel and observe variables in the +//! watch window +//! -# Activate Real time mode +//! -# Run the code +//! -# Watch ePWM1A-4A waveforms on a Oscilloscope +//! -# In the watch window: +//! Set the variable UpdateFine = 1 to observe the ePWMxA output +//! with HRPWM capabilities (default). +//! Observe the duty cycle of the waveform changes in fine MEP steps +//! -# In the watch window: +//! Change the variable UpdateFine to 0, to observe the +//! ePWMxA output without HRPWM capabilities. +//! Observe the duty cycle of the waveform changes in coarse steps of 10nsec. +//! +//! \b External \b Connections \n +//! Monitor ePWM1-ePWM4 pins on an oscilloscope as described +//! below. +//! - EPWM1A is on GPIO0 +//! - EPWM2A is on GPIO2 +//! - EPWM3A is on GPIO4 +//! - EPWM4A is on GPIO6 +//! +//! \b Watch \b Variables \n +//! - UpdateFine +//! - MEP_ScaleFactor +//! - EPwm1Regs.CMPA.all +//! - EPwm2Regs.CMPA.all +//! - EPwm3Regs.CMPA.all +//! - EPwm4Regs.CMPA.all +//! +//! \note THE SFO.H FUNCTIONS INCLUDED WITH THIS EXAMPLE ONLY SUPPORTS +//! EPWM1-EPWM4. FOR SUPPORT FOR MORE THAN 4 EPWMS, USE SFO_V5.H WITH THE +//! SFO_TI_BUILD_V5.LIB LIBRARY. SEE THE HRPWM REFERENCE GUIDE (SPRU924) +//! FOR USAGE INFORMATION AND DIFFERENCES BETWEEN VERSIONS. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization +#include "SFO.h" // SFO library headerfile + +// +// Function prototypes +// +void HRPWM1_Config(int); +void HRPWM2_Config(int); +void HRPWM3_Config(int); +void HRPWM4_Config(int); + +// +// General System nets - Useful for debug +// +Uint16 j,duty, DutyFine, n, UpdateFine; +volatile int i; +Uint32 temp; + +// +// Global array used by the SFO library +// +int16 MEP_ScaleFactor[5]; + +volatile struct +EPWM_REGS *ePWM[] ={ &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, + &EPwm4Regs, &EPwm5Regs, &EPwm6Regs}; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + // For this case, just init GPIO for ePWM1-ePWM4 + + // + // For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4 + // These functions are in the DSP2833x_EPwm.c file + // + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // For this example, only initialize the ePWM + // Step 5. User specific code, enable interrupts + // + UpdateFine = 1; + DutyFine = 0; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + // + // MEP_ScaleFactor variables initialization for SFO library functions + // + MEP_ScaleFactor[0] = 0; // Common Variables for SFO functions + MEP_ScaleFactor[1] = 0; // SFO for HRPWM1 + MEP_ScaleFactor[2] = 0; // SFO for HRPWM2 + MEP_ScaleFactor[3] = 0; // SFO for HRPWM3 + MEP_ScaleFactor[4] = 0; // SFO for HRPWM4 + + // + // MEP_ScaleFactor variables initialized using function SFO_MepDis + // + while ( MEP_ScaleFactor[1] == 0 ) + { + SFO_MepDis(1); // SFO for HRPWM1 + } + while ( MEP_ScaleFactor[2] == 0 ) + { + SFO_MepDis(2); // SFO for HRPWM2 + } + while ( MEP_ScaleFactor[3] == 0 ) + { + SFO_MepDis(3); // SFO for HRPWM3 + } + while ( MEP_ScaleFactor[4] == 0 ) + { + SFO_MepDis(4); // SFO for HRPWM4 + } + + // + // Initialize a common seed variable MEP_ScaleFactor[0] required for all + // SFO functions + // + + // + //Common Variable for SFO library function + // + MEP_ScaleFactor[0] = MEP_ScaleFactor[1]; + + // + // Some useful Period vs Frequency values + // SYSCLKOUT = 150MHz 100 MHz + // ----------------------------------------- + // Period Frequency Frequency + // 1000 150 kHz 100 KHz + // 800 187 kHz 125 KHz + // 600 250 kHz 167 KHz + // 500 300 kHz 200 KHz + // 250 600 kHz 400 KHz + // 200 750 kHz 500 KHz + // 100 1.5 MHz 1.0 MHz + // 50 3.0 MHz 2.0 MHz + // 30 5.0 MHz 3.33 MHz + // 25 6.0 MHz 4.0 MHz + // 20 7.5 MHz 5.0 MHz + // 12 12.5 MHz 8.33 MHz + // 10 15.0 MHz 10.0 MHz + // 9 16.7 MHz 11.1 MHz + // 8 18.8 MHz 12.5 MHz + // 7 21.4 MHz 14.3 MHz + // 6 25.0 MHz 16.7 MHz + // 5 30.0 MHz 20.0 MHz + // + + // + // ePWM and HRPWM register initialization + // + + // + // ePWM1 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + // + HRPWM1_Config(30); + + // + // ePWM2 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + HRPWM2_Config(30); + + // + // ePWM3 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + // + HRPWM3_Config(30); + + // + // ePWM4 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz) + // + HRPWM4_Config(30); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + + EDIS; + + for(;;) + { + // + // Sweep DutyFine as a Q15 number from 0.2 - 0.999 + // + for(DutyFine = 0x2300; DutyFine < 0x7000; DutyFine++) + { + // + // Variables + // + int16 CMPA_reg_val, CMPAHR_reg_val; + int32 temp; + + if(UpdateFine) + { + /* + // + // CMPA_reg_val is calculated as a Q0. + // Since DutyFine is a Q15 number, and the period is Q0 + // the product is Q15. So to store as a Q0, we shift right + // 15 bits. + // + CMPA_reg_val = ((long)DutyFine * EPwm1Regs.TBPRD)>>15; + + // + // This next step is to obtain the remainder which was + // truncated during our 15 bit shift above. + // compute the whole value, and then subtract CMPA_reg_val + // shifted LEFT 15 bits: + // + temp = ((long)DutyFine * EPwm1Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + + // + // This obtains the MEP count in digits, from + // 0,1, .... MEP_Scalefactor. Once again since this is Q15 + // convert to Q0 by shifting: + // + CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15; + + // + // Now the lower 8 bits contain the MEP count. + // Since the MEP count needs to be in the upper 8 bits of + // the 16 bit CMPAHR register, shift left by 8. + // + CMPAHR_reg_val = CMPAHR_reg_val << 8; + + // + // Add the offset and rounding + // + CMPAHR_reg_val += 0x0180; + + // + // Write the values to the registers as one 32-bit or two 16-bits + // + EPwm1Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm1Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + */ + + // + // All the above operations may be condensed into + // the following form: EPWM1 calculations + // + CMPA_reg_val = ((long)DutyFine * EPwm1Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm1Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + + // + // Example for a 32 bit write to CMPA:CMPAHR + // + EPwm1Regs.CMPA.all = ((long)CMPA_reg_val)<<16 | CMPAHR_reg_val; + + // + // EPWM2 calculations + // + CMPA_reg_val = ((long)DutyFine * EPwm2Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm2Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[2])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + + // + // Example as a 16 bit write to CMPA and then a 16-bit write to + // CMPAHR + // + EPwm2Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm2Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + + // + // EPWM3 calculations + // + CMPA_reg_val = ((long)DutyFine * EPwm3Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm3Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[3])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + EPwm3Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm3Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + + // + // EPWM4 calculations + // + CMPA_reg_val = ((long)DutyFine * EPwm4Regs.TBPRD)>>15; + temp = ((long)DutyFine * EPwm4Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[4])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + EPwm4Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm4Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + } + + else + { + // + // CMPA_reg_val is calculated as a Q0. + // Since DutyFine is a Q15 number, and the period is Q0 + // the product is Q15. So to store as a Q0, we shift right + // 15 bits. + // + EPwm1Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm1Regs.TBPRD>>15); + EPwm2Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm2Regs.TBPRD)>>15; + EPwm3Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm3Regs.TBPRD)>>15; + EPwm4Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm4Regs.TBPRD)>>15; + } + + for (i=0;i<300;i++) + { + // + // Call the scale factor optimizer lib + // + SFO_MepEn(1); + SFO_MepEn(2); + SFO_MepEn(3); + SFO_MepEn(4); + } + } + } +} + +// +// HRPWM1_Config - +// +void +HRPWM1_Config(period) +{ + // + // ePWM1 register configuration with HRPWM + // ePWM1A toggle low/high with MEP control on Rising edge + // + EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.CMPB = period / 2; // set duty 50% initially + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// +// HRPWM2_Config - +// +void +HRPWM2_Config(period) +{ + // + // ePWM2 register configuration with HRPWM + // ePWM2A toggle low/high with MEP control on Rising edge + // + EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm2Regs.CMPB = period / 2; // set duty 50% initially + EPwm2Regs.TBPHS.all = 0; + EPwm2Regs.TBCTR = 0; + + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm2Regs.HRCNFG.all = 0x0; + EPwm2Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + + EDIS; +} + +// +// HRPWM3_Config - +// +void +HRPWM3_Config(period) +{ + // + // ePWM3 register configuration with HRPWM + // ePWM3A toggle high/low with MEP control on falling edge + // + EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm3Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm3Regs.TBPHS.all = 0; + EPwm3Regs.TBCTR = 0; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm3Regs.HRCNFG.all = 0x0; + EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// +// HRPWM4_Config - +// +void +HRPWM4_Config(period) +{ + // + // ePWM4 register configuration with HRPWM + // ePWM4A toggle high/low with MEP control on falling edge + // + EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm4Regs.TBPRD = period-1; // PWM frequency = 1 / period + EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm4Regs.CMPB = period / 2; // set duty 50% initially + EPwm4Regs.TBPHS.all = 0; + EPwm4Regs.TBCTR = 0; + + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.FREE_SOFT = 11; + + EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm4Regs.HRCNFG.all = 0x0; + EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// +// End of File +// + diff --git a/f2833x/examples/hrpwm_sfo_v5/.ccsproject b/f2833x/examples/hrpwm_sfo_v5/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/hrpwm_sfo_v5/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/hrpwm_sfo_v5/.cproject b/f2833x/examples/hrpwm_sfo_v5/.cproject new file mode 100644 index 0000000..22e034d --- /dev/null +++ b/f2833x/examples/hrpwm_sfo_v5/.cproject @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/hrpwm_sfo_v5/.project b/f2833x/examples/hrpwm_sfo_v5/.project new file mode 100644 index 0000000..4b9ec52 --- /dev/null +++ b/f2833x/examples/hrpwm_sfo_v5/.project @@ -0,0 +1,107 @@ + + + Example_2833xHRPWM_SFO_V5 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + SFO_TI_Build_V5B_fpu.lib + 1 + INSTALLROOT_HRPWM/lib/SFO_TI_Build_V5B_fpu.lib + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_HRPWM + $%7BPARENT-4-PROJECT_LOC%7D/libraries/calibration/hrpwm/f2833x + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c b/f2833x/examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c new file mode 100644 index 0000000..1dcd920 --- /dev/null +++ b/f2833x/examples/hrpwm_sfo_v5/Example_2833xHRPWM_SFO_V5.c @@ -0,0 +1,553 @@ +//########################################################################### +// +// FILE: Example_2833xHRPWM_SFO_V5.c +// +// TITLE: High Resolution PWM SFO V5 Example +// +//! \addtogroup f2833x_example_list +//!

High Resolution PWM SFO V5

+//! +//! This example modifies the MEP control registers to show edge displacement +//! due to the HRPWM control extension of the respective ePWM module. +//! +//! \note By default, this example project is configured for floating-point +//! math. All included libraries must be pre-compiled for floating-point math. +//! Therefore, SFO_TI_Build_V5B_fpu.lib (compiled for floating-point) is +//! included in the project instead of the SFO_TI_Build_V5B.lib +//! (compiled for fixed-point). To convert the example for fixed-point math, +//! follow the instructions in sfo_readme.txt in the /doc directory of the +//! header files and peripheral examples package. +//! +//! \note This program requires the DSP2833x header files, which include +//! the following files required for this example: +//! SFO_V5.h and SFO_TI_Build_V5B_fpu.lib (or SFO_TI_Build_V5B.lib for +//! fixed point) +//! +//! This example calls the following TI's MEP Scale Factor Optimizer (SFO) +//! software library V5 functions: +//! +//! - \b int \b SFO_MepEn_V5(int i); updates MEP_ScaleFactor[i] dynamically +//! when HRPWM is in use. +//! - \b Returns +//! - 1 when complete for the specified channel +//! - 0 if not complete for the specified channel +//! - 2 if there is a scale factor out-of-range error (MEP_ScaleFactor[n] +//! differs from seed MEP_ScaleFactor[0] by more than +/-15) +//! +//! - \b int \b SFO_MepDis_V5(int i); updates MEP_ScaleFactor[i] when HRPWM +//! is not used +//! - \b Returns +//! - 1 when complete for the specified channel +//! - 0 if not complete for the specified channel +//! +//! This example is intended to explain the HRPWM capabilities. The code can be +//! optimized for code efficiency. Refer to TI's Digital power application +//! examples and TI Digital Power Supply software libraries for details. +//! All ePWM1A-6A channels will have fine +//! edge movement due to the HRPWM logic +//! +//! - 5MHz PWM (for 150 MHz SYSCLKOUT), ePWMxA toggle high/low with MEP control +//! on rising edge +//! - 3.33MHz PWM (for 100 MHz SYSCLKOUT), ePWMxA toggle high/low with MEP +//! control on rising edge +//! +//! \b Running \b the \b Application \n +//! -# \b **!!IMPORTANT!!** - in SFO_V5.h, set PWM_CH to the max number of +//! HRPWM channels plus one. For example, for the F28335, the +//! maximum number of HRPWM channels is 6. 6+1=7, so set +//! \#define PWM_CH 7 in SFO_V5.h. (Default is 7) +//! -# Run this example at 150/100MHz SYSCLKOUT +//! -# Load the Example_2833xHRPWM_SFO.gel and observe variables in the watch +//! window +//! -# Activate Real time mode +//! -# Run the code +//! -# Watch ePWM1-6 waveforms on a Oscilloscope +//! -# In the watch window: +//! Set the variable UpdateFine = 1 to observe the ePWMxA output +//! with HRPWM capabilities (default). Observe the duty cycle of the waveform +//! changes in fine MEP steps +//! -# In the watch window: +//! Change the variable UpdateFine to 0, to observe the +//! ePWMxA output without HRPWM capabilities. Observe the duty cycle of the +//! waveform changes in coarse steps of 10nsec. +//! +//! \b External \b Connections \n +//! Monitor the following pins on an oscilloscope: +//! - ePWM1A is on GPIO0 +//! - ePWM2A is on GPIO2 +//! - ePWM3A is on GPIO4 +//! - ePWM4A is on GPIO6 +//! - ePWM5A is on GPIO8 +//! - ePWM6A is onGPIO10 +//! +//! \b Watch \b Variables \n +//! - UpdateFine +//! - MEP_ScaleFactor +//! - EPwm1Regs.CMPA.all +//! - EPwm2Regs.CMPA.all +//! - EPwm3Regs.CMPA.all +//! - EPwm4Regs.CMPA.all +//! - EPwm5Regs.CMPA.all +//! - EPwm6Regs.CMPA.all +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization + +// +// SFO V5 library headerfile - required to use SFO library functions +// +#include "SFO_V5.h" + +// +// !!IMPORTANT!! +// UPDATE NUMBER OF HRPWM CHANNELS + 1 USED IN SFO_V5.H +// i.e. #define PWM_CH // F28335 has a maximum of 6 HRPWM channels (7=6+1) +// + +// +// Declare your function prototypes here +// +void HRPWM_Config(int); +void error (void); + +// +// General System nets - Useful for debug +// +Uint16 UpdateFine, DutyFine, status, nMepChannel; + +// +// The following declarations are required in order to use the SFO +// library functions: +// + +// +// Global array used by the SFO library. For n HRPWM channels + 1 for +// MEP_ScaleFactor[0] +// +int MEP_ScaleFactor[PWM_CH]; + +// +// Array of pointers to EPwm register structures: +// *ePWM[0] is defined as dummy value not used in the example +// +volatile struct EPWM_REGS *ePWM[PWM_CH] = + { &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, + &EPwm4Regs, &EPwm5Regs, &EPwm6Regs}; + +// +// Main +// +void main(void) +{ + // + // Local variables + // + int i; + Uint32 temp; + int16 CMPA_reg_val, CMPAHR_reg_val; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this case just init GPIO pins for ePWM1-ePWM6 + // This function is in the DSP2833x_EPwm.c file + // + InitEPwmGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // For this example, only initialize the ePWM + // Step 5. User specific code, enable interrupts + // + + UpdateFine = 1; + DutyFine = 0; + nMepChannel=1; // HRPWM diagnostics start on ePWM channel 1 + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + // + // MEP_ScaleFactor variables initialization for SFO library functions + // + for(i=0;i>15; + + // + // This next step is to obtain the remainder which was + // truncated during our 15 bit shift above. + // compute the whole value, and then subtract CMPA_reg_val + // shifted LEFT 15 bits: + // + temp = ((long)DutyFine * EPwm1Regs.TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + + // + // This obtains the MEP count in digits, from + // 0,1, .... MEP_Scalefactor. Once again since this is Q15 + // convert to Q0 by shifting: + // + CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15; + + // + // Now the lower 8 bits contain the MEP count. + // Since the MEP count needs to be in the upper 8 bits of + // the 16 bit CMPAHR register, shift left by 8. + // + CMPAHR_reg_val = CMPAHR_reg_val << 8; + + // + // Add the offset and rounding + // + CMPAHR_reg_val += 0x0180; + + // + // Write the values to the registers as one 32-bit or + // two 16-bits + // + EPwm1Regs.CMPA.half.CMPA = CMPA_reg_val; + EPwm1Regs.CMPA.half.CMPAHR = CMPAHR_reg_val; + + // + // All the above operations may be condensed into + // the following form for each channel: + // + */ + + // + // EPWM calculations where EPwm1Regs are accessed + // by (*ePWM[1]), EPwm2Regs are accessed by (*ePWM[2]), + // etc.: + // + for(i=1;i>15; + temp = ((long)DutyFine * (*ePWM[i]).TBPRD) ; + temp = temp - ((long)CMPA_reg_val<<15); + CMPAHR_reg_val = (temp*MEP_ScaleFactor[i])>>15; + CMPAHR_reg_val = CMPAHR_reg_val << 8; + CMPAHR_reg_val += 0x0180; + + // + // Example for a 32 bit write to CMPA:CMPAHR + // + (*ePWM[i]).CMPA.all = ((long)CMPA_reg_val)<<16 | + CMPAHR_reg_val; + } + + } + + else + { + // + // CMPA_reg_val is calculated as a Q0. + // Since DutyFine is a Q15 number, and the period is Q0 + // the product is Q15. So to store as a Q0, we shift right + // 15 bits. + // + for(i=1;i>15); + } + } + + // + // Call the scale factor optimizer lib function SFO_MepEn_V5() + // periodically to track for any changes due to temp/voltage. + // SFO_MepEn_V5 Calibration must be finished on one channel + // (return 1) before moving on to the next channel. + // + // *NOTE*: In this example, SFO_MepEn_V5 is called 700 times in a + // loop. For example purposes, this allows the CMPAHR and + // CMPA registers to change in such a way that when + // watching in "Continuous Refresh" mode, the user + // can see the CMPAHR register increment in fine steps to a + // certain point before the CMPA register increments in a + // coarse step. Normally, SFO_MepEn_V5 can be called once + // every so often in the background for a slow update with + // no for-loop. + // + + // + // Call SFO_MepEn_V5 700 times. + // + for (i=0; i<700; i++) + { + status = SFO_MepEn_V5(nMepChannel); + + // + // Once SFO_MepEn_V5 complete (returns 1)- + // + if (status == SFO_COMPLETE) + { + nMepChannel++; // move on to next channel + } + + // + // If MEP_ScaleFactor[nMepChannel] differs from seed + // Mep_ScaleFactor[0] by more than +/-15, status = 2 + // (out of range error) + // + else if (status == SFO_OUTRANGE_ERROR) + { + error(); + } + + if(nMepChannel==PWM_CH) + { + // + // Once max channels reached, loop back to channel 1 + // + nMepChannel =1; + } + } + } + } +} + +// +// HRPWM_Config - Configures all ePWM channels and sets up HRPWM on +// PWMxA channels +// +void +HRPWM_Config(period) +{ + Uint16 j; + + // + // ePWM channel register configuration with HRPWM + // ePWMxA toggle low/high with MEP control on Rising edge + // + for (j=1;j +/- 15 from the Seed Value in MEP_ScaleFactor[0]. +// SFO_MepEn_V5 returned a "2" (SFO_OUTRANGE_ERROR). The user should: +// (1) Re-run SFO_MepDis_V5 to re-calibrate an appropriate seed value. +// (2) Ensure the code is not calling Mep_En_V5 on a different channel when it +// is currently still running on a channel. (Repetitively call Mep_En_V5 +// on current channel until an SFO_COMPLETE ( i.e. 1) is returned. +// (3) If the out-of-range condition is acceptable for the application, ignore +// the "2" and treat it as a "1" or SFO_COMPLETE. +// +void +error (void) +{ + // + // Error - MEP_ScaleFactor out of range of Seed - rerun MepDis calibration. + // + ESTOP0; +} + +// +// End of File +// + diff --git a/f2833x/examples/hrpwm_slider/.ccsproject b/f2833x/examples/hrpwm_slider/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/hrpwm_slider/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/hrpwm_slider/.cproject b/f2833x/examples/hrpwm_slider/.cproject new file mode 100644 index 0000000..aa85b85 --- /dev/null +++ b/f2833x/examples/hrpwm_slider/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/hrpwm_slider/.project b/f2833x/examples/hrpwm_slider/.project new file mode 100644 index 0000000..0054314 --- /dev/null +++ b/f2833x/examples/hrpwm_slider/.project @@ -0,0 +1,98 @@ + + + Example_2833xHRPWM_slider + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_EPwm.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_EPwm.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/hrpwm_slider/Example_2833xHRPWM_slider.c b/f2833x/examples/hrpwm_slider/Example_2833xHRPWM_slider.c new file mode 100644 index 0000000..8f6f98e --- /dev/null +++ b/f2833x/examples/hrpwm_slider/Example_2833xHRPWM_slider.c @@ -0,0 +1,446 @@ +//########################################################################### +// +// FILE: Example_2833xHRPWM_slider.c +// +// TITLE: High Resolution PWM with slider Example +// +//! \addtogroup f2833x_example_list +//!

High Resolution PWM with slider(hrpwm_slider)

+//! +//! This example modifies the MEP control registers to show edge displacement +//! due to HRPWM control blocks of the respective ePWM module, ePWM1A, 2A, 3A, +//! and 4A channels (GPIO0, GPIO2, GPIO4, and GPIO6) will have fine edge +//! movement due to HRPWM logic. +//! +//! \b Running \b the \b Application +//! -# Launch the target configuration and connect to the target first +//! -# Load the program and set it up to run in real time mode. Do not run yet! +//! -# Load the Example_2833xHRPWM_slider.gel file (provded in the folder) +//! -# Select the HRPWM FineDutySlider from the GEL menu. A FineDuty slider +//! graphics will show up in CCS. +//! -# Add "DutyFine" variable to the watch window +//! -# Load the program and run. Use the Slider to and observe the epwm edge +//! displacement for each slider step change. \n +//! +//! This explains the MEP control on the ePWMxA channels, +//! -# 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),\n +//! ePWM1A toggle low/high with MEP control on rising edge \n +//! ePWM1B toggle low/high with NO HRPWM control +//! -# 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),\n +//! ePWM2A toggle low/high with MEP control on rising edge \n +//! ePWM2B toggle low/high with NO HRPWM control +//! -# 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),\n +//! ePWM3A toggle as high/low with MEP control on falling edge \n +//! ePWM3B toggle low/high with NO HRPWM control +//! -# 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),\n +//! ePWM4A toggle as high/low with MEP control on falling edge \n +//! ePWM4B toggle low/high with NO HRPWM control +//! +//! \b External \b Connections \n +//! - EPWM1A is on GPIO0 +//! - EPWM1B is on GPIO1 +//! - EPWM2A is on GPIO2 +//! - EPWM2B is on GPIO3 +//! - EPWM3A is on GPIO4 +//! - EPWM3B is on GPIO5 +//! +//! \b Watch \b Variables \n +//! - DutyFine +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_EPwm_defines.h" // useful defines for initialization + +// +// Function prototypes +// +void HRPWM1_Config(int); +void HRPWM2_Config(int); +void HRPWM3_Config(int); +void HRPWM4_Config(int); + +// +// General System nets - Useful for debug +// +Uint16 i,j, duty, DutyFine, n,update; + +Uint32 temp; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + // For this case, just init GPIO for ePWM1-ePWM4 + + // + // For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4 + // These functions are in the DSP2833x_EPwm.c file + // + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // For this example, only initialize the ePWM + // Step 5. User specific code, enable interrupts + // + update =1; + DutyFine =0; + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; + EDIS; + + // + // Some useful Period vs Frequency values + // SYSCLKOUT = 150MHz 100 MHz + // ----------------------------------------- + // Period Frequency Frequency + // 1000 150 kHz 100 KHz + // 800 187 kHz 125 KHz + // 600 250 kHz 167 KHz + // 500 300 kHz 200 KHz + // 250 600 kHz 400 KHz + // 200 750 kHz 500 KHz + // 100 1.5 MHz 1.0 MHz + // 50 3.0 MHz 2.0 MHz + // 25 6.0 MHz 4.0 MHz + // 20 7.5 MHz 5.0 MHz + // 12 12.5 MHz 8.33 MHz + // 10 15.0 MHz 10.0 MHz + // 9 16.7 MHz 11.1 MHz + // 8 18.8 MHz 12.5 MHz + // 7 21.4 MHz 14.3 MHz + // 6 25.0 MHz 16.7 MHz + // 5 30.0 MHz 20.0 MHz + // + + // + // ePWM and HRPWM register initialization + // + + // + // ePWM1 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + // + HRPWM1_Config(10); + + // + // ePWM2 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + // + HRPWM2_Config(20); + + // + // ePWM3 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz) + // + HRPWM3_Config(10); + + // + // ePWM4 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz) + // + HRPWM4_Config(20); + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; + EDIS; + + while (update ==1) + { + // + //for(DutyFine =1; DutyFine <256 ;DutyFine ++) + // + { + // + // Example, write to the HRPWM extension of CMPA + // + + // + // Left shift by 8 to write into MSB bits + // + EPwm1Regs.CMPA.half.CMPAHR = DutyFine << 8; + + // + // Left shift by 8 to write into MSB bits + // + EPwm2Regs.CMPA.half.CMPAHR = DutyFine << 8; + + // + // Example, 32-bit write to CMPA:CMPAHR + // + EPwm3Regs.CMPA.all = ((Uint32)EPwm3Regs.CMPA.half.CMPA << 16) + + (DutyFine << 8); + EPwm4Regs.CMPA.all = ((Uint32)EPwm4Regs.CMPA.half.CMPA << 16) + + (DutyFine << 8); + + // + // Dummy delay between MEP changes + // + //for (i=0;i<10000;i++) + //{ + // + //} + } + } +} + +// +// HRPWM1_Config - +// +void +HRPWM1_Config(period) +{ + // + // ePWM1 register configuration with HRPWM + // ePWM1A toggle low/high with MEP control on Rising edge + // + EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm1Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm1Regs.CMPB = period / 2; // set duty 50% initially + EPwm1Regs.TBPHS.all = 0; + EPwm1Regs.TBCTR = 0; + + EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm1Regs.HRCNFG.all = 0x0; + EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; // MEP control on Rising edge + EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// +// HRPWM2_Config - +// +void +HRPWM2_Config(period) +{ + // + // ePWM2 register configuration with HRPWM + // ePWM2A toggle low/high with MEP control on Rising edge + // + EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm2Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm2Regs.CMPB = period / 2; // set duty 50% initially + EPwm2Regs.TBPHS.all = 0; + EPwm2Regs.TBCTR = 0; + + EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high + EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; + EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; + EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; + + EALLOW; + EPwm2Regs.HRCNFG.all = 0x0; + EPwm2Regs.HRCNFG.bit.EDGMODE = HR_REP; // MEP control on Rising edge + EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + + EDIS; +} + +// +// HRPWM3_Config - +// +void +HRPWM3_Config(period) +{ + // + // ePWM3 register configuration with HRPWM + // ePWM3A toggle high/low with MEP control on falling edge + // + EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm3Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm3Regs.CMPB = period / 2; // set duty 50% initially + EPwm3Regs.TBPHS.all = 0; + EPwm3Regs.TBCTR = 0; + + EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm3Regs.HRCNFG.all = 0x0; + EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// +// HRPWM4_Config - +// +void +HRPWM4_Config(period) +{ + // + // ePWM4 register configuration with HRPWM + // ePWM4A toggle high/low with MEP control on falling edge + // + EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load + EPwm4Regs.TBPRD = period - 1; // PWM frequency = 1 / period + EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially + EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension + EPwm4Regs.CMPB = period / 2; // set duty 50% initially + EPwm4Regs.TBPHS.all = 0; + EPwm4Regs.TBCTR = 0; + + EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; + EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; + + EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; + EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; + EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; + + EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low + EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; + EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET; + EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; + + EALLOW; + EPwm4Regs.HRCNFG.all = 0x0; + EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge + EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; + EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; + EDIS; +} + +// +// End of File +// + diff --git a/f2833x/examples/hrpwm_slider/Example_2833xHRPWM_slider.gel b/f2833x/examples/hrpwm_slider/Example_2833xHRPWM_slider.gel new file mode 100644 index 0000000..740db5f --- /dev/null +++ b/f2833x/examples/hrpwm_slider/Example_2833xHRPWM_slider.gel @@ -0,0 +1,52 @@ +/* +// TI File $Revision: /main/1 $ +// Checkin $Date: May 27, 2009 13:29:55 $ +//########################################################################### +// +// This .gel file can be used to help load and build the example project. +// It should be unloaded from Code Composer Studio before loading another +// project. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +menuitem "DSP2833x HRPWM FineDutySlider" +slider FineDutySlider(1, 255, 1, 1, finedutyvalue) +{ + + DutyFine = finedutyvalue; +} diff --git a/f2833x/examples/i2c_eeprom/.ccsproject b/f2833x/examples/i2c_eeprom/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/i2c_eeprom/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/i2c_eeprom/.cproject b/f2833x/examples/i2c_eeprom/.cproject new file mode 100644 index 0000000..4ee511c --- /dev/null +++ b/f2833x/examples/i2c_eeprom/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/i2c_eeprom/.project b/f2833x/examples/i2c_eeprom/.project new file mode 100644 index 0000000..123583a --- /dev/null +++ b/f2833x/examples/i2c_eeprom/.project @@ -0,0 +1,103 @@ + + + Example_2833xI2C_eeprom + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_I2C.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_I2C.c + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/i2c_eeprom/Example_2833xI2C_eeprom.c b/f2833x/examples/i2c_eeprom/Example_2833xI2C_eeprom.c new file mode 100644 index 0000000..cd5e331 --- /dev/null +++ b/f2833x/examples/i2c_eeprom/Example_2833xI2C_eeprom.c @@ -0,0 +1,609 @@ +//########################################################################### +// +// FILE: Example_2833xI2C_eeprom.c +// +// TITLE: I2C EEPROM Example +// +//! \addtogroup f2833x_example_list +//!

I2C EEPROM (i2c_eeprom)

+//! +//! This program requires an external I2C EEPROM connected to +//! the I2C bus at address 0x50. \n +//! This program will write 1-14 words to EEPROM and read them back. +//! The data written and the EEPROM address written to are contained +//! in the message structure, \b I2cMsgOut1. The data read back will be +//! contained in the message structure \b I2cMsgIn1. +//! +//! \b Watch \b Variables \n +//! - I2cMsgIn1 +//! - I2cMsgOut1 +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Note: I2C Macros used in this example can be found in the +// DSP2833x_I2C_defines.h file +// + +// +// Function Prototypes +// +void I2CA_Init(void); +Uint16 I2CA_WriteData(struct I2CMSG *msg); +Uint16 I2CA_ReadData(struct I2CMSG *msg); +__interrupt void i2c_int1a_isr(void); +void pass(void); +void fail(void); + +// +// Defines +// +#define I2C_SLAVE_ADDR 0x50 +#define I2C_NUMBYTES 4 +#define I2C_EEPROM_HIGH_ADDR 0x00 +#define I2C_EEPROM_LOW_ADDR 0x30 + +// +// Globals +// + +// +// Two bytes will be used for the outgoing address, thus only setup 14 bytes +// maximum +// +struct I2CMSG I2cMsgOut1= +{ + I2C_MSGSTAT_SEND_WITHSTOP, + I2C_SLAVE_ADDR, + I2C_NUMBYTES, + I2C_EEPROM_HIGH_ADDR, + I2C_EEPROM_LOW_ADDR, + 0x12, // Msg Byte 1 + 0x34, // Msg Byte 2 + 0x56, // Msg Byte 3 + 0x78, // Msg Byte 4 + 0x9A, // Msg Byte 5 + 0xBC, // Msg Byte 6 + 0xDE, // Msg Byte 7 + 0xF0, // Msg Byte 8 + 0x11, // Msg Byte 9 + 0x10, // Msg Byte 10 + 0x11, // Msg Byte 11 + 0x12, // Msg Byte 12 + 0x13, // Msg Byte 13 + 0x12 // Msg Byte 14 +}; + +struct I2CMSG I2cMsgIn1= +{ I2C_MSGSTAT_SEND_NOSTOP, + I2C_SLAVE_ADDR, + I2C_NUMBYTES, + I2C_EEPROM_HIGH_ADDR, + I2C_EEPROM_LOW_ADDR +}; + +// +// Globals +// +struct I2CMSG *CurrentMsgPtr; // Used in interrupts +Uint16 PassCount; +Uint16 FailCount; + +// +// Main +// +void main(void) +{ + Uint16 Error; + Uint16 i; + + CurrentMsgPtr = &I2cMsgOut1; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); + + // + // Setup only the GP I/O only for I2C functionality + // + InitI2CGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.I2CINT1A = &i2c_int1a_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + I2CA_Init(); + + // + // Step 5. User specific code + // + + // + // Clear Counters + // + PassCount = 0; + FailCount = 0; + + // + // Clear incoming message buffer + // + for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++) + { + I2cMsgIn1.MsgBuffer[i] = 0x0000; + } + + // + // Enable interrupts required for this example + // + + // + // Enable I2C interrupt 1 in the PIE: Group 8 interrupt 1 + // + PieCtrlRegs.PIEIER8.bit.INTx1 = 1; + + // + // Enable CPU INT8 which is connected to PIE group 8 + // + IER |= M_INT8; + EINT; + + // + // Application loop + // + for(;;) + { + // + // Write data to EEPROM section + // + + // + // Check the outgoing message to see if it should be sent. + // In this example it is initialized to send with a stop bit. + // + if(I2cMsgOut1.MsgStatus == I2C_MSGSTAT_SEND_WITHSTOP) + { + Error = I2CA_WriteData(&I2cMsgOut1); + + // + // If communication is correctly initiated, set msg status to busy + // and update CurrentMsgPtr for the interrupt service routine. + // Otherwise, do nothing and try again next loop. Once message is + // initiated, the I2C interrupts will handle the rest. Search for + // ICINTR1A_ISR in the i2c_eeprom_isr.c file. + // + if (Error == I2C_SUCCESS) + { + CurrentMsgPtr = &I2cMsgOut1; + I2cMsgOut1.MsgStatus = I2C_MSGSTAT_WRITE_BUSY; + } + } // end of write section + + // + // Read data from EEPROM section + // + + // + // Check outgoing message status. Bypass read section if status is + // not inactive. + // + if (I2cMsgOut1.MsgStatus == I2C_MSGSTAT_INACTIVE) + { + // + // Check incoming message status. + // + if(I2cMsgIn1.MsgStatus == I2C_MSGSTAT_SEND_NOSTOP) + { + // + // EEPROM address setup portion + // + while(I2CA_ReadData(&I2cMsgIn1) != I2C_SUCCESS) + { + // + // Maybe setup an attempt counter to break an infinite + // while loop. The EEPROM will send back a NACK while it is + // performing a write operation. Even though the write + // communique is complete at this point, the EEPROM could + // still be busy programming the data. Therefore, multiple + // attempts are necessary. + // + } + + // + // Update current message pointer and message status + // + CurrentMsgPtr = &I2cMsgIn1; + I2cMsgIn1.MsgStatus = I2C_MSGSTAT_SEND_NOSTOP_BUSY; + } + + // + // Once message has progressed past setting up the internal address + // of the EEPROM, send a restart to read the data bytes from the + // EEPROM. Complete the communique with a stop bit. MsgStatus is + // updated in the interrupt service routine. + // + else if(I2cMsgIn1.MsgStatus == I2C_MSGSTAT_RESTART) + { + // + // Read data portion + // + while(I2CA_ReadData(&I2cMsgIn1) != I2C_SUCCESS) + { + // + // Maybe setup an attempt counter to break an infinite + // while loop. + // + } + + // + // Update current message pointer and message status + // + CurrentMsgPtr = &I2cMsgIn1; + I2cMsgIn1.MsgStatus = I2C_MSGSTAT_READ_BUSY; + } + } // end of read section + } // end of for(;;) +} // end of main + +// +// I2CA_Init - +// +void +I2CA_Init(void) +{ + // + // Initialize I2C + // + I2caRegs.I2CSAR = 0x0050; // Slave address - EEPROM control code + +#if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT + // + // Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz) + // + I2caRegs.I2CPSC.all = 14; +#endif +#if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT + // + // Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz) + // + I2caRegs.I2CPSC.all = 9; +#endif + + I2caRegs.I2CCLKL = 10; // NOTE: must be non zero + I2caRegs.I2CCLKH = 5; // NOTE: must be non zero + I2caRegs.I2CIER.all = 0x24; // Enable SCD & ARDY interrupts + + // + // Take I2C out of reset + // Stop I2C when suspended + // + I2caRegs.I2CMDR.all = 0x0020; + + I2caRegs.I2CFFTX.all = 0x6000; // Enable FIFO mode and TXFIFO + I2caRegs.I2CFFRX.all = 0x2040; // Enable RXFIFO, clear RXFFINT, + + return; +} + +// +// I2CA_WriteData - +// +Uint16 +I2CA_WriteData(struct I2CMSG *msg) +{ + Uint16 i; + + // + // Wait until the STP bit is cleared from any previous master communication + // Clearing of this bit by the module is delayed until after the SCD bit is + // set. If this bit is not checked prior to initiating a new message, the + // I2C could get confused. + // + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + + // + // Setup slave address + // + I2caRegs.I2CSAR = msg->SlaveAddress; + + // + // Check if bus busy + // + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + + // + // Setup number of bytes to send MsgBuffer + Address + // + I2caRegs.I2CCNT = msg->NumOfBytes+2; + + // + // Setup data to send + // + I2caRegs.I2CDXR = msg->MemoryHighAddr; + I2caRegs.I2CDXR = msg->MemoryLowAddr; + + for (i=0; iNumOfBytes; i++) + { + I2caRegs.I2CDXR = *(msg->MsgBuffer+i); + } + + // + // Send start as master transmitter + // + I2caRegs.I2CMDR.all = 0x6E20; + + return I2C_SUCCESS; +} + +// +// I2CA_ReadData - +// +Uint16 +I2CA_ReadData(struct I2CMSG *msg) +{ + // + // Wait until the STP bit is cleared from any previous master communication. + // Clearing of this bit by the module is delayed until after the SCD bit is + // set. If this bit is not checked prior to initiating a new message, the + // I2C could get confused. + // + if (I2caRegs.I2CMDR.bit.STP == 1) + { + return I2C_STP_NOT_READY_ERROR; + } + + I2caRegs.I2CSAR = msg->SlaveAddress; + + if(msg->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP) + { + // + // Check if bus busy + // + if (I2caRegs.I2CSTR.bit.BB == 1) + { + return I2C_BUS_BUSY_ERROR; + } + I2caRegs.I2CCNT = 2; + I2caRegs.I2CDXR = msg->MemoryHighAddr; + I2caRegs.I2CDXR = msg->MemoryLowAddr; + I2caRegs.I2CMDR.all = 0x2620; // Send data to setup EEPROM address + } + else if(msg->MsgStatus == I2C_MSGSTAT_RESTART) + { + I2caRegs.I2CCNT = msg->NumOfBytes; // Setup how many bytes to expect + I2caRegs.I2CMDR.all = 0x2C20; // Send restart as master receiver + } + + return I2C_SUCCESS; +} + +// +// i2c_int1a_isr - I2C-A +// +__interrupt void +i2c_int1a_isr(void) +{ + Uint16 IntSource, i; + + // + // Read interrupt source + // + IntSource = I2caRegs.I2CISRC.all; + + // + // Interrupt source = stop condition detected + // + if(IntSource == I2C_SCD_ISRC) + { + // + // If completed message was writing data, reset msg to inactive state + // + if (CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_WRITE_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_INACTIVE; + } + else + { + // + // If a message receives a NACK during the address setup portion + // of the EEPROM read, the code further below included in the + // register access ready interrupt source code will generate a stop + // condition. After the stop condition is received (here), set the + // message status to try again. User may want to limit the number + // of retries before generating an error. + // + if(CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_SEND_NOSTOP; + } + + // + // If completed message was reading EEPROM data, reset msg + // to inactive state and read data from FIFO. + // + else if (CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_READ_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_INACTIVE; + for(i=0; i < I2C_NUMBYTES; i++) + { + CurrentMsgPtr->MsgBuffer[i] = I2caRegs.I2CDRR; + } + { + // + // Check received data + // + for(i=0; i < I2C_NUMBYTES; i++) + { + if(I2cMsgIn1.MsgBuffer[i] == I2cMsgOut1.MsgBuffer[i]) + { + PassCount++; + } + else + { + FailCount++; + } + } + + if(PassCount == I2C_NUMBYTES) + { + pass(); + } + else + { + fail(); + } + } + } + } + } // end of stop condition detected + + // + // Interrupt source = Register Access Ready + // This interrupt is used to determine when the EEPROM address setup + // portion of the read data communication is complete. Since no stop bit is + // commanded, this flag tells us when the message has been sent instead of + // the SCD flag. If a NACK is received, clear the NACK bit and command a + // stop. Otherwise, move on to the read data portion of the communication. + // + else if(IntSource == I2C_ARDY_ISRC) + { + if(I2caRegs.I2CSTR.bit.NACK == 1) + { + I2caRegs.I2CMDR.bit.STP = 1; + I2caRegs.I2CSTR.all = I2C_CLR_NACK_BIT; + } + else if(CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP_BUSY) + { + CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_RESTART; + } + } + + else + { + // + // Generate some error due to invalid interrupt source + // + __asm(" ESTOP0"); + } + + // + // Enable future I2C (PIE Group 8) interrupts + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; +} + +// +// pass - +// +void pass() +{ + __asm(" ESTOP0"); + for(;;); +} + +// +// fail - +// +void fail() +{ + __asm(" ESTOP0"); + for(;;); +} + +// +// End of File +// + diff --git a/f2833x/examples/lpm_haltwake/.ccsproject b/f2833x/examples/lpm_haltwake/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/lpm_haltwake/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/lpm_haltwake/.cproject b/f2833x/examples/lpm_haltwake/.cproject new file mode 100644 index 0000000..1a078df --- /dev/null +++ b/f2833x/examples/lpm_haltwake/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/lpm_haltwake/.project b/f2833x/examples/lpm_haltwake/.project new file mode 100644 index 0000000..5b83cfe --- /dev/null +++ b/f2833x/examples/lpm_haltwake/.project @@ -0,0 +1,98 @@ + + + Example_2833xHaltWake + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/lpm_haltwake/Example_2833xHaltWake.c b/f2833x/examples/lpm_haltwake/Example_2833xHaltWake.c new file mode 100644 index 0000000..c60ff91 --- /dev/null +++ b/f2833x/examples/lpm_haltwake/Example_2833xHaltWake.c @@ -0,0 +1,229 @@ +//########################################################################### +// +// FILE: Example_2833xHaltWake.c +// +// TITLE: Low Power Modes: Halt Mode and Wakeup Example +// +//! \addtogroup f2833x_example_list +//!

Low Power Modes: Halt Mode and Wakeup (lpm_haltwake)

+//! +//! This example puts the device into HALT mode. If the lowest +//! possible current consumption in HALT mode is desired, the +//! JTAG connector must be removed from the device board while +//! the device is in HALT mode. +//! +//! The example then wakes up the device from HALT using GPIO0. +//! GPIO0 wakes the device from HALT mode when a high-to-low +//! signal is detected on the pin. This pin must be pulsed by +//! an external agent for wakeup. +//! +//! The wakeup process begins as soon as GPIO0 is held low for the +//! time indicated in the device datasheet. After the +//! device wakes up, GPIO1 can be observed to go high. +//! +//! GPIO0 is configured as the LPM wakeup pin to trigger a +//! WAKEINT interrupt upon detection of a low pulse. +//! Initially, pull GPIO0 high externally. To wake device +//! from halt mode, pull GPIO0 low for at least the crystal +//! startup time + 2 OSCLKS, then pull it high again. +//! +//! \b External \b Connections \n +//! - To observe when device wakes from HALT mode, monitor +//! GPIO1 with an oscilloscope (set to 1 in WAKEINT ISR) +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +__interrupt void WAKE_ISR(void); // ISR for WAKEINT + +// +// Main +// +void main() +{ + __asm(" EALLOW"); + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Enable all pull-ups + // + EALLOW; + GpioCtrlRegs.GPAPUD.all = 0; + GpioCtrlRegs.GPBPUD.all = 0; + + // + // GPIO1 set in the ISR to indicate device woken up. + // + GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; + + GpioIntRegs.GPIOLPMSEL.bit.GPIO0 = 1; // Choose GPIO0 pin for wakeup + EDIS; + + // + // Step 3. Clear all interrupts and initialize PIE vector table + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.WAKEINT = &WAKE_ISR; + EDIS; + + // + // Step 4. Initialize all the Device Peripherals: + // Not applicable for this example. + // + + // + // Step 5. User specific code, enable interrupts + // + + // + // Enable CPU INT1 which is connected to WakeInt + // + IER |= M_INT1; + + // + // Enable WAKEINT in the PIE: Group 1 interrupt 8 + // + PieCtrlRegs.PIEIER1.bit.INTx8 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + + // + // Enable global Interrupts + // + EINT; // Enable Global interrupt INTM + + // + // Write the LPM code value + // + EALLOW; + + // + // Only enter low power mode when PLL is not in limp mode. + // + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) + { + SysCtrlRegs.LPMCR0.bit.LPM = 0x0002; // LPM mode = Halt + } + EDIS; + + // + // Force device into HALT + // + + // + // Device waits in IDLE until falling edge on GPIO0/XNMI pin + // wakes device from halt mode. + // + __asm(" IDLE"); + + // + // Loop here after wake-up. + // + for(;;) + { + + } +} + +// +// ISR for WAKEINT - Will be executed when low pulse triggered on GPIO0 pin +// +__interrupt void +WAKE_ISR(void) +{ + // + // Toggle GPIO1 in the ISR - monitored with oscilloscope + // + GpioDataRegs.GPATOGGLE.bit.GPIO1 = 1; + + PieCtrlRegs.PIEACK.bit.ACK1 = 1; +} + +// +// End of File +// + diff --git a/f2833x/examples/lpm_idlewake/.ccsproject b/f2833x/examples/lpm_idlewake/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/lpm_idlewake/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/lpm_idlewake/.cproject b/f2833x/examples/lpm_idlewake/.cproject new file mode 100644 index 0000000..69901e4 --- /dev/null +++ b/f2833x/examples/lpm_idlewake/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/lpm_idlewake/.project b/f2833x/examples/lpm_idlewake/.project new file mode 100644 index 0000000..7b0999c --- /dev/null +++ b/f2833x/examples/lpm_idlewake/.project @@ -0,0 +1,98 @@ + + + Example_2833xIdleWake + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/lpm_idlewake/Example_2833xIdleWake.c b/f2833x/examples/lpm_idlewake/Example_2833xIdleWake.c new file mode 100644 index 0000000..5740eb6 --- /dev/null +++ b/f2833x/examples/lpm_idlewake/Example_2833xIdleWake.c @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: Example_2833xIdleWake.c +// +// TITLE: Low Power Modes: Device Idle Mode and Wakeup Example +// +//! \addtogroup f2833x_example_list +//!

Low Power Modes: Device Idle Mode and Wakeup (lpm_idlewake)

+//! +//! This example puts the device into IDLE mode then +//! wakes up the device from IDLE using XINT1 +//! which triggers on a falling edge from GPIO0. +//! +//! This pin must be pulled from high to low by an external agent for +//! wakeup. GPIO0 is configured as an XINT1 pin to trigger an +//! XINT1 interrupt upon detection of a falling edge. +//! +//! Initially, pull GPIO0 high externally. To wake device +//! from idle mode by triggering an XINT1 interrupt, +//! pull GPIO0 low (falling edge). +//! +//! \b External \b Connections \n +//! - To observe the device wakeup from IDLE mode, monitor GPIO1 with +//! an oscilloscope, which goes high in the XINT_1_ISR. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +__interrupt void XINT_1_ISR(void); // ISR + +// +// Main +// +void main() +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + EALLOW; + GpioCtrlRegs.GPAPUD.all = 0; // Enable all Pull-ups + GpioCtrlRegs.GPBPUD.all = 0; + GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 0; // Choose GPIO0 as the XINT1 pin. + GpioCtrlRegs.GPADIR.all = 0xFFFFFFFE; // All pins are outputs except 0 + GpioDataRegs.GPADAT.all = 0x00000000; // All I/O pins are driven low + EDIS; + + XIntruptRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1 pin + + // + // Interrupt triggers on falling edge + // + XIntruptRegs.XINT1CR.bit.POLARITY = 0; + + // + // Step 3. Clear all interrupts and initialize PIE vector table + // + + // + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.XINT1 = &XINT_1_ISR; + EDIS; + + // + // Step 4. Initialize all the Device Peripherals + // + // Not applicable for this example. + + // + // Step 5. User specific code, enable interrupts + // + + // + // Enable CPU INT1 which is connected to WakeInt + // + IER |= M_INT1; + + // + // Enable XINT1 in the PIE: Group 1 interrupt 4 + // + PieCtrlRegs.PIEIER1.bit.INTx4 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + + // + // Enable global Interrupts + // + EINT; // Enable Global interrupt INTM + + // + // Write the LPM code value + // + EALLOW; + + // + // Only enter Idle mode when PLL is not in limp mode. + // + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) + { + SysCtrlRegs.LPMCR0.bit.LPM = 0x0000; // LPM mode = Idle + } + EDIS; + + __asm(" IDLE"); // Device waits in IDLE until XINT1 interrupts + + for(;;) + { + + } +} + +// +// XINT_1_ISR - +// +__interrupt void +XINT_1_ISR(void) +{ + GpioDataRegs.GPASET.bit.GPIO1 = 1; //GPIO1 is driven high upon exiting IDLE + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + EINT; + return; +} + +// +// End of File +// + diff --git a/f2833x/examples/lpm_standbywake/.ccsproject b/f2833x/examples/lpm_standbywake/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/lpm_standbywake/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/lpm_standbywake/.cproject b/f2833x/examples/lpm_standbywake/.cproject new file mode 100644 index 0000000..a0a5008 --- /dev/null +++ b/f2833x/examples/lpm_standbywake/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/lpm_standbywake/.project b/f2833x/examples/lpm_standbywake/.project new file mode 100644 index 0000000..bb1e576 --- /dev/null +++ b/f2833x/examples/lpm_standbywake/.project @@ -0,0 +1,98 @@ + + + Example_2833xStandbyWake + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/lpm_standbywake/Example_2833xStandbyWake.c b/f2833x/examples/lpm_standbywake/Example_2833xStandbyWake.c new file mode 100644 index 0000000..6ce5413 --- /dev/null +++ b/f2833x/examples/lpm_standbywake/Example_2833xStandbyWake.c @@ -0,0 +1,231 @@ +//########################################################################### +// +// FILE: Example_2833xStandbyWake.c +// +// TITLE: Low Power Modes: Device Standby Mode and Wakeup Example +// +//! \addtogroup f2833x_example_list +//!

Low Power Modes: Device Standby Mode and Wakeup (lpm_standbywake)

+//! +//! This example puts the device into STANDBY mode. If the lowest +//! possible current consumption in STANDBY mode is desired, the +//! JTAG connector must be removed from the device board while +//! the device is in STANDBY mode. +//! +//! GPIO0 is configured as the LPM wakeup pin to trigger a +//! WAKEINT interrupt upon detection of a low pulse. +//! Initially, pull GPIO0 high externally. To wake device +//! from standby mode, pull GPIO0 low for at least (2+QUALSTDBY) +//! OSCLKS, then pull it high again. +//! +//! The example then wakes up the device from STANDBY using GPIO0. +//! GPIO0 wakes the device from STANDBY mode when a low pulse +//! (signal goes high->low->high)is detected on the pin. +//! This pin must be pulsed by an external agent for wakeup. +//! +//! As soon as GPIO0 goes high again after the pulse, the device +//! should wake up, and GPIO1 can be observed to toggle. +//! +//! \b External \b Connections \n +//! - To observe when device wakes from STANDBY mode, monitor +//! GPIO1 with an oscilloscope (set to 1 in WAKEINT ISR) +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +__interrupt void WAKE_ISR(void); // ISR for WAKEINT + +// +// Main +// +void main() +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + EALLOW; + GpioCtrlRegs.GPAPUD.all = 0; // Enable all Pull-ups + GpioCtrlRegs.GPBPUD.all = 0; + + // + // GPIO1 set in the ISR to indicate device woken up. + // + GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; + + GpioIntRegs.GPIOLPMSEL.bit.GPIO0 = 1; // Choose GPIO0 pin for wakeup + EDIS; + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.WAKEINT = &WAKE_ISR; + EDIS; + + // + // Step 4. Initialize all the Device Peripherals: + // Not applicable for this example. + // + + // + // Step 5. User specific code, enable interrupts + // + + // + // Enable CPU INT1 which is connected to WakeInt + // + IER |= M_INT1; + + // + // Enable WAKEINT in the PIE: Group 1 interrupt 8 + // + PieCtrlRegs.PIEIER1.bit.INTx8 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; + + // + // Enable global Interrupts + // + EINT; // Enable Global interrupt INTM + + // + // Choose qualification cycles in LPMCR0 register + // + + // + // The wakeup signal should be (2+QUALSTDBY) OSCCLKs wide. + // + SysCtrlRegs.LPMCR0.bit.QUALSTDBY = 0; + + // + // Write the LPM code value + // + EALLOW; + + // + // Only enter Standby mode when PLL is not in limp mode. + // + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) + { + SysCtrlRegs.LPMCR0.bit.LPM = 0x0001; // LPM mode = Standby + } + EDIS; + + // + // Force device into STANDBY + // + + // + // Device waits in IDLE until falling edge on GPIO0/XNMI pin + // wakes device from Standby mode. + // + __asm(" IDLE"); + + // + // Loop here after wake-up. + // + for(;;) + { + + } +} + +// +// ISR for WAKEINT - Will be executed when low pulse triggered on GPIO0 pin +// +__interrupt void +WAKE_ISR(void) +{ + // + // Toggle GPIO1 in the ISR - monitored with oscilloscope + // + GpioDataRegs.GPATOGGLE.bit.GPIO1 = 1; + PieCtrlRegs.PIEACK.bit.ACK1 = 1; +} + +// +// End of File +// + diff --git a/f2833x/examples/mcbsp_loopback/.ccsproject b/f2833x/examples/mcbsp_loopback/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/mcbsp_loopback/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/mcbsp_loopback/.cproject b/f2833x/examples/mcbsp_loopback/.cproject new file mode 100644 index 0000000..58073b0 --- /dev/null +++ b/f2833x/examples/mcbsp_loopback/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/mcbsp_loopback/.project b/f2833x/examples/mcbsp_loopback/.project new file mode 100644 index 0000000..7e0c28a --- /dev/null +++ b/f2833x/examples/mcbsp_loopback/.project @@ -0,0 +1,98 @@ + + + Example_2833xMcBSP_DLB + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_Mcbsp.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Mcbsp.c + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/mcbsp_loopback/Example_2833xMcBSP_DLB.c b/f2833x/examples/mcbsp_loopback/Example_2833xMcBSP_DLB.c new file mode 100644 index 0000000..5063009 --- /dev/null +++ b/f2833x/examples/mcbsp_loopback/Example_2833xMcBSP_DLB.c @@ -0,0 +1,393 @@ +//########################################################################### +// +// FILE: Example_2833xMcBSP_DLB.c +// +// TITLE: McBSP Digital Loop Back Example +// +//! \addtogroup f2833x_example_list +//!

McBSP Digital Loop Back (mcbsp_loopback)

+//! +//! This example performs digital loopback tests for the McBSP peripheral. +//! This example does not use interrupts. Instead, a polling +//! method is used to check the receive data. The incoming +//! data is checked for accuracy. If an error is found the error() +//! function is called and execution stops. +//! +//! \b Watch \b Variables \n +//! - sdata1 +//! - sdata2 +//! - rdata1 +//! - rdata2 +//! - rdata1_point +//! - rdata2_point +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines +// + +// +// Choose a word size. Uncomment one of the following lines +// +#define WORD_SIZE 8 // Run a loopback test in 8-bit mode +//#define WORD_SIZE 16 // Run a loopback test in 16-bit mode +//#define WORD_SIZE 32 // Run a loopback test in 32-bit mode + +// +// Function Prototypes +// +void mcbsp_init_dlb(void); +void mcbsp_xmit(int a, int b); +void error(void); + +// +// Globals +// +Uint16 sdata1 = 0x000; // Sent Data +Uint16 rdata1 = 0x000; // Received Data + +Uint16 sdata2 = 0x000; // Sent Data +Uint16 rdata2 = 0x000; // Received Data + +Uint16 rdata1_point; +Uint16 rdata2_point; + +Uint16 data_size; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + // For this example, only enable the GPIO for McBSP-A + InitMcbspaGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table + // + + // + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + data_size = WORD_SIZE; + + // + // Initialize and release peripheral (McBSP) from Reset. + // + mcbsp_init_dlb(); + + // + // Step 5. User specific code, enable interrupts + // + + // + // Run a loopback test in 8-bit mode + // + if(data_size == 8) + { + sdata2 = 0x0000; // value is a don't care for 8-bit mode + sdata1 = 0x0000; // 8-bit value to send + rdata2_point = 0x0000; // value is a don't care for 8-bit mode + rdata1_point = sdata1; + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + sdata1++; + sdata1 = sdata1 & 0x00FF; // Keep it to 8-bits + + // + // Check for receive + // + while(McbspaRegs.SPCR1.bit.RRDY == 0 ) + { + + } + + rdata1 = McbspaRegs.DRR1.all; // read DRR1 + if(rdata1 != rdata1_point) + { + error(); + } + rdata1_point++; + rdata1_point = rdata1_point & 0x00FF; // Keep it to 8-bits + + // + // Good place for a breakpoint + // Check: rdatax_point = sdatax + // rdata1 = sdata1 - 1 + // + __asm(" nop"); + } + } + + // + // Run a loopback test in 16-bit mode + // + else if(data_size == 16) + { + sdata2 = 0x0000; // value is a don't care for 16-bit mode + sdata1 = 0x0000; // 16-bit value to send + rdata2_point = 0x0000; // value is a don't care for 16-bit mode + rdata1_point = sdata1; + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + sdata1++; + + // + // Check for receive + // + while(McbspaRegs.SPCR1.bit.RRDY == 0 ) + { + + } + + rdata1 = McbspaRegs.DRR1.all; // read DRR1 + + if(rdata1 != rdata1_point) + { + error(); + } + rdata1_point++; + + // + // Good place for a breakpoint + // Check: rdatax_point = sdatax + // rdata1 = sdata1 - 1 + // + __asm(" nop"); + } + } + + // + // Run a loopback test in 16-bit mode + // + else if(data_size == 32) + { + sdata1 = 0x0000; + sdata2 = 0xFFFF; + rdata1_point = sdata1; + rdata2_point = sdata2; + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + sdata1++; + sdata2--; + + // + // Check for receive + // + while(McbspaRegs.SPCR1.bit.RRDY == 0 ) + { + + } + + rdata2 = McbspaRegs.DRR2.all; + rdata1 = McbspaRegs.DRR1.all; + if(rdata1 != rdata1_point) + { + error(); + } + if(rdata2 != rdata2_point) + { + error(); + } + rdata1_point++; + rdata2_point--; + + // + // Good place for a breakpoint + // Check: rdatax_point = sdatax + // rdata1 = sdata1 - 1 + // rdata2 = sdata2 + 1 + // + __asm(" nop"); + } + } +} + +// +// error - +// +void error(void) +{ + __asm(" ESTOP0"); // test failed!! Stop! + for (;;); +} + +// +// mcbsp_init_dlb - +// +void +mcbsp_init_dlb() +{ + // + // Reset FS generator, sample rate generator & transmitter + // + McbspaRegs.SPCR2.all=0x0000; + + McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + + // + // Enable loopback mode for test. Comment out for normal McBSP + // transfer mode. + // + McbspaRegs.SPCR1.bit.DLB = 1; + + McbspaRegs.MFFINT.all=0x0; // Disable all interrupts + + // + // Single-phase frame, 1 word/frame, No companding (Receive) + // + McbspaRegs.RCR2.all=0x0; + McbspaRegs.RCR1.all=0x0; + + // + // Single-phase frame, 1 word/frame, No companding (Transmit) + // + McbspaRegs.XCR2.all=0x0; + McbspaRegs.XCR1.all=0x0; + + // + // FSX generated internally, FSR derived from an external source + // + McbspaRegs.PCR.bit.FSXM = 1; + + // + // CLKX generated internally, CLKR derived from an external source + // + McbspaRegs.PCR.bit.CLKXM = 1; + + // + // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + // + McbspaRegs.SRGR2.bit.CLKSM = 1; + + McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + McbspaRegs.SRGR1.bit.CLKGDV = 1; // CLKG frequency = LSPCLK/(CLKGDV+1) + + delay_loop(); // Wait at least 2 SRG clock cycles + + // + // Initialize McBSP Data Length + // + if(data_size == 8) // Run a loopback test in 8-bit mode + { + InitMcbspa8bit(); + } + if(data_size == 16) // Run a loopback test in 16-bit mode + { + InitMcbspa16bit(); + } + if(data_size == 32) // Run a loopback test in 32-bit mode + { + InitMcbspa32bit(); + } + + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + delay_loop(); + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset +} + +// +// mcbsp_xmit - +// +void +mcbsp_xmit(int a, int b) +{ + McbspaRegs.DXR2.all=b; + McbspaRegs.DXR1.all=a; +} + +// +// End of File +// + diff --git a/f2833x/examples/mcbsp_loopback_dma/.ccsproject b/f2833x/examples/mcbsp_loopback_dma/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/mcbsp_loopback_dma/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/mcbsp_loopback_dma/.cproject b/f2833x/examples/mcbsp_loopback_dma/.cproject new file mode 100644 index 0000000..30eb458 --- /dev/null +++ b/f2833x/examples/mcbsp_loopback_dma/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/mcbsp_loopback_dma/.project b/f2833x/examples/mcbsp_loopback_dma/.project new file mode 100644 index 0000000..e4ccdaf --- /dev/null +++ b/f2833x/examples/mcbsp_loopback_dma/.project @@ -0,0 +1,98 @@ + + + Example_2833xMcBSP_DLB_DMA + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_Mcbsp.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Mcbsp.c + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.c b/f2833x/examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.c new file mode 100644 index 0000000..ca0bf30 --- /dev/null +++ b/f2833x/examples/mcbsp_loopback_dma/Example_2833xMcBSP_DLB_DMA.c @@ -0,0 +1,673 @@ +//########################################################################### +// +// FILE: Example_2833xMcBSP_DLB_DMA.c +// +// TITLE: McBSP Digital Loop Back with DMA Example +// +//! \addtogroup f2833x_example_list +//!

McBSP Digital Loop Back with DMA (mcbsp_loopback_dma)

+//! +//! This program is a McBSP example that uses the internal loopback of +//! the peripheral and utilizes the DMA to transfer data from one buffer +//! to the McBSP, and then from the McBSP to another buffer. +//! +//! Initially, sdata[] is filled with values from 0x0000- 0x007F. The DMA +//! moves the values in sdata[] one by one to the DXRx registers of the McBSP. +//! These values are transmitted and subsequently received by the McBSP. +//! Then, the DMA moves each data value to rdata[] as it is received by the +//! McBSP. +//! +//! By default for the McBSP examples, the McBSP sample rate generator (SRG) +//! input clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming SYSCLKOUT = +//! 150 MHz or 100 MHz respectively. If while testing, the SRG input frequency +//! is changed, the #define MCBSP_SRG_FREQ (150E6/4 or 100E6/4) in the Mcbsp.c +//! file must also be updated accordingly. This define is used to determine +//! the Mcbsp initialization delay after the SRG is enabled, which must be at +//! least 2 SRG clock cycles. +//! +//! \b Watch \b Variables \n +//! - sdata +//! - rdata +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines +// + +// +// Choose a word size. Uncomment one of the following lines +// +#define WORD_SIZE 8 // Run a loopback test in 8-bit mode +//#define WORD_SIZE 16 // Run a loopback test in 16-bit mode +//#define WORD_SIZE 32 // Run a loopback test in 32-bit mode + +// +// Function Prototypes +// +__interrupt void local_D_INTCH1_ISR(void); +__interrupt void local_D_INTCH2_ISR(void); +void mcbsp_init_dlb(void); +void init_dma(void); +void init_dma_32(void); +void start_dma(void); +void error(void); + +// +// Place sdata and rdata buffers in DMA-accessible RAM (L4 for this example) +// +#pragma DATA_SECTION(sdata, "DMARAML4") +#pragma DATA_SECTION(rdata, "DMARAML4") +Uint16 sdata[128]; // Sent Data +Uint16 rdata[128]; // Received Data +Uint16 data_size; // Word Length variable + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Setup only the GP I/O only for McBSP-A functionality + // + InitMcbspaGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.DINTCH1= &local_D_INTCH1_ISR; + PieVectTable.DINTCH2= &local_D_INTCH2_ISR; + EDIS; // Disable access to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code, enable interrupts + // + data_size = WORD_SIZE; + for (i=0; i<128; i++) + { + sdata[i] = i; // Fill sdata with values between 0 and 0x007F + rdata[i] = 0; // Initialize rdata to all 0x0000. + } + + if (data_size == 32) + { + init_dma_32(); // DMA Initialization for 32-bit transfers + } + else + { + // + // 1. When using DMA, initialize DMA with peripheral interrupts first. + // + init_dma(); + } + start_dma(); + + // + // 2. Then initialize and release peripheral (McBSP) from Reset. + // + mcbsp_init_dlb(); + + // + // Enable interrupts required for this example + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable PIE Group 7, INT 1 (DMA CH1) + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable PIE Group 7, INT 2 (DMA CH2) + + IER=0x40; // Enable CPU INT group 7 + EINT; // Enable Global Interrupts + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;); +} + +// +// Step 7. Insert all local Interrupt Service Routines (ISRs) and +// functions here: +// + +// +// error - +// +void +error(void) +{ + __asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + +// +// mcbsp_init_dlb - +// +void +mcbsp_init_dlb() +{ + // + // Reset FS generator, sample rate generator & transmitter + // + McbspaRegs.SPCR2.all=0x0000; + + McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word + + // + // Enable DLB mode. Comment out for non-DLB mode. + // + McbspaRegs.SPCR1.bit.DLB = 1; + + McbspaRegs.MFFINT.all=0x0; // Disable all interrupts + + // + // Single-phase frame, 1 word/frame, No companding (Receive) + // + McbspaRegs.RCR2.all=0x0; + McbspaRegs.RCR1.all=0x0; + + // + // Single-phase frame, 1 word/frame, No companding (Transmit) + // + McbspaRegs.XCR2.all=0x0; + McbspaRegs.XCR1.all=0x0; + + // + // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK) + // + McbspaRegs.SRGR2.bit.CLKSM = 1; + + McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods + + McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period + McbspaRegs.SRGR1.bit.CLKGDV = 0; // CLKG frequency = LSPCLK/(CLKGDV+1) + + // + // FSX generated internally, FSR derived from an external source + // + McbspaRegs.PCR.bit.FSXM = 1; + + // + // CLKX generated internally, CLKR derived from an external source + // + McbspaRegs.PCR.bit.CLKXM = 1; + + // + // Initialize McBSP Data Length + // + if(data_size == 8) // Run a loopback test in 8-bit mode + { + InitMcbspa8bit(); + } + if(data_size == 16) // Run a loopback test in 16-bit mode + { + InitMcbspa16bit(); + } + if(data_size == 32) // Run a loopback test in 32-bit mode + { + InitMcbspa32bit(); + } + + // + // Enable Sample rate generator + // + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + delay_loop(); // Wait at least 2 SRG clock cycles + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset +} + +// +// init_dma - DMA Initialization for data size <= 16-bit +// +void +init_dma() +{ + EALLOW; + + DmaRegs.DMACTRL.bit.HARDRESET = 1; + __asm(" NOP"); // Only 1 NOP needed per Design + DmaRegs.CH1.MODE.bit.CHINTE = 0; + + // + // Channel 1, McBSPA transmit + // + DmaRegs.CH1.BURST_SIZE.all = 0; // 1 word/burst + DmaRegs.CH1.SRC_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH1.DST_BURST_STEP = 0; // no effect when using 1 word/burst + + // + // Interrupt every frame (127 bursts/transfer) + // + DmaRegs.CH1.TRANSFER_SIZE = 127; + + // + // Move to next word in buffer after each word in a burst + // + DmaRegs.CH1.SRC_TRANSFER_STEP = 1; + + DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Don't move destination address + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0]; // Start address = buffer + + // + // Not needed unless using wrap function + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0]; + + // + // Start address = McBSPA DXR + // + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all; + + // + // Not needed unless using wrap function + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all; + + // + // Clear peripheral interrupt event flag + // + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; + + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + + // + // Put to maximum - don't want destination wrap + // + DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; + + // + // Put to maximum - don't want source wrap + // + DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; + DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + + // + // Peripheral interrupt select = McBSP MXSYNCA + // + DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA; + + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;// Clear any spurious interrupt flags + + // + // Channel 2, McBSPA Receive + // + DmaRegs.CH2.MODE.bit.CHINTE = 0; + DmaRegs.CH2.BURST_SIZE.all = 0; // 1 word/burst + DmaRegs.CH2.SRC_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH2.DST_BURST_STEP = 0; // no effect when using 1 word/burst + DmaRegs.CH2.TRANSFER_SIZE = 127; // Interrupt every 127 bursts/transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = 0; // Don't move source address + + // + // Move to next word in buffer after each word in a burst + // + DmaRegs.CH2.DST_TRANSFER_STEP = 1; + + // + // Start address = McBSPA DRR + // + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all; + + // + // Not needed unless using wrap function + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all; + + // + // Start address = Receive buffer (for McBSP-A) + // + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0]; + + // + // Not needed unless using wrap function + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0]; + + // + // Clear peripheral interrupt event flag + // + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + + // + // Put to maximum - don't want destination wrap + // + DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; + + // + // Put to maximum - don't want source wrap + // + DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; + DmaRegs.CH2.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH2.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH2.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + + // + // Peripheral interrupt select = McBSP MRSYNCA + // + DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA; + + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;// Clear any spurious interrupt flags + EDIS; +} + +// +// init_dma_32 - DMA Initialization for data size > 16-bit and <= 32-bit. +// +void +init_dma_32() +{ + EALLOW; + DmaRegs.DMACTRL.bit.HARDRESET = 1; + __asm(" NOP"); // Only 1 NOP needed per Design + + // + // Channel 1, McBSPA transmit + // + DmaRegs.CH1.BURST_SIZE.all = 1; // 2 word/burst + DmaRegs.CH1.SRC_BURST_STEP = 1; // increment 1 16-bit addr. btwn words + DmaRegs.CH1.DST_BURST_STEP = 1; // increment 1 16-bit addr. btwn words + DmaRegs.CH1.TRANSFER_SIZE = 63; // Interrupt every 63 bursts/transfer + + // + // Move to next word in buffer after each word in a burst + // + DmaRegs.CH1.SRC_TRANSFER_STEP = 1; + + DmaRegs.CH1.DST_TRANSFER_STEP = 0xFFFF; // Go back to DXR2 + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0]; // Start address = buffer + + // + // Not needed unless using wrap function + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0]; + + // + // Start address = McBSPA DXR2 + // + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; + + // + // Not needed unless using wrap function + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; + + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + + // + // Put to maximum - don't want destination wrapz + // + DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; + + // + // Put to maximum - don't want source wrap + // + DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; + DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal + DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal + DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + + // + // Peripheral interrupt select = McBSP MXSYNCA + // + DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA; + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; + + // + // Channel 2, McBSPA Receive + // + DmaRegs.CH2.BURST_SIZE.all = 1; // 2 words/burst + DmaRegs.CH2.SRC_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words + DmaRegs.CH2.DST_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words + DmaRegs.CH2.TRANSFER_SIZE = 63; // Interrupt every 63 bursts/transfer + DmaRegs.CH2.SRC_TRANSFER_STEP = 0xFFFF; // Decrement back to DRR2 + + // + // Move to next word in buffer after each word in a burst + // + DmaRegs.CH2.DST_TRANSFER_STEP = 1; + + // + // Start address = McBSPA DRR + // + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; + + // + // Not needed unless using wrap function + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; + + // + // Start address = Receive buffer (for McBSP-A) + // + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0]; + + // + // Not needed unless using wrap function + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0]; + + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear sync flag + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear sync error flag + + // + // Put to maximum - don't want destination wrap + // + DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; + + // + // Put to maximum - don't want source wrap + // + DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; + + DmaRegs.CH2.MODE.bit.CHINTE = 1; // Enable channel interrupt + DmaRegs.CH2.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer + DmaRegs.CH2.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event + + // + // Peripheral interrupt select = McBSP MRSYNCA + // + DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA; + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; + EDIS; +} + +// +// start_dma - +// +void +start_dma (void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; // Start DMA Transmit from McBSP-A + DmaRegs.CH2.CONTROL.bit.RUN = 1; // Start DMA Receive from McBSP-A + + EDIS; +} + +// +// local_D_INTCH1_ISR - DMA Ch1 (INT7.1) +// +__interrupt void +local_D_INTCH1_ISR(void) +{ + EALLOW; // NEED TO EXECUTE EALLOW INSIDE ISR !!! + + // + // Re-enable DMA CH1. Should be done every transfer + // + DmaRegs.CH1.CONTROL.bit.HALT = 1 ; + + // + // To receive more interrupts from this PIE group, acknowledge + // this interrupt + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + EDIS; + return; +} + +// +// local_D_INTCH2_ISR - DMA Ch2 (INT7.2) +// +__interrupt void +local_D_INTCH2_ISR(void) +{ + Uint16 i; + EALLOW; // NEED TO EXECUTE EALLOW INSIDE ISR !!! + + // + // Re-enable DMA CH2. Should be done every transfer + // + DmaRegs.CH2.CONTROL.bit.HALT = 1 ; + + // + // To receive more interrupts from this PIE group, acknowledge + // this interrupt + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + for (i=0; i<128; i++) + { + if(data_size == 8) + { + if( (rdata[i]&0x00FF) !=(sdata[i]&0x00FF)) + { + error( ); // Check for correct received data + } + } + + else if (data_size == 16) + { + if (rdata[i] != sdata[i]) + { + error(); // STOP if there is an error !! + } + } + + else if (data_size == 32) + { + if ((rdata[i])!=(sdata[i])) + { + error (); + } + } + } + EDIS; + return; +} + +// +// End of File +// + diff --git a/f2833x/examples/mcbsp_loopback_interrupts/.ccsproject b/f2833x/examples/mcbsp_loopback_interrupts/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/mcbsp_loopback_interrupts/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/mcbsp_loopback_interrupts/.cproject b/f2833x/examples/mcbsp_loopback_interrupts/.cproject new file mode 100644 index 0000000..418d512 --- /dev/null +++ b/f2833x/examples/mcbsp_loopback_interrupts/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/mcbsp_loopback_interrupts/.project b/f2833x/examples/mcbsp_loopback_interrupts/.project new file mode 100644 index 0000000..e398bf8 --- /dev/null +++ b/f2833x/examples/mcbsp_loopback_interrupts/.project @@ -0,0 +1,98 @@ + + + Example_2833xMcBSP_DLB_int + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_Mcbsp.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Mcbsp.c + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.c b/f2833x/examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.c new file mode 100644 index 0000000..2abe7da --- /dev/null +++ b/f2833x/examples/mcbsp_loopback_interrupts/Example_2833xMcBSP_DLB_int.c @@ -0,0 +1,285 @@ +//########################################################################### +// +// FILE: Example_2833xMcBSP_DLB_int.c +// +// TITLE: McBSP Digital Loop Back with Interrupts Example +// +//! \addtogroup f2833x_example_list +//!

McBSP Digital Loop Back with Interrupts(mcbsp_loopback_interrupts)

+//! +//! This program uses the internal loopback of +//! the peripheral. Both Rx and Tx interrupts are enabled. +//! +//! Incrementing values from 0x0000 to 0x00FF are being sent and received. +//! +//! This pattern is repeated forever. +//! +//! By default for the McBSP examples, the McBSP sample rate generator (SRG) +//! input clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming +//! SYSCLKOUT = 150 MHz or 100 MHz respectively. If while testing, the SRG +//! input frequency is changed, the #define MCBSP_SRG_FREQ (150E6/4 or 100E6/4) +//! in the Mcbsp.c file must also be updated accordingly. This define is used +//! to determine the Mcbsp initialization delay after the SRG is enabled, which +//! must be at least 2 SRG clock cycles. +//! +//! \b Watch \b Variables \n +//! - sdata +//! - rdata +//! - rdata_point +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +__interrupt void Mcbsp_TxINTA_ISR(void); +__interrupt void Mcbsp_RxINTA_ISR(void); +void mcbsp_init_dlb(void); +void error(void); + +// +// Globals +// +Uint16 sdata; // Sent Data +Uint16 rdata; // Received Data +Uint16 rdata_point; // Keep track of where we are in the data stream + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Setup only the GP I/O only for McBSP-A functionality + // + InitMcbspaGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // Allow access to EALLOW protected registers + PieVectTable.MRINTA= &Mcbsp_RxINTA_ISR; + PieVectTable.MXINTA= &Mcbsp_TxINTA_ISR; + EDIS; // Disable access to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + mcbsp_init_dlb(); // For this example, only initialize the Mcbsp + + // + // Step 5. User specific code, enable interrupts + // + sdata = 0; + rdata_point = sdata; + + // + // Enable interrupts required for this example + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER6.bit.INTx5=1; // Enable PIE Group 6, INT 5 + PieCtrlRegs.PIEIER6.bit.INTx6=1; // Enable PIE Group 6, INT 6 + IER=0x20; // Enable CPU INT6 + EINT; // Enable Global Interrupts + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;); +} + +// +// Step 7. Insert all local Interrupt Service Routines (ISRs) and +// functions here +// + +// +// error - +// +void +error(void) +{ + __asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + +// +// mcbsp_init_dlb - +// +void +mcbsp_init_dlb() +{ + // + // RESET MCBSP + // + McbspaRegs.SPCR2.bit.FRST=0; // Frame Sync generator reset + McbspaRegs.SPCR2.bit.GRST=0; // Sample Rate generator Reset + McbspaRegs.SPCR2.bit.XRST=0; // Transmitter reset + McbspaRegs.SPCR1.bit.RRST=0; // Receiver reset + + // + // Initialize McBSP Registers + // McBSP register settings for Digital loop back + // + McbspaRegs.SPCR2.all=0x0000; // XRST =0 + McbspaRegs.SPCR1.all=0x8000; // RRST =0, DLB enabled + McbspaRegs.RCR2.all=0x0001; // RDATDLY = 1 + McbspaRegs.RCR1.all=0x0; + McbspaRegs.XCR2.all=0x0001; // XDATDLY = 1 + McbspaRegs.XCR1.all=0x0; + + McbspaRegs.SRGR2.all=0x3140; + McbspaRegs.SRGR1.all=0x010f; + McbspaRegs.MCR2.all=0x0; + McbspaRegs.MCR1.all=0x0; + McbspaRegs.PCR.all=0x0A00; + + McbspaRegs.MFFINT.bit.XINT = 1; // Enable Transmit Interrupts + McbspaRegs.MFFINT.bit.RINT = 1; // Enable Receive Interrupts + + // + // Enable Sample rate generator + // + McbspaRegs.SPCR2.bit.GRST=1; + delay_loop(); // Wait at least 2 SRG clock cycles + + // + // Enable TX/RX unit + // + McbspaRegs.SPCR2.bit.XRST=1; + McbspaRegs.SPCR1.bit.RRST=1; + + // + // Frame Sync generator reset + // + McbspaRegs.SPCR2.bit.FRST=1; +} + +// +// Mcbsp_TxINTA_ISR - +// +__interrupt void +Mcbsp_TxINTA_ISR(void) +{ + McbspaRegs.DXR1.all= sdata; + sdata = (sdata+1)& 0x00FF ; + + // + // To receive more interrupts from this PIE group, acknowledge + // this interrupt + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; +} + +// +// Mcbsp_RxINTA_ISR - +// +__interrupt void +Mcbsp_RxINTA_ISR(void) +{ + rdata=McbspaRegs.DRR1.all; + + if (rdata != ( (rdata_point) & 0x00FF) ) + { + error(); + } + rdata_point = (rdata_point+1) & 0x00FF; + + // + // To receive more interrupts from this PIE group, acknowledge + // this interrupt + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; +} + +// +// End of File +// + diff --git a/f2833x/examples/mcbsp_spi_loopback/.ccsproject b/f2833x/examples/mcbsp_spi_loopback/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/mcbsp_spi_loopback/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/mcbsp_spi_loopback/.cproject b/f2833x/examples/mcbsp_spi_loopback/.cproject new file mode 100644 index 0000000..17b3fde --- /dev/null +++ b/f2833x/examples/mcbsp_spi_loopback/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/mcbsp_spi_loopback/.project b/f2833x/examples/mcbsp_spi_loopback/.project new file mode 100644 index 0000000..ca3f4f8 --- /dev/null +++ b/f2833x/examples/mcbsp_spi_loopback/.project @@ -0,0 +1,98 @@ + + + Example_2833xMcBSP_SPI_DLB + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_Mcbsp.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Mcbsp.c + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.c b/f2833x/examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.c new file mode 100644 index 0000000..0cdd948 --- /dev/null +++ b/f2833x/examples/mcbsp_spi_loopback/Example_2833xMcBSP_SPI_DLB.c @@ -0,0 +1,268 @@ +//########################################################################### +// +// FILE: Example_2833xMcBSP_SPI_DLB.c +// +// TITLE: McBSP Digital Loop Back using SPI Mode Example +// +//! \addtogroup f2833x_example_list +//!

McBSP Digital Loop Back using SPI Mode (mcbsp_spi_loopback)

+//! +//! This program will execute and transmit words until terminated by the user. +//! +//! By default for the McBSP examples, the McBSP sample rate generator (SRG) +//! input clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming SYSCLKOUT = +//! 150 MHz or 100 MHz respectively. If while testing, the SRG input frequency +//! is changed, the #define MCBSP_SRG_FREQ (CPU_SPD/4) in the Mcbsp.c file +//! must also be updated accordingly. This define is used to determine the +//! Mcbsp initialization delay after the SRG is enabled, which must be at least +//! 2 SRG clock cycles. +//! +//! \b Watch \b Variables \n +//! - sdata1 +//! - sdata2 +//! - rdata1 +//! - rdata2 +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +void init_mcbsp_spi(void); +void mcbsp_xmit(int a, int b); +void error(void); + +// +// Globals +// +Uint16 sdata1 = 0x000; // Sent Data +Uint16 rdata1 = 0x000; // Received Data + +Uint16 sdata2 = 0x000; // Sent Data +Uint16 rdata2 = 0x000; // Received Data + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // For this example, only enable the GPIO for McBSP-A + // + InitMcbspaGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code + // + init_mcbsp_spi(); + sdata1 = 0x55aa; + sdata2 = 0xaa55; + + // + // Main loop to transfer 32-bit words through MCBSP in + // SPI mode periodically + // + for(;;) + { + mcbsp_xmit(sdata1,sdata2); + + // + // Master waits until RX data is ready + // + while( McbspaRegs.SPCR1.bit.RRDY == 0 ) + { + + } + rdata2 = McbspaRegs.DRR2.all; // Read DRR2 first. + + // + // Then read DRR1 to complete receiving of data + // + rdata1 = McbspaRegs.DRR1.all; + + // + // Check that correct data is received. + // + if((rdata2 != sdata2)&&(rdata1 != sdata1)) + { + error(); + } + + delay_loop(); + sdata1^=0xFFFF; + sdata2^=0xFFFF; + __asm(" nop"); // Good place for a breakpoint + } +} + +// +// error - +// +void +error(void) +{ + __asm(" ESTOP0"); // test failed!! Stop! + for (;;); +} + +// +// init_mcbsp_spi - +// +void +init_mcbsp_spi() +{ + // + // McBSP-A register settings + // + + // + // Reset FS generator, sample rate generator & transmitter + // + McbspaRegs.SPCR2.all=0x0000; + + // + // Reset Receiver, Right justify word, Digital loopback dis. + // + McbspaRegs.SPCR1.all=0x0000; + + // + // (CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1) + // + McbspaRegs.PCR.all=0x0F08; + + McbspaRegs.SPCR1.bit.DLB = 1; + + // + // Together with CLKXP/CLKRP determines clocking scheme + // + McbspaRegs.SPCR1.bit.CLKSTP = 2; + + McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 rising edge no delay + McbspaRegs.PCR.bit.CLKRP = 0; + + // + // FSX setup time 1 in master mode. 0 for slave mode (Receive) + // + McbspaRegs.RCR2.bit.RDATDLY=01; + + // + // FSX setup time 1 in master mode. 0 for slave mode (Transmit) + // + McbspaRegs.XCR2.bit.XDATDLY=01; + + McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word + McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word + + McbspaRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 1 CLKG periods + McbspaRegs.SRGR1.all= 0x000F; // Frame Width = 1 CLKG period, CLKGDV=16 + + McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator + delay_loop(); // Wait at least 2 SRG clock cycles + McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset + McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset + McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset +} + +// +// mcbsp_xmit +// +void +mcbsp_xmit(int a, int b) +{ + McbspaRegs.DXR2.all=b; + McbspaRegs.DXR1.all=a; +} + +// +// End of File +// + diff --git a/f2833x/examples/pinmux/.ccsproject b/f2833x/examples/pinmux/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/pinmux/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/pinmux/.cproject b/f2833x/examples/pinmux/.cproject new file mode 100644 index 0000000..12c4779 --- /dev/null +++ b/f2833x/examples/pinmux/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/pinmux/.project b/f2833x/examples/pinmux/.project new file mode 100644 index 0000000..85c07bf --- /dev/null +++ b/f2833x/examples/pinmux/.project @@ -0,0 +1,98 @@ + + + Example_2833x_Pinmux + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_Spi.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Spi.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/pinmux/Example_2833x_Pinmux.c b/f2833x/examples/pinmux/Example_2833x_Pinmux.c new file mode 100644 index 0000000..826bed6 --- /dev/null +++ b/f2833x/examples/pinmux/Example_2833x_Pinmux.c @@ -0,0 +1,105 @@ +//########################################################################### +// +// FILE: Example_2833x_Pinmux.c +// +// TITLE: Empty Pinmux Project +// +//! \addtogroup f2833x_example_list +//!

Empty Pinmux

+// +//############################################################################# +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // + InitSysCtrl(); + + // + // Step 2. Initalize GPIO: + // + //InitGpio(); // Skipped for this example + + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // + InitPieVectTable(); + + + for(;;) + { + + } +} + +// +// End of File +// + diff --git a/f2833x/examples/pinmux/pinmux_176pgf.syscfg b/f2833x/examples/pinmux/pinmux_176pgf.syscfg new file mode 100644 index 0000000..e86df59 --- /dev/null +++ b/f2833x/examples/pinmux/pinmux_176pgf.syscfg @@ -0,0 +1,5 @@ +// These arguments were used when this file was generated. They will be automatically applied on subsequent loads +// via the GUI or CLI invocations. Run CLI with '--help' for additional information on how to override these arguments. +// @cliArgs --device "F2833x" --package "F2833x_176PGF" --part "F2833x_176PGF" +// @versions {"data":"2019083011","timestamp":"2019083011","tool":"1.2.952","templates":"2019083011"} + diff --git a/f2833x/examples/pinmux/pinmux_176zjz.syscfg b/f2833x/examples/pinmux/pinmux_176zjz.syscfg new file mode 100644 index 0000000..81bb5aa --- /dev/null +++ b/f2833x/examples/pinmux/pinmux_176zjz.syscfg @@ -0,0 +1,5 @@ +// These arguments were used when this file was generated. They will be automatically applied on subsequent loads +// via the GUI or CLI invocations. Run CLI with '--help' for additional information on how to override these arguments. +// @cliArgs --device "F2833x" --package "F2833x_176ZJZ" --part "F2833x_176ZJZ" +// @versions {"data":"2019083011","timestamp":"2019083011","tool":"1.2.952","templates":"2019083011"} + diff --git a/f2833x/examples/pinmux/pinmux_179zhh.syscfg b/f2833x/examples/pinmux/pinmux_179zhh.syscfg new file mode 100644 index 0000000..82268ef --- /dev/null +++ b/f2833x/examples/pinmux/pinmux_179zhh.syscfg @@ -0,0 +1,5 @@ +// These arguments were used when this file was generated. They will be automatically applied on subsequent loads +// via the GUI or CLI invocations. Run CLI with '--help' for additional information on how to override these arguments. +// @cliArgs --device "F2833x" --package "F2833x_179ZHH" --part "F2833x_179ZHH" +// @versions {"data":"2019083011","timestamp":"2019083011","tool":"1.2.952","templates":"2019083011"} + diff --git a/f2833x/examples/sci_autobaud/.ccsproject b/f2833x/examples/sci_autobaud/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/sci_autobaud/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/sci_autobaud/.cproject b/f2833x/examples/sci_autobaud/.cproject new file mode 100644 index 0000000..964d16a --- /dev/null +++ b/f2833x/examples/sci_autobaud/.cproject @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/sci_autobaud/.project b/f2833x/examples/sci_autobaud/.project new file mode 100644 index 0000000..d79ecc1 --- /dev/null +++ b/f2833x/examples/sci_autobaud/.project @@ -0,0 +1,98 @@ + + + Example_2833xSci_Autobaud + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_Sci.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Sci.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/sci_autobaud/Example_2833xSci_Autobaud.c b/f2833x/examples/sci_autobaud/Example_2833xSci_Autobaud.c new file mode 100644 index 0000000..be966bd --- /dev/null +++ b/f2833x/examples/sci_autobaud/Example_2833xSci_Autobaud.c @@ -0,0 +1,479 @@ +//########################################################################### +// +// FILE: Example_2833xSci_Autobaud.c +// +// TITLE: SCI Autobaud Example +// +//! \addtogroup f2833x_example_list +//!

SCI Autobaud (sci_autobaud)

+//! +//! This test will perform autobaud lock at a variety of baud rates, including +//! very high baud rates. +//! +//! For this test to properly run, connect the SCI-A pins to the +//! SCI-B pins without going through a transceiver. +//! At higher baud rates, the slew rate of the incoming data bits can be +//! affected by transceiver and connector performance. This slew rate may +//! limit reliable autobaud detection at higher baud rates. +//! +//! SCIA: Slave, autobaud locks, receives characters and +//! echos them back to the host. Uses the RX interrupt +//! to receive characters. +//! +//! SCIB: Host, known baud rate, sends characters to the slave +//! and checks that they are echoed back. +//! +//! \b External \b Connections \n +//! - SCITXDA is on GPIO29 +//! - SCIRXDB is on GPIO19 +//! - SCIRXDA is on GPIO28 +//! - SCITXDB is on GPIO18 +//! - Connect GPIO29 to GPIO19 +//! - Connect GPIO28 to GPIO18 +//! +//! \b Watch \b Variables \n +//! - BRRVal - current BRR value used for SCIB +//! - ReceivedAChar - character received by SCIA +//! - ReceivedBChar - character received by SCIB +//! - SendChar - character being sent by SCIB +//! - SciaRegs.SCILBAUD - SCIA baud register set by autobaud lock +//! - SciaRegs.SCIHBAUD - SCIA baud register set by autobaud lock +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines +// + +// +// Amount BRR will be incremented between each autobaud lock +// +#define BAUDSTEP 100 + +// +// Function Prototypes +// +void scia_init(void); +void scib_init(void); +void scia_xmit(int a); +void scib_xmit(int a); +void scia_AutobaudLock(void); +void error(); +__interrupt void rxaint_isr(void); + +// +// Globals +// +Uint16 LoopCount; +//Uint16 xmitCount; +Uint16 ReceivedCount; +Uint16 ErrorCount; +Uint16 SendChar; +Uint16 ReceivedAChar; // scia received character +Uint16 ReceivedBChar; // scib received character +Uint16 BRRVal; +Uint16 Buff[10] = {0x55, 0xAA, 0xF0, 0x0F, 0x00, 0xFF, 0xF5, 0x5F, 0xA5, 0x5A}; + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + InitSciGpio(); + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.SCIRXINTA = &rxaint_isr; + EDIS; // This is needed to disable write to EALLOW protected register + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + scia_init(); // Initialize SCIA + scib_init(); // Initialize SCIB + + // + // Step 5. User specific code, enable interrupts + // + LoopCount = 0; + ErrorCount = 0; + + // + // Enable interrupts + // + PieCtrlRegs.PIEIER9.all = 0x0001; // Enable all SCIA RXINT interrupt + IER |= 0x0100; // enable PIEIER9, and INT9 + EINT; + + // + // Start with BRR = 1, work through each baud rate setting + // incrementing BRR by BAUDSTEP + // + for (BRRVal = 0x0000; BRRVal < (Uint32)0xFFFF; BRRVal+=BAUDSTEP) + { + // + // SCIB has a known baud rate. SCIA will autobaud to match + // + ScibRegs.SCIHBAUD = (BRRVal >> 8); + ScibRegs.SCILBAUD = (BRRVal); + + // + // Initiate an autobaud lock with scia. Check + // returned character against baud lock character 'A' + // + scia_AutobaudLock(); + while(ScibRegs.SCIRXST.bit.RXRDY != 1) + { + + } + ReceivedBChar = 0; + ReceivedBChar = ScibRegs.SCIRXBUF.bit.RXDT; + if(ReceivedBChar != 'A') + { + error(0); + } + + // + // Send/echoback characters + // 55 AA F0 0F 00 FF F5 5F A5 5A + // + for(i= 0; i<=9; i++) + { + SendChar = Buff[i]; + scib_xmit(SendChar); // Initiate interrupts and xmit data in isr + + // + // Wait to get the character back and check against the + // sent character. + // + while(ScibRegs.SCIRXST.bit.RXRDY != 1) + { + __asm(" NOP"); + } + ReceivedBChar = 0; + ReceivedBChar = ScibRegs.SCIRXBUF.bit.RXDT; + + if(ReceivedBChar != SendChar) + { + error(1); + } + } + } + + // + // Stop here, no more + // + for(;;) + { + __asm(" NOP"); + } +} + +// +// rxaint_isr - ISR for PIE INT9.1 Connected to RXAINT SCI-A +// +__interrupt void +rxaint_isr(void) +{ + // + // Insert ISR Code here + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // If autobaud detected, we must clear CDC + // + if(SciaRegs.SCIFFCT.bit.ABD == 1) + { + SciaRegs.SCIFFCT.bit.ABDCLR = 1; + SciaRegs.SCIFFCT.bit.CDC = 0; + + // + // Check received character - should be 'A' + // + ReceivedAChar = 0; + ReceivedAChar = SciaRegs.SCIRXBUF.all; + + if(ReceivedAChar != 'A') + { + error(2); + } + else + { + scia_xmit(ReceivedAChar); + } + } + + // + // This was not autobaud detect + // + else + { + // + // Check received character against sendchar + // + ReceivedAChar = 0; + ReceivedAChar = SciaRegs.SCIRXBUF.all; + + if(ReceivedAChar != SendChar) + { + error(3); + } + else + { + scia_xmit(ReceivedAChar); + } + } + + SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // clear Receive interrupt flag + ReceivedCount++; +} + +// +// error - +// +void +error() +{ + ErrorCount++; + __asm(" ESTOP0"); // Uncomment to stop the test here + for (;;); +} + +// +// scia_init - SCIA 8-bit word, baud rate 0x000F, default, 1 STOP bit, +// no parity +// +void +scia_init() +{ + // + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + // + + // + // Reset FIFO's + // + SciaRegs.SCIFFTX.all=0x8000; + + // + // 1 stop bit, No loopback, No parity,8 char bits, async mode, + // idle-line protocol + // + SciaRegs.SCICCR.all =0x0007; + + // + // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE + // + SciaRegs.SCICTL1.all =0x0003; + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset +} + +// +// scib_init - SCIB 8-bit word, baud rate 0x000F, default, +// 1 STOP bit, no parity +// +void +scib_init() +{ + // + // Reset FIFO's + // + ScibRegs.SCIFFTX.all=0x8000; + + // + // 1 stop bit, No parity, 8-bit character, No loopback + // + ScibRegs.SCICCR.all = 0x0007; + + // + // Enable TX, RX, Use internal SCICLK + // + ScibRegs.SCICTL1.all = 0x0003; + + // + // Disable RxErr, Sleep, TX Wake, Disable Rx Interrupt, Tx Interrupt + // + ScibRegs.SCICTL2.all = 0x0000; + + // + // Relinquish SCI-A from reset + // + ScibRegs.SCICTL1.all = 0x0023; + + return; +} + +// +// scia_xmit - Transmit a character from the SCI-A' +// +void +scia_xmit(int a) +{ + SciaRegs.SCITXBUF=a; +} + +// +// scib_xmit - Transmit a character from the SCI-B' +// +void +scib_xmit(int a) +{ + ScibRegs.SCITXBUF=a; +} + +// +// scia_AutobaudLock - Perform autobaud lock with the host. Note that if +// autobaud never occurs the program will hang in this routine as there is +// no timeout mechanism included. +// +void +scia_AutobaudLock() +{ + SciaRegs.SCICTL1.bit.SWRESET = 0; + SciaRegs.SCICTL1.bit.SWRESET = 1; + + // + // Must prime baud register with >= 1 + // + SciaRegs.SCIHBAUD = 0; + SciaRegs.SCILBAUD = 1; + + // + // Prepare for autobaud detection + // Make sure the ABD bit is clear by writing a 1 to ABDCLR + // Set the CDC bit to enable autobaud detection + // + SciaRegs.SCIFFCT.bit.ABDCLR = 1; + SciaRegs.SCIFFCT.bit.CDC = 1; + + // + // Wait until we correctly read an + // 'A' or 'a' and lock + // + // As long as Autobaud calibration is enabled (CDC = 1), + // SCI-B (host) will continue transmitting 'A'. This will + // continue until interrupted by the SCI-A RX ISR, where + // SCI-A RXBUF receives 'A', autobaud-locks (ABDCLR=1 + // CDC=0),and returns an 'A' back to the host. Then control + // is returned to this loop and the loop is exited. + // + // NOTE: ABD will become set sometime between + // scib_xmit and the DELAY_US loop, and + // the SCI-A RX ISR will be triggered. + // Upon returning and reaching the if-statement, + // ABD will have been cleared again by the ISR. + // + + while(SciaRegs.SCIFFCT.bit.CDC== 1) + { + // + // Note the lower the baud rate the longer + // this delay has to be to allow the other end + // to echo back a character (about 4 characters long) + // Make this really long since we are going through all + // the baud rates. + // + DELAY_US(280000L); + + if(SciaRegs.SCIFFCT.bit.CDC == 1) + { + + } + scib_xmit('A'); // host transmits 'A' + } + return; +} + +// +// End of File +// + diff --git a/f2833x/examples/sci_echoback/.ccsproject b/f2833x/examples/sci_echoback/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/sci_echoback/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/sci_echoback/.cproject b/f2833x/examples/sci_echoback/.cproject new file mode 100644 index 0000000..5dba4f9 --- /dev/null +++ b/f2833x/examples/sci_echoback/.cproject @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/sci_echoback/.project b/f2833x/examples/sci_echoback/.project new file mode 100644 index 0000000..acbf79d --- /dev/null +++ b/f2833x/examples/sci_echoback/.project @@ -0,0 +1,98 @@ + + + Example_2833xSci_Echoback + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_Sci.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Sci.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/sci_echoback/Example_2833xSci_Echoback.c b/f2833x/examples/sci_echoback/Example_2833xSci_Echoback.c new file mode 100644 index 0000000..45da45d --- /dev/null +++ b/f2833x/examples/sci_echoback/Example_2833xSci_Echoback.c @@ -0,0 +1,290 @@ +//########################################################################### +// +// FILE: Example_2833xSci_Echoback.c +// +// TITLE: SCI Echo Back Example +// +//! \addtogroup f2833x_example_list +//!

SCI Echo Back (sci_echoback)

+//! +//! This test receives and echo-backs data through the SCI-A port. +//! +//! The PC application 'hypterterminal' can be used to view the data +//! from the SCI and to send information to the SCI. Characters received +//! by the SCI port are sent back to the host. +//! +//! \b Running \b the \b Application +//! -# Configure hyperterminal: +//! Use the included hyperterminal configuration file SCI_96.ht. +//! To load this configuration in hyperterminal +//! -# Open hyperterminal +//! -# Go to file->open +//! -# Browse to the location of the project and +//! select the SCI_96.ht file. +//! -# Check the COM port. +//! The configuration file is currently setup for COM1. +//! If this is not correct, disconnect (Call->Disconnect) +//! Open the File-Properties dialog and select the correct COM port. +//! -# Connect hyperterminal Call->Call +//! and then start the 2833x SCI echoback program execution. +//! -# The program will print out a greeting and then ask you to +//! enter a character which it will echo back to hyperterminal. +//! +//! As is, the program configures SCI-A for 9600 baud with +//! SYSCLKOUT = 150MHz and LSPCLK = 37.5 MHz +//! or SYSCLKOUT = 100MHz and LSPCLK = 25.0 Mhz +//! +//! \b Watch \b Variables \n +//! - LoopCount - Number of characters sent +//! - ErrorCount +//! +//! \b External \b Connections \n +//! Connect the SCI-A port to a PC via a transceiver and cable. +//! - GPIO28 is SCI_A-RXD (Connect to Pin3, PC-TX, of serial DB9 cable) +//! - GPIO29 is SCI_A-TXD (Connect to Pin2, PC-RX, of serial DB9 cable) +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +void scia_echoback_init(void); +void scia_fifo_init(void); +void scia_xmit(int a); +void scia_msg(char *msg); + +// +// Globals +// +Uint16 LoopCount; +Uint16 ErrorCount; + +// +// Main +// +void main(void) +{ + Uint16 ReceivedChar; + char *msg; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); Skipped for this example + + // + // For this example, only init the pins for the SCI-A port. + // This function is found in the DSP2833x_Sci.c file. + // + InitSciaGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code + // + LoopCount = 0; + ErrorCount = 0; + + scia_fifo_init(); // Initialize the SCI FIFO + scia_echoback_init(); // Initialize SCI for echoback + + msg = "\r\n\n\nHello World!\0"; + scia_msg(msg); + + msg = "\r\nYou will enter a character, and the DSP will echo \ + it back! \n\0"; + scia_msg(msg); + + for(;;) + { + msg = "\r\nEnter a character: \0"; + scia_msg(msg); + + // + // Wait for inc character + // + while(SciaRegs.SCIFFRX.bit.RXFFST !=1) + { + // + // wait for XRDY =1 for empty state + // + } + + // + // Get character + // + ReceivedChar = SciaRegs.SCIRXBUF.all; + + // + // Echo character back + // + msg = " You sent: \0"; + scia_msg(msg); + scia_xmit(ReceivedChar); + + LoopCount++; + } +} + +// +// scia_echoback_init - Test 1,SCIA DLB, 8-bit word, baud rate 0x000F, +// default, 1 STOP bit, no parity +// +void +scia_echoback_init() +{ + // + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + // + + // 1 stop bit, No loopback, No parity,8 char bits, + // async mode, idle-line protocol + // + SciaRegs.SCICCR.all =0x0007; + + // + // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + // + SciaRegs.SCICTL1.all =0x0003; + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.TXINTENA =0; + SciaRegs.SCICTL2.bit.RXBKINTENA =0; +#if (CPU_FRQ_150MHZ) + SciaRegs.SCIHBAUD =0x0001; // 9600 baud @LSPCLK = 37.5MHz. + SciaRegs.SCILBAUD =0x00E7; +#endif +#if (CPU_FRQ_100MHZ) + SciaRegs.SCIHBAUD =0x0001; // 9600 baud @LSPCLK = 20MHz. + SciaRegs.SCILBAUD =0x0044; +#endif + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset +} + +// +// scia_xmit - Transmit a character from the SCI +// +void +scia_xmit(int a) +{ + while (SciaRegs.SCIFFTX.bit.TXFFST != 0) + { + + } + SciaRegs.SCITXBUF=a; +} + +// +// scia_msg - +// +void +scia_msg(char * msg) +{ + int i; + i = 0; + while(msg[i] != '\0') + { + scia_xmit(msg[i]); + i++; + } +} + +// +// scia_fifo_init - Initialize the SCI FIFO +// +void +scia_fifo_init() +{ + SciaRegs.SCIFFTX.all=0xE040; + SciaRegs.SCIFFRX.all=0x204f; + SciaRegs.SCIFFCT.all=0x0; +} + +// +// End of File +// + diff --git a/f2833x/examples/sci_echoback/SCI_96.ht b/f2833x/examples/sci_echoback/SCI_96.ht new file mode 100644 index 0000000..fbc4e44 Binary files /dev/null and b/f2833x/examples/sci_echoback/SCI_96.ht differ diff --git a/f2833x/examples/scia_loopback/.ccsproject b/f2833x/examples/scia_loopback/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/scia_loopback/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/scia_loopback/.cproject b/f2833x/examples/scia_loopback/.cproject new file mode 100644 index 0000000..42dc1fa --- /dev/null +++ b/f2833x/examples/scia_loopback/.cproject @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/scia_loopback/.project b/f2833x/examples/scia_loopback/.project new file mode 100644 index 0000000..e9ca439 --- /dev/null +++ b/f2833x/examples/scia_loopback/.project @@ -0,0 +1,98 @@ + + + Example_2833xScia_FFDLB + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_Sci.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Sci.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/scia_loopback/Example_2833xScia_FFDLB.c b/f2833x/examples/scia_loopback/Example_2833xScia_FFDLB.c new file mode 100644 index 0000000..4410549 --- /dev/null +++ b/f2833x/examples/scia_loopback/Example_2833xScia_FFDLB.c @@ -0,0 +1,277 @@ +//########################################################################### +// +// FILE: Example_2833xSci_FFDLB.c +// +// TITLE: SCI Digital Loop Back Example +// +//! \addtogroup f2833x_example_list +//!

SCI Digital Loop Back (scia_loopback)

+//! +//! This program uses the internal loop back test mode of the peripheral. +//! Other then boot mode pin configuration, no other hardware configuration +//! is required. +//! +//! This test uses the loopback test mode of the SCI module to send +//! characters starting with 0x00 through 0xFF. The test will send +//! a character and then check the receive buffer for a correct match. +//! +//! \b Watch \b Variables \n +//! - LoopCount - Number of characters sent +//! - ErrorCount - Number of errors detected +//! - SendChar - Character sent +//! - ReceivedChar - Character received +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +void scia_loopback_init(void); +void scia_fifo_init(void); +void scia_xmit(int a); +void error(); +__interrupt void scia_rx_isr(void); +__interrupt void scia_tx_isr(void); + +// +// Globals +// +Uint16 LoopCount; +Uint16 ErrorCount; + +// +// Main +// +void main(void) +{ + Uint16 SendChar; + Uint16 ReceivedChar; + + // + // Step 1. Initialize System Control registers, PLL, WatchDog, + // Clocks to default state: + // This function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Select GPIO for the device or for the specific application: + // This function is found in the DSP2833x_Gpio.c file. + // + + // + // skip this as this is example selects the I/O for SCI-A in this + // file itself + // + // InitGpio(); + InitSciGpio(); + + // + // Step 3. Initialize PIE vector table: + // The PIE vector table is initialized with pointers to shell Interrupt + // Service Routines (ISR). The shell routines are found in + // DSP2833x_DefaultIsr.c. Insert user specific ISR code in the + // appropriate shell ISR routine in the DSP28_DefaultIsr.c file. + // + + // + // Disable and clear all CPU interrupts + // + DINT; + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize Pie Control Registers To Default State: + // This function is found in the DSP2833x_PieCtrl.c file. + // + // InitPieCtrl(); PIE is not used for this example + + // + // Initialize the PIE Vector Table To a Known State: + // This function is found in DSP2833x_PieVect.c. + // This function populates the PIE vector table with pointers + // to the shell ISR functions found in DSP2833x_DefaultIsr.c. + // + InitPieVectTable(); + + // + // Enable CPU and PIE interrupts + // This example function is found in the DSP2833x_PieCtrl.c file. + // + EnableInterrupts(); + + // + // Step 4. Initialize all the Device Peripherals to a known state: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); skip this for SCI tests + + // + // Step 5. User specific functions, Reassign vectors (optional), + // Enable Interrupts: + // + LoopCount = 0; + ErrorCount = 0; + + scia_fifo_init(); // Initialize the SCI FIFO + scia_loopback_init(); // Initialize SCI for digital loop back + + // + // Note: Autobaud lock is not required for this example + // + + // + // Send a character starting with 0 + // + SendChar = 0; + + // + // Step 6. Send Characters forever starting with 0x00 and going through + // 0xFF. After sending each, check the receive buffer for the correct + // value + // + for(;;) + { + scia_xmit(SendChar); + + // + // wait for RRDY/RXFFST =1 for 1 data available in FIFO + // + while(SciaRegs.SCIFFRX.bit.RXFFST !=1) + { + + } + + // + // Check received character + // + ReceivedChar = SciaRegs.SCIRXBUF.all; + if(ReceivedChar != SendChar) + { + error(); + } + + // + // Move to the next character and repeat the test + // + SendChar++; + + // + // Limit the character to 8-bits + // + SendChar &= 0x00FF; + LoopCount++; + } +} + +// +// Step 7. Insert all local Interrupt Service Routines (ISRs) and +// functions here: +// + +// +// error - +// +void +error() +{ + ErrorCount++; + //__asm(" ESTOP0"); // Uncomment to stop the test here + //for (;;); +} + +// +// scia_loopback_init - Test 1, SCIA DLB, 8-bit word, baud rate 0x000F, +// default, 1 STOP bit, no parity +// +void +scia_loopback_init() +{ + // + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + // + + // + // 1 stop bit, No loopback, No parity,8 char bits, async mode, + // idle-line protocol + // + SciaRegs.SCICCR.all =0x0007; + + // + // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE + // + SciaRegs.SCICTL1.all =0x0003; + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.TXINTENA =0; + SciaRegs.SCICTL2.bit.RXBKINTENA =0; + SciaRegs.SCIHBAUD =0x0000; + SciaRegs.SCILBAUD =0x000F; + SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset +} + +// +// scia_xmit - Transmit a character from the SCI +// +void +scia_xmit(int a) +{ + SciaRegs.SCITXBUF=a; +} + +// +// scia_fifo_init - Initialize the SCI FIFO +// +void +scia_fifo_init() +{ + SciaRegs.SCIFFTX.all=0xE040; + SciaRegs.SCIFFRX.all=0x204f; + SciaRegs.SCIFFCT.all=0x0; +} + +// +// End of File +// + diff --git a/f2833x/examples/scia_loopback_interrupts/.ccsproject b/f2833x/examples/scia_loopback_interrupts/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/scia_loopback_interrupts/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/scia_loopback_interrupts/.cproject b/f2833x/examples/scia_loopback_interrupts/.cproject new file mode 100644 index 0000000..9fca750 --- /dev/null +++ b/f2833x/examples/scia_loopback_interrupts/.cproject @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/scia_loopback_interrupts/.project b/f2833x/examples/scia_loopback_interrupts/.project new file mode 100644 index 0000000..c2a049d --- /dev/null +++ b/f2833x/examples/scia_loopback_interrupts/.project @@ -0,0 +1,98 @@ + + + Example_2833xSci_FFDLB_int + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_Sci.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Sci.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.c b/f2833x/examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.c new file mode 100644 index 0000000..585d27c --- /dev/null +++ b/f2833x/examples/scia_loopback_interrupts/Example_2833xSci_FFDLB_int.c @@ -0,0 +1,395 @@ +//########################################################################### +// +// FILE: Example_2833xSci_FFDLB_int.c +// +// TITLE: SCI Digital Loop Back with Interrupts Example +// +//! \addtogroup f2833x_example_list +//!

SCI Digital Loop Back with Interrupts (scia_loopback_interrupts)

+//! +//! This program uses the internal loop back test mode of the peripheral. +//! Other then boot mode pin configuration, no other hardware configuration +//! is required. Both interrupts and the SCI FIFOs are used. +//! +//! A stream of data is sent and then compared to the received stream. +//! +//! The SCI-A sent data looks like this: \n +//! 00 01 02 03 04 05 06 07 \n +//! 01 02 03 04 05 06 07 08 \n +//! 02 03 04 05 06 07 08 09 \n +//! .... \n +//! FE FF 00 01 02 03 04 05 \n +//! FF 00 01 02 03 04 05 06 \n +//! etc.. +//! +//! The SCI-B sent data looks like this: \n +//! FF FE FD FC FB FA F9 F8 \n +//! FE FD FC FB FA F9 F8 F7 \n +//! FD FC FB FA F9 F8 F7 F6 \n +//! .... \n +//! 01 00 FF FE FD FC FB FA \n +//! 00 FF FE FD FC FB FA F9 \n +//! etc.. +//! +//! Both patterns are repeated forever. +//! +//! \b Watch \b Variables \n +//! - sdataA, sdataB - Data to send +//! - rdataA, rdataB - Received data +//! - rdata_pointA, rdata_pointB - Used to keep track of the last position in +//! the receive stream for error checking +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Defines +// +#define CPU_FREQ (Uint32)150E6 +#define LSPCLK_FREQ (Uint32)(CPU_FREQ / 4) +#define SCI_FREQ (Uint32)100E3 +#define SCI_PRD (Uint16)((LSPCLK_FREQ / (SCI_FREQ * 8)) - 1) + +// +// Function Prototypes +// +__interrupt void sciaTxFifoIsr(void); +__interrupt void sciaRxFifoIsr(void); +__interrupt void scibTxFifoIsr(void); +__interrupt void scibRxFifoIsr(void); +void scia_fifo_init(void); +void scib_fifo_init(void); +void error(void); + +// +// Globals +// +Uint16 sdataA[8]; // Send data for SCI-A +Uint16 sdataB[8]; // Send data for SCI-B +Uint16 rdataA[8]; // Received data for SCI-A +Uint16 rdataB[8]; // Received data for SCI-A +Uint16 rdata_pointA; // Used for checking the received data +Uint16 rdata_pointB; + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); + + // + // Setup only the GP I/O only for SCI-A and SCI-B functionality + // This function is found in DSP2833x_Sci.c + // + InitSciGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.SCIRXINTA = &sciaRxFifoIsr; + PieVectTable.SCITXINTA = &sciaTxFifoIsr; + PieVectTable.SCIRXINTB = &scibRxFifoIsr; + PieVectTable.SCITXINTB = &scibTxFifoIsr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + scia_fifo_init(); // Init SCI-A + scib_fifo_init(); // Init SCI-B + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Init send data. After each transmission this data will be updated for + // the next transmission + // + for(i = 0; i<8; i++) + { + sdataA[i] = i; + } + + for(i = 0; i<8; i++) + { + sdataB[i] = 0xFF - i; + } + + rdata_pointA = sdataA[0]; + rdata_pointB = sdataB[0]; + + // + // Enable interrupts required for this example + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, int1 + PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2 + PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3 + PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4 + IER = 0x100; // Enable CPU INT + EINT; + + // + // Step 6. IDLE loop. Just sit and loop forever (optional): + // + for(;;); +} + +// +// errror - +// +void +error(void) +{ + __asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + +// +// sciaTxFifoIsr - +// +__interrupt void +sciaTxFifoIsr(void) +{ + Uint16 i; + for(i=0; i< 8; i++) + { + SciaRegs.SCITXBUF=sdataA[i]; // Send data + } + + for(i=0; i< 8; i++) // Increment send data for next cycle + { + sdataA[i] = (sdataA[i]+1) & 0x00FF; + } + + SciaRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear SCI Interrupt flag + PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK +} + +// +// sciaRxFifoIsr - +// +__interrupt void +sciaRxFifoIsr(void) +{ + Uint16 i; + for(i=0;i<8;i++) + { + rdataA[i]=SciaRegs.SCIRXBUF.all; // Read data + } + + for(i=0;i<8;i++) // Check received data + { + if(rdataA[i] != ( (rdata_pointA+i) & 0x00FF) ) + { + error(); + } + } + + rdata_pointA = (rdata_pointA+1) & 0x00FF; + + SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag + SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag + + PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack +} + +// +// scia_fifo_init - +// +void +scia_fifo_init() +{ + // + // 1 stop bit, No loopback, No parity,8 char bits, async mode, + // idle-line protocol + // + SciaRegs.SCICCR.all =0x0007; + + // + // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE + // + SciaRegs.SCICTL1.all =0x0003; + SciaRegs.SCICTL2.bit.TXINTENA =1; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + SciaRegs.SCIHBAUD = SCI_PRD >> 8; + SciaRegs.SCILBAUD = SCI_PRD; + SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back + SciaRegs.SCIFFTX.all=0xC028; + SciaRegs.SCIFFRX.all=0x0028; + SciaRegs.SCIFFCT.all=0x00; + + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1; + SciaRegs.SCIFFRX.bit.RXFIFORESET=1; +} + +// +// scibTxFifoIsr - +// +__interrupt void +scibTxFifoIsr(void) +{ + Uint16 i; + for(i=0; i< 8; i++) + { + ScibRegs.SCITXBUF=sdataB[i]; // Send data + } + + for(i=0; i< 8; i++) // Increment send data for next cycle + { + sdataB[i] = (sdataB[i]-1) & 0x00FF; + } + + ScibRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear Interrupt flag + PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK +} + +// +// scibRxFifoIsr - +// +__interrupt void +scibRxFifoIsr(void) +{ + Uint16 i; + for(i=0;i<8;i++) + { + rdataB[i]=ScibRegs.SCIRXBUF.all; // Read data + } + for(i=0;i<8;i++) // Check received data + { + if(rdataB[i] != ( (rdata_pointB-i) & 0x00FF) ) + { + error(); + } + } + rdata_pointB = (rdata_pointB-1) & 0x00FF; + + ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag + ScibRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag + PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack +} + +// +// scib_fifo_init - +// +void +scib_fifo_init() +{ + // + // 1 stop bit, No loopback, No parity,8 char bits, + // async mode, idle-line protocol + // + ScibRegs.SCICCR.all =0x0007; + + // + // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + // + ScibRegs.SCICTL1.all =0x0003; + ScibRegs.SCICTL2.bit.TXINTENA =1; + ScibRegs.SCICTL2.bit.RXBKINTENA =1; + ScibRegs.SCIHBAUD =0x0000; + ScibRegs.SCILBAUD =SCI_PRD; + ScibRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back + ScibRegs.SCIFFTX.all=0xC028; + ScibRegs.SCIFFRX.all=0x0028; + ScibRegs.SCIFFCT.all=0x00; + + ScibRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1; + ScibRegs.SCIFFRX.bit.RXFIFORESET=1; +} + +// +// End of File +// + diff --git a/f2833x/examples/spi_loopback/.ccsproject b/f2833x/examples/spi_loopback/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/spi_loopback/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/spi_loopback/.cproject b/f2833x/examples/spi_loopback/.cproject new file mode 100644 index 0000000..f96674a --- /dev/null +++ b/f2833x/examples/spi_loopback/.cproject @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/spi_loopback/.project b/f2833x/examples/spi_loopback/.project new file mode 100644 index 0000000..831b2a8 --- /dev/null +++ b/f2833x/examples/spi_loopback/.project @@ -0,0 +1,98 @@ + + + Example_2833xSpi_FFDLB + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_Spi.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Spi.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/spi_loopback/Example_2833xSpi_FFDLB.c b/f2833x/examples/spi_loopback/Example_2833xSpi_FFDLB.c new file mode 100644 index 0000000..ce02bf5 --- /dev/null +++ b/f2833x/examples/spi_loopback/Example_2833xSpi_FFDLB.c @@ -0,0 +1,243 @@ +//########################################################################### +// +// FILE: Example_2833xSpi_FFDLB.c +// +// TITLE: SPI Digital Loop Back Example +// +//! \addtogroup f2833x_example_list +//!

SPI Digital Loop Back (spi_loopback)

+//! +//! This program uses the internal loop back test mode of the peripheral. +//! Other then boot mode pin configuration, no other hardware configuration +//! is required. Interrupts are not used. +//! +//! A stream of data is sent and then compared to the received stream. +//! The sent data looks like this: \n +//! 0000 0001 0002 0003 0004 0005 0006 0007 .... FFFE FFFF \n +//! This pattern is repeated forever. +//! +//! \b Watch \b Variables \n +//! - sdata - Sent data +//! - rdata - Received data +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +//__interrupt void ISRTimer2(void); +void delay_loop(void); +void spi_xmit(Uint16 a); +void spi_fifo_init(void); +void spi_init(void); +void error(void); + +// +// Main +// +void main(void) +{ + Uint16 sdata; // send data + Uint16 rdata; // received data + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Setup only the GP I/O only for SPI-A functionality + // This function is found in DSP2833x_Spi.c + // + InitSpiaGpio(); + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + spi_fifo_init(); // Initialize the Spi FIFO + spi_init(); // init SPI + + // + // Step 5. User specific code: + // + + // + // Interrupts are not used in this example. + // + sdata = 0x0000; + for(;;) + { + // + // Transmit data + // + spi_xmit(sdata); + + // + // Wait until data is received + // + while(SpiaRegs.SPIFFRX.bit.RXFFST !=1) + { + + } + + // + // Check against sent data + // + rdata = SpiaRegs.SPIRXBUF; + + if(rdata != sdata) + { + error(); + } + sdata++; + } +} + +// +// delay_loop - Step 7. Insert all local Interrupt Service Routines (ISRs) and +// functions here: +// +void +delay_loop() +{ + long i; + for (i = 0; i < 1000000; i++) + { + + } +} + +// +// error - +// +void +error(void) +{ + __asm(" ESTOP0"); // Test failed!! Stop! + for (;;); +} + +// +// spi_init - +// +void +spi_init() +{ + SpiaRegs.SPICCR.all =0x000F; // Reset on, rising edge, 16-bit char bits + + // + // Enable master mode, normal phase, enable talk, and SPI int disabled. + // + SpiaRegs.SPICTL.all =0x0006; + SpiaRegs.SPIBRR =0x007F; + SpiaRegs.SPICCR.all =0x009F; // Relinquish SPI from Reset + SpiaRegs.SPIPRI.bit.FREE = 1; // Set so breakpoints don't disturb xmission +} + +// +// spi_xmit - +// +void +spi_xmit(Uint16 a) +{ + SpiaRegs.SPITXBUF=a; +} + +// +// spi_fifo_init - +// +void +spi_fifo_init() +{ + // + // Initialize SPI FIFO registers + // + SpiaRegs.SPIFFTX.all=0xE040; + SpiaRegs.SPIFFRX.all=0x204f; + SpiaRegs.SPIFFCT.all=0x0; +} + +// +// End of File +// + diff --git a/f2833x/examples/spi_loopback_interrupts/.ccsproject b/f2833x/examples/spi_loopback_interrupts/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/spi_loopback_interrupts/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/spi_loopback_interrupts/.cproject b/f2833x/examples/spi_loopback_interrupts/.cproject new file mode 100644 index 0000000..dde51ca --- /dev/null +++ b/f2833x/examples/spi_loopback_interrupts/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/spi_loopback_interrupts/.project b/f2833x/examples/spi_loopback_interrupts/.project new file mode 100644 index 0000000..a071037 --- /dev/null +++ b/f2833x/examples/spi_loopback_interrupts/.project @@ -0,0 +1,98 @@ + + + Example_2833xSpi_FFDLB_int + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_Spi.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Spi.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.c b/f2833x/examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.c new file mode 100644 index 0000000..0a033ae --- /dev/null +++ b/f2833x/examples/spi_loopback_interrupts/Example_2833xSpi_FFDLB_int.c @@ -0,0 +1,290 @@ +//########################################################################### +// +// FILE: Example_2833xSpi_FFDLB_int.c +// +// TITLE: SPI Digital Loop Back with Interrupts Example +// +//! \addtogroup f2833x_example_list +//!

SPI Digital Loop Back with Interrupts (spi_loopback_interrupts)

+//! +//! This program uses the internal loop back test mode of the peripheral. +//! Other then boot mode pin configuration, no other hardware configuration +//! is required. Both interrupts and the SPI FIFOs are used. +//! +//! A stream of data is sent and then compared to the received stream. +//! The sent data looks like this: \n +//! 0000 0001 0002 0003 0004 0005 0006 0007 \n +//! 0001 0002 0003 0004 0005 0006 0007 0008 \n +//! 0002 0003 0004 0005 0006 0007 0008 0009 \n +//! .... \n +//! FFFE FFFF 0000 0001 0002 0003 0004 0005 \n +//! FFFF 0000 0001 0002 0003 0004 0005 0006 \n +//! etc.. \n +//! +//! This pattern is repeated forever. +//! +//! \b Watch \b Variables \n +//! - sdata - Data to send +//! - rdata - Received data +//! - rdata_point - Used to keep track of the last position in +//! the receive stream for error checking +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +//__interrupt void ISRTimer2(void); +__interrupt void spiTxFifoIsr(void); +__interrupt void spiRxFifoIsr(void); +void delay_loop(void); +void spi_fifo_init(void); +void error(); + +// +// Globals +// +Uint16 sdata[8]; // Send data buffer +Uint16 rdata[8]; // Receive data buffer + +// +// Keep track of where we are in the data stream to check received data +// +Uint16 rdata_point; + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Setup only the GP I/O only for SPI-A functionality + // + InitSpiaGpio(); + + // + // Step 3. Initialize PIE vector table: + // Disable and clear all CPU interrupts + /// + DINT; + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize PIE control registers to their default state: + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.SPIRXINTA = &spiRxFifoIsr; + PieVectTable.SPITXINTA = &spiTxFifoIsr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + spi_fifo_init(); // Initialize the SPI only + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Initialize the send data buffer + // + for(i=0; i<8; i++) + { + sdata[i] = i; + } + rdata_point = 0; + + // + // Enable interrupts required for this example + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER6.bit.INTx1=1; // Enable PIE Group 6, INT 1 + PieCtrlRegs.PIEIER6.bit.INTx2=1; // Enable PIE Group 6, INT 2 + IER=0x20; // Enable CPU INT6 + EINT; // Enable Global Interrupts + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;); +} + +// +// Some Useful local functions +// + +// +// delay_loop - +// +void +delay_loop() +{ + long i; + for (i = 0; i < 1000000; i++) + { + + } +} + +// +// error - +// +void +error(void) +{ + __asm(" ESTOP0"); //Test failed!! Stop! + for (;;); +} + +// +// spi_fifo_init - +// +void +spi_fifo_init() +{ + // + // Initialize SPI FIFO registers + // + SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI + + SpiaRegs.SPICCR.all=0x001F; // 16-bit character, Loopback mode + SpiaRegs.SPICTL.all=0x0017; // Interrupt enabled, Master/Slave XMIT enabled + SpiaRegs.SPISTS.all=0x0000; + SpiaRegs.SPIBRR=0x0063; // Baud rate + SpiaRegs.SPIFFTX.all=0xC028; // Enable FIFO's, set TX FIFO level to 8 + SpiaRegs.SPIFFRX.all=0x0028; // Set RX FIFO level to 8 + SpiaRegs.SPIFFCT.all=0x00; + SpiaRegs.SPIPRI.all=0x0010; + + SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI + + SpiaRegs.SPIFFTX.bit.TXFIFO=1; + SpiaRegs.SPIFFRX.bit.RXFIFORESET=1; +} + +// +// spiTxFifoIsr - +// +__interrupt void +spiTxFifoIsr(void) +{ + Uint16 i; + for(i=0;i<8;i++) + { + SpiaRegs.SPITXBUF=sdata[i]; // Send data + } + + for(i=0;i<8;i++) // Increment data for next cycle + { + sdata[i] = sdata[i]+ 1; + } + + SpiaRegs.SPIFFTX.bit.TXFFINTCLR=1; // Clear Interrupt flag + PieCtrlRegs.PIEACK.all|=0x20; // Issue PIE ACK +} + +// +// spiRxFifoIsr - +// +__interrupt void +spiRxFifoIsr(void) +{ + Uint16 i; + for(i=0;i<8;i++) + { + rdata[i]=SpiaRegs.SPIRXBUF; // Read data + } + + for(i=0;i<8;i++) // Check received data + { + if(rdata[i] != rdata_point+i) + { + error(); + } + } + rdata_point++; + SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1; // Clear Overflow flag + SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag + PieCtrlRegs.PIEACK.all|=0x20; // Issue PIE ack +} + +// +// End of File +// + diff --git a/f2833x/examples/sw_prioritized_interrupts/.ccsproject b/f2833x/examples/sw_prioritized_interrupts/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/sw_prioritized_interrupts/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/sw_prioritized_interrupts/.cproject b/f2833x/examples/sw_prioritized_interrupts/.cproject new file mode 100644 index 0000000..98171b2 --- /dev/null +++ b/f2833x/examples/sw_prioritized_interrupts/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/sw_prioritized_interrupts/.project b/f2833x/examples/sw_prioritized_interrupts/.project new file mode 100644 index 0000000..1ca4cce --- /dev/null +++ b/f2833x/examples/sw_prioritized_interrupts/.project @@ -0,0 +1,88 @@ + + + Example_2833xSWPrioritizedInterrupts + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_SWPrioritizedPieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SWPrioritizedPieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedDefaultIsr.c b/f2833x/examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedDefaultIsr.c new file mode 100644 index 0000000..08768a2 --- /dev/null +++ b/f2833x/examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedDefaultIsr.c @@ -0,0 +1,2896 @@ +//########################################################################### +// +// FILE: Example_2833xSWPrioritizedDefaultIsr.c +// +// TITLE: DSP2833x Device Default Software Prioritized Interrupt +// Service Routines. +// +// This file is based on the standard +// DSP2833x_SWPrioritizedDefaultIsr.c. The ISR routines have been +// modified slightly to provide a trace mechanism used for this +// example +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +// +// Defined in the Example_28xSWPrioritizedInterrupts.c file +// for this example only +// +extern Uint16 ISRTrace[50]; +extern Uint16 ISRTraceIndex; + +// +// Global used for ISR delays +// +Uint16 i; + +// +// INT13_ISR - INT13 or CPU-Timer1 is connected to INT13 of CPU +// (use MINT13 mask): Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +// +#if (INT13PL != 0) +__interrupt void +INT13_ISR(void) +{ + IER |= MINT13; // Set "global" priority + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} +#endif + +// +// INT14_ISR - CPU-Timer2 is connected to INT14 of CPU (use MINT14 mask) +// +#if (INT14PL != 0) +__interrupt void +INT14_ISR(void) +{ + IER |= MINT14; // Set "global" priority + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} +#endif + +// +// DATALOG_ISR - Datalogging interrupt is connected to int15 of CPU +// (use MINT15 mask) +// +#if (INT15PL != 0) +__interrupt void +DATALOG_ISR(void) +{ + IER |= MINT15; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + __asm (" ESTOP0"); + for(;;); +} +#endif + +// +// RTOSINT_ISR - RTOS interrupt is connected to int16 of CPU (use MINT16 mask) +// +#if (INT16PL != 0) +__interrupt void +RTOSINT_ISR(void) +{ + IER |= MINT16; // Set "global" priority + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} +#endif + +// +// EMUINT_ISR - Emulation interrupt is connected to EMUINT of CPU +// (non-maskable) +// +__interrupt void +EMUINT_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// NMI_ISR - Non-maskable interrupt is connected to NMI of CPU (non-maskable) +// +__interrupt void +NMI_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// ILLEGAL_ISR - Illegal operation TRAP is connected to ITRAP of CPU +// (non-maskable) +// +__interrupt void +ILLEGAL_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER1_ISR - User Defined trap 1 is connected to USER1 of CPU (non-maskable) +// +__interrupt void +USER1_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER2_ISR - User Defined trap 2 is connected to USER2 of CPU (non-maskable) +// +__interrupt void +USER2_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER3_ISR - User Defined trap 3 is connected to USER3 of CPU (non-maskable) +// +__interrupt void +USER3_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER4_ISR - User Defined trap 4 is connected to USER4 of CPU (non-maskable) +// +__interrupt void +USER4_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER5_ISR - User Defined trap 5 is connected to USER5 of CPU (non-maskable) +// +__interrupt void +USER5_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER6_ISR - User Defined trap 6 is connected to USER6 of CPU (non-maskable) +// +__interrupt void +USER6_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER7_ISR - User Defined trap 7 is connected to USER7 of CPU (non-maskable) +// +__interrupt void +USER7_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER8_ISR - User Defined trap 8 is connected to USER8 of CPU (non-maskable) +// +__interrupt void +USER8_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER9_ISR - User Defined trap 9 is connected to USER9 of CPU (non-maskable) +// +__interrupt void +USER9_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER10_ISR - User Defined trap 10 is connected to USER10 of +// CPU (non-maskable) +// +__interrupt void +USER10_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER11_ISR - User Defined trap 11 is connected to USER11 of +// CPU (non-maskable) +// +__interrupt void +USER11_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// USER12_ISR - User Defined trap 12 is connected to USER12 of +// CPU (non-maskable) +// +__interrupt void +USER12_ISR(void) +{ + EINT; + + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + __asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 1 - MUXed into CPU INT1 +// + +// +// SEQ1INT_ISR - ADC is connected to PIEIER1_1 (use MINT1 and MG11 masks) +// +#if (G11PL != 0) +__interrupt void +SEQ1INT_ISR( void ) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0011; + ISRTraceIndex++; +} +#endif + +// +// SEQ2INT_ISR - ADC is connected to PIEIER1_2 (use MINT1 and MG12 masks) +// +#if (G12PL != 0) +__interrupt void +SEQ2INT_ISR( void ) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0012; + ISRTraceIndex++; +} +#endif + +// +// XINT1_ISR - connected to PIEIER1_4 (use MINT1 and MG14 masks) +// +#if (G14PL != 0) +__interrupt void +XINT1_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + __asm(" NOP"); + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0014; + ISRTraceIndex++; +} +#endif + +// +// XINT2_ISR - Connected to PIEIER1_5 (use MINT1 and MG15 masks) +// +#if (G15PL != 0) +__interrupt void +XINT2_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0015; + ISRTraceIndex++; +} +#endif + +// +// ADCINT_ISR - ADC is connected to PIEIER1_6 (use MINT1 and MG16 masks) +// +#if (G16PL != 0) +__interrupt void +ADCINT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0016; + ISRTraceIndex++; +} +#endif + +// +// TINT0_ISR - CPU-Timer 0 is connected to PIEIER1_7 (use MINT1 and MG17 masks) +// +#if (G17PL != 0) +__interrupt void +TINT0_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0017; + ISRTraceIndex++; +} +#endif + +// +// WAKEINT_ISR - WD/LPM is connected to PIEIER1_8 (use MINT1 and MG18 masks) +// +#if (G18PL != 0) +__interrupt void +WAKEINT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0018; + ISRTraceIndex++; +} +#endif + +// +// PIE Group 2 - MUXed into CPU INT2 +// + +// +// EPWM1_TZINT_ISR - ePWM1 Trip Zone is connected to PIEIER2_1 +// (use MINT2 and MG21 masks) +// +#if (G21PL != 0) +__interrupt void +EPWM1_TZINT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0021; + ISRTraceIndex++; +} +#endif + +// +// EPWM2_TZINT_ISR - ePWM2 Trip Zone is connected to PIEIER2_2 +// (use MINT2 and MG22 masks) +// +#if (G22PL != 0) +__interrupt void +EPWM2_TZINT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0022; + ISRTraceIndex++; +} +#endif + +// +// EPWM3_TZINT_ISR - ePWM3 Trip Zone is connected to PIEIER2_3 +// (use MINT2 and MG23 masks) +// +#if (G23PL != 0) +__interrupt void +EPWM3_TZINT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0023; + ISRTraceIndex++; +} +#endif + +// +// EPWM4_TZINT_ISR - ePWM4 Trip Zone is connected to PIEIER2_4 +// (use MINT2 and MG24 masks) +// +#if (G24PL != 0) +__interrupt void +EPWM4_TZINT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0024; + ISRTraceIndex++; +} +#endif + +// +// EPWM5_TZINT_ISR - ePWM5 Trip Zone is connected to PIEIER2_5 +// (use MINT2 and MG25 masks) +// +#if (G25PL != 0) +__interrupt void +EPWM5_TZINT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0025; + ISRTraceIndex++; +} +#endif + +// +// EPWM6_TZINT_ISR - ePWM6 Trip Zone is connected to PIEIER2_6 +// (use MINT2 and MG26 masks) +// +#if (G26PL != 0) +__interrupt void +EPWM6_TZINT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0026; + ISRTraceIndex++; +} +#endif + +// +// PIE Group 3 - MUXed into CPU INT3 +// + +// +// EPWM1_INT_ISR - ePWM1 Interrupt is connected to PIEIER3_1 +// (use MINT3 and MG31 masks) +// +#if (G31PL != 0) +__interrupt void +EPWM1_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0031; + ISRTraceIndex++; +} +#endif + +// +// EPWM2_INT_ISR - ePWM2 Interrupt is connected to PIEIER3_2 +// (use MINT3 and MG32 masks) +// +#if (G32PL != 0) +__interrupt void +EPWM2_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0032; + ISRTraceIndex++; +} +#endif + +// +// EPWM3_INT_ISR - ePWM3 Interrupt is connected to PIEIER3_3 +// (use MINT3 and MG33 masks) +// +#if (G33PL != 0) +__interrupt void +EPWM3_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0033; + ISRTraceIndex++; +} +#endif + +// +// EPWM4_INT_ISR - ePWM4 Interrupt is connected to PIEIER3_4 +// (use MINT3 and MG34 masks) +// +#if (G34PL != 0) +__interrupt void +EPWM4_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0034; + ISRTraceIndex++; +} +#endif + +// +// EPWM5_INT_ISR - ePWM5 Interrupt is connected to PIEIER3_5 +// (use MINT3 and MG35 masks) +// +#if (G35PL != 0) +__interrupt void +EPWM5_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0035; + ISRTraceIndex++; +} +#endif + +// +// EPWM6_INT_ISR - ePWM6 Interrupt is connected to PIEIER3_6 +// (use MINT3 and MG36 masks) +// +#if (G36PL != 0) +__interrupt void +EPWM6_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0036; + ISRTraceIndex++; +} +#endif + +// +// PIE Group 4 - MUXed into CPU INT4 +// + +// +// ECAP1_INT_ISR - eCAP1 Interrupt is connected to PIEIER4_1 +// (use MINT4 and MG41 masks) +// +#if (G41PL != 0) +__interrupt void +ECAP1_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0041; + ISRTraceIndex++; +} +#endif + +// +// ECAP2_INT_ISR - eCAP2 Interrupt is connected to PIEIER4_2 +// (use MINT4 and MG42 masks) +// +#if (G42PL != 0) +__interrupt void +ECAP2_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0042; + ISRTraceIndex++; + +} +#endif + +// +// ECAP3_INT_ISR - eCAP3 Interrupt is connected to PIEIER4_3 +// (use MINT4 and MG43 masks) +// +#if (G43PL != 0) +__interrupt void +ECAP3_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0043; + ISRTraceIndex++; + +} +#endif + +// +// ECAP4_INT_ISR - eCAP4 Interrupt is connected to PIEIER4_4 +// (use MINT4 and MG44 masks) +// +#if (G44PL != 0) +__interrupt void +ECAP4_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0044; + ISRTraceIndex++; +} +#endif + +// +// ECAP5_INT_ISR - eCAP5 Interrupt is connected to PIEIER4_5 +// (use MINT4 and MG45 masks) +// +#if (G44PL != 0) +__interrupt void +ECAP5_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0045; + ISRTraceIndex++; +} +#endif + +// +// ECAP6_INT_ISR - eCAP6 Interrupt is connected to PIEIER4_6 +// (use MINT4 and MG46 masks) +// +#if (G44PL != 0) +__interrupt void +ECAP6_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0046; + ISRTraceIndex++; +} +#endif + +// +// PIE Group 5 - MUXed into CPU INT5 +// + +// +// EQEP1_INT_ISR - eQEP1 Interrupt is connected to PIEIER5_1 +// (use MINT5 and MG51 masks) +// +#if (G51PL != 0) +__interrupt void +EQEP1_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0051; + ISRTraceIndex++; +} +#endif + +// +// EQEP2_INT_ISR - eQEP2 Interrupt is connected to PIEIER5_2 +// (use MINT5 and MG52 masks) +// +#if (G52PL != 0) +__interrupt void +EQEP2_INT_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) {} + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0052; + ISRTraceIndex++; +} +#endif + +// +// PIE Group 6 - MUXed into CPU INT6 +// + +// +// SPIRXINTA_ISR - SPI-A is connected to PIEIER6_1 (use MINT6 and MG61 masks) +// +#if (G61PL != 0) +__interrupt void +SPIRXINTA_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0061; + ISRTraceIndex++; +} +#endif + +// +// SPITXINTA_ISR - SPI-A is connected to PIEIER6_2 (use MINT6 and MG62 masks) +// +#if (G62PL != 0) +__interrupt void +SPITXINTA_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0062; + ISRTraceIndex++; +} +#endif + +// +// MRINTB_ISR - McBSP-B is connected to PIEIER6_3 (use MINT6 and MG63 masks) +// +#if (G63PL != 0) +__interrupt void +MRINTB_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0063; + ISRTraceIndex++; +} +#endif + +// +// MXINTB_ISR - McBSP-B is connected to PIEIER6_4 (use MINT6 and MG64 masks) +// +#if (G64PL != 0) +__interrupt void +MXINTB_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0064; + ISRTraceIndex++; +} +#endif + +// +// MRINTA_ISR - McBSP-A is connected to PIEIER6_5 (use MINT6 and MG65 masks) +// +#if (G65PL != 0) +__interrupt void +MRINTA_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0065; + ISRTraceIndex++; +} +#endif + +// +// MXINTA_ISR - McBSP-A is connected to PIEIER6_6 (use MINT6 and MG66 masks) +// +#if (G66PL != 0) +__interrupt void +MXINTA_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0066; + ISRTraceIndex++; +} +#endif + +// +// PIE Group 7 - MUXed into CPU INT7 +// + +// +// DINTCH1_ISR - DMA-Channel 1 is connected to PIEIER7_1 +// (use MINT7 and MG71 masks) +// +#if (G71PL != 0) +__interrupt void +DINTCH1_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0071; + ISRTraceIndex++; +} +#endif + +// +// DINTCH2_ISR - DMA-Channel 2 is connected to PIEIER7_2 +// (use MINT7 and MG72 masks) +// +#if (G72PL != 0) +__interrupt void +DINTCH2_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0072; + ISRTraceIndex++; +} +#endif + +// +// DINTCH3_ISR - DMA-Channel 3 is connected to PIEIER7_3 +// (use MINT7 and MG73 masks) +// +#if (G73PL != 0) +__interrupt void +DINTCH3_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0073; + ISRTraceIndex++; +} +#endif + +// +// DINTCH4_ISR - DMA-Channel 4 is connected to PIEIER7_4 +// (use MINT7 and MG74 masks) +// +#if (G74PL != 0) +__interrupt void +DINTCH4_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0074; + ISRTraceIndex++; +} +#endif + +// +// DINTCH5_ISR - DMA-Channel 5 is connected to PIEIER7_5 +// (use MINT7 and MG75 masks) +// +#if (G75PL != 0) +__interrupt void +DINTCH5_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0075; + ISRTraceIndex++; +} +#endif + +// +// DINTCH6_ISR - DMA-Channel 6 is connected to PIEIER7_6 +// (use MINT7 and MG76 masks) +// +#if (G76PL != 0) +__interrupt void +DINTCH6_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0076; + ISRTraceIndex++; +} +#endif + +// +// PIE Group 8 - MUXed into CPU INT8 +// + +// +// I2CINT1A_ISR - I2C-A is connected to PIEIER8_1 +// (use MINT8 and MG81 masks) +// +#if (G81PL != 0) +__interrupt void +I2CINT1A_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG81; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here. + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0081; + ISRTraceIndex++; +} +#endif + +// +// I2CINT2A_ISR - I2C-A is connected to PIEIER8_2 (use MINT8 and MG82 masks) +// +#if (G82PL != 0) +__interrupt void +I2CINT2A_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0082; + ISRTraceIndex++; +} +#endif + +// +// SCIRXINTC_ISR - SCI-C is connected to PIEIER8_5 (use MINT8 and MG85 masks) +// +#if (G85PL != 0) +__interrupt void +SCIRXINTC_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG85; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0085; + ISRTraceIndex++; +} +#endif + +// +// SCITXINTC_ISR - SCI-C is connected to PIEIER8_6 (use MINT8 and MG86 masks) +// +#if (G86PL != 0) +__interrupt void +SCITXINTC_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0086; + ISRTraceIndex++; +} +#endif + +// +// PIE Group 9 - MUXed into CPU INT9 +// + +// +// SCIRXINTA_ISR - SCI-A is connected to PIEIER9_1 (use MINT9 and MG91 masks) +// +#if (G91PL != 0) +__interrupt void +SCIRXINTA_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0091; + ISRTraceIndex++; +} +#endif + +// +// SCITXINTA_ISR - SCI-A is connected to PIEIER9_2 (use MINT9 and MG92 masks) +// +#if (G92PL != 0) +__interrupt void +SCITXINTA_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0092; + ISRTraceIndex++; +} +#endif + +// +// SCIRXINTB_ISR - SCI-B is connected to PIEIER9_3 (use MINT9 and MG93 masks) +// +#if (G93PL != 0) +__interrupt void +SCIRXINTB_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0093; + ISRTraceIndex++; +} +#endif + +// +// SCITXINTB_ISR - SCI-B is connected to PIEIER9_4 (use MINT9 and MG94 masks) +// +#if (G94PL != 0) +__interrupt void +SCITXINTB_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0094; + ISRTraceIndex++; +} +#endif + +// +// ECAN0INTA_ISR - eCAN-A is connected to PIEIER9_5 (use MINT9 and MG95 masks) +// +#if (G95PL != 0) +__interrupt void +ECAN0INTA_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0095; + ISRTraceIndex++; +} +#endif + +// +// ECAN1INTA_ISR - eCAN-A is connected to PIEIER9_6 (use MINT9 and MG96 masks) +// +#if (G96PL != 0) +__interrupt void +ECAN1INTA_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0096; + ISRTraceIndex++; +} +#endif + +// +// ECAN0INTB_ISR - eCAN-B is connected to PIEIER9_7 (use MINT9 and MG97 masks) +// +#if (G97PL != 0) +__interrupt void +ECAN0INTB_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0097; + ISRTraceIndex++; +} +#endif + +// +// ECAN1INTB_ISR - eCAN-B is connected to PIEIER9_8 (use MINT9 and MG98 masks) +// +#if (G98PL != 0) +__interrupt void +ECAN1INTB_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0098; + ISRTraceIndex++; +} +#endif + +// +// PIE Group 10 - MUXed into CPU int10 +// + +// +// PIE Group 11 - MUXed into CPU int11 +// + +// +// PIE Group 12 - MUXed into CPU int12 +// + +// +// XINT3_ISR - External Interrupt is connected to PIEIER12_1 +// (use MINT12 and MG121 masks) +// +#if (G121PL != 0) +__interrupt void +XINT3_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0121; + ISRTraceIndex++; +} +#endif + +// +// XINT4_ISR - External Interrupt is connected to PIEIER12_2 +// (use MINT12 and MG122 masks) +// +#if (G122PL != 0) +__interrupt void +XINT4_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0122; + ISRTraceIndex++; +} +#endif + +// +// XINT5_ISR - External Interrupt is connected to PIEIER12_3 +// (use MINT12 and MG123 masks) +// +#if (G123PL != 0) +__interrupt void +XINT5_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0123; + ISRTraceIndex++; +} +#endif + +// +// XINT6_ISR - External Interrupt is connected to PIEIER12_4 +// (use MINT12 and MG124 masks) +// +#if (G124PL != 0) +__interrupt void +XINT6_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0124; + ISRTraceIndex++; +} +#endif + +// +// XINT7_ISR - External Interrupt is connected to PIEIER12_5 +// (use MINT12 and MG125 masks) +// +#if (G125PL != 0) +__interrupt void +XINT7_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0125; + ISRTraceIndex++; +} +#endif + +// +// LVF_ISR - FPA32 is connected to PIEIER12_7 (use MINT12 and MG127 masks) +// +#if (G127PL != 0) +__interrupt void +LVF_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0127; + ISRTraceIndex++; +} +#endif + +// +// LUF_ISR - FPA32 is connected to PIEIER12_8 (use MINT12 and MG128 masks) +// +#if (G128PL != 0) +__interrupt void +LUF_ISR(void) +{ + // + // Set interrupt priority + // + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + __asm(" NOP"); + EINT; + + // + // Insert ISR Code here + // + for(i = 1; i <= 10; i++) + { + + } + + // + // Restore registers saved + // + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // + // Add ISR to Trace + // + ISRTrace[ISRTraceIndex] = 0x0128; + ISRTraceIndex++; +} +#endif + +// +// Catch All Default ISRs +// + +// +// PIE_RESERVED - +// +__interrupt void +PIE_RESERVED(void) +{ + __asm (" ESTOP0"); + for(;;); +} + +// +// INT_NOTUSED_ISR - +// +__interrupt void +INT_NOTUSED_ISR(void) +{ + __asm (" ESTOP0"); + for(;;); +} + +// +// rsvd_ISR - +// +__interrupt void +rsvd_ISR(void) +{ + __asm (" ESTOP0"); + for(;;); +} + +// +// End of File +// + diff --git a/f2833x/examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.c b/f2833x/examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.c new file mode 100644 index 0000000..35440f4 --- /dev/null +++ b/f2833x/examples/sw_prioritized_interrupts/Example_2833xSWPrioritizedInterrupts.c @@ -0,0 +1,859 @@ +//########################################################################### +// +// FILE: Example_2833xSWPrioritizedInterrupts.c +// +// TITLE: Software Prioritized Interrupts Example +// +//! \addtogroup f2833x_example_list +//!

Software Prioritized Interrupts (sw_prioritized_interrupts)

+//! +//! For most applications, the hardware prioritizing of the +//! the PIE module is sufficient. For applications that need custom +//! prioritizing, this example illustrates how this can be done +//! through software. +//! +//! This program simulates interrupt conflicts by writing to the +//! PIEIFR registers. This will cause multiple interrupt requests to come +//! into the PIE block at the same time. +//! +//! The interrupt service routines are software prioritized as per +//! the table found in the DSP2833x_SWPrioritizedIsrLevels.h file. +//! +//! \b Running \b the \b Application +//! -# Before compiling you must set the Global and Group interrupt priorities +//! in the DSP2833x_SWPrioritizedIsrLevels.h file. +//! -# Select which test case you'd like to run with the +//! \#define CASE directive (1-9, default 1). +//! -# Compile the code, load, and run +//! -# At the end of each test there is a hard coded breakpoint (ESTOP0). +//! When code stops at the breakpoint, examine the ISRTrace buffer to +//! see the order in which the ISR's completed. All PIE interrupts will +//! be added to the ISRTrace. +//! The ISRTrace will consist of a list of hex values as shown: \n +//! 0x00wx <- PIE Group w interrupt x finished first \n +//! 0x00yz <- PIE Group y interrupt z finished next \n +//! -# If desired, set a new set of Global and Group interrupt priorities +//! and repeat the test to see the change. +//! +//! \b Watch \b Variables \n +//! - ISRTrace - Trace of ISR's in the order they complete. +//! +//! After each test, examine this buffer to determine if the ISR's completed +//! in the order desired. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +// +// Defines +// +#define TEST 1 // Select a test number: 1 through 10 + +// +// Defines the interrupts that are used in the PIE for each group +// +#define ISRS_GROUP1 (M_INT1|M_INT2|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8) +#define ISRS_GROUP2 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP3 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP4 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP5 (M_INT1|M_INT2) +#define ISRS_GROUP6 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP7 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6) +#define ISRS_GROUP8 (M_INT1|M_INT2|M_INT5|M_INT6) +#define ISRS_GROUP9 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8) +#define ISRS_GROUP12 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT7|M_INT8) + +// +// This array will be used as a trace to check the order that the +// interrupts were serviced +// +Uint16 ISRTrace[50]; +Uint16 ISRTraceIndex; // used to update an element in the trace buffer + +// +// Main +// +void main(void) +{ + Uint16 i; + + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + // InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code, enable interrupts + // + +#if (TEST == 1) + // + // Force all group 1 interrupts at once by writing to the PIEIFR1 register + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable PIE group 1 interrupt 1-8 + // + PieCtrlRegs.PIEIER1.all = 0x00FF; + + // + // Make sure PIEACK for group 1 is clear (default after reset) + // + PieCtrlRegs.PIEACK.all = M_INT1; + + // + // Enable CPU INT1 + // + IER |= M_INT1; + + // + // Force all valid interrupts for Group 1 + // + PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1; + + // + // Enable global Interrupts CPU level: + // + EINT; // Enable Global interrupt INTM + + // + // Wait for all Group 1 interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR1.all != 0x0000 ) + { + + } + + // + // Stop here and check the ISRTrace to determine which order the + // ISR Routines completed. The order is dependant on the priority + // assigned in the DSP2833x_SWPrioritizedIsrLevels.h file + // + // The ISRTrace will contain a list of values corresponding to the + // interrupts serviced in the order they were serviced. + // For example if the ISRTrace looks like this + // 0x0014 ISR Group 1 interrupt 4 + // 0x0017 ISR Group 1 interrupt 7 + // 0x0016 ISR Group 1 interrupt 6 + // 0x0015 ISR Group 1 interrupt 5 + // 0x0018 ISR Group 1 interrupt 8 + // 0x0012 ISR Group 1 interrupt 2 + // 0x0011 ISR Group 1 interrupt 1 + // 0x0000 end of trace + // + __asm(" ESTOP0"); +#endif +#if (TEST == 2) + // + // CASE 2: Force all group 2 interrupts at once by writing to the PIEIFR2 + // register + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable PIE group 2 interrupts 1-8 + // + PieCtrlRegs.PIEIER2.all = 0x00FF; + + // + // Enable CPU INT2 + // + IER |= (M_INT2); + + // + // Make sure PIEACK for group 2 is clear (default after reset) + // + PieCtrlRegs.PIEACK.all = M_INT2; + + // + // Force all valid interrupts for Group 2 + // + PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2; + + // + // Enable Global interrupts + // + EINT; + + // + // Wait for all group 2 interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR2.all != 0x0000 ) + { + + } + + // + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + // + __asm(" ESTOP0"); + +#endif +#if (TEST == 3) + // + // CASE 3: Force all group 3 interrupts at once by writing to the PIEIFR3 + // register + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable PIE group 3 interrupts 1-8 + // + PieCtrlRegs.PIEIER3.all = 0x00FF; + + // + // Make sure PIEACK for group 3 is clear (default after reset) + // + PieCtrlRegs.PIEACK.all = M_INT3; + + // + // Enable CPU INT3 + // + IER |= (M_INT3); + + // + // Force all valid interrupts for Group 3 + // + PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3; + + // + // Enable Global interrupts + // + EINT; + + // + // Wait for all group 3 interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR3.all != 0x0000 ) + { + + } + + // + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + // + __asm(" ESTOP0"); +#endif +#if (TEST == 4) + // + // CASE 4: Force all group 4 interrupts at once by writing to the PIEIFR4 + // register + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable PIE group 4 interrupts 1-8 + // + PieCtrlRegs.PIEIER4.all = 0x00FF; + + // + // Make sure PIEACK for group 3 is clear (default after reset) + // + PieCtrlRegs.PIEACK.all = M_INT4; + + // + // Enable CPU INT4 + // + IER |= (M_INT4); + + // + // Force all valid interrupts for Group 4 + // + PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4; + + // + // Enable Global interrupts + // + EINT; + + // + // Wait for all group 4 interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR4.all != 0x0000 ) + { + + } + + // + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + // + __asm(" ESTOP0"); +#endif +#if (TEST == 5) + // + // CASE 5: Force all group 5 interrupts at once by writing to the PIEIFR5 + // register + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable PIE group 5 interrupts 1-8 + // + PieCtrlRegs.PIEIER5.all = 0x00FF; + + // + // Make sure PIEACK for group 5 is clear (default after reset) + // + PieCtrlRegs.PIEACK.all = M_INT5; + + // + // Enable CPU INT5 + // + IER |= (M_INT5); + + // + // Force all valid interrupts for Group 5 + // + PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5; + + // + // Enable Global interrupts + // + EINT; + + // + // Wait for all group 5 interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR5.all != 0x0000 ) + { + + } + + // + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + // + __asm(" ESTOP0"); +#endif +#if (TEST == 6) + // + // CASE 6: Force all group 6 interrupts at once by writing to the PIEIFR6 + // register + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable PIE group 6 interrupts 1-8 + // + PieCtrlRegs.PIEIER6.all = 0x00FF; + + // + // Make sure PIEACK for group 6 is clear (default after reset) + // + PieCtrlRegs.PIEACK.all = M_INT6; + + // + // Enable CPU INT6 + // + IER |= (M_INT6); + + // + // Force all valid interrupts for Group 6 + // + PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6; + + // + // Enable Global interrupts + // + EINT; + + // + // Wait for all group 6 interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR6.all != 0x0000 ) + { + + } + + // + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + // + __asm(" ESTOP0"); +#endif +#if (TEST == 7) + // + // CASE 7: Force all group 9 interrupts at once by writing to the PIEIFR4 + // register + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable PIE group 9 interrupts 1-8 + // + PieCtrlRegs.PIEIER9.all = 0x00FF; + + // + // Make sure PIEACK for group 9 is clear (default after reset) + // + PieCtrlRegs.PIEACK.all = M_INT9; + + // + // Enable CPU INT9 + // + IER |= (M_INT9); + + // + // Force all valid interrupts for Group 9 + // + PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9; + + // + // Enable Global interrupts + // + EINT; + + // + // Wait for all group 9 interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR9.all != 0x0000 ) + { + + } + + // + // Stop here and check the order the ISR's were serviced in the + // ISRTrace + // + __asm(" ESTOP0"); +#endif +#if (TEST == 8) + // + // CASE 8: Force all group 1 and group 2 interrupts at once + // + + // + // Setup next test - fire interrupts from Group 1 and Group 2 + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable PIE group 1 and group 2 interrupts 1-8 + // + PieCtrlRegs.PIEIER1.all = 0x00FF; + PieCtrlRegs.PIEIER2.all = 0x00FF; + + // + // Make sure PIEACK for group 1 & 2 are clear (default after reset) + // + PieCtrlRegs.PIEACK.all = (M_INT3 | M_INT2); + + // + // Enable CPU INT1 and INT2 + // + IER |= (M_INT1|M_INT2); + + // + // Force all valid interrupts for Group 1 and from Group 2 + // + PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1; + PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2; + + // + // Enable Global interrupts + // + EINT; + + // + // Wait for all group 1 and group 2 interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR1.all != 0x0000 + || PieCtrlRegs.PIEIFR2.all != 0x0000) + { + + } + + // + // Check the ISRTrace to determine which order the ISR Routines completed + // + __asm(" ESTOP0"); + +#endif +#if (TEST == 9) + // + // CASE 9: Force all group 1 and group 2 and group 3 interrupts at once + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable PIE group 1, 2 and 3 interrupts 1-8 + // + PieCtrlRegs.PIEIER1.all = 0x00FF; + PieCtrlRegs.PIEIER2.all = 0x00FF; + PieCtrlRegs.PIEIER3.all = 0x00FF; + + // + // Make sure PIEACK for group 1, 2 & 3 are clear (default after reset) + // + PieCtrlRegs.PIEACK.all = (M_INT3|M_INT2|M_INT3); + + // + // Enable CPU INT1, INT2 & INT3 + // + IER |= (M_INT1|M_INT2|M_INT3); + + // + // Force all valid interrupts for Group1, 2 and 3 + // + PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1; + PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2; + PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3; + + // + // Enable Global interrupts + // + EINT; + + // + // Wait for all group 1 and group 2 and group 3 interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR1.all != 0x0000 + || PieCtrlRegs.PIEIFR2.all != 0x0000 + || PieCtrlRegs.PIEIFR3.all != 0x0000) + { + + } + + // + // Check the ISRTrace to determine which order the ISR Routines completed + // + __asm(" ESTOP0"); +#endif +#if (TEST == 10) + // + // CASE 10: Force all used PIE interrupts at once + // + + // + // Prepare for the test: Disable interrupts + // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers + // + DINT; + for(i = 0; i < 50; i++) + { + ISRTrace[i] = 0; + } + ISRTraceIndex = 0; + InitPieCtrl(); + IER = 0; + IFR &= 0; + + // + // Enable the PIE block + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enable all PIE group interrupts 1-8 + // + PieCtrlRegs.PIEIER1.all = 0x00FF; + PieCtrlRegs.PIEIER2.all = 0x00FF; + PieCtrlRegs.PIEIER3.all = 0x00FF; + PieCtrlRegs.PIEIER4.all = 0x00FF; + PieCtrlRegs.PIEIER5.all = 0x00FF; + PieCtrlRegs.PIEIER6.all = 0x00FF; + PieCtrlRegs.PIEIER9.all = 0x00FF; + + // + // Make sure PIEACK for group 1, 2, 3, 4, 5, 6 and 9 are clear + // (default after reset) + // + PieCtrlRegs.PIEACK.all = (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5| + M_INT6|M_INT9); + + // + // Enable CPU INT1, INT2, INT3, INT4, INT5, INT6 and INT9 + // + IER |= (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9); + + // + // Force all valid interrupts for all PIE groups + // + PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1; + PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2; + PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3; + PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4; + PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5; + PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6; + PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9; + + // + // Enable Global interrupts - CPU level + // + EINT; + + // + // Wait for all group interrupts to be serviced + // + while(PieCtrlRegs.PIEIFR1.all != 0x0000 + || PieCtrlRegs.PIEIFR2.all != 0x0000 + || PieCtrlRegs.PIEIFR3.all != 0x0000 + || PieCtrlRegs.PIEIFR4.all != 0x0000 + || PieCtrlRegs.PIEIFR5.all != 0x0000 + || PieCtrlRegs.PIEIFR6.all != 0x0000 + || PieCtrlRegs.PIEIFR9.all != 0x0000 ) + { + + } + + // + // Check the ISRTrace to determine which order the ISR Routines completed + // + __asm(" ESTOP0"); +#endif +} + +// +// End of File +// + diff --git a/f2833x/examples/timed_led_blink/.ccsproject b/f2833x/examples/timed_led_blink/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/timed_led_blink/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/timed_led_blink/.cproject b/f2833x/examples/timed_led_blink/.cproject new file mode 100644 index 0000000..72525ff --- /dev/null +++ b/f2833x/examples/timed_led_blink/.cproject @@ -0,0 +1,224 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/timed_led_blink/.project b/f2833x/examples/timed_led_blink/.project new file mode 100644 index 0000000..83160c4 --- /dev/null +++ b/f2833x/examples/timed_led_blink/.project @@ -0,0 +1,98 @@ + + + Example_2833xLEDBlink + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/timed_led_blink/Example_2833xLEDBlink.c b/f2833x/examples/timed_led_blink/Example_2833xLEDBlink.c new file mode 100644 index 0000000..912ac76 --- /dev/null +++ b/f2833x/examples/timed_led_blink/Example_2833xLEDBlink.c @@ -0,0 +1,232 @@ +//########################################################################### +// +// FILE: Example_2833xLEDBlink.c +// +// TITLE: Timed LED Blink Example +// +//! \addtogroup f2833x_example_list +//!

Timer based blinking LED (timed_led_blink)

+//! +//! This example configures CPU Timer0 for a 500 msec period, and toggles the +//! GPIO32 LED on the 2833x once per interrupt. For testing purposes, +//! this example also increments a counter each time the timer asserts an +//! interrupt. +//! +//! Select the appropriate board build configuration to have the correct +//! LED GPIO toggled. +//! +//! \b Watch \b Variables \n +//! - CpuTimer0.InterruptCount +//! +//! \b External \b Connections \n +//! - Monitor the GPIO32 LED blink on (for 500 msec) and off (for 500 msec) +//! +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File + +// +// Function Prototypes +// +__interrupt void cpu_timer0_isr(void); + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + //InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags: + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT0 = &cpu_timer0_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize the Device Peripheral. This function can be + // found in DSP2833x_CpuTimers.c + // + InitCpuTimers(); // For this example, only initialize the Cpu Timers +#if (CPU_FRQ_150MHZ) + // + // Configure CPU-Timer 0 to interrupt every 500 milliseconds: + // 150MHz CPU Freq, 50 millisecond Period (in uSeconds) + // + ConfigCpuTimer(&CpuTimer0, 150, 500000); +#endif +#if (CPU_FRQ_100MHZ) + // + // Configure CPU-Timer 0 to interrupt every 500 milliseconds: + // 100MHz CPU Freq, 50 millisecond Period (in uSeconds) + // + ConfigCpuTimer(&CpuTimer0, 100, 500000); +#endif + + // + // To ensure precise timing, use write-only instructions to write to the + // entire register. Therefore, if any of the configuration bits are changed + // in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the + // below settings must also be updated. + // + + // + // Use write-only instruction to set TSS bit = 0 + // + CpuTimer0Regs.TCR.all = 0x4000; + + // + // Step 5. User specific code, enable interrupts + // +#if (_EZDSP_BOARD) + // + // Configure GPIO32 as a GPIO output pin + // + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; + GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; + EDIS; +#else + // + // Configure GPIO31 as a GPIO output pin + // + EALLOW; + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO31 = 1; + EDIS; +#endif + + // + // Enable CPU INT1 which is connected to CPU-Timer 0: + // + IER |= M_INT1; + + // + // Enable TINT0 in the PIE: Group 1 interrupt 7 + // + PieCtrlRegs.PIEIER1.bit.INTx7 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional): + // + for(;;); +} + +// +// cpu_timer0_isr - +// +__interrupt void +cpu_timer0_isr(void) +{ + CpuTimer0.InterruptCount++; + +#if (_EZDSP_BOARD) + // + // Toggle GPIO32 once per 500 milliseconds + // + GpioDataRegs.GPBTOGGLE.bit.GPIO32 = 1; +#else + // + // Toggle GPIO31 once per 500 milliseconds + // + GpioDataRegs.GPATOGGLE.bit.GPIO31 = 1; +#endif + + // + // Acknowledge this interrupt to receive more interrupts from group 1 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +// +// End of File +// + diff --git a/f2833x/examples/watchdog/.ccsproject b/f2833x/examples/watchdog/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/watchdog/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/watchdog/.cproject b/f2833x/examples/watchdog/.cproject new file mode 100644 index 0000000..d02efae --- /dev/null +++ b/f2833x/examples/watchdog/.cproject @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/watchdog/.project b/f2833x/examples/watchdog/.project new file mode 100644 index 0000000..13b4d98 --- /dev/null +++ b/f2833x/examples/watchdog/.project @@ -0,0 +1,93 @@ + + + Example_2833xWatchdog + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 28335_RAM_lnk.cmd + 1 + INSTALLROOT_2833X/common/cmd/28335_RAM_lnk.cmd + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/watchdog/Example_2833xWatchdog.c b/f2833x/examples/watchdog/Example_2833xWatchdog.c new file mode 100644 index 0000000..726a733 --- /dev/null +++ b/f2833x/examples/watchdog/Example_2833xWatchdog.c @@ -0,0 +1,220 @@ +//########################################################################### +// +// FILE: Example_2833xWatchdog.c +// +// TITLE: Watchdog interrupt Test Example +// +//! \addtogroup f2833x_example_list +//!

Watchdog interrupt Test (watchdog)

+//! +//! This program exercises the watchdog. +//! +//! First the watchdog is connected to the WAKEINT interrupt of the +//! PIE block. The code is then put into an infinite loop. +//! +//! The user can select to feed the watchdog key register or not +//! by commenting the following line of code in the infinite loop: +//! \b ServiceDog(); \n +//! +//! If the watchdog key register is fed by the ServiceDog function +//! then the WAKEINT interrupt is not taken. If the key register +//! is not fed by the ServiceDog function then WAKEINT will be taken. +//! +//! \b Watch \b Variables \n +//! - \b LoopCount - Number of times through the infinite loop +//! - \b WakeCount - Number of times through WAKEINT +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// Function Prototypes +// +__interrupt void wakeint_isr(void); + +// +// Globals +// +Uint32 WakeCount; +Uint32 LoopCount; + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + //InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.WAKEINT = &wakeint_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP2833x_InitPeripherals.c + // + //InitPeripherals(); // Not required for this example + + // + // Step 5. User specific code, enable interrupts + // + + // + // Clear the counters + // + WakeCount = 0; // Count interrupts + LoopCount = 0; // Count times through idle loop + + // + // Connect the watchdog to the WAKEINT interrupt of the PIE + // Write to the whole SCSR register to avoid clearing WDOVERRIDE bit + // + EALLOW; + SysCtrlRegs.SCSR = BIT1; + EDIS; + + // + // Enable WAKEINT in the PIE: Group 1 interrupt 8 + // Enable INT1 which is connected to WAKEINT: + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER1.bit.INTx8 = 1; // Enable PIE Group 1 INT8 + IER |= M_INT1; // Enable CPU int1 + EINT; // Enable Global Interrupts + + // + // Reset the watchdog counter + // + ServiceDog(); + + // + // Enable the watchdog + // + EALLOW; + SysCtrlRegs.WDCR = 0x0028; + EDIS; + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;) + { + LoopCount++; + + // + // Uncomment ServiceDog to just loop here + // Comment ServiceDog to take the WAKEINT instead + // + //ServiceDog(); + } +} + +// +// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions +// here: If local ISRs are used, reassign vector addresses in vector table as +// shown in Step 5 +// + +// +// wakeint_isr - +// +__interrupt void +wakeint_isr(void) +{ + WakeCount++; + + // + // Acknowledge this interrupt to get more from group 1 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +// +// End of File +// + diff --git a/f2833x/examples/xintf_run_from/.ccsproject b/f2833x/examples/xintf_run_from/.ccsproject new file mode 100644 index 0000000..a0fa6fb --- /dev/null +++ b/f2833x/examples/xintf_run_from/.ccsproject @@ -0,0 +1,6 @@ + + + + + + diff --git a/f2833x/examples/xintf_run_from/.cproject b/f2833x/examples/xintf_run_from/.cproject new file mode 100644 index 0000000..3c23d38 --- /dev/null +++ b/f2833x/examples/xintf_run_from/.cproject @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/f2833x/examples/xintf_run_from/.project b/f2833x/examples/xintf_run_from/.project new file mode 100644 index 0000000..bbd1858 --- /dev/null +++ b/f2833x/examples/xintf_run_from/.project @@ -0,0 +1,108 @@ + + + Example_2833xCodeRunFromXintf + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + DSP2833x_ADC_cal.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_ADC_cal.asm + + + DSP2833x_CodeStartBranch.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CodeStartBranch.asm + + + DSP2833x_CpuTimers.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_CpuTimers.c + + + DSP2833x_DBGIER.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DBGIER.asm + + + DSP2833x_DefaultIsr.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_DefaultIsr.c + + + DSP2833x_GlobalVariableDefs.c + 1 + INSTALLROOT_2833X/headers/source/DSP2833x_GlobalVariableDefs.c + + + DSP2833x_Headers_nonBIOS.cmd + 1 + INSTALLROOT_2833X/headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + DSP2833x_MemCopy.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_MemCopy.c + + + DSP2833x_PieCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieCtrl.c + + + DSP2833x_PieVect.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_PieVect.c + + + DSP2833x_SysCtrl.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_SysCtrl.c + + + DSP2833x_Xintf.c + 1 + INSTALLROOT_2833X/common/source/DSP2833x_Xintf.c + + + DSP2833x_usDelay.asm + 1 + INSTALLROOT_2833X/common/source/DSP2833x_usDelay.asm + + + + + INSTALLROOT_FASTRTS + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/FPUfastRTS/c28 + + + INSTALLROOT_IQMATH + $%7BPARENT-4-PROJECT_LOC%7D/libraries/math/IQmath/c28 + + + INSTALLROOT_2833X + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/f2833x/examples/xintf_run_from/28335_RAM_xintf_lnk.cmd b/f2833x/examples/xintf_run_from/28335_RAM_xintf_lnk.cmd new file mode 100644 index 0000000..87dbd15 --- /dev/null +++ b/f2833x/examples/xintf_run_from/28335_RAM_xintf_lnk.cmd @@ -0,0 +1,207 @@ +/* +// TI File $Revision: /main/2 $ +// Checkin $Date: July 30, 2009 18:45:43 $ +//########################################################################### +// +// FILE: 28335_RAM_xintf_lnk.cmd +// +// TITLE: Linker Command File For 28335 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28335 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : > RAML0, PAGE = 0 + #else + ramfuncs : > RAML0, PAGE = 0 + #endif +#endif + + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + xintffuncs : LOAD = RAML1, + RUN = ZONE7A, + LOAD_START(_XintffuncsLoadStart), + LOAD_END(_XintffuncsLoadEnd), + RUN_START(_XintffuncsRunStart), + LOAD_SIZE(_XintffuncsLoadSize), + PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/f2833x/examples/xintf_run_from/Example_2833xCodeRunFromXintf.c b/f2833x/examples/xintf_run_from/Example_2833xCodeRunFromXintf.c new file mode 100644 index 0000000..8433201 --- /dev/null +++ b/f2833x/examples/xintf_run_from/Example_2833xCodeRunFromXintf.c @@ -0,0 +1,370 @@ +//########################################################################### +// +// FILE: Example_2833xCodeRunFromXintf.c +// +// TITLE: Code Run from XINTF Example +// +//! \addtogroup f2833x_example_list +//!

Code Run from XINTF (xintf_run_from)

+//! +//! This example configures CPU Timer0 and increments +//! a counter each time the timer asserts an interrupt. +//! +//! The code is loaded into SARAM. The XINTF Zone 7 is +//! configured for x16-bit data bus. A portion of the code +//! is copied to XINTF for execution there. +//! +//! \b Watch \b Variables \n +//! - CpuTimer0.InterruptCount +//! - CpuTimer1.InterruptCount +//! - CpuTimer2.InterruptCount +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include + +// +// These two functions will be loaded into SARAM and copied to XINTF zone 7 for +// execution +// +#pragma CODE_SECTION(cpu_timer0_isr,"xintffuncs"); +#pragma CODE_SECTION(cpu_timer1_isr,"xintffuncs"); + +// +// Function Prototypes +// +void init_zone7(void); +__interrupt void cpu_timer0_isr(void); +__interrupt void cpu_timer1_isr(void); +__interrupt void cpu_timer2_isr(void); + +// +// Main +// +void main(void) +{ + // + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP2833x_SysCtrl.c file. + // + InitSysCtrl(); + + // + // Step 2. Initialize GPIO: + // This example function is found in the DSP2833x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // + // InitGpio(); // Skipped for this example + + // + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + // + DINT; + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP2833x_PieCtrl.c file. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP2833x_DefaultIsr.c. + // This function is found in DSP2833x_PieVect.c. + // + InitPieVectTable(); + + // + // Interrupts that are used in this example are re-mapped to + // ISR functions found within this file. + // + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT0 = &cpu_timer0_isr; + PieVectTable.XINT13 = &cpu_timer1_isr; + PieVectTable.TINT2 = &cpu_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // + // Step 4. Initialize the Device Peripheral. This function can be + // found in DSP2833x_CpuTimers.c + // + InitCpuTimers(); // For this example, only initialize the Cpu Timers + +#if (CPU_FRQ_150MHZ) + // + // Configure CPU-Timer 0, 1, and 2 to interrupt every second: + // 150MHz CPU Freq, 1 second Period (in uSeconds) + // + ConfigCpuTimer(&CpuTimer0, 150, 1000000); + ConfigCpuTimer(&CpuTimer1, 150, 1000000); + ConfigCpuTimer(&CpuTimer2, 150, 1000000); +#endif + +#if (CPU_FRQ_100MHZ) + // + // Configure CPU-Timer 0, 1, and 2 to interrupt every second: + // 100MHz CPU Freq, 1 second Period (in uSeconds) + // + ConfigCpuTimer(&CpuTimer0, 100, 1000000); + ConfigCpuTimer(&CpuTimer1, 100, 1000000); + ConfigCpuTimer(&CpuTimer2, 100, 1000000); +#endif + + // + // To ensure precise timing, use write-only instructions to write to the + // entire register. Therefore, if any of the configuration bits are changed + // in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the + // below settings must also be updated. + // + + // + // Use write-only instruction to set TSS bit = 0 + // + CpuTimer0Regs.TCR.all = 0x4000; + + // + // Use write-only instruction to set TSS bit = 0 + // + CpuTimer1Regs.TCR.all = 0x4000; + + // + // Use write-only instruction to set TSS bit = 0 + // + CpuTimer2Regs.TCR.all = 0x4000; + + // + // Step 5. User specific code, enable interrupts: + // + + // + // Initialize XINTF Zone 7 + // + init_zone7(); + + // + // Copy non-time critical code to XINTF + // This includes the following ISR functions: cpu_timer0_isr(), + // cpu_timer1_isr(). The XintffuncsLoadStart, XintffuncsLoadEnd, + // and XintffuncsRunStart symbols are created by the linker. Refer to the + // F28335_ram_xintf.cmd file. + // + memcpy(&XintffuncsRunStart, &XintffuncsLoadStart, + (Uint32)&XintffuncsLoadSize); + + // + // Enable CPU int1 which is connected to CPU-Timer 0, CPU int13 + // which is connected to CPU-Timer 1, and CPU int 14, which is connected + // to CPU-Timer 2: + // + IER |= M_INT1; + IER |= M_INT13; + IER |= M_INT14; + + // + // Enable TINT0 in the PIE: Group 1 interrupt 7 + // + PieCtrlRegs.PIEIER1.bit.INTx7 = 1; + + // + // Enable global Interrupts and higher priority real-time debug events + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + // + // Step 6. IDLE loop. Just sit and loop forever (optional) + // + for(;;); +} + +// +// cpu_timer0_isr - +// +__interrupt void +cpu_timer0_isr(void) +{ + CpuTimer0.InterruptCount++; + + // + // Acknowledge this interrupt to receive more interrupts from group 1 + // + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; +} + +// +// cpu_timer1_isr - +// +__interrupt void +cpu_timer1_isr(void) +{ + CpuTimer1.InterruptCount++; + + // + // The CPU acknowledges the interrupt. + // + EDIS; +} + +// +// cpu_timer2_isr - +// +__interrupt void +cpu_timer2_isr(void) +{ + EALLOW; + CpuTimer2.InterruptCount++; + + // + // The CPU acknowledges the interrupt. + // + EDIS; +} + +// +// init_zone7 - Configure the timing parameters for Zone 7. +// Notes: This function should not be executed from XINTF. Adjust the timing +// based on the data manual and external device requirements. +// +void +init_zone7(void) +{ + // + // Make sure the XINTF clock is enabled + // + EALLOW; + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; + EDIS; + + // + // Configure the GPIO for XINTF with a 16-bit data bus + // This function is in DSP2833x_Xintf.c + // + InitXintf16Gpio(); + + EALLOW; + + // + // All Zones + // Timing for all zones based on XTIMCLK = SYSCLKOUT + // + XintfRegs.XINTCNF2.bit.XTIMCLK = 0; + + // + // Buffer up to 3 writes + // + XintfRegs.XINTCNF2.bit.WRBUFF = 3; + + // + // XCLKOUT is enabled + // + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + + // + // XCLKOUT = XTIMCLK + // + XintfRegs.XINTCNF2.bit.CLKMODE = 0; + + // + // Disable XHOLD to prevent XINTF bus from going into high impedance state + // whenever TZ3 signal goes low. This occurs because TZ3 on GPIO14 is + // shared with HOLD of XINTF + // + XintfRegs.XINTCNF2.bit.HOLD = 1; + + // + // Zone 7 + // When using ready, ACTIVE must be 1 or greater. Lead must always be 1 or + // greater. Zone write timing + // + XintfRegs.XTIMING7.bit.XWRLEAD = 1; + XintfRegs.XTIMING7.bit.XWRACTIVE = 2; + XintfRegs.XTIMING7.bit.XWRTRAIL = 1; + + // + // Zone read timing + // + XintfRegs.XTIMING7.bit.XRDLEAD = 1; + XintfRegs.XTIMING7.bit.XRDACTIVE = 3; + XintfRegs.XTIMING7.bit.XRDTRAIL = 0; + + // + // don't double all Zone read/write lead/active/trail timing + // + XintfRegs.XTIMING7.bit.X2TIMING = 0; + + // + // Zone will not sample XREADY signal + // + XintfRegs.XTIMING7.bit.USEREADY = 0; + XintfRegs.XTIMING7.bit.READYMODE = 0; + + // + // 1,1 = x16 data bus + // 0,1 = x32 data bus + // other values are reserved + // + XintfRegs.XTIMING7.bit.XSIZE = 3; + EDIS; + + // + // Force a pipeline flush to ensure that the write to + // the last register configured occurs before returning. + // + __asm(" RPT #7 || NOP"); +} + +// +// End of File +// + diff --git a/f2833x/headers/cmd/DSP2833x_Headers_BIOS.cmd b/f2833x/headers/cmd/DSP2833x_Headers_BIOS.cmd new file mode 100644 index 0000000..6994c57 --- /dev/null +++ b/f2833x/headers/cmd/DSP2833x_Headers_BIOS.cmd @@ -0,0 +1,214 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: July 8, 2009 10:22:08 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_BIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file does not include the PieVectorTable structure. +// For non-BIOS applications, please use the DSP2833x_Headers_nonBIOS.cmd +// file which includes the PieVectorTable structure. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ +/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/ + PieVectTableFile : > PIEVECT, PAGE = 1, TYPE = DSECT + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/f2833x/headers/cmd/DSP2833x_Headers_nonBIOS.cmd b/f2833x/headers/cmd/DSP2833x_Headers_nonBIOS.cmd new file mode 100644 index 0000000..da8ec98 --- /dev/null +++ b/f2833x/headers/cmd/DSP2833x_Headers_nonBIOS.cmd @@ -0,0 +1,214 @@ +/* +// TI File $Revision: /main/8 $ +// Checkin $Date: June 2, 2008 11:12:24 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_nonBIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in Non-BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file includes the PieVectorTable structure. +// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file +// which does not include the PieVectorTable structure. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ + PieVectTableFile : > PIE_VECT, PAGE = 1 + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/f2833x/headers/include/DSP2833x_Adc.h b/f2833x/headers/include/DSP2833x_Adc.h new file mode 100644 index 0000000..24dd005 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_Adc.h @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_CpuTimers.h b/f2833x/headers/include/DSP2833x_CpuTimers.h new file mode 100644 index 0000000..20cec0d --- /dev/null +++ b/f2833x/headers/include/DSP2833x_CpuTimers.h @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_DMA.h b/f2833x/headers/include/DSP2833x_DMA.h new file mode 100644 index 0000000..bb1cb9a --- /dev/null +++ b/f2833x/headers/include/DSP2833x_DMA.h @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_DevEmu.h b/f2833x/headers/include/DSP2833x_DevEmu.h new file mode 100644 index 0000000..aef14e9 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_DevEmu.h @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_Device.h b/f2833x/headers/include/DSP2833x_Device.h new file mode 100644 index 0000000..503f701 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_Device.h @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_ECan.h b/f2833x/headers/include/DSP2833x_ECan.h new file mode 100644 index 0000000..b2beaa3 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_ECan.h @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_ECap.h b/f2833x/headers/include/DSP2833x_ECap.h new file mode 100644 index 0000000..9ee836d --- /dev/null +++ b/f2833x/headers/include/DSP2833x_ECap.h @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_EPwm.h b/f2833x/headers/include/DSP2833x_EPwm.h new file mode 100644 index 0000000..8df44c2 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_EPwm.h @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_EQep.h b/f2833x/headers/include/DSP2833x_EQep.h new file mode 100644 index 0000000..3525283 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_EQep.h @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_Gpio.h b/f2833x/headers/include/DSP2833x_Gpio.h new file mode 100644 index 0000000..70f997b --- /dev/null +++ b/f2833x/headers/include/DSP2833x_Gpio.h @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_I2c.h b/f2833x/headers/include/DSP2833x_I2c.h new file mode 100644 index 0000000..0d98732 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_I2c.h @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_Mcbsp.h b/f2833x/headers/include/DSP2833x_Mcbsp.h new file mode 100644 index 0000000..3fb50a3 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_Mcbsp.h @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/f2833x/headers/include/DSP2833x_PieCtrl.h b/f2833x/headers/include/DSP2833x_PieCtrl.h new file mode 100644 index 0000000..3c5a7c3 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_PieCtrl.h @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_PieVect.h b/f2833x/headers/include/DSP2833x_PieVect.h new file mode 100644 index 0000000..92e0022 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_PieVect.h @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_Sci.h b/f2833x/headers/include/DSP2833x_Sci.h new file mode 100644 index 0000000..284b30c --- /dev/null +++ b/f2833x/headers/include/DSP2833x_Sci.h @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_Spi.h b/f2833x/headers/include/DSP2833x_Spi.h new file mode 100644 index 0000000..84b35e0 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_Spi.h @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_SysCtrl.h b/f2833x/headers/include/DSP2833x_SysCtrl.h new file mode 100644 index 0000000..b8d0bbd --- /dev/null +++ b/f2833x/headers/include/DSP2833x_SysCtrl.h @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_XIntrupt.h b/f2833x/headers/include/DSP2833x_XIntrupt.h new file mode 100644 index 0000000..e4a3271 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_XIntrupt.h @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/f2833x/headers/include/DSP2833x_Xintf.h b/f2833x/headers/include/DSP2833x_Xintf.h new file mode 100644 index 0000000..ad554e1 --- /dev/null +++ b/f2833x/headers/include/DSP2833x_Xintf.h @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c b/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c new file mode 100644 index 0000000..aa9f3dd --- /dev/null +++ b/f2833x/headers/source/DSP2833x_GlobalVariableDefs.c @@ -0,0 +1,407 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: June 2, 2008 11:12:33 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalVariableDefs.c +// +// TITLE: DSP2833x Global Variables and Data Section Pragmas. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File + +// +// Define Global Peripheral Variables +// +#ifdef __cplusplus +#pragma DATA_SECTION("AdcRegsFile") +#else +#pragma DATA_SECTION(AdcRegs,"AdcRegsFile"); +#endif +volatile struct ADC_REGS AdcRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdcMirrorFile") +#else +#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile"); +#endif +volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("CsmPwlFile") +#else +#pragma DATA_SECTION(CsmPwl,"CsmPwlFile"); +#endif +volatile struct CSM_PWL CsmPwl; + +#ifdef __cplusplus +#pragma DATA_SECTION("CsmRegsFile") +#else +#pragma DATA_SECTION(CsmRegs,"CsmRegsFile"); +#endif +volatile struct CSM_REGS CsmRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("DevEmuRegsFile") +#else +#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile"); +#endif +volatile struct DEV_EMU_REGS DevEmuRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaRegsFile") +#else +#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile"); +#endif +volatile struct ECAN_REGS ECanaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMboxesFile") +#else +#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanaMboxes; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaLAMRegsFile") +#else +#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanaLAMRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanaMOTSRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTORegsFile") +#else +#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanaMOTORegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbRegsFile") +#else +#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile"); +#endif +volatile struct ECAN_REGS ECanbRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMboxesFile") +#else +#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanbMboxes; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbLAMRegsFile") +#else +#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanbLAMRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTORegsFile") +#else +#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanbMOTORegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("GpioIntRegsFile") +#else +#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile"); +#endif +volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct MCBSP_REGS McbspaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("PartIdRegsFile") +#else +#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile"); +#endif +volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("SysCtrlRegsFile") +#else +#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile"); +#endif +volatile struct SYS_CTRL_REGS SysCtrlRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("FlashRegsFile") +#else +#pragma DATA_SECTION(FlashRegs,"FlashRegsFile"); +#endif +volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("XIntruptRegsFile") +#else +#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile"); +#endif +volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("XintfRegsFile") +#else +#pragma DATA_SECTION(XintfRegs,"XintfRegsFile"); +#endif +volatile struct XINTF_REGS XintfRegs; + +// +// End of file +// +