149 lines
6.0 KiB
Batchfile
149 lines
6.0 KiB
Batchfile
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/* This is the stack that is used by code running within main()
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* In case of NORTOS,
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* - This means all the code outside of ISR uses this stack
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* In case of FreeRTOS
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* - This means all the code until vTaskStartScheduler() is called in main()
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* uses this stack.
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* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
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*/
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--stack_size=16384
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/* This is the heap size for malloc() API in NORTOS and FreeRTOS
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* This is also the heap used by pvPortMalloc in FreeRTOS
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*/
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--heap_size=32768
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-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
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/* This is the size of stack when R5 is in IRQ mode
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* In NORTOS,
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* - Here interrupt nesting is enabled
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* - This is the stack used by ISRs registered as type IRQ
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* In FreeRTOS,
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* - Here interrupt nesting is disabled
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* - This is stack that is used initally when a IRQ is received
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* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
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* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
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*/
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__IRQ_STACK_SIZE = 256;
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/* This is the size of stack when R5 is in IRQ mode
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* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
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*/
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__FIQ_STACK_SIZE = 256;
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__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
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__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
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__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
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SECTIONS
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{
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/* This has the R5F entry point and vector table, this MUST be at 0x0 */
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.vectors:{} palign(8) > R5F_VECS
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/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
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* i.e this cannot be placed in DDR
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*/
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GROUP {
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.text.hwi: palign(8)
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.text.cache: palign(8)
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.text.mpu: palign(8)
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.text.boot: palign(8)
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.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
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} > MSRAM
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/* This is rest of code. This can be placed in DDR if DDR is available and needed */
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GROUP {
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.text: {} palign(8) /* This is where code resides */
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.rodata: {} palign(8) /* This is where const's go */
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} > MSRAM
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/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
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GROUP {
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.data: {} palign(8) /* This is where initialized globals and static go */
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} > MSRAM
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/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
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GROUP {
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.bss: {} palign(8) /* This is where uninitialized globals go */
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RUN_START(__BSS_START)
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RUN_END(__BSS_END)
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.sysmem: {} palign(8) /* This is where the malloc heap goes */
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.stack: {} palign(8) /* This is where the main() stack goes */
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} > MSRAM
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/* This is where the stacks for different R5F modes go */
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GROUP {
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.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
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RUN_START(__IRQ_STACK_START)
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RUN_END(__IRQ_STACK_END)
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.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
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RUN_START(__FIQ_STACK_START)
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RUN_END(__FIQ_STACK_END)
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.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
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RUN_START(__SVC_STACK_START)
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RUN_END(__SVC_STACK_END)
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.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
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RUN_START(__ABORT_STACK_START)
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RUN_END(__ABORT_STACK_END)
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.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
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RUN_START(__UNDEFINED_STACK_START)
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RUN_END(__UNDEFINED_STACK_END)
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} > MSRAM
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/* Sections needed for C++ projects */
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GROUP {
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.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
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.init_array: {} palign(8) /* Contains function pointers called before main */
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.fini_array: {} palign(8) /* Contains function pointers called after main */
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} > MSRAM
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/* General purpose user shared memory, used in some examples */
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.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
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/* this is used when Debug log's to shared memory are enabled, else this is not used */
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.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
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/* this is used only when IPC RPMessage is enabled, else this is not used */
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.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
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/* General purpose non cacheable memory, used in some examples */
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.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
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}
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/*
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NOTE: Below memory is reserved for DMSC usage
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- During Boot till security handoff is complete
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0x701E0000 - 0x701FFFFF (128KB)
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- After "Security Handoff" is complete (i.e at run time)
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0x701F4000 - 0x701FFFFF (48KB)
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Security handoff is complete when this message is sent to the DMSC,
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TISCI_MSG_SEC_HANDOVER
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This should be sent once all cores are loaded and all application
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specific firewall calls are setup.
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*/
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MEMORY
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{
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R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
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R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
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R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
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/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
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NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
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/* when using multi-core application's i.e more than one R5F/M4F active, make sure
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* this memory does not overlap with other R5F's
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*/
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MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x80000
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/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
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* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
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*/
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FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
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/* shared memory segments */
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/* On R5F,
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* - make sure there is a MPU entry which maps below regions as non-cache
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*/
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USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80
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LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
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RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
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}
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