feat: Добавил утилиты для инициализации ddr и загрузчик с SD карты

2023-05-03 14:54:13 +03:00 · 2023-05-03 14:54:13 +03:00 · 50076e8c05
commit 50076e8c05
parent ae3cac8a7d
32 changed files with 1962 additions and 0 deletions
--- a/utils/ddr_init/ccs_files/am64x_xds560v2.ccxml
+++ b/utils/ddr_init/ccs_files/am64x_xds560v2.ccxml
@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configurations XML_version="1.2" id="configurations_0">
+    
+    <configuration XML_version="1.2" id="Spectrum Digital XDS560V2 STM USB Emulator_0">
+        <instance XML_version="1.2" desc="Spectrum Digital XDS560V2 STM USB Emulator_0" href="connections/SD560V2USB_Connection.xml" id="Spectrum Digital XDS560V2 STM USB Emulator_0" xml="SD560V2USB_Connection.xml" xmlpath="connections"/>
+        <connection XML_version="1.2" id="Spectrum Digital XDS560V2 STM USB Emulator_0">
+            <instance XML_version="1.2" href="drivers/tixds560cs_dap.xml" id="drivers" xml="tixds560cs_dap.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560cortexA53.xml" id="drivers" xml="tixds560cortexA53.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560cortexR.xml" id="drivers" xml="tixds560cortexR.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560cortexM.xml" id="drivers" xml="tixds560cortexM.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560pru.xml" id="drivers" xml="tixds560pru.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560csstm.xml" id="drivers" xml="tixds560csstm.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560ctset2.xml" id="drivers" xml="tixds560ctset2.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560etbcs.xml" id="drivers" xml="tixds560etbcs.xml" xmlpath="drivers"/>
+            <platform XML_version="1.2" id="platform_0">
+                <instance XML_version="1.2" desc="AM64x_0" href="devices/AM64x.xml" id="AM64x_0" xml="AM64x.xml" xmlpath="devices"/>
+            </platform>
+        </connection>
+    </configuration>
+</configurations>
--- a/utils/ddr_init/ccs_files/am64xevm_ddr_init.release.out
+++ b/utils/ddr_init/ccs_files/am64xevm_ddr_init.release.out
--- a/utils/ddr_init/ccs_files/load_ddr_init.js
+++ b/utils/ddr_init/ccs_files/load_ddr_init.js
@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2021, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+Description:
+   Load executables to various CPUs on the SOC
+
+Usage:
+
+1. Modify "sdkPath" (search for EDIT THIS) to point to the absolute path of the SDK.
+    - On windows make sure to use '/' or '\\' as path separator
+
+2. Launch AM64x_GP_EVM target connection in CCS, however DO NOT connect to any CPUs.
+
+3. From CCS Scripting console do (CCS Tool Bar > View > Scripting Console)
+
+        js:> loadJSFile "<path/to/sdk>/tools/ccs_load/am64x/load.js"
+
+4. After successful execution you should see a log like below
+
+        js:> loadJSFile "C:/ti/mcu_plus_sdk/tools/ccs_load/am64x/load.js"
+        Connecting, halting, reseting ...
+        [r5fss0-0] Loading ... C:/ti/mcu_plus_sdk/examples/drivers/ipc/ipc_rpmsg_echo/am64x-evm/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo.debug.out
+        [r5fss0-1] Loading ... C:/ti/mcu_plus_sdk/examples/drivers/ipc/ipc_rpmsg_echo/am64x-evm/r5fss0-1_nortos/ti-arm-clang/ipc_rpmsg_echo.debug.out
+        [r5fss1-0] Loading ... C:/ti/mcu_plus_sdk/examples/drivers/ipc/ipc_rpmsg_echo/am64x-evm/r5fss1-0_nortos/ti-arm-clang/ipc_rpmsg_echo.debug.out
+        [r5fss1-1] Loading ... C:/ti/mcu_plus_sdk/examples/drivers/ipc/ipc_rpmsg_echo/am64x-evm/r5fss1-1_nortos/ti-arm-clang/ipc_rpmsg_echo.debug.out
+        [m4fss0-0] Skipping load, C:/ti/mcu_plus_sdk/examples/drivers/ipc/ipc_rpmsg_echo/am64x-evm/m4fss0-0_nortos/ti-arm-clang/ipc_rpmsg_echo.debug.out file NOT FOUND ...
+        [r5fss0-1] Running ...
+        [r5fss1-0] Running ...
+        [r5fss1-1] Running ...
+        [r5fss0-0] Running ...
+        All DONE !!!
+
+5. If any of the logs in step 4 show "fail" or "error" messages then
+   check your EVM, CCS, SDK setup, Executables path and try again.
+
+6. To reload without power cycles, repeat step 4 onwards.
+
+*/
+// !!! EDIT THIS !!! Edit all of below based on the example you want to run
+runAfterLoad = true;
+
+// Указать путь к текущей папке
+var script_path = "D:/Projects_dep/ethercat_translator/utils/ddr_init/ccs_files";
+
+print("script_path = " + script_path);
+
+// !!! EDIT THIS !!! Comment lines below for CPUs that are not needed to be loaded, change 'os' based on the 'os' combo that you have
+var elf_file = {};
+elf_file["r5fss0-0"] = script_path + "/am64xevm_ddr_init.release.out";
+
+print("[load_ddr_init]: elf_file = " + elf_file["r5fss0-0"]);
+
+function connectHaltResetCpu(cpu)
+{
+    dsCPU[cpu].target.connect();
+    dsCPU[cpu].target.halt();
+    dsCPU[cpu].target.reset();
+}
+
+function runCpu(cpu)
+{
+    if(cpu && File(elf_file[cpu]).isFile() )
+    {
+        if(runAfterLoad)
+        {
+            print("[" + cpu + "] Running ... ");
+            dsCPU[cpu].target.runAsynch();
+        }
+    }
+}
+
+function loadCpu(cpu)
+{
+    if(cpu && File(elf_file[cpu]).isFile() )
+    {
+        print("[" + cpu + "] Loading ... " + elf_file[cpu] );
+        dsCPU[cpu].memory.loadProgram(elf_file[cpu]);
+    }
+    else
+    {
+        print("[" + cpu + "] Skipping load, " + elf_file[cpu] + " file NOT FOUND ... " );
+    }
+}
+
+function doEverything()
+{
+    /* Set timeout of in units of msecs */
+    script.setScriptTimeout(10 * 1000);
+
+    // Open a debug session
+    dsCPU["r5fss0-0"] = debugServer.openSession( ".*MAIN_Cortex_R5_0_0" );
+    
+    print("Connecting, halting, reseting ...");
+    connectHaltResetCpu("r5fss0-0");
+    
+    loadCpu("r5fss0-0");
+    
+	runCpu("r5fss0-0");
+	
+	print("[load_ddr_init]: Waiting 1 sec while ddr_init works...");
+	Thread.sleep(1000);
+	
+	print("[load_ddr_init]: Reseting the CPU...");
+	dsCPU["r5fss0-0"].target.reset();
+	
+    print("[load_ddr_init]: All DONE !!!");
+}
+
+// Import the DSS packages into our namespace to save on typing
+importPackage(Packages.com.ti.debug.engine.scripting)
+importPackage(Packages.com.ti.ccstudio.scripting.environment)
+importPackage(Packages.java.lang)
+importPackage(java.io);
+importPackage(java.lang);
+
+var dsCPU = {};
+var ds;
+var debugServer;
+var script;
+
+// Check to see if running from within CCSv4 Scripting Console
+var withinCCS = (ds !== undefined);
+
+// !!! EDIT THIS !!! Add absolute path to the CCXML file here.
+fileCcxml = script_path + "/am64x_xds560v2.ccxml";
+
+// Create scripting environment and get debug server if running standalone
+if (!withinCCS)
+{
+    // Import the DSS packages into our namespace to save on typing
+    importPackage(Packages.com.ti.debug.engine.scripting);
+    importPackage(Packages.com.ti.ccstudio.scripting.environment);
+    importPackage(Packages.java.lang);
+
+    // Create our scripting environment object - which is the main entry point into any script and
+    // the factory for creating other Scriptable ervers and Sessions
+    script = ScriptingEnvironment.instance();
+
+    // Get the Debug Server and start a Debug Session
+    debugServer = script.getServer("DebugServer.1");
+
+    // Check if the CCXML file exists.
+    if(!File(fileCcxml).isFile())
+    {
+        print("[ERROR] File "+fileCcxml+" not found !!!");
+        print("Seems like the script is not run from within CCS. Please edit the load_dmsc_hsfs.js script to add a path to your CCXML configuration file in this case.")
+    }
+    else
+    {
+        debugServer.setConfig(fileCcxml);
+        doEverything();
+    }
+}
+else // otherwise leverage existing scripting environment and debug server
+{
+    debugServer = ds;
+    script = env;
+    doEverything();
+}
+
--- a/utils/ddr_init/ddr_init_fw/.ccsproject
+++ b/utils/ddr_init/ddr_init_fw/.ccsproject
@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<?ccsproject version="1.0"?>
+<projectOptions>
+	<ccsVersion value="11.2.0"/>
+	<deviceVariant value="Cortex R.AM64x"/>
+	<deviceFamily value="TMS470"/>
+	<deviceEndianness value="little"/>
+	<codegenToolVersion value="TICLANG_2.1.3.LTS"/>
+	<isElfFormat value="true"/>
+	<connection value="common/targetdb/connections/TIXDS110_Connection.xml"/>
+	<rts value=""/>
+	<createSlaveProjects value=""/>
+	<ignoreDefaultDeviceSettings value="true"/>
+	<ignoreDefaultCCSSettings value="true"/>
+	<templateProperties value="id=example.projectspec.sciclient_ccs_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang"/>
+	<origin value="D:\ti\mcu_plus_sdk_am64x_08_05_00_24\examples\drivers\sciclient\sciclient_ccs_init\am64x-evm\r5fss0-0_nortos\ti-arm-clang\example.projectspec"/>
+	<filesToOpen value=""/>
+	<isTargetManual value="true"/>
+</projectOptions>
--- a/utils/ddr_init/ddr_init_fw/.cproject
+++ b/utils/ddr_init/ddr_init_fw/.cproject
@ -0,0 +1,233 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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+				<externalSettings/>
+				<extensions>
+					<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.ti.ccstudio.errorparser.SysConfigErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.2140931171" name="Debug" parent="com.ti.ccstudio.buildDefinitions.TMS470.Debug" postbuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE}">
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+									<listOptionValue builtIn="false" value="${SYSCONFIG_TOOL_LIBRARIES}"/>
+									<listOptionValue builtIn="false" value="${COM_TI_MCU_PLUS_SDK_AM64X_LIBRARIES}"/>
+									<listOptionValue builtIn="false" value="nortos.am64x.r5f.ti-arm-clang.release.lib"/>
+									<listOptionValue builtIn="false" value="drivers.am64x.r5f.ti-arm-clang.release.lib"/>
+									<listOptionValue builtIn="false" value="board.am64x.r5f.ti-arm-clang.release.lib"/>
+									<listOptionValue builtIn="false" value="libc.a"/>
+									<listOptionValue builtIn="false" value="libsysbm.a"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.DIAG_SUPPRESS.1480855843" name="Suppress diagnostic &lt;id&gt; (--diag_suppress)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.DIAG_SUPPRESS" useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="10063"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.INITIALIZATION_MODEL.268913437" name="Initialization model" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.INITIALIZATION_MODEL" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.INITIALIZATION_MODEL.RAM_MODEL" valueType="enumerated"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__CMD_SRCS.906384710" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__CMD_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__CMD2_SRCS.983580036" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__CMD2_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__GEN_CMDS.1306022614" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__GEN_CMDS"/>
+							</tool>
+							<tool id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.hex.143562707" name="Arm Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.hex"/>
+							<tool id="com.ti.ccstudio.buildDefinitions.sysConfig.510464264" name="SysConfig" superClass="com.ti.ccstudio.buildDefinitions.sysConfig">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.sysConfig.PRODUCTS.1668013183" name="Root system config meta data file in a product or SDK (-s, --product)" superClass="com.ti.ccstudio.buildDefinitions.sysConfig.PRODUCTS" useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="${SYSCONFIG_TOOL_SYSCONFIG_MANIFEST}"/>
+									<listOptionValue builtIn="false" value="${COM_TI_MCU_PLUS_SDK_AM64X_SYSCONFIG_MANIFEST}"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.sysConfig.CONTEXT.1767462076" name="Name of the context (core name or 'system') to target (-e, --context)" superClass="com.ti.ccstudio.buildDefinitions.sysConfig.CONTEXT" useByScannerDiscovery="false" value="r5fss0-0" valueType="string"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.sysConfig.OTHER_FLAGS.1934836442" name="Other flags" superClass="com.ti.ccstudio.buildDefinitions.sysConfig.OTHER_FLAGS" useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="--part Default"/>
+									<listOptionValue builtIn="false" value="--package ALV"/>
+								</option>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="sciclient_ccs_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang.com.ti.ccstudio.buildDefinitions.TMS470.ProjectType.1106552353" name="TMS470" projectType="com.ti.ccstudio.buildDefinitions.TMS470.ProjectType"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+</cproject>
--- a/utils/ddr_init/ddr_init_fw/.gitignore
+++ b/utils/ddr_init/ddr_init_fw/.gitignore
@ -0,0 +1,2 @@
+/Debug
+/Release
--- a/utils/ddr_init/ddr_init_fw/.project
+++ b/utils/ddr_init/ddr_init_fw/.project
@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>ddr_init</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.ti.ccstudio.core.ccsNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<variableList>
+		<variable>
+			<name>MCU_PLUS_SDK_PATH</name>
+			<value>$%7BCOM_TI_MCU_PLUS_SDK_AM64X_INSTALL_DIR%7D</value>
+		</variable>
+	</variableList>
+</projectDescription>
--- a/utils/ddr_init/ddr_init_fw/.settings/org.eclipse.cdt.codan.core.prefs
+++ b/utils/ddr_init/ddr_init_fw/.settings/org.eclipse.cdt.codan.core.prefs
@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
--- a/utils/ddr_init/ddr_init_fw/.settings/org.eclipse.cdt.debug.core.prefs
+++ b/utils/ddr_init/ddr_init_fw/.settings/org.eclipse.cdt.debug.core.prefs
@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
--- a/utils/ddr_init/ddr_init_fw/.settings/org.eclipse.core.resources.prefs
+++ b/utils/ddr_init/ddr_init_fw/.settings/org.eclipse.core.resources.prefs
@ -0,0 +1,11 @@
+eclipse.preferences.version=1
+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
+encoding//Debug/subdir_rules.mk=UTF-8
+encoding//Debug/subdir_vars.mk=UTF-8
+encoding//Release/makefile=UTF-8
+encoding//Release/objects.mk=UTF-8
+encoding//Release/sources.mk=UTF-8
+encoding//Release/subdir_rules.mk=UTF-8
+encoding//Release/subdir_vars.mk=UTF-8
--- a/utils/ddr_init/ddr_init_fw/am64x_xds560v2.ccxml
+++ b/utils/ddr_init/ddr_init_fw/am64x_xds560v2.ccxml
@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configurations XML_version="1.2" id="configurations_0">
+    
+    <configuration XML_version="1.2" id="Spectrum Digital XDS560V2 STM USB Emulator_0">
+        <instance XML_version="1.2" desc="Spectrum Digital XDS560V2 STM USB Emulator_0" href="connections/SD560V2USB_Connection.xml" id="Spectrum Digital XDS560V2 STM USB Emulator_0" xml="SD560V2USB_Connection.xml" xmlpath="connections"/>
+        <connection XML_version="1.2" id="Spectrum Digital XDS560V2 STM USB Emulator_0">
+            <instance XML_version="1.2" href="drivers/tixds560cs_dap.xml" id="drivers" xml="tixds560cs_dap.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560cortexA53.xml" id="drivers" xml="tixds560cortexA53.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560cortexR.xml" id="drivers" xml="tixds560cortexR.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560cortexM.xml" id="drivers" xml="tixds560cortexM.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560pru.xml" id="drivers" xml="tixds560pru.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560csstm.xml" id="drivers" xml="tixds560csstm.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560ctset2.xml" id="drivers" xml="tixds560ctset2.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds560etbcs.xml" id="drivers" xml="tixds560etbcs.xml" xmlpath="drivers"/>
+            <platform XML_version="1.2" id="platform_0">
+                <instance XML_version="1.2" desc="AM64x_0" href="devices/AM64x.xml" id="AM64x_0" xml="AM64x.xml" xmlpath="devices"/>
+            </platform>
+        </connection>
+    </configuration>
+</configurations>
--- a/utils/ddr_init/ddr_init_fw/ddr_init.rprc
+++ b/utils/ddr_init/ddr_init_fw/ddr_init.rprc
--- a/utils/ddr_init/ddr_init_fw/example.syscfg
+++ b/utils/ddr_init/ddr_init_fw/example.syscfg
@ -0,0 +1,59 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM64x@08.05.00"
+ * @versions {"tool":"1.15.0+2826"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const ddr        = scripting.addModule("/drivers/ddr/ddr", {}, false);
+const ddr1       = ddr.addInstance();
+const watchdog   = scripting.addModule("/drivers/watchdog/watchdog", {}, false);
+const watchdog1  = watchdog.addInstance();
+const debug_log  = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7  = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+const mpu_armv76 = mpu_armv7.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+ddr1.$name = "CONFIG_DDR0";
+
+watchdog1.$name          = "CONFIG_WDT0";
+watchdog1.expirationTime = 10;
+
+mpu_armv71.$name             = "CONFIG_MPU_REGION0";
+mpu_armv71.size              = 31;
+mpu_armv71.attributes        = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv71.allowExecute      = false;
+
+mpu_armv72.$name             = "CONFIG_MPU_REGION1";
+mpu_armv72.size              = 15;
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv73.$name             = "CONFIG_MPU_REGION2";
+mpu_armv73.baseAddr          = 0x41010000;
+mpu_armv73.size              = 15;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name             = "CONFIG_MPU_REGION3";
+mpu_armv74.baseAddr          = 0x70000000;
+mpu_armv74.size              = 21;
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv75.$name             = "CONFIG_MPU_REGION4";
+mpu_armv75.baseAddr          = 0x60000000;
+mpu_armv75.size              = 28;
+mpu_armv75.accessPermissions = "Supervisor RD, User RD";
+
+mpu_armv76.$name    = "CONFIG_MPU_REGION5";
+mpu_armv76.baseAddr = 0x80000000;
+mpu_armv76.size     = 31;
--- a/utils/ddr_init/ddr_init_fw/linker.cmd
+++ b/utils/ddr_init/ddr_init_fw/linker.cmd
@ -0,0 +1,148 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ *   uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors  /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256;  /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256;  /* This is the size of stack when R5 is in UNDEF mode */
+
+SECTIONS
+{
+    /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+    .vectors:{} palign(8) > R5F_VECS
+
+    /* This has the R5F boot code until MPU is enabled,  this MUST be at a address < 0x80000000
+     * i.e this cannot be placed in DDR
+     */
+    GROUP {
+        .text.hwi: palign(8)
+        .text.cache: palign(8)
+        .text.mpu: palign(8)
+        .text.boot: palign(8)
+        .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+    } > MSRAM
+
+    /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .text:   {} palign(8)   /* This is where code resides */
+        .rodata: {} palign(8)   /* This is where const's go */
+    } > MSRAM
+
+    /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .data:   {} palign(8)   /* This is where initialized globals and static go */
+    } > MSRAM
+
+    /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .bss:    {} palign(8)   /* This is where uninitialized globals go */
+        RUN_START(__BSS_START)
+        RUN_END(__BSS_END)
+        .sysmem: {} palign(8)   /* This is where the malloc heap goes */
+        .stack:  {} palign(8)   /* This is where the main() stack goes */
+    } > MSRAM
+
+    /* This is where the stacks for different R5F modes go */
+    GROUP {
+        .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+        RUN_START(__IRQ_STACK_START)
+        RUN_END(__IRQ_STACK_END)
+        .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+        RUN_START(__FIQ_STACK_START)
+        RUN_END(__FIQ_STACK_END)
+        .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+        RUN_START(__SVC_STACK_START)
+        RUN_END(__SVC_STACK_END)
+        .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+        RUN_START(__ABORT_STACK_START)
+        RUN_END(__ABORT_STACK_END)
+        .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+        RUN_START(__UNDEFINED_STACK_START)
+        RUN_END(__UNDEFINED_STACK_END)
+    } > MSRAM
+
+    /* Sections needed for C++ projects */
+    GROUP {
+        .ARM.exidx:  {} palign(8)   /* Needed for C++ exception handling */
+        .init_array: {} palign(8)   /* Contains function pointers called before main */
+        .fini_array: {} palign(8)   /* Contains function pointers called after main */
+    } > MSRAM
+
+    /* General purpose user shared memory, used in some examples */
+    .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+    /* this is used when Debug log's to shared memory are enabled, else this is not used */
+    .bss.log_shared_mem  (NOLOAD) : {} > LOG_SHM_MEM
+    /* this is used only when IPC RPMessage is enabled, else this is not used */
+    .bss.ipc_vring_mem   (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+    /* General purpose non cacheable memory, used in some examples */
+    .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+   0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+   0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+   TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+    R5F_VECS  : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+    R5F_TCMA  : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+    R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+    /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+    NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+    /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+     * this memory does not overlap with other R5F's
+     */
+    MSRAM     : ORIGIN = 0x70080000 , LENGTH = 0x80000
+
+    /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+     * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+     */
+    FLASH     : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+    /* shared memory segments */
+    /* On R5F,
+     * - make sure there is a MPU entry which maps below regions as non-cache
+     */
+    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x80
+    LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
+    RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}
--- a/utils/ddr_init/ddr_init_fw/main.c
+++ b/utils/ddr_init/ddr_init_fw/main.c
@ -0,0 +1,48 @@
+/*
+ *  Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "ti_drivers_open_close.h"
+#include "ti_board_open_close.h"
+
+int main(void)
+{
+    System_init();
+    Board_init();
+
+    DebugP_log("[ddr_init]: DDR Initialization completed.\r\n");
+    DebugP_log("[ddr_init]: Please wait while the cpu reboots\r\n");
+
+    return 0;
+}
--- a/utils/ddr_init/ddr_init_fw/makefile_ccs_bootimage_gen
+++ b/utils/ddr_init/ddr_init_fw/makefile_ccs_bootimage_gen
@ -0,0 +1,107 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MCU_PLUS_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include $(MCU_PLUS_SDK_PATH)/imports.mak
+include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_a53ss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
+else
+  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+#	No post build steps
+else
+	@echo  Boot image: am64x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
+	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+	@echo Boot image signing: Encryption is disabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+	$(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+	@echo  Boot image: am64x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+	@echo  .
+ifeq ($(DEVICE_TYPE),HS)
+	@echo  Boot image: am64x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+	@echo  .
+else
+	@echo  Boot image: am64x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo  .
+endif
+endif
--- a/utils/ddr_init/ddr_init_fw/targetConfigs/AM64x.ccxml
+++ b/utils/ddr_init/ddr_init_fw/targetConfigs/AM64x.ccxml
@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configurations XML_version="1.2" id="configurations_0">
+        
+    <configuration XML_version="1.2" id="configuration_0">
+                
+        <instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
+                
+        <connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
+                        
+            <instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
+                        
+            <instance XML_version="1.2" href="drivers/tixds510cortexA53.xml" id="drivers" xml="tixds510cortexA53.xml" xmlpath="drivers"/>
+                        
+            <instance XML_version="1.2" href="drivers/tixds510cortexR.xml" id="drivers" xml="tixds510cortexR.xml" xmlpath="drivers"/>
+                        
+            <instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
+                        
+            <instance XML_version="1.2" href="drivers/tixds510pru.xml" id="drivers" xml="tixds510pru.xml" xmlpath="drivers"/>
+                        
+            <instance XML_version="1.2" href="drivers/tixds510csstm.xml" id="drivers" xml="tixds510csstm.xml" xmlpath="drivers"/>
+                        
+            <instance XML_version="1.2" href="drivers/tixds510ctset2.xml" id="drivers" xml="tixds510ctset2.xml" xmlpath="drivers"/>
+                        
+            <instance XML_version="1.2" href="drivers/tixds510etbcs.xml" id="drivers" xml="tixds510etbcs.xml" xmlpath="drivers"/>
+                        
+            <platform XML_version="1.2" id="platform_0">
+                                
+                <instance XML_version="1.2" desc="AM64x" href="devices/AM64x.xml" id="AM64x" xml="AM64x.xml" xmlpath="devices"/>
+                            
+            </platform>
+                    
+        </connection>
+            
+    </configuration>
+    
+</configurations>
--- a/utils/ddr_init/ddr_init_fw/targetConfigs/readme.txt
+++ b/utils/ddr_init/ddr_init_fw/targetConfigs/readme.txt
@ -0,0 +1,9 @@
+The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based
+on the device and connection settings specified in your project on the Properties > General page.
+
+Please note that in automatic target-configuration management, changes to the project's device and/or
+connection settings will either modify an existing or generate a new target-configuration file. Thus,
+if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
+you may create your own target-configuration file for this project and manage it manually. You can
+always switch back to automatic target-configuration management by checking the "Manage the project's
+target-configuration automatically" checkbox on the project's Properties > General page.
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.ccsproject
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.ccsproject
@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<?ccsproject version="1.0"?>
+<projectOptions>
+	<ccsVersion value="11.2.0"/>
+	<deviceVariant value="Cortex R.AM64x"/>
+	<deviceFamily value="TMS470"/>
+	<deviceEndianness value="little"/>
+	<codegenToolVersion value="TICLANG_2.1.2.LTS"/>
+	<isElfFormat value="true"/>
+	<connection value="common/targetdb/connections/TIXDS110_Connection.xml"/>
+	<rts value=""/>
+	<createSlaveProjects value=""/>
+	<ignoreDefaultDeviceSettings value="true"/>
+	<ignoreDefaultCCSSettings value="true"/>
+	<templateProperties value="id=example.projectspec.sbl_sd_am64x-evm_r5fss0-0_nortos_ti-arm-clang"/>
+	<origin value="/home/algin/ti/mcu_plus_sdk_am64x_08_05_00_24/examples/drivers/boot/sbl_sd/am64x-evm/r5fss0-0_nortos/ti-arm-clang/example.projectspec"/>
+	<filesToOpen value=""/>
+	<isTargetManual value="false"/>
+</projectOptions>
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.cproject
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.cproject
@ -0,0 +1,242 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.1573602807">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.1573602807" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.ti.ccstudio.errorparser.SysConfigErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.1573602807" name="Debug" parent="com.ti.ccstudio.buildDefinitions.TMS470.Debug" postbuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE}">
+					<folderInfo id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.1573602807." name="/" resourcePath="">
+						<toolChain id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.DebugToolchain.2018376097" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.linkerDebug.1434451427">
+							<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1392911935" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+								<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=Cortex R.AM64x"/>
+								<listOptionValue builtIn="false" value="DEVICE_CORE_ID=MAIN_PULSAR_Cortex_R5_0_0"/>
+								<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+								<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
+								<listOptionValue builtIn="false" value="CCS_MBS_VERSION=6.1.3"/>
+								<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY="/>
+								<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
+								<listOptionValue builtIn="false" value="PRODUCTS=sysconfig:1.15.0;com.ti.MCU_PLUS_SDK_AM64X:8.5.0.24;"/>
+								<listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={&quot;com.ti.MCU_PLUS_SDK_AM64X&quot;:[&quot;${COM_TI_MCU_PLUS_SDK_AM64X_INCLUDE_PATH}&quot;,&quot;${COM_TI_MCU_PLUS_SDK_AM64X_LIBRARY_PATH}&quot;,&quot;${COM_TI_MCU_PLUS_SDK_AM64X_LIBRARIES}&quot;,&quot;${COM_TI_MCU_PLUS_SDK_AM64X_SYMBOLS}&quot;,&quot;${COM_TI_MCU_PLUS_SDK_AM64X_SYSCONFIG_MANIFEST}&quot;],&quot;sysconfig&quot;:[&quot;${SYSCONFIG_TOOL_INCLUDE_PATH}&quot;,&quot;${SYSCONFIG_TOOL_LIBRARY_PATH}&quot;,&quot;${SYSCONFIG_TOOL_LIBRARIES}&quot;,&quot;${SYSCONFIG_TOOL_SYMBOLS}&quot;,&quot;${SYSCONFIG_TOOL_SYSCONFIG_MANIFEST}&quot;]}"/>
+							</option>
+							<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.820822261" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="TICLANG_2.1.2.LTS" valueType="string"/>
+							<targetPlatform id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.targetPlatformDebug.1458643401" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.targetPlatformDebug"/>
+							<builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.builderDebug.1244306652" keepEnvironmentInBuildfile="false" name="GNU Make" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.builderDebug"/>
+							<tool id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.compilerDebug.564819187" name="Arm Compiler" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.compilerDebug">
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+								<option id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.GENERATE_DWARF_DEBUG.1673937611" name="Generate DWARF debug" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.GENERATE_DWARF_DEBUG" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.GENERATE_DWARF_DEBUG.G_LOWERCASE" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.ENDIAN_NESS__BIG_LITTLE.2075581569" name="Endian-ness (big/little) [See 'General' page to edit]" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.ENDIAN_NESS__BIG_LITTLE" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.ENDIAN_NESS__BIG_LITTLE.MLITTLE_ENDIAN" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.INCLUDE_PATH.517059568" name="Add dir to #include search path (-I)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.INCLUDE_PATH" valueType="includePath">
+									<listOptionValue builtIn="false" value="${SYSCONFIG_TOOL_INCLUDE_PATH}"/>
+									<listOptionValue builtIn="false" value="${COM_TI_MCU_PLUS_SDK_AM64X_INCLUDE_PATH}"/>
+									<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include/c"/>
+									<listOptionValue builtIn="false" value="${MCU_PLUS_SDK_PATH}/source"/>
+									<listOptionValue builtIn="false" value="${MCU_PLUS_SDK_PATH}/source/fs/freertos_fat/FreeRTOS-FAT/include"/>
+									<listOptionValue builtIn="false" value="${MCU_PLUS_SDK_PATH}/source/fs/freertos_fat/portable"/>
+									<listOptionValue builtIn="false" value="${MCU_PLUS_SDK_PATH}/source/fs/freertos_fat/portable/nortos"/>
+									<listOptionValue builtIn="false" value="${MCU_PLUS_SDK_PATH}/source/fs/freertos_fat/config"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.DEFINE.1279973236" name="Pre-define NAME (-D)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.DEFINE" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="${SYSCONFIG_TOOL_SYMBOLS}"/>
+									<listOptionValue builtIn="false" value="${COM_TI_MCU_PLUS_SDK_AM64X_SYMBOLS}"/>
+									<listOptionValue builtIn="false" value="SOC_AM64X"/>
+									<listOptionValue builtIn="false" value="_DEBUG_=1"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.MCPU.1213800729" name="Select ARM processor variant (-mcpu)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.MCPU" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.MCPU.cortex-r5" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.MFLOAT_ABI.30290720" name="Select assumed floating-point ABI (-mfloat-abi)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.MFLOAT_ABI" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.MFLOAT_ABI.hard" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.MFPU.310258754" name="Select floating-point hardware processor (-mfpu)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.MFPU" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compilerID.MFPU.vfpv3-d16" valueType="enumerated"/>
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+									<listOptionValue builtIn="false" value="gnu-variable-sized-type-not-at-end"/>
+									<listOptionValue builtIn="false" value="unused-function"/>
+								</option>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compiler.inputType__C_SRCS.837183244" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compiler.inputType__C_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compiler.inputType__CPP_SRCS.1846113689" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compiler.inputType__CPP_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compiler.inputType__ASM_SRCS.1107798962" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compiler.inputType__ASM_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compiler.inputType__ASM2_SRCS.411545211" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.compiler.inputType__ASM2_SRCS"/>
+							</tool>
+							<tool id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.linkerDebug.1434451427" name="Arm Linker" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exe.linkerDebug">
+								<option id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.OUTPUT_FILE.1470704011" name="Specify output file name (--output_file, -o)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.OUTPUT_FILE" useByScannerDiscovery="false" value="${ProjName}.out" valueType="string"/>
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+									<listOptionValue builtIn="false" value="10063"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.INITIALIZATION_MODEL.1670153414" name="Initialization model" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.INITIALIZATION_MODEL" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.linkerID.INITIALIZATION_MODEL.RAM_MODEL" valueType="enumerated"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__CMD_SRCS.132114698" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__CMD_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__CMD2_SRCS.274634623" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__CMD2_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__GEN_CMDS.1891686356" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.exeLinker.inputType__GEN_CMDS"/>
+							</tool>
+							<tool id="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.hex.788917200" name="Arm Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.TMS470_TICLANG_2.0.hex"/>
+							<tool id="com.ti.ccstudio.buildDefinitions.sysConfig.736852246" name="SysConfig" superClass="com.ti.ccstudio.buildDefinitions.sysConfig">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.sysConfig.PRODUCTS.1542056416" name="Root system config meta data file in a product or SDK (-s, --product)" superClass="com.ti.ccstudio.buildDefinitions.sysConfig.PRODUCTS" useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="${SYSCONFIG_TOOL_SYSCONFIG_MANIFEST}"/>
+									<listOptionValue builtIn="false" value="${COM_TI_MCU_PLUS_SDK_AM64X_SYSCONFIG_MANIFEST}"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.sysConfig.CONTEXT.1431197764" name="Name of the context (core name or 'system') to target (-e, --context)" superClass="com.ti.ccstudio.buildDefinitions.sysConfig.CONTEXT" useByScannerDiscovery="false" value="r5fss0-0" valueType="string"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.sysConfig.OTHER_FLAGS.309656358" name="Other flags" superClass="com.ti.ccstudio.buildDefinitions.sysConfig.OTHER_FLAGS" useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="--part Default"/>
+									<listOptionValue builtIn="false" value="--package ALV"/>
+								</option>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="sbl_sd_am64x-evm_r5fss0-0_nortos_ti-arm-clang.com.ti.ccstudio.buildDefinitions.TMS470.ProjectType.1038690225" name="TMS470" projectType="com.ti.ccstudio.buildDefinitions.TMS470.ProjectType"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+</cproject>
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.gitignore
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.gitignore
@ -0,0 +1,2 @@
+/Debug/
+/Release/
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.project
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.project
@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.ti.ccstudio.core.ccsNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>README.html</name>
+			<type>1</type>
+			<locationURI>MCU_PLUS_SDK_PATH/docs/api_guide_am64x/EXAMPLES_DRIVERS_SBL_UART.html</locationURI>
+		</link>
+	</linkedResources>
+	<variableList>
+		<variable>
+			<name>MCU_PLUS_SDK_PATH</name>
+			<value>$%7BCOM_TI_MCU_PLUS_SDK_AM64X_INSTALL_DIR%7D</value>
+		</variable>
+	</variableList>
+</projectDescription>
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.settings/org.eclipse.cdt.codan.core.prefs
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.settings/org.eclipse.cdt.codan.core.prefs
@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.settings/org.eclipse.cdt.debug.core.prefs
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.settings/org.eclipse.cdt.debug.core.prefs
@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.settings/org.eclipse.core.resources.prefs
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/.settings/org.eclipse.core.resources.prefs
@ -0,0 +1,11 @@
+eclipse.preferences.version=1
+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
+encoding//Debug/subdir_rules.mk=UTF-8
+encoding//Debug/subdir_vars.mk=UTF-8
+encoding//Release/makefile=UTF-8
+encoding//Release/objects.mk=UTF-8
+encoding//Release/sources.mk=UTF-8
+encoding//Release/subdir_rules.mk=UTF-8
+encoding//Release/subdir_vars.mk=UTF-8
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/example.syscfg
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/example.syscfg
@ -0,0 +1,85 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01"
+ * @versions {"tool":"1.14.0+2667"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const bootloader    = scripting.addModule("/drivers/bootloader/bootloader", {}, false);
+const bootloader1   = bootloader.addInstance();
+const ddr           = scripting.addModule("/drivers/ddr/ddr", {}, false);
+const ddr1          = ddr.addInstance();
+const freertos_fat  = scripting.addModule("/fs/freertos_fat/freertos_fat", {}, false);
+const freertos_fat1 = freertos_fat.addInstance();
+const debug_log     = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7     = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71    = mpu_armv7.addInstance();
+const mpu_armv72    = mpu_armv7.addInstance();
+const mpu_armv73    = mpu_armv7.addInstance();
+const mpu_armv74    = mpu_armv7.addInstance();
+const mpu_armv75    = mpu_armv7.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+bootloader1.$name     = "CONFIG_BOOTLOADER_MEM";
+bootloader1.bootMedia = "MEM";
+
+ddr1.$name = "CONFIG_DDR0";
+
+freertos_fat1.$name                     = "CONFIG_FREERTOS_FAT0";
+freertos_fat1.peripheralDriver.$name    = "CONFIG_MMCSD0";
+freertos_fat1.peripheralDriver.cardType = "SD";
+freertos_fat1.peripheralDriver.phyType  = "SW_PHY";
+
+debug_log.enableCssLog         = false;
+debug_log.enableUartLog        = true;
+debug_log.enableLogZoneWarning = false;
+debug_log.uartLog.$name        = "CONFIG_UART0";
+debug_log.uartLog.intrEnable   = "DISABLE";
+
+mpu_armv71.$name             = "CONFIG_MPU_REGION0";
+mpu_armv71.size              = 31;
+mpu_armv71.attributes        = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv71.allowExecute      = false;
+
+mpu_armv72.$name             = "CONFIG_MPU_REGION1";
+mpu_armv72.size              = 15;
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv73.$name             = "CONFIG_MPU_REGION2";
+mpu_armv73.baseAddr          = 0x41010000;
+mpu_armv73.size              = 15;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name             = "CONFIG_MPU_REGION3";
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv74.baseAddr          = 0x70000000;
+mpu_armv74.size              = 21;
+
+mpu_armv75.$name             = "CONFIG_MPU_REGION4";
+mpu_armv75.baseAddr          = 0x80000000;
+mpu_armv75.size              = 31;
+mpu_armv75.accessPermissions = "Supervisor RD+WR, User RD";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+freertos_fat1.peripheralDriver.MMC1.$suggestSolution       = "MMC1";
+freertos_fat1.peripheralDriver.MMC1.CLK.$suggestSolution   = "ball.L20";
+freertos_fat1.peripheralDriver.MMC1.CLKLB.$suggestSolution = "MMC1_CLKLB";
+freertos_fat1.peripheralDriver.MMC1.CMD.$suggestSolution   = "ball.J19";
+freertos_fat1.peripheralDriver.MMC1.DAT0.$suggestSolution  = "ball.K21";
+freertos_fat1.peripheralDriver.MMC1.DAT1.$suggestSolution  = "ball.L21";
+freertos_fat1.peripheralDriver.MMC1.DAT2.$suggestSolution  = "ball.K19";
+freertos_fat1.peripheralDriver.MMC1.DAT3.$suggestSolution  = "ball.K18";
+freertos_fat1.peripheralDriver.MMC1.SDCD.$suggestSolution  = "ball.D19";
+debug_log.uartLog.UART.$suggestSolution                    = "USART0";
+debug_log.uartLog.UART.RXD.$suggestSolution                = "ball.D15";
+debug_log.uartLog.UART.TXD.$suggestSolution                = "ball.C16";
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/linker.cmd
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/linker.cmd
@ -0,0 +1,74 @@
+
+--stack_size=16384
+--heap_size=32768
+-e_vectors_sbl  /* for SBL make sure to set entry point to _vectors_sbl */
+
+__IRQ_STACK_SIZE = 4096;
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 256;
+__ABORT_STACK_SIZE = 256;
+__UNDEFINED_STACK_SIZE = 256;
+
+SECTIONS
+{
+    .vectors:{} palign(8) > MSRAM_VECS
+    GROUP {
+        .text:   {} palign(8)
+        .text.hwi: palign(8)
+        .text.cache: palign(8)
+        .text.mpu: palign(8)
+        .text.boot: palign(8)
+        .data:   {} palign(8)
+        .rodata: {} palign(8)
+    } > MSRAM_0
+    .bss:    {} palign(8) > MSRAM_1
+    RUN_START(__BSS_START)
+    RUN_END(__BSS_END)
+    .sysmem: {} palign(8) > MSRAM_1
+    .stack:  {} palign(8) > MSRAM_1
+    GROUP {
+        .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+        RUN_START(__IRQ_STACK_START)
+        RUN_END(__IRQ_STACK_END)
+        .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+        RUN_START(__FIQ_STACK_START)
+        RUN_END(__FIQ_STACK_END)
+        .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+        RUN_START(__SVC_STACK_START)
+        RUN_END(__SVC_STACK_END)
+        .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+        RUN_START(__ABORT_STACK_START)
+        RUN_END(__ABORT_STACK_END)
+        .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+        RUN_START(__UNDEFINED_STACK_START)
+        RUN_END(__UNDEFINED_STACK_END)
+    } > MSRAM_1
+
+    .bss.filebuf (NOLOAD) : {} > DDR
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+   0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+   0x701FC000 - 0x701FFFFF (16KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+   TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+    R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+    R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+    R5F_TCMB0: ORIGIN = 0x41010000 , LENGTH = 0x00008000
+    MSRAM_VECS: ORIGIN = 0x70000000 , LENGTH = 0x100
+    MSRAM_0  : ORIGIN = 0x70000100 , LENGTH = 0x70000 - 0x100
+    MSRAM_1  : ORIGIN = 0x70070000 , LENGTH = 0x10000
+    MSRAM_2  : ORIGIN = 0x70160000 , LENGTH = 0x80000
+    DDR      : ORIGIN = 0x808A0000 , LENGTH = 0x150000
+}
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/main.c
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/main.c
@ -0,0 +1,308 @@
+/*
+ *  Copyright (C) 2018-2022 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Auto generated file
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include "ti_drivers_config.h"
+#include "ti_drivers_open_close.h"
+#include "ti_board_open_close.h"
+#include <drivers/sciclient.h>
+#include <drivers/bootloader.h>
+
+#define BOOTLOADER_SD_APPIMAGE_FILENAME ("/sd0/app")
+
+#define BOOTLOADER_APPIMAGE_MAX_FILE_SIZE (0x150000) /* Size of section MSRAM_2 specified in linker.cmd */
+uint8_t gAppImageBuf[BOOTLOADER_APPIMAGE_MAX_FILE_SIZE] __attribute__((aligned(128), section(".bss.filebuf")));
+
+/* call this API to stop the booting process and spin, do that you can connect
+ * debugger, load symbols and then make the 'loop' variable as 0 to continue execution
+ * with debugger connected.
+ */
+void loop_forever(void)
+{
+    volatile uint32_t loop = 1;
+    while(loop)
+        ;
+}
+
+int main(void)
+{
+    int32_t status;
+
+    Bootloader_profileReset();
+
+    Bootloader_socWaitForFWBoot();
+
+#ifndef DISABLE_WARM_REST_WA
+    /* Warm Reset Workaround to prevent CPSW register lockup */
+    if (!Bootloader_socIsMCUResetIsoEnabled())
+    {
+        Bootloader_socResetWorkaround();
+    }
+#endif
+
+    Bootloader_profileAddProfilePoint("SYSFW init");
+
+    if (!Bootloader_socIsMCUResetIsoEnabled())
+    {
+        /* Update devGrp to ALL to initialize MCU domain when reset isolation is
+        not enabled */
+        Sciclient_BoardCfgPrms_t boardCfgPrms_pm =
+            {
+                .boardConfigLow = (uint32_t)0,
+                .boardConfigHigh = 0,
+                .boardConfigSize = 0,
+                .devGrp = DEVGRP_ALL,
+            };
+
+        status = Sciclient_boardCfgPm(&boardCfgPrms_pm);
+        if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+
+        /* Enable MCU PLL. MCU PLL will not be enabled by DMSC when devGrp is set
+        to Main in boardCfg */
+        Bootloader_enableMCUPLL();
+    }
+
+    Bootloader_socOpenFirewalls();
+
+    Bootloader_socNotifyFirewallOpen();
+
+    System_init();
+    Bootloader_profileAddProfilePoint("System_init");
+
+    Drivers_open();
+    Bootloader_profileAddProfilePoint("Drivers_open");
+
+    #if 1
+    DebugP_log("\r\n");
+    DebugP_log("Starting SD Bootloader ... \r\n");
+    #endif
+
+    status = Board_driversOpen();
+    if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+    DebugP_assert(status == SystemP_SUCCESS);
+    Bootloader_profileAddProfilePoint("Board_driversOpen");
+
+    status = Sciclient_getVersionCheck(1);
+    if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+    Bootloader_profileAddProfilePoint("Sciclient Get Version");
+    /* File I/O */
+    if(SystemP_SUCCESS == status)
+    {
+        /* Open app file */
+        FF_FILE *appFp = ff_fopen(BOOTLOADER_SD_APPIMAGE_FILENAME, "rb");
+
+        /* Check if file open succeeded */
+        if(appFp == NULL)
+        {
+            status =  SystemP_FAILURE;
+            if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+        }
+        else
+        {
+            /* Check file size */
+            uint32_t fileSize = ff_filelength(appFp);
+
+            if(fileSize >= BOOTLOADER_APPIMAGE_MAX_FILE_SIZE)
+            {
+                /* Application size more than buffer size, abort */
+                status = SystemP_FAILURE;
+                DebugP_log("Appimage size exceeded limit !!\r\n");
+            }
+            else
+            {
+                /* Read the file into RAM buffer */
+                ff_fread(gAppImageBuf, fileSize, 1, appFp);
+            }
+
+            /* Close the file */
+            ff_fclose(appFp);
+        }
+    }
+    Bootloader_profileAddProfilePoint("File read from SD card");
+
+    if(SystemP_SUCCESS == status)
+    {
+        Bootloader_BootImageInfo bootImageInfo;
+        Bootloader_Params bootParams;
+        Bootloader_Handle bootHandle;
+
+        Bootloader_Params_init(&bootParams);
+        Bootloader_BootImageInfo_init(&bootImageInfo);
+
+        bootParams.memArgsAppImageBaseAddr = (uintptr_t)gAppImageBuf;
+
+        bootHandle = Bootloader_open(CONFIG_BOOTLOADER_MEM, &bootParams);
+        if(bootHandle != NULL)
+        {
+            status = Bootloader_parseMultiCoreAppImage(bootHandle, &bootImageInfo);
+            if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            /* Load CPUs */
+            /* Do not load M4 when MCU domain is reset isolated */
+            if (!Bootloader_socIsMCUResetIsoEnabled())
+            {
+                if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_M4FSS0_0)))
+                {
+                    bootImageInfo.cpuInfo[CSL_CORE_ID_M4FSS0_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_M4FSS0_0);
+                    Bootloader_profileAddCore(CSL_CORE_ID_M4FSS0_0);
+                    status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_M4FSS0_0]);
+                    if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+                }
+            }
+            if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_0)))
+            {
+                bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS1_0);
+                Bootloader_profileAddCore(CSL_CORE_ID_R5FSS1_0);
+                status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0]);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            }
+            if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_1)))
+            {
+                bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_1].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS1_1);
+                Bootloader_profileAddCore(CSL_CORE_ID_R5FSS1_1);
+                status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_1]);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            }
+            if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_A53SS0_0)))
+            {
+                bootImageInfo.cpuInfo[CSL_CORE_ID_A53SS0_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_A53SS0_0);
+                Bootloader_profileAddCore(CSL_CORE_ID_A53SS0_0);
+                status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_A53SS0_0]);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            }
+            if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_A53SS0_1)))
+            {
+                bootImageInfo.cpuInfo[CSL_CORE_ID_A53SS0_1].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_A53SS0_1);
+                Bootloader_profileAddCore(CSL_CORE_ID_A53SS0_1);
+                status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_A53SS0_1]);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            }
+
+            /* Assume self boot for either of the cores of R50 cluster */
+            uint32_t isSelfBoot = FALSE;
+            if(TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_0))
+            {
+                isSelfBoot = TRUE;
+                Bootloader_profileAddCore(CSL_CORE_ID_R5FSS0_0);
+            }
+
+            if(TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_1))
+            {
+                isSelfBoot = TRUE;
+                Bootloader_profileAddCore(CSL_CORE_ID_R5FSS0_1);
+            }
+
+            /* Self cores has to be reset together, so check for both */
+            if(status == SystemP_SUCCESS && (TRUE == isSelfBoot))
+            {
+                /* Set clocks for self cluster */
+                bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS0_0);
+                bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_1].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS0_1);
+
+                /* Reset self cluster, both Core0 and Core 1. Init RAMs and load the app  */
+                status = Bootloader_loadSelfCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0]);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+                if(status == SystemP_SUCCESS)
+                {
+                    status = Bootloader_loadSelfCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_1]);
+                    if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+                }
+            }
+            Bootloader_profileAddProfilePoint("CPU load");
+            Bootloader_profileUpdateAppimageSize(Bootloader_getMulticoreImageSize(bootHandle));
+            Bootloader_profileUpdateMediaAndClk(BOOTLOADER_MEDIA_SD, 0);
+
+            if(status == SystemP_SUCCESS)
+            {
+                /* Print SBL Profiling logs to UART as other cores may use the UART for logging */
+                Bootloader_profileAddProfilePoint("SBL End");
+                Bootloader_profilePrintProfileLog();
+                DebugP_log("Image loading done, switching to application ...\r\n");
+                UART_flushTxFifo(gUartHandle[CONFIG_UART0]);
+            }
+
+            /* Run CPUs */
+            /* Do not run M4 when MCU domain is reset isolated */
+            if (!Bootloader_socIsMCUResetIsoEnabled())
+            {
+                if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_M4FSS0_0)))
+                {
+                    status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_M4FSS0_0]);
+                    if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+                }
+            }
+            if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_0)))
+            {
+                status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0]);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            }
+            if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_1)))
+            {
+                status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_1]);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            }
+            if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_A53SS0_0)))
+            {
+                status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_A53SS0_0]);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            }
+            if(status == SystemP_SUCCESS && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_A53SS0_1)))
+            {
+                status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_A53SS0_1]);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            }
+            if(status == SystemP_SUCCESS)
+            {
+                /* Reset self cluster, both Core0 and Core 1. Init RAMs and run the app  */
+                status = Bootloader_runSelfCpu(bootHandle, &bootImageInfo);
+                if(status != SystemP_SUCCESS) DebugP_log("Line: %d\r\n", __LINE__);
+            }
+
+            /* it should not return here, if it does, then there was some error */
+            Bootloader_close(bootHandle);
+        }
+    }
+    if(status != SystemP_SUCCESS)
+    {
+        DebugP_log("Some tests have failed!!\r\n");
+    }
+    Drivers_close();
+    System_deinit();
+
+    return 0;
+}
+
+
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/makefile_ccs_bootimage_gen
@ -0,0 +1,79 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MCU_PLUS_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include $(MCU_PLUS_SDK_PATH)/imports.mak
+include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME_GP:=$(BOOTIMAGE_PATH)/$(OUTNAME).tiimage
+BOOTIMAGE_NAME_HS:=sbl_sd_ddr_init.$(PROFILE).hs.tiimage
+BOOTIMAGE_NAME_HS_FS:=sbl_sd_ddr_init.$(PROFILE).hs_fs.tiimage
+ifeq ($(DEVICE_TYPE),HS)
+	BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_HS)
+else
+	BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_GP)
+endif
+BOOTIMAGE_BIN_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).bin
+
+#
+# Generation of boot image which can be loaded by ROM Boot Loader (RBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/rom_image_gen.py
+SYSFW_PATH=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/soc/am64x_am243x
+SYSFW_LOAD_ADDR=0x44000
+BOARDCFG_LOAD_ADDR=0x7B000
+BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am64x_am243x/boardcfg_blob.bin
+
+SBL_RUN_ADDRESS=0x70000000
+
+SBL_PREBUILT_PATH=$(MCU_PLUS_SDK_PATH)/tools/boot/sbl_prebuilt/am64x-evm
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+#	No post build steps
+else
+	@echo  Boot image: am64x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_NAME) ...
+	$(OBJCOPY) --strip-sections -O binary $(OUTFILE) $(BOOTIMAGE_BIN_NAME)
+ifeq ($(DEVICE_TYPE),HS)
+	$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --debug DBG_FULL_ENABLE --rom-image $(BOOTIMAGE_NAME)
+else
+	$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-fs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-fs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS)
+	$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_NAME)
+endif
+	$(COPY) $(BOOTIMAGE_NAME) $(BOOTIMAGE_PATH)/tiboot3.bin
+ifeq ($(DEVICE_TYPE),GP)
+	@echo  Boot image: am64x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+endif
+	@echo  Boot image: am64x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+	@echo  .
+endif
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/syscfg_c.rov.xs
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/syscfg_c.rov.xs
@ -0,0 +1,8 @@
+/*
+ *  ======== syscfg_c.rov.xs ========
+ *  This file contains the information needed by the Runtime Object
+ *  View (ROV) tool.
+ */
+var crovFiles = [
+    "kernel/freertos/rov/FreeRTOS.rov.js",
+];
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/targetConfigs/AM62.ccxml
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/targetConfigs/AM62.ccxml
@ -0,0 +1,140 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configurations XML_version="1.2" id="configurations_0">
+                        
+    
+    
+    
+    
+    <configuration XML_version="1.2" id="configuration_0">
+                                                
+        
+        
+        
+        
+        <instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
+                                                
+        
+        
+        
+        
+        <connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
+                                                                        
+            
+            
+            
+            
+            <instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
+                                                                        
+            
+            
+            
+            
+            <instance XML_version="1.2" href="drivers/tixds510cortexA53.xml" id="drivers" xml="tixds510cortexA53.xml" xmlpath="drivers"/>
+                                                                        
+            
+            
+            
+            
+            <instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
+                                                                        
+            
+            
+            
+            
+            <instance XML_version="1.2" href="drivers/tixds510cortexR.xml" id="drivers" xml="tixds510cortexR.xml" xmlpath="drivers"/>
+                                                                        
+            
+            
+            
+            
+            <platform XML_version="1.2" id="platform_0">
+                                                                                                
+                
+                
+                
+                
+                <instance XML_version="1.2" desc="AM62" href="devices/AM62x.xml" id="AM62" xml="AM62x.xml" xmlpath="devices"/>
+                                                                                                
+                
+                
+                
+                
+                <device HW_revision="1" XML_version="1.2" description="AM62" id="AM62" partnum="AM64x" simulation="no">
+                                                                                                                        
+                    
+                    
+                    
+                    
+                    <router HW_revision="1.0" XML_version="1.2" description="CS_DAP Router" id="CS_DAP_0" isa="CS_DAP">
+                                                                                                                                                
+                        
+                        
+                        
+                        
+                        <subpath id="SMS_CM4_0_TIFS">
+                                                                                                                                                                        
+                            
+                            
+                            
+                            
+                            <cpu HW_revision="1.0" XML_version="1.2" desc="SMS_CM4_0_TIFS_0" description="Cortex_M4F CPU" deviceSim="false" id="SMS_CM4_0_TIFS" isa="Cortex_M4F"/>
+                                                                                                                                                                    
+                        
+                        
+                        
+                        
+                        </subpath>
+                                                                                                                                                
+                        
+                        
+                        
+                        
+                        <subpath id="BLAZER_CM4">
+                                                                                                                                                                        
+                            
+                            
+                            
+                            
+                            <cpu HW_revision="1.0" XML_version="1.2" desc="BLAZAR_Cortex_M4F_1" description="Cortex_M4F CPU" deviceSim="false" id="BLAZER_CM4" isa="Cortex_M4F"/>
+                                                                                                                                                                    
+                        
+                        
+                        
+                        
+                        </subpath>
+                                                                                                                                            
+                    
+                    
+                    
+                    
+                    </router>
+                                                                                                                    
+                
+                
+                
+                
+                </device>
+                                                                                            
+            
+            
+            
+            
+            </platform>
+                                                                    
+        
+        
+        
+        
+        </connection>
+                                            
+    
+    
+    
+    
+    </configuration>
+                    
+
+
+
+
+</configurations>
--- a/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/targetConfigs/readme.txt
+++ b/utils/sbl_sd_ddr_init_am64x-evm_r5fss0-0_nortos_ti-arm-clang/targetConfigs/readme.txt
@ -0,0 +1,9 @@
+The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based
+on the device and connection settings specified in your project on the Properties > General page.
+
+Please note that in automatic target-configuration management, changes to the project's device and/or
+connection settings will either modify an existing or generate a new target-configuration file. Thus,
+if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
+you may create your own target-configuration file for this project and manage it manually. You can
+always switch back to automatic target-configuration management by checking the "Manage the project's
+target-configuration automatically" checkbox on the project's Properties > General page.