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Pull request #46: am64x/am243x: hdsl: Bug fixes based on SICK Testing

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Merge in PINDSW/motor_control_sdk from PINDSW-6528_hdsl_bugfixes to next

* commit '9fa938d6aeed61f4cc6b575f675eac36404c3b22':
  am64x/am243x: hdsl: Fix the clearing behavior of ONLINE STATUS 1 SCE bit
  am64x/am243x: hdsl: Fix SSUM bit in EVENT_S register
  am64x/am243x: hdsl: Add APIs for long message read and write
  am64x/am243x: hdsl: Fix compiler warnings
  am64x/am243x: hdsl: Add support for PIPE_D register
  am64x/am243x: hdsl: Fix the QM update for safe channel 2
  am64x/am243x: hdsl: Fix the reset value of PRST bit in status/event
This commit is contained in:
Dhaval Khandla 2023-11-22 04:51:50 -06:00 committed by Pratheesh Gangadhar TK
commit e9cc53f0ee
14 changed files with 1028 additions and 753 deletions
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2
docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md
View File

@ -159,4 +159,6 @@ Notable exceptions in TI HDSL Solution when compared with SICK HDSL MASTER IP Co
6. Reset values of registers are not same as SICK HDSL MASTER IP Core.
7. As registers are implemented using Data Memory of Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS), the application has a read-write access for all registers.
8. When safe position is invalid (VPOS bit is set in EVENT_S), 0xFDFDFDFDFD value is not set in fast and safe position registers.
9. For long message offset, only 15-bit wide offset is supported. If offset is enabled, then master will always send 2 bytes of offset.

2
docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md
View File

@ -984,7 +984,7 @@ TI HDSL Solution's register map is compatible with SICK HDSL MASTER IP Core rele
<td> Bits 9:8 of 10 bit address for a "long message" operation
</tr>
<tr>
<td> PC_ADD_H
<td> PC_ADD_L
<td> 0x29
<td>
<td> Long message address (Low Byte)

382
examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c
View File

@ -30,6 +30,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
#include <drivers/hw_include/hw_types.h>
#include <stdio.h>
@ -71,6 +75,10 @@
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h>
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
#if (CONFIG_HDSL0_CHANNEL0 + CONFIG_HDSL0_CHANNEL1 > 1)
#define HDSL_MULTI_CHANNEL
#endif
@ -97,9 +105,12 @@
#define CTR_EN (1 << 3)
#define MAX_WAIT 20000
/*Timeout in micorseconds for short message read/write*/
/*Timeout in micro-seconds for short message read/write*/
#define SHORT_MSG_TIMEOUT (1000)
/*Timeout in micro-seconds for long message read/write*/
#define LONG_MSG_TIMEOUT (200000)
/*Register Addresses for Short Messages (Parameter Channel)*/
#define ENCODER_STATUS0_REG_ADDRESS (0x40)
@ -119,6 +130,70 @@
#define HDSL_MEMORY_TRACE_R5F_IRQ_NUM (CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_3)
#endif
/* ========================================================================== */
/* Function Declarations */
/* ========================================================================== */
#if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_)
void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData);
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
const void *destBuf,
const void *srcBuf,
uint32_t length);
void udma_copy(uint8_t *srcBuf, uint8_t *destBuf, uint32_t length);
static void HDSL_IsrFxn();
#ifndef HDSL_MULTI_CHANNEL
void traces_into_memory(HDSL_Handle hdslHandle);
#endif
void sync_calculation(HDSL_Handle hdslHandle);
void process_request(HDSL_Handle hdslHandle,int32_t menu);
void hdsl_pruss_init(void);
void hdsl_pruss_init_300m(void);
void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle);
void hdsl_init(void);
void hdsl_init_300m(void);
void TC_read_pc_short_msg(HDSL_Handle hdslHandle);
void TC_write_pc_short_msg(HDSL_Handle hdslHandle);
static void display_menu(void);
void direct_read_rid0_length4(HDSL_Handle hdslHandle);
void direct_read_rid81_length8(HDSL_Handle hdslHandle);
void direct_read_rid81_length2(HDSL_Handle hdslHandle);
void indirect_write_rid0_length8_offset0(HDSL_Handle hdslHandle);
void indirect_write_rid0_length8(HDSL_Handle hdslHandle);
static int get_menu(void);
#ifdef HDSL_AM64xE1_TRANSCEIVER
static void hdsl_i2c_io_expander(void *args);
#endif
uint32_t read_encoder_resolution(HDSL_Handle hdslHandle);
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
HDSL_Handle gHdslHandleCh0;
HDSL_Handle gHdslHandleCh1;
@ -165,15 +240,10 @@ HwiP_Object gPRUHwiObject;
uint8_t gUdmaTestTrpdMem[UDMA_TEST_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
#endif
#if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_)
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData);
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
const void *destBuf,
const void *srcBuf,
uint32_t length);
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
@ -567,8 +637,8 @@ void process_request(HDSL_Handle hdslHandle,int32_t menu)
case MENU_PC_SHORT_MSG_READ:
TC_read_pc_short_msg(hdslHandle);
break;
case MENU_DIRECT_READ_RID0_LENGTH8:
direct_read_rid0_length8(hdslHandle);
case MENU_DIRECT_READ_RID0_LENGTH4:
direct_read_rid0_length4(hdslHandle);
break;
case MENU_DIRECT_READ_RID81_LENGTH8:
direct_read_rid81_length8(hdslHandle);
@ -765,6 +835,7 @@ void hdsl_init(void)
HDSL_generate_memory_image(gHdslHandleCh0);
}
}
void hdsl_init_300m(void)
{
uint8_t ES;
@ -910,16 +981,16 @@ static void display_menu(void)
DebugP_log("\r\n | %2d : RSSI |", MENU_RSSI);
DebugP_log("\r\n | %2d : Parameter Channel Short Message Write |", MENU_PC_SHORT_MSG_WRITE);
DebugP_log("\r\n | %2d : Parameter Channel Short Message Read |", MENU_PC_SHORT_MSG_READ);
DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID0_LENGTH8);
DebugP_log("\r\n | Access on RID 0h, direct read access with length 8 |");
DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID0_LENGTH4);
DebugP_log("\r\n | Access on RID 0x0, direct read access with length 4 |");
DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID81_LENGTH8);
DebugP_log("\r\n | Access on RID 81h, direct read access with length 8 |");
DebugP_log("\r\n | Access on RID 0x81, direct read access with length 8 |");
DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID81_LENGTH2);
DebugP_log("\r\n | Access on RID 81h, direct read access with length 2 |");
DebugP_log("\r\n | Access on RID 0x81, direct read access with length 2 and offset 3 |");
DebugP_log("\r\n | %2d : Parameter Channel Long Message Write |", MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0);
DebugP_log("\r\n | Access on RID 0h, indirect write, length 8, with offset 0 |");
DebugP_log("\r\n | Access on RID 0x0, indirect write, length 8, with offset 0 |");
DebugP_log("\r\n | %2d : Parameter Channel Long Message Write |", MENU_INDIRECT_WRITE_RID0_LENGTH8);
DebugP_log("\r\n | Access on RID 0h; indirect write, length 8, without offset value |");
DebugP_log("\r\n | Access on RID 0x0; indirect write, length 8, without offset value |");
#if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_)
DebugP_log("\r\n | %2d : HDSL registers into Memory |", MENU_HDSL_REG_INTO_MEMORY);
#endif
@ -927,242 +998,246 @@ static void display_menu(void)
DebugP_log("\r\n Enter value: ");
}
void direct_read_rid0_length8(HDSL_Handle hdslHandle)
void direct_read_rid0_length4(HDSL_Handle hdslHandle)
{
uint8_t dir = 0x01;
int32_t status = SystemP_FAILURE;
gPc_addrh = 0xec;
gPc_addrl = 0x00;
gPc_offh = 0x80;
gPc_offl = 0x00;
DebugP_log("\r\n Parameter channel long message read : RID 0, Length 4");
HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl);
/* Set the parameter channel buffers to 0xff */
HDSL_write_pc_buffer(hdslHandle, 0, 0xff);
HDSL_write_pc_buffer(hdslHandle, 1, 0xff);
HDSL_write_pc_buffer(hdslHandle, 2, 0xff);
HDSL_write_pc_buffer(hdslHandle, 3, 0xff);
HDSL_set_pc_ctrl(hdslHandle,dir);
status = HDSL_read_pc_long_msg(hdslHandle, 0, HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET, HDSL_LONG_MSG_ADDR_DIRECT, HDSL_LONG_MSG_LENGTH_4, 0, LONG_MSG_TIMEOUT);
ClockP_sleep(1);
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0);
if(gPc_buf0 == 82)
if(SystemP_SUCCESS != status)
{
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1);
if(gPc_buf1 == 79)
DebugP_log("\r\n FAIL: HDSL_read_pc_long_msg() did not return success");
return;
}
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0);
if(gPc_buf0 == 'R')
{
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1);
if(gPc_buf1 == 'O')
{
gPc_buf2 = HDSL_read_pc_buffer(hdslHandle,2);
if(gPc_buf2 == 79)
gPc_buf2 = HDSL_read_pc_buffer(hdslHandle, 2);
if(gPc_buf2 == 'O')
{
gPc_buf3 = HDSL_read_pc_buffer(hdslHandle,3);
if(gPc_buf3 == 84)
gPc_buf3 = HDSL_read_pc_buffer(hdslHandle, 3);
if(gPc_buf3 == 'T')
{
DebugP_log("\r\n PASS");
DebugP_log("\r\n PASS : Read \"ROOT\"");
}
else
{
DebugP_log("\r\n FAIL: gPc_buf3 != T = %u", gPc_buf3);
DebugP_log("\r\n FAIL: PC_BUFFER3 != T (It is %u)", gPc_buf3);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf2 != O = %u", gPc_buf2);
DebugP_log("\r\n FAIL: PC_BUFFER2 != O (It is %u)", gPc_buf2);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf1 != O = %u", gPc_buf1);
DebugP_log("\r\n FAIL: PC_BUFFER1 != O (It is %u)", gPc_buf1);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf0 != R = %u", gPc_buf0);
DebugP_log("\r\n FAIL: PC_BUFFER0 != R (It is %u)", gPc_buf0);
}
}
void direct_read_rid81_length8(HDSL_Handle hdslHandle)
void direct_read_rid81_length8(HDSL_Handle hdslHandle)
{
uint8_t dir = 0x01;
gPc_addrh = 0xec;
gPc_addrl = 0x81;
gPc_offh = 0x80;
gPc_offl = 0x00;
int32_t status = SystemP_FAILURE;
HDSL_set_pc_addr( hdslHandle,gPc_addrh, gPc_addrl, gPc_offh, gPc_offl);
DebugP_log("\r\n Parameter channel long message read : RID 0x81, Length 8");
HDSL_set_pc_ctrl(hdslHandle,dir);
/* Set the parameter channel buffers to 0xff */
HDSL_write_pc_buffer(hdslHandle, 0, 0xff);
HDSL_write_pc_buffer(hdslHandle, 1, 0xff);
HDSL_write_pc_buffer(hdslHandle, 2, 0xff);
HDSL_write_pc_buffer(hdslHandle, 3, 0xff);
HDSL_write_pc_buffer(hdslHandle, 4, 0xff);
HDSL_write_pc_buffer(hdslHandle, 5, 0xff);
HDSL_write_pc_buffer(hdslHandle, 6, 0xff);
HDSL_write_pc_buffer(hdslHandle, 7, 0xff);
ClockP_sleep(1);
status = HDSL_read_pc_long_msg(hdslHandle, 0x81, HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET, HDSL_LONG_MSG_ADDR_DIRECT, HDSL_LONG_MSG_LENGTH_8, 0, LONG_MSG_TIMEOUT);
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0);
if(gPc_buf0 == 82)
if(SystemP_SUCCESS != status)
{
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1);
if(gPc_buf1 == 69)
DebugP_log("\r\n FAIL: HDSL_read_pc_long_msg() did not return success");
return;
}
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0);
if(gPc_buf0 == 'R')
{
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1);
if(gPc_buf1 == 'E')
{
gPc_buf2 = HDSL_read_pc_buffer(hdslHandle,2);
if(gPc_buf2 == 83)
gPc_buf2 = HDSL_read_pc_buffer(hdslHandle, 2);
if(gPc_buf2 == 'S')
{
gPc_buf3 = HDSL_read_pc_buffer(hdslHandle,3);
if(gPc_buf3 == 79)
gPc_buf3 = HDSL_read_pc_buffer(hdslHandle, 3);
if(gPc_buf3 == 'O')
{
gPc_buf4 = HDSL_read_pc_buffer(hdslHandle,4);
if(gPc_buf4 == 76)
gPc_buf4 = HDSL_read_pc_buffer(hdslHandle, 4);
if(gPc_buf4 == 'L')
{
gPc_buf5 = HDSL_read_pc_buffer(hdslHandle,5);
if(gPc_buf5 == 85)
gPc_buf5 = HDSL_read_pc_buffer(hdslHandle, 5);
if(gPc_buf5 == 'U')
{
gPc_buf6 = HDSL_read_pc_buffer(hdslHandle,6);
if(gPc_buf6 == 84)
gPc_buf6 = HDSL_read_pc_buffer(hdslHandle, 6);
if(gPc_buf6 == 'T')
{
gPc_buf7 = HDSL_read_pc_buffer(hdslHandle,7);
if(gPc_buf7 == 78)
gPc_buf7 = HDSL_read_pc_buffer(hdslHandle, 7);
if(gPc_buf7 == 'N')
{
DebugP_log("\r\n PASS ");
DebugP_log("\r\n PASS : Read \"RESOLUTN\"");
}
else
{
DebugP_log("\r\n FAIL: gPc_buf7 != N ", gPc_buf7);
DebugP_log("\r\n FAIL: PC_BUFFER7 != N (It is %u)", gPc_buf7);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf6 != T ", gPc_buf6);
DebugP_log("\r\n FAIL: PC_BUFFER6 != T (It is %u)", gPc_buf6);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf5 != U ", gPc_buf5);
DebugP_log("\r\n FAIL: PC_BUFFER5 != U (It is %u)", gPc_buf5);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf4 != L ", gPc_buf4);
DebugP_log("\r\n FAIL: PC_BUFFER4 != L (It is %u)", gPc_buf4);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf3 != O ", gPc_buf3);
DebugP_log("\r\n FAIL: PC_BUFFER3 != O (It is %u)", gPc_buf3);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf2 != S = %u", gPc_buf2);
DebugP_log("\r\n FAIL: PC_BUFFER2 != S (It is %u)", gPc_buf2);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf1 != E = %u", gPc_buf1);
DebugP_log("\r\n FAIL: PC_BUFFER1 != E (It is %u)", gPc_buf1);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf0 != R = %u", gPc_buf0);
DebugP_log("\r\n FAIL: PC_BUFFER0 != R (It is %u)", gPc_buf0);
}
}
void direct_read_rid81_length2(HDSL_Handle hdslHandle)
void direct_read_rid81_length2(HDSL_Handle hdslHandle)
{
uint8_t dir = 0x01;
int32_t status = SystemP_FAILURE;
gPc_addrh = 0xe4;
gPc_addrl = 0x81;
gPc_offh = 0x80;
gPc_offl = 0x03;
DebugP_log("\r\n Parameter channel long message read : RID 0x81, Offset 3, Length 2");
HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl);
/* Set the parameter channel buffers to 0xaa */
HDSL_write_pc_buffer(hdslHandle, 0, 0xaa);
HDSL_write_pc_buffer(hdslHandle, 1, 0xaa);
HDSL_set_pc_ctrl(hdslHandle,dir);
status = HDSL_read_pc_long_msg(hdslHandle, 0x81, HDSL_LONG_MSG_ADDR_WITH_OFFSET, HDSL_LONG_MSG_ADDR_DIRECT, HDSL_LONG_MSG_LENGTH_2, 3, LONG_MSG_TIMEOUT);
ClockP_sleep(1);
if(SystemP_SUCCESS != status)
{
DebugP_log("\r\n FAIL: HDSL_read_pc_long_msg() did not return success");
return;
}
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0);
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0);
if(gPc_buf0 == 0x00)
{
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1);
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1);
if(gPc_buf1 == 0x0f)
{
DebugP_log("\r\n PASS ");
DebugP_log("\r\n PASS : Read 15");
}
else
{
DebugP_log("\r\n FAIL: gPc_buf1 != 0x0f = %u", gPc_buf1);
DebugP_log("\r\n FAIL: PC_BUFFER1 != 0x0f (It is %u)", gPc_buf1);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf0 != 0x00 = %u", gPc_buf0);
DebugP_log("\r\n FAIL: PC_BUFFER0 != 0x00 (It is %u)", gPc_buf0);
}
}
void indirect_write_rid0_length8_offset0(HDSL_Handle hdslHandle)
void indirect_write_rid0_length8_offset0(HDSL_Handle hdslHandle)
{
uint8_t dir = 0x01;
DebugP_log("\r\n Parameter channel long message write : RID 0x0, Offset 0, Length 8");
gPc_addrh = 0xbc;
gPc_addrl = 0x00;
gPc_offh = 0x80;
gPc_offl = 0x00;
HDSL_write_pc_long_msg(hdslHandle, 0x0, HDSL_LONG_MSG_ADDR_WITH_OFFSET, HDSL_LONG_MSG_ADDR_INDIRECT, HDSL_LONG_MSG_LENGTH_8, 0, LONG_MSG_TIMEOUT);
HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl);
/*FIXME: Add error check*/
HDSL_set_pc_ctrl(hdslHandle,dir);
ClockP_sleep(1);
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0);
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0);
if(gPc_buf0 == 0x41)
{
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1);
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1);
if(gPc_buf1 == 0x10)
{
DebugP_log("\r\n PASS ");
}
else
{
DebugP_log("\r\n FAIL: gPc_buf1 != 0x10 = %u", gPc_buf1);
DebugP_log("\r\n FAIL: PC_BUFFER1 != 0x10 (It is %u)", gPc_buf1);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf0 != 0x41 = %u", gPc_buf0);
DebugP_log("\r\n FAIL: PC_BUFFER0 != 0x41 (It is %u)", gPc_buf0);
}
}
void indirect_write_rid0_length8(HDSL_Handle hdslHandle)
void indirect_write_rid0_length8(HDSL_Handle hdslHandle)
{
uint8_t dir = 0x01;
gPc_addrh = 0x9c;
gPc_addrl = 0x00;
gPc_offh = 0x80;
gPc_offl = 0x00;
DebugP_log("\r\n Parameter channel long message write : RID 0x0, Length 8");
HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl);
HDSL_write_pc_long_msg(hdslHandle, 0x0, HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET, HDSL_LONG_MSG_ADDR_INDIRECT, HDSL_LONG_MSG_LENGTH_8, 0, LONG_MSG_TIMEOUT);
HDSL_set_pc_ctrl(hdslHandle,dir);
/*FIXME: Add error check*/
ClockP_sleep(1);
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0);
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0);
if(gPc_buf0 == 0x41)
{
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1);
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1);
if(gPc_buf1 == 0x10)
{
DebugP_log("\r\n PASS ");
}
else
{
DebugP_log("\r\n FAIL: gPc_buf1 != 0x10 = %u", gPc_buf1);
DebugP_log("\r\n FAIL: PC_BUFFER1 != 0x10 (It is %u)", gPc_buf1);
}
}
else
{
DebugP_log("\r\n FAIL: gPc_buf0 != 0x41 = %u", gPc_buf0);
DebugP_log("\r\n FAIL: PC_BUFFER0 != 0x41 (It is %u)", gPc_buf0);
}
}
@ -1240,6 +1315,34 @@ static void hdsl_i2c_io_expander(void *args)
}
#endif
uint32_t read_encoder_resolution(HDSL_Handle hdslHandle)
{
int32_t status = SystemP_FAILURE;
uint32_t resolution = 0;
/* Set the parameter channel buffers to 0xff */
HDSL_write_pc_buffer(hdslHandle, 0, 0xff);
HDSL_write_pc_buffer(hdslHandle, 1, 0xff);
HDSL_write_pc_buffer(hdslHandle, 2, 0xff);
HDSL_write_pc_buffer(hdslHandle, 3, 0xff);
/* Parameter channel long message read with RID 0x81, Offset 5, Length 4
* for reading resolution */
status = HDSL_read_pc_long_msg(hdslHandle, 0x81, HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET, HDSL_LONG_MSG_ADDR_INDIRECT, HDSL_LONG_MSG_LENGTH_4, 0, LONG_MSG_TIMEOUT);
DebugP_assert(SystemP_SUCCESS == status);
gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0);
gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1);
gPc_buf2 = HDSL_read_pc_buffer(hdslHandle, 2);
gPc_buf3 = HDSL_read_pc_buffer(hdslHandle, 3);
resolution = log2((gPc_buf0 << 24) | (gPc_buf1 << 16) | (gPc_buf2 << 8) | (gPc_buf3));
return resolution;
}
void hdsl_diagnostic_main(void *arg)
{
uint32_t val, acc_bits, pos_bits;
@ -1328,23 +1431,24 @@ void hdsl_diagnostic_main(void *arg)
pos_bits += acc_bits;
DebugP_log("\r\n | Encoder ID: 0x%x", val);
DebugP_log( "(");
DebugP_log( "Acceleration bits: %u ,", acc_bits);
DebugP_log( "Acceleration bits: %u, ", acc_bits);
DebugP_log( "Position bits: %u,", pos_bits);
DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
DebugP_log(")|");
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
DebugP_log("\r\n Enter single turn bits: ");
if((DebugP_scanf("%d\n", &gHdslHandleCh0->res) < 0) || gHdslHandleCh0->res > pos_bits)
{
DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n");
gHdslHandleCh0->res = pos_bits;
}
gHdslHandleCh0->res = read_encoder_resolution(gHdslHandleCh0);
gHdslHandleCh0->multi_turn = pos_bits - gHdslHandleCh0->res;
gHdslHandleCh0->mask = pow(2, gHdslHandleCh0->res) - 1;
if (gHdslHandleCh0->multi_turn)
if(gHdslHandleCh0->multi_turn)
{
DebugP_log( "\r\n Multi turn bits: %u\n", gHdslHandleCh0->multi_turn);
DebugP_log( "\r\n | Single-turn bits: %u, Multi-turn bits: %u |", pos_bits - gHdslHandleCh0->multi_turn, gHdslHandleCh0->multi_turn);
}
else
{
DebugP_log( "\r\n | Single-turn bits: %u |", pos_bits);
}
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
#endif
#if (CONFIG_HDSL0_CHANNEL1==1)
@ -1379,24 +1483,22 @@ void hdsl_diagnostic_main(void *arg)
pos_bits += acc_bits;
DebugP_log("\r\n | Encoder ID: 0x%x", val);
DebugP_log( "(");
DebugP_log( "Acceleration bits: %u ,", acc_bits);
DebugP_log( "Acceleration bits: %u, ", acc_bits);
DebugP_log( "Position bits: %u,", pos_bits);
DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
DebugP_log(")|");
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
DebugP_log("\r\n Enter single turn bits: ");
if((DebugP_scanf("%d\n", &gHdslHandleCh1->res) < 0) || gHdslHandleCh1->res > pos_bits)
{
DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n");
gHdslHandleCh1->res = pos_bits;
}
gHdslHandleCh1->res = read_encoder_resolution(gHdslHandleCh1);
gHdslHandleCh1->multi_turn = pos_bits - gHdslHandleCh1->res;
gHdslHandleCh1->mask = pow(2, gHdslHandleCh1->res) - 1;
if (gHdslHandleCh1->multi_turn)
if(gHdslHandleCh0->multi_turn)
{
DebugP_log( "\r\n Multi turn bits: %u\n", gHdslHandleCh1->multi_turn);
DebugP_log( "\r\n | Single-turn bits: %u, Multi-turn bits: %u |", pos_bits - gHdslHandleCh1->multi_turn, gHdslHandleCh1->multi_turn);
}
else
{
DebugP_log( "\r\n | Single-turn bits: %u |", pos_bits);
}
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
#endif
while(1)

20
examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.h
View File

@ -56,26 +56,6 @@ extern "C" {
/* UDMA TR packet descriptor memory size - with one TR */
#define UDMA_TEST_TRPD_SIZE (UDMA_GET_TRPD_TR15_SIZE(1U))
/* ISR for v-frame-reception */
static void HDSL_IsrFxn(void);
void TC_read_pc_short_msg();
void TC_write_pc_short_msg();
#ifndef HDSL_MULTI_CHANNEL
/*
* @brief It will test copy of traces into memory
* \n Here user will decide how many copies of HDSL_Interface_Register
* \n will be copied into memory
*/
void traces_into_memory();
#endif
void direct_read_rid0_length8();
void direct_read_rid81_length8();
void direct_read_rid81_length2();
void indirect_write_rid0_length8();
void indirect_write_rid0_length8_offset0();
#ifdef __cplusplus
}
#endif

275
source/position_sense/hdsl/driver/hdsl_drv.c
View File

@ -34,6 +34,27 @@
#include <kernel/dpl/ClockP.h>
#include <drivers/hw_include/tistdtypes.h>
#define ONLINE_STATUS_1_L_FRES (1<<0)
#define ONLINE_STATUS_D_L_FREL (1)
#define PC_ADD_H_LONG_MSG_ENABLE (1<<7)
#define PC_ADD_H_LONG_MSG_WRITE (0<<6)
#define PC_ADD_H_LONG_MSG_READ (1<<6)
#define PC_ADD_H_LONG_MSG_ERROR (1<<5)
#define PC_ADD_H_OFFSET_EN_SHIFT (5)
#define PC_ADD_H_ADDR_TYPE_SHIFT (4)
#define PC_ADD_H_LENGTH_SHIFT (2)
#define PC_ADD_H_ADDR_HIGH_MASK (0x0300)
#define PC_ADD_L_ADDR_LOW_MASK (0x00FF)
#define PC_OFF_H_LONG_MSG_ENABLE (1<<7)
#define PC_OFF_H_OFFSET_HIGH_MASK (0x7F00)
#define PC_OFF_L_OFFSET_LOW_MASK (0x00FF)
#define PC_CTRL_ENABLE (0x01)
/* Should move the below to sysconfig generated code */
HDSL_Config hdslConfig0;
HDSL_Config hdslConfig1;
@ -309,52 +330,228 @@ int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *dat
return SystemP_SUCCESS;
}
int32_t HDSL_write_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout)
{
uint64_t end;
end = ClockP_getTimeUsec() + timeout;
while(!(hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1<<ONLINE_STATUS_D_L_FREL)))
{
if(ClockP_getTimeUsec() > end)
{
return SystemP_TIMEOUT;
}
}
/*
Setting PC_ADD_L
Bits 7:0 contain bits 7:0 of 10 bit address for long message
*/
hdslHandle->hdslInterface->PC_ADD_L = (addr & PC_ADD_L_ADDR_LOW_MASK);
/*
Setting PC_ADD_H
Bit 7 should always be set for long message
Bit 6 is unset for write operation
Bit 5 is to enable/disable offset
Bit 4 is to select direct/indirect addressing
Bits 3:2 define the length of the message
Bits 1:0 contain bits 9:8 of 10 bit address for long message
*/
hdslHandle->hdslInterface->PC_ADD_H = (PC_ADD_H_LONG_MSG_ENABLE) |
(PC_ADD_H_LONG_MSG_WRITE) |
(offsetEnable << PC_ADD_H_OFFSET_EN_SHIFT) |
(addrType << PC_ADD_H_ADDR_TYPE_SHIFT) |
(length << PC_ADD_H_LENGTH_SHIFT) |
((addr & PC_ADD_H_ADDR_HIGH_MASK) >> 8);
/*
Setting PC_OFF_L
Bits 7:0 contain bits 7:0 of 15 bit offset value
*/
hdslHandle->hdslInterface->PC_OFF_L = (offset & PC_OFF_L_OFFSET_LOW_MASK);
/*
Setting PC_OFF_H
Bit 7 should always be set for long message
Bits 6:0 contain bits 14:8 of 15 bit offset value
*/
hdslHandle->hdslInterface->PC_OFF_H = (PC_OFF_H_LONG_MSG_ENABLE) |
((offset & PC_OFF_H_OFFSET_HIGH_MASK) >> 8);
/* Setting PC_CTRL */
hdslHandle->hdslInterface->PC_CTRL = PC_CTRL_ENABLE;
while((hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1<<ONLINE_STATUS_D_L_FREL)))
{
if(ClockP_getTimeUsec() > end)
{
return SystemP_TIMEOUT;
}
}
while(!(hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1<<ONLINE_STATUS_D_L_FREL)))
{
if(ClockP_getTimeUsec() > end)
{
return SystemP_TIMEOUT;
}
}
/* Checking for error */
if(hdslHandle->hdslInterface->PC_ADD_H & PC_ADD_H_LONG_MSG_ERROR)
{
return SystemP_FAILURE;
}
return SystemP_SUCCESS;
}
int32_t HDSL_read_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout)
{
uint64_t end;
end = ClockP_getTimeUsec() + timeout;
while(!(hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1<<ONLINE_STATUS_D_L_FREL)))
{
if(ClockP_getTimeUsec() > end)
{
return SystemP_TIMEOUT;
}
}
/*
Setting PC_ADD_L
Bits 7:0 contain bits 7:0 of 10 bit address for long message
*/
hdslHandle->hdslInterface->PC_ADD_L = (addr & PC_ADD_L_ADDR_LOW_MASK);
/*
Setting PC_ADD_H
Bit 7 should always be set for long message
Bit 6 is set for read operation
Bit 5 is to enable/disable offset
Bit 4 is to select direct/indirect addressing
Bits 3:2 define the length of the message
Bits 1:0 contain bits 9:8 of 10 bit address for long message
*/
hdslHandle->hdslInterface->PC_ADD_H = (PC_ADD_H_LONG_MSG_ENABLE) |
(PC_ADD_H_LONG_MSG_READ) |
(offsetEnable << PC_ADD_H_OFFSET_EN_SHIFT) |
(addrType << PC_ADD_H_ADDR_TYPE_SHIFT) |
(length << PC_ADD_H_LENGTH_SHIFT) |
((addr & PC_ADD_H_ADDR_HIGH_MASK) >> 8);
/*
Setting PC_OFF_L
Bits 7:0 contain bits 7:0 of 15 bit offset value
*/
hdslHandle->hdslInterface->PC_OFF_L = (offset & PC_OFF_L_OFFSET_LOW_MASK);
/*
Setting PC_OFF_H
Bit 7 should always be set for long message
Bits 6:0 contain bits 14:8 of 15 bit offset value
*/
hdslHandle->hdslInterface->PC_OFF_H = (PC_OFF_H_LONG_MSG_ENABLE) |
((offset & PC_OFF_H_OFFSET_HIGH_MASK) >> 8);
/* Setting PC_CTRL */
hdslHandle->hdslInterface->PC_CTRL = PC_CTRL_ENABLE;
while((hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1<<ONLINE_STATUS_D_L_FREL)))
{
if(ClockP_getTimeUsec() > end)
{
return SystemP_TIMEOUT;
}
}
while(!(hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1<<ONLINE_STATUS_D_L_FREL)))
{
if(ClockP_getTimeUsec() > end)
{
return SystemP_TIMEOUT;
}
}
/* Checking for error */
if(hdslHandle->hdslInterface->PC_ADD_H & PC_ADD_H_LONG_MSG_ERROR)
{
return SystemP_FAILURE;
}
return SystemP_SUCCESS;
}
void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off, uint8_t data)
{
switch(buff_off)
{
case 0:
hdslHandle->hdslInterface->PC_BUFFER0 = data;
break;
case 1:
hdslHandle->hdslInterface->PC_BUFFER1 = data;
break;
case 2:
hdslHandle->hdslInterface->PC_BUFFER2 = data;
break;
case 3:
hdslHandle->hdslInterface->PC_BUFFER3 = data;
break;
case 4:
hdslHandle->hdslInterface->PC_BUFFER4 = data;
break;
case 5:
hdslHandle->hdslInterface->PC_BUFFER5 = data;
break;
case 6:
hdslHandle->hdslInterface->PC_BUFFER6 = data;
break;
case 7:
hdslHandle->hdslInterface->PC_BUFFER7 = data;
break;
default:
break;
}
}
uint8_t HDSL_read_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off)
{
switch(buff_off)
{
case 0:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER0);
break;
case 1:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER1);
break;
case 2:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER2);
break;
case 3:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER3);
break;
case 4:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER4);
break;
case 5:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER5);
break;
case 6:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER6);
break;
case 7:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER7);
break;
default:
return 0;
break;
case 0:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER0);
break;
case 1:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER1);
break;
case 2:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER2);
break;
case 3:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER3);
break;
case 4:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER4);
break;
case 5:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER5);
break;
case 6:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER6);
break;
case 7:
return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER7);
break;
default:
return 0;
break;
}
}
void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t pc_buf0, uint8_t pc_buf1, uint8_t pc_buf2, uint8_t pc_buf3, uint8_t pc_buf4, uint8_t pc_buf5, uint8_t pc_buf6, uint8_t pc_buf7)
{
hdslHandle->hdslInterface->PC_BUFFER0 = pc_buf0;
hdslHandle->hdslInterface->PC_BUFFER1 = pc_buf1;
hdslHandle->hdslInterface->PC_BUFFER2 = pc_buf2;
hdslHandle->hdslInterface->PC_BUFFER3 = pc_buf3;
hdslHandle->hdslInterface->PC_BUFFER4 = pc_buf4;
hdslHandle->hdslInterface->PC_BUFFER5 = pc_buf5;
hdslHandle->hdslInterface->PC_BUFFER6 = pc_buf6;
hdslHandle->hdslInterface->PC_BUFFER7 = pc_buf7;
}
uint8_t HDSL_get_sync_ctrl(HDSL_Handle hdslHandle)
{
return (uint8_t) (hdslHandle->hdslInterface->SYNC_CTRL);

38
source/position_sense/hdsl/firmware/datalink.asm
View File

@ -116,7 +116,7 @@ datalink_wait_vsynch:
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_FRES
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int0, REG_TMP0.b1, EVENT_S_FRES
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ4
@ -1470,23 +1470,23 @@ is_val_FC:
qba adjustment_done
is_val_F8:
qbne is_val_F0, EXTRA_EDGE_SELF, 0xF8
sub REG_TMP0, REG_TMP0, 12
sub REG_TMP0, REG_TMP0, 12
qba adjustment_done
is_val_F0:
qbne is_val_E0, EXTRA_EDGE_SELF, 0xF0
sub REG_TMP0, REG_TMP0, 16
sub REG_TMP0, REG_TMP0, 16
qba adjustment_done
is_val_E0:
qbne is_val_C0, EXTRA_EDGE_SELF, 0xE0
sub REG_TMP0, REG_TMP0, 20
sub REG_TMP0, REG_TMP0, 20
qba adjustment_done
is_val_C0:
qbne is_val_80, EXTRA_EDGE_SELF, 0xC0
sub REG_TMP0, REG_TMP0, 24
sub REG_TMP0, REG_TMP0, 24
qba adjustment_done
is_val_80:
qbne adjustment_done,EXTRA_EDGE_SELF, 0x80
sub REG_TMP0, REG_TMP0, 28
sub REG_TMP0, REG_TMP0, 28
qba adjustment_done
adjustment_done:
sbco &REG_TMP0, MASTER_REGS_CONST, EXTRA_EDGE_TIMESTAMP, 4
@ -1570,7 +1570,6 @@ log_done1:
;HINT: we have processing time here (~168 cycles)
;check if we reset protocol
lbco &FIFO_L, MASTER_REGS_CONST, SYS_CTRL, 1
;ERROR: qbbc datalink_abort2 is not working, though no compiler error
qbbc SYS_CTRL_PRST_cleared,FIFO_L, SYS_CTRL_PRST
jmp No_long_short_msg
SYS_CTRL_PRST_cleared:
@ -1879,31 +1878,6 @@ datalink_abort_no_wait:
lbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
add REG_TMP0.b0, REG_TMP0.b0, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
; Set EVENT_PRST in EVENT register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
set REG_TMP0.w0, REG_TMP0.w0, EVENT_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2
qbbc update_events_no_int2, REG_TMP0.w2, EVENT_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int2:
; Set EVENT_S_PRST in EVENT_S register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int18, REG_TMP0.b1, EVENT_S_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int18:
; Set PRST bits in ONLINE_STATUS registers
lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST
set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST
set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
jmp datalink_reset
;--------------------------------------------------------------------------------------------------
;Function: switch_clk (RET_ADDR1)

56
source/position_sense/hdsl/firmware/datalink_init.asm
View File

@ -101,30 +101,48 @@ datalink_reset:
;reset SAFE_CTRL register
zero &REG_TMP0.b0, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, SAFE_CTRL, 1
; Set EVENT_PRST in EVENT_H register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
set REG_TMP0.w0, REG_TMP0.w0, EVENT_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2
qbbc update_events_no_int15, REG_TMP0.w2, EVENT_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int15:
; Set EVENT_S_PRST in EVENT_S register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST
;save events
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int22, REG_TMP0.b1, EVENT_S_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int22:
; Initialize ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2
; In ONLINE_STATUS_D high, bit 2 is FIX0, bit 4 is FIX1 and bit 5 is FIX0
; In ONLINE_STATUS_D low, bit 0 is FIX0 and bit 3 is FIX0
lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 2
; clearing bits
ldi REG_TMP0.w0, 0
; setting bits with fix1
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_D_HIGH_BIT4_FIX1)
; setting bits with fix1 and PRST bit
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_D_HIGH_BIT4_FIX1) | (1<<ONLINE_STATUS_D_PRST)
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 2
; In ONLINE_STATUS_1 high, bit 1 is FIX0, bit 3 is FIX0 and bit 4 is FIX1
; In ONLINE_STATUS_1 low, bit 1 is FIX0, bit 3 is FIX0 and bit 4 is FIX0
lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 2
; clearing bits
ldi REG_TMP0.w0, 0
; setting bits with fix1
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_1_HIGH_BIT4_FIX1)
; setting bits with fix1 and PRST bit
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_1_HIGH_BIT4_FIX1) | (1<<ONLINE_STATUS_1_PRST)
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 2
; In ONLINE_STATUS_2 high, bit 1 is FIX0, bit 3 is FIX0, bit 4 is FIX1 and bit7 is FIX1
; In ONLINE_STATUS_2 low, bits 0, 1, 3, 4, 5 are FIX0
lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 2
; clearing bits
ldi REG_TMP0.w0, 0
; setting bits with fix1
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_2_HIGH_BIT4_FIX1)
; setting bits with fix1 and PRST bit
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_2_HIGH_BIT4_FIX1) | (1<<ONLINE_STATUS_2_PRST)
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 2
;check for SPOL and configure eCAP accordingly
ldi REG_TMP1, (ECAP+ECAP_ECCTL1)
@ -560,24 +578,6 @@ datalink_abort2_no_wait:
lbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
add REG_TMP0.b0, REG_TMP0.b0, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
; Set EVENT_PRST in EVENT_H register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
set REG_TMP0.w0, REG_TMP0.w0, EVENT_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2
qbbc update_events_no_int15, REG_TMP0.w2, EVENT_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int15:
; Set EVENT_S_PRST in EVENT_S register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int22, REG_TMP0.b1, EVENT_S_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int22:
;we need rel. jump here
qba datalink_reset
;--------------------------------------------------------------------------------------------------
@ -627,6 +627,14 @@ datalink_line_check:
qblt datalink_line_check, LOOP_CNT.b1, 0
;qba datalink_line_check
datalink_line_check_end:
; Clear PRST bits in ONLINE_STATUS registers
lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
clr REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST
clr REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST
clr REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
;--------------------------------------------------------------------------------------------------
;State ID REQ
;save delay to master registers after all checks were successful

2
source/position_sense/hdsl/firmware/defines.inc
View File

@ -34,7 +34,7 @@
; bit7..4 major number
FIRMWARE_VERSION_MAJOR .set 0x0
; bit3..0 minor number
FIRMWARE_VERSION_MINOR .set 0x5
FIRMWARE_VERSION_MINOR .set 0x9
ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0))

211
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
View File

@ -1,6 +1,4 @@
/*
* hdsl_master_icssg_multichannel_ch0_bin.h
*
*
* Copyright (c) 2021-2023, Texas Instruments Incorporated
* All rights reserved not granted herein.
@ -54,7 +52,7 @@
*
*/
const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x21078900,
0x21078000,
0x2eff8f8e,
0x24000725,
0x24041e8d,
@ -105,19 +103,19 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x5101450a,
0x2400040d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000009,
0x69014508,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000004,
0x2400010d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x1d03c4c4,
0x2302cbd1,
0x2305ac9d,
0x23059d9d,
0x05014545,
0x51074514,
0x49004502,
@ -146,7 +144,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400001e,
0x7f0000c5,
0x24002005,
0x230349d1,
0x23033ad1,
0x24000080,
0x2405a4eb,
0x2eff8992,
@ -159,7 +157,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f6,
0x24001d05,
0xc918ff00,
@ -171,7 +169,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0105f6,
0xc918ff00,
0x101f1f00,
@ -272,7 +270,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -291,7 +289,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -314,7 +312,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230361d1,
0x230352d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -339,7 +337,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -358,7 +356,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -381,7 +379,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230361d1,
0x230352d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -398,7 +396,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x20d10000,
0x24000605,
0x2eff8283,
0x230349d1,
0x23033ad1,
0x240000c0,
0x2400002d,
0x2300d0d1,
@ -452,32 +450,32 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f04c4c4,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000006,
0xc9005005,
0x51fd0304,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0xc9017005,
0x2400010d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000005,
0xc9015004,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0xc9027004,
0x2400010d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x111870e0,
0x5100e006,
0x1f03c4c4,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000008,
0xc9035002,
0x69fd2403,
@ -485,7 +483,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x51fd0404,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x2400052d,
0x24000605,
0x230113d1,
@ -509,7 +507,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f05c4c4,
0x2400080d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x14637878,
0x69014502,
0x15ff7878,
@ -575,14 +573,14 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400ff1e,
0x2103ac00,
0x21039d00,
0x69074507,
0xc901c405,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x21040000,
0x2103f100,
0x51000c2d,
0x51015b04,
0x100c0c02,
@ -691,7 +689,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21052100,
0x21051000,
0xd1077905,
0xd104ff00,
0xd703ffff,
@ -743,12 +741,12 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd1047905,
0x106d6d79,
0x2400037b,
0x21036600,
0x21035700,
0x2102b600,
0x106d6d79,
0x2400027b,
0x21036600,
0x21044c00,
0x21035700,
0x21043b00,
0xd104ff00,
0xd703ffff,
0xd1074d03,
@ -855,7 +853,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10d1d18b,
0x2400040d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x108b8bd1,
0x810c3c80,
0x20d10000,
@ -864,28 +862,13 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91505880,
0x1f008080,
0x1f00c0c0,
0x1f008181,
0x81505880,
0x21063e00,
0x21063000,
0x20d10000,
0x117f6666,
0xc9066604,
0x24000066,
0x81031866,
0x7f0000e6,
0x7f0000f5,
0x710f6602,
0x24000f66,
0x590e6604,
@ -957,7 +940,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400017b,
0x2102b700,
0x2400017b,
0x21044c00,
0x21043b00,
0xd104ff00,
0xd703ffff,
0xd1077903,
@ -985,7 +968,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400ff1e,
0x09017979,
0x2400017b,
0x21044c00,
0x21043b00,
0x2eff838e,
0x24003f00,
0x81401800,
@ -1013,7 +996,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81521802,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x7900002e,
0xd104ff00,
0xd703ffff,
@ -1021,7 +1004,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400ff1e,
0x2400010d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x69fd7309,
0x913d1880,
0x1f040000,
@ -1047,7 +1030,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x686e5303,
0x24000019,
0x79000002,
0x23061ed1,
0x230610d1,
0x10535300,
0x10333320,
0x10131340,
@ -1059,7 +1042,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x2103f300,
0x2103e400,
0x31010004,
0xd104ff00,
0xd703ffff,
@ -1085,23 +1068,20 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd105c008,
0x915818c0,
0x5100c007,
0x1f058000,
0x1f050000,
0x81541800,
0x2400060d,
0x2400080d,
0x040d6666,
0x23033bd1,
0x79000017,
0x1d058000,
0x23032cd1,
0x79000014,
0x1d050000,
0x81541800,
0x2400010d,
0x000d6666,
0x23033bd1,
0x91541800,
0x69fd6204,
0x1f028000,
0x1f020000,
0x81541800,
0x79000002,
0x1d028000,
0x1d020000,
0x15e06262,
0x2ed00381,
0xd1060204,
@ -1133,24 +1113,25 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81361800,
0x91081821,
0x10210001,
0x5100010b,
0x51000106,
0x91043880,
0x1f068080,
0x81041880,
0xc8c0c002,
0x2400229f,
0x913d1880,
0x1f060000,
0x813d1880,
0xc9062002,
0x2400269f,
0x91361800,
0x91503802,
0x1d060202,
0x1d060242,
0x51000003,
0x51000009,
0x1f060202,
0x1f060242,
0x1f064242,
0x913d1880,
0x1f060000,
0x813d1800,
0xc9062002,
0x2400269f,
0x79000003,
0x1d060202,
0x1d064242,
0x81503802,
0x10abab8d,
0x21021100,
@ -1256,7 +1237,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x24003001,
0xd1066b0e,
0x2400010d,
0x23077bd1,
0x230772d1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
@ -1269,7 +1250,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81531800,
0x7900003b,
0x2400020d,
0x23077bd1,
0x230772d1,
0x688b8d38,
0x8137184b,
0x13803b3b,
@ -1312,7 +1293,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1d09c4c4,
0x2400040d,
0x24003001,
0x23077bd1,
0x230772d1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1367,7 +1348,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xc9027a02,
0x01081b1b,
0x2102b700,
0xc901c460,
0xc901c462,
0x24001031,
0x91001800,
0xc9060007,
@ -1376,7 +1357,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x24001e31,
0x2eff829a,
0x1d09c4c4,
0x79000057,
0x79000059,
0x91351800,
0xc9060007,
0x1d060000,
@ -1384,7 +1365,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x24001e31,
0x2eff829a,
0x1d09c4c4,
0x7900004f,
0x79000051,
0xc909c41c,
0x05041b1b,
0x490c1b06,
@ -1392,7 +1373,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x110f3131,
0x69001b02,
0x1d09c4c4,
0x79000047,
0x79000049,
0xc9077a08,
0x905a1831,
0xc9021b03,
@ -1412,7 +1393,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x14809a9a,
0x69101b02,
0x15ff1a1a,
0x79000033,
0x79000035,
0x91401800,
0x513f0013,
0x91531840,
@ -1432,9 +1413,9 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400201b,
0x2400403b,
0x1f09c4c4,
0x7900001f,
0x79000021,
0x912c1800,
0xc900001d,
0xc900001f,
0x1d000000,
0x812c1800,
0x1f09c4c4,
@ -1442,9 +1423,11 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1d010000,
0x81511800,
0x91283881,
0x1f070101,
0x1001017a,
0x2400101b,
0xc9050102,
0xc9050103,
0x1f074141,
0x01101b1b,
0x0b031b00,
0x8fc4d801,
@ -1553,7 +1536,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x230605d1,
0x2305f7d1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
@ -1577,7 +1560,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x230605d1,
0x2305f7d1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1592,6 +1575,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81107880,
0x24000200,
0x814e1800,
0x812e1843,
0x2400209f,
0x2400259f,
0x209d0000,
@ -1666,11 +1650,11 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81080580,
0x240003c0,
0x810605c0,
0x24000500,
0x24000900,
0x810b1800,
0x81441800,
0x2eff8383,
0x2303a49d,
0x2303959d,
0x24000866,
0x2400000c,
0x2400002c,
@ -1679,17 +1663,27 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81001800,
0x2eff8000,
0x81351800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91501880,
0x24000080,
0x13108080,
0x13118080,
0x81501880,
0x91521880,
0x24000080,
0x13108080,
0x13118080,
0x81521880,
0x91541880,
0x24000080,
0x13108080,
0x13118080,
0x81541880,
0x240128e1,
0x90e13382,
@ -1895,7 +1889,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10656546,
0x05012525,
0x4f002560,
0x79000013,
0x79000009,
0xd118fe04,
0xd105ff00,
0x31080002,
@ -1903,23 +1897,13 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x7d0000fb,
0x24000925,
0x24001b8d,
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010ded,
0x6f010df7,
0x05012525,
0x4f0025fa,
0x24001025,
@ -1927,18 +1911,23 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010de1,
0x6f010deb,
0x05012525,
0x4f0025fa,
0x91505880,
0x1d008080,
0x1d00c0c0,
0x1d008181,
0x81505880,
0x810a1846,
0x24001d8d,
0x2301d19d,
0x2301569d,
0x6e0403da,
0x6e2423d9,
0x6e0403df,
0x6e2423de,
0x110f4300,
0x0b044320,
0x6e2000d6,
0x6e2000db,
0x10848480,
0x10434340,
0x10404001,
@ -1947,7 +1936,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x810d3801,
0x2400000d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x1f08c4c4,
0x110fe05d,
0x01085d5d,
@ -1986,5 +1975,5 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x21063e00};
0x21063000};

211
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h
View File

@ -1,6 +1,4 @@
/*
* hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h
*
*
* Copyright (c) 2021-2023, Texas Instruments Incorporated
* All rights reserved not granted herein.
@ -54,7 +52,7 @@
*
*/
const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2107cd00,
0x2107c400,
0x2eff8f8e,
0x24000725,
0x24041e8d,
@ -105,19 +103,19 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x5101450a,
0x2400040d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000009,
0x69014508,
0x2400060d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000004,
0x2400010d,
0x000d6666,
0x23035ad1,
0x23034bd1,
0x1d03c4c4,
0x2302ddd1,
0x2306209d,
0x2306119d,
0x05014545,
0x51074514,
0x49004502,
@ -146,7 +144,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2400001e,
0x7f0000c5,
0x24002005,
0x230368d1,
0x230359d1,
0x24000080,
0x2405a4eb,
0x2eff8992,
@ -159,7 +157,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f6,
0x24001d05,
0xc918ff00,
@ -171,7 +169,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0105f6,
0xc918ff00,
0x101f1f00,
@ -272,7 +270,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -291,7 +289,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -314,7 +312,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230382d1,
0x230373d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -339,7 +337,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -358,7 +356,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -381,7 +379,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230382d1,
0x230373d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -398,7 +396,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x20d10000,
0x24000605,
0x2eff8283,
0x230368d1,
0x230359d1,
0x240000c0,
0x2400002d,
0x2300d0d1,
@ -452,32 +450,32 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1f04c4c4,
0x2400060d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000006,
0xc9005005,
0x51fd0304,
0x2400020d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0xc9017005,
0x2400010d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000005,
0xc9015004,
0x2400020d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0xc9027004,
0x2400010d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x111870e0,
0x5100e006,
0x1f03c4c4,
0x2400020d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000008,
0xc9035002,
0x69fd2403,
@ -485,7 +483,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x51fd0404,
0x2400020d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x2400052d,
0x24000605,
0x230113d1,
@ -509,7 +507,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1f05c4c4,
0x2400080d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x14637878,
0x69014502,
0x15ff7878,
@ -575,14 +573,14 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400ff1e,
0x21042000,
0x21041100,
0x69074507,
0xc901c405,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x21047400,
0x21046500,
0x51000c4a,
0x51015b04,
0x100c0c02,
@ -705,7 +703,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21059500,
0x21058400,
0xd1077905,
0xd104ff00,
0xd703ffff,
@ -757,12 +755,12 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0xd1047905,
0x106d6d79,
0x2400037b,
0x21038700,
0x21037800,
0x2102c400,
0x106d6d79,
0x2400027b,
0x21038700,
0x2104c000,
0x21037800,
0x2104af00,
0xd104ff00,
0xd703ffff,
0xd1074d03,
@ -886,7 +884,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x10d1d18b,
0x2400040d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x108b8bd1,
0x810c3c80,
0x20d10000,
@ -895,28 +893,13 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91505880,
0x1f008080,
0x1f00c0c0,
0x1f008181,
0x81505880,
0x2106b200,
0x2106a400,
0x20d10000,
0x117f6666,
0xc9066604,
0x24000066,
0x81031866,
0x7f0000e6,
0x7f0000f5,
0x710f6602,
0x24000f66,
0x590e6604,
@ -1073,7 +1056,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2400017b,
0x2102c500,
0x2400017b,
0x2104c000,
0x2104af00,
0xd104ff00,
0xd703ffff,
0xd1077903,
@ -1101,7 +1084,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2400ff1e,
0x09017979,
0x2400017b,
0x2104c000,
0x2104af00,
0x2eff838e,
0x24003f00,
0x81401800,
@ -1129,7 +1112,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81521802,
0x2400060d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x7900002e,
0xd104ff00,
0xd703ffff,
@ -1137,7 +1120,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2400ff1e,
0x2400010d,
0x000d6666,
0x23035ad1,
0x23034bd1,
0x69fd7309,
0x913d1880,
0x1f040000,
@ -1163,7 +1146,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x686e5303,
0x24000019,
0x79000002,
0x230692d1,
0x230684d1,
0x10535300,
0x10333320,
0x10131340,
@ -1175,7 +1158,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x21046700,
0x21045800,
0x31010004,
0xd104ff00,
0xd703ffff,
@ -1201,23 +1184,20 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0xd105c008,
0x915818c0,
0x5100c007,
0x1f058000,
0x1f050000,
0x81541800,
0x2400060d,
0x2400080d,
0x040d6666,
0x23035ad1,
0x79000017,
0x1d058000,
0x23034bd1,
0x79000014,
0x1d050000,
0x81541800,
0x2400010d,
0x000d6666,
0x23035ad1,
0x91541800,
0x69fd6204,
0x1f028000,
0x1f020000,
0x81541800,
0x79000002,
0x1d028000,
0x1d020000,
0x15e06262,
0x2ed00381,
0xd1060204,
@ -1249,24 +1229,25 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81361800,
0x91081821,
0x10210001,
0x5100010b,
0x51000106,
0x91043880,
0x1f068080,
0x81041880,
0xc8c0c002,
0x2400229f,
0x913d1880,
0x1f060000,
0x813d1880,
0xc9062002,
0x2400269f,
0x91361800,
0x91503802,
0x1d060202,
0x1d060242,
0x51000003,
0x51000009,
0x1f060202,
0x1f060242,
0x1f064242,
0x913d1880,
0x1f060000,
0x813d1800,
0xc9062002,
0x2400269f,
0x79000003,
0x1d060202,
0x1d064242,
0x81503802,
0x10abab8d,
0x21021100,
@ -1372,7 +1353,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x24003001,
0xd1066b0e,
0x2400010d,
0x2307bfd1,
0x2307b6d1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
@ -1385,7 +1366,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81531800,
0x7900003b,
0x2400020d,
0x2307bfd1,
0x2307b6d1,
0x688b8d38,
0x8137184b,
0x13803b3b,
@ -1428,7 +1409,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1d09c4c4,
0x2400040d,
0x24003001,
0x2307bfd1,
0x2307b6d1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1483,7 +1464,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0xc9027a02,
0x01081b1b,
0x2102c500,
0xc901c460,
0xc901c462,
0x24001031,
0x91001800,
0xc9060007,
@ -1492,7 +1473,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x24001e31,
0x2eff829a,
0x1d09c4c4,
0x79000057,
0x79000059,
0x91351800,
0xc9060007,
0x1d060000,
@ -1500,7 +1481,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x24001e31,
0x2eff829a,
0x1d09c4c4,
0x7900004f,
0x79000051,
0xc909c41c,
0x05041b1b,
0x490c1b06,
@ -1508,7 +1489,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x110f3131,
0x69001b02,
0x1d09c4c4,
0x79000047,
0x79000049,
0xc9077a08,
0x905a1831,
0xc9021b03,
@ -1528,7 +1509,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x14809a9a,
0x69101b02,
0x15ff1a1a,
0x79000033,
0x79000035,
0x91401800,
0x513f0013,
0x91531840,
@ -1548,9 +1529,9 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2400201b,
0x2400403b,
0x1f09c4c4,
0x7900001f,
0x79000021,
0x912c1800,
0xc900001d,
0xc900001f,
0x1d000000,
0x812c1800,
0x1f09c4c4,
@ -1558,9 +1539,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1d010000,
0x81511800,
0x91283881,
0x1f070101,
0x1001017a,
0x2400101b,
0xc9050102,
0xc9050103,
0x1f074141,
0x01101b1b,
0x0b031b00,
0x8fc4d801,
@ -1669,7 +1652,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x230679d1,
0x23066bd1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
@ -1693,7 +1676,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x230679d1,
0x23066bd1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1708,6 +1691,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81107880,
0x24000200,
0x814e1800,
0x812e1843,
0x2400209f,
0x2400259f,
0x209d0000,
@ -1782,11 +1766,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81080580,
0x240003c0,
0x810605c0,
0x24000500,
0x24000900,
0x810b1800,
0x81441800,
0x2eff8383,
0x2304189d,
0x2304099d,
0x24000866,
0x2400000c,
0x2400002c,
@ -1795,17 +1779,27 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81001800,
0x2eff8000,
0x81351800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91501880,
0x24000080,
0x13108080,
0x13118080,
0x81501880,
0x91521880,
0x24000080,
0x13108080,
0x13118080,
0x81521880,
0x91541880,
0x24000080,
0x13108080,
0x13118080,
0x81541880,
0x240128e1,
0x90e13382,
@ -1963,7 +1957,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2302ddd1,
0x05012525,
0x4f00258f,
0x79000013,
0x79000009,
0xd118fe04,
0xd105ff00,
0x31080002,
@ -1971,23 +1965,13 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x7f00002b,
0x24000925,
0x24001b8d,
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010ded,
0x6f010df7,
0x05012525,
0x4f0025fa,
0x24001025,
@ -1995,18 +1979,23 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010de1,
0x6f010deb,
0x05012525,
0x4f0025fa,
0x91505880,
0x1d008080,
0x1d00c0c0,
0x1d008181,
0x81505880,
0x810a1846,
0x24001d8d,
0x2301d19d,
0x2301569d,
0x6e0403da,
0x6e2423d9,
0x6e0403df,
0x6e2423de,
0x110f4300,
0x0b044320,
0x6e2000d6,
0x6e2000db,
0x10848480,
0x10434340,
0x10404001,
@ -2015,7 +2004,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x810d3801,
0x2400000d,
0x000d6666,
0x23035ad1,
0x23034bd1,
0x1f08c4c4,
0x110fe05d,
0x01085d5d,
@ -2054,5 +2043,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x2106b200};
0x2106a400};

211
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h
View File

@ -1,6 +1,4 @@
/*
* hdsl_master_icssg_multichannel_ch1_bin.h
*
*
* Copyright (c) 2021-2023, Texas Instruments Incorporated
* All rights reserved not granted herein.
@ -54,7 +52,7 @@
*
*/
const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x21078a00,
0x21078100,
0x2eff8f8e,
0x24000725,
0x24041e8d,
@ -105,19 +103,19 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x5101450a,
0x2400040d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000009,
0x69014508,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000004,
0x2400010d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x1d03c4c4,
0x2302cbd1,
0x2305ac9d,
0x23059d9d,
0x05014545,
0x51074514,
0x49004502,
@ -146,7 +144,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400001e,
0x7f0000c5,
0x24002005,
0x230349d1,
0x23033ad1,
0x24000080,
0x240ca4eb,
0x2eff8992,
@ -159,7 +157,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f6,
0x24001d05,
0xc919ff00,
@ -171,7 +169,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0105f6,
0xc919ff00,
0x103f3f00,
@ -272,7 +270,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x240820eb,
0xf0cd0b0d,
@ -291,7 +289,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -314,7 +312,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230361d1,
0x230352d1,
0x110fcdc0,
0x240868eb,
0xf0c00b00,
@ -339,7 +337,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x240820eb,
0xf0cd0b0d,
@ -358,7 +356,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -381,7 +379,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230361d1,
0x230352d1,
0x110fcdc0,
0x240868eb,
0xf0c00b00,
@ -398,7 +396,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x20d10000,
0x24000605,
0x2eff8283,
0x230349d1,
0x23033ad1,
0x240000c0,
0x2400002d,
0x2300d0d1,
@ -452,32 +450,32 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f04c4c4,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000006,
0xc9005005,
0x51fd0304,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0xc9017005,
0x2400010d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000005,
0xc9015004,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0xc9027004,
0x2400010d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x111870e0,
0x5100e006,
0x1f03c4c4,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000008,
0xc9035002,
0x69fd2403,
@ -485,7 +483,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x51fd0404,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x2400052d,
0x24000605,
0x230113d1,
@ -509,7 +507,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f05c4c4,
0x2400080d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x14637878,
0x69014502,
0x15ff7878,
@ -575,14 +573,14 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400ff1e,
0x2103ac00,
0x21039d00,
0x69074507,
0xc901c405,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400ff1e,
0x21040000,
0x2103f100,
0x51000c2d,
0x51015b04,
0x100c0c02,
@ -691,7 +689,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21052100,
0x21051000,
0xd1077905,
0xd10cff00,
0xd70bffff,
@ -743,12 +741,12 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd1047905,
0x106d6d79,
0x2400037b,
0x21036600,
0x21035700,
0x2102b600,
0x106d6d79,
0x2400027b,
0x21036600,
0x21044c00,
0x21035700,
0x21043b00,
0xd10cff00,
0xd70bffff,
0xd1074d03,
@ -855,7 +853,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10d1d18b,
0x2400040d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x108b8bd1,
0x810c3c80,
0x20d10000,
@ -864,28 +862,13 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91505880,
0x1f008080,
0x1f00c0c0,
0x1f008181,
0x81505880,
0x21063e00,
0x21063000,
0x20d10000,
0x117f6666,
0xc9066604,
0x24000066,
0x81031866,
0x7f0000e6,
0x7f0000f5,
0x710f6602,
0x24000f66,
0x590e6604,
@ -957,7 +940,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400017b,
0x2102b700,
0x2400017b,
0x21044c00,
0x21043b00,
0xd10cff00,
0xd70bffff,
0xd1077903,
@ -985,7 +968,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400ff1e,
0x09017979,
0x2400017b,
0x21044c00,
0x21043b00,
0x2eff838e,
0x24003f00,
0x81401800,
@ -1013,7 +996,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81521802,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x7900002e,
0xd10cff00,
0xd70bffff,
@ -1021,7 +1004,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400ff1e,
0x2400010d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x69fd7309,
0x913d1880,
0x1f040000,
@ -1047,7 +1030,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x686e5303,
0x24000019,
0x79000002,
0x23061ed1,
0x230610d1,
0x10535300,
0x10333320,
0x10131340,
@ -1059,7 +1042,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x2103f300,
0x2103e400,
0x31010004,
0xd10cff00,
0xd70bffff,
@ -1085,23 +1068,20 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd105c008,
0x915818c0,
0x5100c007,
0x1f058000,
0x1f050000,
0x81541800,
0x2400060d,
0x2400080d,
0x040d6666,
0x23033bd1,
0x79000017,
0x1d058000,
0x23032cd1,
0x79000014,
0x1d050000,
0x81541800,
0x2400010d,
0x000d6666,
0x23033bd1,
0x91541800,
0x69fd6204,
0x1f028000,
0x1f020000,
0x81541800,
0x79000002,
0x1d028000,
0x1d020000,
0x15e06262,
0x2ed00381,
0xd1060204,
@ -1133,24 +1113,25 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81361800,
0x91081821,
0x10210001,
0x5100010b,
0x51000106,
0x91043880,
0x1f068080,
0x81041880,
0xc8c0c002,
0x2400229f,
0x913d1880,
0x1f060000,
0x813d1880,
0xc9062002,
0x2400269f,
0x91361800,
0x91503802,
0x1d060202,
0x1d060242,
0x51000003,
0x51000009,
0x1f060202,
0x1f060242,
0x1f064242,
0x913d1880,
0x1f060000,
0x813d1800,
0xc9062002,
0x2400269f,
0x79000003,
0x1d060202,
0x1d064242,
0x81503802,
0x10abab8d,
0x21021100,
@ -1256,7 +1237,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x24003001,
0xd1066b0e,
0x2400010d,
0x23077cd1,
0x230773d1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
@ -1269,7 +1250,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81531800,
0x7900003b,
0x2400020d,
0x23077cd1,
0x230773d1,
0x688b8d38,
0x8137184b,
0x13803b3b,
@ -1312,7 +1293,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1d09c4c4,
0x2400040d,
0x24003001,
0x23077cd1,
0x230773d1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1367,7 +1348,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xc9027a02,
0x01081b1b,
0x2102b700,
0xc901c460,
0xc901c462,
0x24001031,
0x91001800,
0xc9060007,
@ -1376,7 +1357,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x24001e31,
0x2eff829a,
0x1d09c4c4,
0x79000057,
0x79000059,
0x91351800,
0xc9060007,
0x1d060000,
@ -1384,7 +1365,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x24001e31,
0x2eff829a,
0x1d09c4c4,
0x7900004f,
0x79000051,
0xc909c41c,
0x05041b1b,
0x490c1b06,
@ -1392,7 +1373,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x110f3131,
0x69001b02,
0x1d09c4c4,
0x79000047,
0x79000049,
0xc9077a08,
0x905a1831,
0xc9021b03,
@ -1412,7 +1393,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x14809a9a,
0x69101b02,
0x15ff1a1a,
0x79000033,
0x79000035,
0x91401800,
0x513f0013,
0x91531840,
@ -1432,9 +1413,9 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400201b,
0x2400403b,
0x1f09c4c4,
0x7900001f,
0x79000021,
0x912c1800,
0xc900001d,
0xc900001f,
0x1d000000,
0x812c1800,
0x1f09c4c4,
@ -1442,9 +1423,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1d010000,
0x81511800,
0x91283881,
0x1f070101,
0x1001017a,
0x2400101b,
0xc9050102,
0xc9050103,
0x1f074141,
0x01101b1b,
0x0b031b00,
0x8fc4d801,
@ -1553,7 +1536,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400001e,
0x230605d1,
0x2305f7d1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
@ -1577,7 +1560,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400001e,
0x230605d1,
0x2305f7d1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1592,6 +1575,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81107880,
0x24000200,
0x814e1800,
0x812e1843,
0x2400209f,
0x2400259f,
0x209d0000,
@ -1667,11 +1651,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81100580,
0x240003c0,
0x810605c0,
0x24000500,
0x24000900,
0x810b1800,
0x81441800,
0x2eff8383,
0x2303a49d,
0x2303959d,
0x24000866,
0x2400000c,
0x2400002c,
@ -1680,17 +1664,27 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81001800,
0x2eff8000,
0x81351800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91501880,
0x24000080,
0x13108080,
0x13118080,
0x81501880,
0x91521880,
0x24000080,
0x13108080,
0x13118080,
0x81521880,
0x91541880,
0x24000080,
0x13108080,
0x13118080,
0x81541880,
0x240128e1,
0x90e13382,
@ -1896,7 +1890,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10656546,
0x05012525,
0x4f002560,
0x79000013,
0x79000009,
0xd119fe04,
0xd10dff00,
0x31080002,
@ -1904,23 +1898,13 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x7d0000fa,
0x24000925,
0x24001b8d,
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010ded,
0x6f010df7,
0x05012525,
0x4f0025fa,
0x24001025,
@ -1928,18 +1912,23 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010de1,
0x6f010deb,
0x05012525,
0x4f0025fa,
0x91505880,
0x1d008080,
0x1d00c0c0,
0x1d008181,
0x81505880,
0x810a1846,
0x24001d8d,
0x2301d19d,
0x2301569d,
0x6e0403da,
0x6e2423d9,
0x6e0403df,
0x6e2423de,
0x110f4300,
0x0b044320,
0x6e2000d6,
0x6e2000db,
0x10848480,
0x10434340,
0x10404001,
@ -1948,7 +1937,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x810d3801,
0x2400000d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x1f08c4c4,
0x110fe05d,
0x01085d5d,
@ -1987,5 +1976,5 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x21063e00};
0x21063000};

211
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h
View File

@ -1,6 +1,4 @@
/*
* hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h
*
*
* Copyright (c) 2021-2023, Texas Instruments Incorporated
* All rights reserved not granted herein.
@ -54,7 +52,7 @@
*
*/
const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2107ce00,
0x2107c500,
0x2eff8f8e,
0x24000725,
0x24041e8d,
@ -105,19 +103,19 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x5101450a,
0x2400040d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000009,
0x69014508,
0x2400060d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000004,
0x2400010d,
0x000d6666,
0x23035ad1,
0x23034bd1,
0x1d03c4c4,
0x2302ddd1,
0x2306209d,
0x2306119d,
0x05014545,
0x51074514,
0x49004502,
@ -146,7 +144,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2400001e,
0x7f0000c5,
0x24002005,
0x230368d1,
0x230359d1,
0x24000080,
0x240ca4eb,
0x2eff8992,
@ -159,7 +157,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f6,
0x24001d05,
0xc919ff00,
@ -171,7 +169,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0105f6,
0xc919ff00,
0x103f3f00,
@ -272,7 +270,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f7,
0x240820eb,
0xf0cd0b0d,
@ -291,7 +289,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -314,7 +312,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230382d1,
0x230373d1,
0x110fcdc0,
0x240868eb,
0xf0c00b00,
@ -339,7 +337,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f7,
0x240820eb,
0xf0cd0b0d,
@ -358,7 +356,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230382d1,
0x230373d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -381,7 +379,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230382d1,
0x230373d1,
0x110fcdc0,
0x240868eb,
0xf0c00b00,
@ -398,7 +396,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x20d10000,
0x24000605,
0x2eff8283,
0x230368d1,
0x230359d1,
0x240000c0,
0x2400002d,
0x2300d0d1,
@ -452,32 +450,32 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1f04c4c4,
0x2400060d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000006,
0xc9005005,
0x51fd0304,
0x2400020d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0xc9017005,
0x2400010d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000005,
0xc9015004,
0x2400020d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0xc9027004,
0x2400010d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x111870e0,
0x5100e006,
0x1f03c4c4,
0x2400020d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x79000008,
0xc9035002,
0x69fd2403,
@ -485,7 +483,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x51fd0404,
0x2400020d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x2400052d,
0x24000605,
0x230113d1,
@ -509,7 +507,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1f05c4c4,
0x2400080d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x14637878,
0x69014502,
0x15ff7878,
@ -575,14 +573,14 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400ff1e,
0x21042000,
0x21041100,
0x69074507,
0xc901c405,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400ff1e,
0x21047400,
0x21046500,
0x51000c4a,
0x51015b04,
0x100c0c02,
@ -705,7 +703,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21059500,
0x21058400,
0xd1077905,
0xd10cff00,
0xd70bffff,
@ -757,12 +755,12 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0xd1047905,
0x106d6d79,
0x2400037b,
0x21038700,
0x21037800,
0x2102c400,
0x106d6d79,
0x2400027b,
0x21038700,
0x2104c000,
0x21037800,
0x2104af00,
0xd10cff00,
0xd70bffff,
0xd1074d03,
@ -886,7 +884,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x10d1d18b,
0x2400040d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x108b8bd1,
0x810c3c80,
0x20d10000,
@ -895,28 +893,13 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91505880,
0x1f008080,
0x1f00c0c0,
0x1f008181,
0x81505880,
0x2106b200,
0x2106a400,
0x20d10000,
0x117f6666,
0xc9066604,
0x24000066,
0x81031866,
0x7f0000e6,
0x7f0000f5,
0x710f6602,
0x24000f66,
0x590e6604,
@ -1073,7 +1056,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2400017b,
0x2102c500,
0x2400017b,
0x2104c000,
0x2104af00,
0xd10cff00,
0xd70bffff,
0xd1077903,
@ -1101,7 +1084,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2400ff1e,
0x09017979,
0x2400017b,
0x2104c000,
0x2104af00,
0x2eff838e,
0x24003f00,
0x81401800,
@ -1129,7 +1112,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81521802,
0x2400060d,
0x040d6666,
0x23035ad1,
0x23034bd1,
0x7900002e,
0xd10cff00,
0xd70bffff,
@ -1137,7 +1120,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2400ff1e,
0x2400010d,
0x000d6666,
0x23035ad1,
0x23034bd1,
0x69fd7309,
0x913d1880,
0x1f040000,
@ -1163,7 +1146,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x686e5303,
0x24000019,
0x79000002,
0x230692d1,
0x230684d1,
0x10535300,
0x10333320,
0x10131340,
@ -1175,7 +1158,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x21046700,
0x21045800,
0x31010004,
0xd10cff00,
0xd70bffff,
@ -1201,23 +1184,20 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0xd105c008,
0x915818c0,
0x5100c007,
0x1f058000,
0x1f050000,
0x81541800,
0x2400060d,
0x2400080d,
0x040d6666,
0x23035ad1,
0x79000017,
0x1d058000,
0x23034bd1,
0x79000014,
0x1d050000,
0x81541800,
0x2400010d,
0x000d6666,
0x23035ad1,
0x91541800,
0x69fd6204,
0x1f028000,
0x1f020000,
0x81541800,
0x79000002,
0x1d028000,
0x1d020000,
0x15e06262,
0x2ed00381,
0xd1060204,
@ -1249,24 +1229,25 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81361800,
0x91081821,
0x10210001,
0x5100010b,
0x51000106,
0x91043880,
0x1f068080,
0x81041880,
0xc8c0c002,
0x2400229f,
0x913d1880,
0x1f060000,
0x813d1880,
0xc9062002,
0x2400269f,
0x91361800,
0x91503802,
0x1d060202,
0x1d060242,
0x51000003,
0x51000009,
0x1f060202,
0x1f060242,
0x1f064242,
0x913d1880,
0x1f060000,
0x813d1800,
0xc9062002,
0x2400269f,
0x79000003,
0x1d060202,
0x1d064242,
0x81503802,
0x10abab8d,
0x21021100,
@ -1372,7 +1353,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x24003001,
0xd1066b0e,
0x2400010d,
0x2307c0d1,
0x2307b7d1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
@ -1385,7 +1366,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81531800,
0x7900003b,
0x2400020d,
0x2307c0d1,
0x2307b7d1,
0x688b8d38,
0x8137184b,
0x13803b3b,
@ -1428,7 +1409,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1d09c4c4,
0x2400040d,
0x24003001,
0x2307c0d1,
0x2307b7d1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1483,7 +1464,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0xc9027a02,
0x01081b1b,
0x2102c500,
0xc901c460,
0xc901c462,
0x24001031,
0x91001800,
0xc9060007,
@ -1492,7 +1473,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x24001e31,
0x2eff829a,
0x1d09c4c4,
0x79000057,
0x79000059,
0x91351800,
0xc9060007,
0x1d060000,
@ -1500,7 +1481,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x24001e31,
0x2eff829a,
0x1d09c4c4,
0x7900004f,
0x79000051,
0xc909c41c,
0x05041b1b,
0x490c1b06,
@ -1508,7 +1489,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x110f3131,
0x69001b02,
0x1d09c4c4,
0x79000047,
0x79000049,
0xc9077a08,
0x905a1831,
0xc9021b03,
@ -1528,7 +1509,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x14809a9a,
0x69101b02,
0x15ff1a1a,
0x79000033,
0x79000035,
0x91401800,
0x513f0013,
0x91531840,
@ -1548,9 +1529,9 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2400201b,
0x2400403b,
0x1f09c4c4,
0x7900001f,
0x79000021,
0x912c1800,
0xc900001d,
0xc900001f,
0x1d000000,
0x812c1800,
0x1f09c4c4,
@ -1558,9 +1539,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1d010000,
0x81511800,
0x91283881,
0x1f070101,
0x1001017a,
0x2400101b,
0xc9050102,
0xc9050103,
0x1f074141,
0x01101b1b,
0x0b031b00,
0x8fc4d801,
@ -1669,7 +1652,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400001e,
0x230679d1,
0x23066bd1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
@ -1693,7 +1676,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400001e,
0x230679d1,
0x23066bd1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1708,6 +1691,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81107880,
0x24000200,
0x814e1800,
0x812e1843,
0x2400209f,
0x2400259f,
0x209d0000,
@ -1783,11 +1767,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81100580,
0x240003c0,
0x810605c0,
0x24000500,
0x24000900,
0x810b1800,
0x81441800,
0x2eff8383,
0x2304189d,
0x2304099d,
0x24000866,
0x2400000c,
0x2400002c,
@ -1796,17 +1780,27 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81001800,
0x2eff8000,
0x81351800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91501880,
0x24000080,
0x13108080,
0x13118080,
0x81501880,
0x91521880,
0x24000080,
0x13108080,
0x13118080,
0x81521880,
0x91541880,
0x24000080,
0x13108080,
0x13118080,
0x81541880,
0x240128e1,
0x90e13382,
@ -1964,7 +1958,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2302ddd1,
0x05012525,
0x4f00258f,
0x79000013,
0x79000009,
0xd119fe04,
0xd10dff00,
0x31080002,
@ -1972,23 +1966,13 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x7f00002a,
0x24000925,
0x24001b8d,
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010ded,
0x6f010df7,
0x05012525,
0x4f0025fa,
0x24001025,
@ -1996,18 +1980,23 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010de1,
0x6f010deb,
0x05012525,
0x4f0025fa,
0x91505880,
0x1d008080,
0x1d00c0c0,
0x1d008181,
0x81505880,
0x810a1846,
0x24001d8d,
0x2301d19d,
0x2301569d,
0x6e0403da,
0x6e2423d9,
0x6e0403df,
0x6e2423de,
0x110f4300,
0x0b044320,
0x6e2000d6,
0x6e2000db,
0x10848480,
0x10434340,
0x10404001,
@ -2016,7 +2005,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x810d3801,
0x2400000d,
0x000d6666,
0x23035ad1,
0x23034bd1,
0x1f08c4c4,
0x110fe05d,
0x01085d5d,
@ -2055,5 +2044,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x2106b200};
0x2106a400};

60
source/position_sense/hdsl/firmware/transport.asm
View File

@ -119,7 +119,7 @@ transport_on_v_frame:
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SCE
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int4, REG_TMP0.b1, EVENT_S_SCE
; generate interrupt_s
ldi r31.w0, PRU0_ARM_IRQ4
@ -152,7 +152,7 @@ push_1B:
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_VPOS
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int5, REG_TMP0.b1, EVENT_S_VPOS
; generate interrupt_s
ldi r31.w0, PRU0_ARM_IRQ4
@ -283,28 +283,26 @@ transport_on_v_frame_2:
lbco &REG_TMP0.w2, MASTER_REGS_CONST, CRC_SEC_TEMP, 2
qbeq check_for_slave_error_on_secondary_channel, REG_TMP0.w2, 0
; set SCE2 bit in ONLINE_STATUS_2
set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2
set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SCE2
sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
QM_SUB 6
QM_SUB 8
transport_on_v_frame_dont_update_qm_secondary_channel:
qba transport_on_v_frame_2_exit
check_for_slave_error_on_secondary_channel:
; clear SCE2 bit in ONLINE_STATUS_2
clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2
clr REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SCE2
sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
;CRC was correct -> add 1 to QM
QM_ADD 1
; NOTE: QM_ADD uses REG_TMP0. Loading REG_TMP0 again here. It can be optimized.
; No QM updates for CRC check success with safe channel 2
lbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
;check for special character: K29.7 is sent in first byte of secondary vertical channel if slave error occured
; assumption: r21.b3 contains the first byte of secondary vertical channel
qbne transport_on_v_frame_no_vpos2_error, REG_TMP2.b3, K29_7
; set VPOS2 bit in ONLINE_STATUS_2
set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2
set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_VPOS2
sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
qba transport_on_v_frame_vpos2_error_exit
transport_on_v_frame_no_vpos2_error:
clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2
clr REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_VPOS2
transport_on_v_frame_vpos2_error_exit:
; store the data from secondary channel
@ -377,26 +375,28 @@ transport_skip_vpos_update:
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int7:
;set event_s and generate interrupt_s
lbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SSUM
;save events
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2
qbbc update_events_no_int17, REG_TMP0.b1, EVENT_S_SSUM
; generate interrupt_s
ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int17:
summary_no_int:
; Update SUM and SSUM bits in ONLINE_STATUS registers
lbco &REG_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM, 1
lbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3
clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM
clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM
qbeq online_status_sum_clear, REG_TMP0.b0, 0x00
set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM
set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM
set REG_TMP2.b2, REG_TMP2.b2, ONLINE_STATUS_1_SSUM
;set SSUM in EVENT_S and generate interrupt_s
lbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SSUM
;save events
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int17, REG_TMP0.b1, EVENT_S_SSUM
; generate interrupt_s
ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int17:
qba online_status_sum_save
online_status_sum_clear:
clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM
clr REG_TMP2.b2, REG_TMP2.b2, ONLINE_STATUS_1_SSUM
online_status_sum_save:
sbco &REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3
;restore REG_FNC.w0 content
@ -554,7 +554,7 @@ transport_layer_received_short_msg:
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.w0, REG_TMP0.w0, EVENT_S_FRES
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int100, REG_TMP0.b1, EVENT_S_FRES
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ
@ -578,7 +578,7 @@ transport_layer_short_msg_recv_read:
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.w0, REG_TMP0.w0, EVENT_S_FRES
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int10, REG_TMP0.b1, EVENT_S_FRES
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ
@ -702,7 +702,7 @@ update_events_no_int19:
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_MIN
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int20, REG_TMP0.b1, EVENT_S_MIN
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ4
@ -877,12 +877,16 @@ transport_layer_no_short_msg:
clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8)
sbco &REG_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1
lbco &REG_TMP1, MASTER_REGS_CONST, PC_ADD_H, 4
; Bit 7 should be set for long message in PC_ADD_H
set REG_TMP1.b0, REG_TMP1.b0, 7
mov SHORT_MSG.addr, REG_TMP1.b0
ldi SHORT_MSG.bits_left, 16
;using PC_OFF?
qbbc transport_layer_assemble_long_msg_no_pc_off, REG_TMP1.b0, LOFF
; Bit 7 should be set for long message in PC_OFF_H
set REG_TMP1.b2, REG_TMP1.b2, 7
add SHORT_MSG.bits_left, SHORT_MSG.bits_left, 16
transport_layer_assemble_long_msg_no_pc_off:
;save ADDR(+OFF) to memory buffer
@ -931,7 +935,7 @@ update_events_no_int3:
lbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_QMLW
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int16, REG_TMP0.b1, EVENT_S_QMLW
; generate interrupt_s
ldi r31.w0, PRU0_ARM_IRQ4
@ -1144,6 +1148,10 @@ calc_relpos_extend_vel:
; Set POSTX to 2
ldi REG_TMP0.b0, 0x2
sbco &REG_TMP0.b0, MASTER_REGS_CONST, POSTX, 1
; Store PIPE data
sbco &H_FRAME.pipe, MASTER_REGS_CONST, PIPE_D, 1
; signal event mst_intr[0] and PRU0_ARM_IRQ3
ldi r31.w0, 32+0
ldi r31.w0, PRU0_ARM_IRQ3

100
source/position_sense/hdsl/include/hdsl_drv.h
View File

@ -63,6 +63,50 @@ extern "C" {
/* Macros & Typedefs */
/* ========================================================================== */
/**
* \anchor HDSL_LongMessageAddrTypes
* \name HDSL Long Message Addressing Types
*
*
* @{
*/
/** \brief Direct addressing of long messages */
#define HDSL_LONG_MSG_ADDR_DIRECT (0U)
/** \brief Indirect addressing of long messages */
#define HDSL_LONG_MSG_ADDR_INDIRECT (1U)
/** @} */
/**
* \anchor HDSL_LongMessageAddrOffsetModes
* \name HDSL Long Message Addressing with/without offset
*
*
* @{
*/
/** \brief Addressing of long messages without offset */
#define HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET (0U)
/** \brief Addressing of long messages with offset */
#define HDSL_LONG_MSG_ADDR_WITH_OFFSET (1U)
/** @} */
/**
* \anchor HDSL_LongMessageLengths
* \name HDSL Long Message Data Lengths
*
*
* @{
*/
/** \brief No data bytes */
#define HDSL_LONG_MSG_LENGTH_0 (0U)
/** \brief 2 data bytes */
#define HDSL_LONG_MSG_LENGTH_2 (1U)
/** \brief 4 data bytes */
#define HDSL_LONG_MSG_LENGTH_4 (2U)
/** \brief 8 data bytes */
#define HDSL_LONG_MSG_LENGTH_8 (3U)
/** @} */
#define MAX_WAIT 20000
#define HDSL_ICSSG0_INST 0U
@ -92,8 +136,6 @@ extern "C" {
/* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */
#define SYNCEVT_RTR_SYNC10_EVT 0x2C
#define ONLINE_STATUS_1_L_FRES (1<<0)
enum {
MENU_SAFE_POSITION,
MENU_QUALITY_MONITORING,
@ -103,7 +145,7 @@ enum {
MENU_RSSI,
MENU_PC_SHORT_MSG_WRITE,
MENU_PC_SHORT_MSG_READ,
MENU_DIRECT_READ_RID0_LENGTH8,
MENU_DIRECT_READ_RID0_LENGTH4,
MENU_DIRECT_READ_RID81_LENGTH8,
MENU_DIRECT_READ_RID81_LENGTH2,
MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0,
@ -386,7 +428,7 @@ uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle);
uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle);
/**
* \brief Write Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) with gPc_data and Short message control value(SLAVE_REG_CTRL) in hdsl interface
* \brief Trigger a short message write operation using parameters channel
*
* \param[in] hdslHandle
* \param[in] addr Address
@ -396,10 +438,10 @@ uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle);
* \return SystemP_SUCCESS in case of success, SystemP_TIMEOUT in case of timeout
*
*/
int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t data, uint64_t timeout);
int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t data, uint64_t timeout);
/**
* \brief Read Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) and write Short message control value(SLAVE_REG_CTRL) with gPc_addr in hdsl interface
* \brief Trigger a short message read operation using parameters channel
*
* \param[in] hdslHandle
* \param[in] addr Address
@ -409,44 +451,50 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat
* \return SystemP_SUCCESS in case of success, SystemP_TIMEOUT in case of timeout
*
*/
int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *data, uint64_t timeout);
int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t *data, uint64_t timeout);
/**
* \brief Write PC_AAD_L ,PC_ADD_H ,PC_OFF_L,PC_OFF_H and PC_CTRL values in hdsl interface
* \brief Trigger a long message write operation using parameters channel.
* Call \ref HDSL_write_pc_buffer before this to write the data to be sent using long message.
*
* \param[in] hdslHandle
* \param[in] pc_addrh
* \param[in] pc_addrl
* \param[in] pc_offh
* \param[in] pc_offl
* \param[in] addr 10 bit address for long message
* \param[in] offsetEnable Addressing with offset enable/disable from \ref HDSL_LongMessageAddrOffsetModes
* \param[in] addrType Addressing Type from \ref HDSL_LongMessageAddrTypes
* \param[in] length Length from \ref HDSL_LongMessageLength
* \param[in] offset 15 bit address offset for long message (if offset is enabled in offsetEnable parameter)
* \param[in] timeout Timeout in microseconds
*
* \return SystemP_SUCCESS in case of success, SystemP_FAILURE in case of error, SystemP_TIMEOUT in case of timeout
*
*/
void HDSL_set_pc_addr(HDSL_Handle hdslHandle, uint8_t pc_addrh, uint8_t pc_addrl, uint8_t pc_offh, uint8_t pc_offl);
int32_t HDSL_write_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout);
/**
* \brief To set the direction read/write for long message communication
*
* \brief Trigger a long message read operation using parameters channel
* If this API returns SystemP_SUCCESS, call \ref HDSL_read_pc_buffer after this to read the data received using long message.
* \param[in] hdslHandle
* \param[in] value
* \param[in] addr 10 bit address for long message
* \param[in] offsetEnable Addressing with offset enable/disable from \ref HDSL_LongMessageAddrOffsetModes
* \param[in] addrType Addressing Type from \ref HDSL_LongMessageAddrTypes
* \param[in] length Length from \ref HDSL_LongMessageLength
* \param[in] offset 15 bit address offset for long message
* \param[in] timeout Timeout in microseconds
*
* \return SystemP_SUCCESS in case of success, SystemP_FAILURE in case of error, SystemP_TIMEOUT in case of timeout
*
*/
void HDSL_set_pc_ctrl(HDSL_Handle hdslHandle, uint8_t value);
int32_t HDSL_read_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout);
/**
* \brief Write Parameters channel buffer for different bytes(bytes 0-7)
*
* \param[in] hdslHandle
* \param[in] pc_buf0
* \param[in] pc_buf1
* \param[in] pc_buf2
* \param[in] pc_buf3
* \param[in] pc_buf4
* \param[in] pc_buf5
* \param[in] pc_buf6
* \param[in] pc_buf7
* \param[in] buff_off
* \param[in] data
*
*/
void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t pc_buf0, uint8_t pc_buf1, uint8_t pc_buf2, uint8_t pc_buf3, uint8_t pc_buf4, uint8_t pc_buf5, uint8_t pc_buf6, uint8_t pc_buf7);
void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off, uint8_t data);
/**
* \brief Returns Parameters channel buffer for different bytes(bytes 0-7)