From 35788f6e6457ba1739dbd0635637ab3ee0f75585 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Fri, 22 Sep 2023 16:24:52 +0530 Subject: [PATCH 1/7] am64x/am243x: hdsl: Fix the reset value of PRST bit in status/event - Set the bit during initialization for status and event registers - Unset the bit in status registers after link_check state Fixes: PINDSW-6628 Signed-off-by: Dhaval Khandla --- .../position_sense/hdsl/firmware/datalink.asm | 36 +-- .../hdsl/firmware/datalink_init.asm | 56 +++-- .../position_sense/hdsl/firmware/defines.inc | 2 +- .../hdsl_master_icssg_multichannel_ch0_bin.h | 211 ++++++------------ 4 files changed, 111 insertions(+), 194 deletions(-) diff --git a/source/position_sense/hdsl/firmware/datalink.asm b/source/position_sense/hdsl/firmware/datalink.asm index 789d0a3..bace865 100644 --- a/source/position_sense/hdsl/firmware/datalink.asm +++ b/source/position_sense/hdsl/firmware/datalink.asm @@ -1470,23 +1470,23 @@ is_val_FC: qba adjustment_done is_val_F8: qbne is_val_F0, EXTRA_EDGE_SELF, 0xF8 - sub REG_TMP0, REG_TMP0, 12 + sub REG_TMP0, REG_TMP0, 12 qba adjustment_done is_val_F0: qbne is_val_E0, EXTRA_EDGE_SELF, 0xF0 - sub REG_TMP0, REG_TMP0, 16 + sub REG_TMP0, REG_TMP0, 16 qba adjustment_done is_val_E0: qbne is_val_C0, EXTRA_EDGE_SELF, 0xE0 - sub REG_TMP0, REG_TMP0, 20 + sub REG_TMP0, REG_TMP0, 20 qba adjustment_done is_val_C0: qbne is_val_80, EXTRA_EDGE_SELF, 0xC0 - sub REG_TMP0, REG_TMP0, 24 + sub REG_TMP0, REG_TMP0, 24 qba adjustment_done is_val_80: qbne adjustment_done,EXTRA_EDGE_SELF, 0x80 - sub REG_TMP0, REG_TMP0, 28 + sub REG_TMP0, REG_TMP0, 28 qba adjustment_done adjustment_done: sbco ®_TMP0, MASTER_REGS_CONST, EXTRA_EDGE_TIMESTAMP, 4 @@ -1570,7 +1570,6 @@ log_done1: ;HINT: we have processing time here (~168 cycles) ;check if we reset protocol lbco &FIFO_L, MASTER_REGS_CONST, SYS_CTRL, 1 -;ERROR: qbbc datalink_abort2 is not working, though no compiler error qbbc SYS_CTRL_PRST_cleared,FIFO_L, SYS_CTRL_PRST jmp No_long_short_msg SYS_CTRL_PRST_cleared: @@ -1879,31 +1878,6 @@ datalink_abort_no_wait: lbco ®_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1 add REG_TMP0.b0, REG_TMP0.b0, 1 sbco ®_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1 -; Set EVENT_PRST in EVENT register - lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 - set REG_TMP0.w0, REG_TMP0.w0, EVENT_PRST -;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 - qbbc update_events_no_int2, REG_TMP0.w2, EVENT_PRST -; generate interrupt - ldi r31.w0, PRU0_ARM_IRQ -update_events_no_int2: -; Set EVENT_S_PRST in EVENT_S register - lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 - set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST -;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 - qbbc update_events_no_int18, REG_TMP0.b1, EVENT_S_PRST -; generate interrupt - ldi r31.w0, PRU0_ARM_IRQ4 -update_events_no_int18: - -; Set PRST bits in ONLINE_STATUS registers - lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 - set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST - set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST - set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST - sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6 jmp datalink_reset ;-------------------------------------------------------------------------------------------------- ;Function: switch_clk (RET_ADDR1) diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm index 4e4f30d..76f26d9 100644 --- a/source/position_sense/hdsl/firmware/datalink_init.asm +++ b/source/position_sense/hdsl/firmware/datalink_init.asm @@ -101,30 +101,48 @@ datalink_reset: ;reset SAFE_CTRL register zero ®_TMP0.b0, 1 sbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_CTRL, 1 +; Set EVENT_PRST in EVENT_H register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + set REG_TMP0.w0, REG_TMP0.w0, EVENT_PRST +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int15, REG_TMP0.w2, EVENT_PRST +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int15: +; Set EVENT_S_PRST in EVENT_S register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 + set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + qbbc update_events_no_int22, REG_TMP0.b1, EVENT_S_PRST +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ4 +update_events_no_int22: ; Initialize ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2 ; In ONLINE_STATUS_D high, bit 2 is FIX0, bit 4 is FIX1 and bit 5 is FIX0 ; In ONLINE_STATUS_D low, bit 0 is FIX0 and bit 3 is FIX0 lbco ®_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 2 ; clearing bits ldi REG_TMP0.w0, 0 - ; setting bits with fix1 - or REG_TMP0.w0, REG_TMP0.w0, (1< Date: Fri, 22 Sep 2023 18:43:53 +0530 Subject: [PATCH 2/7] am64x/am243x: hdsl: Fix the QM update for safe channel 2 - Remove increment by 1 after CRC check success on safe channel 2 data - For CRC check failure, decrement by 8 Fixes: PINDSW-6944 Signed-off-by: Dhaval Khandla --- .../hdsl_master_icssg_multichannel_ch0_bin.h | 35 +++++++++---------- .../hdsl/firmware/transport.asm | 6 ++-- 2 files changed, 18 insertions(+), 23 deletions(-) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h index b127eae..f91bfc7 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h @@ -1,5 +1,5 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { -0x21077f00, +0x21077c00, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -62,7 +62,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x23032cd1, 0x1d03c4c4, 0x2302cbd1, -0x23059d9d, +0x23059a9d, 0x05014545, 0x51074514, 0x49004502, @@ -636,7 +636,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21051200, +0x21050f00, 0xd1077905, 0xd104ff00, 0xd703ffff, @@ -693,7 +693,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x106d6d79, 0x2400027b, 0x21035700, -0x21043d00, +0x21043a00, 0xd104ff00, 0xd703ffff, 0xd1074d03, @@ -809,7 +809,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x21062f00, +0x21062c00, 0x20d10000, 0x117f6666, 0xc9066604, @@ -887,7 +887,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x2400017b, 0x2102b700, 0x2400017b, -0x21043d00, +0x21043a00, 0xd104ff00, 0xd703ffff, 0xd1077903, @@ -915,7 +915,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x21043d00, +0x21043a00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -977,7 +977,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x23060fd1, +0x23060cd1, 0x10535300, 0x10333320, 0x10131340, @@ -1017,15 +1017,12 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x5100c007, 0x1f058000, 0x81541800, -0x2400060d, +0x2400080d, 0x040d6666, 0x23032cd1, -0x79000017, +0x79000014, 0x1d058000, 0x81541800, -0x2400010d, -0x000d6666, -0x23032cd1, 0x91541800, 0x69fd6204, 0x1f028000, @@ -1186,7 +1183,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x230771d1, +0x23076ed1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1199,7 +1196,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x230771d1, +0x23076ed1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1242,7 +1239,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x230771d1, +0x23076ed1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1483,7 +1480,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x2305f6d1, +0x2305f3d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1507,7 +1504,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x2305f6d1, +0x2305f3d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1921,5 +1918,5 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x21062f00}; +0x21062c00}; diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 6286c35..db55d73 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -285,16 +285,14 @@ transport_on_v_frame_2: ; set SCE2 bit in ONLINE_STATUS_2 set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 - QM_SUB 6 + QM_SUB 8 transport_on_v_frame_dont_update_qm_secondary_channel: qba transport_on_v_frame_2_exit check_for_slave_error_on_secondary_channel: ; clear SCE2 bit in ONLINE_STATUS_2 clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 -;CRC was correct -> add 1 to QM - QM_ADD 1 -; NOTE: QM_ADD uses REG_TMP0. Loading REG_TMP0 again here. It can be optimized. +; No QM updates for CRC check success with safe channel 2 lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ;check for special character: K29.7 is sent in first byte of secondary vertical channel if slave error occured ; assumption: r21.b3 contains the first byte of secondary vertical channel From 3e7fbec549fd3e5d08c00e4eef93df3426580b33 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 10 Oct 2023 11:57:59 +0530 Subject: [PATCH 3/7] am64x/am243x: hdsl: Add support for PIPE_D register Fixes: PINDSW-7030 Signed-off-by: Dhaval Khandla --- source/position_sense/hdsl/firmware/defines.inc | 2 +- source/position_sense/hdsl/firmware/transport.asm | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc index 749bfd4..e336c9f 100644 --- a/source/position_sense/hdsl/firmware/defines.inc +++ b/source/position_sense/hdsl/firmware/defines.inc @@ -34,7 +34,7 @@ ; bit7..4 major number FIRMWARE_VERSION_MAJOR .set 0x0 ; bit3..0 minor number -FIRMWARE_VERSION_MINOR .set 0x6 +FIRMWARE_VERSION_MINOR .set 0x7 ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index db55d73..884d1dc 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -1142,6 +1142,10 @@ calc_relpos_extend_vel: ; Set POSTX to 2 ldi REG_TMP0.b0, 0x2 sbco ®_TMP0.b0, MASTER_REGS_CONST, POSTX, 1 + +; Store PIPE data + sbco &H_FRAME.pipe, MASTER_REGS_CONST, PIPE_D, 1 + ; signal event mst_intr[0] and PRU0_ARM_IRQ3 ldi r31.w0, 32+0 ldi r31.w0, PRU0_ARM_IRQ3 From 450ce5a37fe2518f3940737ade5ac98e52d54f0a Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Mon, 23 Oct 2023 16:24:01 +0530 Subject: [PATCH 4/7] am64x/am243x: hdsl: Fix compiler warnings Fixes: PINDSW-7020 Signed-off-by: Dhaval Khandla --- .../hdsl_diagnostic/hdsl_diagnostic.c | 81 +++++++++++++++++-- .../hdsl_diagnostic/hdsl_diagnostic.h | 20 ----- 2 files changed, 73 insertions(+), 28 deletions(-) diff --git a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c index b47e295..c8b9cef 100644 --- a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c +++ b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c @@ -30,6 +30,10 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + #include #include @@ -71,6 +75,10 @@ #include #include +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + #if (CONFIG_HDSL0_CHANNEL0 + CONFIG_HDSL0_CHANNEL1 > 1) #define HDSL_MULTI_CHANNEL #endif @@ -119,6 +127,68 @@ #define HDSL_MEMORY_TRACE_R5F_IRQ_NUM (CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_3) #endif +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +#if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_) + +void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData); + +static void App_udmaTrpdInit(Udma_ChHandle chHandle, + uint8_t *trpdMem, + const void *destBuf, + const void *srcBuf, + uint32_t length); + +void udma_copy(uint8_t *srcBuf, uint8_t *destBuf, uint32_t length); + +static void HDSL_IsrFxn(); + +#ifndef HDSL_MULTI_CHANNEL +void traces_into_memory(HDSL_Handle hdslHandle); +#endif + +void sync_calculation(HDSL_Handle hdslHandle); + +void process_request(HDSL_Handle hdslHandle,int32_t menu); + +void hdsl_pruss_init(void); + +void hdsl_pruss_init_300m(void); + +void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle); + +void hdsl_init(void); + +void hdsl_init_300m(void); + +void TC_read_pc_short_msg(HDSL_Handle hdslHandle); + +void TC_write_pc_short_msg(HDSL_Handle hdslHandle); + +static void display_menu(void); + +void direct_read_rid0_length4(HDSL_Handle hdslHandle); + +void direct_read_rid81_length8(HDSL_Handle hdslHandle); + +void direct_read_rid81_length2(HDSL_Handle hdslHandle); + +void indirect_write_rid0_length8_offset0(HDSL_Handle hdslHandle); + +void indirect_write_rid0_length8(HDSL_Handle hdslHandle); + +static int get_menu(void); + +#ifdef HDSL_AM64xE1_TRANSCEIVER +static void hdsl_i2c_io_expander(void *args); +#endif + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + HDSL_Handle gHdslHandleCh0; HDSL_Handle gHdslHandleCh1; @@ -165,15 +235,10 @@ HwiP_Object gPRUHwiObject; uint8_t gUdmaTestTrpdMem[UDMA_TEST_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT))); #endif -#if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_) +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ -void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData); - -static void App_udmaTrpdInit(Udma_ChHandle chHandle, - uint8_t *trpdMem, - const void *destBuf, - const void *srcBuf, - uint32_t length); static void App_udmaTrpdInit(Udma_ChHandle chHandle, uint8_t *trpdMem, diff --git a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.h b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.h index ab47291..a9821bd 100644 --- a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.h +++ b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.h @@ -56,26 +56,6 @@ extern "C" { /* UDMA TR packet descriptor memory size - with one TR */ #define UDMA_TEST_TRPD_SIZE (UDMA_GET_TRPD_TR15_SIZE(1U)) -/* ISR for v-frame-reception */ -static void HDSL_IsrFxn(void); -void TC_read_pc_short_msg(); -void TC_write_pc_short_msg(); - -#ifndef HDSL_MULTI_CHANNEL -/* - * @brief It will test copy of traces into memory - * \n Here user will decide how many copies of HDSL_Interface_Register - * \n will be copied into memory - */ -void traces_into_memory(); -#endif - -void direct_read_rid0_length8(); -void direct_read_rid81_length8(); -void direct_read_rid81_length2(); -void indirect_write_rid0_length8(); -void indirect_write_rid0_length8_offset0(); - #ifdef __cplusplus } #endif From 54303c850ee07fcfe7231a7421eb8f6f0faabcd7 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 17 Oct 2023 15:25:36 +0530 Subject: [PATCH 5/7] am64x/am243x: hdsl: Add APIs for long message read and write - Also update the HDSL_write_pc_buffer API - Update the SDK example to use updated APIs - Set bit 7 in PC_ADD_H and PC_OFF_H in firmware for long messages Fixes: PINDSW-7032 Signed-off-by: Dhaval Khandla --- .../position_sense/hdsl_exceptions_list.md | 2 + .../position_sense/hdsl_registers_list.md | 2 +- .../hdsl_diagnostic/hdsl_diagnostic.c | 301 ++++++++++-------- source/position_sense/hdsl/driver/hdsl_drv.c | 275 +++++++++++++--- .../hdsl_master_icssg_multichannel_ch0_bin.h | 95 ++++-- ...ter_icssg_multichannel_ch0_sync_mode_bin.h | 165 +++++----- .../hdsl_master_icssg_multichannel_ch1_bin.h | 166 +++++----- ...ter_icssg_multichannel_ch1_sync_mode_bin.h | 166 +++++----- .../hdsl/firmware/transport.asm | 4 + source/position_sense/hdsl/include/hdsl_drv.h | 100 ++++-- 10 files changed, 792 insertions(+), 484 deletions(-) diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md b/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md index 9c105d3..4a07901 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md @@ -159,4 +159,6 @@ Notable exceptions in TI HDSL Solution when compared with SICK HDSL MASTER IP Co 6. Reset values of registers are not same as SICK HDSL MASTER IP Core. 7. As registers are implemented using Data Memory of Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS), the application has a read-write access for all registers. 8. When safe position is invalid (VPOS bit is set in EVENT_S), 0xFDFDFDFDFD value is not set in fast and safe position registers. +9. For long message offset, only 15-bit wide offset is supported. If offset is enabled, then master will always send 2 bytes of offset. + diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md b/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md index 952ad3c..b18364f 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md @@ -984,7 +984,7 @@ TI HDSL Solution's register map is compatible with SICK HDSL MASTER IP Core rele Bits 9:8 of 10 bit address for a "long message" operation - PC_ADD_H + PC_ADD_L 0x29 Long message address (Low Byte) diff --git a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c index c8b9cef..ae3818f 100644 --- a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c +++ b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c @@ -105,9 +105,12 @@ #define CTR_EN (1 << 3) #define MAX_WAIT 20000 -/*Timeout in micorseconds for short message read/write*/ +/*Timeout in micro-seconds for short message read/write*/ #define SHORT_MSG_TIMEOUT (1000) +/*Timeout in micro-seconds for long message read/write*/ +#define LONG_MSG_TIMEOUT (200000) + /*Register Addresses for Short Messages (Parameter Channel)*/ #define ENCODER_STATUS0_REG_ADDRESS (0x40) @@ -185,6 +188,8 @@ static int get_menu(void); static void hdsl_i2c_io_expander(void *args); #endif +uint32_t read_encoder_resolution(HDSL_Handle hdslHandle); + /* ========================================================================== */ /* Global Variables */ /* ========================================================================== */ @@ -632,8 +637,8 @@ void process_request(HDSL_Handle hdslHandle,int32_t menu) case MENU_PC_SHORT_MSG_READ: TC_read_pc_short_msg(hdslHandle); break; - case MENU_DIRECT_READ_RID0_LENGTH8: - direct_read_rid0_length8(hdslHandle); + case MENU_DIRECT_READ_RID0_LENGTH4: + direct_read_rid0_length4(hdslHandle); break; case MENU_DIRECT_READ_RID81_LENGTH8: direct_read_rid81_length8(hdslHandle); @@ -830,6 +835,7 @@ void hdsl_init(void) HDSL_generate_memory_image(gHdslHandleCh0); } } + void hdsl_init_300m(void) { uint8_t ES; @@ -975,16 +981,16 @@ static void display_menu(void) DebugP_log("\r\n | %2d : RSSI |", MENU_RSSI); DebugP_log("\r\n | %2d : Parameter Channel Short Message Write |", MENU_PC_SHORT_MSG_WRITE); DebugP_log("\r\n | %2d : Parameter Channel Short Message Read |", MENU_PC_SHORT_MSG_READ); - DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID0_LENGTH8); - DebugP_log("\r\n | Access on RID 0h, direct read access with length 8 |"); + DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID0_LENGTH4); + DebugP_log("\r\n | Access on RID 0x0, direct read access with length 4 |"); DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID81_LENGTH8); - DebugP_log("\r\n | Access on RID 81h, direct read access with length 8 |"); + DebugP_log("\r\n | Access on RID 0x81, direct read access with length 8 |"); DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID81_LENGTH2); - DebugP_log("\r\n | Access on RID 81h, direct read access with length 2 |"); + DebugP_log("\r\n | Access on RID 0x81, direct read access with length 2 and offset 3 |"); DebugP_log("\r\n | %2d : Parameter Channel Long Message Write |", MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0); - DebugP_log("\r\n | Access on RID 0h, indirect write, length 8, with offset 0 |"); + DebugP_log("\r\n | Access on RID 0x0, indirect write, length 8, with offset 0 |"); DebugP_log("\r\n | %2d : Parameter Channel Long Message Write |", MENU_INDIRECT_WRITE_RID0_LENGTH8); - DebugP_log("\r\n | Access on RID 0h; indirect write, length 8, without offset value |"); + DebugP_log("\r\n | Access on RID 0x0; indirect write, length 8, without offset value |"); #if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_) DebugP_log("\r\n | %2d : HDSL registers into Memory |", MENU_HDSL_REG_INTO_MEMORY); #endif @@ -992,242 +998,246 @@ static void display_menu(void) DebugP_log("\r\n Enter value: "); } -void direct_read_rid0_length8(HDSL_Handle hdslHandle) +void direct_read_rid0_length4(HDSL_Handle hdslHandle) { - uint8_t dir = 0x01; + int32_t status = SystemP_FAILURE; - gPc_addrh = 0xec; - gPc_addrl = 0x00; - gPc_offh = 0x80; - gPc_offl = 0x00; + DebugP_log("\r\n Parameter channel long message read : RID 0, Length 4"); - HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + /* Set the parameter channel buffers to 0xff */ + HDSL_write_pc_buffer(hdslHandle, 0, 0xff); + HDSL_write_pc_buffer(hdslHandle, 1, 0xff); + HDSL_write_pc_buffer(hdslHandle, 2, 0xff); + HDSL_write_pc_buffer(hdslHandle, 3, 0xff); - HDSL_set_pc_ctrl(hdslHandle,dir); + status = HDSL_read_pc_long_msg(hdslHandle, 0, HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET, HDSL_LONG_MSG_ADDR_DIRECT, HDSL_LONG_MSG_LENGTH_4, 0, LONG_MSG_TIMEOUT); - ClockP_sleep(1); - - gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); - - if(gPc_buf0 == 82) + if(SystemP_SUCCESS != status) { - gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); - if(gPc_buf1 == 79) + DebugP_log("\r\n FAIL: HDSL_read_pc_long_msg() did not return success"); + return; + } + + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0); + + if(gPc_buf0 == 'R') + { + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1); + if(gPc_buf1 == 'O') { - gPc_buf2 = HDSL_read_pc_buffer(hdslHandle,2); - if(gPc_buf2 == 79) + gPc_buf2 = HDSL_read_pc_buffer(hdslHandle, 2); + if(gPc_buf2 == 'O') { - gPc_buf3 = HDSL_read_pc_buffer(hdslHandle,3); - if(gPc_buf3 == 84) + gPc_buf3 = HDSL_read_pc_buffer(hdslHandle, 3); + if(gPc_buf3 == 'T') { - DebugP_log("\r\n PASS"); + DebugP_log("\r\n PASS : Read \"ROOT\""); } else { - DebugP_log("\r\n FAIL: gPc_buf3 != T = %u", gPc_buf3); + DebugP_log("\r\n FAIL: PC_BUFFER3 != T (It is %u)", gPc_buf3); } } else { - DebugP_log("\r\n FAIL: gPc_buf2 != O = %u", gPc_buf2); + DebugP_log("\r\n FAIL: PC_BUFFER2 != O (It is %u)", gPc_buf2); } } else { - DebugP_log("\r\n FAIL: gPc_buf1 != O = %u", gPc_buf1); + DebugP_log("\r\n FAIL: PC_BUFFER1 != O (It is %u)", gPc_buf1); } } else { - DebugP_log("\r\n FAIL: gPc_buf0 != R = %u", gPc_buf0); + DebugP_log("\r\n FAIL: PC_BUFFER0 != R (It is %u)", gPc_buf0); } } -void direct_read_rid81_length8(HDSL_Handle hdslHandle) +void direct_read_rid81_length8(HDSL_Handle hdslHandle) { - uint8_t dir = 0x01; - gPc_addrh = 0xec; - gPc_addrl = 0x81; - gPc_offh = 0x80; - gPc_offl = 0x00; + int32_t status = SystemP_FAILURE; - HDSL_set_pc_addr( hdslHandle,gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + DebugP_log("\r\n Parameter channel long message read : RID 0x81, Length 8"); - HDSL_set_pc_ctrl(hdslHandle,dir); + /* Set the parameter channel buffers to 0xff */ + HDSL_write_pc_buffer(hdslHandle, 0, 0xff); + HDSL_write_pc_buffer(hdslHandle, 1, 0xff); + HDSL_write_pc_buffer(hdslHandle, 2, 0xff); + HDSL_write_pc_buffer(hdslHandle, 3, 0xff); + HDSL_write_pc_buffer(hdslHandle, 4, 0xff); + HDSL_write_pc_buffer(hdslHandle, 5, 0xff); + HDSL_write_pc_buffer(hdslHandle, 6, 0xff); + HDSL_write_pc_buffer(hdslHandle, 7, 0xff); - ClockP_sleep(1); + status = HDSL_read_pc_long_msg(hdslHandle, 0x81, HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET, HDSL_LONG_MSG_ADDR_DIRECT, HDSL_LONG_MSG_LENGTH_8, 0, LONG_MSG_TIMEOUT); - gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); - if(gPc_buf0 == 82) + if(SystemP_SUCCESS != status) { - gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); - if(gPc_buf1 == 69) + DebugP_log("\r\n FAIL: HDSL_read_pc_long_msg() did not return success"); + return; + } + + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0); + if(gPc_buf0 == 'R') + { + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1); + if(gPc_buf1 == 'E') { - gPc_buf2 = HDSL_read_pc_buffer(hdslHandle,2); - if(gPc_buf2 == 83) + gPc_buf2 = HDSL_read_pc_buffer(hdslHandle, 2); + if(gPc_buf2 == 'S') { - gPc_buf3 = HDSL_read_pc_buffer(hdslHandle,3); - if(gPc_buf3 == 79) + gPc_buf3 = HDSL_read_pc_buffer(hdslHandle, 3); + if(gPc_buf3 == 'O') { - gPc_buf4 = HDSL_read_pc_buffer(hdslHandle,4); - if(gPc_buf4 == 76) + gPc_buf4 = HDSL_read_pc_buffer(hdslHandle, 4); + if(gPc_buf4 == 'L') { - gPc_buf5 = HDSL_read_pc_buffer(hdslHandle,5); - if(gPc_buf5 == 85) + gPc_buf5 = HDSL_read_pc_buffer(hdslHandle, 5); + if(gPc_buf5 == 'U') { - gPc_buf6 = HDSL_read_pc_buffer(hdslHandle,6); - if(gPc_buf6 == 84) + gPc_buf6 = HDSL_read_pc_buffer(hdslHandle, 6); + if(gPc_buf6 == 'T') { - gPc_buf7 = HDSL_read_pc_buffer(hdslHandle,7); - if(gPc_buf7 == 78) + gPc_buf7 = HDSL_read_pc_buffer(hdslHandle, 7); + if(gPc_buf7 == 'N') { - DebugP_log("\r\n PASS "); + DebugP_log("\r\n PASS : Read \"RESOLUTN\""); } else { - DebugP_log("\r\n FAIL: gPc_buf7 != N ", gPc_buf7); + DebugP_log("\r\n FAIL: PC_BUFFER7 != N (It is %u)", gPc_buf7); } } else { - DebugP_log("\r\n FAIL: gPc_buf6 != T ", gPc_buf6); + DebugP_log("\r\n FAIL: PC_BUFFER6 != T (It is %u)", gPc_buf6); } } else { - DebugP_log("\r\n FAIL: gPc_buf5 != U ", gPc_buf5); + DebugP_log("\r\n FAIL: PC_BUFFER5 != U (It is %u)", gPc_buf5); } } else { - DebugP_log("\r\n FAIL: gPc_buf4 != L ", gPc_buf4); + DebugP_log("\r\n FAIL: PC_BUFFER4 != L (It is %u)", gPc_buf4); } } else { - DebugP_log("\r\n FAIL: gPc_buf3 != O ", gPc_buf3); + DebugP_log("\r\n FAIL: PC_BUFFER3 != O (It is %u)", gPc_buf3); } } else { - DebugP_log("\r\n FAIL: gPc_buf2 != S = %u", gPc_buf2); + DebugP_log("\r\n FAIL: PC_BUFFER2 != S (It is %u)", gPc_buf2); } } else { - DebugP_log("\r\n FAIL: gPc_buf1 != E = %u", gPc_buf1); + DebugP_log("\r\n FAIL: PC_BUFFER1 != E (It is %u)", gPc_buf1); } } else { - DebugP_log("\r\n FAIL: gPc_buf0 != R = %u", gPc_buf0); + DebugP_log("\r\n FAIL: PC_BUFFER0 != R (It is %u)", gPc_buf0); } } -void direct_read_rid81_length2(HDSL_Handle hdslHandle) +void direct_read_rid81_length2(HDSL_Handle hdslHandle) { - uint8_t dir = 0x01; + int32_t status = SystemP_FAILURE; - gPc_addrh = 0xe4; - gPc_addrl = 0x81; - gPc_offh = 0x80; - gPc_offl = 0x03; + DebugP_log("\r\n Parameter channel long message read : RID 0x81, Offset 3, Length 2"); - HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + /* Set the parameter channel buffers to 0xaa */ + HDSL_write_pc_buffer(hdslHandle, 0, 0xaa); + HDSL_write_pc_buffer(hdslHandle, 1, 0xaa); - HDSL_set_pc_ctrl(hdslHandle,dir); + status = HDSL_read_pc_long_msg(hdslHandle, 0x81, HDSL_LONG_MSG_ADDR_WITH_OFFSET, HDSL_LONG_MSG_ADDR_DIRECT, HDSL_LONG_MSG_LENGTH_2, 3, LONG_MSG_TIMEOUT); - ClockP_sleep(1); + if(SystemP_SUCCESS != status) + { + DebugP_log("\r\n FAIL: HDSL_read_pc_long_msg() did not return success"); + return; + } - gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0); if(gPc_buf0 == 0x00) { - gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1); if(gPc_buf1 == 0x0f) { - DebugP_log("\r\n PASS "); - + DebugP_log("\r\n PASS : Read 15"); } else { - DebugP_log("\r\n FAIL: gPc_buf1 != 0x0f = %u", gPc_buf1); + DebugP_log("\r\n FAIL: PC_BUFFER1 != 0x0f (It is %u)", gPc_buf1); } } else { - DebugP_log("\r\n FAIL: gPc_buf0 != 0x00 = %u", gPc_buf0); + DebugP_log("\r\n FAIL: PC_BUFFER0 != 0x00 (It is %u)", gPc_buf0); } } -void indirect_write_rid0_length8_offset0(HDSL_Handle hdslHandle) +void indirect_write_rid0_length8_offset0(HDSL_Handle hdslHandle) { - uint8_t dir = 0x01; + DebugP_log("\r\n Parameter channel long message write : RID 0x0, Offset 0, Length 8"); - gPc_addrh = 0xbc; - gPc_addrl = 0x00; - gPc_offh = 0x80; - gPc_offl = 0x00; + HDSL_write_pc_long_msg(hdslHandle, 0x0, HDSL_LONG_MSG_ADDR_WITH_OFFSET, HDSL_LONG_MSG_ADDR_INDIRECT, HDSL_LONG_MSG_LENGTH_8, 0, LONG_MSG_TIMEOUT); - HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + /*FIXME: Add error check*/ - HDSL_set_pc_ctrl(hdslHandle,dir); - - ClockP_sleep(1); - - gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0); if(gPc_buf0 == 0x41) { - gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1); if(gPc_buf1 == 0x10) { DebugP_log("\r\n PASS "); } else { - DebugP_log("\r\n FAIL: gPc_buf1 != 0x10 = %u", gPc_buf1); + DebugP_log("\r\n FAIL: PC_BUFFER1 != 0x10 (It is %u)", gPc_buf1); } } else { - DebugP_log("\r\n FAIL: gPc_buf0 != 0x41 = %u", gPc_buf0); + DebugP_log("\r\n FAIL: PC_BUFFER0 != 0x41 (It is %u)", gPc_buf0); } } -void indirect_write_rid0_length8(HDSL_Handle hdslHandle) +void indirect_write_rid0_length8(HDSL_Handle hdslHandle) { - uint8_t dir = 0x01; - gPc_addrh = 0x9c; - gPc_addrl = 0x00; - gPc_offh = 0x80; - gPc_offl = 0x00; + DebugP_log("\r\n Parameter channel long message write : RID 0x0, Length 8"); - HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + HDSL_write_pc_long_msg(hdslHandle, 0x0, HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET, HDSL_LONG_MSG_ADDR_INDIRECT, HDSL_LONG_MSG_LENGTH_8, 0, LONG_MSG_TIMEOUT); - HDSL_set_pc_ctrl(hdslHandle,dir); + /*FIXME: Add error check*/ - ClockP_sleep(1); - - gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0); if(gPc_buf0 == 0x41) { - gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1); if(gPc_buf1 == 0x10) { DebugP_log("\r\n PASS "); } else { - DebugP_log("\r\n FAIL: gPc_buf1 != 0x10 = %u", gPc_buf1); + DebugP_log("\r\n FAIL: PC_BUFFER1 != 0x10 (It is %u)", gPc_buf1); } } else { - DebugP_log("\r\n FAIL: gPc_buf0 != 0x41 = %u", gPc_buf0); + DebugP_log("\r\n FAIL: PC_BUFFER0 != 0x41 (It is %u)", gPc_buf0); } } @@ -1305,6 +1315,34 @@ static void hdsl_i2c_io_expander(void *args) } #endif +uint32_t read_encoder_resolution(HDSL_Handle hdslHandle) +{ + int32_t status = SystemP_FAILURE; + uint32_t resolution = 0; + + /* Set the parameter channel buffers to 0xff */ + HDSL_write_pc_buffer(hdslHandle, 0, 0xff); + HDSL_write_pc_buffer(hdslHandle, 1, 0xff); + HDSL_write_pc_buffer(hdslHandle, 2, 0xff); + HDSL_write_pc_buffer(hdslHandle, 3, 0xff); + + /* Parameter channel long message read with RID 0x81, Offset 5, Length 4 + * for reading resolution */ + + status = HDSL_read_pc_long_msg(hdslHandle, 0x81, HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET, HDSL_LONG_MSG_ADDR_INDIRECT, HDSL_LONG_MSG_LENGTH_4, 0, LONG_MSG_TIMEOUT); + + DebugP_assert(SystemP_SUCCESS == status); + + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle, 0); + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle, 1); + gPc_buf2 = HDSL_read_pc_buffer(hdslHandle, 2); + gPc_buf3 = HDSL_read_pc_buffer(hdslHandle, 3); + + resolution = log2((gPc_buf0 << 24) | (gPc_buf1 << 16) | (gPc_buf2 << 8) | (gPc_buf3)); + + return resolution; +} + void hdsl_diagnostic_main(void *arg) { uint32_t val, acc_bits, pos_bits; @@ -1393,23 +1431,24 @@ void hdsl_diagnostic_main(void *arg) pos_bits += acc_bits; DebugP_log("\r\n | Encoder ID: 0x%x", val); DebugP_log( "("); - DebugP_log( "Acceleration bits: %u ,", acc_bits); + DebugP_log( "Acceleration bits: %u, ", acc_bits); DebugP_log( "Position bits: %u,", pos_bits); DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position"); DebugP_log(")|"); - DebugP_log("\r\n |-------------------------------------------------------------------------------|"); - DebugP_log("\r\n Enter single turn bits: "); - if((DebugP_scanf("%d\n", &gHdslHandleCh0->res) < 0) || gHdslHandleCh0->res > pos_bits) - { - DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n"); - gHdslHandleCh0->res = pos_bits; - } + gHdslHandleCh0->res = read_encoder_resolution(gHdslHandleCh0); gHdslHandleCh0->multi_turn = pos_bits - gHdslHandleCh0->res; gHdslHandleCh0->mask = pow(2, gHdslHandleCh0->res) - 1; - if (gHdslHandleCh0->multi_turn) + if(gHdslHandleCh0->multi_turn) { - DebugP_log( "\r\n Multi turn bits: %u\n", gHdslHandleCh0->multi_turn); + DebugP_log( "\r\n | Single-turn bits: %u, Multi-turn bits: %u |", pos_bits - gHdslHandleCh0->multi_turn, gHdslHandleCh0->multi_turn); } + else + { + DebugP_log( "\r\n | Single-turn bits: %u |", pos_bits); + } + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); + + #endif #if (CONFIG_HDSL0_CHANNEL1==1) @@ -1444,24 +1483,22 @@ void hdsl_diagnostic_main(void *arg) pos_bits += acc_bits; DebugP_log("\r\n | Encoder ID: 0x%x", val); DebugP_log( "("); - DebugP_log( "Acceleration bits: %u ,", acc_bits); + DebugP_log( "Acceleration bits: %u, ", acc_bits); DebugP_log( "Position bits: %u,", pos_bits); DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position"); DebugP_log(")|"); - DebugP_log("\r\n |-------------------------------------------------------------------------------|"); - - DebugP_log("\r\n Enter single turn bits: "); - if((DebugP_scanf("%d\n", &gHdslHandleCh1->res) < 0) || gHdslHandleCh1->res > pos_bits) - { - DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n"); - gHdslHandleCh1->res = pos_bits; - } + gHdslHandleCh1->res = read_encoder_resolution(gHdslHandleCh1); gHdslHandleCh1->multi_turn = pos_bits - gHdslHandleCh1->res; gHdslHandleCh1->mask = pow(2, gHdslHandleCh1->res) - 1; - if (gHdslHandleCh1->multi_turn) + if(gHdslHandleCh0->multi_turn) { - DebugP_log( "\r\n Multi turn bits: %u\n", gHdslHandleCh1->multi_turn); + DebugP_log( "\r\n | Single-turn bits: %u, Multi-turn bits: %u |", pos_bits - gHdslHandleCh1->multi_turn, gHdslHandleCh1->multi_turn); } + else + { + DebugP_log( "\r\n | Single-turn bits: %u |", pos_bits); + } + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); #endif while(1) diff --git a/source/position_sense/hdsl/driver/hdsl_drv.c b/source/position_sense/hdsl/driver/hdsl_drv.c index dbde6a1..95dbf63 100644 --- a/source/position_sense/hdsl/driver/hdsl_drv.c +++ b/source/position_sense/hdsl/driver/hdsl_drv.c @@ -34,6 +34,27 @@ #include #include +#define ONLINE_STATUS_1_L_FRES (1<<0) +#define ONLINE_STATUS_D_L_FREL (1) + +#define PC_ADD_H_LONG_MSG_ENABLE (1<<7) +#define PC_ADD_H_LONG_MSG_WRITE (0<<6) +#define PC_ADD_H_LONG_MSG_READ (1<<6) +#define PC_ADD_H_LONG_MSG_ERROR (1<<5) +#define PC_ADD_H_OFFSET_EN_SHIFT (5) +#define PC_ADD_H_ADDR_TYPE_SHIFT (4) +#define PC_ADD_H_LENGTH_SHIFT (2) +#define PC_ADD_H_ADDR_HIGH_MASK (0x0300) + +#define PC_ADD_L_ADDR_LOW_MASK (0x00FF) + +#define PC_OFF_H_LONG_MSG_ENABLE (1<<7) +#define PC_OFF_H_OFFSET_HIGH_MASK (0x7F00) + +#define PC_OFF_L_OFFSET_LOW_MASK (0x00FF) + +#define PC_CTRL_ENABLE (0x01) + /* Should move the below to sysconfig generated code */ HDSL_Config hdslConfig0; HDSL_Config hdslConfig1; @@ -309,52 +330,228 @@ int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *dat return SystemP_SUCCESS; } +int32_t HDSL_write_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout) +{ + uint64_t end; + end = ClockP_getTimeUsec() + timeout; + + while(!(hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1< end) + { + return SystemP_TIMEOUT; + } + } + + /* + Setting PC_ADD_L + Bits 7:0 contain bits 7:0 of 10 bit address for long message + */ + hdslHandle->hdslInterface->PC_ADD_L = (addr & PC_ADD_L_ADDR_LOW_MASK); + + /* + Setting PC_ADD_H + Bit 7 should always be set for long message + Bit 6 is unset for write operation + Bit 5 is to enable/disable offset + Bit 4 is to select direct/indirect addressing + Bits 3:2 define the length of the message + Bits 1:0 contain bits 9:8 of 10 bit address for long message + */ + hdslHandle->hdslInterface->PC_ADD_H = (PC_ADD_H_LONG_MSG_ENABLE) | + (PC_ADD_H_LONG_MSG_WRITE) | + (offsetEnable << PC_ADD_H_OFFSET_EN_SHIFT) | + (addrType << PC_ADD_H_ADDR_TYPE_SHIFT) | + (length << PC_ADD_H_LENGTH_SHIFT) | + ((addr & PC_ADD_H_ADDR_HIGH_MASK) >> 8); + + /* + Setting PC_OFF_L + Bits 7:0 contain bits 7:0 of 15 bit offset value + */ + hdslHandle->hdslInterface->PC_OFF_L = (offset & PC_OFF_L_OFFSET_LOW_MASK); + + /* + Setting PC_OFF_H + Bit 7 should always be set for long message + Bits 6:0 contain bits 14:8 of 15 bit offset value + */ + hdslHandle->hdslInterface->PC_OFF_H = (PC_OFF_H_LONG_MSG_ENABLE) | + ((offset & PC_OFF_H_OFFSET_HIGH_MASK) >> 8); + + /* Setting PC_CTRL */ + hdslHandle->hdslInterface->PC_CTRL = PC_CTRL_ENABLE; + + while((hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1< end) + { + return SystemP_TIMEOUT; + } + } + + while(!(hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1< end) + { + return SystemP_TIMEOUT; + } + } + + /* Checking for error */ + if(hdslHandle->hdslInterface->PC_ADD_H & PC_ADD_H_LONG_MSG_ERROR) + { + return SystemP_FAILURE; + } + + return SystemP_SUCCESS; +} + +int32_t HDSL_read_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout) +{ + uint64_t end; + end = ClockP_getTimeUsec() + timeout; + + while(!(hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1< end) + { + return SystemP_TIMEOUT; + } + } + + /* + Setting PC_ADD_L + Bits 7:0 contain bits 7:0 of 10 bit address for long message + */ + hdslHandle->hdslInterface->PC_ADD_L = (addr & PC_ADD_L_ADDR_LOW_MASK); + + /* + Setting PC_ADD_H + Bit 7 should always be set for long message + Bit 6 is set for read operation + Bit 5 is to enable/disable offset + Bit 4 is to select direct/indirect addressing + Bits 3:2 define the length of the message + Bits 1:0 contain bits 9:8 of 10 bit address for long message + */ + hdslHandle->hdslInterface->PC_ADD_H = (PC_ADD_H_LONG_MSG_ENABLE) | + (PC_ADD_H_LONG_MSG_READ) | + (offsetEnable << PC_ADD_H_OFFSET_EN_SHIFT) | + (addrType << PC_ADD_H_ADDR_TYPE_SHIFT) | + (length << PC_ADD_H_LENGTH_SHIFT) | + ((addr & PC_ADD_H_ADDR_HIGH_MASK) >> 8); + + /* + Setting PC_OFF_L + Bits 7:0 contain bits 7:0 of 15 bit offset value + */ + hdslHandle->hdslInterface->PC_OFF_L = (offset & PC_OFF_L_OFFSET_LOW_MASK); + + /* + Setting PC_OFF_H + Bit 7 should always be set for long message + Bits 6:0 contain bits 14:8 of 15 bit offset value + */ + hdslHandle->hdslInterface->PC_OFF_H = (PC_OFF_H_LONG_MSG_ENABLE) | + ((offset & PC_OFF_H_OFFSET_HIGH_MASK) >> 8); + + /* Setting PC_CTRL */ + hdslHandle->hdslInterface->PC_CTRL = PC_CTRL_ENABLE; + + while((hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1< end) + { + return SystemP_TIMEOUT; + } + } + + while(!(hdslHandle->hdslInterface->ONLINE_STATUS_D_L & (1< end) + { + return SystemP_TIMEOUT; + } + } + + /* Checking for error */ + + if(hdslHandle->hdslInterface->PC_ADD_H & PC_ADD_H_LONG_MSG_ERROR) + { + return SystemP_FAILURE; + } + + return SystemP_SUCCESS; +} + +void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off, uint8_t data) +{ + switch(buff_off) + { + case 0: + hdslHandle->hdslInterface->PC_BUFFER0 = data; + break; + case 1: + hdslHandle->hdslInterface->PC_BUFFER1 = data; + break; + case 2: + hdslHandle->hdslInterface->PC_BUFFER2 = data; + break; + case 3: + hdslHandle->hdslInterface->PC_BUFFER3 = data; + break; + case 4: + hdslHandle->hdslInterface->PC_BUFFER4 = data; + break; + case 5: + hdslHandle->hdslInterface->PC_BUFFER5 = data; + break; + case 6: + hdslHandle->hdslInterface->PC_BUFFER6 = data; + break; + case 7: + hdslHandle->hdslInterface->PC_BUFFER7 = data; + break; + default: + break; + } +} + uint8_t HDSL_read_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off) { switch(buff_off) { - case 0: - return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER0); - break; - case 1: - return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER1); - break; - case 2: - return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER2); - break; - case 3: - return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER3); - break; - case 4: - return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER4); - break; - case 5: - return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER5); - break; - case 6: - return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER6); - break; - case 7: - return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER7); - break; - default: - return 0; - break; + case 0: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER0); + break; + case 1: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER1); + break; + case 2: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER2); + break; + case 3: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER3); + break; + case 4: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER4); + break; + case 5: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER5); + break; + case 6: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER6); + break; + case 7: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER7); + break; + default: + return 0; + break; } } -void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t pc_buf0, uint8_t pc_buf1, uint8_t pc_buf2, uint8_t pc_buf3, uint8_t pc_buf4, uint8_t pc_buf5, uint8_t pc_buf6, uint8_t pc_buf7) -{ - hdslHandle->hdslInterface->PC_BUFFER0 = pc_buf0; - hdslHandle->hdslInterface->PC_BUFFER1 = pc_buf1; - hdslHandle->hdslInterface->PC_BUFFER2 = pc_buf2; - hdslHandle->hdslInterface->PC_BUFFER3 = pc_buf3; - hdslHandle->hdslInterface->PC_BUFFER4 = pc_buf4; - hdslHandle->hdslInterface->PC_BUFFER5 = pc_buf5; - hdslHandle->hdslInterface->PC_BUFFER6 = pc_buf6; - hdslHandle->hdslInterface->PC_BUFFER7 = pc_buf7; -} - uint8_t HDSL_get_sync_ctrl(HDSL_Handle hdslHandle) { return (uint8_t) (hdslHandle->hdslInterface->SYNC_CTRL); diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h index f91bfc7..90a931d 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h @@ -1,5 +1,59 @@ +/* + * + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + const uint32_t Hiperface_DSL2_0_RTU_0[] = { -0x21077c00, +0x21077f00, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -62,7 +116,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x23032cd1, 0x1d03c4c4, 0x2302cbd1, -0x23059a9d, +0x23059c9d, 0x05014545, 0x51074514, 0x49004502, @@ -809,7 +863,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x21062c00, +0x21062f00, 0x20d10000, 0x117f6666, 0xc9066604, @@ -977,7 +1031,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x23060cd1, +0x23060fd1, 0x10535300, 0x10333320, 0x10131340, @@ -1183,7 +1237,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x23076ed1, +0x230771d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1196,7 +1250,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x23076ed1, +0x230771d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1239,7 +1293,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x23076ed1, +0x230771d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1294,7 +1348,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xc9027a02, 0x01081b1b, 0x2102b700, -0xc901c460, +0xc901c462, 0x24001031, 0x91001800, 0xc9060007, @@ -1303,7 +1357,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x79000057, +0x79000059, 0x91351800, 0xc9060007, 0x1d060000, @@ -1311,7 +1365,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x7900004f, +0x79000051, 0xc909c41c, 0x05041b1b, 0x490c1b06, @@ -1319,7 +1373,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x110f3131, 0x69001b02, 0x1d09c4c4, -0x79000047, +0x79000049, 0xc9077a08, 0x905a1831, 0xc9021b03, @@ -1339,7 +1393,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x14809a9a, 0x69101b02, 0x15ff1a1a, -0x79000033, +0x79000035, 0x91401800, 0x513f0013, 0x91531840, @@ -1359,9 +1413,9 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x2400201b, 0x2400403b, 0x1f09c4c4, -0x7900001f, +0x79000021, 0x912c1800, -0xc900001d, +0xc900001f, 0x1d000000, 0x812c1800, 0x1f09c4c4, @@ -1369,9 +1423,11 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x1d010000, 0x81511800, 0x91283881, +0x1f070101, 0x1001017a, 0x2400101b, -0xc9050102, +0xc9050103, +0x1f074141, 0x01101b1b, 0x0b031b00, 0x8fc4d801, @@ -1480,7 +1536,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x2305f3d1, +0x2305f6d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1504,7 +1560,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x2305f3d1, +0x2305f6d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1519,6 +1575,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81107880, 0x24000200, 0x814e1800, +0x812e1843, 0x2400209f, 0x2400259f, 0x209d0000, @@ -1593,7 +1650,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000600, +0x24000700, 0x810b1800, 0x81441800, 0x2eff8383, @@ -1918,5 +1975,5 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x21062c00}; +0x21062f00}; diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h index 2fba981..826740a 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h @@ -1,6 +1,4 @@ /* - * hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h - * * * Copyright (c) 2021-2023, Texas Instruments Incorporated * All rights reserved not granted herein. @@ -53,8 +51,9 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ + const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { -0x2107cd00, +0x2107c100, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -105,19 +104,19 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x5101450a, 0x2400040d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000009, 0x69014508, 0x2400060d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000004, 0x2400010d, 0x000d6666, -0x23035ad1, +0x23034bd1, 0x1d03c4c4, 0x2302ddd1, -0x2306209d, +0x23060e9d, 0x05014545, 0x51074514, 0x49004502, @@ -146,7 +145,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400001e, 0x7f0000c5, 0x24002005, -0x230368d1, +0x230359d1, 0x24000080, 0x2405a4eb, 0x2eff8992, @@ -159,7 +158,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x10000020, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f6, 0x24001d05, 0xc918ff00, @@ -171,7 +170,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x10000020, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0105f6, 0xc918ff00, 0x101f1f00, @@ -272,7 +271,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f7, 0x240120eb, 0xf0cd0b0d, @@ -291,7 +290,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -314,7 +313,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230382d1, +0x230373d1, 0x110fcdc0, 0x240168eb, 0xf0c00b00, @@ -339,7 +338,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f7, 0x240120eb, 0xf0cd0b0d, @@ -358,7 +357,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -381,7 +380,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230382d1, +0x230373d1, 0x110fcdc0, 0x240168eb, 0xf0c00b00, @@ -398,7 +397,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x20d10000, 0x24000605, 0x2eff8283, -0x230368d1, +0x230359d1, 0x240000c0, 0x2400002d, 0x2300d0d1, @@ -452,32 +451,32 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1f04c4c4, 0x2400060d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000006, 0xc9005005, 0x51fd0304, 0x2400020d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0xc9017005, 0x2400010d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000005, 0xc9015004, 0x2400020d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0xc9027004, 0x2400010d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x111870e0, 0x5100e006, 0x1f03c4c4, 0x2400020d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000008, 0xc9035002, 0x69fd2403, @@ -485,7 +484,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x51fd0404, 0x2400020d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x2400052d, 0x24000605, 0x230113d1, @@ -509,7 +508,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1f05c4c4, 0x2400080d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x14637878, 0x69014502, 0x15ff7878, @@ -575,14 +574,14 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400ff1e, -0x21042000, +0x21041100, 0x69074507, 0xc901c405, 0xd104ff00, 0xd703ffff, 0x2400ff1e, 0x2400ff1e, -0x21047400, +0x21046500, 0x51000c4a, 0x51015b04, 0x100c0c02, @@ -705,7 +704,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21059500, +0x21058300, 0xd1077905, 0xd104ff00, 0xd703ffff, @@ -757,12 +756,12 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd1047905, 0x106d6d79, 0x2400037b, -0x21038700, +0x21037800, 0x2102c400, 0x106d6d79, 0x2400027b, -0x21038700, -0x2104c000, +0x21037800, +0x2104ae00, 0xd104ff00, 0xd703ffff, 0xd1074d03, @@ -886,7 +885,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x10d1d18b, 0x2400040d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x108b8bd1, 0x810c3c80, 0x20d10000, @@ -895,28 +894,13 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x91043880, -0x1f008080, -0x81041880, -0xc900c002, -0x2400229f, -0x913d1880, -0x1f020000, -0x813d1800, -0xc9022002, -0x2400269f, -0x91505880, -0x1f008080, -0x1f00c0c0, -0x1f008181, -0x81505880, -0x2106b200, +0x2106a100, 0x20d10000, 0x117f6666, 0xc9066604, 0x24000066, 0x81031866, -0x7f0000e6, +0x7f0000f5, 0x710f6602, 0x24000f66, 0x590e6604, @@ -1073,7 +1057,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400017b, 0x2102c500, 0x2400017b, -0x2104c000, +0x2104ae00, 0xd104ff00, 0xd703ffff, 0xd1077903, @@ -1101,7 +1085,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x2104c000, +0x2104ae00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1129,7 +1113,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81521802, 0x2400060d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x7900002e, 0xd104ff00, 0xd703ffff, @@ -1137,7 +1121,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400ff1e, 0x2400010d, 0x000d6666, -0x23035ad1, +0x23034bd1, 0x69fd7309, 0x913d1880, 0x1f040000, @@ -1163,7 +1147,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x230692d1, +0x230681d1, 0x10535300, 0x10333320, 0x10131340, @@ -1175,7 +1159,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x815618c4, 0x815818d8, 0x81637894, -0x21046700, +0x21045800, 0x31010004, 0xd104ff00, 0xd703ffff, @@ -1203,15 +1187,12 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x5100c007, 0x1f058000, 0x81541800, -0x2400060d, +0x2400080d, 0x040d6666, -0x23035ad1, -0x79000017, +0x23034bd1, +0x79000014, 0x1d058000, 0x81541800, -0x2400010d, -0x000d6666, -0x23035ad1, 0x91541800, 0x69fd6204, 0x1f028000, @@ -1372,7 +1353,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x2307bfd1, +0x2307b3d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1385,7 +1366,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x2307bfd1, +0x2307b3d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1428,7 +1409,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x2307bfd1, +0x2307b3d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1669,7 +1650,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x230679d1, +0x230668d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1693,7 +1674,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x230679d1, +0x230668d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1708,6 +1689,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81107880, 0x24000200, 0x814e1800, +0x812e1843, 0x2400209f, 0x2400259f, 0x209d0000, @@ -1782,11 +1764,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000500, +0x24000700, 0x810b1800, 0x81441800, 0x2eff8383, -0x2304189d, +0x2304099d, 0x24000866, 0x2400000c, 0x2400002c, @@ -1795,17 +1777,27 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81001800, 0x2eff8000, 0x81351800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, 0x91501880, 0x24000080, -0x13108080, +0x13118080, 0x81501880, 0x91521880, 0x24000080, -0x13108080, +0x13118080, 0x81521880, 0x91541880, 0x24000080, -0x13108080, +0x13118080, 0x81541880, 0x240128e1, 0x90e13382, @@ -1963,7 +1955,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2302ddd1, 0x05012525, 0x4f00258f, -0x79000013, +0x79000009, 0xd118fe04, 0xd105ff00, 0x31080002, @@ -1971,23 +1963,13 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x91043880, -0x1f008080, -0x81041880, -0xc900c002, -0x2400229f, -0x913d1880, -0x1f020000, -0x813d1800, -0xc9022002, -0x2400269f, 0x7f00002b, 0x24000925, 0x24001b8d, 0x2301d19d, 0x23005b9d, 0x230095d1, -0x6f010ded, +0x6f010df7, 0x05012525, 0x4f0025fa, 0x24001025, @@ -1995,18 +1977,23 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2301d19d, 0x23005b9d, 0x230095d1, -0x6f010de1, +0x6f010deb, 0x05012525, 0x4f0025fa, +0x91505880, +0x1d008080, +0x1d00c0c0, +0x1d008181, +0x81505880, 0x810a1846, 0x24001d8d, 0x2301d19d, 0x2301569d, -0x6e0403da, -0x6e2423d9, +0x6e0403df, +0x6e2423de, 0x110f4300, 0x0b044320, -0x6e2000d6, +0x6e2000db, 0x10848480, 0x10434340, 0x10404001, @@ -2015,7 +2002,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x810d3801, 0x2400000d, 0x000d6666, -0x23035ad1, +0x23034bd1, 0x1f08c4c4, 0x110fe05d, 0x01085d5d, @@ -2054,5 +2041,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2106b200}; +0x2106a100}; diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h index 28b0588..d162a80 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h @@ -1,6 +1,5 @@ + /* - * hdsl_master_icssg_multichannel_ch1_bin.h - * * * Copyright (c) 2021-2023, Texas Instruments Incorporated * All rights reserved not granted herein. @@ -53,8 +52,9 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ + const uint32_t Hiperface_DSL2_0_PRU_0[] = { -0x21078a00, +0x21077e00, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -105,19 +105,19 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x5101450a, 0x2400040d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x79000009, 0x69014508, 0x2400060d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x79000004, 0x2400010d, 0x000d6666, -0x23033bd1, +0x23032cd1, 0x1d03c4c4, 0x2302cbd1, -0x2305ac9d, +0x23059a9d, 0x05014545, 0x51074514, 0x49004502, @@ -146,7 +146,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400001e, 0x7f0000c5, 0x24002005, -0x230349d1, +0x23033ad1, 0x24000080, 0x240ca4eb, 0x2eff8992, @@ -159,7 +159,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x10000020, 0x0b018001, 0x14000130, -0x230361d1, +0x230352d1, 0x6f0005f6, 0x24001d05, 0xc919ff00, @@ -171,7 +171,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x10000020, 0x0b018001, 0x14000130, -0x230361d1, +0x230352d1, 0x6f0105f6, 0xc919ff00, 0x103f3f00, @@ -272,7 +272,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230361d1, +0x230352d1, 0x6f0005f7, 0x240820eb, 0xf0cd0b0d, @@ -291,7 +291,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230361d1, +0x230352d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -314,7 +314,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230361d1, +0x230352d1, 0x110fcdc0, 0x240868eb, 0xf0c00b00, @@ -339,7 +339,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230361d1, +0x230352d1, 0x6f0005f7, 0x240820eb, 0xf0cd0b0d, @@ -358,7 +358,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230361d1, +0x230352d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -381,7 +381,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230361d1, +0x230352d1, 0x110fcdc0, 0x240868eb, 0xf0c00b00, @@ -398,7 +398,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x20d10000, 0x24000605, 0x2eff8283, -0x230349d1, +0x23033ad1, 0x240000c0, 0x2400002d, 0x2300d0d1, @@ -452,32 +452,32 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1f04c4c4, 0x2400060d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x79000006, 0xc9005005, 0x51fd0304, 0x2400020d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0xc9017005, 0x2400010d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x79000005, 0xc9015004, 0x2400020d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0xc9027004, 0x2400010d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x111870e0, 0x5100e006, 0x1f03c4c4, 0x2400020d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x79000008, 0xc9035002, 0x69fd2403, @@ -485,7 +485,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x51fd0404, 0x2400020d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x2400052d, 0x24000605, 0x230113d1, @@ -509,7 +509,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1f05c4c4, 0x2400080d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x14637878, 0x69014502, 0x15ff7878, @@ -575,14 +575,14 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400ff1e, -0x2103ac00, +0x21039d00, 0x69074507, 0xc901c405, 0xd10cff00, 0xd70bffff, 0x2400ff1e, 0x2400ff1e, -0x21040000, +0x2103f100, 0x51000c2d, 0x51015b04, 0x100c0c02, @@ -691,7 +691,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21052100, +0x21050f00, 0xd1077905, 0xd10cff00, 0xd70bffff, @@ -743,12 +743,12 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd1047905, 0x106d6d79, 0x2400037b, -0x21036600, +0x21035700, 0x2102b600, 0x106d6d79, 0x2400027b, -0x21036600, -0x21044c00, +0x21035700, +0x21043a00, 0xd10cff00, 0xd70bffff, 0xd1074d03, @@ -855,7 +855,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x10d1d18b, 0x2400040d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x108b8bd1, 0x810c3c80, 0x20d10000, @@ -864,28 +864,13 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x91043880, -0x1f008080, -0x81041880, -0xc900c002, -0x2400229f, -0x913d1880, -0x1f020000, -0x813d1800, -0xc9022002, -0x2400269f, -0x91505880, -0x1f008080, -0x1f00c0c0, -0x1f008181, -0x81505880, -0x21063e00, +0x21062d00, 0x20d10000, 0x117f6666, 0xc9066604, 0x24000066, 0x81031866, -0x7f0000e6, +0x7f0000f5, 0x710f6602, 0x24000f66, 0x590e6604, @@ -957,7 +942,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400017b, 0x2102b700, 0x2400017b, -0x21044c00, +0x21043a00, 0xd10cff00, 0xd70bffff, 0xd1077903, @@ -985,7 +970,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x21044c00, +0x21043a00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1013,7 +998,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81521802, 0x2400060d, 0x040d6666, -0x23033bd1, +0x23032cd1, 0x7900002e, 0xd10cff00, 0xd70bffff, @@ -1021,7 +1006,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400ff1e, 0x2400010d, 0x000d6666, -0x23033bd1, +0x23032cd1, 0x69fd7309, 0x913d1880, 0x1f040000, @@ -1047,7 +1032,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x23061ed1, +0x23060dd1, 0x10535300, 0x10333320, 0x10131340, @@ -1059,7 +1044,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x815618c4, 0x815818d8, 0x81637894, -0x2103f300, +0x2103e400, 0x31010004, 0xd10cff00, 0xd70bffff, @@ -1087,15 +1072,12 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x5100c007, 0x1f058000, 0x81541800, -0x2400060d, +0x2400080d, 0x040d6666, -0x23033bd1, -0x79000017, +0x23032cd1, +0x79000014, 0x1d058000, 0x81541800, -0x2400010d, -0x000d6666, -0x23033bd1, 0x91541800, 0x69fd6204, 0x1f028000, @@ -1256,7 +1238,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x23077cd1, +0x230770d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1269,7 +1251,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x23077cd1, +0x230770d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1312,7 +1294,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x23077cd1, +0x230770d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1553,7 +1535,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x230605d1, +0x2305f4d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1577,7 +1559,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x230605d1, +0x2305f4d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1592,6 +1574,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81107880, 0x24000200, 0x814e1800, +0x812e1843, 0x2400209f, 0x2400259f, 0x209d0000, @@ -1667,11 +1650,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000500, +0x24000700, 0x810b1800, 0x81441800, 0x2eff8383, -0x2303a49d, +0x2303959d, 0x24000866, 0x2400000c, 0x2400002c, @@ -1680,17 +1663,27 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81001800, 0x2eff8000, 0x81351800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, 0x91501880, 0x24000080, -0x13108080, +0x13118080, 0x81501880, 0x91521880, 0x24000080, -0x13108080, +0x13118080, 0x81521880, 0x91541880, 0x24000080, -0x13108080, +0x13118080, 0x81541880, 0x240128e1, 0x90e13382, @@ -1896,7 +1889,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x10656546, 0x05012525, 0x4f002560, -0x79000013, +0x79000009, 0xd119fe04, 0xd10dff00, 0x31080002, @@ -1904,23 +1897,13 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x91043880, -0x1f008080, -0x81041880, -0xc900c002, -0x2400229f, -0x913d1880, -0x1f020000, -0x813d1800, -0xc9022002, -0x2400269f, 0x7d0000fa, 0x24000925, 0x24001b8d, 0x2301d19d, 0x23005b9d, 0x230095d1, -0x6f010ded, +0x6f010df7, 0x05012525, 0x4f0025fa, 0x24001025, @@ -1928,18 +1911,23 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2301d19d, 0x23005b9d, 0x230095d1, -0x6f010de1, +0x6f010deb, 0x05012525, 0x4f0025fa, +0x91505880, +0x1d008080, +0x1d00c0c0, +0x1d008181, +0x81505880, 0x810a1846, 0x24001d8d, 0x2301d19d, 0x2301569d, -0x6e0403da, -0x6e2423d9, +0x6e0403df, +0x6e2423de, 0x110f4300, 0x0b044320, -0x6e2000d6, +0x6e2000db, 0x10848480, 0x10434340, 0x10404001, @@ -1948,7 +1936,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x810d3801, 0x2400000d, 0x000d6666, -0x23033bd1, +0x23032cd1, 0x1f08c4c4, 0x110fe05d, 0x01085d5d, @@ -1987,5 +1975,5 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x21063e00}; +0x21062d00}; diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h index ca95c57..590a7c6 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h @@ -1,6 +1,5 @@ + /* - * hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h - * * * Copyright (c) 2021-2023, Texas Instruments Incorporated * All rights reserved not granted herein. @@ -53,8 +52,9 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ + const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { -0x2107ce00, +0x2107c200, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -105,19 +105,19 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x5101450a, 0x2400040d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000009, 0x69014508, 0x2400060d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000004, 0x2400010d, 0x000d6666, -0x23035ad1, +0x23034bd1, 0x1d03c4c4, 0x2302ddd1, -0x2306209d, +0x23060e9d, 0x05014545, 0x51074514, 0x49004502, @@ -146,7 +146,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400001e, 0x7f0000c5, 0x24002005, -0x230368d1, +0x230359d1, 0x24000080, 0x240ca4eb, 0x2eff8992, @@ -159,7 +159,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x10000020, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f6, 0x24001d05, 0xc919ff00, @@ -171,7 +171,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x10000020, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0105f6, 0xc919ff00, 0x103f3f00, @@ -272,7 +272,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f7, 0x240820eb, 0xf0cd0b0d, @@ -291,7 +291,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -314,7 +314,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230382d1, +0x230373d1, 0x110fcdc0, 0x240868eb, 0xf0c00b00, @@ -339,7 +339,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f7, 0x240820eb, 0xf0cd0b0d, @@ -358,7 +358,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1e05cdcd, 0x0b018001, 0x14000130, -0x230382d1, +0x230373d1, 0x6f0005f7, 0x24000001, 0x1c2d5050, @@ -381,7 +381,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1f00cdcd, 0x0b018021, 0x14002130, -0x230382d1, +0x230373d1, 0x110fcdc0, 0x240868eb, 0xf0c00b00, @@ -398,7 +398,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x20d10000, 0x24000605, 0x2eff8283, -0x230368d1, +0x230359d1, 0x240000c0, 0x2400002d, 0x2300d0d1, @@ -452,32 +452,32 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1f04c4c4, 0x2400060d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000006, 0xc9005005, 0x51fd0304, 0x2400020d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0xc9017005, 0x2400010d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000005, 0xc9015004, 0x2400020d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0xc9027004, 0x2400010d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x111870e0, 0x5100e006, 0x1f03c4c4, 0x2400020d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x79000008, 0xc9035002, 0x69fd2403, @@ -485,7 +485,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x51fd0404, 0x2400020d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x2400052d, 0x24000605, 0x230113d1, @@ -509,7 +509,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1f05c4c4, 0x2400080d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x14637878, 0x69014502, 0x15ff7878, @@ -575,14 +575,14 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400ff1e, -0x21042000, +0x21041100, 0x69074507, 0xc901c405, 0xd10cff00, 0xd70bffff, 0x2400ff1e, 0x2400ff1e, -0x21047400, +0x21046500, 0x51000c4a, 0x51015b04, 0x100c0c02, @@ -705,7 +705,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21059500, +0x21058300, 0xd1077905, 0xd10cff00, 0xd70bffff, @@ -757,12 +757,12 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd1047905, 0x106d6d79, 0x2400037b, -0x21038700, +0x21037800, 0x2102c400, 0x106d6d79, 0x2400027b, -0x21038700, -0x2104c000, +0x21037800, +0x2104ae00, 0xd10cff00, 0xd70bffff, 0xd1074d03, @@ -886,7 +886,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x10d1d18b, 0x2400040d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x108b8bd1, 0x810c3c80, 0x20d10000, @@ -895,28 +895,13 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x91043880, -0x1f008080, -0x81041880, -0xc900c002, -0x2400229f, -0x913d1880, -0x1f020000, -0x813d1800, -0xc9022002, -0x2400269f, -0x91505880, -0x1f008080, -0x1f00c0c0, -0x1f008181, -0x81505880, -0x2106b200, +0x2106a100, 0x20d10000, 0x117f6666, 0xc9066604, 0x24000066, 0x81031866, -0x7f0000e6, +0x7f0000f5, 0x710f6602, 0x24000f66, 0x590e6604, @@ -1073,7 +1058,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400017b, 0x2102c500, 0x2400017b, -0x2104c000, +0x2104ae00, 0xd10cff00, 0xd70bffff, 0xd1077903, @@ -1101,7 +1086,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x2104c000, +0x2104ae00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1129,7 +1114,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81521802, 0x2400060d, 0x040d6666, -0x23035ad1, +0x23034bd1, 0x7900002e, 0xd10cff00, 0xd70bffff, @@ -1137,7 +1122,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400ff1e, 0x2400010d, 0x000d6666, -0x23035ad1, +0x23034bd1, 0x69fd7309, 0x913d1880, 0x1f040000, @@ -1163,7 +1148,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x230692d1, +0x230681d1, 0x10535300, 0x10333320, 0x10131340, @@ -1175,7 +1160,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x815618c4, 0x815818d8, 0x81637894, -0x21046700, +0x21045800, 0x31010004, 0xd10cff00, 0xd70bffff, @@ -1203,15 +1188,12 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x5100c007, 0x1f058000, 0x81541800, -0x2400060d, +0x2400080d, 0x040d6666, -0x23035ad1, -0x79000017, +0x23034bd1, +0x79000014, 0x1d058000, 0x81541800, -0x2400010d, -0x000d6666, -0x23035ad1, 0x91541800, 0x69fd6204, 0x1f028000, @@ -1372,7 +1354,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x2307c0d1, +0x2307b4d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1385,7 +1367,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x2307c0d1, +0x2307b4d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1428,7 +1410,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x2307c0d1, +0x2307b4d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1669,7 +1651,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x230679d1, +0x230668d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1693,7 +1675,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x230679d1, +0x230668d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1708,6 +1690,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81107880, 0x24000200, 0x814e1800, +0x812e1843, 0x2400209f, 0x2400259f, 0x209d0000, @@ -1783,11 +1766,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000500, +0x24000700, 0x810b1800, 0x81441800, 0x2eff8383, -0x2304189d, +0x2304099d, 0x24000866, 0x2400000c, 0x2400002c, @@ -1796,17 +1779,27 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81001800, 0x2eff8000, 0x81351800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, 0x91501880, 0x24000080, -0x13108080, +0x13118080, 0x81501880, 0x91521880, 0x24000080, -0x13108080, +0x13118080, 0x81521880, 0x91541880, 0x24000080, -0x13108080, +0x13118080, 0x81541880, 0x240128e1, 0x90e13382, @@ -1964,7 +1957,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2302ddd1, 0x05012525, 0x4f00258f, -0x79000013, +0x79000009, 0xd119fe04, 0xd10dff00, 0x31080002, @@ -1972,23 +1965,13 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x91043880, -0x1f008080, -0x81041880, -0xc900c002, -0x2400229f, -0x913d1880, -0x1f020000, -0x813d1800, -0xc9022002, -0x2400269f, 0x7f00002a, 0x24000925, 0x24001b8d, 0x2301d19d, 0x23005b9d, 0x230095d1, -0x6f010ded, +0x6f010df7, 0x05012525, 0x4f0025fa, 0x24001025, @@ -1996,18 +1979,23 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2301d19d, 0x23005b9d, 0x230095d1, -0x6f010de1, +0x6f010deb, 0x05012525, 0x4f0025fa, +0x91505880, +0x1d008080, +0x1d00c0c0, +0x1d008181, +0x81505880, 0x810a1846, 0x24001d8d, 0x2301d19d, 0x2301569d, -0x6e0403da, -0x6e2423d9, +0x6e0403df, +0x6e2423de, 0x110f4300, 0x0b044320, -0x6e2000d6, +0x6e2000db, 0x10848480, 0x10434340, 0x10404001, @@ -2016,7 +2004,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x810d3801, 0x2400000d, 0x000d6666, -0x23035ad1, +0x23034bd1, 0x1f08c4c4, 0x110fe05d, 0x01085d5d, @@ -2055,5 +2043,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2106b200}; +0x2106a100}; diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 884d1dc..1c21811 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -875,12 +875,16 @@ transport_layer_no_short_msg: clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 lbco ®_TMP1, MASTER_REGS_CONST, PC_ADD_H, 4 +; Bit 7 should be set for long message in PC_ADD_H + set REG_TMP1.b0, REG_TMP1.b0, 7 mov SHORT_MSG.addr, REG_TMP1.b0 ldi SHORT_MSG.bits_left, 16 ;using PC_OFF? qbbc transport_layer_assemble_long_msg_no_pc_off, REG_TMP1.b0, LOFF +; Bit 7 should be set for long message in PC_OFF_H + set REG_TMP1.b2, REG_TMP1.b2, 7 add SHORT_MSG.bits_left, SHORT_MSG.bits_left, 16 transport_layer_assemble_long_msg_no_pc_off: ;save ADDR(+OFF) to memory buffer diff --git a/source/position_sense/hdsl/include/hdsl_drv.h b/source/position_sense/hdsl/include/hdsl_drv.h index 18e2d9c..cdf3878 100644 --- a/source/position_sense/hdsl/include/hdsl_drv.h +++ b/source/position_sense/hdsl/include/hdsl_drv.h @@ -63,6 +63,50 @@ extern "C" { /* Macros & Typedefs */ /* ========================================================================== */ +/** + * \anchor HDSL_LongMessageAddrTypes + * \name HDSL Long Message Addressing Types + * + * + * @{ + */ +/** \brief Direct addressing of long messages */ +#define HDSL_LONG_MSG_ADDR_DIRECT (0U) +/** \brief Indirect addressing of long messages */ +#define HDSL_LONG_MSG_ADDR_INDIRECT (1U) +/** @} */ + +/** + * \anchor HDSL_LongMessageAddrOffsetModes + * \name HDSL Long Message Addressing with/without offset + * + * + * @{ + */ +/** \brief Addressing of long messages without offset */ +#define HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET (0U) +/** \brief Addressing of long messages with offset */ +#define HDSL_LONG_MSG_ADDR_WITH_OFFSET (1U) +/** @} */ + + +/** + * \anchor HDSL_LongMessageLengths + * \name HDSL Long Message Data Lengths + * + * + * @{ + */ +/** \brief No data bytes */ +#define HDSL_LONG_MSG_LENGTH_0 (0U) +/** \brief 2 data bytes */ +#define HDSL_LONG_MSG_LENGTH_2 (1U) +/** \brief 4 data bytes */ +#define HDSL_LONG_MSG_LENGTH_4 (2U) +/** \brief 8 data bytes */ +#define HDSL_LONG_MSG_LENGTH_8 (3U) +/** @} */ + #define MAX_WAIT 20000 #define HDSL_ICSSG0_INST 0U @@ -92,8 +136,6 @@ extern "C" { /* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */ #define SYNCEVT_RTR_SYNC10_EVT 0x2C -#define ONLINE_STATUS_1_L_FRES (1<<0) - enum { MENU_SAFE_POSITION, MENU_QUALITY_MONITORING, @@ -103,7 +145,7 @@ enum { MENU_RSSI, MENU_PC_SHORT_MSG_WRITE, MENU_PC_SHORT_MSG_READ, - MENU_DIRECT_READ_RID0_LENGTH8, + MENU_DIRECT_READ_RID0_LENGTH4, MENU_DIRECT_READ_RID81_LENGTH8, MENU_DIRECT_READ_RID81_LENGTH2, MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0, @@ -386,7 +428,7 @@ uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle); uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle); /** - * \brief Write Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) with gPc_data and Short message control value(SLAVE_REG_CTRL) in hdsl interface + * \brief Trigger a short message write operation using parameters channel * * \param[in] hdslHandle * \param[in] addr Address @@ -396,10 +438,10 @@ uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle); * \return SystemP_SUCCESS in case of success, SystemP_TIMEOUT in case of timeout * */ -int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t data, uint64_t timeout); +int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t data, uint64_t timeout); /** - * \brief Read Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) and write Short message control value(SLAVE_REG_CTRL) with gPc_addr in hdsl interface + * \brief Trigger a short message read operation using parameters channel * * \param[in] hdslHandle * \param[in] addr Address @@ -409,44 +451,50 @@ int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t dat * \return SystemP_SUCCESS in case of success, SystemP_TIMEOUT in case of timeout * */ -int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *data, uint64_t timeout); +int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t *data, uint64_t timeout); /** - * \brief Write PC_AAD_L ,PC_ADD_H ,PC_OFF_L,PC_OFF_H and PC_CTRL values in hdsl interface + * \brief Trigger a long message write operation using parameters channel. + * Call \ref HDSL_write_pc_buffer before this to write the data to be sent using long message. * * \param[in] hdslHandle - * \param[in] pc_addrh - * \param[in] pc_addrl - * \param[in] pc_offh - * \param[in] pc_offl + * \param[in] addr 10 bit address for long message + * \param[in] offsetEnable Addressing with offset enable/disable from \ref HDSL_LongMessageAddrOffsetModes + * \param[in] addrType Addressing Type from \ref HDSL_LongMessageAddrTypes + * \param[in] length Length from \ref HDSL_LongMessageLength + * \param[in] offset 15 bit address offset for long message (if offset is enabled in offsetEnable parameter) + * \param[in] timeout Timeout in microseconds + * + * \return SystemP_SUCCESS in case of success, SystemP_FAILURE in case of error, SystemP_TIMEOUT in case of timeout * */ -void HDSL_set_pc_addr(HDSL_Handle hdslHandle, uint8_t pc_addrh, uint8_t pc_addrl, uint8_t pc_offh, uint8_t pc_offl); +int32_t HDSL_write_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout); /** - * \brief To set the direction read/write for long message communication - * + * \brief Trigger a long message read operation using parameters channel + * If this API returns SystemP_SUCCESS, call \ref HDSL_read_pc_buffer after this to read the data received using long message. * \param[in] hdslHandle - * \param[in] value + * \param[in] addr 10 bit address for long message + * \param[in] offsetEnable Addressing with offset enable/disable from \ref HDSL_LongMessageAddrOffsetModes + * \param[in] addrType Addressing Type from \ref HDSL_LongMessageAddrTypes + * \param[in] length Length from \ref HDSL_LongMessageLength + * \param[in] offset 15 bit address offset for long message + * \param[in] timeout Timeout in microseconds + * + * \return SystemP_SUCCESS in case of success, SystemP_FAILURE in case of error, SystemP_TIMEOUT in case of timeout * */ -void HDSL_set_pc_ctrl(HDSL_Handle hdslHandle, uint8_t value); +int32_t HDSL_read_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout); /** * \brief Write Parameters channel buffer for different bytes(bytes 0-7) * * \param[in] hdslHandle - * \param[in] pc_buf0 - * \param[in] pc_buf1 - * \param[in] pc_buf2 - * \param[in] pc_buf3 - * \param[in] pc_buf4 - * \param[in] pc_buf5 - * \param[in] pc_buf6 - * \param[in] pc_buf7 + * \param[in] buff_off + * \param[in] data * */ -void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t pc_buf0, uint8_t pc_buf1, uint8_t pc_buf2, uint8_t pc_buf3, uint8_t pc_buf4, uint8_t pc_buf5, uint8_t pc_buf6, uint8_t pc_buf7); +void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off, uint8_t data); /** * \brief Returns Parameters channel buffer for different bytes(bytes 0-7) From ccda32786b63a6a68aa9c3b898df5553fb22cb67 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 31 Oct 2023 13:54:50 +0530 Subject: [PATCH 6/7] am64x/am243x: hdsl: Fix SSUM bit in EVENT_S register - Bit should be set if summary is non-zero Fixes: PINDSW-6629 Signed-off-by: Dhaval Khandla --- .../position_sense/hdsl/firmware/defines.inc | 2 +- .../hdsl_master_icssg_multichannel_ch0_bin.h | 44 ++++++------- ...ter_icssg_multichannel_ch0_sync_mode_bin.h | 62 +++++++++--------- .../hdsl_master_icssg_multichannel_ch1_bin.h | 63 ++++++++++--------- ...ter_icssg_multichannel_ch1_sync_mode_bin.h | 63 ++++++++++--------- .../hdsl/firmware/transport.asm | 24 +++---- 6 files changed, 132 insertions(+), 126 deletions(-) diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc index e336c9f..6423ab2 100644 --- a/source/position_sense/hdsl/firmware/defines.inc +++ b/source/position_sense/hdsl/firmware/defines.inc @@ -34,7 +34,7 @@ ; bit7..4 major number FIRMWARE_VERSION_MAJOR .set 0x0 ; bit3..0 minor number -FIRMWARE_VERSION_MINOR .set 0x7 +FIRMWARE_VERSION_MINOR .set 0x8 ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h index 90a931d..2c19c76 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h @@ -51,9 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - const uint32_t Hiperface_DSL2_0_RTU_0[] = { -0x21077f00, +0x21078000, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -116,7 +115,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x23032cd1, 0x1d03c4c4, 0x2302cbd1, -0x23059c9d, +0x23059d9d, 0x05014545, 0x51074514, 0x49004502, @@ -690,7 +689,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21050f00, +0x21051000, 0xd1077905, 0xd104ff00, 0xd703ffff, @@ -747,7 +746,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x106d6d79, 0x2400027b, 0x21035700, -0x21043a00, +0x21043b00, 0xd104ff00, 0xd703ffff, 0xd1074d03, @@ -863,7 +862,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x21062f00, +0x21063000, 0x20d10000, 0x117f6666, 0xc9066604, @@ -941,7 +940,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x2400017b, 0x2102b700, 0x2400017b, -0x21043a00, +0x21043b00, 0xd104ff00, 0xd703ffff, 0xd1077903, @@ -969,7 +968,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x21043a00, +0x21043b00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1031,7 +1030,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x23060fd1, +0x230610d1, 0x10535300, 0x10333320, 0x10131340, @@ -1114,24 +1113,25 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81361800, 0x91081821, 0x10210001, -0x5100010b, +0x51000106, 0x91043880, 0x1f068080, 0x81041880, 0xc8c0c002, 0x2400229f, +0x91361800, +0x91503802, +0x51000009, +0x1f060202, +0x1f060242, 0x913d1880, 0x1f060000, 0x813d1880, 0xc9062002, 0x2400269f, -0x91361800, -0x91503802, +0x79000003, 0x1d060202, 0x1d060242, -0x51000003, -0x1f060202, -0x1f060242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1237,7 +1237,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x230771d1, +0x230772d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1250,7 +1250,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x230771d1, +0x230772d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1293,7 +1293,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x230771d1, +0x230772d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1536,7 +1536,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x2305f6d1, +0x2305f7d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1560,7 +1560,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x2305f6d1, +0x2305f7d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1650,7 +1650,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000700, +0x24000800, 0x810b1800, 0x81441800, 0x2eff8383, @@ -1975,5 +1975,5 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x21062f00}; +0x21063000}; diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h index 826740a..431e917 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h @@ -51,9 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { -0x2107c100, +0x2107c400, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -116,7 +115,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x23034bd1, 0x1d03c4c4, 0x2302ddd1, -0x23060e9d, +0x2306119d, 0x05014545, 0x51074514, 0x49004502, @@ -704,7 +703,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21058300, +0x21058400, 0xd1077905, 0xd104ff00, 0xd703ffff, @@ -761,7 +760,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x106d6d79, 0x2400027b, 0x21037800, -0x2104ae00, +0x2104af00, 0xd104ff00, 0xd703ffff, 0xd1074d03, @@ -894,7 +893,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x2106a100, +0x2106a400, 0x20d10000, 0x117f6666, 0xc9066604, @@ -1057,7 +1056,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400017b, 0x2102c500, 0x2400017b, -0x2104ae00, +0x2104af00, 0xd104ff00, 0xd703ffff, 0xd1077903, @@ -1085,7 +1084,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x2104ae00, +0x2104af00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1147,7 +1146,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x230681d1, +0x230684d1, 0x10535300, 0x10333320, 0x10131340, @@ -1230,24 +1229,25 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81361800, 0x91081821, 0x10210001, -0x5100010b, +0x51000106, 0x91043880, 0x1f068080, 0x81041880, 0xc8c0c002, 0x2400229f, +0x91361800, +0x91503802, +0x51000009, +0x1f060202, +0x1f060242, 0x913d1880, 0x1f060000, 0x813d1880, 0xc9062002, 0x2400269f, -0x91361800, -0x91503802, +0x79000003, 0x1d060202, 0x1d060242, -0x51000003, -0x1f060202, -0x1f060242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1353,7 +1353,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x2307b3d1, +0x2307b6d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1366,7 +1366,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x2307b3d1, +0x2307b6d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1409,7 +1409,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x2307b3d1, +0x2307b6d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1464,7 +1464,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xc9027a02, 0x01081b1b, 0x2102c500, -0xc901c460, +0xc901c462, 0x24001031, 0x91001800, 0xc9060007, @@ -1473,7 +1473,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x79000057, +0x79000059, 0x91351800, 0xc9060007, 0x1d060000, @@ -1481,7 +1481,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x7900004f, +0x79000051, 0xc909c41c, 0x05041b1b, 0x490c1b06, @@ -1489,7 +1489,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x110f3131, 0x69001b02, 0x1d09c4c4, -0x79000047, +0x79000049, 0xc9077a08, 0x905a1831, 0xc9021b03, @@ -1509,7 +1509,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x14809a9a, 0x69101b02, 0x15ff1a1a, -0x79000033, +0x79000035, 0x91401800, 0x513f0013, 0x91531840, @@ -1529,9 +1529,9 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400201b, 0x2400403b, 0x1f09c4c4, -0x7900001f, +0x79000021, 0x912c1800, -0xc900001d, +0xc900001f, 0x1d000000, 0x812c1800, 0x1f09c4c4, @@ -1539,9 +1539,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1d010000, 0x81511800, 0x91283881, +0x1f070101, 0x1001017a, 0x2400101b, -0xc9050102, +0xc9050103, +0x1f074141, 0x01101b1b, 0x0b031b00, 0x8fc4d801, @@ -1650,7 +1652,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x230668d1, +0x23066bd1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1674,7 +1676,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x230668d1, +0x23066bd1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1764,7 +1766,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000700, +0x24000800, 0x810b1800, 0x81441800, 0x2eff8383, @@ -2041,5 +2043,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2106a100}; +0x2106a400}; diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h index d162a80..e031ecb 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h @@ -1,4 +1,3 @@ - /* * * Copyright (c) 2021-2023, Texas Instruments Incorporated @@ -52,9 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - const uint32_t Hiperface_DSL2_0_PRU_0[] = { -0x21077e00, +0x21078100, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -117,7 +115,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x23032cd1, 0x1d03c4c4, 0x2302cbd1, -0x23059a9d, +0x23059d9d, 0x05014545, 0x51074514, 0x49004502, @@ -691,7 +689,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21050f00, +0x21051000, 0xd1077905, 0xd10cff00, 0xd70bffff, @@ -748,7 +746,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x106d6d79, 0x2400027b, 0x21035700, -0x21043a00, +0x21043b00, 0xd10cff00, 0xd70bffff, 0xd1074d03, @@ -864,7 +862,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x21062d00, +0x21063000, 0x20d10000, 0x117f6666, 0xc9066604, @@ -942,7 +940,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400017b, 0x2102b700, 0x2400017b, -0x21043a00, +0x21043b00, 0xd10cff00, 0xd70bffff, 0xd1077903, @@ -970,7 +968,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x21043a00, +0x21043b00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1032,7 +1030,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x23060dd1, +0x230610d1, 0x10535300, 0x10333320, 0x10131340, @@ -1115,24 +1113,25 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81361800, 0x91081821, 0x10210001, -0x5100010b, +0x51000106, 0x91043880, 0x1f068080, 0x81041880, 0xc8c0c002, 0x2400229f, +0x91361800, +0x91503802, +0x51000009, +0x1f060202, +0x1f060242, 0x913d1880, 0x1f060000, 0x813d1880, 0xc9062002, 0x2400269f, -0x91361800, -0x91503802, +0x79000003, 0x1d060202, 0x1d060242, -0x51000003, -0x1f060202, -0x1f060242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1238,7 +1237,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x230770d1, +0x230773d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1251,7 +1250,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x230770d1, +0x230773d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1294,7 +1293,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x230770d1, +0x230773d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1349,7 +1348,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xc9027a02, 0x01081b1b, 0x2102b700, -0xc901c460, +0xc901c462, 0x24001031, 0x91001800, 0xc9060007, @@ -1358,7 +1357,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x79000057, +0x79000059, 0x91351800, 0xc9060007, 0x1d060000, @@ -1366,7 +1365,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x7900004f, +0x79000051, 0xc909c41c, 0x05041b1b, 0x490c1b06, @@ -1374,7 +1373,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x110f3131, 0x69001b02, 0x1d09c4c4, -0x79000047, +0x79000049, 0xc9077a08, 0x905a1831, 0xc9021b03, @@ -1394,7 +1393,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x14809a9a, 0x69101b02, 0x15ff1a1a, -0x79000033, +0x79000035, 0x91401800, 0x513f0013, 0x91531840, @@ -1414,9 +1413,9 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400201b, 0x2400403b, 0x1f09c4c4, -0x7900001f, +0x79000021, 0x912c1800, -0xc900001d, +0xc900001f, 0x1d000000, 0x812c1800, 0x1f09c4c4, @@ -1424,9 +1423,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1d010000, 0x81511800, 0x91283881, +0x1f070101, 0x1001017a, 0x2400101b, -0xc9050102, +0xc9050103, +0x1f074141, 0x01101b1b, 0x0b031b00, 0x8fc4d801, @@ -1535,7 +1536,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x2305f4d1, +0x2305f7d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1559,7 +1560,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x2305f4d1, +0x2305f7d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1650,7 +1651,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000700, +0x24000800, 0x810b1800, 0x81441800, 0x2eff8383, @@ -1975,5 +1976,5 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x21062d00}; +0x21063000}; diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h index 590a7c6..6bf8094 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h @@ -1,4 +1,3 @@ - /* * * Copyright (c) 2021-2023, Texas Instruments Incorporated @@ -52,9 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { -0x2107c200, +0x2107c500, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -117,7 +115,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x23034bd1, 0x1d03c4c4, 0x2302ddd1, -0x23060e9d, +0x2306119d, 0x05014545, 0x51074514, 0x49004502, @@ -705,7 +703,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21058300, +0x21058400, 0xd1077905, 0xd10cff00, 0xd70bffff, @@ -762,7 +760,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x106d6d79, 0x2400027b, 0x21037800, -0x2104ae00, +0x2104af00, 0xd10cff00, 0xd70bffff, 0xd1074d03, @@ -895,7 +893,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x2106a100, +0x2106a400, 0x20d10000, 0x117f6666, 0xc9066604, @@ -1058,7 +1056,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400017b, 0x2102c500, 0x2400017b, -0x2104ae00, +0x2104af00, 0xd10cff00, 0xd70bffff, 0xd1077903, @@ -1086,7 +1084,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x2104ae00, +0x2104af00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1148,7 +1146,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x230681d1, +0x230684d1, 0x10535300, 0x10333320, 0x10131340, @@ -1231,24 +1229,25 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81361800, 0x91081821, 0x10210001, -0x5100010b, +0x51000106, 0x91043880, 0x1f068080, 0x81041880, 0xc8c0c002, 0x2400229f, +0x91361800, +0x91503802, +0x51000009, +0x1f060202, +0x1f060242, 0x913d1880, 0x1f060000, 0x813d1880, 0xc9062002, 0x2400269f, -0x91361800, -0x91503802, +0x79000003, 0x1d060202, 0x1d060242, -0x51000003, -0x1f060202, -0x1f060242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1354,7 +1353,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x2307b4d1, +0x2307b7d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1367,7 +1366,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x2307b4d1, +0x2307b7d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1410,7 +1409,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x2307b4d1, +0x2307b7d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1465,7 +1464,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xc9027a02, 0x01081b1b, 0x2102c500, -0xc901c460, +0xc901c462, 0x24001031, 0x91001800, 0xc9060007, @@ -1474,7 +1473,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x79000057, +0x79000059, 0x91351800, 0xc9060007, 0x1d060000, @@ -1482,7 +1481,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x7900004f, +0x79000051, 0xc909c41c, 0x05041b1b, 0x490c1b06, @@ -1490,7 +1489,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x110f3131, 0x69001b02, 0x1d09c4c4, -0x79000047, +0x79000049, 0xc9077a08, 0x905a1831, 0xc9021b03, @@ -1510,7 +1509,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x14809a9a, 0x69101b02, 0x15ff1a1a, -0x79000033, +0x79000035, 0x91401800, 0x513f0013, 0x91531840, @@ -1530,9 +1529,9 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400201b, 0x2400403b, 0x1f09c4c4, -0x7900001f, +0x79000021, 0x912c1800, -0xc900001d, +0xc900001f, 0x1d000000, 0x812c1800, 0x1f09c4c4, @@ -1540,9 +1539,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1d010000, 0x81511800, 0x91283881, +0x1f070101, 0x1001017a, 0x2400101b, -0xc9050102, +0xc9050103, +0x1f074141, 0x01101b1b, 0x0b031b00, 0x8fc4d801, @@ -1651,7 +1652,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x230668d1, +0x23066bd1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1675,7 +1676,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x230668d1, +0x23066bd1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1766,7 +1767,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000700, +0x24000800, 0x810b1800, 0x81441800, 0x2eff8383, @@ -2043,5 +2044,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2106a100}; +0x2106a400}; diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 1c21811..9fd7884 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -375,26 +375,28 @@ transport_skip_vpos_update: ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ update_events_no_int7: -;set event_s and generate interrupt_s +summary_no_int: + +; Update SUM and SSUM bits in ONLINE_STATUS registers + lbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM, 1 + lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 + qbeq online_status_sum_clear, REG_TMP0.b0, 0x00 + set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM + set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM +;set SSUM in EVENT_S and generate interrupt_s lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SSUM ;save events sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 qbbc update_events_no_int17, REG_TMP0.b1, EVENT_S_SSUM ; generate interrupt_s - ldi r31.w0, PRU0_ARM_IRQ4 + ldi r31.w0, PRU0_ARM_IRQ4 update_events_no_int17: -summary_no_int: - -; Update SUM and SSUM bits in ONLINE_STATUS registers - lbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM, 1 - lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 + qba online_status_sum_save +online_status_sum_clear: clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM - qbeq online_status_sum_clear, REG_TMP0.b0, 0x00 - set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM - set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM -online_status_sum_clear: +online_status_sum_save: sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 ;restore REG_FNC.w0 content From 9fa938d6aeed61f4cc6b575f675eac36404c3b22 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Wed, 1 Nov 2023 14:41:47 +0530 Subject: [PATCH 7/7] am64x/am243x: hdsl: Fix the clearing behavior of ONLINE STATUS 1 SCE bit - Fix register corruption during SUM/SSUM update in ONLINE STATUS Fixes: PINDSW-7048 Signed-off-by: Dhaval Khandla --- .../position_sense/hdsl/firmware/datalink.asm | 2 +- .../hdsl/firmware/datalink_init.asm | 2 +- .../position_sense/hdsl/firmware/defines.inc | 2 +- .../hdsl_master_icssg_multichannel_ch0_bin.h | 16 ++++++------ ...ter_icssg_multichannel_ch0_sync_mode_bin.h | 16 ++++++------ .../hdsl_master_icssg_multichannel_ch1_bin.h | 16 ++++++------ ...ter_icssg_multichannel_ch1_sync_mode_bin.h | 16 ++++++------ .../hdsl/firmware/transport.asm | 26 +++++++++---------- 8 files changed, 48 insertions(+), 48 deletions(-) diff --git a/source/position_sense/hdsl/firmware/datalink.asm b/source/position_sense/hdsl/firmware/datalink.asm index bace865..6380a16 100644 --- a/source/position_sense/hdsl/firmware/datalink.asm +++ b/source/position_sense/hdsl/firmware/datalink.asm @@ -116,7 +116,7 @@ datalink_wait_vsynch: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_FRES ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int0, REG_TMP0.b1, EVENT_S_FRES ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ4 diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm index 76f26d9..2854f7a 100644 --- a/source/position_sense/hdsl/firmware/datalink_init.asm +++ b/source/position_sense/hdsl/firmware/datalink_init.asm @@ -114,7 +114,7 @@ update_events_no_int15: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int22, REG_TMP0.b1, EVENT_S_PRST ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ4 diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc index 6423ab2..18a1c9c 100644 --- a/source/position_sense/hdsl/firmware/defines.inc +++ b/source/position_sense/hdsl/firmware/defines.inc @@ -34,7 +34,7 @@ ; bit7..4 major number FIRMWARE_VERSION_MAJOR .set 0x0 ; bit3..0 minor number -FIRMWARE_VERSION_MINOR .set 0x8 +FIRMWARE_VERSION_MINOR .set 0x9 ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h index 2c19c76..e450daf 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h @@ -1068,20 +1068,20 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd105c008, 0x915818c0, 0x5100c007, -0x1f058000, +0x1f050000, 0x81541800, 0x2400080d, 0x040d6666, 0x23032cd1, 0x79000014, -0x1d058000, +0x1d050000, 0x81541800, 0x91541800, 0x69fd6204, -0x1f028000, +0x1f020000, 0x81541800, 0x79000002, -0x1d028000, +0x1d020000, 0x15e06262, 0x2ed00381, 0xd1060204, @@ -1123,15 +1123,15 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91503802, 0x51000009, 0x1f060202, -0x1f060242, +0x1f064242, 0x913d1880, 0x1f060000, -0x813d1880, +0x813d1800, 0xc9062002, 0x2400269f, 0x79000003, 0x1d060202, -0x1d060242, +0x1d064242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1650,7 +1650,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000800, +0x24000900, 0x810b1800, 0x81441800, 0x2eff8383, diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h index 431e917..531c271 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h @@ -1184,20 +1184,20 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd105c008, 0x915818c0, 0x5100c007, -0x1f058000, +0x1f050000, 0x81541800, 0x2400080d, 0x040d6666, 0x23034bd1, 0x79000014, -0x1d058000, +0x1d050000, 0x81541800, 0x91541800, 0x69fd6204, -0x1f028000, +0x1f020000, 0x81541800, 0x79000002, -0x1d028000, +0x1d020000, 0x15e06262, 0x2ed00381, 0xd1060204, @@ -1239,15 +1239,15 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x91503802, 0x51000009, 0x1f060202, -0x1f060242, +0x1f064242, 0x913d1880, 0x1f060000, -0x813d1880, +0x813d1800, 0xc9062002, 0x2400269f, 0x79000003, 0x1d060202, -0x1d060242, +0x1d064242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1766,7 +1766,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000800, +0x24000900, 0x810b1800, 0x81441800, 0x2eff8383, diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h index e031ecb..a851b43 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h @@ -1068,20 +1068,20 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd105c008, 0x915818c0, 0x5100c007, -0x1f058000, +0x1f050000, 0x81541800, 0x2400080d, 0x040d6666, 0x23032cd1, 0x79000014, -0x1d058000, +0x1d050000, 0x81541800, 0x91541800, 0x69fd6204, -0x1f028000, +0x1f020000, 0x81541800, 0x79000002, -0x1d028000, +0x1d020000, 0x15e06262, 0x2ed00381, 0xd1060204, @@ -1123,15 +1123,15 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x91503802, 0x51000009, 0x1f060202, -0x1f060242, +0x1f064242, 0x913d1880, 0x1f060000, -0x813d1880, +0x813d1800, 0xc9062002, 0x2400269f, 0x79000003, 0x1d060202, -0x1d060242, +0x1d064242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1651,7 +1651,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000800, +0x24000900, 0x810b1800, 0x81441800, 0x2eff8383, diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h index 6bf8094..a2670b9 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h @@ -1184,20 +1184,20 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd105c008, 0x915818c0, 0x5100c007, -0x1f058000, +0x1f050000, 0x81541800, 0x2400080d, 0x040d6666, 0x23034bd1, 0x79000014, -0x1d058000, +0x1d050000, 0x81541800, 0x91541800, 0x69fd6204, -0x1f028000, +0x1f020000, 0x81541800, 0x79000002, -0x1d028000, +0x1d020000, 0x15e06262, 0x2ed00381, 0xd1060204, @@ -1239,15 +1239,15 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x91503802, 0x51000009, 0x1f060202, -0x1f060242, +0x1f064242, 0x913d1880, 0x1f060000, -0x813d1880, +0x813d1800, 0xc9062002, 0x2400269f, 0x79000003, 0x1d060202, -0x1d060242, +0x1d064242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1767,7 +1767,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000800, +0x24000900, 0x810b1800, 0x81441800, 0x2eff8383, diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 9fd7884..fbe3af0 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -119,7 +119,7 @@ transport_on_v_frame: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SCE ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int4, REG_TMP0.b1, EVENT_S_SCE ; generate interrupt_s ldi r31.w0, PRU0_ARM_IRQ4 @@ -152,7 +152,7 @@ push_1B: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_VPOS ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int5, REG_TMP0.b1, EVENT_S_VPOS ; generate interrupt_s ldi r31.w0, PRU0_ARM_IRQ4 @@ -283,14 +283,14 @@ transport_on_v_frame_2: lbco ®_TMP0.w2, MASTER_REGS_CONST, CRC_SEC_TEMP, 2 qbeq check_for_slave_error_on_secondary_channel, REG_TMP0.w2, 0 ; set SCE2 bit in ONLINE_STATUS_2 - set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 + set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SCE2 sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 QM_SUB 8 transport_on_v_frame_dont_update_qm_secondary_channel: qba transport_on_v_frame_2_exit check_for_slave_error_on_secondary_channel: ; clear SCE2 bit in ONLINE_STATUS_2 - clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 + clr REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SCE2 sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ; No QM updates for CRC check success with safe channel 2 lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 @@ -298,11 +298,11 @@ check_for_slave_error_on_secondary_channel: ; assumption: r21.b3 contains the first byte of secondary vertical channel qbne transport_on_v_frame_no_vpos2_error, REG_TMP2.b3, K29_7 ; set VPOS2 bit in ONLINE_STATUS_2 - set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 + set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_VPOS2 sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 qba transport_on_v_frame_vpos2_error_exit transport_on_v_frame_no_vpos2_error: - clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 + clr REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_VPOS2 transport_on_v_frame_vpos2_error_exit: ; store the data from secondary channel @@ -382,12 +382,12 @@ summary_no_int: lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 qbeq online_status_sum_clear, REG_TMP0.b0, 0x00 set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM - set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM + set REG_TMP2.b2, REG_TMP2.b2, ONLINE_STATUS_1_SSUM ;set SSUM in EVENT_S and generate interrupt_s lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SSUM ;save events - sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int17, REG_TMP0.b1, EVENT_S_SSUM ; generate interrupt_s ldi r31.w0, PRU0_ARM_IRQ4 @@ -395,7 +395,7 @@ update_events_no_int17: qba online_status_sum_save online_status_sum_clear: clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM - clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM + clr REG_TMP2.b2, REG_TMP2.b2, ONLINE_STATUS_1_SSUM online_status_sum_save: sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 @@ -554,7 +554,7 @@ transport_layer_received_short_msg: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.w0, REG_TMP0.w0, EVENT_S_FRES ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int100, REG_TMP0.b1, EVENT_S_FRES ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ @@ -578,7 +578,7 @@ transport_layer_short_msg_recv_read: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.w0, REG_TMP0.w0, EVENT_S_FRES ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int10, REG_TMP0.b1, EVENT_S_FRES ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ @@ -702,7 +702,7 @@ update_events_no_int19: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_MIN ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int20, REG_TMP0.b1, EVENT_S_MIN ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ4 @@ -935,7 +935,7 @@ update_events_no_int3: lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_QMLW ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int16, REG_TMP0.b1, EVENT_S_QMLW ; generate interrupt_s ldi r31.w0, PRU0_ARM_IRQ4