External/motor-control-sdk
8
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

am64x/am243x/am263x : initial commit for motor control sdk

Browse Source 
Initial commit for motor control sdk

Fixes: PINDSW-5635

Signed-off-by: Naresh A <nareshk@ti.com>
This commit is contained in:
Naresh A 2023-07-04 18:02:46 +05:30
commit 5f968b0bf2
559 changed files with 98219 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
.gitignore vendored Normal file
View File

@ -0,0 +1,67 @@
lib/
obj/
node_modules/
coverage/
docs/api_guide_*
docs/datasheet*
*.out
*.out*
*.profdata
*.map
*.zip
*.rprc
*.rprc_tmp
*.tmp
*.swp
*.rprc_xip
*.appimage
*.appimage_xip
*.appimage_qspi
*.appimage.signed
*.appimage.hs
*.appimage.hs_fs
*.bin
*.tiimage
*.tiimage.hs
*-fw
*.vscode/
temp_stdout_*.txt
ccs_projects/
generated/
source/kernel/freertos/FreeRTOS-Kernel
source/kernel/freertos/FreeRTOS-Kernel-smp
source/kernel/freertos/FreeRTOS-POSIX
source/fs/freertos_fat/FreeRTOS-FAT
source/kernel/safertos/safeRTOS
source/industrial_comms/ethercat_slave/beckhoff_stack/stack_sources/*.c
source/industrial_comms/ethercat_slave/beckhoff_stack/stack_sources/*.h
source/industrial_comms/ethercat_slave/beckhoff_stack/stack_sources/*.dll
source/industrial_comms/ethercat_slave/beckhoff_stack/stack_sources/*.lib
source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/*.c
source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/*.h
source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/*.dll
source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/*.lib
source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/src/*.c
source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/src/*.h
source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/src/*.dll
source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/src/*.lib
source/networking/enet/core
source/networking/lwip/lwip-stack
source/networking/lwip/lwip-contrib
source/cmsis
source/commercial
source/usb/tinyusb/tinyusb-stack
source/dsplib_c66x_3_4_0_0/
docs/industrial_protocol_docs
mcusdk_tagfile
__pycache__/
source/motor_control/position_sense/hdsl/firmware/*.lst
source/motor_control/position_sense/hdsl/firmware/*.obj
source/motor_control/position_sense/hdsl/firmware/*.b00
source/motor_control/position_sense/hdsl/firmware/*.xml
source/networking/mbedtls_library/mbedtls
source/motor_control/position_sense/endat/firmware/*.lst
source/motor_control/position_sense/endat/firmware/*.obj
source/motor_control/position_sense/endat/firmware/*.b00
source/motor_control/position_sense/endat/firmware/*.xml
!*boardcfg_*.bin

413
.metadata/.tirex/am243x.content.tirex.json Normal file
View File

@ -0,0 +1,413 @@
[
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Endat Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "endat_diagnostic_single_channel",
"location": "../../examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"endat_diagnostic",
"single_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Endat Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "endat_diagnostic_single_channel",
"location": "../../examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_LAUNCHPAD"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"endat_diagnostic",
"single_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Endat Diagnostic Multi Channel Load Share Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "endat_diagnostic_multi_channel_load_share",
"location": "../../examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"endat_diagnostic",
"multi_channel_load_share",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Endat Diagnostic Multi Channel Single Pru Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "endat_diagnostic_multi_channel_single_pru",
"location": "../../examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"endat_diagnostic",
"multi_channel_single_pru",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Multi Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_multi_channel",
"location": "../../examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"hdsl_diagnostic",
"multi_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_single_channel",
"location": "../../examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"hdsl_diagnostic",
"single_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_single_channel",
"location": "../../examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_LAUNCHPAD"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"hdsl_diagnostic",
"single_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Ddr Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_ddr",
"location": "../../examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"hdsl_diagnostic_with_traces",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Tamagawa Diagnostic Multi Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "tamagawa_diagnostic_multi_channel",
"location": "../../examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"tamagawa_diagnostic",
"multi_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Tamagawa Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "tamagawa_diagnostic_single_channel",
"location": "../../examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"tamagawa_diagnostic",
"single_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Tamagawa Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "tamagawa_diagnostic_single_channel",
"location": "../../examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_LAUNCHPAD"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"tamagawa_diagnostic",
"single_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Icss Sdfm Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "icss_sdfm",
"location": "../../examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"icss_sdfm",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "web.page",
"resourceClass": [
"document"
],
"name": "User Guide",
"location": "../../docs/api_guide_am243x/index.html",
"devtools": [
"AM243x_GP_EVM",
"AM243x_LAUNCHPAD"
],
"mainCategories": [
[
"Documents"
]
]
}
]

50
.metadata/.tirex/am263x.content.tirex.json Normal file
View File

@ -0,0 +1,50 @@
[
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "An Example of tamagawa single channel with soc uart CPU is R5FSS0-0 running FREERTOS.",
"name": "tamagawa_diagnostic_soc_uart",
"location": "../../examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"LP-AM263"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"tamagawa_diagnostic_over_soc_uart",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "web.page",
"resourceClass": [
"document"
],
"name": "User Guide",
"location": "../../docs/api_guide_am263x/index.html",
"devtools": [
"LP-AM263"
],
"mainCategories": [
[
"Documents"
]
]
}
]

313
.metadata/.tirex/am64x.content.tirex.json Normal file
View File

@ -0,0 +1,313 @@
[
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Endat Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "endat_diagnostic_single_channel",
"location": "../../examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"endat_diagnostic",
"single_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Endat Diagnostic Multi Channel Load Share Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "endat_diagnostic_multi_channel_load_share",
"location": "../../examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"endat_diagnostic",
"multi_channel_load_share",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Endat Diagnostic Multi Channel Single Pru Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "endat_diagnostic_multi_channel_single_pru",
"location": "../../examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"endat_diagnostic",
"multi_channel_single_pru",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Multi Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_multi_channel",
"location": "../../examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"hdsl_diagnostic",
"multi_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_single_channel",
"location": "../../examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"hdsl_diagnostic",
"single_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Ddr Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_ddr",
"location": "../../examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"hdsl_diagnostic_with_traces",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Tamagawa Diagnostic Multi Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "tamagawa_diagnostic_multi_channel",
"location": "../../examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"tamagawa_diagnostic",
"multi_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Tamagawa Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "tamagawa_diagnostic_single_channel",
"location": "../../examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"tamagawa_diagnostic",
"single_channel",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Icss Sdfm Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "icss_sdfm",
"location": "../../examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"motor_control",
"icss_sdfm",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "web.page",
"resourceClass": [
"document"
],
"name": "User Guide",
"location": "../../docs/api_guide_am64x/index.html",
"devtools": [
"AM64x_GP_EVM"
],
"mainCategories": [
[
"Documents"
]
]
}
]

BIN
.metadata/.tirex/motor_control_sdk.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 8.4 KiB

18
.metadata/.tirex/package.ccs.json Normal file
View File

@ -0,0 +1,18 @@
[
{
"rootMacroName": "COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR",
"compilerIncludePath": [ ],
"compilerSymbols": [ ],
"linkerSearchPath": [ ],
"properties": {
"rtsc.repositories": [
"source",
"."
]
},
"helpTocs": [
],
"docs": [
]
}
]

20
.metadata/.tirex/package.tirex.json Normal file
View File

@ -0,0 +1,20 @@
[
{
"metadataVersion": "3.01.00",
"id": "com.ti.MOTOR_CONTROL_SDK_AMXXX",
"name": "MOTOR CONTROL SDK for AMXXX",
"rootCategory": [ "MOTOR CONTROL SDK", "MOTOR CONTROL SDK for AMXXX" ],
"version": "09.00.00.01",
"type": "software",
"image": "./mcu_plus_sdk.png",
"license": "../../license.txt",
"devices": ["AMXXX"],
"tags": ["SDK", "Baremetal", "FreeRTOS"],
"description": "Welcome to MOTOR CONTROL SDK for AMXXX. This SDK contains examples, libraries and tools to develop RTOS and no-RTOS based applications for ARM R5F, ARM M4F CPUs and related peripherals.",
"dependencies": [
{ "packageId": "sysconfig", "version": "1.14.0", "require": "mandatory" },
{ "packageId": "ti_cgt_tiarmclang", "version": "2.1.2", "require": "mandatory" },
{ "packageId": "arm.gnu.aarch64-none", "version": "9.2.1", "require": "mandatory" }
]
}
]

75
.metadata/product.json Normal file
View File

@ -0,0 +1,75 @@
{
"name": "MOTOR_CONTROL_SDK",
"displayName": "MOTOR CONTROL SDK",
"version": "09.00.00",
"documentationPath": "../docs",
"includePaths": [
"../source",
],
"components": [
"/motor_control/motor_control",
],
"devices": [
"AM64x_beta",
"AM243x_ALV_beta",
"AM243x_ALX_beta",
"AM273x",
"AWR294X",
"AM263x_beta",
"AM62x",
],
"contexts": {
"AM64x_beta": [
"r5fss0-0",
"r5fss0-1",
"r5fss1-0",
"r5fss1-1",
"m4fss0-0",
"a53ss0-0",
],
"AM243x_ALV_beta": [
"r5fss0-0",
"r5fss0-1",
"r5fss1-0",
"r5fss1-1",
"m4fss0-0",
],
"AM243x_ALX_beta": [
"r5fss0-0",
"r5fss0-1",
"r5fss1-0",
"r5fss1-1",
"m4fss0-0",
],
"AM273x": [
"r5fss0-0",
"r5fss0-1",
"c66ss0",
"hsm0-0",
],
"AWR294X": [
"r5fss0-0",
"r5fss0-1",
"c66ss0",
"hsm0-0",
],
"AM263x_beta": [
"r5fss0-0",
"r5fss0-1",
"r5fss1-0",
"r5fss1-1",
"hsm0-0",
],
"AM62x": [
"m4fss0-0",
],
},
"pinmuxUIOptions": {
"group": "merged",
"hidePeripheralTab": false,
"showPinTable": true,
"showSignals": true,
"showUsed": true
},
"minToolVersion" : "1.14.0"
}

88
.project/cgt/cgt_gcc-aarch64.js Normal file
View File

@ -0,0 +1,88 @@
const common = require(`../common.js`);
const cgt_a53 ={
cflags: {
common: [
"-mcpu=cortex-a53+fp+simd",
"-mabi=lp64",
"-mcmodel=large",
"-mstrict-align",
"-mfix-cortex-a53-835769",
"-mfix-cortex-a53-843419",
],
},
}
const cgt_common = {
path: "CGT_GCC_AARCH64_PATH",
cc: "aarch64-none-elf-gcc",
ar: "aarch64-none-elf-gcc-ar",
lnk: "aarch64-none-elf-gcc",
strip: "aarch64-none-elf-strip",
objcopy: "aarch64-none-elf-objcopy",
cov: "aarch64-none-elf-gcov",
includes: {
common: [
"${MCU_PLUS_SDK_PATH}/source",
"${MOTOR_CONTROL_SDK_PATH}/source",
],
},
cflags: {
common: [
"-Wall",
"-Werror",
"-g",
"-Wno-int-to-pointer-cast",
"-Wno-pointer-to-int-cast",
"-Wno-unused-but-set-variable",
"-fdata-sections",
"-ffunction-sections"
],
debug: [
"-D_DEBUG_=1"
],
release: [
"-O2"
],
},
arflags: {
common: [
"cr",
],
},
lflags: {
common: [
"-Wl,-static",
"-Wl,--gc-sections",
"-Wl,--build-id=none",
"-lstdc++",
"-lgcc",
"-lm",
"-lc",
"-lrdimon",
],
},
libdirs: {
common: [
"$(CGT_GCC_AARCH64_PATH)/lib",
],
}
};
function getCgtOptions(cpu, device)
{
let cgtOptions = {};
if (cpu.match(/a53*/))
{
cgtOptions = common.mergeCgtOptions(cgt_common, cgt_a53);
}
return cgtOptions;
}
module.exports = {
getCgtOptions,
};

95
.project/cgt/cgt_gcc-armv7.js Normal file
View File

@ -0,0 +1,95 @@
const common = require(`../common.js`);
const cgt_r5f = {
cflags: {
common: [
"-mcpu=cortex-r5",
"-mfloat-abi=hard",
"-mfpu=vfpv3-d16",
"-marm",
],
},
lflags: {
common: [
"-mcpu=cortex-r5",
"-mfloat-abi=hard",
"-mfpu=vfpv3-d16",
"-marm",
],
},
}
const cgt_common = {
path: "CGT_GCC_ARMV7_PATH",
cc: "arm-none-eabi-gcc",
ar: "arm-none-eabi-gcc-ar",
lnk: "arm-none-eabi-gcc",
strip: "arm-none-eabi-strip",
objcopy: "arm-none-eabi-objcopy",
includes: {
common: [
"${MCU_PLUS_SDK_PATH}/source",
"${MOTOR_CONTROL_SDK_PATH}/source",
],
},
cflags: {
common: [
"-Wall",
"-Werror",
"-g",
"-Wno-gnu-variable-sized-type-not-at-end",
"-Wno-unused-function",
"-Wno-int-to-pointer-cast",
"-Wno-pointer-to-int-cast",
"-Wno-unused-but-set-variable",
"-fdata-sections", /* this option is needed so that compiler throws away unused sections */
"-ffunction-sections", /* this option is needed so that compiler throws away unused sections */
],
debug: [
"-D_DEBUG_=1",
],
release: [
"-O2",
],
},
arflags: {
common: [
"cr",
],
},
lflags: {
common: [
"-Wl,-static",
"-Wl,--gc-sections",
"-Wl,--build-id=none",
"-lstdc++",
"-lgcc",
"-lm",
"-lc",
"-lnosys", /* this disable CCS output, rdimon enables CCS output, i.e semi-hosting, but there is some problem so disabling it */
],
},
libdirs: {
common: [
"${CGT_GCC_ARMV7_PATH}/lib",
],
},
};
function getCgtOptions(cpu, device)
{
let cgtOptions = {};
if(cpu.match(/r5f*/))
{
cgtOptions = common.mergeCgtOptions(cgt_common, cgt_r5f);
}
return cgtOptions;
}
module.exports = {
getCgtOptions,
};

131
.project/cgt/cgt_ti-arm-clang.js Normal file
View File

@ -0,0 +1,131 @@
const common = require(`../common.js`);
const cgt_r5f = {
cflags: {
common: [
"-mcpu=cortex-r5",
"-mfloat-abi=hard",
"-mfpu=vfpv3-d16",
],
},
lflags: {
common: [
"--diag_suppress=10063",
],
},
}
const cgt_m4f = {
cflags: {
common: [
"-mcpu=cortex-m4",
"-mfloat-abi=hard",
],
},
lflags: {
common: [
],
},
}
const cgt_common = {
path: "CGT_TI_ARM_CLANG_PATH",
cc: "tiarmclang",
ar: "tiarmar",
lnk: "tiarmclang",
strip: "tiarmstrip",
objcopy: "tiarmobjcopy",
cov: "tiarmcov",
profdata: "tiarmprofdata",
includes: {
common: [
"${CG_TOOL_ROOT}/include/c",
"${MCU_PLUS_SDK_PATH}/source",
"${MOTOR_CONTROL_SDK_PATH}/source",
],
},
cflags: {
common: [
"-mthumb",
"-Wall",
"-Werror",
"-g",
"-Wno-gnu-variable-sized-type-not-at-end",
"-Wno-unused-function",
],
cpp_common: [
"-Wno-c99-designator",
"-Wno-extern-c-compat",
"-Wno-c++11-narrowing",
"-Wno-reorder-init-list",
"-Wno-deprecated-register",
"-Wno-writable-strings",
"-Wno-enum-compare",
"-Wno-reserved-user-defined-literal",
"-Wno-unused-const-variable",
"-x c++",
],
debug: [
"-D_DEBUG_=1",
],
release: [
"-Os",
],
},
arflags: {
common: [
"rc",
],
},
lflags: {
common: [
"--ram_model",
"--reread_libs",
],
},
libdirs: {
common: [
"${CG_TOOL_ROOT}/lib",
],
},
libs: {
common: [
"libc.a",
"libsysbm.a",
],
},
};
const cgt_instrumentation = {
cflags: {
common: [
"-fprofile-instr-generate",
"-fcoverage-mapping",
],
},
};
function getCgtOptions(cpu, device)
{
let cgtOptions = {};
if(cpu.match(/r5f*/))
{
cgtOptions = common.mergeCgtOptions(cgt_common, cgt_r5f);
if(common.isInstrumentationMode()) {
cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_instrumentation);
}
}
if(cpu.match(/m4f*/))
{
cgtOptions = common.mergeCgtOptions(cgt_common, cgt_m4f);
}
return cgtOptions;
}
module.exports = {
getCgtOptions,
};

42
.project/cgt/cgt_ti-arm.js Normal file
View File

@ -0,0 +1,42 @@
const cgt = {
path: "CGT_TI_ARM_PATH",
cc: "armcl",
ar: "armar",
includes: {
common: [
"$(CGT_TI_ARM_PATH)/include",
".",
"$(MCU_PLUS_SDK_PATH)/source"],
"${MOTOR_CONTROL_SDK_PATH}/source",
},
cflags: {
common: [
"-c", "-qq",
"-pdsw225",
"--endian=little",
"-mv7R5",
"--abi=eabi",
"--float_support=vfpv3d16",
"--code_state=16",
"--emit_warnings_as_errors",
],
debug: [
"--symdebug:dwarf",
"-g",
"-D_DEBUG_=1",
],
release: [
"--embed_inline_assembly",
"-ms",
"-o3",
],
},
arflags: {
common: [
"rq",
]
},
};
module.exports = cgt;

150
.project/cgt/cgt_ti-c6000.js Normal file
View File

@ -0,0 +1,150 @@
const common = require(`../common.js`);
const cgt_common = {
path: "CGT_TI_C6000_PATH",
cc: "cl6x",
ar: "ar6x",
lnk: "lnk6x",
strip: "strip6x",
objcopy: "",
includes: {
common: [
"${CG_TOOL_ROOT}/include",
"${MCU_PLUS_SDK_PATH}/source",
"${MOTOR_CONTROL_SDK_PATH}/source",
],
},
cflags: {
common: [
"-mv6600",
"--abi=eabi",
"-q",
"-mi10",
"-mo",
"-pden",
"-pds=238",
"-pds=880",
"-pds1110",
"--emit_warnings_as_errors",
],
debug: [
"-D_DEBUG_=1",
],
release: [
"--program_level_compile",
"-o3",
"-mf3",
],
},
arflags: {
common: [
"rq",
],
},
lflags: {
common: [
"--warn_sections",
"--emit_warnings_as_errors",
"--rom_model",
"-x",
],
},
libdirs: {
common: [
"${CG_TOOL_ROOT}/lib",
],
},
libs: {
common: [
"libc.a",
],
},
};
const cgt_common_awr294x = {
path: "CGT_TI_C6000_PATH",
cc: "cl6x",
ar: "ar6x",
lnk: "lnk6x",
strip: "strip6x",
objcopy: "",
includes: {
common: [
"${CG_TOOL_ROOT}/include",
"${MCU_PLUS_SDK_PATH}/source",
"${MOTOR_CONTROL_SDK_PATH}/source",
],
},
cflags: {
common: [
"-mv6600",
"--c99",
"-q",
"-mo",
"-pden",
"--emit_warnings_as_errors",
"--mem_model:const=data",
"--mem_model:data=far_aggregates",
"--remove_hooks_when_inlining",
"-on2",
"--disable_push_pop",
"--fp_mode=relaxed",
"--assume_control_regs_read",
],
debug: [
"-D_DEBUG_=1",
],
release: [
"--program_level_compile",
"-o3",
"-mf2",
],
},
arflags: {
common: [
"rq",
],
},
lflags: {
common: [
"--warn_sections",
"--emit_warnings_as_errors",
"--ram_model",
"-x",
],
},
libdirs: {
common: [
"${CG_TOOL_ROOT}/lib",
],
},
libs: {
common: [
"libc.a",
],
},
};
function getCgtOptions(cpu, device)
{
let cgtOptions = {};
if(device.match(/awr294x*/))
{
cgtOptions = cgt_common_awr294x;
}
else
{
cgtOptions = cgt_common;
}
return cgtOptions;
}
module.exports = {
getCgtOptions,
};

149
.project/cgt/cgt_ti-pru-cgt.js Normal file
View File

@ -0,0 +1,149 @@
const common = require(`../common.js`);
const cgt_icssg0 = {
cflags: {
common: [
"-DICSSG0"
],
},
}
const cgt_icssg1 = {
cflags: {
common: [
"-DICSSG1"
],
},
}
const cgt_pru0 = {
cflags: {
common: [
"-DPRU0",
"-DSLICE0"
],
},
}
const cgt_pru1 = {
cflags: {
common: [
"-DPRU1",
"-DSLICE1"
],
},
}
const cgt_rtpru0 = {
cflags: {
common: [
"-DRTU_PRU0",
"-DSLICE0"
],
},
}
const cgt_rtpru1 = {
cflags: {
common: [
"-DRTU_PRU1",
"-DSLICE1"
],
},
}
const cgt_txpru0 = {
cflags: {
common: [
"-DTX_PRU0",
"-DSLICE0"
],
},
}
const cgt_txpru1 = {
cflags: {
common: [
"-DTX_PRU1",
"-DSLICE1"
],
},
}
const cgt_common = {
path: "CGT_TI_PRU_PATH",
includes: {
common: [
"${CG_TOOL_ROOT}/include",
"${MCU_PLUS_SDK_PATH}/source",
"${MOTOR_CONTROL_SDK_PATH}/source",
],
},
cflags: {
common: [
"-v4",
],
debug: [
"-D_DEBUG_=1",
],
release: [
"-O3",
],
},
lflags: {
common: [
"-llibc.a"
],
},
libdirs: {
common: [
"${CG_TOOL_ROOT}/lib"
],
},
};
function getCgtOptions(cpu, device)
{
let cgtOptions = {};
if(cpu.match(/pru0/))
{
cgtOptions = common.mergeCgtOptions(cgt_common, cgt_pru0);
}
if(cpu.match(/pru1/))
{
cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_pru1);
}
if(cpu.match(/rtpru0/))
{
cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_rtpru0);
}
if(cpu.match(/rtpru1/))
{
cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_rtpru1);
}
if(cpu.match(/txpru0/))
{
cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_txpru0);
}
if(cpu.match(/txpru1/))
{
cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_txpru1);
}
if(cpu.match(/icssg0/))
{
cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_icssg0);
}
if(cpu.match(/icssg1/))
{
cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_icssg1);
}
return cgtOptions;
}
module.exports = {
getCgtOptions,
};

203
.project/common.js Normal file
View File

@ -0,0 +1,203 @@
const fs = require('fs');
const path = require(`path`);
const _ = require('lodash');
const template = require("./templateCompiler");
function concatArrayPropertiesInObject(obj1, obj2, arr_prop, swap) {
if(obj2.hasOwnProperty(arr_prop)==false)
return;
if(obj1.hasOwnProperty(arr_prop)==false)
obj1[arr_prop] = {};
for (let prop in obj2[arr_prop]) {
if (obj2[arr_prop].hasOwnProperty(prop) && Array.isArray(obj2[arr_prop][prop])) {
if( obj1[arr_prop].hasOwnProperty(prop) == false )
obj1[arr_prop][prop] = [];
if( Array.isArray(obj1[arr_prop][prop]))
{
if(swap)
{
/* here the CGT options appear after project specific options, for some options
* esp libaries we want cgt libs to appear at the end.
*/
obj1[arr_prop][prop] = obj1[arr_prop][prop].concat(obj2[arr_prop][prop]);
}
else
{
/* here the CGT options appear before project specific options, most we want
* this so that project options can override CGT options
*/
obj1[arr_prop][prop] = obj2[arr_prop][prop].concat(obj1[arr_prop][prop]);
}
}
}
}
}
function mergeCgtOptions(project, commonCgtOptions) {
project = _.cloneDeep(project);
concatArrayPropertiesInObject(project, commonCgtOptions, "cflags", false);
concatArrayPropertiesInObject(project, commonCgtOptions, "arflags", false);
concatArrayPropertiesInObject(project, commonCgtOptions, "includes", false);
concatArrayPropertiesInObject(project, commonCgtOptions, "defines", false);
concatArrayPropertiesInObject(project, commonCgtOptions, "files", false);
concatArrayPropertiesInObject(project, commonCgtOptions, "filedirs", false);
concatArrayPropertiesInObject(project, commonCgtOptions, "asmfiles", false);
concatArrayPropertiesInObject(project, commonCgtOptions, "lflags", false);
concatArrayPropertiesInObject(project, commonCgtOptions, "libs", true);
concatArrayPropertiesInObject(project, commonCgtOptions, "libdirs", true);
concatArrayPropertiesInObject(project, commonCgtOptions, "lnkfiles", false);
return project;
}
function relative(pathStr1, pathStr2) {
let relpath = path.relative(pathStr1, pathStr2)
relpath = path.normalize(relpath);
return relpath.replace(/\\/g, "/");
}
function genBuildfiles(device) {
/* first call genExampleFiles, genComponentFiles since these create files that
* are then used by genProjectSpec and genMakefiles
*/
require(`./genExampleFiles`).genExampleFilesDevice(device);
require(`./genComponentFiles`).genComponentFilesDevice(device);
require(`./genMakefiles`).genMakefilesDevice(device);
require(`./genProjectSpec`).genProjectSpecsDevice(device);
require(`./genTirex`).genTirexDevice(device);
require(`./genSystemProject`).genSystemProjectDevice(device);
require(`./genCcsPackageFiles`).genCcsPackageFilesDevice(device);
}
function cleanBuildfiles(device) {
require(`./genExampleFiles`).cleanExampleFilesDevice(device);
require(`./genComponentFiles`).cleanComponentFilesDevice(device);
require(`./genMakefiles`).cleanMakefilesDevice(device);
require(`./genProjectSpec`).cleanProjectSpecsDevice(device);
require(`./genSystemProject`).cleanSystemProjectDevice(device);
}
function convertTemplateToFile(templateFilename, outputFilename, args) {
let inData = fs.readFileSync(templateFilename, 'utf8',
function (err, data) {
if (err) throw err;
}
);
let outData = template.executeTemplate(inData, args);
fs.writeFileSync(outputFilename, outData,
function (err) {
if (err) throw err;
}
);
}
function makeExampleOutPath(projectPath, buildOption)
{
return `${projectPath}/${buildOption.board}/${buildOption.cpu}_${buildOption.os}/${buildOption.cgt}`
}
const fs_promise = require('fs').promises;
function deleteFile(filepath)
{
(async () => {
try {
await fs_promise.unlink(filepath);
} catch (e) {
/* file doens't exist. Skip error!! */
}
})();
}
function getDefaultProjectDescription(name, cpu, os) {
let title = name.replace(/_/g, ' ');
// Title Case : Converts "hello world" to "Hello World" using regex
title = title.replace(
/\w\S*/g,
function (s) {
return s.charAt(0).toUpperCase() + s.substr(1).toLowerCase();
}
);
title = "A " + title + " Example. CPU is " + cpu.toUpperCase() + " running " + os.toUpperCase() + ".";
return title;
}
function getDefaultSystemProjectDescription(name) {
let title = name.replace(/_/g, ' ');
// Title Case : Converts "hello world" to "Hello World" using regex
title = title.replace(
/\w\S*/g,
function (s) {
return s.charAt(0).toUpperCase() + s.substr(1).toLowerCase();
}
);
title = "A " + title + " System Example.";
return title;
}
/* this can be "development" or "production" */
let genBuildFilesMode = "development";
function isDevelopmentMode()
{
if(genBuildFilesMode=="development")
return true;
return false;
}
function setGenBuildFilesMode(mode)
{
if(mode=="production" || mode == "development")
{
genBuildFilesMode = mode;
}
}
/* this can be "enable" or "disable" */
let genInstrumentationMode = "disable";
function isInstrumentationMode()
{
if(genInstrumentationMode=="enable")
return true;
return false;
}
function setInstrumentationMode(mode)
{
genInstrumentationMode = mode;
}
module.exports = {
genBuildfiles,
isDevelopmentMode,
setGenBuildFilesMode,
isInstrumentationMode,
setInstrumentationMode,
cleanBuildfiles,
mergeCgtOptions,
convertTemplateToFile,
path: {
relative,
makeExampleOutPath,
},
deleteFile,
getDefaultProjectDescription,
getDefaultSystemProjectDescription,
};

180
.project/device/project_am243x.js Normal file
View File

@ -0,0 +1,180 @@
const common = require("../common.js");
const component_file_list = [
"source/motor_control/current_sense/sdfm/.project/project.js",
"source/motor_control/position_sense/endat/.project/project.js",
"source/motor_control/position_sense/hdsl/.project/project.js",
"source/motor_control/position_sense/tamagawa/.project/project.js",
];
const device_defines = {
common: [
"SOC_AM243X",
],
};
const example_file_list = [
"examples/motor_control/endat_diagnostic/single_channel/.project/project.js",
"examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project.js",
"examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project.js",
"examples/motor_control/hdsl_diagnostic/multi_channel/.project/project.js",
"examples/motor_control/hdsl_diagnostic/single_channel/.project/project.js",
"examples/motor_control/hdsl_diagnostic_with_traces/.project/project.js",
"examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project.js",
"examples/motor_control/tamagawa_diagnostic/single_channel/.project/project.js",
"examples/motor_control/icss_sdfm/.project/project.js",
"source/motor_control/current_sense/sdfm/firmware/.project/project.js",
"source/motor_control/position_sense/endat/firmware/multi_channel_load_share/.project/project.js",
"source/motor_control/position_sense/endat/firmware/single_channel/.project/project.js",
"source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js",
"source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project.js",
"source/motor_control/position_sense/tamagawa/firmware/single_channel/.project/project.js",
];
function getProjectSpecCpu(cpu) {
let projectSpecCpu =
{
"r5fss0-0": "MAIN_PULSAR_Cortex_R5_0_0",
"r5fss0-1": "MAIN_PULSAR_Cortex_R5_0_1",
"r5fss1-0": "MAIN_PULSAR_Cortex_R5_1_0",
"r5fss1-1": "MAIN_PULSAR_Cortex_R5_1_1",
"m4fss0-0": "Cortex_M4F_0",
"icssg0-pru0": "ICSS_G0_PRU_0",
"icssg0-pru1": "ICSS_G0_PRU_1",
"icssg0-rtupru0": "ICSS_G0_RTU_PRU_0",
"icssg0-rtupru1": "ICSS_G0_RTU_PRU_1",
"icssg0-txpru0": "ICSS_G0_TX_PRU_0",
"icssg0-txpru1": "ICSS_G0_TX_PRU_1",
"icssg1-pru0": "ICSS_G1_PRU_0",
"icssg1-pru1": "ICSS_G1_PRU_1",
"icssg1-rtupru0": "ICSS_G1_RTU_PRU_0",
"icssg1-rtupru1": "ICSS_G1_RTU_PRU_1",
"icssg1-txpru0": "ICSS_G1_TX_PRU_0",
"icssg1-txpru1": "ICSS_G1_TX_PRU_1",
}
return projectSpecCpu[cpu];
}
function getComponentList() {
return component_file_list;
}
function getExampleList() {
return example_file_list;
}
function getSysCfgDevice(board) {
switch (board) {
case "am243x-lp":
return "AM243x_ALX_beta";
default:
case "am243x-evm":
return "AM243x_ALV_beta";
}
}
function getProjectSpecDevice(board) {
switch (board) {
case "am243x":
return "AM243x";
case "am243x-lp":
return "AM2434_ALX";
default:
case "am243x-evm":
return "AM2434_ALV";
}
}
function getSysCfgCpu(cpu) {
return cpu;
}
function getSysCfgPkg(board) {
switch (board) {
case "am243x-lp":
return "ALX";
default:
case "am243x-evm":
return "ALV";
}
}
function getSysCfgPart(board) {
switch (board) {
case "am243x-lp":
return "ALX";
default:
case "am243x-evm":
return "ALV";
}
}
function getDevToolTirex(board) {
switch (board) {
case "am243x-lp":
return "AM243x_LAUNCHPAD";
default:
case "am243x-evm":
return "AM243x_GP_EVM";
}
}
function getProperty() {
let property = {};
property.defines = device_defines;
return property;
}
function getLinuxFwName(cpu) {
switch(cpu) {
case "r5fss0-0":
return "am243-main-r5f0_0-fw";
case "r5fss0-1":
return "am243-main-r5f0_1-fw";
case "r5fss1-0":
return "am243-main-r5f1_0-fw";
case "r5fss1-1":
return "am243-main-r5f1_1-fw";
case "m4fss0-0":
return "am243-mcu-m4f0_0-fw";
}
return undefined;
}
function getProductNameProjectSpec() {
return "MOTOR_CONTROL_SDK_AM243X";
}
function getDependentProductNameProjectSpec() {
return "MCU_PLUS_SDK_AM243X";
}
function getFlashAddr() {
return 0x60000000;
}
module.exports = {
getComponentList,
getExampleList,
getSysCfgDevice,
getSysCfgCpu,
getSysCfgPkg,
getSysCfgPart,
getProjectSpecDevice,
getProjectSpecCpu,
getDevToolTirex,
getProperty,
getLinuxFwName,
getProductNameProjectSpec,
getDependentProductNameProjectSpec,
getFlashAddr,
};

140
.project/device/project_am263x.js Normal file
View File

@ -0,0 +1,140 @@
const common = require("../common.js");
const component_file_list = [
"source/motor_control/position_sense/tamagawa_over_soc_uart/.project/project.js",
];
const device_defines = {
common: [
"SOC_AM263X",
],
};
const example_file_list = [
"examples/motor_control/tamagawa_diagnostic_over_soc_uart/.project/project.js",
];
function getProjectSpecCpu(cpu) {
let projectSpecCpu =
{
"r5fss0-0": "MAIN_PULSAR_Cortex_R5_0_0",
"r5fss0-1": "MAIN_PULSAR_Cortex_R5_0_1",
"r5fss1-0": "MAIN_PULSAR_Cortex_R5_1_0",
"r5fss1-1": "MAIN_PULSAR_Cortex_R5_1_1",
"icssm-pru0": "ICSSM_PRU_0",
"icssm-pru1": "ICSSM_PRU_1",
}
return projectSpecCpu[cpu];
}
function getComponentList() {
return component_file_list;
}
function getExampleList() {
return example_file_list;
}
function getSysCfgDevice(board) {
switch (board) {
case "am263x-lp":
return "AM263x_beta";
default:
case "am263x-cc":
return "AM263x_beta";
}
}
function getProjectSpecDevice(board) {
switch (board) {
case "am263x":
return "AM263x";
case "am263x-lp":
return "AM263x";
default:
case "am263x-cc":
return "AM263x";
}
}
function getSysCfgCpu(cpu) {
return cpu;
}
function getSysCfgPkg(board) {
switch (board) {
case "am263x-lp":
return "ZCZ";
default:
case "am263x-cc":
return "ZCZ";
}
}
function getSysCfgPart(board) {
switch (board) {
case "am263x-lp":
return "AM263x";
default:
case "am263x-cc":
return "AM263x";
}
}
function getDevToolTirex(board) {
switch (board) {
case "am263x-lp":
return "LP-AM263";
default:
case "am263x-cc":
return "TMDSCNCD263";
}
}
function getProperty() {
let property = {};
property.defines = device_defines;
return property;
}
function getLinuxFwName(cpu) {
switch(cpu) {
case "r5fss0-0":
return "am263-main-r5f0_0-fw";
case "r5fss0-1":
return "am263-main-r5f0_1-fw";
case "r5fss1-0":
return "am263-main-r5f1_0-fw";
case "r5fss1-1":
return "am263-main-r5f1_1-fw";
}
return undefined;
}
function getProductNameProjectSpec() {
return "MCU_PLUS_SDK_AM263X";
}
function getFlashAddr() {
return 0x60000000;
}
module.exports = {
getComponentList,
getExampleList,
getSysCfgDevice,
getSysCfgCpu,
getSysCfgPkg,
getSysCfgPart,
getProjectSpecDevice,
getProjectSpecCpu,
getDevToolTirex,
getProperty,
getLinuxFwName,
getProductNameProjectSpec,
getFlashAddr,
};

155
.project/device/project_am64x.js Normal file
View File

@ -0,0 +1,155 @@
const common = require("../common.js");
const component_file_list = [
"source/motor_control/current_sense/sdfm/.project/project.js",
"source/motor_control/position_sense/endat/.project/project.js",
"source/motor_control/position_sense/hdsl/.project/project.js",
"source/motor_control/position_sense/tamagawa/.project/project.js",
];
const device_defines = {
common: [
"SOC_AM64X",
],
};
const example_file_list = [
"examples/motor_control/endat_diagnostic/single_channel/.project/project.js",
"examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project.js",
"examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project.js",
"examples/motor_control/hdsl_diagnostic/multi_channel/.project/project.js",
"examples/motor_control/hdsl_diagnostic/single_channel/.project/project.js",
"examples/motor_control/hdsl_diagnostic_with_traces/.project/project.js",
"examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project.js",
"examples/motor_control/tamagawa_diagnostic/single_channel/.project/project.js",
"examples/motor_control/icss_sdfm/.project/project.js",
"source/motor_control/current_sense/sdfm/firmware/.project/project.js",
"source/motor_control/position_sense/endat/firmware/multi_channel_load_share/.project/project.js",
"source/motor_control/position_sense/endat/firmware/single_channel/.project/project.js",
"source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js",
"source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js",
"source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project.js",
"source/motor_control/position_sense/tamagawa/firmware/single_channel/.project/project.js",
];
function getProjectSpecCpu(cpu) {
let projectSpecCpu =
{
"r5fss0-0": "MAIN_PULSAR_Cortex_R5_0_0",
"r5fss0-1": "MAIN_PULSAR_Cortex_R5_0_1",
"r5fss1-0": "MAIN_PULSAR_Cortex_R5_1_0",
"r5fss1-1": "MAIN_PULSAR_Cortex_R5_1_1",
"m4fss0-0": "Cortex_M4F_0",
"a53ss0-0": "CortexA53_0",
"icssg0-pru0": "ICSS_G0_PRU_0",
"icssg0-pru1": "ICSS_G0_PRU_1",
"icssg0-rtupru0": "ICSS_G0_RTU_PRU_0",
"icssg0-rtupru1": "ICSS_G0_RTU_PRU_1",
"icssg0-txpru0": "ICSS_G0_TX_PRU_0",
"icssg0-txpru1": "ICSS_G0_TX_PRU_1",
"icssg1-pru0": "ICSS_G1_PRU_0",
"icssg1-pru1": "ICSS_G1_PRU_1",
"icssg1-rtupru0": "ICSS_G1_RTU_PRU_0",
"icssg1-rtupru1": "ICSS_G1_RTU_PRU_1",
"icssg1-txpru0": "ICSS_G1_TX_PRU_0",
"icssg1-txpru1": "ICSS_G1_TX_PRU_1",
}
return projectSpecCpu[cpu];
}
function getComponentList() {
return component_file_list;
}
function getExampleList() {
return example_file_list;
}
function getSysCfgDevice(board) {
return "AM64x_beta";
}
function getProjectSpecDevice(board) {
return "AM64x";
}
function getSysCfgCpu(cpu) {
return cpu;
}
function getSysCfgPkg(board) {
return "ALV";
}
function getSysCfgPart(board) {
return "Default";
}
function getDevToolTirex(board) {
switch (board) {
case "am64x-sk":
return "AM64x_SK_EVM";
default:
case "am64x-evm":
return "AM64x_GP_EVM";
}
}
function getProperty() {
let property = {};
property.defines = device_defines;
return property;
}
function getLinuxFwName(cpu) {
switch(cpu) {
case "r5fss0-0":
return "am64-main-r5f0_0-fw";
case "r5fss0-1":
return "am64-main-r5f0_1-fw";
case "r5fss1-0":
return "am64-main-r5f1_0-fw";
case "r5fss1-1":
return "am64-main-r5f1_1-fw";
case "m4fss0-0":
return "am64-mcu-m4f0_0-fw";
}
return undefined;
}
function getProductNameProjectSpec() {
return "MOTOR_CONTROL_SDK_AM64X";
}
function getDependentProductNameProjectSpec() {
return "MCU_PLUS_SDK_AM64X";
}
function getFlashAddr() {
return 0x60000000;
}
module.exports = {
getComponentList,
getExampleList,
getSysCfgDevice,
getSysCfgCpu,
getSysCfgPkg,
getSysCfgPart,
getProjectSpecDevice,
getProjectSpecCpu,
getDevToolTirex,
getProperty,
getLinuxFwName,
getProductNameProjectSpec,
getDependentProductNameProjectSpec,
getFlashAddr,
};

28
.project/genCcsPackageFiles.js Normal file
View File

@ -0,0 +1,28 @@
const common = require(`./common.js`);
function genCcsPackageFilesDevice(device) {
let args = {
device: device,
utils: require(`./genProjectSpec.js`).utils,
common: common,
};
common.convertTemplateToFile(
`.project/templates/package.ccs.json.xdt`,
`.metadata/.tirex/package.ccs.json`,
args);
common.convertTemplateToFile(
`.project/templates/package.tirex.json.xdt`,
`.metadata/.tirex/package.tirex.json`,
args);
common.convertTemplateToFile(
`.project/templates/product.json.xdt`,
`.metadata/product.json`,
args);
}
module.exports = {
genCcsPackageFilesDevice
}

71
.project/genComponentFiles.js Normal file
View File

@ -0,0 +1,71 @@
const common = require(`./common.js`);
const _ = require('lodash');
function genComponentFilesDevice(device) {
let file_list = require(`./device/project_${device}`).getComponentList();
for(component of file_list) {
property = require(`../${component}`).getComponentProperty(device);
for(buildOption of property.buildOptionCombos) {
let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device);
let common_build_property = require(`./device/project_${device}`).getProperty();
let project = [];
build_property = require(`../${component}`).getComponentBuildProperty(buildOption);
project = _.merge({}, project, property);
project = _.merge({}, project, buildOption);
project = common.mergeCgtOptions(project, common_build_property);
project = _.merge({}, project, build_property);
if(!project.templates)
continue;
for(template of project.templates)
{
let args = {
sdkPath: "MOTOR_CONTROL_SDK_PATH",
relPath: common.path.relative(project.dirPath, "."),
project: project,
options: template.options,
};
common.convertTemplateToFile(
template.input,
`${project.dirPath}/${template.output}`,
args);
}
}
}
}
function cleanComponentFilesDevice(device) {
let file_list = require(`./device/project_${device}`).getComponentList();
for(component of file_list) {
property = require(`../${component}`).getComponentProperty(device);
for(buildOption of property.buildOptionCombos) {
let project = [];
build_property = require(`../${component}`).getComponentBuildProperty(buildOption);
project = _.merge({}, project, property);
project = _.merge({}, project, buildOption);
project = _.merge({}, project, build_property);
if(!project.templates)
continue;
for(template of project.templates)
{
common.deleteFile(`${project.dirPath}/${template.output}`);
}
}
}
}
module.exports = {
genComponentFilesDevice,
cleanComponentFilesDevice,
}

84
.project/genExampleFiles.js Normal file
View File

@ -0,0 +1,84 @@
const common = require(`./common.js`);
const path = require(`path`);
const fs = require(`fs`);
const _ = require('lodash');
function genExampleFilesDevice(device) {
let example_file_list = require(`./device/project_${device}`).getExampleList();
for(example of example_file_list) {
property = require(`../${example}`).getComponentProperty(device);
for(buildOption of property.buildOptionCombos) {
let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device);
let common_build_property = require(`./device/project_${device}`).getProperty();
let project = [];
let outPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
fs.mkdirSync(outPath, { recursive: true });
build_property = require(`../${example}`).getComponentBuildProperty(buildOption);
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath);
project = _.merge({}, project, buildOption);
project = common.mergeCgtOptions(project, common_build_property);
project = _.merge({}, project, build_property);
project.dirPath = outPath;
if(!project.templates)
continue;
let isInstrumentation = common.isInstrumentationMode();
for(template of project.templates)
{
let args = {
sdkPath: "MOTOR_CONTROL_SDK_PATH",
relPath: common.path.relative(project.dirPath, "."),
project: project,
options: template.options,
isInstrumentation: isInstrumentation,
};
common.convertTemplateToFile(
template.input,
`${project.dirPath}/${template.output}`,
args);
}
}
}
}
function cleanExampleFilesDevice(device) {
let example_file_list = require(`./device/project_${device}`).getExampleList();
for(example of example_file_list) {
property = require(`../${example}`).getComponentProperty(device);
for(buildOption of property.buildOptionCombos) {
let project = [];
let outPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
fs.mkdirSync(outPath, { recursive: true });
build_property = require(`../${example}`).getComponentBuildProperty(buildOption);
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath);
project = _.merge({}, project, buildOption);
project = _.merge({}, project, build_property);
project.dirPath = outPath;
if(!project.templates)
continue;
for(template of project.templates)
{
common.deleteFile(`${project.dirPath}/${template.output}`);
}
}
}
}
module.exports = {
genExampleFilesDevice,
cleanExampleFilesDevice,
}

410
.project/genMakefiles.js Normal file
View File

@ -0,0 +1,410 @@
const common = require(`./common.js`);
const path = require(`path`);
const fs = require(`fs`);
const _ = require('lodash');
function genMakefileDeviceTop(component_file_list, example_file_list, device, isInternal) {
let component_make_list = [];
let example_make_list = [];
let example_make_projectspec_list = [];
let system_example_make_list = [];
let system_example_make_projectspec_list = [];
let genFolder = ".";
let relPath = ".";
if(isInternal == true) {
genFolder = "./test"
relPath = "..";
}
for(component of component_file_list) {
let component_make = [];
let buildTarget = [];
let buildTargetClean = [];
let buildTargetScrub = [];
property = require(`../${component}`).getComponentProperty(device);
let tag="";
if(property.tag)
{
tag = `.${property.tag}`;
}
component_make.name = property.name;
component_make.tag = tag;
component_make.relpath = common.path.relative(path.normalize(__dirname + `/../${genFolder}`), property.dirPath);
if(property.isSkipTopLevelBuild === true)
{
component_make.isSkipTopLevelBuild = true;
}
if(property.isPrebuilt === true)
{
component_make.isPrebuilt = true;
}
for(buildOption of property.buildOptionCombos) {
buildTarget +=` ${property.name}_${buildOption.cpu}.${buildOption.cgt}`;
buildTargetClean +=` ${property.name}_${buildOption.cpu}.${buildOption.cgt}_clean`;
buildTargetScrub +=` ${property.name}_${buildOption.cpu}.${buildOption.cgt}_scrub`;
}
component_make.buildTarget = buildTarget;
component_make.buildTargetClean = buildTargetClean;
component_make.buildTargetScrub = buildTargetScrub;
if(property.isInternal == isInternal) {
component_make_list.push(component_make);
}
}
for(example of example_file_list) {
property = require(`../${example}`).getComponentProperty(device);
for(buildOption of property.buildOptionCombos) {
let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
let example_make = {};
let buildTarget = {};
let buildTargetClean = {};
let buildTargetScrub = {};
example_make.name = `${property.name}_${buildOption.board}_${buildOption.cpu}_${buildOption.os}_${buildOption.cgt}`;
example_make.relpath = common.path.relative(path.normalize(__dirname + `/../${genFolder}`), makefileOutPath);
if(property.isSkipTopLevelBuild === true)
{
example_make.isSkipTopLevelBuild = true;
}
if(property.isBootLoader === true)
{
example_make.isBootLoader = true;
}
buildTarget =` ${property.name}_${buildOption.board}_${buildOption.cpu}_${buildOption.os}_${buildOption.cgt}`;
buildTargetClean =` ${property.name}_${buildOption.board}_${buildOption.cpu}_${buildOption.os}_${buildOption.cgt}_clean`;
buildTargetScrub =` ${property.name}_${buildOption.board}_${buildOption.cpu}_${buildOption.os}_${buildOption.cgt}_scrub`;
example_make.buildTarget = buildTarget;
example_make.buildTargetClean = buildTargetClean;
example_make.buildTargetScrub = buildTargetScrub;
if(property.isInternal == isInternal) {
let isPartOfSystemProject = false;
if(buildOption.isPartOfSystemProject && buildOption.isPartOfSystemProject === true)
{
isPartOfSystemProject = true;
}
if(isPartOfSystemProject === false)
{
example_make_list.push(example_make);
if(property.skipProjectSpec) {
/* no need to output project spec make commands */
}
else {
example_make_projectspec_list.push(example_make);
}
}
}
}
}
for(example of example_file_list) {
example = require(`../${example}`);
if( ! example.getSystemProjects)
continue;
let property = example.getComponentProperty(device);
let systemProjects = example.getSystemProjects(device);
for ( project of systemProjects)
{
let outPath = `${property.dirPath}/${project.board}/system_${project.tag}`
let system_example_make = {};
system_example_make.name = `${project.name}_${project.board}_system_${project.tag}`;
system_example_make.relpath = common.path.relative(path.normalize(__dirname + `/../${genFolder}`), outPath);
system_example_make.buildTarget = " " + system_example_make.name;
system_example_make.buildTargetClean = " " + system_example_make.name + "_clean";
system_example_make.buildTargetScrub = " " + system_example_make.name + "_scrub";
if(property.isSkipTopLevelBuild === true)
{
system_example_make.isSkipTopLevelBuild = true;
}
if(property.isInternal == isInternal) {
system_example_make_list.push(system_example_make);
if( project.skipProjectSpec && project.skipProjectSpec === true)
{
/* skip project spec */
}
else
{
system_example_make_projectspec_list.push(system_example_make);
}
}
}
}
let args = {
component_list: component_make_list,
example_list: example_make_list,
system_example_list: system_example_make_list,
device: device,
};
common.convertTemplateToFile(
`.project/templates/makefile_device_top.xdt`,
`${genFolder}/makefile.${device}`,
args);
args = {
example_list: example_make_projectspec_list,
system_example_list: system_example_make_projectspec_list,
device: device,
sdkPath: "MOTOR_CONTROL_SDK_PATH",
relPath: relPath
};
common.convertTemplateToFile(
`.project/templates/makefile_device_projectspec_top.xdt`,
`${genFolder}/makefile_projectspec.${device}`,
args);
}
function genMakefileLibrary(component_file_list, device) {
for(component of component_file_list) {
property = require(`../${component}`).getComponentProperty(device);
for(buildOption of property.buildOptionCombos) {
let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device);
let common_build_property = require(`./device/project_${device}`).getProperty();
build_property = require(`../${component}`).getComponentBuildProperty(buildOption);
let project = [];
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), property.dirPath);
project = _.merge({}, project, buildOption);
project = _.merge({}, project, build_property);
project = common.mergeCgtOptions(project, commonCgtOptions);
project = common.mergeCgtOptions(project, common_build_property);
let args = {
sdkPath: "MOTOR_CONTROL_SDK_PATH",
relPath: common.path.relative(project.dirPath, "."),
project: project,
cgtOptions: require(`./cgt/cgt_${project.cgt}`).getCgtOptions(buildOption.cpu, device),
};
let tag="";
if(property.tag)
{
tag = `.${property.tag}`;
}
common.convertTemplateToFile(
`.project/templates/makefile_${project.type}.xdt`,
`${project.dirPath}/makefile${tag}.${project.device}.${project.cpu}.${project.cgt}`,
args);
}
}
}
function cleanMakefileLibrary(component_file_list, device) {
for(component of component_file_list) {
property = require(`../${component}`).getComponentProperty(device);
for(buildOption of property.buildOptionCombos) {
build_property = require(`../${component}`).getComponentBuildProperty(buildOption);
let project = [];
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), property.dirPath);
common.deleteFile(`${project.dirPath}/makefile.${buildOption.device}.${buildOption.cpu}.${buildOption.cgt}`);
}
}
}
function genMakefileExample(example_file_list, device) {
for(example of example_file_list) {
property = require(`../${example}`).getComponentProperty(device);
for(buildOption of property.buildOptionCombos) {
let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device);
let common_build_property = require(`./device/project_${device}`).getProperty();
let project = [];
let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
fs.mkdirSync(makefileOutPath, { recursive: true });
build_property = require(`../${example}`).getComponentBuildProperty(buildOption);
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath);
project = _.merge({}, project, buildOption);
project = _.merge({}, project, build_property);
project = common.mergeCgtOptions(project, commonCgtOptions);
project = common.mergeCgtOptions(project, common_build_property);
project.dirPath = makefileOutPath;
let isInstrumentationMode = false;
if(common.isInstrumentationMode()) {
isInstrumentationMode = true;
}
let args = {
sdkPath: "MOTOR_CONTROL_SDK_PATH",
relPath: common.path.relative(project.dirPath, "."),
project: project,
cgtOptions: require(`./cgt/cgt_${project.cgt}`).getCgtOptions(buildOption.cpu, device),
syscfg: {
device: require(`./device/project_${device}.js`).getSysCfgDevice(buildOption.board),
cpu: require(`./device/project_${device}.js`).getSysCfgCpu(buildOption.cpu),
pkg: require(`./device/project_${device}.js`).getSysCfgPkg(buildOption.board),
part: require(`./device/project_${device}.js`).getSysCfgPart(buildOption.board),
},
linuxFwName: require(`./device/project_${device}`).getLinuxFwName(project.cpu),
isInstrumentationMode: isInstrumentationMode,
flashAddr: require(`./device/project_${device}.js`).getFlashAddr(),
};
if(project.makefile) {
common.convertTemplateToFile(
`.project/templates/makefile_${project.makefile}.xdt`,
`${project.dirPath}/makefile`,
args);
} else
common.convertTemplateToFile(
`.project/templates/makefile_${project.type}.xdt`,
`${project.dirPath}/makefile`,
args);
}
}
}
function cleanMakefileExample(example_file_list, device) {
for(example of example_file_list) {
property = require(`../${example}`).getComponentProperty(device);
for(buildOption of property.buildOptionCombos) {
let project = [];
let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
fs.mkdirSync(makefileOutPath, { recursive: true });
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath);
project.dirPath = makefileOutPath;
common.deleteFile(`${project.dirPath}/makefile`);
}
}
}
function genMakefileProjectSpec(example_file_list, device) {
for(example of example_file_list) {
property = require(`../${example}`).getComponentProperty(device);
if(property.skipProjectSpec)
continue;
for(buildOption of property.buildOptionCombos) {
let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device);
let common_build_property = require(`./device/project_${device}`).getProperty();
let project = [];
let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
fs.mkdirSync(makefileOutPath, { recursive: true });
build_property = require(`../${example}`).getComponentBuildProperty(buildOption);
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath);
project = _.merge({}, project, buildOption);
project = common.mergeCgtOptions(project, common_build_property);
project = _.merge({}, project, build_property);
project.dirPath = makefileOutPath;
let args = {
sdkPath: "MOTOR_CONTROL_SDK_PATH",
relPath: common.path.relative(project.dirPath, "."),
project: project
};
common.convertTemplateToFile(
`.project/templates/makefile_projectspec.xdt`,
`${project.dirPath}/makefile_projectspec`,
args);
}
}
}
function cleanMakefileProjectSpec(example_file_list, device) {
for(example of example_file_list) {
property = require(`../${example}`).getComponentProperty(device);
if(property.skipProjectSpec)
continue;
for(buildOption of property.buildOptionCombos) {
let project = [];
let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
fs.mkdirSync(makefileOutPath, { recursive: true });
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath);
project.dirPath = makefileOutPath;
common.deleteFile(`${project.dirPath}/makefile_projectspec`);
}
}
}
function genMakeImport(device) {
let args = {
device: device,
utils: require(`./genProjectSpec.js`).utils,
common: common,
};
common.convertTemplateToFile(
`.project/templates/imports.mak.xdt`,
`imports.mak`,
args);
}
function genMakefilesDevice(device) {
let component_file_list = require(`./device/project_${device}`).getComponentList();
let example_file_list = require(`./device/project_${device}`).getExampleList();
genMakefileDeviceTop(component_file_list, example_file_list, device, false); /* External libs/examples */
genMakefileDeviceTop(component_file_list, example_file_list, device, false); /* Internal libs/examples */
genMakefileLibrary(component_file_list, device);
genMakefileExample(example_file_list, device);
genMakefileProjectSpec(example_file_list, device);
genMakeImport(device);
}
function cleanMakefilesDevice(device) {
let component_file_list = require(`./device/project_${device}`).getComponentList();
let example_file_list = require(`./device/project_${device}`).getExampleList();
/* Remove top level files */
common.deleteFile(`./makefile.${device}`);
common.deleteFile(`./makefile_projectspec.${device}`);
common.deleteFile(`./test/makefile.${device}`);
common.deleteFile(`./test/makefile_projectspec.${device}`);
cleanMakefileLibrary(component_file_list, device);
cleanMakefileExample(example_file_list, device);
cleanMakefileProjectSpec(example_file_list, device);
}
module.exports = {
genMakefilesDevice,
cleanMakefilesDevice,
}

323
.project/genProjectSpec.js Normal file
View File

@ -0,0 +1,323 @@
const common = require(`./common.js`);
const path = require(`path`);
const _ = require('lodash');
const fs = require('fs');
const utils = {
capitalize: (s) => {
if (typeof s !== 'string') return ''
return s.charAt(0).toUpperCase() + s.slice(1)
},
replace: (s, a, b) => {
return s.replace(a, b);
},
getDeviceFamilyProjectSpec: (cpu) => {
let cpuFamily = 'ARM';
if (cpu.includes('r5f') == true) {
cpuFamily = 'ARM';
}
if (cpu.includes('c66') == true) {
cpuFamily = 'C6000';
}
if (cpu.includes('pru') == true) {
cpuFamily = 'PRU';
}
return cpuFamily;
},
getOutputTypeProjectSpec: (type) => {
let outputType = 'executable';
if(type == "executable")
outputType = 'executable';
if(type == "library")
outputType = 'staticLibrary';
return outputType;
},
getSysCfgDeviceProjectSpec: (device, board) => {
return require(`./device/project_${device}`).getSysCfgDevice(board);
},
getSysCfgCpuProjectSpec: (cpu) => {
return require(`./device/project_${device}`).getSysCfgCpu(cpu);
},
getProjectSpecDevice: (device) => {
return require(`./device/project_${device}`).getProjectSpecDevice(device);
},
getProjectSpecCpu: (device, cpu) => {
return require(`./device/project_${device}`).getProjectSpecCpu(cpu);
},
getDeviceIdProjectSpec: (device, cpu, board) => {
let deviceName = '';
let cpuName = '';
deviceName = require(`./device/project_${device}`).getProjectSpecDevice(board);
if (cpu.includes('r5f') == true) {
cpuName = 'Cortex R';
}
if (cpu.includes('a53') == true) {
cpuName = 'Cortex A';
}
if (cpu.includes('m4f') == true) {
cpuName = 'Cortex M';
}
if (cpu.includes('c66') == true) {
cpuName = 'TMS320C66XX';
}
if (cpu.includes('pru') == true) {
if (board == "am64x-evm") {
return "AM64x_GP_EVM"; // check for other devices
} else if (board == "am243x-evm") {
return "AM243x_GP_EVM";
} else if (board == "am243x-lp") {
return "AM243x_LAUNCHPAD";
} else if (board == "am263x-cc") {
return "AM263x_CC";
} else if (board == "am263x-lp") {
return "AM263x_LAUNCHPAD";
}
}
return cpuName + '.' + deviceName;
},
getFileListProjectSpec: (files, filedirs, projectabspath) => {
let filelist = [];
for (prop in files) {
if (files.hasOwnProperty(prop) && Array.isArray(files[prop])) {
for (let file of files[prop]) {
let foundFile = false;
for (filedir of filedirs[prop]) {
let checkPath = path.normalize(projectabspath + '/' + filedir + '/' + file);
if (fs.existsSync(checkPath) == true) {
filelist.push(filedir + '/' + file);
foundFile = true;
}
}
if(foundFile == false) {
console.log(`ERROR : Couldn't find ${file} in given source directories for ${projectabspath} ...`)
}
}
}
}
return filelist;
},
getToolChainProjectSpec: (cgt) => {
let toolchain = ''
switch(cgt) {
case 'ti-arm-clang':
toolchain = 'TICLANG'
break;
case 'ti-arm-cgt':
toolchain = 'TI'
break;
case 'gcc-armv7':
toolchain = 'GNU'
break;
case 'gcc-aarch64':
toolchain = 'GNU'
break;
case 'ti-pru-cgt':
toolchain = 'TI'
break;
default:
toolchain = 'TI'
}
return toolchain;
},
getProductNameProjectSpec: (device) => {
if(common.isDevelopmentMode())
return "MOTOR_CONTROL_SDK_AMXXX"
return require(`./device/project_${device}`).getProductNameProjectSpec();
},
getDependentProductNameProjectSpec: (device) => {
if(common.isDevelopmentMode())
return "MCU_PLUS_SDK_AMXXX"
return require(`./device/project_${device}`).getDependentProductNameProjectSpec();
},
/* default action for files in project spec, i.e copy or link */
getDefaultActionProjectSpec: () => {
if(common.isDevelopmentMode())
return "copy"; /* use copy for development mode as well */
return "copy";
},
getToolChainVersionProjectSpec: (cgt) => {
let toolchainVersion = ''
switch(cgt) {
case 'ti-arm-clang':
toolchainVersion = '2.1.2'
break;
case 'gcc-aarch64':
toolchainVersion = '9.2'
break;
case 'gcc-armv7':
toolchainVersion = '7.2'
break;
case 'ti-c6000':
toolchainVersion = '8.3.12'
break;
case 'ti-pru-cgt':
toolchainVersion = '2.3.3'
break;
}
return toolchainVersion;
},
getSysCfgVersionProjectSpec: () => {
return "1.14.0";
},
getCCSVersionProjectSpec: () => {
return "1210";
},
getTiClangVersionProjectSpec: () => {
return "2.1.2";
},
getGCCAarch64NoneVersionProjectSpec: () => {
return "9.2.1";
},
getGCCArmv7NoneVersionProjectSpec: () => {
return "10";
},
getTitleProjectSpec: (name) => {
let title = name.replace(/_/g, ' ');
// Title Case : Converts "hello world" to "Hello World" using regex
return title.replace(
/\w\S*/g,
function (s) {
return s.charAt(0).toUpperCase() + s.substr(1).toLowerCase();
}
);
}
}
function genProjectSpecExample(device) {
let example_file_list = require(`./device/project_${device}`).getExampleList();
for(example of example_file_list) {
let property = require(`../${example}`).getComponentProperty(device);
if(property.skipProjectSpec)
continue;
for(buildOption of property.buildOptionCombos) {
let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device);
let common_build_property = require(`./device/project_${device}`).getProperty();
let project = [];
let projectSpecOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
fs.mkdirSync(projectSpecOutPath, { recursive: true });
buildOption.isProjectSpecBuild = true;
build_property = require(`../${example}`).getComponentBuildProperty(buildOption);
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath);
project = _.merge({}, project, buildOption);
project = _.merge({}, project, build_property);
project = common.mergeCgtOptions(project, commonCgtOptions);
project = common.mergeCgtOptions(project, common_build_property);
project.dirPath = projectSpecOutPath;
let args = {
sdkName: "MOTOR_CONTROL_SDK_PATH",
sdkPath: common.path.relative(projectSpecOutPath, path.normalize(__dirname + "/..")),
relPath: common.path.relative(project.dirPath, "."),
project: project,
utils: utils,
cgtOptions: require(`./cgt/cgt_${project.cgt}`).getCgtOptions(buildOption.cpu, device),
linuxFwName: require(`./device/project_${device}`).getLinuxFwName(buildOption.cpu),
syscfg: {
device: require(`./device/project_${device}.js`).getSysCfgDevice(buildOption.board),
cpu: require(`./device/project_${device}.js`).getSysCfgCpu(buildOption.cpu),
pkg: require(`./device/project_${device}.js`).getSysCfgPkg(buildOption.board),
part: require(`./device/project_${device}.js`).getSysCfgPart(buildOption.board),
},
flashAddr: require(`./device/project_${device}.js`).getFlashAddr(),
};
common.convertTemplateToFile(
`.project/templates/projectspec_${project.type}.xdt`,
`${project.dirPath}/example.projectspec`,
args);
if("syscfgfile" in args.project) {
common.convertTemplateToFile(
`.project/templates/syscfg_c.rov.xs.xdt`,
`${project.dirPath}/syscfg_c.rov.xs`,
args);
}
if(args.project.skipMakefileCcsBootimageGen) {
// skip makefile_ccs_bootimage_gen
}
else{
common.convertTemplateToFile(
`.project/templates/makefile_ccs_bootimage_gen.xdt`,
`${project.dirPath}/makefile_ccs_bootimage_gen`,
args);
}
}
}
}
function genProjectSpecsDevice(device) {
genProjectSpecExample(device);
}
function cleanProjectSpecsDevice(device) {
let example_file_list = require(`./device/project_${device}`).getExampleList();
for(example of example_file_list) {
let property = require(`../${example}`).getComponentProperty(device);
if(property.skipProjectSpec)
continue;
for(buildOption of property.buildOptionCombos) {
let project = [];
let projectSpecOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
fs.mkdirSync(projectSpecOutPath, { recursive: true });
build_property = require(`../${example}`).getComponentBuildProperty(buildOption);
project = _.merge({}, project, property);
project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath);
project = _.merge({}, project, buildOption);
project = _.merge({}, project, build_property);
project.dirPath = projectSpecOutPath;
common.deleteFile(`${project.dirPath}/example.projectspec`);
common.deleteFile(`${project.dirPath}/makefile_ccs_bootimage_gen`);
common.deleteFile(`${project.dirPath}/syscfg_c.rov.xs`);
}
}
}
module.exports = {
genProjectSpecsDevice,
cleanProjectSpecsDevice,
utils,
}

88
.project/genSystemProject.js Normal file
View File

@ -0,0 +1,88 @@
const common = require(`./common.js`);
const fs = require('fs');
function genSystemProjectDevice(device) {
let example_file_list = require(`./device/project_${device}`).getExampleList();
for(example of example_file_list) {
example = require(`../${example}`);
if( ! example.getSystemProjects)
continue;
let property = example.getComponentProperty(device);
let systemProjects = example.getSystemProjects(device);
for ( project of systemProjects)
{
let outPath = `${property.dirPath}/${project.board}/system_${project.tag}`
project.device = device;
let args = {
sdkName: "MOTOR_CONTROL_SDK_PATH",
relPath: common.path.relative(outPath, "."),
project: project,
utils: require(`./genProjectSpec.js`).utils,
device: require(`./device/project_${device}.js`),
};
fs.mkdirSync(outPath, { recursive: true });
common.convertTemplateToFile(
".project/templates/makefile_system.xdt",
`${outPath}/makefile`,
args);
if( project.skipProjectSpec && project.skipProjectSpec === true)
continue;
common.convertTemplateToFile(
".project/templates/makefile_system_projectspec.xdt",
`${outPath}/makefile_projectspec`,
args);
common.convertTemplateToFile(
".project/templates/projectspec_system.xdt",
`${outPath}/system.projectspec`,
args);
common.convertTemplateToFile(
".project/templates/system.xml.xdt",
`${outPath}/system.xml`,
args);
common.convertTemplateToFile(
".project/templates/makefile_system_ccs_bootimage_gen.xdt",
`${outPath}/makefile_system_ccs_bootimage_gen`,
args);
}
}
}
function cleanSystemProjectDevice(device) {
let example_file_list = require(`./device/project_${device}`).getExampleList();
for(example of example_file_list) {
example = require(`../${example}`);
if( ! example.getSystemProjects)
continue;
let property = example.getComponentProperty(device);
let systemProjects = example.getSystemProjects(device);
for ( project of systemProjects)
{
let outPath = `${property.dirPath}/${project.board}/system_${project.tag}`
common.deleteFile(`${outPath}/makefile`);
common.deleteFile(`${outPath}/makefile_system_ccs_bootimage_gen`);
common.deleteFile(`${outPath}/makefile_projectspec`);
common.deleteFile(`${outPath}/system.projectspec`);
common.deleteFile(`${outPath}/system.xml`);
}
}
}
module.exports = {
genSystemProjectDevice,
cleanSystemProjectDevice,
}

190
.project/genTirex.js Normal file
View File

@ -0,0 +1,190 @@
const common = require(`./common.js`);
function genTirexSystemProjectContent(example, device) {
let deviceData = require(`./device/project_${device}.js`);
let property = require(`../${example}`).getComponentProperty(device);
let systemProjects = require(`../${example}`).getSystemProjects(device);
let folder_list = common.path.relative("examples", property.dirPath).split("/");
let tirex_content = {};
tirex_content.resourceType = `project.ccs`;
tirex_content.resourceClass = [ `example` ];
if(property.tirexResourceSubClass)
{
tirex_content.resourceSubClass = property.tirexResourceSubClass;
}
else
{
tirex_content.resourceSubClass = [ "example.general" ];
}
if(property.description)
{
tirex_content.description = property.description + " System project.";
}
else
{
tirex_content.description = common.getDefaultSystemProjectDescription(property.name);
}
tirex_content.name = property.name;
tirex_content.location = common.path.relative(".metadata/.tirex", `${property.dirPath}/${project.board}/system_${project.tag}`) + "/system.projectspec";
tirex_content.devtools = [ deviceData.getDevToolTirex(project.board) ];
tirex_content.kernel = [];
/* Temp fix: TIREX doesn't support multiple compiler for a project. System project doesn't need this. So keep it empty */
//tirex_content.compiler = [];
/* Temp fix: Push only one kernel as TIREX doesn't support a list yet. Remove when this is fixed */
tirex_content.kernel.push(project.projects[0].os);
for (subproject of project.projects)
{
/* Temp fix: see above */
//tirex_content.kernel.push(subproject.os);
/* Temp fix: see above */
//switch(subproject.cgt)
//{
// case "ti-arm-clang":
// tirex_content.compiler.push("ticlang");
// break;
// case "gcc-aarch64":
// tirex_content.compiler.push("gcc");
// break;
// case "gcc-armv7":
// tirex_content.compiler.push("gcc");
// break;
//}
}
/* Remove duplicates */
tirex_content.kernel = [...new Set(tirex_content.kernel)];
/* Temp fix: see above */
//tirex_content.compiler = [...new Set(tirex_content.compiler)];
tirex_content.subCategories = [ ...folder_list, "system_" + `${project.tag}`];
tirex_content.mainCategories = [[ `Examples`, `Development Tools` ]];
return (tirex_content);
}
function genTirexExampleContentList(example_file_list, device) {
let tirex_content_list = [];
let deviceData = require(`./device/project_${device}.js`);
let devtools_list = []; /* For userguide */
for(example of example_file_list) {
let property = require(`../${example}`).getComponentProperty(device);
if(property.skipUpdatingTirex || property.skipProjectSpec || property.isInternal)
continue;
for(buildOption of property.buildOptionCombos) {
let projectSpecOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption);
let folder_list = common.path.relative("examples", property.dirPath).split("/");
let tirex_content = {};
tirex_content.resourceType = `project.ccs`;
tirex_content.resourceClass = [ `example` ];
if(property.tirexResourceSubClass)
{
tirex_content.resourceSubClass = property.tirexResourceSubClass;
}
else
{
tirex_content.resourceSubClass = [ "example.general" ];
}
if(property.description)
{
tirex_content.description = property.description + " CPU is " + buildOption.cpu.toUpperCase() + " running " + buildOption.os.toUpperCase() + ".";
}
else
{
tirex_content.description = common.getDefaultProjectDescription(property.name, buildOption.cpu, buildOption.os);
}
tirex_content.name = property.name;
tirex_content.location = common.path.relative(".metadata/.tirex", projectSpecOutPath) + "/example.projectspec";
let devtools = deviceData.getDevToolTirex(buildOption.board);
tirex_content.devtools = [ devtools ];
devtools_list.push(devtools);
tirex_content.kernel = [];
tirex_content.compiler = [];
tirex_content.kernel.push(buildOption.os);
switch(buildOption.cgt)
{
case "ti-arm-clang":
tirex_content.compiler.push("ticlang");
break;
case "gcc-aarch64":
tirex_content.compiler.push("gcc");
break;
case "gcc-armv7":
tirex_content.compiler.push("gcc");
break;
case "ti-c6000":
tirex_content.compiler.push("ccs");
break;
}
tirex_content.subCategories = [ ...folder_list, `${buildOption.cpu}` + "_" +`${buildOption.os}`];
tirex_content.mainCategories = [[ `Examples`, `Development Tools` ]];
if (buildOption.os == "freertos-smp")
{
}
else
{
tirex_content_list.push(tirex_content);
}
}
}
for(example of example_file_list) {
let tirex_content = {};
example_js = require(`../${example}`);
if( ! example_js.getSystemProjects)
continue;
let property = require(`../${example}`).getComponentProperty(device);
if(property.skipUpdatingTirex || property.skipProjectSpec || property.isInternal)
continue;
let systemProjects = require(`../${example}`).getSystemProjects(device);
for(project of systemProjects) {
tirex_content = genTirexSystemProjectContent(example, device);
tirex_content_list.push(tirex_content);
}
}
let tirex_content = {};
tirex_content.resourceType = `web.page`
tirex_content.resourceClass = [ `document` ];
tirex_content.name = "User Guide";
tirex_content.location = `../../docs/api_guide_${device}/index.html`;
tirex_content.devtools = [ ...new Set(devtools_list) ];
tirex_content.mainCategories = [[ `Documents` ]];
tirex_content_list.push(tirex_content);
let args = {
tirex_content_list
};
common.convertTemplateToFile(
`.project/templates/tirex_content.xdt`,
`.metadata/.tirex/${device}.content.tirex.json`,
args);
}
function genTirexDevice(device) {
let example_file_list = require(`./device/project_${device}`).getExampleList();
genTirexExampleContentList(example_file_list, device);
}
module.exports = {
genTirexDevice
}

49
.project/project.js Normal file
View File

@ -0,0 +1,49 @@
const common = require("./common.js");
const yargs = require('yargs');
const argv = yargs
.usage('Usage: node $0 [OPTIONS]')
.option('device', {
alias: 's',
description: 'DEVICE to generate buildfiles',
type: 'string',
choices: [ "am64x", "am243x", "am263x", "am273x", "awr294x", "am62x" ],
default: "am64x",
array: true
})
.option('target', {
alias: 't',
description: 'Build target',
type: 'string',
choices: [ "development", "production", "clean" ],
default: "development",
array: false
})
.option('instrumentation', {
alias: 'i',
description: 'Code Coverage Instrumentation',
type: 'string',
choices: [ "enable", "disable" ],
default: "disable",
array: false
})
.help()
.alias('help', 'h')
.argv;
if(argv.target == "clean") {
for(device of argv.device) {
console.log(`Cleaning build files for ${device} ...`);
common.cleanBuildfiles(device);
}
console.log("Cleaning build files ... Done !!!")
}
else {
common.setGenBuildFilesMode(argv.target);
common.setInstrumentationMode(argv.instrumentation);
for(device of argv.device) {
console.log(`Generating build files for ${device} in ${argv.target} mode ...`);
common.genBuildfiles(device);
}
console.log("Generating build files ... Done !!!")
}

95
.project/templateCompiler.js Normal file
View File

@ -0,0 +1,95 @@
let _ = require("lodash");
// Returns the compiled source from the template source. The compiled source
// is in the form of a exports = templateFunction(argsObj); so it can be used
// just like a script would.
function compileTemplate(templateSource) {
templateSource = adaptSource(templateSource);
let compiled;
try {
compiled = _.template(templateSource, templateSettings).source;
} catch (err) {
if (!err.source || !_.startsWith(err.toString(), "SyntaxError")) {
throw err;
}
compiled = err;
}
compiled = "return " + compiled + " ;"
return compiled;
}
const templateSettings = {
// Setup _.template to work just like RTSC/XDC
// %%{\n
// stmt ...\n
// stmt ...\n
// %%}\n
// Multiple lines of script to be evaluated at this point.
// Some notes about the regex:
// %%\{ matches %%{
// ([\s\S]*?) captures whatever is next as few times as possible
// %%\} matches %%}
// \r?\n? matches a eol on any OS if there, this way the block doesn't
// include a newline in the output
evaluate: /%%\{([\s\S]*?)%%\}\r?\n?/g,
// text`script`text ... \n
// A line of text to be output by the template at this
// point. If present, all script between and including the
// `` quotes is replaced with its (textual) value in the
// current context.
interpolate: /`([\s\S]*?)`/g,
// This prevents lodash from generating a "with" statement to make the keys
// of the passed in object instantiated. Instead, "args" is the name of the
// object passed in
variable: "args",
};
function adaptSource(templateSource) {
// % script ... \n
// a single line of script evaluated by the template at
// this point
// Now, regex replace "% ..." with "%%{ ... %%}"
// Some notes about the regex:
// ^ matches a new line
// [\t\f ] matches any tab, form feed or space
// we use this because \s would match \r\n
// % matches %
// (?!%) excludes matching if a % follows the first $ (to exclude %%{ and %%})
// (.*?) matches and captures everything except the line terminator
// $ matches the line terminator
templateSource = templateSource.replace(/^[\t\f ]*%(?!%)(.*?)$/gm, "%%{$1\n%%}");
// Next, if we have adjacent escaped blocks (ie adjacent %%} and %%{),
// we shoudl combine them into one block. This allows people to escape
// adjacent lines using % but still have it be logically inline. If we
// don't do this, then _ will add a ; between the blocks.
templateSource = templateSource.replace(/%%}\r?\n%%{/g, "");
return templateSource;
}
function executeTemplate(templateSource, args) {
let compile = compileTemplate(templateSource);
let func1 = new Function(compile);
let func2 = func1();
return func2(args);
}
module.exports = {
executeTemplate,
}

74
.project/templates/am243x/common/linker_m4f.cmd.xdt Normal file
View File

@ -0,0 +1,74 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let heapSize = 32*1024;
/* if no options given use defaults */
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.heapSize)
heapSize = options.heapSize;
%%}
/* make sure below retain is there in your linker command file, it keeps the vector table in the final binary */
--retain="*(.vectors)"
/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
--stack_size=`stackSize`
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
--heap_size=`heapSize`
SECTIONS
{
/* This has the M4F entry point and vector table, this MUST be at 0x0 */
.vectors:{} palign(8) > M4F_VECS
.text: {} palign(8) > M4F_IRAM /* This is where code resides */
.bss: {} palign(8) > M4F_DRAM /* This is where uninitialized globals go */
RUN_START(__BSS_START)
RUN_END(__BSS_END)
.data: {} palign(8) > M4F_DRAM /* This is where initialized globals and static go */
.rodata: {} palign(8) > M4F_DRAM /* This is where const's go */
.sysmem: {} palign(8) > M4F_IRAM /* This is where the malloc heap goes */
.stack: {} palign(8) > M4F_IRAM /* This is where the main() stack goes */
/* Sections needed for C++ projects */
.ARM.exidx: {} palign(8) > M4F_IRAM /* Needed for C++ exception handling */
.init_array: {} palign(8) > M4F_IRAM /* Contains function pointers called before main */
.fini_array: {} palign(8) > M4F_IRAM /* Contains function pointers called after main */
/* General purpose user shared memory */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > IPC_VRING_MEM
}
MEMORY
{
M4F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000200
M4F_IRAM : ORIGIN = 0x00000200 , LENGTH = 0x0002FE00
M4F_DRAM : ORIGIN = 0x00030000 , LENGTH = 0x00010000
/* shared memories that are used by all cores */
/* On M4F,
* - By default MSMC RAM is not accessible to M4F, a RAT entry is needed to make it
* accessible on M4F
* - So make sure there is a RAT entry which has a 1:1 mapping from 0x70000000 to 0x70200000
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
IPC_VRING_MEM: ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}

342
.project/templates/am243x/common/linker_r5f.cmd.xdt Normal file
View File

@ -0,0 +1,342 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let heapSize = 32*1024;
/* with nested interrupts logic added, IRQ stack is only used minimally, instead
* SVC stack is used, hence IRQ stack size is less as compared to SVC stack
*/
let irqStackSize = 256;
let svcStackSize = 4*1024;
let fiqStackSize = 256;
let abortStackSize = 256;
let undefinedStackSize = 256;
let codeDataAddr = 0;
let codeDataSize = 0;
let nocacheDataSize = 0;
let codeDataAddrDdr = 0;
let codeDataSizeDdr = 0;
let codeDataAddrFlash = 0;
let codeDataSizeFlash = 0;
let nocacheDataAddr = 0;
let useDdr = false;
let useFlash = false;
let addrBase = 0;
let addrBaseDdr = 0;
let addrBaseFlash = 0;
let nocacheAddrBase = 0;
let isSingleCore = false;
/* Temp change till we support DDR - alloc all memory to single core
* as we don't plan to run code coverage for system project */
if(args.isInstrumentation)
{
isSingleCore = true;
}
let isIcssPktBufEnable = false;
if(options && options.isXip)
{
useFlash = true;
}
/* if no options given use defaults */
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.heapSize)
heapSize = options.heapSize;
if(options && options.irqStackSize)
irqStackSize = options.irqStackSize;
if(options && options.fiqStackSize)
fiqStackSize = options.fiqStackSize;
if(options && options.svcStackSize)
svcStackSize = options.svcStackSize;
if(options && options.abortStackSize)
abortStackSize = options.abortStackSize;
if(options && options.undefinedStackSize)
undefinedStackSize = options.undefinedStackSize;
if(options && options.isSingleCore)
isSingleCore = options.isSingleCore;
if(options && options.isIcssPktBufEnable)
isIcssPktBufEnable = options.isIcssPktBufEnable;
if(isSingleCore === true) {
codeDataSize = 0x40000 * 4;
codeDataSizeFlash = 0x80000;
codeDataSizeDdr = 0x1000000 * 4;
nocacheDataSize = 0x8000;
}
else {
codeDataSize = 0x40000;
codeDataSizeFlash = 0x80000;
codeDataSizeDdr = 0x1000000;
nocacheDataSize = 0x8000;
}
/* offset from top of codeDataAddrDdr where the code/data is actually placed,
the first codeDataOffsetDdr bytes are used for IPC in linux
*/
codeDataOffsetDdr = 0x100000;
if(args.project.isLinuxInSystem === true) {
addrBase = 0x70040000;
addrBaseDdr = 0xA0000000;
addrBaseFlash = 0x60100000;
useDdr = true;
} else {
addrBase = 0x70080000;
addrBaseFlash = 0x60100000;
nocacheAddrBase = 0x70060000;
}
if(isSingleCore === true) {
codeDataAddr = addrBase;
codeDataAddrDdr = addrBaseDdr;
codeDataAddrFlash = addrBaseFlash;
nocacheDataAddr = nocacheAddrBase;
}
else {
if(args.project.cpu == "r5fss0-0") {
codeDataAddr = addrBase + codeDataSize*0;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*0;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*0;
}
if(args.project.cpu == "r5fss0-1") {
codeDataAddr = addrBase + codeDataSize*1;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*1;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*1;
}
if(args.project.cpu == "r5fss1-0") {
codeDataAddr = addrBase + codeDataSize*2;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*2;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*2;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*2;
}
if(args.project.cpu == "r5fss1-1") {
codeDataAddr = addrBase + codeDataSize*3;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*3;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*3;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*3;
}
}
if(options && options.codeDataAddr)
codeDataAddr = options.codeDataAddr;
if(options && options.codeDataSize)
codeDataSize = options.codeDataSize;
if(options && options.codeDataAddrFlash)
codeDataAddrFlash = options.codeDataAddrFlash;
if(options && options.codeDataSizeFlash)
codeDataSizeFlash = options.codeDataSizeFlash;
%%}
/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
--stack_size=`stackSize`
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
--heap_size=`heapSize`
-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
/* This is the size of stack when R5 is in IRQ mode
* In NORTOS,
* - Here interrupt nesting is enabled
* - This is the stack used by ISRs registered as type IRQ
* In FreeRTOS,
* - Here interrupt nesting is disabled
* - This is stack that is used initally when a IRQ is received
* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
*/
__IRQ_STACK_SIZE = `irqStackSize`;
/* This is the size of stack when R5 is in IRQ mode
* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
*/
__FIQ_STACK_SIZE = `fiqStackSize`;
__SVC_STACK_SIZE = `svcStackSize`; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = `abortStackSize`; /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = `undefinedStackSize`; /* This is the size of stack when R5 is in UNDEF mode */
SECTIONS
{
/* This has the R5F entry point and vector table, this MUST be at 0x0 */
.vectors:{} palign(8) > R5F_VECS
/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
* i.e this cannot be placed in DDR
*/
GROUP {
.text.hwi: palign(8)
.text.cache: palign(8)
.text.mpu: palign(8)
.text.boot: palign(8)
.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
} > MSRAM
/* This is rest of code. This can be placed in DDR if DDR is available and needed */
GROUP {
.text: {} palign(8) /* This is where code resides */
.rodata: {} palign(8) /* This is where const's go */
% if(useDdr) {
} > DDR
% } else if(useFlash) {
} > FLASH
% } else {
} > MSRAM
% }
% if(useFlash) {
GROUP {
.rodata.cfg: {} palign(8) /* This is to keep the MPU config, Cache config and other consts */
} > MSRAM
% }
/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
% if(useDdr) {
/* This is the resource table used by linux to know where the IPC "VRINGs" are located */
.resource_table: {} palign(4096)
% }
.data: {} palign(8) /* This is where initialized globals and static go */
% if(useDdr) {
} > DDR
% } else {
} > MSRAM
% }
/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.bss: {} palign(8) /* This is where uninitialized globals go */
RUN_START(__BSS_START)
RUN_END(__BSS_END)
.sysmem: {} palign(8) /* This is where the malloc heap goes */
.stack: {} palign(8) /* This is where the main() stack goes */
% if(useDdr) {
} > DDR
% } else {
} > MSRAM
% }
% if(args.isInstrumentation) {
GROUP {
__llvm_prf_cnts: {} align(8)
RUN_START(__start___llvm_prf_cnts)
RUN_END(__stop___llvm_prf_cnts)
} > MSRAM
% }
/* This is where the stacks for different R5F modes go */
GROUP {
.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
RUN_START(__IRQ_STACK_START)
RUN_END(__IRQ_STACK_END)
.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
RUN_START(__FIQ_STACK_START)
RUN_END(__FIQ_STACK_END)
.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
RUN_START(__SVC_STACK_START)
RUN_END(__SVC_STACK_END)
.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
RUN_START(__ABORT_STACK_START)
RUN_END(__ABORT_STACK_END)
.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
RUN_START(__UNDEFINED_STACK_START)
RUN_END(__UNDEFINED_STACK_END)
% if(useDdr) {
} > DDR
% } else {
} > MSRAM
% }
/* Sections needed for C++ projects */
GROUP {
.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
.init_array: {} palign(8) /* Contains function pointers called before main */
.fini_array: {} palign(8) /* Contains function pointers called after main */
% if(useDdr) {
} > DDR
% } else if(useFlash) {
} > FLASH
% } else {
} > MSRAM
% }
% if (isIcssPktBufEnable) {
/* Packet buffer memory used by ICCS */
.bss.icss_emac_pktbuf_mem (NOLOAD): {} > ICSS_PKT_BUF_MEM
% }
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
% if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
% }
}
/*
NOTE: Below memory is reserved for DMSC usage
- During Boot till security handoff is complete
0x701E0000 - 0x701FFFFF (128KB)
- After "Security Handoff" is complete (i.e at run time)
0x701F4000 - 0x701FFFFF (48KB)
Security handoff is complete when this message is sent to the DMSC,
TISCI_MSG_SEC_HANDOVER
This should be sent once all cores are loaded and all application
specific firewall calls are setup.
*/
MEMORY
{
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
% if (isIcssPktBufEnable) {
/* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */
ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000
% }
% if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */
/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
NON_CACHE_MEM : ORIGIN = 0x`nocacheDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`nocacheDataSize.toString(16).toUpperCase()`
% }
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
MSRAM : ORIGIN = 0x`codeDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSize.toString(16).toUpperCase()`
/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
*/
FLASH : ORIGIN = 0x`codeDataAddrFlash.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSizeFlash.toString(16).toUpperCase()`
% if(useDdr) {
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
DDR : ORIGIN = 0x`(codeDataAddrDdr+codeDataOffsetDdr).toString(16).toUpperCase()` , LENGTH = 0x`(codeDataSizeDdr - codeDataOffsetDdr).toString(16).toUpperCase()`
% }
/* shared memory segments */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
% if(args.project.isLinuxInSystem) {
LINUX_IPC_SHM_MEM : ORIGIN = 0x`codeDataAddrDdr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataOffsetDdr.toString(16).toUpperCase()`
% }
}

3
.project/templates/am243x/common/pru/hexpru.cmd.xdt Normal file
View File

@ -0,0 +1,3 @@
-b
-map=pru_project.map
SECTIONS {.text}

87
.project/templates/am243x/common/pru/linker_pru0.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM243x_PRU0.cmd
*
* Example Linker command file for linking programs built with the TI-PRU-CGT
* on AM243x PRU0 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 12 KB PRU Instruction RAM */
PRU_IMEM : org = 0x00000000 len = 0x00003000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
* the second 4 KB for RTU0 and Tx_PRU0 */
PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
* RTU1 and Tx_PRU1; do not use for any Slice0 cores */
PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU0_DMEM_0 : org = 0x00001000 len = 0x00000800
TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
RTU0_DMEM_1 : org = 0x00003000 len = 0x00000800
TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > PRU_IMEM, PAGE 0
.stack > PRU_IMEM, PAGE 0
.bss > PRU0_DMEM_0, PAGE 1
/*
.cio > PRU0_DMEM_0, PAGE 1
.data > PRU0_DMEM_0, PAGE 1
.switch > PRU0_DMEM_0, PAGE 1
.sysmem > PRU0_DMEM_0, PAGE 1
.cinit > PRU0_DMEM_0, PAGE 1
.rodata > PRU0_DMEM_0, PAGE 1
.rofardata > PRU0_DMEM_0, PAGE 1
.farbss > PRU0_DMEM_0, PAGE 1
.fardata > PRU0_DMEM_0, PAGE 1
*/
}

88
.project/templates/am243x/common/pru/linker_pru1.cmd.xdt Normal file
View File

@ -0,0 +1,88 @@
/*
* AM243x_PRU1.cmd
*
* Example Linker command file for linking programs built with the C compiler
* on AM243x PRU1 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 12 KB PRU Instruction RAM */
PRU_IMEM : org = 0x00000000 len = 0x00003000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve
* the second 4 KB for RTU1 and Tx_PRU1 */
PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0,
* RTU0 and Tx_PRU0; do not use for any Slice1 cores */
PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800
TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800
RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800
TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > PRU_IMEM, PAGE 0
.stack > PRU_IMEM, PAGE 1
/* TODO: review if this should be PRU1_DMEM_1 */
.bss > PRU1_DMEM_0, PAGE 1
/*
.cio > PRU1_DMEM_0, PAGE 1
.data > PRU1_DMEM_0, PAGE 1
.switch > PRU1_DMEM_0, PAGE 1
.sysmem > PRU1_DMEM_0, PAGE 1
.cinit > PRU1_DMEM_0, PAGE 1
.rodata > PRU1_DMEM_0, PAGE 1
.rofardata > PRU1_DMEM_0, PAGE 1
.farbss > PRU1_DMEM_0, PAGE 1
.fardata > PRU1_DMEM_0, PAGE 1
*/
}

87
.project/templates/am243x/common/pru/linker_rtu_pru0.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM243x_RTU_PRU0.cmd
*
* Example Linker command file for linking programs built with the TI-PRU-CGT
* on AM243x RTU_PRU0 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 8 KB PRU Instruction RAM */
RTU_PRU_IMEM : org = 0x00000000 len = 0x00002000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
* the second 4 KB for RTU0 and Tx_PRU0 */
PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
* RTU1 and Tx_PRU1; do not use for any Slice0 cores */
PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800
TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800
TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > RTU_PRU_IMEM, PAGE 0
.stack > RTU_PRU_IMEM, PAGE 0
.bss > RTU_PRU0_DMEM_0, PAGE 1
/*
.cio > RTU_PRU0_DMEM_0, PAGE 1
.data > RTU_PRU0_DMEM_0, PAGE 1
.switch > RTU_PRU0_DMEM_0, PAGE 1
.sysmem > RTU_PRU0_DMEM_0, PAGE 1
.cinit > RTU_PRU0_DMEM_0, PAGE 1
.rodata > RTU_PRU0_DMEM_0, PAGE 1
.rofardata > RTU_PRU0_DMEM_0, PAGE 1
.farbss > RTU_PRU0_DMEM_0, PAGE 1
.fardata > RTU_PRU0_DMEM_0, PAGE 1
*/
}

87
.project/templates/am243x/common/pru/linker_rtu_pru1.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM243x_RTU_PRU1.cmd
*
* Example Linker command file for linking programs built with the C compiler
* on AM243x RTU_PRU1 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 8 KB PRU Instruction RAM */
RTU_PRU_IMEM : org = 0x00000000 len = 0x00002000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve
* the second 4 KB for RTU1 and Tx_PRU1 */
PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0,
* RTU0 and Tx_PRU0; do not use for any Slice1 cores */
PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800
TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800
RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800
TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > RTU_PRU_IMEM, PAGE 0
.stack > RTU_PRU_IMEM, PAGE 1
.bss > RTU_PRU1_DMEM_0, PAGE 1
/*
.cio > RTU_PRU1_DMEM_0, PAGE 1
.data > RTU_PRU1_DMEM_0, PAGE 1
.switch > RTU_PRU1_DMEM_0, PAGE 1
.sysmem > RTU_PRU1_DMEM_0, PAGE 1
.cinit > RTU_PRU1_DMEM_0, PAGE 1
.rodata > RTU_PRU1_DMEM_0, PAGE 1
.rofardata > RTU_PRU1_DMEM_0, PAGE 1
.farbss > RTU_PRU1_DMEM_0, PAGE 1
.fardata > RTU_PRU1_DMEM_0, PAGE 1
*/
}

87
.project/templates/am243x/common/pru/linker_tx_pru0.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM243x_TX_PRU0.cmd
*
* Example Linker command file for linking programs built with the TI-PRU-CGT
* on AM243x TX_PRU0 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 6 KB PRU Instruction RAM */
TX_PRU_IMEM : org = 0x00000000 len = 0x00001800
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
* the second 4 KB for RTU0 and Tx_PRU0 */
PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
* RTU1 and Tx_PRU1; do not use for any Slice0 cores */
PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800
TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800
TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > TX_PRU_IMEM, PAGE 0
.stack > TX_PRU_IMEM, PAGE 0
.bss > TX_PRU0_DMEM_0, PAGE 1
/*
.cio > TX_PRU0_DMEM_0, PAGE 1
.data > TX_PRU0_DMEM_0, PAGE 1
.switch > TX_PRU0_DMEM_0, PAGE 1
.sysmem > TX_PRU0_DMEM_0, PAGE 1
.cinit > TX_PRU0_DMEM_0, PAGE 1
.rodata > TX_PRU0_DMEM_0, PAGE 1
.rofardata > TX_PRU0_DMEM_0, PAGE 1
.farbss > TX_PRU0_DMEM_0, PAGE 1
.fardata > TX_PRU0_DMEM_0, PAGE 1
*/
}

87
.project/templates/am243x/common/pru/linker_tx_pru1.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM243x_TX_PRU1.cmd
*
* Example Linker command file for linking programs built with the C compiler
* on AM243x TX_PRU1 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 6 KB TX_PRU Instruction RAM */
TX_PRU_IMEM : org = 0x00000000 len = 0x00001800
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve
* the second 4 KB for RTU1 and Tx_PRU1 */
PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0,
* RTU0 and Tx_PRU0; do not use for any Slice1 cores */
PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800
TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800
RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800
TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of Tx_PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > TX_PRU_IMEM, PAGE 0
.stack > TX_PRU_IMEM, PAGE 1
.bss > TX_PRU1_DMEM_0, PAGE 1
/*
.cio > TX_PRU1_DMEM_0, PAGE 1
.data > TX_PRU1_DMEM_0, PAGE 1
.switch > TX_PRU1_DMEM_0, PAGE 1
.sysmem > TX_PRU1_DMEM_0, PAGE 1
.cinit > TX_PRU1_DMEM_0, PAGE 1
.rodata > TX_PRU1_DMEM_0, PAGE 1
.rofardata > TX_PRU1_DMEM_0, PAGE 1
.farbss > TX_PRU1_DMEM_0, PAGE 1
.fardata > TX_PRU1_DMEM_0, PAGE 1
*/
}

179
.project/templates/am243x/freertos/FreeRTOSConfig.h.xdt Normal file
View File

@ -0,0 +1,179 @@
%%{
let cpu = args.project.cpu;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef TI_FREERTOS_CONFIG_H
#define TI_FREERTOS_CONFIG_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <kernel/dpl/DebugP.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE
* FreeRTOS REFERENCE MANUAL.
*----------------------------------------------------------*/
/* Keep below as 1 if the most optimized task switching latency is needed.
* This disables tracing, logging, assert and other error checks.
* So unless every last cycle of task switching is important leave this as 0.
*
* This is not a FreeRTOS defined config and is defined by TI to quickly switch
* between optimized and not-so-optimized config
*/
#define configOPTIMIZE_FOR_LATENCY (0)
#define configUSE_PREEMPTION (1)
#define configUSE_PORT_OPTIMISED_TASK_SELECTION (`(cpu === "r5f") ? 0 : 1`)
#define configUSE_TICKLESS_IDLE (0)
#define configUSE_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationIdleHook(void) as the hook function */
#define configUSE_MALLOC_FAILED_HOOK (0)
#define configUSE_DAEMON_TASK_STARTUP_HOOK (0)
#define configUSE_TICK_HOOK (0)
#define configCPU_CLOCK_HZ (0) /* NOT USED in TI ports */
#define configSYSTICK_CLOCK_HZ (0) /* NOT USED in TI ports */
#define configTICK_RATE_HZ (1000)
#define configMAX_PRIORITIES (32)
#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */
#define configMAX_TASK_NAME_LEN (32)
#define configUSE_TRACE_FACILITY (1)
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configUSE_STATS_FORMATTING_FUNCTIONS (1)
#else
#define configUSE_STATS_FORMATTING_FUNCTIONS (0)
#endif
#define configUSE_16_BIT_TICKS (0)
#define configIDLE_SHOULD_YIELD (1)
#define configUSE_TASK_NOTIFICATIONS (1)
#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1)
#define configUSE_MUTEXES (1)
#define configUSE_RECURSIVE_MUTEXES (1)
#define configUSE_COUNTING_SEMAPHORES (1)
#define configUSE_ALTERNATIVE_API (0)
/* when = 1, Need to provied below,
* void vApplicationStackOverflowHook( TaskHandle_t xTask,
* char *pcTaskName );
*/
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configCHECK_FOR_STACK_OVERFLOW (1)
#else
#define configCHECK_FOR_STACK_OVERFLOW (0)
#endif
#define configQUEUE_REGISTRY_SIZE (32)
#define configUSE_QUEUE_SETS (0)
#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */
#define configUSE_NEWLIB_REENTRANT (0)
#define configENABLE_BACKWARD_COMPATIBILITY (1)
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4)
#define configSTACK_DEPTH_TYPE UBaseType_t
#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below,
*
* void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
* StackType_t **ppxTimerTaskStackBuffer,
* uint32_t *pulTimerTaskStackSize );
*
* void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
* StackType_t **ppxIdleTaskStackBuffer,
* uint32_t *pulIdleTaskStackSize );
*/
#define configSUPPORT_DYNAMIC_ALLOCATION (1)
#define configTOTAL_HEAP_SIZE (4*1024) /* not used when heap_3.c is the selected heap */
#define configAPPLICATION_ALLOCATED_HEAP (0)
/* run-time stats config */
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configGENERATE_RUN_TIME_STATS (1)
#else
#define configGENERATE_RUN_TIME_STATS (0)
#endif
void vPortConfigTimerForRunTimeStats();
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats()
uint32_t uiPortGetRunTimeCounterValue();
#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue()
/* co-routine related config */
#define configUSE_CO_ROUTINES (0)
#define configMAX_CO_ROUTINE_PRIORITIES (0)
/* timer related config */
#define configUSE_TIMERS (1)
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
#define configTIMER_QUEUE_LENGTH (16)
#define configTIMER_TASK_STACK_DEPTH (256)
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U)
#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configASSERT(x) DebugP_assert( (uint32_t)(x))
#endif
/* MPU aware FreeRTOS, not supported as TI */
#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0)
#define configTOTAL_MPU_REGIONS (0)
#undef configTEX_S_C_B_FLASH
#undef configTEX_S_C_B_SRAM
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0)
/* defines need for FreeRTOS+POSIX*/
#define configUSE_POSIX_ERRNO (1)
#define configUSE_APPLICATION_TASK_TAG (1)
/* include specific functions */
#define INCLUDE_vTaskDelete (1)
#define INCLUDE_vTaskDelay (1)
#define INCLUDE_vTaskSuspend (1)
#define INCLUDE_xTimerDelete (1)
#define INCLUDE_vSemaphoreDelete (1)
#define INCLUDE_xTimerPendFunctionCall (1)
#define INCLUDE_xTaskGetIdleTaskHandle (1)
#ifdef __cplusplus
}
#endif
#endif /* TI_FREERTOS_CONFIG_H */

98
.project/templates/am243x/freertos/main_freertos.c.xdt Normal file
View File

@ -0,0 +1,98 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let taskPri = "configMAX_PRIORITIES-1"
let entryFunction = "example_main";
if(options && options.entryFunction)
entryFunction = options.entryFunction;
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.taskPri)
taskPri = options.taskPri;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
#include "FreeRTOS.h"
#include "task.h"
#define MAIN_TASK_PRI (`taskPri`)
#define MAIN_TASK_SIZE (`stackSize`U/sizeof(configSTACK_DEPTH_TYPE))
StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
StaticTask_t gMainTaskObj;
TaskHandle_t gMainTask;
void `entryFunction`(void *args);
void freertos_main(void *args)
{
`entryFunction`(NULL);
vTaskDelete(NULL);
}
int main(void)
{
/* init SOC specific modules */
System_init();
Board_init();
/* This task is created at highest priority, it should create more tasks and then delete itself */
gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
"freertos_main", /* Text name for the task. This is to facilitate debugging only. */
MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
NULL, /* We are not using the task parameter. */
MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
gMainTaskStack, /* pointer to stack base */
&gMainTaskObj ); /* pointer to statically allocated task object memory */
configASSERT(gMainTask != NULL);
/* Start the scheduler to start the tasks executing. */
vTaskStartScheduler();
/* The following line should never be reached because vTaskStartScheduler()
will only return if there was not enough FreeRTOS heap memory available to
create the Idle and (if configured) Timer tasks. Heap management, and
techniques for trapping heap exhaustion, are described in the book text. */
DebugP_assertNoLog(0);
return 0;
}

186
.project/templates/am243x/gpio/board_gpio.c.xdt Normal file
View File

@ -0,0 +1,186 @@
%%{
let options = args.options;
exampleType = "input_interrupt";
if(options && options.exampleType)
exampleType = options.exampleType;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <drivers/hw_include/cslr_soc.h>
#include <drivers/gpio.h>
% if ( exampleType == "input_interrupt" ) {
#include <drivers/sciclient.h>
% }
#include "ti_drivers_config.h"
/*
* Board info
*/
% if ( exampleType == "input_interrupt" ) {
/* This is based on DMSC board config and core */
#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8)
#define BOARD_BUTTON_GPIO_SWITCH_NUM (5)
/** \brief bank interrupt source index base */
#define TISCI_BANK_SRC_IDX_BASE_GPIO0 (90U)
#define TISCI_BANK_SRC_IDX_BASE_GPIO1 (90U)
#define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (90U)
static void Sciclient_gpioIrqSet(void);
static void Sciclient_gpioIrqRelease(void);
void Board_gpioInit(void)
{
Sciclient_gpioIrqSet();
}
void Board_gpioDeinit(void)
{
Sciclient_gpioIrqRelease();
}
uint32_t Board_getGpioButtonIntrNum(void)
{
return (BOARD_BUTTON_GPIO_INTR_NUM);
}
uint32_t Board_getGpioButtonSwitchNum(void)
{
return (BOARD_BUTTON_GPIO_SWITCH_NUM);
}
static void Sciclient_gpioIrqSet(void)
{
int32_t retVal;
struct tisci_msg_rm_irq_set_req rmIrqReq;
struct tisci_msg_rm_irq_set_resp rmIrqResp;
/* For setting the IRQ for GPIO using sciclient APIs, we need to populate
* a structure, tisci_msg_rm_irq_set_req instantiated above. The definition
* of this struct and details regarding the struct members can be found in
* the tisci_rm_irq.h.
*/
/* Initialize all flags to zero since we'll be setting only a few */
rmIrqReq.valid_params = 0U;
/* Our request has a destination id, so enable the flag for DST ID */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
/* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
/* This is not a global event */
rmIrqReq.global_event = 0U;
/* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW.
* The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/.
* In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt,
* we need to choose the TISCI_DEV_GPIO1
*/
rmIrqReq.src_id = TISCI_DEV_GPIO1;
/* This is the interrupt source index within the GPIO peripheral */
rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);
/* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core.
* For a different core, the corresponding TISCI device id has to be provided */
rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
/* This is the output index of the interrupt router. This depends on the core and board configuration */
rmIrqReq.dst_host_irq = Board_getGpioButtonIntrNum();
/* Rest of the struct members are unused for GPIO interrupt */
rmIrqReq.ia_id = 0U;
rmIrqReq.vint = 0U;
rmIrqReq.vint_status_bit_index = 0U;
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
/* To set the interrupt we now invoke the Sciclient_rmIrqSet function which
* will find out the route to configure the interrupt and request DMSC to
* grant the resource
*/
retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
if(0 != retVal)
{
DebugP_log("[Error] Sciclient event config failed!!!\r\n");
DebugP_assert(FALSE);
}
return;
}
static void Sciclient_gpioIrqRelease(void)
{
int32_t retVal;
struct tisci_msg_rm_irq_release_req rmIrqReq;
/* For releasing the IRQ for GPIO using sciclient APIs, we need to populate
* a structure, tisci_msg_rm_irq_release_req instantiated above. The definition
* of this struct and details regarding the struct members can be found in
* the tisci_rm_irq.h. These are similar to the struct members for the set request
* used above.
*/
/* Initialize all flags to zero since we'll be setting only a few */
rmIrqReq.valid_params = 0U;
/* Our request has a destination id, so enable the flag for DST ID */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
/* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
/* This is not a global event */
rmIrqReq.global_event = 0U;
/* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW.
* The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/.
* In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt,
* we need to choose the TISCI_DEV_GPIO1
*/
rmIrqReq.src_id = TISCI_DEV_GPIO1;
/* This is the interrupt source index within the GPIO peripheral */
rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);
/* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core.
* For a different core, the corresponding TISCI device id has to be provided */
rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
/* This is the output index of the interrupt router. This depends on the core and board configuration */
rmIrqReq.dst_host_irq = Board_getGpioButtonIntrNum();
/* Rest of the struct members are unused for GPIO interrupt */
rmIrqReq.ia_id = 0U;
rmIrqReq.vint = 0U;
rmIrqReq.vint_status_bit_index = 0U;
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
/* To set the interrupt we now invoke the Sciclient_rmIrqRelease function which
* will find specifics about the route and request DMSC/SYSFW to relase/clear the interrupt
*/
retVal = Sciclient_rmIrqRelease(&rmIrqReq, SystemP_WAIT_FOREVER);
if(0 != retVal)
{
DebugP_log("[Error] Sciclient event reset failed!!!\r\n");
DebugP_assert(FALSE);
}
return;
}
% }

58
.project/templates/am243x/i2c/board_i2c.c.xdt Normal file
View File

@ -0,0 +1,58 @@
/*
* Copyright (C) 2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <drivers/hw_include/cslr_soc.h>
#include "ti_board_open_close.h"
/*
* Board info
*/
uint32_t Board_getnumLedPerGroup(void)
{
%if(args.project.board == "am243x-lp") {
/* For AM243x-LP board only 4 leds are connected */
uint32_t ledCount = 4U;
%}
%else {
uint32_t ledCount;
const LED_Attrs *attrs;
attrs = LED_getAttrs(CONFIG_LED0);
DebugP_assert(NULL != attrs);
/* For AM243x-EVM all LEDs are connected, so return
* the driver atrributes value of 8 */
ledCount = attrs->numLedPerGroup;
%}
return ledCount;
}

58
.project/templates/am243x/nortos/main_nortos.c.xdt Normal file
View File

@ -0,0 +1,58 @@
%%{
let options = args.options;
entryFunction = "example_main";
if(options && options.entryFunction)
entryFunction = options.entryFunction;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
void `entryFunction`(void *args);
int main(void)
{
System_init();
Board_init();
`entryFunction`(NULL);
Board_deinit();
System_deinit();
return 0;
}

266
.project/templates/am263x/common/linker_r5f.cmd.xdt Normal file
View File

@ -0,0 +1,266 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let heapSize = 32*1024;
/* with nested interrupts logic added, IRQ stack is only used minimally, instead
* SVC stack is used, hence IRQ stack size is less as compared to SVC stack
*/
let irqStackSize = 256;
let svcStackSize = 4*1024;
let fiqStackSize = 256;
let abortStackSize = 256;
let undefinedStackSize = 256;
let codeDataAddr = 0;
let codeDataSize = 0;
let codeDataAddrFlash = 0;
let codeDataSizeFlash = 0;
let useFlash = false;
let addrBase = 0;
let addrBaseFlash = 0;
let isSingleCore = false;
/* Temp change till we support DDR - alloc all memory to single core
* as we don't plan to run code coverage for system project */
if(args.isInstrumentation)
{
isSingleCore = true;
}
let isIcssPktBufEnable = false;
if(options && options.isXip)
{
useFlash = true;
}
/* if no options given use defaults */
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.heapSize)
heapSize = options.heapSize;
if(options && options.irqStackSize)
irqStackSize = options.irqStackSize;
if(options && options.fiqStackSize)
fiqStackSize = options.fiqStackSize;
if(options && options.svcStackSize)
svcStackSize = options.svcStackSize;
if(options && options.abortStackSize)
abortStackSize = options.abortStackSize;
if(options && options.undefinedStackSize)
undefinedStackSize = options.undefinedStackSize;
if(options && options.isSingleCore)
isSingleCore = options.isSingleCore;
if(options && options.isIcssPktBufEnable)
isIcssPktBufEnable = options.isIcssPktBufEnable;
if(isSingleCore === true) {
codeDataSize = 0x40000 * 4;
codeDataSizeFlash = 0x80000;
}
else {
codeDataSize = 0x40000;
codeDataSizeFlash = 0x80000;
}
/* MSS mailbox memory */
let ipcShmAddrBase = 0x72000000;
/* offset from top of codeDataAddrDdr where the code/data is actually placed,
the first codeDataOffsetDdr bytes are used for IPC in linux
*/
addrBase = 0x70040000;
addrBaseFlash = 0x60100000;
if(isSingleCore === true) {
codeDataAddr = addrBase;
codeDataAddrFlash = addrBaseFlash;
}
else {
if(args.project.cpu == "r5fss0-0") {
codeDataAddr = addrBase + codeDataSize*0;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*0;
}
if(args.project.cpu == "r5fss0-1") {
codeDataAddr = addrBase + codeDataSize*1;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*1;
}
if(args.project.cpu == "r5fss1-0") {
codeDataAddr = addrBase + codeDataSize*2;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*2;
}
if(args.project.cpu == "r5fss1-1") {
codeDataAddr = addrBase + codeDataSize*3;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*3;
}
}
if(options && options.codeDataAddr)
codeDataAddr = options.codeDataAddr;
if(options && options.codeDataSize)
codeDataSize = options.codeDataSize;
if(options && options.codeDataAddrFlash)
codeDataAddrFlash = options.codeDataAddrFlash;
if(options && options.codeDataSizeFlash)
codeDataSizeFlash = options.codeDataSizeFlash;
%%}
/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
--stack_size=`stackSize`
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
--heap_size=`heapSize`
-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
/* This is the size of stack when R5 is in IRQ mode
* In NORTOS,
* - Here interrupt nesting is enabled
* - This is the stack used by ISRs registered as type IRQ
* In FreeRTOS,
* - Here interrupt nesting is enabled
* - This is stack that is used initally when a IRQ is received
* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
*/
__IRQ_STACK_SIZE = `irqStackSize`;
/* This is the size of stack when R5 is in IRQ mode
* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
*/
__FIQ_STACK_SIZE = `fiqStackSize`;
__SVC_STACK_SIZE = `svcStackSize`; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = `abortStackSize`; /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = `undefinedStackSize`; /* This is the size of stack when R5 is in UNDEF mode */
SECTIONS
{
/* This has the R5F entry point and vector table, this MUST be at 0x0 */
.vectors:{} palign(8) > R5F_VECS
/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
* i.e this cannot be placed in DDR
*/
GROUP {
.text.hwi: palign(8)
.text.cache: palign(8)
.text.mpu: palign(8)
.text.boot: palign(8)
.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
} > OCRAM
/* This is rest of code. This can be placed in DDR if DDR is available and needed */
GROUP {
.text: {} palign(8) /* This is where code resides */
.rodata: {} palign(8) /* This is where const's go */
% if(useFlash) {
} > FLASH
% } else {
} > OCRAM
% }
/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.data: {} palign(8) /* This is where initialized globals and static go */
} > OCRAM
/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.bss: {} palign(8) /* This is where uninitialized globals go */
RUN_START(__BSS_START)
RUN_END(__BSS_END)
.sysmem: {} palign(8) /* This is where the malloc heap goes */
.stack: {} palign(8) /* This is where the main() stack goes */
} > OCRAM
% if(args.isInstrumentation) {
GROUP {
__llvm_prf_cnts: {} align(8)
RUN_START(__start___llvm_prf_cnts)
RUN_END(__stop___llvm_prf_cnts)
} > OCRAM
% }
/* This is where the stacks for different R5F modes go */
GROUP {
.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
RUN_START(__IRQ_STACK_START)
RUN_END(__IRQ_STACK_END)
.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
RUN_START(__FIQ_STACK_START)
RUN_END(__FIQ_STACK_END)
.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
RUN_START(__SVC_STACK_START)
RUN_END(__SVC_STACK_END)
.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
RUN_START(__ABORT_STACK_START)
RUN_END(__ABORT_STACK_END)
.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
RUN_START(__UNDEFINED_STACK_START)
RUN_END(__UNDEFINED_STACK_END)
} > OCRAM
/* Sections needed for C++ projects */
GROUP {
.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
.init_array: {} palign(8) /* Contains function pointers called before main */
.fini_array: {} palign(8) /* Contains function pointers called after main */
% if(useFlash) {
} > FLASH
% } else {
} > OCRAM
% }
% if (isIcssPktBufEnable) {
/* Packet buffer memory used by ICCS */
.bss.icss_emac_pktbuf_mem (NOLOAD): {} > ICSS_PKT_BUF_MEM
% }
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* this is used only when Secure IPC is enabled */
.bss.sipc_hsm_queue_mem (NOLOAD) : {} > MAILBOX_HSM
.bss.sipc_r5f_queue_mem (NOLOAD) : {} > MAILBOX_R5F
}
MEMORY
{
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB : ORIGIN = 0x00080000 , LENGTH = 0x00008000
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
OCRAM : ORIGIN = 0x`codeDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSize.toString(16).toUpperCase()`
/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
*/
FLASH : ORIGIN = 0x`codeDataAddrFlash.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSizeFlash.toString(16).toUpperCase()`
% if (isIcssPktBufEnable) {
/* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */
ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000
% }
/* shared memories that are used by RTOS/NORTOS cores */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x00004000
LOG_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x00004000
/* MSS mailbox memory is used as shared memory, we dont use bottom 32*12 bytes, since its used as SW queue by ipc_notify */
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x`ipcShmAddrBase.toString(16).toUpperCase()`, LENGTH = 0x3E80
MAILBOX_HSM: ORIGIN = 0x44000000 , LENGTH = 0x000003CE
MAILBOX_R5F: ORIGIN = 0x44000400 , LENGTH = 0x000003CE
}

3
.project/templates/am263x/common/pru/hexpru.cmd.xdt Normal file
View File

@ -0,0 +1,3 @@
-b
-map=pru_project.map
SECTIONS {.text}

67
.project/templates/am263x/common/pru/linker_pru0.cmd.xdt Normal file
View File

@ -0,0 +1,67 @@
/*
* AM263x_PRU0.cmd
*
* Example Linker command file for linking programs built with the TI-PRU-CGT
* on AM263x PRU0 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 12 KB PRU Instruction RAM */
PRU_IMEM : org = 0x00000000 len = 0x00003000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 0 */
PRU0_DMEM_0 : org = 0x00000000 len = 0x00002000
/* 8 KB PRU Data RAM 1 */
PRU0_DMEM_1 : org = 0x00002000 len = 0x00002000
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 32 KB Shared general purpose memory RAM with ECC, shared between PRU0 and PRU1 */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00008000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > PRU_IMEM, PAGE 0
.bss > PRU0_DMEM_0, PAGE 1
.stack > PRU0_DMEM_0, PAGE 1
}

67
.project/templates/am263x/common/pru/linker_pru1.cmd.xdt Normal file
View File

@ -0,0 +1,67 @@
/*
* AM263x_PRU1.cmd
*
* Example Linker command file for linking programs built with the C compiler
* on AM263x PRU1 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 12 KB PRU Instruction RAM */
PRU_IMEM : org = 0x00000000 len = 0x00003000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 1 */
PRU1_DMEM_1 : org = 0x00000000 len = 0x00002000
/* 8 KB PRU Data RAM 0 */
PRU1_DMEM_0 : org = 0x00002000 len = 0x00002000
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 32 KB Shared general purpose memory RAM with ECC, shared between PRU0 and PRU1 */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00008000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > PRU_IMEM, PAGE 0
.bss > PRU1_DMEM_0, PAGE 1
.stack > PRU1_DMEM_0, PAGE 1
}

179
.project/templates/am263x/freertos/FreeRTOSConfig.h.xdt Normal file
View File

@ -0,0 +1,179 @@
%%{
let cpu = args.project.cpu;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef TI_FREERTOS_CONFIG_H
#define TI_FREERTOS_CONFIG_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <kernel/dpl/DebugP.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE
* FreeRTOS REFERENCE MANUAL.
*----------------------------------------------------------*/
/* Keep below as 1 if the most optimized task switching latency is needed.
* This disables tracing, logging, assert and other error checks.
* So unless every last cycle of task switching is important leave this as 0.
*
* This is not a FreeRTOS defined config and is defined by TI to quickly switch
* between optimized and not-so-optimized config
*/
#define configOPTIMIZE_FOR_LATENCY (0)
#define configUSE_PREEMPTION (1)
#define configUSE_PORT_OPTIMISED_TASK_SELECTION (`(cpu === "r5f") ? 0 : 1`)
#define configUSE_TICKLESS_IDLE (0)
#define configUSE_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationIdleHook(void) as the hook function */
#define configUSE_MALLOC_FAILED_HOOK (0)
#define configUSE_DAEMON_TASK_STARTUP_HOOK (0)
#define configUSE_TICK_HOOK (0)
#define configCPU_CLOCK_HZ (0) /* NOT USED in TI ports */
#define configSYSTICK_CLOCK_HZ (0) /* NOT USED in TI ports */
#define configTICK_RATE_HZ (1000)
#define configMAX_PRIORITIES (32)
#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */
#define configMAX_TASK_NAME_LEN (32)
#define configUSE_TRACE_FACILITY (1)
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configUSE_STATS_FORMATTING_FUNCTIONS (1)
#else
#define configUSE_STATS_FORMATTING_FUNCTIONS (0)
#endif
#define configUSE_16_BIT_TICKS (0)
#define configIDLE_SHOULD_YIELD (1)
#define configUSE_TASK_NOTIFICATIONS (1)
#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1)
#define configUSE_MUTEXES (1)
#define configUSE_RECURSIVE_MUTEXES (1)
#define configUSE_COUNTING_SEMAPHORES (1)
#define configUSE_ALTERNATIVE_API (0)
/* when = 1, Need to provied below,
* void vApplicationStackOverflowHook( TaskHandle_t xTask,
* char *pcTaskName );
*/
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configCHECK_FOR_STACK_OVERFLOW (1)
#else
#define configCHECK_FOR_STACK_OVERFLOW (0)
#endif
#define configQUEUE_REGISTRY_SIZE (32)
#define configUSE_QUEUE_SETS (0)
#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */
#define configUSE_NEWLIB_REENTRANT (0)
#define configENABLE_BACKWARD_COMPATIBILITY (1)
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4)
#define configSTACK_DEPTH_TYPE UBaseType_t
#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below,
*
* void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
* StackType_t **ppxTimerTaskStackBuffer,
* uint32_t *pulTimerTaskStackSize );
*
* void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
* StackType_t **ppxIdleTaskStackBuffer,
* uint32_t *pulIdleTaskStackSize );
*/
#define configSUPPORT_DYNAMIC_ALLOCATION (1)
#define configTOTAL_HEAP_SIZE (4*1024) /* not used when heap_3.c is the selected heap */
#define configAPPLICATION_ALLOCATED_HEAP (0)
/* run-time stats config */
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configGENERATE_RUN_TIME_STATS (1)
#else
#define configGENERATE_RUN_TIME_STATS (0)
#endif
void vPortConfigTimerForRunTimeStats();
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats()
uint32_t uiPortGetRunTimeCounterValue();
#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue()
/* co-routine related config */
#define configUSE_CO_ROUTINES (0)
#define configMAX_CO_ROUTINE_PRIORITIES (0)
/* timer related config */
#define configUSE_TIMERS (1)
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
#define configTIMER_QUEUE_LENGTH (16)
#define configTIMER_TASK_STACK_DEPTH (256)
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U)
#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configASSERT(x) DebugP_assert( (uint32_t)(x))
#endif
/* MPU aware FreeRTOS, not supported as TI */
#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0)
#define configTOTAL_MPU_REGIONS (0)
#undef configTEX_S_C_B_FLASH
#undef configTEX_S_C_B_SRAM
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0)
/* defines need for FreeRTOS+POSIX*/
#define configUSE_POSIX_ERRNO (1)
#define configUSE_APPLICATION_TASK_TAG (1)
/* include specific functions */
#define INCLUDE_vTaskDelete (1)
#define INCLUDE_vTaskDelay (1)
#define INCLUDE_vTaskSuspend (1)
#define INCLUDE_xTimerDelete (1)
#define INCLUDE_vSemaphoreDelete (1)
#define INCLUDE_xTimerPendFunctionCall (1)
#define INCLUDE_xTaskGetIdleTaskHandle (1)
#ifdef __cplusplus
}
#endif
#endif /* TI_FREERTOS_CONFIG_H */

110
.project/templates/am263x/freertos/main_freertos.c.xdt Normal file
View File

@ -0,0 +1,110 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let taskPri = "configMAX_PRIORITIES-1"
let entryFunction = "example_main";
if(options && options.entryFunction)
entryFunction = options.entryFunction;
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.taskPri)
taskPri = options.taskPri;
if(options.license == "ti_commercial")
license = `/*
* TIFS-MCU Source File
*
* Example main.c
*
* Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
* ALL RIGHTS RESERVED
*/
`
else
license = `/*
* Copyright (C) 2018-2022 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`
%%}
`license`
#include <stdlib.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
#include "FreeRTOS.h"
#include "task.h"
#define MAIN_TASK_PRI (`taskPri`)
#define MAIN_TASK_SIZE (`stackSize`U/sizeof(configSTACK_DEPTH_TYPE))
StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
StaticTask_t gMainTaskObj;
TaskHandle_t gMainTask;
void `entryFunction`(void *args);
void freertos_main(void *args)
{
`entryFunction`(NULL);
vTaskDelete(NULL);
}
int main(void)
{
/* init SOC specific modules */
System_init();
Board_init();
/* This task is created at highest priority, it should create more tasks and then delete itself */
gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
"freertos_main", /* Text name for the task. This is to facilitate debugging only. */
MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
NULL, /* We are not using the task parameter. */
MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
gMainTaskStack, /* pointer to stack base */
&gMainTaskObj ); /* pointer to statically allocated task object memory */
configASSERT(gMainTask != NULL);
/* Start the scheduler to start the tasks executing. */
vTaskStartScheduler();
/* The following line should never be reached because vTaskStartScheduler()
will only return if there was not enough FreeRTOS heap memory available to
create the Idle and (if configured) Timer tasks. Heap management, and
techniques for trapping heap exhaustion, are described in the book text. */
DebugP_assertNoLog(0);
return 0;
}

77
.project/templates/am263x/gpio/board_gpio.c.xdt Normal file
View File

@ -0,0 +1,77 @@
%%{
let options = args.options;
exampleType = "input_interrupt";
if(options && options.exampleType)
exampleType = options.exampleType;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <drivers/hw_include/cslr_soc.h>
#include <drivers/gpio.h>
#include "ti_drivers_config.h"
/*
* Board info
*/
% if ( exampleType == "input_interrupt" ) {
/* This is based on DMSC board config and core */
%if(args.project.board == "am263x-lp") {
#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_GPIO_INTRXBAR_OUT_14)
#define BOARD_BUTTON_GPIO_SWITCH_NUM (4)
%}
%else {
#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_GPIO_INTRXBAR_OUT_14)
#define BOARD_BUTTON_GPIO_SWITCH_NUM (1)
%}
void Board_gpioInit(void)
{
}
void Board_gpioDeinit(void)
{
}
uint32_t Board_getGpioButtonIntrNum(void)
{
return (BOARD_BUTTON_GPIO_INTR_NUM);
}
uint32_t Board_getGpioButtonSwitchNum(void)
{
return (BOARD_BUTTON_GPIO_SWITCH_NUM);
}
% }

52
.project/templates/am263x/i2c/board_i2c.c.xdt Normal file
View File

@ -0,0 +1,52 @@
/*
* Copyright (C) 2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <drivers/hw_include/cslr_soc.h>
#include "ti_board_open_close.h"
/*
* Board info
*/
uint32_t Board_getnumLedPerGroup(void)
{
uint32_t ledCount;
const LED_Attrs *attrs;
attrs = LED_getAttrs(CONFIG_LED0);
DebugP_assert(NULL != attrs);
/* All LEDs are connected, so return
* the driver atrributes value of 8 */
ledCount = attrs->numLedPerGroup;
return (ledCount);
}

71
.project/templates/am263x/nortos/main_nortos.c.xdt Normal file
View File

@ -0,0 +1,71 @@
%%{
let options = args.options;
entryFunction = "example_main";
if(options && options.entryFunction)
entryFunction = options.entryFunction;
if(options.license == "ti_commercial")
license = `/*
* TIFS-MCU Source File
*
* Example main.c
*
* Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
* ALL RIGHTS RESERVED
*/
`
else
license = `/*
* Copyright (C) 2018-2022 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`
%%}
`license`
#include <stdlib.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
void `entryFunction`(void *args);
int main(void)
{
System_init();
Board_init();
`entryFunction`(NULL);
Board_deinit();
System_deinit();
return 0;
}

105
.project/templates/am64x/common/linker_a53.cmd.xdt Normal file
View File

@ -0,0 +1,105 @@
%%{
let options = args.options;
let stackSize = 0x10000;
let heapSize = 0x20000;
let isSingleCore = true;
let useDdr = true;
let addrBaseDdr = 0x80000000;
let codeDataSizeDdr = 0x1000000;
/* if no options given use defaults */
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.heapSize)
heapSize = options.heapSize;
if(isSingleCore == true) {
codeDataAddrDdr = addrBaseDdr;
codeDataSizeDdr = 0x1000000 * 2;
}
else {
if(args.project.cpu == "a53ss0-0")
{
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0;
}
if(args.project.cpu == "a53ss0-1")
{
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1;
}
}
if(options && options.addrBaseDdr)
addrBaseDdr = options.addrBaseDdr;
if(options && options.codeDataSizeDdr)
codeDataSizeDdr = options.codeDataSizeDdr;
%%}
ENTRY(_c_int00)
__TI_STACK_SIZE = `stackSize`;
__TI_HEAP_SIZE = `heapSize`;
MEMORY
{
% if(useDdr) {
DDR : ORIGIN = 0x`(codeDataAddrDdr).toString(16).toUpperCase()`, LENGTH = 0x`(codeDataSizeDdr).toString(16).toUpperCase()`
% }
/* shared memory segments */
/* On A53,
* - make sure there is a MMU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}
SECTIONS {
.vecs : {} > DDR
.text : {} > DDR
.rodata : {} > DDR
.data : ALIGN (8) {
__data_load__ = LOADADDR (.data);
__data_start__ = .;
*(.data)
*(.data*)
. = ALIGN (8);
__data_end__ = .;
} > DDR
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM
.bss : {
__bss_start__ = .;
*(.bss)
*(.bss.*)
. = ALIGN (8);
*(COMMON)
__bss_end__ = .;
. = ALIGN (8);
} > DDR
.heap (NOLOAD) : {
__heap_start__ = .;
KEEP(*(.heap))
. = . + __TI_HEAP_SIZE;
__heap_end__ = .;
} > DDR
.stack (NOLOAD) : ALIGN(16) {
__TI_STACK_BASE = .;
KEEP(*(.stack))
. = . + __TI_STACK_SIZE;
} > DDR
}

108
.project/templates/am64x/common/linker_a53_smp.cmd.xdt Normal file
View File

@ -0,0 +1,108 @@
%%{
let options = args.options;
let stackSize = 0x10000;
let heapSize = 0x20000;
let isSingleCore = true;
let useDdr = true;
let addrBaseDdr = 0x80000000;
let codeDataSizeDdr = 0x1000000;
/* if no options given use defaults */
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.heapSize)
heapSize = options.heapSize;
if(isSingleCore == true) {
codeDataAddrDdr = addrBaseDdr;
codeDataSizeDdr = 0x1000000 * 2;
}
else {
if(args.project.cpu == "a53ss0-0")
{
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0;
}
if(args.project.cpu == "a53ss0-1")
{
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1;
}
}
if(options && options.addrBaseDdr)
addrBaseDdr = options.addrBaseDdr;
if(options && options.codeDataSizeDdr)
codeDataSizeDdr = options.codeDataSizeDdr;
%%}
ENTRY(_c_int00)
__TI_STACK_SIZE = `stackSize`;
__TI_HEAP_SIZE = `heapSize`;
MEMORY
{
% if(useDdr) {
DDR : ORIGIN = 0x`(codeDataAddrDdr).toString(16).toUpperCase()`, LENGTH = 0x`(codeDataSizeDdr).toString(16).toUpperCase()`
% }
/* shared memory segments */
/* On A53,
* - make sure there is a MMU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}
SECTIONS {
.vecs : {} > DDR
.text : {} > DDR
.rodata : {} > DDR
.data : ALIGN (8) {
__data_load__ = LOADADDR (.data);
__data_start__ = .;
*(.data)
*(.data*)
. = ALIGN (8);
__data_end__ = .;
} > DDR
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM
.bss : {
__bss_start__ = .;
*(.bss)
*(.bss.*)
. = ALIGN (8);
*(COMMON)
__bss_end__ = .;
. = ALIGN (8);
} > DDR
.heap (NOLOAD) : {
__heap_start__ = .;
KEEP(*(.heap))
. = . + __TI_HEAP_SIZE;
__heap_end__ = .;
} > DDR
.stack (NOLOAD) : ALIGN(16) {
__TI_STACK_BASE = .;
KEEP(*(.stack))
. = . + __TI_STACK_SIZE;
__TI_STACK_BASE1 = .;
KEEP(*(.stack))
. = . + __TI_STACK_SIZE;
} > DDR
}

95
.project/templates/am64x/common/linker_m4f.cmd.xdt Normal file
View File

@ -0,0 +1,95 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let heapSize = 32*1024;
/* if no options given use defaults */
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.heapSize)
heapSize = options.heapSize;
%%}
/* make sure below retain is there in your linker command file, it keeps the vector table in the final binary */
--retain="*(.vectors)"
/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
--stack_size=`stackSize`
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
--heap_size=`heapSize`
SECTIONS
{
/* This has the M4F entry point and vector table, this MUST be at 0x0 */
.vectors:{} palign(8) > M4F_VECS
.text: {} palign(8) > M4F_IRAM /* This is where code resides */
.bss: {} palign(8) > M4F_DRAM /* This is where uninitialized globals go */
RUN_START(__BSS_START)
RUN_END(__BSS_END)
.data: {} palign(8) > M4F_DRAM /* This is where initialized globals and static go */
.rodata: {} palign(8) > M4F_DRAM /* This is where const's go */
.sysmem: {} palign(8) > M4F_IRAM /* This is where the malloc heap goes */
.stack: {} palign(8) > M4F_IRAM /* This is where the main() stack goes */
% if(args.project.isLinuxInSystem === true) {
GROUP {
/* This is the resource table used by linux to know where the IPC "VRINGs" are located */
.resource_table: {} palign(4096)
} > DDR_0
% }
/* Sections needed for C++ projects */
.ARM.exidx: {} palign(8) > M4F_IRAM /* Needed for C++ exception handling */
.init_array: {} palign(8) > M4F_IRAM /* Contains function pointers called before main */
.fini_array: {} palign(8) > M4F_IRAM /* Contains function pointers called after main */
/* General purpose user shared memory */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > IPC_VRING_MEM
}
MEMORY
{
M4F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000200
M4F_IRAM : ORIGIN = 0x00000200 , LENGTH = 0x0002FE00
M4F_DRAM : ORIGIN = 0x00030000 , LENGTH = 0x00010000
% if(args.project.isLinuxInSystem === true) {
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with R5F's
*/
/* Resource table must be placed at the start of DDR_0 when M4 core is early booting with Linux */
DDR_0 : ORIGIN = 0xA4100000 , LENGTH = 0x1000
% }
% if(args.project.isLinuxInSystem) {
USER_SHM_MEM : ORIGIN = 0xA5000000, LENGTH = 0x80
LOG_SHM_MEM : ORIGIN = 0xA5000000 + 0x80, LENGTH = 0x00004000 - 0x80
IPC_VRING_MEM : ORIGIN = 0xA5004000, LENGTH = 0x0000C000
% } else {
/* shared memories that are used by all cores */
/* On M4F,
* - By default MSMC RAM is not accessible to M4F, a RAT entry is needed to make it
* accessible on M4F
* - So make sure there is a RAT entry which has a 1:1 mapping from 0x70000000 to 0x70200000
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
IPC_VRING_MEM: ORIGIN = 0x701D4000, LENGTH = 0x0000C000
% }
}

362
.project/templates/am64x/common/linker_r5f.cmd.xdt Normal file
View File

@ -0,0 +1,362 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let heapSize = 32*1024;
/* with nested interrupts logic added, IRQ stack is only used minimally, instead
* SVC stack is used, hence IRQ stack size is less as compared to SVC stack
*/
let irqStackSize = 256;
let svcStackSize = 4*1024;
let fiqStackSize = 256;
let abortStackSize = 256;
let undefinedStackSize = 256;
let codeDataAddr = 0;
let codeDataSize = 0;
let nocacheDataSize = 0;
let codeDataAddrDdr = 0;
let codeDataSizeDdr = 0;
let codeDataAddrFlash = 0;
let codeDataSizeFlash = 0;
let nocacheDataAddr = 0;
let useDdr = false;
let usetcma = false;
let resourceTableSizeDdr = 0;
let useFlash = false;
let addrBase = 0;
let addrBaseDdr = 0;
let addrBaseFlash = 0;
let nocacheAddrBase = 0;
let isSingleCore = false;
/* Temp change till we support DDR - alloc all memory to single core
* as we don't plan to run code coverage for system project */
if(args.isInstrumentation)
{
isSingleCore = true;
}
let isIcssPktBufEnable = false;
if(options && options.isXip)
{
useFlash = true;
}
/* if no options given use defaults */
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.heapSize)
heapSize = options.heapSize;
if(options && options.irqStackSize)
irqStackSize = options.irqStackSize;
if(options && options.fiqStackSize)
fiqStackSize = options.fiqStackSize;
if(options && options.svcStackSize)
svcStackSize = options.svcStackSize;
if(options && options.abortStackSize)
abortStackSize = options.abortStackSize;
if(options && options.undefinedStackSize)
undefinedStackSize = options.undefinedStackSize;
if(options && options.isSingleCore)
isSingleCore = options.isSingleCore;
if(options && options.isIcssPktBufEnable)
isIcssPktBufEnable = options.isIcssPktBufEnable;
if(isSingleCore === true) {
codeDataSize = 0x40000 * 4;
codeDataSizeFlash = 0x80000;
codeDataSizeDdr = 0x1000000 * 4;
nocacheDataSize = 0x8000;
resourceTableSizeDdr = 0x1000 * 4;
}
else {
codeDataSize = 0x40000;
codeDataSizeFlash = 0x80000;
codeDataSizeDdr = 0x1000000;
nocacheDataSize = 0x8000;
resourceTableSizeDdr = 0x1000;
}
/* offset from top of codeDataAddrDdr where the code/data is actually placed,
the first codeDataOffsetDdr bytes are used for IPC in linux
*/
codeDataOffsetDdr = 0x100000;
if(args.project.isLinuxInSystem === true) {
addrBase = 0x70080000;
addrBaseDdr = 0xA0000000;
addrBaseFlash = 0x60100000;
useDdr = true;
usetcma = true;
} else {
addrBase = 0x70080000;
addrBaseFlash = 0x60100000;
nocacheAddrBase = 0x70060000;
}
if(isSingleCore === true) {
codeDataAddr = addrBase;
codeDataAddrDdr = addrBaseDdr;
codeDataAddrFlash = addrBaseFlash;
nocacheDataAddr = nocacheAddrBase;
}
else {
if(args.project.cpu == "r5fss0-0") {
codeDataAddr = addrBase + codeDataSize*0;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*0;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*0;
}
if(args.project.cpu == "r5fss0-1") {
codeDataAddr = addrBase + codeDataSize*1;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*1;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*1;
}
if(args.project.cpu == "r5fss1-0") {
codeDataAddr = addrBase + codeDataSize*2;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*2;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*2;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*2;
}
if(args.project.cpu == "r5fss1-1") {
codeDataAddr = addrBase + codeDataSize*3;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*3;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*3;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*3;
}
}
if(options && options.codeDataAddr)
codeDataAddr = options.codeDataAddr;
if(options && options.codeDataSize)
codeDataSize = options.codeDataSize;
if(options && options.codeDataAddrFlash)
codeDataAddrFlash = options.codeDataAddrFlash;
if(options && options.codeDataSizeFlash)
codeDataSizeFlash = options.codeDataSizeFlash;
%%}
/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
--stack_size=`stackSize`
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
--heap_size=`heapSize`
-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
/* This is the size of stack when R5 is in IRQ mode
* In NORTOS,
* - Here interrupt nesting is enabled
* - This is the stack used by ISRs registered as type IRQ
* In FreeRTOS,
* - Here interrupt nesting is disabled
* - This is stack that is used initally when a IRQ is received
* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
*/
__IRQ_STACK_SIZE = `irqStackSize`;
/* This is the size of stack when R5 is in IRQ mode
* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
*/
__FIQ_STACK_SIZE = `fiqStackSize`;
__SVC_STACK_SIZE = `svcStackSize`; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = `abortStackSize`; /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = `undefinedStackSize`; /* This is the size of stack when R5 is in UNDEF mode */
SECTIONS
{
/* This has the R5F entry point and vector table, this MUST be at 0x0 */
.vectors:{} palign(8) > R5F_VECS
/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
* i.e this cannot be placed in DDR
*/
GROUP {
.text.hwi: palign(8)
.text.cache: palign(8)
.text.mpu: palign(8)
.text.boot: palign(8)
.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
% if(usetcma) {
} > R5F_TCMA
% } else {
} > MSRAM
% }
% if(useFlash) {
GROUP {
.rodata.cfg: {} palign(8) /* This is to keep the MPU config, Cache config and other consts */
} > MSRAM
% }
/* This is rest of code. This can be placed in DDR if DDR is available and needed */
GROUP {
.text: {} palign(8) /* This is where code resides */
.rodata: {} palign(8) /* This is where const's go */
% if(useDdr) {
} > DDR_1
% } else if(useFlash) {
} > FLASH
% } else {
} > MSRAM
% }
% if (useDdr) {
GROUP {
/* This is the resource table used by linux to know where the IPC "VRINGs" are located */
.resource_table: {} palign(4096)
} > DDR_0
% }
/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.data: {} palign(8) /* This is where initialized globals and static go */
% if(useDdr) {
} > DDR_1
% } else {
} > MSRAM
% }
/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.bss: {} palign(8) /* This is where uninitialized globals go */
RUN_START(__BSS_START)
RUN_END(__BSS_END)
.sysmem: {} palign(8) /* This is where the malloc heap goes */
.stack: {} palign(8) /* This is where the main() stack goes */
% if(useDdr) {
} > DDR_1
% } else {
} > MSRAM
% }
% if(args.isInstrumentation) {
GROUP {
__llvm_prf_cnts: {} align(8)
RUN_START(__start___llvm_prf_cnts)
RUN_END(__stop___llvm_prf_cnts)
} > MSRAM
% }
/* This is where the stacks for different R5F modes go */
GROUP {
.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
RUN_START(__IRQ_STACK_START)
RUN_END(__IRQ_STACK_END)
.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
RUN_START(__FIQ_STACK_START)
RUN_END(__FIQ_STACK_END)
.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
RUN_START(__SVC_STACK_START)
RUN_END(__SVC_STACK_END)
.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
RUN_START(__ABORT_STACK_START)
RUN_END(__ABORT_STACK_END)
.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
RUN_START(__UNDEFINED_STACK_START)
RUN_END(__UNDEFINED_STACK_END)
% if(useDdr) {
} > DDR_1
% } else {
} > MSRAM
% }
/* Sections needed for C++ projects */
GROUP {
.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
.init_array: {} palign(8) /* Contains function pointers called before main */
.fini_array: {} palign(8) /* Contains function pointers called after main */
% if(useDdr) {
} > DDR_1
% } else if(useFlash) {
} > FLASH
% } else {
} > MSRAM
% }
% if (isIcssPktBufEnable) {
/* Packet buffer memory used by ICCS */
.bss.icss_emac_pktbuf_mem (NOLOAD): {} > ICSS_PKT_BUF_MEM
% }
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
% if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
% }
}
/*
NOTE: Below memory is reserved for DMSC usage
- During Boot till security handoff is complete
0x701E0000 - 0x701FFFFF (128KB)
- After "Security Handoff" is complete (i.e at run time)
0x701F4000 - 0x701FFFFF (48KB)
Security handoff is complete when this message is sent to the DMSC,
TISCI_MSG_SEC_HANDOVER
This should be sent once all cores are loaded and all application
specific firewall calls are setup.
*/
MEMORY
{
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
% if (isIcssPktBufEnable) {
/* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */
ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000
% }
% if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */
/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
NON_CACHE_MEM : ORIGIN = 0x`nocacheDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`nocacheDataSize.toString(16).toUpperCase()`
% }
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
MSRAM : ORIGIN = 0x`codeDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSize.toString(16).toUpperCase()`
/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
*/
FLASH : ORIGIN = 0x`codeDataAddrFlash.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSizeFlash.toString(16).toUpperCase()`
% if(useDdr) {
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
/* Resource table must be placed at the start of DDR_0 when R5 cores are early booting with Linux */
DDR_0 : ORIGIN = 0x`(codeDataAddrDdr+codeDataOffsetDdr).toString(16).toUpperCase()` , LENGTH = 0x`(resourceTableSizeDdr).toString(16).toUpperCase()`
DDR_1 : ORIGIN = 0x`(codeDataAddrDdr+codeDataOffsetDdr+resourceTableSizeDdr).toString(16).toUpperCase()` , LENGTH = 0x`(codeDataSizeDdr - codeDataOffsetDdr -resourceTableSizeDdr).toString(16).toUpperCase()`
% }
/* shared memory segments */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
% if(args.project.isLinuxInSystem) {
USER_SHM_MEM : ORIGIN = 0xA5000000, LENGTH = 0x80
LOG_SHM_MEM : ORIGIN = 0xA5000000 + 0x80, LENGTH = 0x00004000 - 0x80
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0xA5004000, LENGTH = 0x0000C000
% } else {
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
% }
% if(args.project.isLinuxInSystem) {
LINUX_IPC_SHM_MEM : ORIGIN = 0x`codeDataAddrDdr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataOffsetDdr.toString(16).toUpperCase()`
% }
}

396
.project/templates/am64x/common/linker_r5f_gcc.cmd.xdt Normal file
View File

@ -0,0 +1,396 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let heapSize = 32*1024;
/* with nested interrupts logic added, IRQ stack is only used minimally, instead
* SVC stack is used, hence IRQ stack size is less as compared to SVC stack
*/
let irqStackSize = 256;
let svcStackSize = 4*1024;
let fiqStackSize = 256;
let abortStackSize = 256;
let undefinedStackSize = 256;
let codeDataAddr = 0;
let codeDataSize = 0;
let nocacheDataSize = 0;
let codeDataAddrDdr = 0;
let codeDataSizeDdr = 0;
let codeDataAddrFlash = 0;
let codeDataSizeFlash = 0;
let nocacheDataAddr = 0;
let useDdr = false;
let useFlash = false;
let addrBase = 0;
let addrBaseDdr = 0;
let addrBaseFlash = 0;
let nocacheAddrBase = 0;
let isSingleCore = false;
/* Temp change till we support DDR - alloc all memory to single core
* as we don't plan to run code coverage for system project */
if(args.isInstrumentation)
{
isSingleCore = true;
}
let isIcssPktBufEnable = false;
if(options && options.isXip)
{
useFlash = true;
}
/* if no options given use defaults */
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.heapSize)
heapSize = options.heapSize;
if(options && options.irqStackSize)
irqStackSize = options.irqStackSize;
if(options && options.fiqStackSize)
fiqStackSize = options.fiqStackSize;
if(options && options.svcStackSize)
svcStackSize = options.svcStackSize;
if(options && options.abortStackSize)
abortStackSize = options.abortStackSize;
if(options && options.undefinedStackSize)
undefinedStackSize = options.undefinedStackSize;
if(options && options.isSingleCore)
isSingleCore = options.isSingleCore;
if(options && options.isIcssPktBufEnable)
isIcssPktBufEnable = options.isIcssPktBufEnable;
if(isSingleCore === true) {
codeDataSize = 0x40000 * 4;
codeDataSizeFlash = 0x80000;
codeDataSizeDdr = 0x1000000 * 4;
nocacheDataSize = 0x8000;
}
else {
codeDataSize = 0x40000;
codeDataSizeFlash = 0x80000;
codeDataSizeDdr = 0x1000000;
nocacheDataSize = 0x8000;
}
/* offset from top of codeDataAddrDdr where the code/data is actually placed,
the first codeDataOffsetDdr bytes are used for IPC in linux
*/
codeDataOffsetDdr = 0x100000;
if(args.project.isLinuxInSystem === true) {
addrBase = 0x70080000;
addrBaseDdr = 0xA0000000;
addrBaseFlash = 0x60100000;
useDdr = true;
} else {
addrBase = 0x70080000;
addrBaseFlash = 0x60100000;
nocacheAddrBase = 0x70060000;
}
if(isSingleCore === true) {
codeDataAddr = addrBase;
codeDataAddrDdr = addrBaseDdr;
codeDataAddrFlash = addrBaseFlash;
nocacheDataAddr = nocacheAddrBase;
}
else {
if(args.project.cpu == "r5fss0-0") {
codeDataAddr = addrBase + codeDataSize*0;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*0;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*0;
}
if(args.project.cpu == "r5fss0-1") {
codeDataAddr = addrBase + codeDataSize*1;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*1;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*1;
}
if(args.project.cpu == "r5fss1-0") {
codeDataAddr = addrBase + codeDataSize*2;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*2;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*2;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*2;
}
if(args.project.cpu == "r5fss1-1") {
codeDataAddr = addrBase + codeDataSize*3;
codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*3;
codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*3;
nocacheDataAddr = nocacheAddrBase + nocacheDataSize*3;
}
}
if(options && options.codeDataAddr)
codeDataAddr = options.codeDataAddr;
if(options && options.codeDataSize)
codeDataSize = options.codeDataSize;
if(options && options.codeDataAddrFlash)
codeDataAddrFlash = options.codeDataAddrFlash;
if(options && options.codeDataSizeFlash)
codeDataSizeFlash = options.codeDataSizeFlash;
%%}
/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
__TI_STACK_SIZE = 16384;
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
__TI_HEAP_SIZE = 32768;
ENTRY(_vectors) /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
/* This is the size of stack when R5 is in IRQ mode
* In NORTOS,
* - Here interrupt nesting is disabled as of now
* - This is the stack used by ISRs registered as type IRQ
* In FreeRTOS,
* - Here interrupt nesting is enabled
* - This is stack that is used initally when a IRQ is received
* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
*/
__IRQ_STACK_SIZE = `irqStackSize`;
/* This is the size of stack when R5 is in IRQ mode
* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
*/
__FIQ_STACK_SIZE = `fiqStackSize`;
__SVC_STACK_SIZE = `svcStackSize`; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = `abortStackSize`; /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = `undefinedStackSize`; /* This is the size of stack when R5 is in UNDEF mode */
/*
NOTE: Below memory is reserved for DMSC usage
- During Boot till security handoff is complete
0x701E0000 - 0x701FFFFF (128KB)
- After "Security Handoff" is complete (i.e at run time)
0x701F4000 - 0x701FFFFF (48KB)
Security handoff is complete when this message is sent to the DMSC,
TISCI_MSG_SEC_HANDOVER
This should be sent once all cores are loaded and all application
specific firewall calls are setup.
*/
MEMORY
{
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
% if (isIcssPktBufEnable) {
/* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */
ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000
% }
% if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */
/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
NON_CACHE_MEM : ORIGIN = 0x`nocacheDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`nocacheDataSize.toString(16).toUpperCase()`
% }
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
MSRAM : ORIGIN = 0x`codeDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSize.toString(16).toUpperCase()`
/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
*/
FLASH : ORIGIN = 0x`codeDataAddrFlash.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSizeFlash.toString(16).toUpperCase()`
% if(useDdr) {
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
DDR : ORIGIN = 0x`(codeDataAddrDdr+codeDataOffsetDdr).toString(16).toUpperCase()` , LENGTH = 0x`(codeDataSizeDdr - codeDataOffsetDdr).toString(16).toUpperCase()`
% }
/* shared memory segments */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
% if(args.project.isLinuxInSystem) {
LINUX_IPC_SHM_MEM : ORIGIN = 0x`codeDataAddrDdr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataOffsetDdr.toString(16).toUpperCase()`
% }
}
SECTIONS
{
/* This has the R5F entry point and vector table, this MUST be at 0x0 */
.vectors : ALIGN (8) {} > R5F_VECS
/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
* i.e this cannot be placed in DDR
*/
.text.hwi : ALIGN (8) {} > MSRAM
.text.cache : ALIGN (8) {} > MSRAM
.text.mpu : ALIGN (8) {} > MSRAM
.text.boot : ALIGN (8) {} > MSRAM
.text:abort : ALIGN (8) {} > MSRAM /* this helps in loading symbols when using XIP mode */
/* This is rest of code. This can be placed in DDR if DDR is available and needed */
% if(useDdr) {
.text : ALIGN (8) {} > DDR /* This is where code resides */
.rodata : ALIGN (8) {} > DDR /* This is where const's go */
% } else if(useFlash) {
.text : ALIGN (8) {} > FLASH /* This is where code resides */
.rodata : ALIGN (8) {} > FLASH /* This is where const's go */
% } else {
.text : ALIGN (8) {} > MSRAM /* This is where code resides */
.rodata : ALIGN (8) {} > MSRAM /* This is where const's go */
% }
/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
% if(useDdr) {
/* This is the resource table used by linux to know where the IPC "VRINGs" are located */
.resource_table : ALIGN (4096) {} > DDR
.data : ALIGN (8) {} > DDR /* This is where initialized globals and static go */
% } else {
.data : ALIGN (8) {} > MSRAM /* This is where initialized globals and static go */
% }
/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
% if(useDdr) {
.bss : {
__bss_start__ = .;
__BSS_START = .;
*(.bss)
*(.bss.*)
. = ALIGN (8);
__BSS_END = .;
__bss_end__ = .;
. = ALIGN (8);
} > DDR
% } else {
.bss : {
__bss_start__ = .;
__BSS_START = .;
*(.bss)
*(.bss.*)
. = ALIGN (8);
__BSS_END = .;
__bss_end__ = .;
. = ALIGN (8);
} > MSRAM
% }
/* This is where the stacks for different R5F modes go */
% if(useDdr) {
.irqstack : ALIGN(16) {
__IRQ_STACK_START = .;
. = . + __IRQ_STACK_SIZE;
__IRQ_STACK_END = .;
. = ALIGN (8);
} > DDR
.fiqstack : ALIGN(16) {
__FIQ_STACK_START = .;
. = . + __FIQ_STACK_SIZE;
__FIQ_STACK_END = .;
} > DDR
.svcstack : ALIGN(16) {
__SVC_STACK_START = .;
. = . + __SVC_STACK_SIZE;
__SVC_STACK_END = .;
} > DDR
.abortstack : ALIGN(16) {
__ABORT_STACK_START = .;
. = . + __ABORT_STACK_SIZE;
__ABORT_STACK_END = .;
} > DDR
.undefinedstack : ALIGN(16) {
__UNDEFINED_STACK_START = .;
. = . + __UNDEFINED_STACK_SIZE;
__UNDEFINED_STACK_END = .;
} > DDR
.heap (NOLOAD) : {
end = .;
KEEP(*(.heap))
. = . + __TI_HEAP_SIZE;
} > DDR
.stack (NOLOAD) : ALIGN(16) {
__TI_STACK_BASE = .;
KEEP(*(.stack))
. = . + __TI_STACK_SIZE;
__STACK_END = .;
} > DDR
% } else {
.irqstack : ALIGN(16) {
__IRQ_STACK_START = .;
. = . + __IRQ_STACK_SIZE;
__IRQ_STACK_END = .;
. = ALIGN (8);
} > MSRAM
.fiqstack : ALIGN(16) {
__FIQ_STACK_START = .;
. = . + __FIQ_STACK_SIZE;
__FIQ_STACK_END = .;
} > MSRAM
.svcstack : ALIGN(16) {
__SVC_STACK_START = .;
. = . + __SVC_STACK_SIZE;
__SVC_STACK_END = .;
} > MSRAM
.abortstack : ALIGN(16) {
__ABORT_STACK_START = .;
. = . + __ABORT_STACK_SIZE;
__ABORT_STACK_END = .;
} > MSRAM
.undefinedstack : ALIGN(16) {
__UNDEFINED_STACK_START = .;
. = . + __UNDEFINED_STACK_SIZE;
__UNDEFINED_STACK_END = .;
} > MSRAM
.heap (NOLOAD) : {
end = .;
KEEP(*(.heap))
. = . + __TI_HEAP_SIZE;
} > MSRAM
.stack (NOLOAD) : ALIGN(16) {
__TI_STACK_BASE = .;
KEEP(*(.stack))
. = . + __TI_STACK_SIZE;
__STACK_END = .;
} > MSRAM
% }
/* Sections needed for C++ projects */
% if(useDdr) {
.ARM.exidx : ALIGN (8) {} > DDR /* Needed for C++ exception handling */
.init_array : ALIGN (8) {} > DDR /* Contains function pointers called before main */
.fini_array : ALIGN (8) {} > DDR /* Contains function pointers called after main */
% } else if(useFlash) {
.ARM.exidx : ALIGN (8) {} > FLASH /* Needed for C++ exception handling */
.init_array : ALIGN (8) {} > FLASH /* Contains function pointers called before main */
.fini_array : ALIGN (8) {} > FLASH /* Contains function pointers called after main */
% } else {
.ARM.exidx : ALIGN (8) {} > MSRAM /* Needed for C++ exception handling */
.init_array : ALIGN (8) {} > MSRAM /* Contains function pointers called before main */
.fini_array : ALIGN (8) {} > MSRAM /* Contains function pointers called after main */
% }
% if (isIcssPktBufEnable) {
/* Packet buffer memory used by ICCS */
.bss.icss_emac_pktbuf_mem (NOLOAD) : { KEEP(*(.bss.icss_emac_pktbuf_mem)) } > ICSS_PKT_BUF_MEM
% }
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM
% if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : { KEEP(*(.bss.nocache)) } > NON_CACHE_MEM
% }
}

3
.project/templates/am64x/common/pru/hexpru.cmd.xdt Normal file
View File

@ -0,0 +1,3 @@
-b
-map=pru_project.map
SECTIONS {.text}

87
.project/templates/am64x/common/pru/linker_pru0.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM64x_PRU0.cmd
*
* Example Linker command file for linking programs built with the TI-PRU-CGT
* on AM64x PRU0 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 12 KB PRU Instruction RAM */
PRU_IMEM : org = 0x00000000 len = 0x00003000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
* the second 4 KB for RTU0 and Tx_PRU0 */
PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
* RTU1 and Tx_PRU1; do not use for any Slice0 cores */
PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800
TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800
TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > PRU_IMEM, PAGE 0
.stack > PRU_IMEM, PAGE 0
.bss > PRU0_DMEM_0, PAGE 1
/*
.cio > PRU0_DMEM_0, PAGE 1
.data > PRU0_DMEM_0, PAGE 1
.switch > PRU0_DMEM_0, PAGE 1
.sysmem > PRU0_DMEM_0, PAGE 1
.cinit > PRU0_DMEM_0, PAGE 1
.rodata > PRU0_DMEM_0, PAGE 1
.rofardata > PRU0_DMEM_0, PAGE 1
.farbss > PRU0_DMEM_0, PAGE 1
.fardata > PRU0_DMEM_0, PAGE 1
*/
}

88
.project/templates/am64x/common/pru/linker_pru1.cmd.xdt Normal file
View File

@ -0,0 +1,88 @@
/*
* AM64x_PRU1.cmd
*
* Example Linker command file for linking programs built with the C compiler
* on AM64x PRU1 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 12 KB PRU Instruction RAM */
PRU_IMEM : org = 0x00000000 len = 0x00003000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve
* the second 4 KB for RTU1 and Tx_PRU1 */
PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0,
* RTU0 and Tx_PRU0; do not use for any Slice1 cores */
PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800
TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800
RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800
TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > PRU_IMEM, PAGE 0
.stack > PRU_IMEM, PAGE 1
/* TODO: review if this should be PRU1_DMEM_1 */
.bss > PRU1_DMEM_0, PAGE 1
/*
.cio > PRU1_DMEM_0, PAGE 1
.data > PRU1_DMEM_0, PAGE 1
.switch > PRU1_DMEM_0, PAGE 1
.sysmem > PRU1_DMEM_0, PAGE 1
.cinit > PRU1_DMEM_0, PAGE 1
.rodata > PRU1_DMEM_0, PAGE 1
.rofardata > PRU1_DMEM_0, PAGE 1
.farbss > PRU1_DMEM_0, PAGE 1
.fardata > PRU1_DMEM_0, PAGE 1
*/
}

87
.project/templates/am64x/common/pru/linker_rtu_pru0.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM64x_RTU_PRU0.cmd
*
* Example Linker command file for linking programs built with the TI-PRU-CGT
* on AM64x RTU_PRU0 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 8 KB PRU Instruction RAM */
RTU_PRU_IMEM : org = 0x00000000 len = 0x00002000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
* the second 4 KB for RTU0 and Tx_PRU0 */
PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
* RTU1 and Tx_PRU1; do not use for any Slice0 cores */
PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800
TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800
TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > RTU_PRU_IMEM, PAGE 0
.stack > RTU_PRU_IMEM, PAGE 0
.bss > RTU_PRU0_DMEM_0, PAGE 1
/*
.cio > RTU_PRU0_DMEM_0, PAGE 1
.data > RTU_PRU0_DMEM_0, PAGE 1
.switch > RTU_PRU0_DMEM_0, PAGE 1
.sysmem > RTU_PRU0_DMEM_0, PAGE 1
.cinit > RTU_PRU0_DMEM_0, PAGE 1
.rodata > RTU_PRU0_DMEM_0, PAGE 1
.rofardata > RTU_PRU0_DMEM_0, PAGE 1
.farbss > RTU_PRU0_DMEM_0, PAGE 1
.fardata > RTU_PRU0_DMEM_0, PAGE 1
*/
}

87
.project/templates/am64x/common/pru/linker_rtu_pru1.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM64x_RTU_PRU1.cmd
*
* Example Linker command file for linking programs built with the C compiler
* on AM64x RTU_PRU1 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 8 KB PRU Instruction RAM */
RTU_PRU_IMEM : org = 0x00000000 len = 0x00002000
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve
* the second 4 KB for RTU1 and Tx_PRU1 */
PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0,
* RTU0 and Tx_PRU0; do not use for any Slice1 cores */
PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800
TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800
RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800
TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > RTU_PRU_IMEM, PAGE 0
.stack > RTU_PRU_IMEM, PAGE 1
.bss > RTU_PRU1_DMEM_0, PAGE 1
/*
.cio > RTU_PRU1_DMEM_0, PAGE 1
.data > RTU_PRU1_DMEM_0, PAGE 1
.switch > RTU_PRU1_DMEM_0, PAGE 1
.sysmem > RTU_PRU1_DMEM_0, PAGE 1
.cinit > RTU_PRU1_DMEM_0, PAGE 1
.rodata > RTU_PRU1_DMEM_0, PAGE 1
.rofardata > RTU_PRU1_DMEM_0, PAGE 1
.farbss > RTU_PRU1_DMEM_0, PAGE 1
.fardata > RTU_PRU1_DMEM_0, PAGE 1
*/
}

87
.project/templates/am64x/common/pru/linker_tx_pru0.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM64x_TX_PRU0.cmd
*
* Example Linker command file for linking programs built with the TI-PRU-CGT
* on AM64x TX_PRU0 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 6 KB PRU Instruction RAM */
TX_PRU_IMEM : org = 0x00000000 len = 0x00001800
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
* the second 4 KB for RTU0 and Tx_PRU0 */
PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
* RTU1 and Tx_PRU1; do not use for any Slice0 cores */
PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800
TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800
TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > TX_PRU_IMEM, PAGE 0
.stack > TX_PRU_IMEM, PAGE 0
.bss > TX_PRU0_DMEM_0, PAGE 1
/*
.cio > TX_PRU0_DMEM_0, PAGE 1
.data > TX_PRU0_DMEM_0, PAGE 1
.switch > TX_PRU0_DMEM_0, PAGE 1
.sysmem > TX_PRU0_DMEM_0, PAGE 1
.cinit > TX_PRU0_DMEM_0, PAGE 1
.rodata > TX_PRU0_DMEM_0, PAGE 1
.rofardata > TX_PRU0_DMEM_0, PAGE 1
.farbss > TX_PRU0_DMEM_0, PAGE 1
.fardata > TX_PRU0_DMEM_0, PAGE 1
*/
}

87
.project/templates/am64x/common/pru/linker_tx_pru1.cmd.xdt Normal file
View File

@ -0,0 +1,87 @@
/*
* AM64x_TX_PRU1.cmd
*
* Example Linker command file for linking programs built with the C compiler
* on AM64x TX_PRU1 cores
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Specify the System Memory Map */
MEMORY
{
PAGE 0:
/* 6 KB TX_PRU Instruction RAM */
TX_PRU_IMEM : org = 0x00000000 len = 0x00001800
PAGE 1:
/* Data RAMs */
/* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve
* the second 4 KB for RTU1 and Tx_PRU1 */
PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000
/* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0,
* RTU0 and Tx_PRU0; do not use for any Slice1 cores */
PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000
/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
* split equally between the corresponding RTU and Tx_PRU cores in
* each slice */
RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800
TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800
RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800
TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800
PAGE 2:
/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
/* 64 KB PRU Shared RAM */
PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
}
/* Specify the sections allocation into memory */
SECTIONS {
/* Forces _c_int00 to the start of Tx_PRU IRAM. Not necessary when loading
an ELF file, but useful when loading a binary */
.text:_c_int00* > 0x0, PAGE 0
.text > TX_PRU_IMEM, PAGE 0
.stack > TX_PRU_IMEM, PAGE 1
.bss > TX_PRU1_DMEM_0, PAGE 1
/*
.cio > TX_PRU1_DMEM_0, PAGE 1
.data > TX_PRU1_DMEM_0, PAGE 1
.switch > TX_PRU1_DMEM_0, PAGE 1
.sysmem > TX_PRU1_DMEM_0, PAGE 1
.cinit > TX_PRU1_DMEM_0, PAGE 1
.rodata > TX_PRU1_DMEM_0, PAGE 1
.rofardata > TX_PRU1_DMEM_0, PAGE 1
.farbss > TX_PRU1_DMEM_0, PAGE 1
.fardata > TX_PRU1_DMEM_0, PAGE 1
*/
}

180
.project/templates/am64x/freertos/FreeRTOSConfig.h.xdt Normal file
View File

@ -0,0 +1,180 @@
%%{
let cpu = args.project.cpu;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef TI_FREERTOS_CONFIG_H
#define TI_FREERTOS_CONFIG_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <kernel/dpl/DebugP.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE
* FreeRTOS REFERENCE MANUAL.
*----------------------------------------------------------*/
/* Keep below as 1 if the most optimized task switching latency is needed.
* This disables tracing, logging, assert and other error checks.
* So unless every last cycle of task switching is important leave this as 0.
*
* This is not a FreeRTOS defined config and is defined by TI to quickly switch
* between optimized and not-so-optimized config
*/
#define configOPTIMIZE_FOR_LATENCY (0)
#define configUSE_PREEMPTION (1)
#define configUSE_PORT_OPTIMISED_TASK_SELECTION (`(cpu === "r5f") ? 0 : 1`)
#define configUSE_TICKLESS_IDLE (0)
#define configUSE_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationIdleHook(void) as the hook function */
#define configUSE_MALLOC_FAILED_HOOK (0)
#define configUSE_DAEMON_TASK_STARTUP_HOOK (0)
#define configUSE_TICK_HOOK (0)
#define configCPU_CLOCK_HZ (0) /* NOT USED in TI ports */
#define configSYSTICK_CLOCK_HZ (0) /* NOT USED in TI ports */
#define configTICK_RATE_HZ (1000)
#define configMAX_PRIORITIES (32)
#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */
#define configMAX_TASK_NAME_LEN (32)
#define configUSE_TRACE_FACILITY (1)
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configUSE_STATS_FORMATTING_FUNCTIONS (1)
#else
#define configUSE_STATS_FORMATTING_FUNCTIONS (0)
#endif
#define configUSE_16_BIT_TICKS (0)
#define configIDLE_SHOULD_YIELD (1)
#define configUSE_TASK_NOTIFICATIONS (1)
#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1)
#define configUSE_MUTEXES (1)
#define configUSE_RECURSIVE_MUTEXES (1)
#define configUSE_COUNTING_SEMAPHORES (1)
#define configUSE_ALTERNATIVE_API (0)
/* when = 1, Need to provied below,
* void vApplicationStackOverflowHook( TaskHandle_t xTask,
* char *pcTaskName );
*/
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configCHECK_FOR_STACK_OVERFLOW (1)
#else
#define configCHECK_FOR_STACK_OVERFLOW (0)
#endif
#define configQUEUE_REGISTRY_SIZE (32)
#define configUSE_QUEUE_SETS (0)
#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */
#define configUSE_NEWLIB_REENTRANT (0)
#define configENABLE_BACKWARD_COMPATIBILITY (1)
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4)
#define configSTACK_DEPTH_TYPE UBaseType_t
#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below,
*
* void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
* StackType_t **ppxTimerTaskStackBuffer,
* uint32_t *pulTimerTaskStackSize );
*
* void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
* StackType_t **ppxIdleTaskStackBuffer,
* uint32_t *pulIdleTaskStackSize );
*/
#define configSUPPORT_DYNAMIC_ALLOCATION (1)
#define configTOTAL_HEAP_SIZE (4*1024) /* not used when heap_3.c is the selected heap */
#define configAPPLICATION_ALLOCATED_HEAP (0)
/* run-time stats config */
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configGENERATE_RUN_TIME_STATS (1)
#else
#define configGENERATE_RUN_TIME_STATS (0)
#endif
void vPortConfigTimerForRunTimeStats();
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats()
uint32_t uiPortGetRunTimeCounterValue();
#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue()
/* co-routine related config */
#define configUSE_CO_ROUTINES (0)
#define configMAX_CO_ROUTINE_PRIORITIES (0)
/* timer related config */
#define configUSE_TIMERS (1)
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
#define configTIMER_QUEUE_LENGTH (16)
#define configTIMER_TASK_STACK_DEPTH (256)
/* used in M4F, not applicable in R5F, C66x, A53 */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U)
#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configASSERT(x) DebugP_assert( (uint32_t)(x))
#endif
/* MPU aware FreeRTOS, not supported as TI */
#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0)
#define configTOTAL_MPU_REGIONS (0)
#undef configTEX_S_C_B_FLASH
#undef configTEX_S_C_B_SRAM
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0)
/* defines need for FreeRTOS+POSIX*/
#define configUSE_POSIX_ERRNO (1)
#define configUSE_APPLICATION_TASK_TAG (1)
/* include specific functions */
#define INCLUDE_vTaskDelete (1)
#define INCLUDE_vTaskDelay (1)
#define INCLUDE_vTaskSuspend (1)
#define INCLUDE_xTimerDelete (1)
#define INCLUDE_vSemaphoreDelete (1)
#define INCLUDE_xTimerPendFunctionCall (1)
#define INCLUDE_xTaskGetIdleTaskHandle (1)
#ifdef __cplusplus
}
#endif
#endif /* TI_FREERTOS_CONFIG_H */

184
.project/templates/am64x/freertos/FreeRTOSConfig_smp.h.xdt Normal file
View File

@ -0,0 +1,184 @@
%%{
let cpu = args.project.cpu;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef TI_FREERTOS_CONFIG_H
#define TI_FREERTOS_CONFIG_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <kernel/dpl/DebugP.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE
* FreeRTOS REFERENCE MANUAL.
*----------------------------------------------------------*/
/* Keep below as 1 if the most optimized task switching latency is needed.
* This disables tracing, logging, assert and other error checks.
* So unless every last cycle of task switching is important leave this as 0.
*
* This is not a FreeRTOS defined config and is defined by TI to quickly switch
* between optimized and not-so-optimized config
*/
#define configOPTIMIZE_FOR_LATENCY (0)
#define configUSE_PREEMPTION (1)
#define configUSE_PORT_OPTIMISED_TASK_SELECTION (0)
#define configNUM_CORES (2)
#define configRUN_MULTIPLE_PRIORITIES (1)
#define configUSE_CORE_AFFINITY (1)
#define configUSE_TICKLESS_IDLE (0)
#define configUSE_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationIdleHook(void) as the hook function */
#define configUSE_MINIMAL_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationMinimalIdleHook(void) as the hook function */
#define configUSE_MALLOC_FAILED_HOOK (0)
#define configUSE_DAEMON_TASK_STARTUP_HOOK (0)
#define configUSE_TICK_HOOK (0)
#define configCPU_CLOCK_HZ (0) /* NOT USED in TI ports */
#define configSYSTICK_CLOCK_HZ (0) /* NOT USED in TI ports */
#define configTICK_RATE_HZ (1000)
#define configMAX_PRIORITIES (32)
#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */
#define configMAX_TASK_NAME_LEN (32)
#define configUSE_TRACE_FACILITY (1)
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configUSE_STATS_FORMATTING_FUNCTIONS (1)
#else
#define configUSE_STATS_FORMATTING_FUNCTIONS (0)
#endif
#define configUSE_16_BIT_TICKS (0)
#define configIDLE_SHOULD_YIELD (1)
#define configUSE_TASK_NOTIFICATIONS (1)
#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1)
#define configUSE_MUTEXES (1)
#define configUSE_RECURSIVE_MUTEXES (1)
#define configUSE_COUNTING_SEMAPHORES (1)
#define configUSE_ALTERNATIVE_API (0)
/* when = 1, Need to provied below,
* void vApplicationStackOverflowHook( TaskHandle_t xTask,
* char *pcTaskName );
*/
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configCHECK_FOR_STACK_OVERFLOW (1)
#else
#define configCHECK_FOR_STACK_OVERFLOW (0)
#endif
#define configQUEUE_REGISTRY_SIZE (32)
#define configUSE_QUEUE_SETS (0)
#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */
#define configUSE_NEWLIB_REENTRANT (0)
#define configENABLE_BACKWARD_COMPATIBILITY (1)
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4)
#define configSTACK_DEPTH_TYPE UBaseType_t
#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below,
*
* void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
* StackType_t **ppxTimerTaskStackBuffer,
* uint32_t *pulTimerTaskStackSize );
*
* void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
* StackType_t **ppxIdleTaskStackBuffer,
* uint32_t *pulIdleTaskStackSize );
*/
#define configSUPPORT_DYNAMIC_ALLOCATION (1)
#define configTOTAL_HEAP_SIZE (0xF80000) /* not used when heap_3.c is the selected heap */
#define configAPPLICATION_ALLOCATED_HEAP (0)
/* run-time stats config */
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configGENERATE_RUN_TIME_STATS (1)
#else
#define configGENERATE_RUN_TIME_STATS (0)
#endif
void vPortConfigTimerForRunTimeStats();
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats()
uint32_t uiPortGetRunTimeCounterValue();
#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue()
/* co-routine related config */
#define configUSE_CO_ROUTINES (0)
#define configMAX_CO_ROUTINE_PRIORITIES (0)
/* timer related config */
#define configUSE_TIMERS (1)
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
#define configTIMER_QUEUE_LENGTH (16)
#define configTIMER_TASK_STACK_DEPTH (256)
/* used in M4F, not applicable in R5F, C66x, A53 */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U)
#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
#if (configOPTIMIZE_FOR_LATENCY==0)
#define configASSERT(x) DebugP_assert( (uint32_t)(x))
#endif
/* MPU aware FreeRTOS, not supported as TI */
#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0)
#define configTOTAL_MPU_REGIONS (0)
#undef configTEX_S_C_B_FLASH
#undef configTEX_S_C_B_SRAM
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0)
/* defines need for FreeRTOS+POSIX*/
#define configUSE_POSIX_ERRNO (1)
#define configUSE_APPLICATION_TASK_TAG (1)
/* include specific functions */
#define INCLUDE_vTaskDelete (1)
#define INCLUDE_vTaskDelay (1)
#define INCLUDE_vTaskSuspend (1)
#define INCLUDE_xTimerDelete (1)
#define INCLUDE_vSemaphoreDelete (1)
#define INCLUDE_xTimerPendFunctionCall (1)
#define INCLUDE_xTaskGetIdleTaskHandle (1)
#ifdef __cplusplus
}
#endif
#endif /* TI_FREERTOS_CONFIG_H */

98
.project/templates/am64x/freertos/main_freertos.c.xdt Normal file
View File

@ -0,0 +1,98 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let taskPri = "configMAX_PRIORITIES-1"
let entryFunction = "example_main";
if(options && options.entryFunction)
entryFunction = options.entryFunction;
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.taskPri)
taskPri = options.taskPri;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
#include "FreeRTOS.h"
#include "task.h"
#define MAIN_TASK_PRI (`taskPri`)
#define MAIN_TASK_SIZE (`stackSize`U/sizeof(configSTACK_DEPTH_TYPE))
StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
StaticTask_t gMainTaskObj;
TaskHandle_t gMainTask;
void `entryFunction`(void *args);
void freertos_main(void *args)
{
`entryFunction`(NULL);
vTaskDelete(NULL);
}
int main(void)
{
/* init SOC specific modules */
System_init();
Board_init();
/* This task is created at highest priority, it should create more tasks and then delete itself */
gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
"freertos_main", /* Text name for the task. This is to facilitate debugging only. */
MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
NULL, /* We are not using the task parameter. */
MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
gMainTaskStack, /* pointer to stack base */
&gMainTaskObj ); /* pointer to statically allocated task object memory */
configASSERT(gMainTask != NULL);
/* Start the scheduler to start the tasks executing. */
vTaskStartScheduler();
/* The following line should never be reached because vTaskStartScheduler()
will only return if there was not enough FreeRTOS heap memory available to
create the Idle and (if configured) Timer tasks. Heap management, and
techniques for trapping heap exhaustion, are described in the book text. */
DebugP_assertNoLog(0);
return 0;
}

114
.project/templates/am64x/freertos/main_freertos_smp.c.xdt Normal file
View File

@ -0,0 +1,114 @@
%%{
let options = args.options;
let stackSize = 16*1024;
let taskPri = "configMAX_PRIORITIES-1"
let entryFunction = "example_main";
if(options && options.entryFunction)
entryFunction = options.entryFunction;
if(options && options.stackSize)
stackSize = options.stackSize;
if(options && options.taskPri)
taskPri = options.taskPri;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
#include "FreeRTOS.h"
#include "task.h"
extern volatile uint64_t ullPortSchedularRunning;
#define MAIN_TASK_PRI (`taskPri`)
#define MAIN_TASK_SIZE (`stackSize`U/sizeof(configSTACK_DEPTH_TYPE))
StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
StaticTask_t gMainTaskObj;
TaskHandle_t gMainTask;
void `entryFunction`(void *args);
void frertos_main(void *args)
{
`entryFunction`(NULL);
vTaskDelete(NULL);
}
int main(void)
{
/* init SOC specific modules */
System_init();
Board_init();
if (0 == Armv8_getCoreId())
{
/* This task is created at highest priority, it should create more tasks and then delete itself */
gMainTask = xTaskCreateStatic( frertos_main, /* Pointer to the function that implements the task. */
"freertos_main", /* Text name for the task. This is to facilitate debugging only. */
MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
NULL, /* We are not using the task parameter. */
MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
gMainTaskStack, /* pointer to stack base */
&gMainTaskObj ); /* pointer to statically allocated task object memory */
configASSERT(gMainTask != NULL);
vTaskCoreAffinitySet(gMainTask, 1);
configASSERT(gMainTask != NULL);
/* Start the scheduler to start the tasks executing. */
vTaskStartScheduler();
}
else
{
while(ullPortSchedularRunning == 0)
{
;
}
xPortStartScheduler();
}
/* The following line should never be reached because vTaskStartScheduler()
will only return if there was not enough FreeRTOS heap memory available to
create the Idle and (if configured) Timer tasks. Heap management, and
techniques for trapping heap exhaustion, are described in the book text. */
DebugP_assertNoLog(0);
return 0;
}

186
.project/templates/am64x/gpio/board_gpio.c.xdt Normal file
View File

@ -0,0 +1,186 @@
%%{
let options = args.options;
exampleType = "input_interrupt";
if(options && options.exampleType)
exampleType = options.exampleType;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <drivers/hw_include/cslr_soc.h>
#include <drivers/gpio.h>
% if ( exampleType == "input_interrupt" ) {
#include <drivers/sciclient.h>
% }
#include "ti_drivers_config.h"
/*
* Board info
*/
% if ( exampleType == "input_interrupt" ) {
/* This is based on DMSC board config and core */
#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8)
#define BOARD_BUTTON_GPIO_SWITCH_NUM (5)
/** \brief bank interrupt source index base */
#define TISCI_BANK_SRC_IDX_BASE_GPIO0 (90U)
#define TISCI_BANK_SRC_IDX_BASE_GPIO1 (90U)
#define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (90U)
static void Sciclient_gpioIrqSet(void);
static void Sciclient_gpioIrqRelease(void);
void Board_gpioInit(void)
{
Sciclient_gpioIrqSet();
}
void Board_gpioDeinit(void)
{
Sciclient_gpioIrqRelease();
}
uint32_t Board_getGpioButtonIntrNum(void)
{
return (BOARD_BUTTON_GPIO_INTR_NUM);
}
uint32_t Board_getGpioButtonSwitchNum(void)
{
return (BOARD_BUTTON_GPIO_SWITCH_NUM);
}
static void Sciclient_gpioIrqSet(void)
{
int32_t retVal;
struct tisci_msg_rm_irq_set_req rmIrqReq;
struct tisci_msg_rm_irq_set_resp rmIrqResp;
/* For setting the IRQ for GPIO using sciclient APIs, we need to populate
* a structure, tisci_msg_rm_irq_set_req instantiated above. The definition
* of this struct and details regarding the struct members can be found in
* the tisci_rm_irq.h.
*/
/* Initialize all flags to zero since we'll be setting only a few */
rmIrqReq.valid_params = 0U;
/* Our request has a destination id, so enable the flag for DST ID */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
/* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
/* This is not a global event */
rmIrqReq.global_event = 0U;
/* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW.
* The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/.
* In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt,
* we need to choose the TISCI_DEV_GPIO1
*/
rmIrqReq.src_id = TISCI_DEV_GPIO1;
/* This is the interrupt source index within the GPIO peripheral */
rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);
/* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core.
* For a different core, the corresponding TISCI device id has to be provided */
rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
/* This is the output index of the interrupt router. This depends on the core and board configuration */
rmIrqReq.dst_host_irq = Board_getGpioButtonIntrNum();
/* Rest of the struct members are unused for GPIO interrupt */
rmIrqReq.ia_id = 0U;
rmIrqReq.vint = 0U;
rmIrqReq.vint_status_bit_index = 0U;
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
/* To set the interrupt we now invoke the Sciclient_rmIrqSet function which
* will find out the route to configure the interrupt and request DMSC to
* grant the resource
*/
retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
if(0 != retVal)
{
DebugP_log("[Error] Sciclient event config failed!!!\r\n");
DebugP_assert(FALSE);
}
return;
}
static void Sciclient_gpioIrqRelease(void)
{
int32_t retVal;
struct tisci_msg_rm_irq_release_req rmIrqReq;
/* For releasing the IRQ for GPIO using sciclient APIs, we need to populate
* a structure, tisci_msg_rm_irq_release_req instantiated above. The definition
* of this struct and details regarding the struct members can be found in
* the tisci_rm_irq.h. These are similar to the struct members for the set request
* used above.
*/
/* Initialize all flags to zero since we'll be setting only a few */
rmIrqReq.valid_params = 0U;
/* Our request has a destination id, so enable the flag for DST ID */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
/* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
/* This is not a global event */
rmIrqReq.global_event = 0U;
/* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW.
* The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/.
* In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt,
* we need to choose the TISCI_DEV_GPIO1
*/
rmIrqReq.src_id = TISCI_DEV_GPIO1;
/* This is the interrupt source index within the GPIO peripheral */
rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);
/* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core.
* For a different core, the corresponding TISCI device id has to be provided */
rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
/* This is the output index of the interrupt router. This depends on the core and board configuration */
rmIrqReq.dst_host_irq = Board_getGpioButtonIntrNum();
/* Rest of the struct members are unused for GPIO interrupt */
rmIrqReq.ia_id = 0U;
rmIrqReq.vint = 0U;
rmIrqReq.vint_status_bit_index = 0U;
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
/* To set the interrupt we now invoke the Sciclient_rmIrqRelease function which
* will find specifics about the route and request DMSC/SYSFW to relase/clear the interrupt
*/
retVal = Sciclient_rmIrqRelease(&rmIrqReq, SystemP_WAIT_FOREVER);
if(0 != retVal)
{
DebugP_log("[Error] Sciclient event reset failed!!!\r\n");
DebugP_assert(FALSE);
}
return;
}
% }

52
.project/templates/am64x/i2c/board_i2c.c.xdt Normal file
View File

@ -0,0 +1,52 @@
/*
* Copyright (C) 2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <drivers/hw_include/cslr_soc.h>
#include "ti_board_open_close.h"
/*
* Board info
*/
uint32_t Board_getnumLedPerGroup(void)
{
uint32_t ledCount;
const LED_Attrs *attrs;
attrs = LED_getAttrs(CONFIG_LED0);
DebugP_assert(NULL != attrs);
/* For AM243x-EVM all LEDs are connected, so return
* the driver atrributes value of 8 */
ledCount = attrs->numLedPerGroup;
return (ledCount);
}

58
.project/templates/am64x/nortos/main_nortos.c.xdt Normal file
View File

@ -0,0 +1,58 @@
%%{
let options = args.options;
entryFunction = "example_main";
if(options && options.entryFunction)
entryFunction = options.entryFunction;
%%}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
void `entryFunction`(void *args);
int main(void)
{
System_init();
Board_init();
`entryFunction`(NULL);
Board_deinit();
System_deinit();
return 0;
}

66
.project/templates/imports.mak.xdt Normal file
View File

@ -0,0 +1,66 @@
%%{
isDevelopmentMode = args.common.isDevelopmentMode();
deviceName = args.utils.getProjectSpecDevice(args.device);
%%}
DEVICE ?= am64x
ifeq ($(OS),Windows_NT)
TOOLS_PATH?=C:/ti
CCS_PATH?=$(TOOLS_PATH)/ccs1210/ccs
CCS_ECLIPSE=$(CCS_PATH)/eclipse/eclipsec
CYGWIN_PATH?=$(CCS_PATH)/utils/cygwin
MKDIR=$(CYGWIN_PATH)/mkdir -p
RMDIR=$(CYGWIN_PATH)/rm -rf
RM=$(CYGWIN_PATH)/rm -f
COPY=$(CYGWIN_PATH)/cp
TOUCH=$(CYGWIN_PATH)/touch
PATHSEP=\\
CHMOD=$(CYGWIN_PATH)/echo
SHELL=cmd.exe
% if((args.device == "am64x") || (isDevelopmentMode)) {
CGT_GCC_AARCH64_PATH=$(TOOLS_PATH)/gcc-arm-9.2-2019.12-mingw-w64-i686-aarch64-none-elf
CGT_GCC_ARM_PATH=$(TOOLS_PATH)/gcc-arm-none-eabi-7-2017-q4-major-win32
CGT_GCC_ARMV7_PATH=$(CGT_GCC_ARM_PATH)
% }
else
UNAME_S := $(shell uname -s)
ifeq ($(UNAME_S),Linux)
export TOOLS_PATH?=$(HOME)/ti
export CCS_PATH?=$(TOOLS_PATH)/ccs1210/ccs
export CCS_ECLIPSE=$(CCS_PATH)/eclipse/eclipse
export MKDIR=mkdir -p
export RMDIR=rm -rf
export RM=rm -f
export COPY=cp
export TOUCH=touch
export PATHSEP=/
export CHMOD=chmod
% if((args.device == "am64x") || (isDevelopmentMode)) {
CGT_GCC_AARCH64_PATH=$(TOOLS_PATH)/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf
CGT_GCC_ARM_PATH=$(TOOLS_PATH)/gcc-arm-none-eabi-7-2017-q4-major
CGT_GCC_ARMV7_PATH=$(CGT_GCC_ARM_PATH)
% }
endif
endif
# Variable pointing to location of MCU+ SDK
export MCU_PLUS_SDK_PATH?=$(TOOLS_PATH)/mcu_plus_sdk_`args.device`_09_00_00_01
CGT_TI_PRU_PATH=$(TOOLS_PATH)/ti-cgt-pru_2.3.3
CGT_TI_SMART_PLACEMENT_TOOL_PATH=$(TOOLS_PATH)/ti-cgt-armllvm_3.0.0.STS
CGT_TI_ARM_CLANG_PATH=$(CCS_PATH)/tools/compiler/ti-cgt-armllvm_2.1.2.LTS
ifeq ($(wildcard $(CGT_TI_ARM_CLANG_PATH)),)
CGT_TI_ARM_CLANG_PATH=$(TOOLS_PATH)/ti-cgt-armllvm_2.1.2.LTS
endif
% if((args.device == "am273x") || (args.device == "awr294x") || (isDevelopmentMode)) {
CGT_TI_C6000_PATH=$(CCS_PATH)/tools/compiler/ti-cgt-c6000_8.3.12
DSPLIB_PATH=$(MCU_PLUS_SDK_PATH)/source/dsplib_c66x_3_4_0_0
% }
CCS_NODE = $(CCS_PATH)/tools/node/node
SYSCFG_PATH ?= $(TOOLS_PATH)/sysconfig_1.14.0
SYSCFG_CLI_PATH ?= $(SYSCFG_PATH)
SYSCFG_NODE = $(SYSCFG_PATH)/nodejs/node
SYSCFG_NWJS = $(SYSCFG_PATH)/nw/nw
SYSCFG_SDKPRODUCT=$(MOTOR_CONTROL_SDK_PATH)/.metadata/product.json
SYSCFG_MCUPLUSSDKPRODUCT=$(MCU_PLUS_SDK_PATH)/.metadata/product.json

293
.project/templates/makefile_ccs_bootimage_gen.xdt Normal file
View File

@ -0,0 +1,293 @@
#
# Auto generated makefile
#
# Below variables need to be defined outside this file or via command line
# - MCU_PLUS_SDK_PATH
# - PROFILE
# - CG_TOOL_ROOT
# - OUTNAME
# - CCS_INSTALL_DIR
# - CCS_IDE_MODE
CCS_PATH=$(CCS_INSTALL_DIR)
include $(MCU_PLUS_SDK_PATH)/imports.mak
% if (["am243x", "am64x", "am263x", "am273x"].includes(args.project.device)) {
include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak
% }
STRIP=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.strip`
OBJCOPY=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.objcopy`
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif
OUTFILE=$(PROFILE)/$(OUTNAME).out
BOOTIMAGE_PATH=$(abspath ${PROFILE})
% if (args.project.isBootLoader) {
% if (["am243x", "am64x", "am263x", "am273x"].includes(args.project.device)) {
BOOTIMAGE_NAME_GP:=$(BOOTIMAGE_PATH)/$(OUTNAME).tiimage
BOOTIMAGE_NAME_HS:=`args.project.name`.$(PROFILE).hs.tiimage
BOOTIMAGE_NAME_HS_FS:=`args.project.name`.$(PROFILE).hs_fs.tiimage
ifeq ($(DEVICE_TYPE),HS)
BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_HS)
else
BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_GP)
endif
% } else {
BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).tiimage
% }
BOOTIMAGE_BIN_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).bin
% } else {
BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
% if (args.project.device == "awr294x") {
BOOTIMAGE_NAME_QSPI:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_qspi
% }
BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
% }
% if (args.project.isBootLoader) {
#
# Generation of boot image which can be loaded by ROM Boot Loader (RBL)
#
% } else {
#
# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
#
% }
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
ifeq ($(OS),Windows_NT)
BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1
else
BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh
endif
BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
% if (args.project.isBootLoader) {
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/rom_image_gen.py
SYSFW_PATH=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/soc/am64x_am243x
SYSFW_LOAD_ADDR=0x44000
BOARDCFG_LOAD_ADDR=0x7B000
% if (args.project.name.includes("linux")) {
% if (args.project.device == "am64x") {
BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am64x/boardcfg_blob_linux.bin
% } else if (args.project.device == "am243x") {
BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am243x/boardcfg_blob_linux.bin
% }
% } else {
% if (args.project.device == "am64x") {
BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am64x/boardcfg_blob.bin
% } else if (args.project.device == "am243x") {
BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am243x/boardcfg_blob.bin
% }
% }
% }
% if ((args.project.device == "am273x") || (args.project.device == "awr294x") || (args.project.device == "am263x")) {
ifeq ($(DEVICE_TYPE),HS)
BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
else
BOOTIMAGE_CERT_KEY=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_gpkey.pem
endif
BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_rom_image_gen.py
% }
% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) {
SBL_RUN_ADDRESS=0x10200000
% } else if (args.project.device == "am263x") {
SBL_RUN_ADDRESS=0x70002000
% } else {
SBL_RUN_ADDRESS=0x70000000
% }
SBL_PREBUILT_PATH=$(MCU_PLUS_SDK_PATH)/tools/boot/sbl_prebuilt/`args.project.board`
all:
ifeq ($(CCS_IDE_MODE),cloud)
# No post build steps
else
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME) ...
$(OBJCOPY) --strip-sections -O binary $(OUTFILE) $(BOOTIMAGE_BIN_NAME)
% if (args.project.device == "awr294x") {
ifeq ($(DEVICE_TYPE),HS)
ifeq ($(DBG_ENABLED),no)
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug DBG_PUBLIC_ENABLE
endif
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT
endif
% } else if ((args.project.device == "am263x") || (args.project.device == "am273x")) {
ifeq ($(DEVICE_TYPE),HS)
ifeq ($(DEBUG_TIFS), yes)
ifeq ($(ENC_SBL_ENABLED),yes)
$(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME)
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME)
endif
else
ifeq ($(ENC_SBL_ENABLED),yes)
$(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION)
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION)
endif
endif
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT
endif
% } else {
ifeq ($(DEVICE_TYPE),HS)
$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --debug DBG_FULL_ENABLE --rom-image $(BOOTIMAGE_NAME)
else
$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-fs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-fs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS)
$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_NAME)
endif
$(COPY) $(BOOTIMAGE_NAME) $(BOOTIMAGE_PATH)/tiboot3.bin
ifeq ($(DEVICE_TYPE),GP)
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
endif
% }
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME) Done !!!
@echo .
endif
% } else {
% if (args.project.device == "am64x") {
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) {
BOOTIMAGE_CORE_ID_a53ss0-1 = 1
% }
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if (args.project.device == "am243x") {
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if (args.project.device == "am263x") {
BOOTIMAGE_CORE_ID_r5fss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-1 = 1
BOOTIMAGE_CORE_ID_r5fss1-0 = 2
BOOTIMAGE_CORE_ID_r5fss1-1 = 3
SBL_RUN_ADDRESS=0x70002000
SBL_DEV_ID=55
% }
% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) {
BOOTIMAGE_CORE_ID_r5fss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-1 = 1
BOOTIMAGE_CORE_ID_c66ss0 = 2
% if (args.project.device == "awr294x") {
BOOTIMAGE_CORE_ID_r4 = 3
R4_RPRC_PATH = $(MCU_PLUS_SDK_PATH)/source/drivers/bootloader/soc/awr294x/xwr2xxx_radarss_metarprc.bin
% }
SBL_RUN_ADDRESS=0x10200000
SBL_DEV_ID=55
% }
% if (args.project.device == "am62x") {
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
BOOTIMAGE_CORE_ID_a53ss0-1 = 1
BOOTIMAGE_CORE_ID_a53ss1-0 = 2
BOOTIMAGE_CORE_ID_a53ss1-1 = 3
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_m4fss0-0 = 5
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) {
APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py
% }
ifeq ($(OS),Windows_NT)
XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
else
XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
endif
MULTI_CORE_IMAGE_PARAMS = \
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_`args.project.cpu`) \
% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) {
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_a53ss0-1) \
% }
MULTI_CORE_IMAGE_PARAMS_XIP = \
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_`args.project.cpu`) \
% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) {
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_a53ss0-1) \
% }
% if (args.project.device == "awr294x") {
MULTI_CORE_IMAGE_PARAMS_QSPI = $(MULTI_CORE_IMAGE_PARAMS) $(R4_RPRC_PATH)@$(BOOTIMAGE_CORE_ID_r4)
% }
all:
ifeq ($(CCS_IDE_MODE),cloud)
# No post build steps
else
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME) ...
$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x`args.flashAddr.toString(16)` -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
% if (args.project.device == "awr294x") {
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_QSPI) $(MULTI_CORE_IMAGE_PARAMS_QSPI) >> $(BOOTIMAGE_TEMP_OUT_FILE)
% }
% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) {
# Sign the appimage for HS-FS using appimage signing script
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
% }
% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) {
ifeq ($(DEVICE_TYPE),HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
$(RM) $(BOOTIMAGE_NAME)-enc
endif
endif
% }
$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
% if (args.project.isLinuxFwGen) {
$(RM) $(PROFILE)/`args.linuxFwName`
$(STRIP) -o=$(PROFILE)/`args.linuxFwName` $(OUTFILE)
% }
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME) Done !!!
@echo .
% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) {
ifeq ($(DEVICE_TYPE),HS)
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME).hs Done !!!
@echo .
else
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME).hs_fs Done !!!
@echo .
endif
% }
endif
% }

184
.project/templates/makefile_device_projectspec_top.xdt Normal file
View File

@ -0,0 +1,184 @@
#
# Auto generated makefile
#
% if (["am243x", "am64x"].includes(args.device)) {
export `args.sdkPath`?=$(abspath `args.relPath`)
include $(`args.sdkPath`)/imports.mak
% }
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL =
# Various Example Projectspec Build Targets
% for (example of args.example_list) {
% if(!example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL +=`example.buildTarget`_build
% }
% }
# Various System Example Projectspec Build Targets
% for (example of args.system_example_list) {
% if(!example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL +=`example.buildTarget`_build
% }
% }
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL =
# Various Private Example Projectspec Build Targets
% for (example of args.example_list) {
% if(example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL +=`example.buildTarget`_build
% }
% }
# Various Private System Example Projectspec Build Targets
% for (example of args.system_example_list) {
% if(example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL +=`example.buildTarget`_build
% }
% }
all: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL)
all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
% for (example of args.example_list) {
`example.buildTarget`_build:
$(MAKE) -C `example.relpath` -f makefile_projectspec all
% }
% for (example of args.system_example_list) {
`example.buildTarget`_build:
$(MAKE) -C `example.relpath` -f makefile_projectspec all
% }
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL =
# Various Example Projectspec Clean Targets
% for (example of args.example_list) {
% if(!example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL +=`example.buildTarget`_clean
% }
% }
# Various System Example Projectspec Clean Targets
% for (example of args.system_example_list) {
% if(!example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL +=`example.buildTarget`_clean
% }
% }
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL =
# Various Private Example Projectspec Clean Targets
% for (example of args.example_list) {
% if(example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL +=`example.buildTarget`_clean
% }
% }
# Various Private System Example Projectspec Clean Targets
% for (example of args.system_example_list) {
% if(example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL +=`example.buildTarget`_clean
% }
% }
clean: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL)
clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
% for (example of args.example_list) {
`example.buildTarget`_clean:
$(MAKE) -C `example.relpath` -f makefile_projectspec clean
% }
% for (example of args.system_example_list) {
`example.buildTarget`_clean:
$(MAKE) -C `example.relpath` -f makefile_projectspec clean
% }
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL =
# Various Example Projectspec Export Targets
% for (example of args.example_list) {
% if(!example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL +=`example.buildTarget`_export
% }
% }
# Various System Example Projectspec Export Targets
% for (example of args.system_example_list) {
% if(!example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL +=`example.buildTarget`_export
% }
% }
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL =
# Various Private Example Projectspec Export Targets
% for (example of args.example_list) {
% if(example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL +=`example.buildTarget`_export
% }
% }
# Various Private System Example Projectspec Export Targets
% for (example of args.system_example_list) {
% if(example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL +=`example.buildTarget`_export
% }
% }
export: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL)
export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
% for (example of args.example_list) {
`example.buildTarget`_export:
$(MAKE) -C `example.relpath` -f makefile_projectspec export
% }
% for (example of args.system_example_list) {
`example.buildTarget`_export:
$(MAKE) -C `example.relpath` -f makefile_projectspec export
% }
% if (["am243x", "am64x"].includes(args.device)) {
# Import extra components into CCS workspace before creating a project
# Setup dependency separately so that it runs if one or all projects are built via the makefile
$(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL) $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL): import_extra_components
# Import extra components based on the configured makefile variables.
# Same CCS workspace used by the examples is used here.
import_extra_components:
$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.common.core.initialize -ccs.productDiscoveryPath $(COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR) -ccs.productDiscoveryPath $(COM_TI_MCU_PLUS_SDK_AMXXX_INSTALL_DIR)
% }
help:
@echo Notes,
@echo - Use -j to invoke parallel builds
@echo - Use PROFILE=Debug or PROFILE=Release [default] to build in Debug or Release profile
@echo .
@echo Overall build targets,
@echo ======================
@echo $(MAKE) -s -f makefile_projectspec.`device` help
@echo .
@echo $(MAKE) -s -f makefile_projectspec.`device` [export all clean]
@echo .
@echo export = export projectspec to CCS project in the folder ./ccs_projects/,
@echo export MUST be called once before 'all' or 'clean'
@echo all = build the previously exported projectspecs
@echo clean = clean the previously exported projectspecs
@echo .
@echo Example ProjectSpec build targets,
@echo ==================================
% for (example of args.example_list) {
@echo $(MAKE) -s -C `example.relpath` -f makefile_projectspec [export all clean]
% }
@echo .
@echo System Example ProjectSpec build targets,
@echo =========================================
% for (example of args.system_example_list) {
@echo $(MAKE) -s -C `example.relpath` -f makefile_projectspec [export all clean]
% }
@echo .
.PHONY: all all-private
.PHONY: clean clean-private
.PHONY: help

289
.project/templates/makefile_device_top.xdt Normal file
View File

@ -0,0 +1,289 @@
%%{
let component_target_list_string = [];
let component_target_private_list_string = [];
let component_target_prebuilt_list_string = [];
let component_target_clean_list_string = [];
let component_target_scrub_list_string = [];
let component_target_prebuilt_clean_list_string = [];
let component_target_prebuilt_scrub_list_string = [];
for (component of args.component_list) {
if(component.isSkipTopLevelBuild) {
component_target_private_list_string +=` \$(BUILD_COMBO_${component.name})`
component_target_clean_list_string +=` \$(BUILD_COMBO_CLEAN_${component.name})`
component_target_scrub_list_string +=` \$(BUILD_COMBO_SCRUB_${component.name})`
}
else if(component.isPrebuilt) {
component_target_prebuilt_list_string +=` \$(BUILD_COMBO_${component.name})`
component_target_prebuilt_clean_list_string +=` \$(BUILD_COMBO_CLEAN_${component.name})`
component_target_prebuilt_scrub_list_string +=` \$(BUILD_COMBO_SCRUB_${component.name})`
}
else {
component_target_list_string +=` \$(BUILD_COMBO_${component.name})`
component_target_clean_list_string +=` \$(BUILD_COMBO_CLEAN_${component.name})`
component_target_scrub_list_string +=` \$(BUILD_COMBO_SCRUB_${component.name})`
}
}
%%}
#
# Auto generated makefile
#
all:
$(MAKE) -f makefile.`device` libs
$(MAKE) -f makefile.`device` examples
clean: libs-clean examples-clean
scrub: libs-scrub examples-scrub
help:
@echo Notes,
@echo - Use -j to invoke parallel builds
@echo - Use PROFILE=debug or PROFILE=release [default] to build in debug or release profile
@echo .
@echo Overall build targets,
@echo ======================
@echo $(MAKE) -s -f makefile.`device` help
@echo .
@echo $(MAKE) -s -f makefile.`device` all
@echo $(MAKE) -s -f makefile.`device` clean # delete's tmp files for current profile
@echo $(MAKE) -s -f makefile.`device` scrub # delete's all tmp files and folders for all profiles
@echo .
@echo $(MAKE) -s -f makefile.`device` libs
@echo $(MAKE) -s -f makefile.`device` libs-clean # delete's tmp files for current profile
@echo $(MAKE) -s -f makefile.`device` libs-scrub # delete's all tmp files and folders for all profiles
@echo .
@echo $(MAKE) -s -f makefile.`device` examples
@echo $(MAKE) -s -f makefile.`device` examples-clean # delete's tmp files for current profile
@echo $(MAKE) -s -f makefile.`device` examples-scrub # delete's all tmp files and folders for all profiles
@echo .
@echo Library build targets,
@echo ======================
% for (component of args.component_list) {
@echo $(MAKE) -s -f makefile.`device``component.buildTarget`
% }
@echo .
@echo Library clean targets,
@echo ======================
% for (component of args.component_list) {
@echo $(MAKE) -s -f makefile.`device``component.buildTargetClean`
% }
@echo .
@echo Example build targets,
@echo ======================
% for (example of args.example_list) {
@echo $(MAKE) -s -C `example.relpath` [all clean syscfg-gui syscfg]
% }
@echo .
@echo System Example build targets,
@echo =============================
% for (example of args.system_example_list) {
@echo $(MAKE) -s -C `example.relpath` [all clean syscfg-gui syscfg]
% }
@echo .
# Various Component Targets
% for (component of args.component_list) {
BUILD_COMBO_`component.name` =`component.buildTarget`
% }
# Combine all Components
BUILD_COMBO_ALL =`component_target_list_string`
# Combine all Pre-built Components
BUILD_COMBO_PREBUILT_ALL =`component_target_prebuilt_list_string`
# Combine all Private Components
BUILD_COMBO_PRIVATE_ALL =`component_target_private_list_string`
libs: $(BUILD_COMBO_ALL)
libs-prebuilt: $(BUILD_COMBO_PREBUILT_ALL)
libs-private: $(BUILD_COMBO_PRIVATE_ALL)
% for (component of args.component_list) {
$(BUILD_COMBO_`component.name`):
$(MAKE) -C `component.relpath` -f makefile`component.tag`.`args.device`.$(subst `component.name`_,,$@) all
% }
# Various Component Clean Targets
% for (component of args.component_list) {
BUILD_COMBO_CLEAN_`component.name` =`component.buildTargetClean`
% }
# Combine all Components Clean
BUILD_COMBO_CLEAN_ALL =`component_target_clean_list_string`
# Combine all Pre-built Components Clean
BUILD_COMBO_PREBUILT_CLEAN_ALL =`component_target_prebuilt_clean_list_string`
libs-clean: $(BUILD_COMBO_CLEAN_ALL)
libs-prebuilt-clean: $(BUILD_COMBO_PREBUILT_CLEAN_ALL)
% for (component of args.component_list) {
$(BUILD_COMBO_CLEAN_`component.name`):
$(MAKE) -C `component.relpath` -f makefile`component.tag`.`args.device`.$(subst `component.name`_,,$(subst _clean,,$@)) clean
% }
# Various Component Scrub Targets
% for (component of args.component_list) {
BUILD_COMBO_SCRUB_`component.name` =`component.buildTargetScrub`_scrub
% }
# Combine all Components Scrub Targets
BUILD_COMBO_SCRUB_ALL =`component_target_scrub_list_string`
# Combine all Pre-built Components Scrub Targets
BUILD_COMBO_PREBUILT_SCRUB_ALL =`component_target_prebuilt_scrub_list_string`
libs-scrub: $(BUILD_COMBO_SCRUB_ALL)
libs-prebuilt-scrub: $(BUILD_COMBO_PREBUILT_SCRUB_ALL)
% for (component of args.component_list) {
$(BUILD_COMBO_SCRUB_`component.name`):
$(MAKE) -C `component.relpath` -f makefile`component.tag`.`args.device`.$(subst `component.name`_,,$(subst _scrub,,$@)) scrub
% }
BUILD_COMBO_EXAMPLE_ALL =
# Various Example Targets
% for (example of args.example_list) {
% if(!example.isSkipTopLevelBuild && !example.isBootLoader) {
BUILD_COMBO_EXAMPLE_ALL +=`example.buildTarget`
% }
% }
# Various System Example Targets
% for (example of args.system_example_list) {
% if(!example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_ALL +=`example.buildTarget`
% }
% }
BUILD_COMBO_EXAMPLE_PRIVATE_ALL =
# Various Private Example Targets
% for (example of args.example_list) {
% if(example.isSkipTopLevelBuild && !example.isBootLoader) {
BUILD_COMBO_EXAMPLE_PRIVATE_ALL +=`example.buildTarget`
% }
% }
# Various Private System Example Targets
% for (example of args.system_example_list) {
% if(example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PRIVATE_ALL +=`example.buildTarget`
% }
% }
examples: $(BUILD_COMBO_EXAMPLE_ALL)
examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
% for (example of args.example_list) {
`example.buildTarget`:
$(MAKE) -C `example.relpath` -f makefile all
% }
% for (example of args.system_example_list) {
`example.buildTarget`:
$(MAKE) -C `example.relpath` -f makefile all
% }
BUILD_COMBO_EXAMPLE_CLEAN_ALL =
# Various Example Clean Targets
% for (example of args.example_list) {
% if(!example.isSkipTopLevelBuild && !example.isBootLoader) {
BUILD_COMBO_EXAMPLE_CLEAN_ALL +=`example.buildTargetClean`
% }
% }
# Various System Example Clean Targets
% for (example of args.system_example_list) {
% if(!example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_CLEAN_ALL +=`example.buildTargetClean`
% }
% }
BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL =
# Various Private Example Targets
% for (example of args.example_list) {
% if(example.isSkipTopLevelBuild && !example.isBootLoader) {
BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL +=`example.buildTargetClean`
% }
% }
# Various Private System Example Targets
% for (example of args.system_example_list) {
% if(example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL +=`example.buildTargetClean`
% }
% }
examples-clean: $(BUILD_COMBO_EXAMPLE_CLEAN_ALL)
examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
% for (example of args.example_list) {
`example.buildTargetClean`:
$(MAKE) -C `example.relpath` -f makefile clean
% }
% for (example of args.system_example_list) {
`example.buildTargetClean`:
$(MAKE) -C `example.relpath` -f makefile clean
% }
BUILD_COMBO_EXAMPLE_SCRUB_ALL =
# Various Example Scrub Targets
% for (example of args.example_list) {
% if(!example.isSkipTopLevelBuild && !example.isBootLoader) {
BUILD_COMBO_EXAMPLE_SCRUB_ALL +=`example.buildTargetScrub`
% }
% }
# Various System Example Scrub Targets
% for (example of args.system_example_list) {
% if(!example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_SCRUB_ALL +=`example.buildTargetScrub`
% }
% }
BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL =
# Various Private Example Targets
% for (example of args.example_list) {
% if(example.isSkipTopLevelBuild && !example.isBootLoader) {
BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL +=`example.buildTargetScrub`
% }
% }
# Various Private System Example Targets
% for (example of args.system_example_list) {
% if(example.isSkipTopLevelBuild) {
BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL +=`example.buildTargetScrub`
% }
% }
examples-scrub: $(BUILD_COMBO_EXAMPLE_SCRUB_ALL)
examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
% for (example of args.example_list) {
`example.buildTargetScrub`:
$(MAKE) -C `example.relpath` -f makefile scrub
% }
% for (example of args.system_example_list) {
`example.buildTargetScrub`:
$(MAKE) -C `example.relpath` -f makefile scrub
% }
.PHONY: all clean scrub help
.PHONY: libs libs-clean libs-scrub
.PHONY: libs-private
.PHONY: libs-prebuilt libs-prebuilt-clean libs-prebuilt-scrub
.PHONY: examples examples-clean examples-scrub
.PHONY: examples-private examples-private-clean examples-private-scrub
.PHONY: $(BUILD_COMBO_ALL) $(BUILD_COMBO_CLEAN_ALL) $(BUILD_COMBO_SCRUB_ALL)
.PHONY: $(BUILD_COMBO_EXAMPLE_ALL) $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_SCRUB_ALL)
.PHONY: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)

710
.project/templates/makefile_executable.xdt Normal file
View File

@ -0,0 +1,710 @@
#
# Auto generated makefile
#
export `args.sdkPath`?=$(abspath `args.relPath`)
include $(`args.sdkPath`)/imports.mak
include $(`args.sdkPath`)/devconfig/devconfig.mak
CG_TOOL_ROOT=$(`args.cgtOptions.path`)
CC=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.cc`
LNK=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.lnk`
STRIP=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.strip`
OBJCOPY=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.objcopy`
% if ((args.isInstrumentationMode) && (args.cgtOptions.cov)) {
COV=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.cov`
PROFDATA=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.profdata`
COVERAGE_PATH=$(abspath .)
% }
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif
PROFILE?=release
ConfigName:=$(PROFILE)
OUTNAME:=`args.project.name`.$(PROFILE).out
BOOTIMAGE_PATH=$(abspath .)
% if (args.project.isBootLoader) {
% if ((args.project.device == "am64x") || (args.project.device == "am243x") || (args.project.device == "am263x") || (args.project.device == "am273x")) {
BOOTIMAGE_NAME_GP:=`args.project.name`.$(PROFILE).tiimage
BOOTIMAGE_NAME_HS:=`args.project.name`.$(PROFILE).hs.tiimage
BOOTIMAGE_NAME_HS_FS:=`args.project.name`.$(PROFILE).hs_fs.tiimage
% } else {
BOOTIMAGE_NAME:=`args.project.name`.$(PROFILE).tiimage
% }
BOOTIMAGE_BIN_NAME:=`args.project.name`.$(PROFILE).bin
% if ((args.project.device == "am64x") || (args.project.device == "am243x") || (args.project.device == "am263x") || (args.project.device == "am273x")) {
ifeq ($(DEVICE_TYPE),HS)
BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_HS)
else
BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_GP)
endif
% }
% } else {
BOOTIMAGE_NAME:=`args.project.name`.$(PROFILE).appimage
BOOTIMAGE_NAME_XIP:=`args.project.name`.$(PROFILE).appimage_xip
% if (args.project.device == "awr294x") {
BOOTIMAGE_NAME_QSPI:=`args.project.name`.$(PROFILE).appimage_qspi
% }
BOOTIMAGE_NAME_SIGNED:=`args.project.name`.$(PROFILE).appimage.signed
BOOTIMAGE_RPRC_NAME:=`args.project.name`.$(PROFILE).rprc
BOOTIMAGE_RPRC_NAME_XIP:=`args.project.name`.$(PROFILE).rprc_xip
BOOTIMAGE_RPRC_NAME_TMP:=`args.project.name`.$(PROFILE).rprc_tmp
% if (((args.project.device == "am64x") || (args.project.device == "am243x")) && (!args.project.isPartOfSystemProject)) {
BOOTIMAGE_NAME_HS:=`args.project.name`.$(PROFILE).appimage.hs
BOOTIMAGE_NAME_HS_FS:=`args.project.name`.$(PROFILE).appimage.hs_fs
TARGETS := $(BOOTIMAGE_NAME)
ifeq ($(DEVICE_TYPE), HS)
TARGETS += $(BOOTIMAGE_NAME_HS)
endif
% }
% }
% let linker_option_prefix = "";
% if (args.project.cgt == "ti-arm-clang") {
% linker_option_prefix = "-Wl,";
% }
% let obj = {}
% obj = args.project.files;
% if(obj["common"] == undefined) {
% obj.common = Array()
%}
% if (args.project.syscfgfile) {
% obj.common.push("ti_drivers_config.c", "ti_drivers_open_close.c", "ti_board_config.c", "ti_board_open_close.c", "ti_dpl_config.c", "ti_pinmux_config.c", "ti_power_clock_config.c");
% }
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
FILES_`prop` := \
% for(let val of obj[prop]) {
`val` \
% }
% for(val of args.project.libs["common"]){
% if (val.startsWith("enet")) {
ti_enet_config.c \
ti_enet_open_close.c \
ti_enet_soc.c \
ti_enet_lwipif.c \
% }
% }
% }
% }
% obj = args.project.asmfiles;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
ASMFILES_`prop` := \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% obj = args.project.filedirs;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
FILES_PATH_`prop` = \
% for(let val of obj[prop]) {
`val` \
% }
% if ( prop == "common" && args.project.syscfgfile) {
generated \
% }
% }
% }
% obj = args.project.includes;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
INCLUDES_`prop` := \
% for(let val of obj[prop]) {
-I`val` \
% }
% if ( prop == "common" && args.project.syscfgfile) {
-Igenerated \
% }
% }
% }
% obj = args.project.defines;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
DEFINES_`prop` := \
% for(let val of obj[prop]) {
-D`val` \
% }
% }
% }
% obj = args.project.cflags;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
CFLAGS_`prop` := \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% obj = args.project.lnkfiles;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
LNK_FILES_`prop` = \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% obj = args.project.libdirs;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
LIBS_PATH_`prop` = \
% for(let val of obj[prop]) {
% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) {
-L`val` \
% }
% else {
`linker_option_prefix`-i`val` \
% }
% }
% }
% }
% obj = args.project.libs;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
LIBS_`prop` = \
% for(let val of obj[prop]) {
% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) {
-l:`val` \
% }
% else {
-l`val` \
% }
% }
% }
% }
% obj = args.project.lflags;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
LFLAGS_`prop` = \
% for(let val of obj[prop]) {
% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) {
`val` \
% }
% else {
`linker_option_prefix``val` \
% }
% }
% }
% }
% if ((args.project.cgt == 'ti-arm-clang')) {
% obj = args.project.loptflags;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
LNKOPTFLAGS_`prop` = \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% }
% obj = args.project.libs;
LIBS_NAME = \
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% obj = args.project.libdirs;
LIBS_PATH_NAME = \
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
FILES := $(FILES_common) $(FILES_$(PROFILE))
% obj = args.project.files;
% if(args.project.files["cpp_common"] != undefined) {
CPPFILES := $(FILES_cpp_common) $(FILES_cpp_$(PROFILE))
% }
ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
% if(args.project.files["cpp_common"] != undefined) {
CPPFILES_PATH := $(FILES_PATH_cpp_common) $(FILES_PATH_$(PROFILE))
CPPFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) $(CFLAGS_cpp_common)
% }
DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
% if ((args.project.cgt == 'ti-arm-clang')) {
LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
% }
LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
OBJDIR := obj/$(PROFILE)/
OBJS := $(FILES:%.c=%.obj)
% if(args.project.files["cpp_common"] != undefined) {
OBJS += $(CPPFILES:%.cpp=%.obj)
% }
OBJS += $(ASMFILES:%.S=%.obj)
DEPS := $(FILES:%.c=%.d)
vpath %.obj $(OBJDIR)
vpath %.c $(FILES_PATH)
% if(args.project.files["cpp_common"] != undefined) {
vpath %.cpp $(CPPFILES_PATH)
% }
vpath %.S $(FILES_PATH)
vpath %.lib $(LIBS_PATH_NAME)
vpath %.a $(LIBS_PATH_NAME)
% if(args.project.files["cpp_common"] != undefined) {
$(OBJDIR)/%.obj %.obj: %.cpp
@echo Compiling: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(OUTNAME): $<
% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") {
$(CC) $(CPPFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fc=$<
% }
% if (args.project.cgt == "ti-arm-clang") {
$(CC) -c $(CPPFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
% }
% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) {
$(CC) -c $(CPPFLAGS) $(INCLUDES) $(DEFINES) -MMD -MT $@ -o $(OBJDIR)/$@ $<
% }
% }
$(OBJDIR)/%.obj %.obj: %.c
@echo Compiling: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(OUTNAME): $<
% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") {
$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fc=$<
% }
% if (args.project.cgt == "ti-arm-clang") {
$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
% }
% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) {
$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -MT $@ -o $(OBJDIR)/$@ $<
% }
$(OBJDIR)/%.obj %.obj: %.S
@echo Compiling: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(LIBNAME): $<
% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") {
$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$<
% }
% if (args.project.cgt == "ti-arm-clang") {
$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
% }
% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) {
$(CC) -c -x assembler-with-cpp $(CFLAGS) $(INCLUDES) $(DEFINES) -o $(OBJDIR)$@ $<
% }
% if(((args.project.device == "am64x") || (args.project.device == "am243x")) && (!args.project.isBootLoader) && (!args.project.isPartOfSystemProject)) {
all: $(TARGETS)
% } else {
all: $(BOOTIMAGE_NAME)
% }
% if ( args.project.syscfgfile ) {
SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
% for(val of args.project.libs["common"]){
% if (val.startsWith("enet")) {
SYSCFG_GEN_FILES+=generated/ti_enet_config.c generated/ti_enet_config.h
SYSCFG_GEN_FILES+=generated/ti_enet_open_close.c generated/ti_enet_open_close.h
SYSCFG_GEN_FILES+=generated/ti_enet_soc.c
SYSCFG_GEN_FILES+=generated/ti_enet_lwipif.c generated/ti_enet_lwipif.h
% }
% }
% }
% if ( args.project.syscfgfile ) {
$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
% } else {
$(OUTNAME): $(OBJS) $(LNK_FILES) $(LIBS_NAME)
% }
@echo .
@echo Linking: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $@ ...
% if (args.project.cgt == "ti-arm-clang" || args.project.cgt == "ti-c6000") {
% if (args.project.cgt == "ti-arm-clang") {
$(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) `linker_option_prefix`-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
% } else {
$(LNK) $(LFLAGS) $(LIBS_PATH) `linker_option_prefix`-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
% }
% if (args.project.isBootLoader) {
% } else {
% if (args.project.isLinuxFwGen) {
$(RM) `args.linuxFwName`
$(STRIP) -o=`args.linuxFwName` $@
% }
% }
% }
% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) {
$(LNK) $(LIBS_PATH) -Wl,-Map=$(OUTNAME:%.out=%.map) -o $@ -Wl,--start-group $(LFLAGS) $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) -Wl,--end-group -Wl,-T,$(LNK_FILES)
% }
@echo Linking: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $@ Done !!!
@echo .
clean:
@echo Cleaning: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(OUTNAME) ...
$(RMDIR) $(OBJDIR)
$(RM) $(OUTNAME)
% if (args.project.isBootLoader) {
% } else {
% if (args.project.isLinuxFwGen) {
$(RM) `args.linuxFwName`
% }
% }
% if (args.project.isBootLoader) {
$(RM) $(BOOTIMAGE_NAME)
$(RM) $(BOOTIMAGE_BIN_NAME)
% } else {
$(RM) $(BOOTIMAGE_NAME)
$(RM) $(BOOTIMAGE_NAME_XIP)
% if (args.project.device == "awr294x") {
$(RM) $(BOOTIMAGE_NAME_QSPI)
% }
$(RM) $(BOOTIMAGE_NAME_SIGNED)
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
$(RM) $(BOOTIMAGE_NAME_HS)
$(RM) $(BOOTIMAGE_NAME_HS_FS)
% }
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
% }
% if (args.project.syscfgfile) {
$(RMDIR) generated/
% }
scrub:
@echo Scrubing: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` `args.project.name` ...
$(RMDIR) obj
% if (args.project.isBootLoader) {
% } else {
% if (args.project.isLinuxFwGen) {
$(RM) `args.linuxFwName`
% }
% }
ifeq ($(OS),Windows_NT)
$(RM) \*.out
$(RM) \*.map
$(RM) \*.appimage*
$(RM) \*.rprc*
$(RM) \*.tiimage*
$(RM) \*.bin
else
$(RM) *.out
$(RM) *.map
$(RM) *.appimage*
$(RM) *.rprc*
$(RM) *.tiimage*
$(RM) *.bin
endif
% if (args.project.syscfgfile) {
$(RMDIR) generated
% }
$(OBJS): | $(OBJDIR)
$(OBJDIR):
$(MKDIR) $@
% if (args.project.syscfgfile) {
% // with syscfg enabled, parallel build does not work due to generated files dependancies
.NOTPARALLEL:
.INTERMEDIATE: syscfg
$(SYSCFG_GEN_FILES): syscfg
syscfg: `args.project.syscfgfile`
@echo Generating SysConfig files ...
$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context `args.syscfg.cpu` --part `args.syscfg.part` --package `args.syscfg.pkg` --output generated/ `args.project.syscfgfile`
syscfg-gui:
$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device `args.syscfg.device` --context `args.syscfg.cpu` --part `args.syscfg.part` --package `args.syscfg.pkg` --output generated/ `args.project.syscfgfile`
% }
% if (args.project.isBootLoader) {
#
# Generation of boot image which can be loaded by ROM Boot Loader (RBL)
#
% } else {
#
# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
#
% }
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
ifeq ($(OS),Windows_NT)
BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1
else
BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh
endif
BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
% }
% if (args.project.isBootLoader) {
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/rom_image_gen.py
SYSFW_PATH=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/soc/am64x_am243x
SYSFW_LOAD_ADDR=0x44000
BOARDCFG_LOAD_ADDR=0x7B000
% if (args.project.name.includes("linux")) {
% if (args.project.device == "am64x") {
BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am64x/boardcfg_blob_linux.bin
% } else if (args.project.device == "am243x") {
BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am243x/boardcfg_blob_linux.bin
% }
% } else {
% if (args.project.device == "am64x") {
BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am64x/boardcfg_blob.bin
% } else if (args.project.device == "am243x") {
BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am243x/boardcfg_blob.bin
% }
% }
% }
% if ((args.project.device == "am273x") || (args.project.device == "awr294x") || (args.project.device == "am263x")) {
ifeq ($(DEVICE_TYPE),HS)
BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
else
BOOTIMAGE_CERT_KEY=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_gpkey.pem
endif
BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_rom_image_gen.py
% }
% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) {
SBL_RUN_ADDRESS=0x10200000
% } else if (args.project.device == "am263x") {
SBL_RUN_ADDRESS=0x70002000
% } else {
SBL_RUN_ADDRESS=0x70000000
% }
SBL_PREBUILT_PATH=$(MCU_PLUS_SDK_PATH)/tools/boot/sbl_prebuilt/`args.project.board`
$(BOOTIMAGE_BIN_NAME): $(OUTNAME)
$(OBJCOPY) --strip-sections -O binary $(OUTNAME) $(BOOTIMAGE_BIN_NAME)
$(BOOTIMAGE_NAME): $(BOOTIMAGE_BIN_NAME)
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$@ ...
% if (args.project.device == "awr294x") {
ifeq ($(DEVICE_TYPE),HS)
ifeq ($(DBG_ENABLED),no)
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug DBG_PUBLIC_ENABLE
endif
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT
endif
% } else if ((args.project.device == "am263x") || (args.project.device == "am273x")) {
ifeq ($(DEVICE_TYPE),HS)
ifeq ($(DEBUG_TIFS), yes)
ifeq ($(ENC_SBL_ENABLED),yes)
$(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME)
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME)
endif
else
ifeq ($(ENC_SBL_ENABLED),yes)
$(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION)
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION)
endif
endif
else
$(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT
endif
% } else {
ifeq ($(DEVICE_TYPE),HS)
ifeq ($(ENC_SBL_ENABLED),yes)
$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --sbl-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --debug DBG_FULL_ENABLE --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME)
else
$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --debug DBG_FULL_ENABLE --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME)
endif
else
$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME)
$(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-fs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-fs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS)
endif
$(COPY) $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) tiboot3.bin
% }
$(COPY) $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) $(SBL_PREBUILT_PATH)/
% if ((args.project.device != "am64x") || (args.project.device != "am243x")) {
$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
% }
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$@ Done !!!
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
ifeq ($(DEVICE_TYPE),GP)
$(COPY) $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) $(SBL_PREBUILT_PATH)/
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
endif
% }
@echo .
% } else {
% if (args.project.device == "am64x") {
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) {
BOOTIMAGE_CORE_ID_a53ss0-1 = 1
% }
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if (args.project.device == "am243x") {
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if (args.project.device == "am263x") {
BOOTIMAGE_CORE_ID_r5fss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-1 = 1
BOOTIMAGE_CORE_ID_r5fss1-0 = 2
BOOTIMAGE_CORE_ID_r5fss1-1 = 3
SBL_RUN_ADDRESS=0x70002000
SBL_DEV_ID=55
% }
% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) {
BOOTIMAGE_CORE_ID_r5fss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-1 = 1
BOOTIMAGE_CORE_ID_c66ss0 = 2
% if (args.project.device == "awr294x") {
BOOTIMAGE_CORE_ID_r4 = 3
R4_RPRC_PATH = $(MCU_PLUS_SDK_PATH)/source/drivers/bootloader/soc/awr294x/xwr2xxx_radarss_metarprc.bin
% }
SBL_RUN_ADDRESS=0x10200000
SBL_DEV_ID=55
% }
% if (args.project.device == "am62x") {
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
BOOTIMAGE_CORE_ID_a53ss0-1 = 1
BOOTIMAGE_CORE_ID_a53ss1-0 = 2
BOOTIMAGE_CORE_ID_a53ss1-1 = 3
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_m4fss0-0 = 5
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) {
APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py
% }
ifeq ($(OS),Windows_NT)
XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
else
XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
endif
MULTI_CORE_IMAGE_PARAMS = \
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_`args.project.cpu`) \
% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) {
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_a53ss0-1) \
% }
MULTI_CORE_IMAGE_PARAMS_XIP = \
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_`args.project.cpu`) \
% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) {
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_a53ss0-1) \
% }
% if (args.project.device == "awr294x") {
MULTI_CORE_IMAGE_PARAMS_QSPI = $(MULTI_CORE_IMAGE_PARAMS) $(R4_RPRC_PATH)@$(BOOTIMAGE_CORE_ID_r4)
% }
$(BOOTIMAGE_NAME): $(OUTNAME)
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$@ ...
ifneq ($(OS),Windows_NT)
$(CHMOD) a+x $(XIPGEN_CMD)
endif
$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x`args.flashAddr.toString(16)` -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
% if (args.project.device == "awr294x") {
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_QSPI) $(MULTI_CORE_IMAGE_PARAMS_QSPI) >> $(BOOTIMAGE_TEMP_OUT_FILE)
% }
% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) {
# Sign the appimage for HS-FS using appimage signing script
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
% }
$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$@ Done !!!
@echo .
% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) {
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
@echo .
% }
% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) {
$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
ifeq ($(DEVICE_TYPE), HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
$(RM) $(BOOTIMAGE_NAME)-enc
endif
@echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
@echo .
endif
% }
% }
% if (args.isInstrumentationMode && args.project.cgt == "ti-arm-clang") {
.PHONY: coverage
coverage:
@echo Creating Coverage Report for `args.project.name`.$(PROFILE) ...
$(MKDIR) coverage
$(PROFDATA) merge -sparse -obj-file=$(OUTNAME) $(OUTNAME).cnt -o `args.project.name`.$(PROFILE).profdata
$(COV) show --format=html --show-expansions --show-instantiations --show-branches=count --object=$(OUTNAME) -instr-profile=`args.project.name`.$(PROFILE).profdata --output-dir=$(COVERAGE_PATH)/coverage
$(COV) export --format=text --object=$(OUTNAME) --instr-profile=`args.project.name`.$(PROFILE).profdata > coverage/`args.project.name`.$(PROFILE).profdata.json
node $(MCU_PLUS_SDK_PATH)/docs_src/code_coverage/clang_coverage_analyse.js --input=coverage/`args.project.name`.$(PROFILE).profdata.json --output-json=coverage/`args.project.name`.$(PROFILE).analysis.json --output-lnk=linker_xip.cmd --top-function-count=500
@echo Coverage Report Generated at $(COVERAGE_PATH)/coverage folder !!!
% }
-include $(addprefix $(OBJDIR)/, $(DEPS))

206
.project/templates/makefile_library.xdt Normal file
View File

@ -0,0 +1,206 @@
#
# Auto generated makefile
#
export `args.sdkPath`?=$(abspath `args.relPath`)
include $(`args.sdkPath`)/imports.mak
CG_TOOL_ROOT=$(`args.cgtOptions.path`)
CC=$(`args.cgtOptions.path`)/bin/`args.cgtOptions.cc`
AR=$(`args.cgtOptions.path`)/bin/`args.cgtOptions.ar`
PROFILE?=release
ConfigName:=$(PROFILE)
% if (args.project.name == "drivers" && (args.project.device == "am243x" || args.project.device == "am64x")) {
DEVICE_TYPE?=GP
% }
LIBNAME:=`args.project.name`.`args.project.device`.`args.project.cpu`.`args.project.cgt`.$(PROFILE).lib
% let obj = {}
% obj = args.project.files;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
FILES_`prop` := \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% obj = args.project.asmfiles;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
ASMFILES_`prop` := \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% if (args.project.device == "awr294x") {
% obj = args.project.asmextnfiles;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
ASMEXTNFILES_`prop` := \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% }
% obj = args.project.filedirs;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
FILES_PATH_`prop` = \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% obj = args.project.includes;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
INCLUDES_`prop` := \
% for(let val of obj[prop]) {
-I`val` \
% }
% }
% }
% obj = args.project.defines;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
DEFINES_`prop` := \
% for(let val of obj[prop]) {
-D`val` \
% }
% }
% }
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == "common" && args.project.name == "drivers" && (args.project.device == "am243x" || args.project.device == "am64x") ) {
# Remove later with combined boot
ifeq ($(DEVICE_TYPE),$(filter $(DEVICE_TYPE), HS))
DEFINES_`prop` += -DBUILD_HS
endif
% }
% }
% obj = args.project.cflags;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
CFLAGS_`prop` := \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
% obj = args.project.arflags;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) {
ARFLAGS_`prop` := \
% for(let val of obj[prop]) {
`val` \
% }
% }
% }
FILES := $(FILES_common) $(FILES_$(PROFILE))
ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
% if (args.project.device == "awr294x") {
ASMEXTNFILES := $(ASMEXTNFILES_common) $(ASMEXTNFILES_$(PROFILE))
% }
FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
ifeq ($(CPLUSPLUS_BUILD), yes)
CFLAGS += $(CFLAGS_cpp_common)
endif
DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE))
LIBDIR := lib
OBJDIR := obj/`args.project.device`/`args.project.cgt`/$(PROFILE)/`args.project.cpu`/`args.project.name`/
OBJS := $(FILES:%.c=%.obj)
OBJS += $(ASMFILES:%.S=%.obj)
% if (args.project.device == "awr294x") {
OBJS += $(ASMEXTNFILES:%.asm=%.obj)
% }
DEPS := $(FILES:%.c=%.d)
vpath %.obj $(OBJDIR)
vpath %.c $(FILES_PATH)
vpath %.S $(FILES_PATH)
% if (args.project.device == "awr294x") {
vpath %.asm $(FILES_PATH)
% }
$(OBJDIR)/%.obj %.obj: %.c
@echo Compiling: $(LIBNAME): $<
% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") {
$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fc=$<
% }
% if (args.project.cgt == "ti-arm-clang") {
$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
% }
% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) {
$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -MT $@ -o $(OBJDIR)/$@ $<
% }
$(OBJDIR)/%.obj %.obj: %.S
@echo Compiling: $(LIBNAME): $<
% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") {
$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$<
% }
% if (args.project.cgt == "ti-arm-clang") {
$(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $<
% }
% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) {
$(CC) -c -x assembler-with-cpp $(CFLAGS) $(INCLUDES) $(DEFINES) -o $(OBJDIR)$@ $<
% }
% if (args.project.device == "awr294x") {
$(OBJDIR)/%.obj %.obj: %.asm
@echo Compiling: $(LIBNAME): $<
% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") {
$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$<
% }
% if (args.project.cgt == "ti-arm-clang") {
$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
% }
% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) {
$(CC) -c -x assembler-with-cpp $(CFLAGS) $(INCLUDES) $(DEFINES) -o $(OBJDIR)$@ $<
% }
% }
all: $(LIBDIR)/$(LIBNAME)
$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR)
@echo .
@echo Archiving: $(LIBNAME) to $@ ...
$(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS))
@echo Archiving: $(LIBNAME) Done !!!
@echo .
clean:
@echo Cleaning: $(LIBNAME) ...
$(RMDIR) $(OBJDIR)
$(RM) $(LIBDIR)/$(LIBNAME)
scrub:
@echo Scrubing: $(LIBNAME) ...
-$(RMDIR) obj/
-$(RMDIR) lib/
$(OBJS): | $(OBJDIR)
$(LIBDIR) $(OBJDIR):
$(MKDIR) $@
-include $(addprefix $(OBJDIR)/, $(DEPS))

20
.project/templates/makefile_projectspec.xdt Normal file
View File

@ -0,0 +1,20 @@
#
# Auto generated makefile
#
export `args.sdkPath`?=$(abspath `args.relPath`)
include $(`args.sdkPath`)/imports.mak
PROFILE?=Release
PROJECT_NAME=`args.project.name`_`args.project.board`_`args.project.cpu`_`args.project.os`_`args.project.cgt`
all:
$(CCS_ECLIPSE) -noSplash -data $(`args.sdkPath`)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
clean:
$(CCS_ECLIPSE) -noSplash -data $(`args.sdkPath`)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
export:
$(MKDIR) $(`args.sdkPath`)/ccs_projects
$(CCS_ECLIPSE) -noSplash -data $(`args.sdkPath`)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full

163
.project/templates/makefile_pru.xdt Normal file
View File

@ -0,0 +1,163 @@
% let obj = args.project;
% let projectName = `${obj.name}_${obj.board}_${obj.cpu}_${obj.os}_${obj.cgt}`;
% let projectPath = `${obj.relpath}/${obj.board}/${obj.cpu}_${obj.os}/${obj.cgt}`;
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Required input arguments:
# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path
# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path
# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path
SHELL = cmd.exe
CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include
CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3
SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
GEN_OPTS__FLAG :=
GEN_CMDS__FLAG :=
ORDERED_OBJS += \
"./`obj.pru_main_file`.obj" \
"$(MCU_PLUS_SDK_PATH)/`projectPath`/`obj.pru_linker_file`.cmd" \
$(GEN_CMDS__FLAG) \
-llibc.a \
% // review these include files
-include ../makefile.init
RM := DEL /F
RMDIR := RMDIR /S/Q
# Every subdirectory with source files must be described here
SUBDIRS := \
. \
# Add inputs and outputs from these tool invocations to the build variables
CMD_SRCS += \
$(MCU_PLUS_SDK_PATH)/`projectPath`/`obj.pru_linker_file`.cmd \
ASM_SRCS += \
$(MCU_PLUS_SDK_PATH)/`obj.relpath`/`obj.pru_main_file`.asm
OBJS += \
./`obj.pru_main_file`.obj
ASM_DEPS += \
./`obj.pru_main_file`.d
OBJS__QUOTED += \
"`obj.pru_main_file`.obj"
ASM_DEPS__QUOTED += \
"`obj.pru_main_file`.d"
ASM_SRCS__QUOTED += \
"$(MCU_PLUS_SDK_PATH)/`obj.relpath`/`obj.pru_main_file`.asm"
% let commandString = "";
% let cflags = obj.cflags;
% for (let prop in cflags) {
% if ( cflags.hasOwnProperty(prop) && Array.isArray(cflags[prop]) && prop == 'common') {
% for(let val of cflags[prop]) {
% commandString += `${val} `;
% }
% }
% }
% let defines = obj.defines;
% for (let prop in defines) {
% if ( defines.hasOwnProperty(prop) && Array.isArray(defines[prop]) && prop == 'common') {
% for(let val of defines[prop]) {
% commandString += `--define=${val} `;
% }
% }
% }
% let cmdSubStr = commandString;
% commandString += `--include_path="$(CCS_PATH)" `;
% if ("postBuildSteps" in obj || obj["defaultPruPostBuildSteps"]) {
% commandString += `--include_path="$(SYSCFG_DIR)" `;
% }
% let includes = obj.includes;
% for (let prop in includes) {
% if ( includes.hasOwnProperty(prop) && Array.isArray(includes[prop]) && prop == 'common') {
% for(let val of includes[prop]) {
% commandString += `--include_path="${val}" `;
% }
% }
% }
# Each subdirectory must supply rules for building sources it contributes
`obj.pru_main_file`.obj: $(MCU_PLUS_SDK_PATH)/`obj.relpath`/`obj.pru_main_file`.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
@echo 'Building file: "$<"'
@echo 'Invoking: PRU Compiler'
"$(CG_TOOL_ROOT)/bin/clpru" `commandString` --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
@echo 'Finished building: "$<"'
@echo ' '
LIBS := -llibc.a
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
EXE_OUTPUTS += \
`projectName`.out \
EXE_OUTPUTS__QUOTED += \
"`projectName`.out" \
BIN_OUTPUTS += \
`projectName`.hex \
BIN_OUTPUTS__QUOTED += \
"`projectName`.hex" \
# All Target
all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
@$(MAKE) --no-print-directory -Onone "`projectName`.out"
# Tool invocations
% // # TODO: ti-cgt specific settings
`projectName`.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
@echo 'Building target: "$@"'
@echo 'Invoking: PRU Linker'
"$(CG_TOOL_ROOT)/bin/clpru" `cmdSubStr` --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"`projectName`.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="`projectName`_linkInfo.xml" --rom_model -o "`projectName`.out" $(ORDERED_OBJS)
@echo 'Finished building target: "$@"'
@echo ' '
@$(MAKE) --no-print-directory post-build
`projectName`.hex: $(EXE_OUTPUTS)
@echo 'Building secondary target: "$@"'
@echo 'Invoking: PRU Hex Utility'
"$(CG_TOOL_ROOT)/bin/hexpru" -o "`projectName`.hex" $(EXE_OUTPUTS__QUOTED)
@echo 'Finished building secondary target: "$@"'
@echo ' '
@$(MAKE) --no-print-directory post-build
# Other Targets
clean:
-$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED)
-$(RM) "`obj.pru_main_file`.obj"
-$(RM) "`obj.pru_main_file`.d"
-@echo 'Finished clean'
-@echo ' '
% if("postBuildSteps" in obj) {
post-build:
% steps = obj.postBuildSteps;
% for (let step of steps) {
-`step.slice(0, step.length-1)`
% }
-@echo ' '
% }
% if(obj["defaultPruPostBuildSteps"]) {
post-build:
-$(CG_TOOL_ROOT)/bin/hexpru.exe ${MCU_PLUS_SDK_PATH}/`projectPath`/hexpru.cmd `projectName`.out
-${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe `projectName`.b00 pru_load_bin.h PRUFirmware 4
-@echo ' '
% }
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets

221
.project/templates/makefile_system.xdt Normal file
View File

@ -0,0 +1,221 @@
#
# Auto generated makefile
#
export `args.sdkName`?=$(abspath `args.relPath`)
include $(`args.sdkName`)/imports.mak
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
include $(`args.sdkName`)/devconfig/devconfig.mak
% }
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif
% }
PROFILE?=release
MULTI_CORE_BOOTIMAGE_PATH=$(abspath .)
MULTI_CORE_BOOTIMAGE_NAME:=`args.project.name`_system.$(PROFILE).appimage
MULTI_CORE_BOOTIMAGE_NAME_SIGNED:=$(MULTI_CORE_BOOTIMAGE_NAME).signed
MULTI_CORE_BOOTIMAGE_NAME_XIP:=`args.project.name`_system.$(PROFILE).appimage_xip
% if (args.project.device == "awr294x") {
MULTI_CORE_BOOTIMAGE_NAME_QSPI:=`args.project.name`_system.$(PROFILE).appimage_qspi
% }
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
MULTI_CORE_BOOTIMAGE_NAME_HS:=$(MULTI_CORE_BOOTIMAGE_NAME).hs
% }
% let numProjects = 0;
% for (let project of args.project.projects) {
CORE_`numProjects`=--script ../`project.cpu`_`project.os`/example.syscfg --context `args.device.getSysCfgCpu(project.cpu)` --output ../`project.cpu`_`project.os`/`project.cgt`/generated
% numProjects = numProjects + 1;
% }
CORES = \
% for (let i = numProjects-1; i>=0; i--) {
$(CORE_`i`) \
% }
all: syscfg
% for (let project of args.project.projects) {
$(MAKE) -C ../`project.cpu`_`project.os`/`project.cgt`/ all
% }
$(MAKE) $(MULTI_CORE_BOOTIMAGE_NAME)
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
ifeq ($(DEVICE_TYPE), HS)
$(MAKE) $(MULTI_CORE_BOOTIMAGE_NAME_HS)
endif
% }
% for (let project of args.project.projects) {
% if (project.isLinuxFwGen) {
$(COPY) ../`project.cpu`_`project.os`/`project.cgt`/`args.device.getLinuxFwName(project.cpu)` .
% }
% }
clean:
% for (let project of args.project.projects) {
$(MAKE) -C ../`project.cpu`_`project.os`/`project.cgt`/ clean
% }
$(RM) $(MULTI_CORE_BOOTIMAGE_NAME)
$(RM) $(MULTI_CORE_BOOTIMAGE_NAME_SIGNED)
$(RM) $(MULTI_CORE_BOOTIMAGE_NAME_XIP)
% if (args.project.device == "awr294x") {
$(RM) $(MULTI_CORE_BOOTIMAGE_NAME_QSPI)
% }
% for (let project of args.project.projects) {
% if (project.isLinuxFwGen) {
$(RM) `args.device.getLinuxFwName(project.cpu)`
% }
% }
scrub:
% for (let project of args.project.projects) {
$(MAKE) -C ../`project.cpu`_`project.os`/`project.cgt`/ scrub
% }
% for (let project of args.project.projects) {
% if (project.isLinuxFwGen) {
$(RM) `args.device.getLinuxFwName(project.cpu)`
% }
% }
ifeq ($(OS),Windows_NT)
$(RM) \*.appimage
$(RM) \*.appimage.signed
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
$(RM) \*.appimage.hs
% }
$(RM) \*.appimage_xip
else
$(RM) *.appimage
$(RM) *.appimage.signed
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
$(RM) \*.appimage.hs
% }
$(RM) *.appimage_xip
endif
syscfg:
@echo Generating SysConfig files ...
$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) $(CORES)
syscfg-gui:
$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device `args.device.getSysCfgDevice(args.project.board)` --part `args.device.getSysCfgPart(args.project.board)` --package `args.device.getSysCfgPkg(args.project.board)` $(CORES)
#
# Generation of multi-core boot image which can be loaded by Secondary Boot Loader (SBL)
#
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
% if (args.project.device == "am64x") {
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if (args.project.device == "am243x") {
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if (args.project.device == "am263x") {
BOOTIMAGE_CORE_ID_r5fss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-1 = 1
BOOTIMAGE_CORE_ID_r5fss1-0 = 2
BOOTIMAGE_CORE_ID_r5fss1-1 = 3
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) {
BOOTIMAGE_CORE_ID_r5fss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-1 = 1
BOOTIMAGE_CORE_ID_c66ss0 = 2
% if (args.project.device == "awr294x") {
BOOTIMAGE_CORE_ID_r4 = 3
R4_RPRC_PATH = $(MCU_PLUS_SDK_PATH)/source/drivers/bootloader/soc/awr294x/xwr2xxx_radarss_metarprc.bin
% }
SBL_RUN_ADDRESS=0x10200000
SBL_DEV_ID=55
% }
% if (args.project.device == "am62x") {
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
BOOTIMAGE_CORE_ID_a53ss0-1 = 1
BOOTIMAGE_CORE_ID_a53ss1-0 = 2
BOOTIMAGE_CORE_ID_a53ss1-1 = 3
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_m4fss0-0 = 5
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
% if ((args.project.device == "am243x") || (args.project.device == "am64x")) {
APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py
% }
MULTI_CORE_APP_PARAMS = \
% for (let project of args.project.projects) {
../`project.cpu`_`project.os`/`project.cgt`/`args.project.name`.$(PROFILE).rprc@$(BOOTIMAGE_CORE_ID_`project.cpu`) \
% }
MULTI_CORE_APP_PARAMS_XIP = \
% for (let project of args.project.projects) {
../`project.cpu`_`project.os`/`project.cgt`/`args.project.name`.$(PROFILE).rprc_xip@$(BOOTIMAGE_CORE_ID_`project.cpu`) \
% }
% if (args.project.device == "awr294x") {
MULTI_CORE_APP_PARAMS_QSPI = $(MULTI_CORE_APP_PARAMS) $(R4_RPRC_PATH)@$(BOOTIMAGE_CORE_ID_r4)
% }
MULTI_CORE_BOOTIMAGE_DEPENDENCY = \
% for (let project of args.project.projects) {
../`project.cpu`_`project.os`/`project.cgt`/`args.project.name`.$(PROFILE).rprc \
% }
$(MULTI_CORE_BOOTIMAGE_DEPENDENCY):
$(MULTI_CORE_BOOTIMAGE_NAME): $(MULTI_CORE_BOOTIMAGE_DEPENDENCY)
@echo Boot multi-core image: $@ ...
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME) $(MULTI_CORE_APP_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME_XIP) $(MULTI_CORE_APP_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
% if (args.project.device == "awr294x") {
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME_QSPI) $(MULTI_CORE_APP_PARAMS_QSPI) >> $(BOOTIMAGE_TEMP_OUT_FILE)
% }
$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
@echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_PATH)/$@ Done !!!
@echo .
% if ((args.project.device == "am243x") || (args.project.device == "am64x")) {
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME).hs_fs
@echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_PATH)/$(MULTI_CORE_BOOTIMAGE_NAME).hs_fs Done !!!
@echo .
$(MULTI_CORE_BOOTIMAGE_NAME_HS): $(MULTI_CORE_BOOTIMAGE_NAME)
ifeq ($(DEVICE_TYPE),HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME_HS)
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME_HS)
$(RM) $(MULTI_CORE_BOOTIMAGE_NAME)-enc
endif
@echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_PATH)/$@ Done !!!
@echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_PATH)/$(MULTI_CORE_BOOTIMAGE_NAME_HS) Done !!!
@echo .
endif
% }

153
.project/templates/makefile_system_ccs_bootimage_gen.xdt Normal file
View File

@ -0,0 +1,153 @@
#
# Auto generated makefile
#
# Below variables need to be defined outside this file or via command line
# - MCU_PLUS_SDK_PATH
# - PROFILE
# - OUTNAME
# - CCS_INSTALL_DIR
CCS_PATH=$(CCS_INSTALL_DIR)
include $(`args.sdkName`)/imports.mak
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
include $(`args.sdkName`)/devconfig/devconfig.mak
% }
% if ((args.project.device == "am64x") || (args.project.device == "am243x")) {
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif
% }
MULTI_CORE_BOOTIMAGE_PATH=$(abspath $(PROFILE))
MULTI_CORE_BOOTIMAGE_NAME:=$(PROFILE)/$(OUTNAME).appimage
MULTI_CORE_BOOTIMAGE_NAME_SIGNED:=$(PROFILE)/$(OUTNAME).appimage.signed
MULTI_CORE_BOOTIMAGE_NAME_XIP:=$(PROFILE)/$(OUTNAME).appimage_xip
% if (args.project.device == "awr294x") {
MULTI_CORE_BOOTIMAGE_NAME_QSPI:=$(PROFILE)/$(OUTNAME).appimage_qspi
% }
#
# Generation of multi-core boot image which can be loaded by Secondary Boot Loader (SBL)
#
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
% if (args.project.device == "am64x") {
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if (args.project.device == "am243x") {
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if (args.project.device == "am263x") {
BOOTIMAGE_CORE_ID_r5fss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-1 = 1
BOOTIMAGE_CORE_ID_r5fss1-0 = 2
BOOTIMAGE_CORE_ID_r5fss1-1 = 3
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) {
BOOTIMAGE_CORE_ID_r5fss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-1 = 1
BOOTIMAGE_CORE_ID_c66ss0 = 2
% if (args.project.device == "awr294x") {
BOOTIMAGE_CORE_ID_r4 = 3
R4_RPRC_PATH = $(MCU_PLUS_SDK_PATH)/source/drivers/bootloader/soc/awr294x/xwr2xxx_radarss_metarprc.bin
% }
SBL_RUN_ADDRESS=0x10200000
SBL_DEV_ID=55
% }
% if (args.project.device == "am62x") {
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
BOOTIMAGE_CORE_ID_a53ss0-1 = 1
BOOTIMAGE_CORE_ID_a53ss1-0 = 2
BOOTIMAGE_CORE_ID_a53ss1-1 = 3
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_m4fss0-0 = 5
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
% }
MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
% if ((args.project.device == "am243x") || (args.project.device == "am64x")) {
APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py
% }
MULTI_CORE_APP_PARAMS = \
% for (let project of args.project.projects) {
../`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`/$(PROFILE)/`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`.rprc@$(BOOTIMAGE_CORE_ID_`project.cpu`) \
% }
MULTI_CORE_APP_PARAMS_XIP = \
% for (let project of args.project.projects) {
../`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`/$(PROFILE)/`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`.rprc_xip@$(BOOTIMAGE_CORE_ID_`project.cpu`) \
% }
% if (args.project.device == "awr294x") {
MULTI_CORE_APP_PARAMS_QSPI = $(MULTI_CORE_APP_PARAMS) $(R4_RPRC_PATH)@$(BOOTIMAGE_CORE_ID_r4)
% }
all:
ifeq ($(CCS_IDE_MODE),cloud)
# No post build steps
else
@echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME) ...
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME) $(MULTI_CORE_APP_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME_XIP) $(MULTI_CORE_APP_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
% if (args.project.device == "awr294x") {
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME_QSPI) $(MULTI_CORE_APP_PARAMS_QSPI) >> $(BOOTIMAGE_TEMP_OUT_FILE)
% }
% if ((args.project.device == "am243x") || (args.project.device == "am64x")) {
# Sign the appimage for HS-FS using appimage signing script
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME).hs_fs
% }
% if ((args.project.device == "am243x") || (args.project.device == "am64x")) {
ifeq ($(DEVICE_TYPE),HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME).hs
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME).hs
$(RM) $(MULTI_CORE_BOOTIMAGE_NAME)-enc
endif
endif
% }
% for (let project of args.project.projects) {
% if (project.isLinuxFwGen) {
$(COPY) ../`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`/$(PROFILE)/`args.device.getLinuxFwName(project.cpu)` $(PROFILE)/
% }
% }
% if ((args.project.device == "am243x") || (args.project.device == "am64x")) {
ifeq ($(DEVICE_TYPE),HS)
@echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME).hs Done !!!
else
@echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME) Done !!!
@echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME).hs_fs Done !!!
endif
% } else {
@echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME) Done !!!
% }
@echo .
endif

23
.project/templates/makefile_system_projectspec.xdt Normal file
View File

@ -0,0 +1,23 @@
#
# Auto generated makefile
#
export `args.sdkName`?=$(abspath `args.relPath`)
include $(`args.sdkName`)/imports.mak
export PROFILE?=Release
PROJECT_NAME=`args.project.name`_`args.project.board`_system_`args.project.tag`
all:
$(CCS_ECLIPSE) -noSplash -data $(`args.sdkName`)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
clean:
$(CCS_ECLIPSE) -noSplash -data $(`args.sdkName`)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
% for (let project of args.project.projects) {
$(MAKE) -C ../`project.cpu`_`project.os`/`project.cgt`/ -f makefile_projectspec clean
% }
export:
$(MKDIR) $(`args.sdkName`)/ccs_projects
$(CCS_ECLIPSE) -noSplash -data $(`args.sdkName`)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec system.projectspec -ccs.overwrite full

21
.project/templates/package.ccs.json.xdt Normal file
View File

@ -0,0 +1,21 @@
%%{
productName = args.utils.getProductNameProjectSpec(args.device);
%%}
[
{
"rootMacroName": "COM_TI_`productName`_INSTALL_DIR",
"compilerIncludePath": [ ],
"compilerSymbols": [ ],
"linkerSearchPath": [ ],
"properties": {
"rtsc.repositories": [
"source",
"."
]
},
"helpTocs": [
],
"docs": [
]
}
]

38
.project/templates/package.tirex.json.xdt Normal file
View File

@ -0,0 +1,38 @@
%%{
productName = args.utils.getProductNameProjectSpec(args.device);
isDevelopmentMode = args.common.isDevelopmentMode();
deviceName = args.utils.getProjectSpecDevice(args.device);
if(args.device == "am273x")
deviceName = "AM273x"
if(args.device == "am62x")
deviceName = "AM62x"
if(isDevelopmentMode)
deviceName = "AMXXX";
%%}
[
{
"metadataVersion": "3.01.00",
"id": "com.ti.`productName`",
"name": "MOTOR CONTROL SDK for `deviceName`",
"rootCategory": [ "MOTOR CONTROL SDK", "MOTOR CONTROL SDK for `deviceName`" ],
"version": "09.00.00.01",
"type": "software",
"image": "./mcu_plus_sdk.png",
% if ((args.device == "am64x") || (args.device == "am243x") || (isDevelopmentMode)) {
"license": "../../license.txt",
% }
"devices": ["`deviceName`"],
"tags": ["SDK", "Baremetal", "FreeRTOS"],
"description": "Welcome to MOTOR CONTROL SDK for `deviceName`. This SDK contains examples, libraries and tools to develop RTOS and no-RTOS based applications for ARM R5F, ARM M4F CPUs and related peripherals.",
"dependencies": [
{ "packageId": "sysconfig", "version": "`args.utils.getSysCfgVersionProjectSpec()`", "require": "mandatory" },
% if (args.device == "am64x" || (isDevelopmentMode)) {
{ "packageId": "ti_cgt_tiarmclang", "version": "`args.utils.getTiClangVersionProjectSpec()`", "require": "mandatory" },
{ "packageId": "arm.gnu.aarch64-none", "version": "`args.utils.getGCCAarch64NoneVersionProjectSpec()`", "require": "mandatory" }
% }
% else {
{ "packageId": "ti_cgt_tiarmclang", "version": "`args.utils.getTiClangVersionProjectSpec()`", "require": "mandatory" }
% }
]
}
]

127
.project/templates/product.json.xdt Normal file
View File

@ -0,0 +1,127 @@
%%{
isDevelopmentMode = args.common.isDevelopmentMode();
deviceName = args.utils.getProjectSpecDevice(args.device);
if(args.device == "am62x")
deviceName = "AM62x"
sysCfgVersion = args.utils.getSysCfgVersionProjectSpec();
%%}
{
% if(isDevelopmentMode) {
"name": "MOTOR_CONTROL_SDK",
"displayName": "MOTOR CONTROL SDK",
% } else {
"name": "MOTOR_CONTROL_SDK_`deviceName`",
"displayName": "MOTOR CONTROL SDK for `deviceName`",
% }
"version": "09.00.00",
"documentationPath": "../docs",
"includePaths": [
"../source",
],
"components": [
% if((args.device == "am64x") || (args.device == "am243x")) {
"/motor_control/motor_control",
% }
% if(args.device == "am263x") {
"/motor_control/motor_control",
% }
% if((args.device == "am273x") || (args.device == "awr294x")) {
"/kernel/dpl",
"/drivers/drivers",
"/board/board",
"/networking/networking",
% }
% if(args.device == "am62x") {
"/kernel/dpl",
"/drivers/drivers",
"/board/board",
% }
],
"devices": [
% if((args.device == "am64x") || (isDevelopmentMode)) {
"AM64x_beta",
% }
% if((args.device == "am243x") || (isDevelopmentMode)) {
"AM243x_ALV_beta",
"AM243x_ALX_beta",
% }
% if((args.device == "am273x") || (isDevelopmentMode)) {
"AM273x",
% }
% if((args.device == "awr294x") || (isDevelopmentMode)) {
"AWR294X",
% }
% if((args.device == "am263x") || (isDevelopmentMode)) {
"AM263x_beta",
% }
% if((args.device == "am62x") || (isDevelopmentMode)) {
"AM62x",
% }
],
"contexts": {
% if((args.device == "am64x") || (isDevelopmentMode)) {
"AM64x_beta": [
"r5fss0-0",
"r5fss0-1",
"r5fss1-0",
"r5fss1-1",
"m4fss0-0",
"a53ss0-0",
],
% }
% if((args.device == "am243x") || (isDevelopmentMode)) {
"AM243x_ALV_beta": [
"r5fss0-0",
"r5fss0-1",
"r5fss1-0",
"r5fss1-1",
"m4fss0-0",
],
"AM243x_ALX_beta": [
"r5fss0-0",
"r5fss0-1",
"r5fss1-0",
"r5fss1-1",
"m4fss0-0",
],
% }
% if((args.device == "am273x") || (isDevelopmentMode)) {
"AM273x": [
"r5fss0-0",
"r5fss0-1",
"c66ss0",
"hsm0-0",
],
% }
% if((args.device == "awr294x") || (isDevelopmentMode)) {
"AWR294X": [
"r5fss0-0",
"r5fss0-1",
"c66ss0",
"hsm0-0",
],
% }
% if((args.device == "am263x") || (isDevelopmentMode)) {
"AM263x_beta": [
"r5fss0-0",
"r5fss0-1",
"r5fss1-0",
"r5fss1-1",
"hsm0-0",
],
% }
% if((args.device == "am62x") || (isDevelopmentMode)) {
"AM62x": [
"m4fss0-0",
],
% }
},
"pinmuxUIOptions": {
"group": "merged",
"hidePeripheralTab": false,
"showPinTable": true,
"showSignals": true,
"showUsed": true
},
"minToolVersion" : "`sysCfgVersion`"
}

303
.project/templates/projectspec_executable.xdt Normal file
View File

@ -0,0 +1,303 @@
%%{
let profile_list = ["debug", "release"];
products = "";
if("syscfgfile" in args.project) {
products+=`sysconfig;`
}
products+=`com.ti.${args.utils.getProductNameProjectSpec(args.project.device)};`
productName = args.utils.getProductNameProjectSpec(args.project.device);
products+=`com.ti.${args.utils.getDependentProductNameProjectSpec(args.project.device)}`
dependentProductName = args.utils.getDependentProductNameProjectSpec(args.project.device);
if(args.project.projecspecFileAction) // should be renamed to projectspecFileAction
{
defaultAction = args.project.projecspecFileAction;
}
else
{
defaultAction = args.utils.getDefaultActionProjectSpec();
}
%%}
<?xml version="1.0" encoding="UTF-8"?>
<projectSpec>
<applicability>
<when>
<context
% obj = args.project
deviceFamily="`args.utils.getDeviceFamilyProjectSpec(obj.cpu)`"
deviceId="`args.utils.getDeviceIdProjectSpec(obj.device, obj.cpu, obj.board)`"
/>
</when>
</applicability>
% if("importOtherProject" in args.project) {
<import spec="`args.project.importOtherProject`"/>
% }
<project
% obj = args.project
title="`args.utils.getTitleProjectSpec(args.project.name)`"
name = "`obj.name`_`obj.board`_`obj.cpu`_`obj.os`_`obj.cgt`"
products="`products`"
configurations="
% if(args.project.device == "am263x")
%{
`args.utils.capitalize(profile_list[1])`,
`args.utils.capitalize(profile_list[0])`,
%}
% else
%{
% for (profile of profile_list) {
`args.utils.capitalize(profile)`,
% }
% }
"
connection="TIXDS110_Connection.xml"
toolChain="`args.utils.getToolChainProjectSpec(obj.cgt)`"
% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) {
toolVersion="`args.utils.getToolChainVersionProjectSpec(obj.cgt)`"
% }
% else {
cgtVersion="`args.utils.getToolChainVersionProjectSpec(obj.cgt)`"
% }
device="`args.utils.getDeviceIdProjectSpec(obj.device, obj.cpu, obj.board)`"
deviceCore="`args.utils.getProjectSpecCpu(obj.device, obj.cpu)`"
ignoreDefaultDeviceSettings="true"
% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) { /* we need to make this as false to that --start-group ... --end-group is used with libraries */
ignoreDefaultCCSSettings="false"
% } else {
ignoreDefaultCCSSettings="true"
% }
endianness="little"
outputFormat="ELF"
outputType="`args.utils.getOutputTypeProjectSpec(obj.type)`"
compilerBuildOptions="
% obj = args.project.includes;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') {
% for(let val of obj[prop]) {
-I`val`
% }
% }
% }
% obj = args.project.cflags;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') {
% for(let val of obj[prop]) {
`val`
% }
% }
% }
% obj = args.project.defines;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') {
% for(let val of obj[prop]) {
-D`val.replace(/\"/g, '&quot;')`
% }
% }
% }
"
linkerBuildOptions="
% obj = args.project.libdirs;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') {
% for(let val of obj[prop]) {
% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) {
-L`val`
% } else {
-i`val`
% }
% }
% }
% }
% obj = args.project
% if (obj.hasOwnProperty('projectspecLnkPath')) {
% obj = args.project.projectspecLnkPath;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') {
% for(let val of obj[prop]) {
-i`val`
% }
% }
% }
% }
% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) {
-Wl,-Map=`args.project.name`.${ConfigName}.map
% } else {
-m=`args.project.name`.${ConfigName}.map
% }
% obj = args.project.lflags;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') {
% for(let val of obj[prop]) {
`val`
% }
% }
% }
"
% if("preBuildSteps" in args.project) {
preBuildStep="
% steps = args.project.preBuildSteps;
% for (let step of steps) {
`step`
% }
"
% }
% if(args.project["enableHexTool"]) {
enableHexTool="true"
hexBuildOptions="
% let options = args.project.hexBuildOptions;
% for (let option of options) {
`option`
% }
"
% }
% obj = args.project;
% let projectName = `${obj.name}_${obj.board}_${obj.cpu}_${obj.os}_${obj.cgt}`;
% let projectPath = `${obj.relpath}/${obj.board}/${obj.cpu}_${obj.os}/${obj.cgt}`;
% if(args.project["defaultPruPostBuildSteps"]) {
postBuildStep="
$(CG_TOOL_ROOT)/bin/hexpru.exe ${MCU_PLUS_SDK_PATH}/`projectPath`/hexpru.cmd `projectName`.out;
${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe `projectName`.b00 pru_load_bin.h PRUFirmware 4;
"
% }
% if("postBuildSteps" in args.project) {
postBuildStep="
% steps = args.project.postBuildSteps;
% for (let step of steps) {
`step`
% }
"
% } else if (args.project.cpu.includes("pru")) {
% } else {
postBuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=`args.project.device`"
% }
% if("syscfgfile" in args.project) {
enableSysConfigTool="true"
sysConfigBuildOptions="
--context `args.syscfg.cpu` --part `args.syscfg.part` --package `args.syscfg.pkg`
"
% }
description="A `args.utils.getTitleProjectSpec(args.project.name)` `args.project.os.toUpperCase()` project">
% for (profile of profile_list ) {
<configuration name="`args.utils.capitalize(profile)`"
compilerBuildOptions="
% obj = args.project.includes;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop] && prop == profile) ) {
% for(let val of obj[prop]) {
-I`val`
% }
% }
% }
% obj = args.project.cflags;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == profile) {
% for(let val of obj[prop]) {
`val`
% }
% }
% }
% obj = args.project.defines;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == profile) {
% for(let val of obj[prop]) {
`val`
% }
% }
% }
"
linkerBuildOptions="
% obj = args.project.libdirs;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop] && prop == profile) ) {
% for(let val of obj[prop]) {
-i`val`
% }
% }
% }
% obj = args.project.libs;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') {
% for(let val of obj[prop]) {
-l`args.utils.replace(val, '${ConfigName}',profile)`
% }
% }
% }
% obj = args.project.libs;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == profile) {
% for(let val of obj[prop]) {
-l`val`
% }
% }
% }
% obj = args.project.lflags;
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop] && prop == profile) ) {
% for(let val of obj[prop]) {
`val`
% }
% }
% }
"
></configuration>
% }
% if(args.project.device == "am273x") {
<pathVariable name="DSPLIB_PATH" path="${COM_TI_`productName`_INSTALL_DIR}/source/dsplib_c66x_3_4_0_0" scope="project" />
% }
<pathVariable name="MCU_PLUS_SDK_PATH" path="${COM_TI_`dependentProductName`_INSTALL_DIR}" scope="project" />
<pathVariable name="`args.sdkName`" path="${COM_TI_`productName`_INSTALL_DIR}" scope="project" />
% filelist = args.utils.getFileListProjectSpec(args.project.files, args.project.filedirs, args.project.dirPath)
% for (file of filelist) {
<file path="`file`" openOnCreation="false" excludeFromBuild="false" action="`defaultAction`">
</file>
% }
% filelist = args.utils.getFileListProjectSpec(args.project.projectspecfiles, args.project.filedirs, args.project.dirPath)
% for (file of filelist) {
<file path="`file`" openOnCreation="false" excludeFromBuild="false" action="`defaultAction`">
</file>
% }
% obj = args.project.lnkfiles
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') {
% for(let val of obj[prop]) {
<file path="`val`" openOnCreation="false" excludeFromBuild="false" action="`defaultAction`">
</file>
% }
% }
% }
% if("syscfgfile" in args.project) {
<file path="`args.project.syscfgfile`" openOnCreation="false" excludeFromBuild="false" action="`defaultAction`">
</file>
% }
% if("readmeDoxygenPageTag" in args.project) {
<file path="${`args.sdkName`}/docs/api_guide_`args.project.device`/`args.project.readmeDoxygenPageTag`.html"
openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
</file>
% }
% obj = args.project.projectspec_files
% for (prop in obj) {
% if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') {
% for(let val of obj[prop]) {
<file path="`val`" openOnCreation="false" excludeFromBuild="true" action="`defaultAction`">
</file>
% }
% }
% }
% if("syscfgfile" in args.project) {
<file path="syscfg_c.rov.xs" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
% }
% if(args.project.skipMakefileCcsBootimageGen) {} else {
<file path="makefile_ccs_bootimage_gen" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
% }
</project>
</projectSpec>

36
.project/templates/projectspec_system.xdt Normal file
View File

@ -0,0 +1,36 @@
%%{
products = "";
products+=`com.ti.${args.utils.getProductNameProjectSpec(args.project.projects[0].device)}`
productName = args.utils.getProductNameProjectSpec(args.project.projects[0].device);
%%}
<?xml version="1.0" encoding="UTF-8"?>
<projectSpec>
% for (let project of args.project.projects) {
<import spec="../`project.cpu`_`project.os`/`project.cgt`/example.projectspec"/>
% }
<project
name="`args.project.name`_`args.project.board`_system_`args.project.tag`"
products="`products`"
configurations="
Debug,
Release,
"
connection="TIXDS110_Connection.xml"
device="Cortex R.`args.device.getProjectSpecDevice(args.project.board)`"
outputType="system"
toolChain="TICLANG"
>
<pathVariable name="`args.sdkName`" path="${COM_TI_`productName`_INSTALL_DIR}" scope="project" />
% if("readmeDoxygenPageTag" in args.project) {
<file path="${`args.sdkName`}/docs/api_guide_`args.project.device`/`args.project.readmeDoxygenPageTag`.html"
openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
</file>
% }
<file path="system.xml" action="copy" openOnCreation="true"/>
<file path="makefile_system_ccs_bootimage_gen" action="copy" openOnCreation="false"/>
<configuration name="Debug"
></configuration>
<configuration name="Release"
></configuration>
</project>
</projectSpec>

8
.project/templates/syscfg_c.rov.xs.xdt Normal file
View File

@ -0,0 +1,8 @@
/*
* ======== syscfg_c.rov.xs ========
* This file contains the information needed by the Runtime Object
* View (ROV) tool.
*/
var crovFiles = [
"kernel/freertos/rov/FreeRTOS.rov.js",
];

16
.project/templates/system.xml.xdt Normal file
View File

@ -0,0 +1,16 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<system>
% let num = 0;
% for (let project of args.project.projects) {
<project configuration="@match" id="project_`num`" name="`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`">
</project>
<core id="`args.device.getProjectSpecCpu(project.cpu)`" project="project_`num`"/>
% num = num + 1;
% }
<preBuildSteps>
</preBuildSteps>
<postBuildSteps>
<step command="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_system_ccs_bootimage_gen OUTNAME=`args.project.name`_system PROFILE=${ConfigName} MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE}"/>
</postBuildSteps>
</system>

1
.project/templates/tirex_content.xdt Normal file
View File

@ -0,0 +1 @@
`JSON.stringify(args.tirex_content_list, null, " ")`

6
CONTRIBUTING.md Normal file
View File

@ -0,0 +1,6 @@
# Contributing to this project
This project is currently not accepting any contributions.
We expect to accept contributions in 2Q23.

1
LICENSE.md Normal file
View File

@ -0,0 +1 @@
Please refer to docs/manifest.html for license information.

269
README.md Normal file
View File

@ -0,0 +1,269 @@
<div align="center">
<img src="https://upload.wikimedia.org/wikipedia/commons/b/ba/TexasInstruments-Logo.svg" width="150"><br/>
# Motor Control SDK
[Introduction](#introduction) | [Features](#features) | [Overview](#overview) | [Learn](#learn) | [Usage](#usage) | [Contribute](#contributing-to-the-project)
</div>
## Introduction
The Motor Control SDK enables real-time industrial communications for TI processors. Industrial communication is typically handled by the Programmable Real-Time Unit Industrial Communication Subsystem (PRU-ICSS). The PRU-ICSS is a co-processor subsystem containing Programmable Real-Time (PRU) cores and Ethernet media access controllers (EMACs), which implement the low level industrial Ethernet and fieldbus protocols through firmware.
These devices currently include
- [AM2431](https://www.ti.com/product/AM2431), [AM2432](https://www.ti.com/product/AM2432), [AM2434](https://www.ti.com/product/AM2434)
- [AM2634](https://www.ti.com/product/AM2634), [AM2634-Q1](https://www.ti.com/product/AM2634-Q1)
- [AM6411](https://www.ti.com/product/AM6411), [AM6412](https://www.ti.com/product/AM6412), [AM6421](https://www.ti.com/product/AM6421), [AM6422](https://www.ti.com/product/AM6422), [AM6441](https://www.ti.com/product/AM6441), [AM6442](https://www.ti.com/product/AM6442)
## Features
- Out of Box peripheral and application Examples
- Application Level Examples: Motor Drives, Industrial Communications etc.
- Protocol stacks and middleware
- Various Industrial Protocol Stacks
- Industrial protocol firmware
- ICCSG, ICSSM etc.
## Overview
## Learn
## Usage
### Prerequisites
#### Supported HOST environments
- Windows 10 64bit
- Ubuntu 18.04 64bit
### Clone and build from GIT
#### Repo Tool Setup
Motor Control SDK has multiple components (in multiple repositories) and dependencies
(like compiler, CCS and other tools). We use repo tool from Google to manage these
multiple repositories. Currently there is no support for native windows shells like
CMD or Powershell. This will be added at a later point. Windows users can rely on
Git Bash for the repo setup. Follow the below mentioned steps to setup repo tool:
Make sure [python3 is installed](https://wiki.python.org/moin/BeginnersGuide/Download) and is in your OS path.
- Linux:
Do the following in terminal
```bash
curl https://storage.googleapis.com/git-repo-downloads/repo > ~/bin/repo
chmod a+x ~/bin/repo
echo "PATH=$HOME/bin:$PATH" >> ~/.bashrc
source ~/.bashrc
```
- Git-Bash (Windows)
Make sure that python 3 is callable as `python` from CMD. Do below in Git-Bash
```bash
mkdir -p /c/ti
curl https://storage.googleapis.com/git-repo-downloads/repo > /c/ti/repo
echo "alias repo=\"winpty python /c/ti/repo\"" >> ~/.bashrc
source ~/.bashrc
```
#### Cloning The Repositories
To clone the repositories using repo tool, do below in your workarea folder:
Note that depending on the SoC you're working with, the components you clone might be
slightly different. So please choose the manifest folder according to the SoC of your
interest. For example, we are showing for am263x below.
```bash
repo init -u https://github.com/TexasInstruments/industrial-comms-manifests.git -m am243x/dev.xml -b main
```
Note that repo uses symbolic links. So if you're on Windows and do not have permissions
to create symbolic links, the above command might fail for you. So you can either enable them
([refer this link](https://portal.perforce.com/s/article/3472)) or use the experimental
worktree feature of repo. To do this, initialize the repo like so:
```bash
repo init --worktree -u https://github.com/TexasInstruments/industrial-comms-manifests.git -m am243x/dev.xml -b main
```
After the repo is initialized, do a
```bash
repo sync
```
This should clone all the repositories required for Motor Control SDK development. Now download and install the dependencies.
#### Downloading And Installing Dependencies
Note that the dependencies are also soc specific, here we take an example of am263x.
You can replace that with the SoC of your choice like the `repo init` step.
**To download and install dependencies in linux, follow the below steps**:
Run the following from the same location where you have `industrial_comms` and `industrial_comms_setup`
folders.
```bash
./industrial_comms_setup/am243x/download_components.sh
```
This will install all the required dependencies including Code Composer Studio (CCS).
The script assumes that `industrial_comms` folder is in the same location from where
you have invoked the script, and that dependencies are installed into `${HOME}/ti`
location. If these defaults don't work for you, please pass these as arguments to
the script like
```bash
./industrial_comms_setup/am243x/download_components.sh --install_dir=/path/to/tools
OR
./industrial_comms_setup/am243x/download_components.sh --industrial_comms_sdk_folder=/path/to/industrial_comms/folder
```
and so on. For a complete list of arguments you can pass to the script, please run
```bash
./industrial_comms_setup/am243x/download_components.sh -h
```
**In windows the dependencies has to be manually installed. Given below are the steps**:
1. Download and install Code Composer Studio v12.1 from [here](https://www.ti.com/tool/download/CCSTUDIO "Code Composer Studio")
- Install at default folder, C:\ti
2. Download and install SysConfig 1.14.0 from [here](https://www.ti.com/tool/download/SYSCONFIG/1.14.0.2667 "SYSCONFIG 1.14.0")
- Install at default folder, C:/ti
3. Download and install GCC for Cortex A53 and ARM R5 from below link (only needed for AM64x developers)
- [GNU-A](https://developer.arm.com/-/media/Files/downloads/gnu-a/9.2-2019.12/binrel/gcc-arm-9.2-2019.12-mingw-w64-i686-aarch64-none-elf.tar.xz)
- [GNU-RM](https://developer.arm.com/-/media/Files/downloads/gnu-rm/7-2017q4/gcc-arm-none-eabi-7-2017-q4-major-win32.zip)
- Install at default folder, C:/ti
4. Download and install Node.js v12.18.4 LTS
- Go to the [NodeJS Website](https://nodejs.org/en/) and use the installer to
download and install v12.18.4 of node. Install in the default directory.
- After successful installation, run an `npm ci` inside the `industrial_comms` folder like so:
```bash
$ cd industrial_comms/
$ npm ci
$ cd ../
```
This should install the node packages required for the SDK.
1. Download and install doxygen,
- Tested with 1.8.20
- Download the correct version of doxygen for windows from [here](https://www.doxygen.nl/download.html)
- Install and add the install path, typically, C:/Program Files/doxygen/bin to your windows PATH
- Test by doing below on the command prompt
```
$ doxygen -v
1.8.20 (<commit SHA-ID>)
```
**Installing OpenSSL**
Some of the SDK signing scripts are dependent on OpenSSL v1.1.1. The v1.1.1 is
important, OpenSSL 3.0 is not compatible with the current signing scripts of SDK.
In Windows,
- Download v1.1.1 from [here](https://slproweb.com/products/Win32OpenSSL.html)
- You can install the "light" version which is smaller download size
- Install to default path, which is C:/Program Files/OpenSSL-Win64/
- When prompted select option to install binaries to /bin folder of installed path instead of Windows system path.
- Add path to OpenSSL, to your environment "Path" variable in windows
- `C:\Program Files\OpenSSL-Win64\bin`
In Linux,
- There is a chance that OpenSSL is already installed. If not, here are the steps:
- If you have Ubuntu 18.04, do below in Linux Ubuntu shell to install openssl
-`$ sudo apt install openssl`
If you have an Ubuntu version higher than that, make sure that you install the 1.1.1 version.
You can get the 1.1.1 packages from [here](http://security.ubuntu.com/ubuntu/pool/main/o/openssl/).
The packages required are openssl, libssl and libssl-dev
Test openssl version by running `openssl version` on a command prompt and make sure there is no error.
Example output is shown below,
```bash
C:\> openssl version
OpenSSL 1.1.1k 25 Mar 2021
```
Now that the dependencies are installed, you can start the repositories with a
default branch `dev` by doing below:
```bash
repo start dev --all
```
---
**NOTE**
- In Linux, you will need to run `$HOME/ti/ccs{version}/ccs/install_scripts/install_drivers.sh` script for setting COM
port accesses correctly. Also add your user to groups `tty` and `dialout`. You can do
```
sudo adduser $USER tty
sudo adduser $USER dialout
```
- Please use the industrial communication libraries from the sdk installer due licensing restrictions.
---
### Building the SDK
#### Basic Building With Makefiles
---
**NOTE**
- Use `gmake` in windows, add path to gmake present in CCS at `C:\ti\ccsxxxx\ccs\utils\bin` to your windows PATH. We have
used `make` in below instructions.
- Unless mentioned otherwise, all below commands are invoked from root folder of the "industrial_comms" repository.
- Current supported device names are am64x, am243x, am263x, am273x and awr294x
- Pass one of these values to `"DEVICE="`
- You can also build components (examples, tests or libraries) in `release` or `debug`
profiles. To do this pass one of these values to `"PROFILE="`
---
1. Run the following command to create makefiles, this step is optional since this is invoked as part of other steps as well,
```bash
make gen-buildfiles DEVICE=am263x
```
2. To see all granular build options, run
```bash
make -s help DEVICE=am263x
```
This should show you commands to build specific libraries, examples or tests.
3. Make sure to build the libraries before attempting to build an example. For example,
to build a Hello World example for AM263x, run the following:
```bash
make -s -j4 libs DEVICE=am263x PROFILE=debug
```
Once the library build is complete, to build the example run:
```bash
make -s -C examples/hello_world/am263x-cc/r5fss0-0_nortos/ti-arm-clang all PROFILE=debug
```
4. Following are the commands to build **all libraries** and **all examples**. Valid PROFILE's are "release" or "debug"
```bash
make -s -j4 clean DEVICE=am263x PROFILE=debug
make -s -j4 all DEVICE=am263x PROFILE=debug
```

12
README_FIRST_AM243X.html Normal file
View File

@ -0,0 +1,12 @@
<html>
<head>
<title>Texas Instruments</title>
<meta http-equiv="refresh" content="0; URL=./docs/api_guide_am243x/index.html">
<meta name="keywords" content="automatic redirection">
</head>
<body>
If your browser doesn't automatically go to the SDK homepage within a few seconds,
please click
<a href="./docs/api_guide_am243x/index.html">HERE</a>
</body>
</html>

12
README_FIRST_AM263X.html Normal file
View File

@ -0,0 +1,12 @@
<html>
<head>
<title>Texas Instruments</title>
<meta http-equiv="refresh" content="0; URL=./docs/api_guide_am263x/index.html">
<meta name="keywords" content="automatic redirection">
</head>
<body>
If your browser doesn't automatically go to the SDK homepage within a few seconds,
please click
<a href="./docs/api_guide_am263x/index.html">HERE</a>
</body>
</html>

12
README_FIRST_AM64X.html Normal file
View File

@ -0,0 +1,12 @@
<html>
<head>
<title>Texas Instruments</title>
<meta http-equiv="refresh" content="0; URL=./docs/api_guide_am64x/index.html">
<meta name="keywords" content="automatic redirection">
</head>
<body>
If your browser doesn't automatically go to the SDK homepage within a few seconds,
please click
<a href="./docs/api_guide_am64x/index.html">HERE</a>
</body>
</html>

45
devconfig/devconfig.mak Normal file
View File

@ -0,0 +1,45 @@
# Device type (HS/GP)
DEVICE_TYPE?=GP
# Path to the signing tools, keys etc
SIGNING_TOOL_PATH=$(MCU_PLUS_SDK_PATH)/tools/boot/signing
# Path to the keys
ROM_DEGENERATE_KEY:=$(SIGNING_TOOL_PATH)/rom_degenerateKey.pem
ifeq ($(DEVICE),am263x)
CUST_MPK=$(SIGNING_TOOL_PATH)/mcu_custMpk.pem
else ifeq ($(DEVICE),am273x)
CUST_MPK=$(SIGNING_TOOL_PATH)/mcu_custMpk.pem
else ifeq ($(DEVICE),awr294x)
CUST_MPK=$(SIGNING_TOOL_PATH)/mcu_custMpk.pem
else
CUST_MPK=$(SIGNING_TOOL_PATH)/custMpk_am64x_am243x.pem
CUST_MEK=$(SIGNING_TOOL_PATH)/custMek_am64x_am243x.txt
endif
# Encryption option for application (yes/no)
ENC_ENABLED?=no
# Encryption option for SBL (yes/no)
ENC_SBL_ENABLED?=yes
# Debug Enable (yes/no)
DBG_ENABLED?=no
# Debug control with TIFS (yes/no)
DEBUG_TIFS?=yes
# Debug options for HS (DBG_PERM_DISABLE / DBG_SOC_DEFAULT / DBG_PUBLIC_ENABLE / DBG_FULL_ENABLE)
# This option is valid only if DEBUG_TIFS is false
DEBUG_OPTION?=DBG_SOC_DEFAULT
# Generic macros to be used depending on the device type
APP_SIGNING_KEY=
APP_ENCRYPTION_KEY=
ifeq ($(DEVICE_TYPE),HS)
APP_SIGNING_KEY=$(CUST_MPK)
APP_ENCRYPTION_KEY=$(CUST_MEK)
else
APP_SIGNING_KEY=$(ROM_DEGENERATE_KEY)
endif

671
docs/manifest.html Normal file
View File

File diff suppressed because one or more lines are too long

2091
examples/motor_control/endat_diagnostic/endat_diagnostic.c Normal file
View File

File diff suppressed because it is too large Load Diff

14
examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project.js Normal file
View File

@ -0,0 +1,14 @@
function getComponentProperty(device)
{
return require(`./project_${device}`).getComponentProperty();
};
function getComponentBuildProperty(buildOption)
{
return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption);
};
module.exports = {
getComponentProperty,
getComponentBuildProperty,
};

123
examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project_am243x.js Normal file
View File

@ -0,0 +1,123 @@
let path = require('path');
let device = "am243x";
const files = {
common: [
"endat_diagnostic.c",
"main.c",
],
};
/* Relative to where the makefile will be generated
* Typically at <example_folder>/<BOARD>/<core_os_combo>/<compiler>
*/
const filedirs = {
common: [
"..", /* core_os_combo base */
"../../../..", /* Example base */
],
};
const libdirs_freertos = {
common: [
"${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib",
"${MCU_PLUS_SDK_PATH}/source/drivers/lib",
"${MCU_PLUS_SDK_PATH}/source/board/lib",
"${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib",
],
};
const includes_freertos_r5f = {
common: [
"${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include",
"${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
"${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f",
],
};
const libs_freertos_r5f = {
common: [
"freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
"drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
"board.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
"motorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
],
};
const defines_r5f = {
common: [
"SOC_AM243X",
],
};
const lnkfiles = {
common: [
"linker.cmd",
]
};
const syscfgfile = "../example.syscfg";
const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_ENDAT";
const templates_freertos_r5f =
[
{
input: ".project/templates/am243x/common/linker_r5f.cmd.xdt",
output: "linker.cmd",
},
{
input: ".project/templates/am243x/freertos/main_freertos.c.xdt",
output: "../main.c",
options: {
entryFunction: "endat_main",
taskPri: 5,
},
}
];
const buildOptionCombos = [
{ device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"},
];
function getComponentProperty() {
let property = {};
property.dirPath = path.resolve(__dirname, "..");
property.type = "executable";
property.name = "endat_diagnostic_multi_channel_load_share";
property.isInternal = false;
property.buildOptionCombos = buildOptionCombos;
property.isSkipTopLevelBuild = false;
return property;
}
function getComponentBuildProperty(buildOption) {
let build_property = {};
build_property.files = files;
build_property.filedirs = filedirs;
build_property.lnkfiles = lnkfiles;
build_property.syscfgfile = syscfgfile;
build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
if(buildOption.cpu.match(/r5f*/)) {
if(buildOption.os.match(/freertos*/) )
{
build_property.includes = includes_freertos_r5f;
build_property.libdirs = libdirs_freertos;
build_property.libs = libs_freertos_r5f;
build_property.templates = templates_freertos_r5f;
build_property.defines = defines_r5f;
}
}
return build_property;
}
module.exports = {
getComponentProperty,
getComponentBuildProperty,
};

123
examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project_am64x.js Normal file
View File

@ -0,0 +1,123 @@
let path = require('path');
let device = "am64x";
const files = {
common: [
"endat_diagnostic.c",
"main.c",
],
};
/* Relative to where the makefile will be generated
* Typically at <example_folder>/<BOARD>/<core_os_combo>/<compiler>
*/
const filedirs = {
common: [
"..", /* core_os_combo base */
"../../../..", /* Example base */
],
};
const libdirs_freertos = {
common: [
"${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib",
"${MCU_PLUS_SDK_PATH}/source/drivers/lib",
"${MCU_PLUS_SDK_PATH}/source/board/lib",
"${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib",
],
};
const includes_freertos_r5f = {
common: [
"${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include",
"${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
"${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f",
],
};
const libs_freertos_r5f = {
common: [
"freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
"drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
"board.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
"motorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
],
};
const defines_r5f = {
common: [
"SOC_AM64X",
],
};
const lnkfiles = {
common: [
"linker.cmd",
]
};
const syscfgfile = "../example.syscfg";
const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_ENDAT";
const templates_freertos_r5f =
[
{
input: ".project/templates/am64x/common/linker_r5f.cmd.xdt",
output: "linker.cmd",
},
{
input: ".project/templates/am64x/freertos/main_freertos.c.xdt",
output: "../main.c",
options: {
entryFunction: "endat_main",
taskPri: 5,
},
}
];
const buildOptionCombos = [
{ device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"},
];
function getComponentProperty() {
let property = {};
property.dirPath = path.resolve(__dirname, "..");
property.type = "executable";
property.name = "endat_diagnostic_multi_channel_load_share";
property.isInternal = false;
property.buildOptionCombos = buildOptionCombos;
property.isSkipTopLevelBuild = false;
return property;
}
function getComponentBuildProperty(buildOption) {
let build_property = {};
build_property.files = files;
build_property.filedirs = filedirs;
build_property.lnkfiles = lnkfiles;
build_property.syscfgfile = syscfgfile;
build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
if(buildOption.cpu.match(/r5f*/)) {
if(buildOption.os.match(/freertos*/) )
{
build_property.includes = includes_freertos_r5f;
build_property.libdirs = libdirs_freertos;
build_property.libs = libs_freertos_r5f;
build_property.templates = templates_freertos_r5f;
build_property.defines = defines_r5f;
}
}
return build_property;
}
module.exports = {
getComponentProperty,
getComponentBuildProperty,
};

Some files were not shown because too many files have changed in this diff Show More