commit 5f968b0bf2166c33bb96a6ffe0c5cc24b9198854 Author: Naresh A Date: Tue Jul 4 18:02:46 2023 +0530 am64x/am243x/am263x : initial commit for motor control sdk Initial commit for motor control sdk Fixes: PINDSW-5635 Signed-off-by: Naresh A diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..09e5ee0 --- /dev/null +++ b/.gitignore @@ -0,0 +1,67 @@ +lib/ +obj/ +node_modules/ +coverage/ +docs/api_guide_* +docs/datasheet* +*.out +*.out* +*.profdata +*.map +*.zip +*.rprc +*.rprc_tmp +*.tmp +*.swp +*.rprc_xip +*.appimage +*.appimage_xip +*.appimage_qspi +*.appimage.signed +*.appimage.hs +*.appimage.hs_fs +*.bin +*.tiimage +*.tiimage.hs +*-fw +*.vscode/ +temp_stdout_*.txt +ccs_projects/ +generated/ +source/kernel/freertos/FreeRTOS-Kernel +source/kernel/freertos/FreeRTOS-Kernel-smp +source/kernel/freertos/FreeRTOS-POSIX +source/fs/freertos_fat/FreeRTOS-FAT +source/kernel/safertos/safeRTOS +source/industrial_comms/ethercat_slave/beckhoff_stack/stack_sources/*.c +source/industrial_comms/ethercat_slave/beckhoff_stack/stack_sources/*.h +source/industrial_comms/ethercat_slave/beckhoff_stack/stack_sources/*.dll +source/industrial_comms/ethercat_slave/beckhoff_stack/stack_sources/*.lib +source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/*.c +source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/*.h +source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/*.dll +source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/*.lib +source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/src/*.c +source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/src/*.h +source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/src/*.dll +source/industrial_comms/ethercat_slave/stack/patch/SlaveFiles/src/*.lib +source/networking/enet/core +source/networking/lwip/lwip-stack +source/networking/lwip/lwip-contrib +source/cmsis +source/commercial +source/usb/tinyusb/tinyusb-stack +source/dsplib_c66x_3_4_0_0/ +docs/industrial_protocol_docs +mcusdk_tagfile +__pycache__/ +source/motor_control/position_sense/hdsl/firmware/*.lst +source/motor_control/position_sense/hdsl/firmware/*.obj +source/motor_control/position_sense/hdsl/firmware/*.b00 +source/motor_control/position_sense/hdsl/firmware/*.xml +source/networking/mbedtls_library/mbedtls +source/motor_control/position_sense/endat/firmware/*.lst +source/motor_control/position_sense/endat/firmware/*.obj +source/motor_control/position_sense/endat/firmware/*.b00 +source/motor_control/position_sense/endat/firmware/*.xml +!*boardcfg_*.bin diff --git a/.metadata/.tirex/am243x.content.tirex.json b/.metadata/.tirex/am243x.content.tirex.json new file mode 100644 index 0000000..13f70d8 --- /dev/null +++ b/.metadata/.tirex/am243x.content.tirex.json @@ -0,0 +1,413 @@ +[ + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Endat Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "endat_diagnostic_single_channel", + "location": "../../examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "endat_diagnostic", + "single_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Endat Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "endat_diagnostic_single_channel", + "location": "../../examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_LAUNCHPAD" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "endat_diagnostic", + "single_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Endat Diagnostic Multi Channel Load Share Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "endat_diagnostic_multi_channel_load_share", + "location": "../../examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "endat_diagnostic", + "multi_channel_load_share", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Endat Diagnostic Multi Channel Single Pru Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "endat_diagnostic_multi_channel_single_pru", + "location": "../../examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "endat_diagnostic", + "multi_channel_single_pru", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Hdsl Diagnostic Multi Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "hdsl_diagnostic_multi_channel", + "location": "../../examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "hdsl_diagnostic", + "multi_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Hdsl Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "hdsl_diagnostic_single_channel", + "location": "../../examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "hdsl_diagnostic", + "single_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Hdsl Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "hdsl_diagnostic_single_channel", + "location": "../../examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_LAUNCHPAD" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "hdsl_diagnostic", + "single_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Hdsl Diagnostic Ddr Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "hdsl_diagnostic_ddr", + "location": "../../examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "hdsl_diagnostic_with_traces", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Tamagawa Diagnostic Multi Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "tamagawa_diagnostic_multi_channel", + "location": "../../examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "tamagawa_diagnostic", + "multi_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Tamagawa Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "tamagawa_diagnostic_single_channel", + "location": "../../examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "tamagawa_diagnostic", + "single_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Tamagawa Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "tamagawa_diagnostic_single_channel", + "location": "../../examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_LAUNCHPAD" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "tamagawa_diagnostic", + "single_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Icss Sdfm Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "icss_sdfm", + "location": "../../examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM243x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "icss_sdfm", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "web.page", + "resourceClass": [ + "document" + ], + "name": "User Guide", + "location": "../../docs/api_guide_am243x/index.html", + "devtools": [ + "AM243x_GP_EVM", + "AM243x_LAUNCHPAD" + ], + "mainCategories": [ + [ + "Documents" + ] + ] + } +] diff --git a/.metadata/.tirex/am263x.content.tirex.json b/.metadata/.tirex/am263x.content.tirex.json new file mode 100644 index 0000000..b52ae87 --- /dev/null +++ b/.metadata/.tirex/am263x.content.tirex.json @@ -0,0 +1,50 @@ +[ + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "An Example of tamagawa single channel with soc uart CPU is R5FSS0-0 running FREERTOS.", + "name": "tamagawa_diagnostic_soc_uart", + "location": "../../examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "LP-AM263" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "tamagawa_diagnostic_over_soc_uart", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "web.page", + "resourceClass": [ + "document" + ], + "name": "User Guide", + "location": "../../docs/api_guide_am263x/index.html", + "devtools": [ + "LP-AM263" + ], + "mainCategories": [ + [ + "Documents" + ] + ] + } +] diff --git a/.metadata/.tirex/am64x.content.tirex.json b/.metadata/.tirex/am64x.content.tirex.json new file mode 100644 index 0000000..50cf766 --- /dev/null +++ b/.metadata/.tirex/am64x.content.tirex.json @@ -0,0 +1,313 @@ +[ + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Endat Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "endat_diagnostic_single_channel", + "location": "../../examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM64x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "endat_diagnostic", + "single_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Endat Diagnostic Multi Channel Load Share Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "endat_diagnostic_multi_channel_load_share", + "location": "../../examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM64x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "endat_diagnostic", + "multi_channel_load_share", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Endat Diagnostic Multi Channel Single Pru Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "endat_diagnostic_multi_channel_single_pru", + "location": "../../examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM64x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "endat_diagnostic", + "multi_channel_single_pru", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Hdsl Diagnostic Multi Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "hdsl_diagnostic_multi_channel", + "location": "../../examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM64x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "hdsl_diagnostic", + "multi_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Hdsl Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "hdsl_diagnostic_single_channel", + "location": "../../examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM64x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "hdsl_diagnostic", + "single_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Hdsl Diagnostic Ddr Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "hdsl_diagnostic_ddr", + "location": "../../examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM64x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "hdsl_diagnostic_with_traces", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Tamagawa Diagnostic Multi Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "tamagawa_diagnostic_multi_channel", + "location": "../../examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM64x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "tamagawa_diagnostic", + "multi_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Tamagawa Diagnostic Single Channel Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "tamagawa_diagnostic_single_channel", + "location": "../../examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM64x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "tamagawa_diagnostic", + "single_channel", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "project.ccs", + "resourceClass": [ + "example" + ], + "resourceSubClass": [ + "example.general" + ], + "description": "A Icss Sdfm Example. CPU is R5FSS0-0 running FREERTOS.", + "name": "icss_sdfm", + "location": "../../examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec", + "devtools": [ + "AM64x_GP_EVM" + ], + "kernel": [ + "freertos" + ], + "compiler": [ + "ticlang" + ], + "subCategories": [ + "motor_control", + "icss_sdfm", + "r5fss0-0_freertos" + ], + "mainCategories": [ + [ + "Examples", + "Development Tools" + ] + ] + }, + { + "resourceType": "web.page", + "resourceClass": [ + "document" + ], + "name": "User Guide", + "location": "../../docs/api_guide_am64x/index.html", + "devtools": [ + "AM64x_GP_EVM" + ], + "mainCategories": [ + [ + "Documents" + ] + ] + } +] diff --git a/.metadata/.tirex/motor_control_sdk.png b/.metadata/.tirex/motor_control_sdk.png new file mode 100644 index 0000000..c084694 Binary files /dev/null and b/.metadata/.tirex/motor_control_sdk.png differ diff --git a/.metadata/.tirex/package.ccs.json b/.metadata/.tirex/package.ccs.json new file mode 100644 index 0000000..80a81fe --- /dev/null +++ b/.metadata/.tirex/package.ccs.json @@ -0,0 +1,18 @@ +[ + { + "rootMacroName": "COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR", + "compilerIncludePath": [ ], + "compilerSymbols": [ ], + "linkerSearchPath": [ ], + "properties": { + "rtsc.repositories": [ + "source", + "." + ] + }, + "helpTocs": [ + ], + "docs": [ + ] + } +] diff --git a/.metadata/.tirex/package.tirex.json b/.metadata/.tirex/package.tirex.json new file mode 100644 index 0000000..fdd44bb --- /dev/null +++ b/.metadata/.tirex/package.tirex.json @@ -0,0 +1,20 @@ +[ + { + "metadataVersion": "3.01.00", + "id": "com.ti.MOTOR_CONTROL_SDK_AMXXX", + "name": "MOTOR CONTROL SDK for AMXXX", + "rootCategory": [ "MOTOR CONTROL SDK", "MOTOR CONTROL SDK for AMXXX" ], + "version": "09.00.00.01", + "type": "software", + "image": "./mcu_plus_sdk.png", + "license": "../../license.txt", + "devices": ["AMXXX"], + "tags": ["SDK", "Baremetal", "FreeRTOS"], + "description": "Welcome to MOTOR CONTROL SDK for AMXXX. This SDK contains examples, libraries and tools to develop RTOS and no-RTOS based applications for ARM R5F, ARM M4F CPUs and related peripherals.", + "dependencies": [ + { "packageId": "sysconfig", "version": "1.14.0", "require": "mandatory" }, + { "packageId": "ti_cgt_tiarmclang", "version": "2.1.2", "require": "mandatory" }, + { "packageId": "arm.gnu.aarch64-none", "version": "9.2.1", "require": "mandatory" } + ] + } +] diff --git a/.metadata/product.json b/.metadata/product.json new file mode 100644 index 0000000..238bc97 --- /dev/null +++ b/.metadata/product.json @@ -0,0 +1,75 @@ +{ + "name": "MOTOR_CONTROL_SDK", + "displayName": "MOTOR CONTROL SDK", + "version": "09.00.00", + "documentationPath": "../docs", + "includePaths": [ + "../source", + ], + "components": [ + "/motor_control/motor_control", + ], + "devices": [ + "AM64x_beta", + "AM243x_ALV_beta", + "AM243x_ALX_beta", + "AM273x", + "AWR294X", + "AM263x_beta", + "AM62x", + ], + "contexts": { + "AM64x_beta": [ + "r5fss0-0", + "r5fss0-1", + "r5fss1-0", + "r5fss1-1", + "m4fss0-0", + "a53ss0-0", + ], + "AM243x_ALV_beta": [ + "r5fss0-0", + "r5fss0-1", + "r5fss1-0", + "r5fss1-1", + "m4fss0-0", + ], + "AM243x_ALX_beta": [ + "r5fss0-0", + "r5fss0-1", + "r5fss1-0", + "r5fss1-1", + "m4fss0-0", + ], + "AM273x": [ + "r5fss0-0", + "r5fss0-1", + "c66ss0", + "hsm0-0", + ], + "AWR294X": [ + "r5fss0-0", + "r5fss0-1", + "c66ss0", + "hsm0-0", + ], + "AM263x_beta": [ + "r5fss0-0", + "r5fss0-1", + "r5fss1-0", + "r5fss1-1", + "hsm0-0", + ], + "AM62x": [ + "m4fss0-0", + ], + }, + "pinmuxUIOptions": { + "group": "merged", + "hidePeripheralTab": false, + "showPinTable": true, + "showSignals": true, + "showUsed": true + }, + "minToolVersion" : "1.14.0" +} diff --git a/.project/cgt/cgt_gcc-aarch64.js b/.project/cgt/cgt_gcc-aarch64.js new file mode 100644 index 0000000..2d0afa9 --- /dev/null +++ b/.project/cgt/cgt_gcc-aarch64.js @@ -0,0 +1,88 @@ + +const common = require(`../common.js`); + +const cgt_a53 ={ + cflags: { + common: [ + "-mcpu=cortex-a53+fp+simd", + "-mabi=lp64", + "-mcmodel=large", + "-mstrict-align", + "-mfix-cortex-a53-835769", + "-mfix-cortex-a53-843419", + ], + }, +} + +const cgt_common = { + path: "CGT_GCC_AARCH64_PATH", + cc: "aarch64-none-elf-gcc", + ar: "aarch64-none-elf-gcc-ar", + lnk: "aarch64-none-elf-gcc", + strip: "aarch64-none-elf-strip", + objcopy: "aarch64-none-elf-objcopy", + cov: "aarch64-none-elf-gcov", + + includes: { + common: [ + "${MCU_PLUS_SDK_PATH}/source", + "${MOTOR_CONTROL_SDK_PATH}/source", + ], + }, + cflags: { + common: [ + "-Wall", + "-Werror", + "-g", + "-Wno-int-to-pointer-cast", + "-Wno-pointer-to-int-cast", + "-Wno-unused-but-set-variable", + "-fdata-sections", + "-ffunction-sections" + ], + debug: [ + "-D_DEBUG_=1" + ], + release: [ + "-O2" + ], + }, + arflags: { + common: [ + "cr", + ], + }, + lflags: { + common: [ + "-Wl,-static", + "-Wl,--gc-sections", + "-Wl,--build-id=none", + "-lstdc++", + "-lgcc", + "-lm", + "-lc", + "-lrdimon", + ], + }, + libdirs: { + common: [ + "$(CGT_GCC_AARCH64_PATH)/lib", + ], + } +}; + +function getCgtOptions(cpu, device) +{ + let cgtOptions = {}; + + if (cpu.match(/a53*/)) + { + cgtOptions = common.mergeCgtOptions(cgt_common, cgt_a53); + } + return cgtOptions; +} + +module.exports = { + + getCgtOptions, +}; \ No newline at end of file diff --git a/.project/cgt/cgt_gcc-armv7.js b/.project/cgt/cgt_gcc-armv7.js new file mode 100644 index 0000000..919fdeb --- /dev/null +++ b/.project/cgt/cgt_gcc-armv7.js @@ -0,0 +1,95 @@ + +const common = require(`../common.js`); + +const cgt_r5f = { + cflags: { + common: [ + "-mcpu=cortex-r5", + "-mfloat-abi=hard", + "-mfpu=vfpv3-d16", + "-marm", + ], + }, + lflags: { + common: [ + "-mcpu=cortex-r5", + "-mfloat-abi=hard", + "-mfpu=vfpv3-d16", + "-marm", + ], + }, +} + +const cgt_common = { + path: "CGT_GCC_ARMV7_PATH", + cc: "arm-none-eabi-gcc", + ar: "arm-none-eabi-gcc-ar", + lnk: "arm-none-eabi-gcc", + strip: "arm-none-eabi-strip", + objcopy: "arm-none-eabi-objcopy", + + includes: { + common: [ + "${MCU_PLUS_SDK_PATH}/source", + "${MOTOR_CONTROL_SDK_PATH}/source", + ], + }, + cflags: { + common: [ + "-Wall", + "-Werror", + "-g", + "-Wno-gnu-variable-sized-type-not-at-end", + "-Wno-unused-function", + "-Wno-int-to-pointer-cast", + "-Wno-pointer-to-int-cast", + "-Wno-unused-but-set-variable", + "-fdata-sections", /* this option is needed so that compiler throws away unused sections */ + "-ffunction-sections", /* this option is needed so that compiler throws away unused sections */ + ], + debug: [ + "-D_DEBUG_=1", + ], + release: [ + "-O2", + ], + }, + arflags: { + common: [ + "cr", + ], + }, + lflags: { + common: [ + "-Wl,-static", + "-Wl,--gc-sections", + "-Wl,--build-id=none", + "-lstdc++", + "-lgcc", + "-lm", + "-lc", + "-lnosys", /* this disable CCS output, rdimon enables CCS output, i.e semi-hosting, but there is some problem so disabling it */ + ], + }, + libdirs: { + common: [ + "${CGT_GCC_ARMV7_PATH}/lib", + ], + }, +}; + +function getCgtOptions(cpu, device) +{ + let cgtOptions = {}; + + if(cpu.match(/r5f*/)) + { + cgtOptions = common.mergeCgtOptions(cgt_common, cgt_r5f); + } + return cgtOptions; +} + +module.exports = { + + getCgtOptions, +}; diff --git a/.project/cgt/cgt_ti-arm-clang.js b/.project/cgt/cgt_ti-arm-clang.js new file mode 100644 index 0000000..3a25732 --- /dev/null +++ b/.project/cgt/cgt_ti-arm-clang.js @@ -0,0 +1,131 @@ + +const common = require(`../common.js`); + +const cgt_r5f = { + cflags: { + common: [ + "-mcpu=cortex-r5", + "-mfloat-abi=hard", + "-mfpu=vfpv3-d16", + ], + }, + lflags: { + common: [ + "--diag_suppress=10063", + ], + }, +} + +const cgt_m4f = { + cflags: { + common: [ + "-mcpu=cortex-m4", + "-mfloat-abi=hard", + ], + }, + lflags: { + common: [ + ], + }, +} + +const cgt_common = { + path: "CGT_TI_ARM_CLANG_PATH", + cc: "tiarmclang", + ar: "tiarmar", + lnk: "tiarmclang", + strip: "tiarmstrip", + objcopy: "tiarmobjcopy", + cov: "tiarmcov", + profdata: "tiarmprofdata", + + includes: { + common: [ + "${CG_TOOL_ROOT}/include/c", + "${MCU_PLUS_SDK_PATH}/source", + "${MOTOR_CONTROL_SDK_PATH}/source", + ], + }, + cflags: { + common: [ + "-mthumb", + "-Wall", + "-Werror", + "-g", + "-Wno-gnu-variable-sized-type-not-at-end", + "-Wno-unused-function", + ], + cpp_common: [ + "-Wno-c99-designator", + "-Wno-extern-c-compat", + "-Wno-c++11-narrowing", + "-Wno-reorder-init-list", + "-Wno-deprecated-register", + "-Wno-writable-strings", + "-Wno-enum-compare", + "-Wno-reserved-user-defined-literal", + "-Wno-unused-const-variable", + "-x c++", + ], + debug: [ + "-D_DEBUG_=1", + ], + release: [ + "-Os", + ], + }, + arflags: { + common: [ + "rc", + ], + }, + lflags: { + common: [ + "--ram_model", + "--reread_libs", + ], + }, + libdirs: { + common: [ + "${CG_TOOL_ROOT}/lib", + ], + }, + libs: { + common: [ + "libc.a", + "libsysbm.a", + ], + }, +}; + +const cgt_instrumentation = { + cflags: { + common: [ + "-fprofile-instr-generate", + "-fcoverage-mapping", + ], + }, +}; + +function getCgtOptions(cpu, device) +{ + let cgtOptions = {}; + + if(cpu.match(/r5f*/)) + { + cgtOptions = common.mergeCgtOptions(cgt_common, cgt_r5f); + if(common.isInstrumentationMode()) { + cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_instrumentation); + } + } + if(cpu.match(/m4f*/)) + { + cgtOptions = common.mergeCgtOptions(cgt_common, cgt_m4f); + } + return cgtOptions; +} + +module.exports = { + + getCgtOptions, +}; diff --git a/.project/cgt/cgt_ti-arm.js b/.project/cgt/cgt_ti-arm.js new file mode 100644 index 0000000..4b0ef91 --- /dev/null +++ b/.project/cgt/cgt_ti-arm.js @@ -0,0 +1,42 @@ +const cgt = { + path: "CGT_TI_ARM_PATH", + cc: "armcl", + ar: "armar", + + includes: { + common: [ + "$(CGT_TI_ARM_PATH)/include", + ".", + "$(MCU_PLUS_SDK_PATH)/source"], + "${MOTOR_CONTROL_SDK_PATH}/source", + }, + cflags: { + common: [ + "-c", "-qq", + "-pdsw225", + "--endian=little", + "-mv7R5", + "--abi=eabi", + "--float_support=vfpv3d16", + "--code_state=16", + "--emit_warnings_as_errors", + ], + debug: [ + "--symdebug:dwarf", + "-g", + "-D_DEBUG_=1", + ], + release: [ + "--embed_inline_assembly", + "-ms", + "-o3", + ], + }, + arflags: { + common: [ + "rq", + ] + }, +}; + +module.exports = cgt; diff --git a/.project/cgt/cgt_ti-c6000.js b/.project/cgt/cgt_ti-c6000.js new file mode 100644 index 0000000..6fd9e9b --- /dev/null +++ b/.project/cgt/cgt_ti-c6000.js @@ -0,0 +1,150 @@ + +const common = require(`../common.js`); + +const cgt_common = { + path: "CGT_TI_C6000_PATH", + cc: "cl6x", + ar: "ar6x", + lnk: "lnk6x", + strip: "strip6x", + objcopy: "", + + includes: { + common: [ + "${CG_TOOL_ROOT}/include", + "${MCU_PLUS_SDK_PATH}/source", + "${MOTOR_CONTROL_SDK_PATH}/source", + ], + }, + cflags: { + common: [ + "-mv6600", + "--abi=eabi", + "-q", + "-mi10", + "-mo", + "-pden", + "-pds=238", + "-pds=880", + "-pds1110", + "--emit_warnings_as_errors", + ], + debug: [ + "-D_DEBUG_=1", + ], + release: [ + "--program_level_compile", + "-o3", + "-mf3", + ], + }, + arflags: { + common: [ + "rq", + ], + }, + lflags: { + common: [ + "--warn_sections", + "--emit_warnings_as_errors", + "--rom_model", + "-x", + ], + }, + libdirs: { + common: [ + "${CG_TOOL_ROOT}/lib", + ], + }, + libs: { + common: [ + "libc.a", + ], + }, +}; + +const cgt_common_awr294x = { + path: "CGT_TI_C6000_PATH", + cc: "cl6x", + ar: "ar6x", + lnk: "lnk6x", + strip: "strip6x", + objcopy: "", + + includes: { + common: [ + "${CG_TOOL_ROOT}/include", + "${MCU_PLUS_SDK_PATH}/source", + "${MOTOR_CONTROL_SDK_PATH}/source", + ], + }, + cflags: { + common: [ + "-mv6600", + "--c99", + "-q", + "-mo", + "-pden", + "--emit_warnings_as_errors", + "--mem_model:const=data", + "--mem_model:data=far_aggregates", + "--remove_hooks_when_inlining", + "-on2", + "--disable_push_pop", + "--fp_mode=relaxed", + "--assume_control_regs_read", + ], + debug: [ + "-D_DEBUG_=1", + ], + release: [ + "--program_level_compile", + "-o3", + "-mf2", + ], + }, + arflags: { + common: [ + "rq", + ], + }, + lflags: { + common: [ + "--warn_sections", + "--emit_warnings_as_errors", + "--ram_model", + "-x", + ], + }, + libdirs: { + common: [ + "${CG_TOOL_ROOT}/lib", + ], + }, + libs: { + common: [ + "libc.a", + ], + }, +}; + +function getCgtOptions(cpu, device) +{ + let cgtOptions = {}; + + if(device.match(/awr294x*/)) + { + cgtOptions = cgt_common_awr294x; + } + else + { + cgtOptions = cgt_common; + } + + return cgtOptions; +} + +module.exports = { + + getCgtOptions, +}; diff --git a/.project/cgt/cgt_ti-pru-cgt.js b/.project/cgt/cgt_ti-pru-cgt.js new file mode 100644 index 0000000..e708f63 --- /dev/null +++ b/.project/cgt/cgt_ti-pru-cgt.js @@ -0,0 +1,149 @@ + +const common = require(`../common.js`); + +const cgt_icssg0 = { + cflags: { + common: [ + "-DICSSG0" + ], + }, +} + +const cgt_icssg1 = { + cflags: { + common: [ + "-DICSSG1" + ], + }, +} + +const cgt_pru0 = { + cflags: { + common: [ + "-DPRU0", + "-DSLICE0" + ], + }, +} + +const cgt_pru1 = { + cflags: { + common: [ + "-DPRU1", + "-DSLICE1" + ], + }, +} + +const cgt_rtpru0 = { + cflags: { + common: [ + "-DRTU_PRU0", + "-DSLICE0" + ], + }, +} + +const cgt_rtpru1 = { + cflags: { + common: [ + "-DRTU_PRU1", + "-DSLICE1" + ], + }, +} + +const cgt_txpru0 = { + cflags: { + common: [ + "-DTX_PRU0", + "-DSLICE0" + ], + }, +} + +const cgt_txpru1 = { + cflags: { + common: [ + "-DTX_PRU1", + "-DSLICE1" + ], + }, +} + +const cgt_common = { + path: "CGT_TI_PRU_PATH", + + includes: { + common: [ + "${CG_TOOL_ROOT}/include", + "${MCU_PLUS_SDK_PATH}/source", + "${MOTOR_CONTROL_SDK_PATH}/source", + ], + }, + cflags: { + common: [ + "-v4", + ], + debug: [ + "-D_DEBUG_=1", + ], + release: [ + "-O3", + ], + }, + lflags: { + common: [ + "-llibc.a" + ], + }, + libdirs: { + common: [ + "${CG_TOOL_ROOT}/lib" + ], + }, +}; + +function getCgtOptions(cpu, device) +{ + let cgtOptions = {}; + + if(cpu.match(/pru0/)) + { + cgtOptions = common.mergeCgtOptions(cgt_common, cgt_pru0); + } + if(cpu.match(/pru1/)) + { + cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_pru1); + } + if(cpu.match(/rtpru0/)) + { + cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_rtpru0); + } + if(cpu.match(/rtpru1/)) + { + cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_rtpru1); + } + if(cpu.match(/txpru0/)) + { + cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_txpru0); + } + if(cpu.match(/txpru1/)) + { + cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_txpru1); + } + if(cpu.match(/icssg0/)) + { + cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_icssg0); + } + if(cpu.match(/icssg1/)) + { + cgtOptions = common.mergeCgtOptions(cgtOptions, cgt_icssg1); + } + return cgtOptions; +} + +module.exports = { + + getCgtOptions, +}; diff --git a/.project/common.js b/.project/common.js new file mode 100644 index 0000000..64f9308 --- /dev/null +++ b/.project/common.js @@ -0,0 +1,203 @@ +const fs = require('fs'); +const path = require(`path`); +const _ = require('lodash'); +const template = require("./templateCompiler"); + +function concatArrayPropertiesInObject(obj1, obj2, arr_prop, swap) { + if(obj2.hasOwnProperty(arr_prop)==false) + return; + + if(obj1.hasOwnProperty(arr_prop)==false) + obj1[arr_prop] = {}; + + for (let prop in obj2[arr_prop]) { + if (obj2[arr_prop].hasOwnProperty(prop) && Array.isArray(obj2[arr_prop][prop])) { + if( obj1[arr_prop].hasOwnProperty(prop) == false ) + obj1[arr_prop][prop] = []; + + if( Array.isArray(obj1[arr_prop][prop])) + { + if(swap) + { + /* here the CGT options appear after project specific options, for some options + * esp libaries we want cgt libs to appear at the end. + */ + obj1[arr_prop][prop] = obj1[arr_prop][prop].concat(obj2[arr_prop][prop]); + } + else + { + /* here the CGT options appear before project specific options, most we want + * this so that project options can override CGT options + */ + obj1[arr_prop][prop] = obj2[arr_prop][prop].concat(obj1[arr_prop][prop]); + } + } + } + } +} + +function mergeCgtOptions(project, commonCgtOptions) { + project = _.cloneDeep(project); + + concatArrayPropertiesInObject(project, commonCgtOptions, "cflags", false); + concatArrayPropertiesInObject(project, commonCgtOptions, "arflags", false); + concatArrayPropertiesInObject(project, commonCgtOptions, "includes", false); + concatArrayPropertiesInObject(project, commonCgtOptions, "defines", false); + concatArrayPropertiesInObject(project, commonCgtOptions, "files", false); + concatArrayPropertiesInObject(project, commonCgtOptions, "filedirs", false); + concatArrayPropertiesInObject(project, commonCgtOptions, "asmfiles", false); + concatArrayPropertiesInObject(project, commonCgtOptions, "lflags", false); + concatArrayPropertiesInObject(project, commonCgtOptions, "libs", true); + concatArrayPropertiesInObject(project, commonCgtOptions, "libdirs", true); + concatArrayPropertiesInObject(project, commonCgtOptions, "lnkfiles", false); + + return project; +} + +function relative(pathStr1, pathStr2) { + let relpath = path.relative(pathStr1, pathStr2) + + relpath = path.normalize(relpath); + + return relpath.replace(/\\/g, "/"); +} + +function genBuildfiles(device) { + + /* first call genExampleFiles, genComponentFiles since these create files that + * are then used by genProjectSpec and genMakefiles + */ + require(`./genExampleFiles`).genExampleFilesDevice(device); + require(`./genComponentFiles`).genComponentFilesDevice(device); + require(`./genMakefiles`).genMakefilesDevice(device); + require(`./genProjectSpec`).genProjectSpecsDevice(device); + require(`./genTirex`).genTirexDevice(device); + require(`./genSystemProject`).genSystemProjectDevice(device); + require(`./genCcsPackageFiles`).genCcsPackageFilesDevice(device); +} + +function cleanBuildfiles(device) { + require(`./genExampleFiles`).cleanExampleFilesDevice(device); + require(`./genComponentFiles`).cleanComponentFilesDevice(device); + require(`./genMakefiles`).cleanMakefilesDevice(device); + require(`./genProjectSpec`).cleanProjectSpecsDevice(device); + require(`./genSystemProject`).cleanSystemProjectDevice(device); +} + +function convertTemplateToFile(templateFilename, outputFilename, args) { + + let inData = fs.readFileSync(templateFilename, 'utf8', + function (err, data) { + if (err) throw err; + } + ); + + let outData = template.executeTemplate(inData, args); + + fs.writeFileSync(outputFilename, outData, + function (err) { + if (err) throw err; + } + ); +} + +function makeExampleOutPath(projectPath, buildOption) +{ + return `${projectPath}/${buildOption.board}/${buildOption.cpu}_${buildOption.os}/${buildOption.cgt}` +} + +const fs_promise = require('fs').promises; + +function deleteFile(filepath) +{ + (async () => { + try { + await fs_promise.unlink(filepath); + } catch (e) { + /* file doens't exist. Skip error!! */ + } + })(); +} + +function getDefaultProjectDescription(name, cpu, os) { + let title = name.replace(/_/g, ' '); + + // Title Case : Converts "hello world" to "Hello World" using regex + title = title.replace( + /\w\S*/g, + function (s) { + return s.charAt(0).toUpperCase() + s.substr(1).toLowerCase(); + } + ); + + title = "A " + title + " Example. CPU is " + cpu.toUpperCase() + " running " + os.toUpperCase() + "."; + return title; +} + +function getDefaultSystemProjectDescription(name) { + let title = name.replace(/_/g, ' '); + + // Title Case : Converts "hello world" to "Hello World" using regex + title = title.replace( + /\w\S*/g, + function (s) { + return s.charAt(0).toUpperCase() + s.substr(1).toLowerCase(); + } + ); + + title = "A " + title + " System Example."; + return title; +} + +/* this can be "development" or "production" */ +let genBuildFilesMode = "development"; + +function isDevelopmentMode() +{ + if(genBuildFilesMode=="development") + return true; + + return false; +} + +function setGenBuildFilesMode(mode) +{ + if(mode=="production" || mode == "development") + { + genBuildFilesMode = mode; + } +} + +/* this can be "enable" or "disable" */ +let genInstrumentationMode = "disable"; + +function isInstrumentationMode() +{ + if(genInstrumentationMode=="enable") + return true; + + return false; +} + +function setInstrumentationMode(mode) +{ + genInstrumentationMode = mode; +} + +module.exports = { + genBuildfiles, + isDevelopmentMode, + setGenBuildFilesMode, + isInstrumentationMode, + setInstrumentationMode, + cleanBuildfiles, + mergeCgtOptions, + convertTemplateToFile, + path: { + relative, + makeExampleOutPath, + }, + deleteFile, + getDefaultProjectDescription, + getDefaultSystemProjectDescription, +}; diff --git a/.project/device/project_am243x.js b/.project/device/project_am243x.js new file mode 100644 index 0000000..370a57d --- /dev/null +++ b/.project/device/project_am243x.js @@ -0,0 +1,180 @@ +const common = require("../common.js"); + +const component_file_list = [ + "source/motor_control/current_sense/sdfm/.project/project.js", + "source/motor_control/position_sense/endat/.project/project.js", + "source/motor_control/position_sense/hdsl/.project/project.js", + "source/motor_control/position_sense/tamagawa/.project/project.js", +]; + +const device_defines = { + common: [ + "SOC_AM243X", + ], +}; + +const example_file_list = [ + "examples/motor_control/endat_diagnostic/single_channel/.project/project.js", + "examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project.js", + "examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project.js", + "examples/motor_control/hdsl_diagnostic/multi_channel/.project/project.js", + "examples/motor_control/hdsl_diagnostic/single_channel/.project/project.js", + "examples/motor_control/hdsl_diagnostic_with_traces/.project/project.js", + "examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project.js", + "examples/motor_control/tamagawa_diagnostic/single_channel/.project/project.js", + "examples/motor_control/icss_sdfm/.project/project.js", + "source/motor_control/current_sense/sdfm/firmware/.project/project.js", + "source/motor_control/position_sense/endat/firmware/multi_channel_load_share/.project/project.js", + "source/motor_control/position_sense/endat/firmware/single_channel/.project/project.js", + "source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js", + "source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project.js", + "source/motor_control/position_sense/tamagawa/firmware/single_channel/.project/project.js", +]; + +function getProjectSpecCpu(cpu) { + let projectSpecCpu = + { + "r5fss0-0": "MAIN_PULSAR_Cortex_R5_0_0", + "r5fss0-1": "MAIN_PULSAR_Cortex_R5_0_1", + "r5fss1-0": "MAIN_PULSAR_Cortex_R5_1_0", + "r5fss1-1": "MAIN_PULSAR_Cortex_R5_1_1", + "m4fss0-0": "Cortex_M4F_0", + "icssg0-pru0": "ICSS_G0_PRU_0", + "icssg0-pru1": "ICSS_G0_PRU_1", + "icssg0-rtupru0": "ICSS_G0_RTU_PRU_0", + "icssg0-rtupru1": "ICSS_G0_RTU_PRU_1", + "icssg0-txpru0": "ICSS_G0_TX_PRU_0", + "icssg0-txpru1": "ICSS_G0_TX_PRU_1", + "icssg1-pru0": "ICSS_G1_PRU_0", + "icssg1-pru1": "ICSS_G1_PRU_1", + "icssg1-rtupru0": "ICSS_G1_RTU_PRU_0", + "icssg1-rtupru1": "ICSS_G1_RTU_PRU_1", + "icssg1-txpru0": "ICSS_G1_TX_PRU_0", + "icssg1-txpru1": "ICSS_G1_TX_PRU_1", + } + + return projectSpecCpu[cpu]; +} + +function getComponentList() { + return component_file_list; +} + +function getExampleList() { + return example_file_list; +} + +function getSysCfgDevice(board) { + switch (board) { + case "am243x-lp": + return "AM243x_ALX_beta"; + default: + case "am243x-evm": + return "AM243x_ALV_beta"; + } +} + +function getProjectSpecDevice(board) { + switch (board) { + case "am243x": + return "AM243x"; + case "am243x-lp": + return "AM2434_ALX"; + default: + case "am243x-evm": + return "AM2434_ALV"; + } +} + +function getSysCfgCpu(cpu) { + return cpu; +} + +function getSysCfgPkg(board) { + switch (board) { + case "am243x-lp": + return "ALX"; + default: + case "am243x-evm": + return "ALV"; + } +} + +function getSysCfgPart(board) { + switch (board) { + case "am243x-lp": + return "ALX"; + default: + case "am243x-evm": + return "ALV"; + } +} + +function getDevToolTirex(board) { + switch (board) { + case "am243x-lp": + return "AM243x_LAUNCHPAD"; + default: + case "am243x-evm": + return "AM243x_GP_EVM"; + } +} + +function getProperty() { + let property = {}; + + property.defines = device_defines; + + return property; +} + +function getLinuxFwName(cpu) { + + switch(cpu) { + case "r5fss0-0": + return "am243-main-r5f0_0-fw"; + case "r5fss0-1": + return "am243-main-r5f0_1-fw"; + case "r5fss1-0": + return "am243-main-r5f1_0-fw"; + case "r5fss1-1": + return "am243-main-r5f1_1-fw"; + case "m4fss0-0": + return "am243-mcu-m4f0_0-fw"; + } + return undefined; +} + +function getProductNameProjectSpec() { + return "MOTOR_CONTROL_SDK_AM243X"; +} + +function getDependentProductNameProjectSpec() { + return "MCU_PLUS_SDK_AM243X"; +} + +function getFlashAddr() { + return 0x60000000; +} + +module.exports = { + getComponentList, + getExampleList, + getSysCfgDevice, + getSysCfgCpu, + getSysCfgPkg, + getSysCfgPart, + getProjectSpecDevice, + getProjectSpecCpu, + getDevToolTirex, + getProperty, + getLinuxFwName, + getProductNameProjectSpec, + getDependentProductNameProjectSpec, + getFlashAddr, +}; \ No newline at end of file diff --git a/.project/device/project_am263x.js b/.project/device/project_am263x.js new file mode 100644 index 0000000..c17d20b --- /dev/null +++ b/.project/device/project_am263x.js @@ -0,0 +1,140 @@ +const common = require("../common.js"); + +const component_file_list = [ + "source/motor_control/position_sense/tamagawa_over_soc_uart/.project/project.js", +]; + +const device_defines = { + common: [ + "SOC_AM263X", + ], +}; + +const example_file_list = [ + "examples/motor_control/tamagawa_diagnostic_over_soc_uart/.project/project.js", +]; + +function getProjectSpecCpu(cpu) { + let projectSpecCpu = + { + "r5fss0-0": "MAIN_PULSAR_Cortex_R5_0_0", + "r5fss0-1": "MAIN_PULSAR_Cortex_R5_0_1", + "r5fss1-0": "MAIN_PULSAR_Cortex_R5_1_0", + "r5fss1-1": "MAIN_PULSAR_Cortex_R5_1_1", + "icssm-pru0": "ICSSM_PRU_0", + "icssm-pru1": "ICSSM_PRU_1", + } + + return projectSpecCpu[cpu]; +} + +function getComponentList() { + return component_file_list; +} + +function getExampleList() { + return example_file_list; +} + +function getSysCfgDevice(board) { + switch (board) { + case "am263x-lp": + return "AM263x_beta"; + default: + case "am263x-cc": + return "AM263x_beta"; + } +} + +function getProjectSpecDevice(board) { + switch (board) { + case "am263x": + return "AM263x"; + case "am263x-lp": + return "AM263x"; + default: + case "am263x-cc": + return "AM263x"; + } +} + +function getSysCfgCpu(cpu) { + return cpu; +} + +function getSysCfgPkg(board) { + switch (board) { + case "am263x-lp": + return "ZCZ"; + default: + case "am263x-cc": + return "ZCZ"; + } +} + +function getSysCfgPart(board) { + switch (board) { + case "am263x-lp": + return "AM263x"; + default: + case "am263x-cc": + return "AM263x"; + } +} + +function getDevToolTirex(board) { + switch (board) { + case "am263x-lp": + return "LP-AM263"; + default: + case "am263x-cc": + return "TMDSCNCD263"; + } +} + +function getProperty() { + let property = {}; + + property.defines = device_defines; + + return property; +} + +function getLinuxFwName(cpu) { + + switch(cpu) { + case "r5fss0-0": + return "am263-main-r5f0_0-fw"; + case "r5fss0-1": + return "am263-main-r5f0_1-fw"; + case "r5fss1-0": + return "am263-main-r5f1_0-fw"; + case "r5fss1-1": + return "am263-main-r5f1_1-fw"; + } + return undefined; +} + +function getProductNameProjectSpec() { + return "MCU_PLUS_SDK_AM263X"; +} + +function getFlashAddr() { + return 0x60000000; +} + +module.exports = { + getComponentList, + getExampleList, + getSysCfgDevice, + getSysCfgCpu, + getSysCfgPkg, + getSysCfgPart, + getProjectSpecDevice, + getProjectSpecCpu, + getDevToolTirex, + getProperty, + getLinuxFwName, + getProductNameProjectSpec, + getFlashAddr, +}; diff --git a/.project/device/project_am64x.js b/.project/device/project_am64x.js new file mode 100644 index 0000000..75cb5df --- /dev/null +++ b/.project/device/project_am64x.js @@ -0,0 +1,155 @@ +const common = require("../common.js"); + +const component_file_list = [ + "source/motor_control/current_sense/sdfm/.project/project.js", + "source/motor_control/position_sense/endat/.project/project.js", + "source/motor_control/position_sense/hdsl/.project/project.js", + "source/motor_control/position_sense/tamagawa/.project/project.js", +]; + +const device_defines = { + common: [ + "SOC_AM64X", + ], +}; + +const example_file_list = [ + "examples/motor_control/endat_diagnostic/single_channel/.project/project.js", + "examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project.js", + "examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project.js", + "examples/motor_control/hdsl_diagnostic/multi_channel/.project/project.js", + "examples/motor_control/hdsl_diagnostic/single_channel/.project/project.js", + "examples/motor_control/hdsl_diagnostic_with_traces/.project/project.js", + "examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project.js", + "examples/motor_control/tamagawa_diagnostic/single_channel/.project/project.js", + "examples/motor_control/icss_sdfm/.project/project.js", + "source/motor_control/current_sense/sdfm/firmware/.project/project.js", + "source/motor_control/position_sense/endat/firmware/multi_channel_load_share/.project/project.js", + "source/motor_control/position_sense/endat/firmware/single_channel/.project/project.js", + "source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js", + "source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js", + "source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project.js", + "source/motor_control/position_sense/tamagawa/firmware/single_channel/.project/project.js", +]; + +function getProjectSpecCpu(cpu) { + let projectSpecCpu = + { + "r5fss0-0": "MAIN_PULSAR_Cortex_R5_0_0", + "r5fss0-1": "MAIN_PULSAR_Cortex_R5_0_1", + "r5fss1-0": "MAIN_PULSAR_Cortex_R5_1_0", + "r5fss1-1": "MAIN_PULSAR_Cortex_R5_1_1", + "m4fss0-0": "Cortex_M4F_0", + "a53ss0-0": "CortexA53_0", + "icssg0-pru0": "ICSS_G0_PRU_0", + "icssg0-pru1": "ICSS_G0_PRU_1", + "icssg0-rtupru0": "ICSS_G0_RTU_PRU_0", + "icssg0-rtupru1": "ICSS_G0_RTU_PRU_1", + "icssg0-txpru0": "ICSS_G0_TX_PRU_0", + "icssg0-txpru1": "ICSS_G0_TX_PRU_1", + "icssg1-pru0": "ICSS_G1_PRU_0", + "icssg1-pru1": "ICSS_G1_PRU_1", + "icssg1-rtupru0": "ICSS_G1_RTU_PRU_0", + "icssg1-rtupru1": "ICSS_G1_RTU_PRU_1", + "icssg1-txpru0": "ICSS_G1_TX_PRU_0", + "icssg1-txpru1": "ICSS_G1_TX_PRU_1", + } + + return projectSpecCpu[cpu]; +} + +function getComponentList() { + return component_file_list; +} + +function getExampleList() { + return example_file_list; +} + +function getSysCfgDevice(board) { + return "AM64x_beta"; +} + +function getProjectSpecDevice(board) { + return "AM64x"; +} + +function getSysCfgCpu(cpu) { + return cpu; +} + +function getSysCfgPkg(board) { + return "ALV"; +} + +function getSysCfgPart(board) { + return "Default"; +} + +function getDevToolTirex(board) { + switch (board) { + case "am64x-sk": + return "AM64x_SK_EVM"; + default: + case "am64x-evm": + return "AM64x_GP_EVM"; + } +} + +function getProperty() { + let property = {}; + + property.defines = device_defines; + + return property; +} + +function getLinuxFwName(cpu) { + + switch(cpu) { + case "r5fss0-0": + return "am64-main-r5f0_0-fw"; + case "r5fss0-1": + return "am64-main-r5f0_1-fw"; + case "r5fss1-0": + return "am64-main-r5f1_0-fw"; + case "r5fss1-1": + return "am64-main-r5f1_1-fw"; + case "m4fss0-0": + return "am64-mcu-m4f0_0-fw"; + } + return undefined; +} + +function getProductNameProjectSpec() { + return "MOTOR_CONTROL_SDK_AM64X"; +} + +function getDependentProductNameProjectSpec() { + return "MCU_PLUS_SDK_AM64X"; +} + +function getFlashAddr() { + return 0x60000000; +} + +module.exports = { + getComponentList, + getExampleList, + getSysCfgDevice, + getSysCfgCpu, + getSysCfgPkg, + getSysCfgPart, + getProjectSpecDevice, + getProjectSpecCpu, + getDevToolTirex, + getProperty, + getLinuxFwName, + getProductNameProjectSpec, + getDependentProductNameProjectSpec, + getFlashAddr, +}; \ No newline at end of file diff --git a/.project/genCcsPackageFiles.js b/.project/genCcsPackageFiles.js new file mode 100644 index 0000000..bcd0677 --- /dev/null +++ b/.project/genCcsPackageFiles.js @@ -0,0 +1,28 @@ +const common = require(`./common.js`); + +function genCcsPackageFilesDevice(device) { + + let args = { + device: device, + utils: require(`./genProjectSpec.js`).utils, + common: common, + }; + + common.convertTemplateToFile( + `.project/templates/package.ccs.json.xdt`, + `.metadata/.tirex/package.ccs.json`, + args); + common.convertTemplateToFile( + `.project/templates/package.tirex.json.xdt`, + `.metadata/.tirex/package.tirex.json`, + args); + common.convertTemplateToFile( + `.project/templates/product.json.xdt`, + `.metadata/product.json`, + args); + +} + +module.exports = { + genCcsPackageFilesDevice +} diff --git a/.project/genComponentFiles.js b/.project/genComponentFiles.js new file mode 100644 index 0000000..1d97325 --- /dev/null +++ b/.project/genComponentFiles.js @@ -0,0 +1,71 @@ +const common = require(`./common.js`); +const _ = require('lodash'); + +function genComponentFilesDevice(device) { + + let file_list = require(`./device/project_${device}`).getComponentList(); + + for(component of file_list) { + property = require(`../${component}`).getComponentProperty(device); + for(buildOption of property.buildOptionCombos) { + let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device); + let common_build_property = require(`./device/project_${device}`).getProperty(); + let project = []; + + build_property = require(`../${component}`).getComponentBuildProperty(buildOption); + + project = _.merge({}, project, property); + project = _.merge({}, project, buildOption); + project = common.mergeCgtOptions(project, common_build_property); + project = _.merge({}, project, build_property); + + if(!project.templates) + continue; + + for(template of project.templates) + { + let args = { + sdkPath: "MOTOR_CONTROL_SDK_PATH", + relPath: common.path.relative(project.dirPath, "."), + project: project, + options: template.options, + }; + + common.convertTemplateToFile( + template.input, + `${project.dirPath}/${template.output}`, + args); + } + } + } +} + +function cleanComponentFilesDevice(device) { + let file_list = require(`./device/project_${device}`).getComponentList(); + + for(component of file_list) { + property = require(`../${component}`).getComponentProperty(device); + for(buildOption of property.buildOptionCombos) { + let project = []; + + build_property = require(`../${component}`).getComponentBuildProperty(buildOption); + + project = _.merge({}, project, property); + project = _.merge({}, project, buildOption); + project = _.merge({}, project, build_property); + + if(!project.templates) + continue; + + for(template of project.templates) + { + common.deleteFile(`${project.dirPath}/${template.output}`); + } + } + } +} + +module.exports = { + genComponentFilesDevice, + cleanComponentFilesDevice, +} diff --git a/.project/genExampleFiles.js b/.project/genExampleFiles.js new file mode 100644 index 0000000..90bc2cc --- /dev/null +++ b/.project/genExampleFiles.js @@ -0,0 +1,84 @@ +const common = require(`./common.js`); +const path = require(`path`); +const fs = require(`fs`); +const _ = require('lodash'); + +function genExampleFilesDevice(device) { + + let example_file_list = require(`./device/project_${device}`).getExampleList(); + + for(example of example_file_list) { + property = require(`../${example}`).getComponentProperty(device); + for(buildOption of property.buildOptionCombos) { + let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device); + let common_build_property = require(`./device/project_${device}`).getProperty(); + let project = []; + let outPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + + fs.mkdirSync(outPath, { recursive: true }); + + build_property = require(`../${example}`).getComponentBuildProperty(buildOption); + + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath); + project = _.merge({}, project, buildOption); + project = common.mergeCgtOptions(project, common_build_property); + project = _.merge({}, project, build_property); + project.dirPath = outPath; + + if(!project.templates) + continue; + + let isInstrumentation = common.isInstrumentationMode(); + for(template of project.templates) + { + let args = { + sdkPath: "MOTOR_CONTROL_SDK_PATH", + relPath: common.path.relative(project.dirPath, "."), + project: project, + options: template.options, + isInstrumentation: isInstrumentation, + }; + + common.convertTemplateToFile( + template.input, + `${project.dirPath}/${template.output}`, + args); + } + } + } +} + +function cleanExampleFilesDevice(device) { + + let example_file_list = require(`./device/project_${device}`).getExampleList(); + + for(example of example_file_list) { + property = require(`../${example}`).getComponentProperty(device); + for(buildOption of property.buildOptionCombos) { + let project = []; + let outPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + + fs.mkdirSync(outPath, { recursive: true }); + build_property = require(`../${example}`).getComponentBuildProperty(buildOption); + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath); + project = _.merge({}, project, buildOption); + project = _.merge({}, project, build_property); + project.dirPath = outPath; + + if(!project.templates) + continue; + + for(template of project.templates) + { + common.deleteFile(`${project.dirPath}/${template.output}`); + } + } + } +} + +module.exports = { + genExampleFilesDevice, + cleanExampleFilesDevice, +} diff --git a/.project/genMakefiles.js b/.project/genMakefiles.js new file mode 100644 index 0000000..c088e02 --- /dev/null +++ b/.project/genMakefiles.js @@ -0,0 +1,410 @@ +const common = require(`./common.js`); +const path = require(`path`); +const fs = require(`fs`); +const _ = require('lodash'); + +function genMakefileDeviceTop(component_file_list, example_file_list, device, isInternal) { + let component_make_list = []; + let example_make_list = []; + let example_make_projectspec_list = []; + let system_example_make_list = []; + let system_example_make_projectspec_list = []; + + let genFolder = "."; + let relPath = "."; + if(isInternal == true) { + genFolder = "./test" + relPath = ".."; + } + + for(component of component_file_list) { + let component_make = []; + let buildTarget = []; + let buildTargetClean = []; + let buildTargetScrub = []; + + property = require(`../${component}`).getComponentProperty(device); + + let tag=""; + if(property.tag) + { + tag = `.${property.tag}`; + } + + component_make.name = property.name; + component_make.tag = tag; + component_make.relpath = common.path.relative(path.normalize(__dirname + `/../${genFolder}`), property.dirPath); + if(property.isSkipTopLevelBuild === true) + { + component_make.isSkipTopLevelBuild = true; + } + if(property.isPrebuilt === true) + { + component_make.isPrebuilt = true; + } + for(buildOption of property.buildOptionCombos) { + buildTarget +=` ${property.name}_${buildOption.cpu}.${buildOption.cgt}`; + buildTargetClean +=` ${property.name}_${buildOption.cpu}.${buildOption.cgt}_clean`; + buildTargetScrub +=` ${property.name}_${buildOption.cpu}.${buildOption.cgt}_scrub`; + } + component_make.buildTarget = buildTarget; + component_make.buildTargetClean = buildTargetClean; + component_make.buildTargetScrub = buildTargetScrub; + if(property.isInternal == isInternal) { + component_make_list.push(component_make); + } + } + + for(example of example_file_list) { + + property = require(`../${example}`).getComponentProperty(device); + + for(buildOption of property.buildOptionCombos) { + + let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + + let example_make = {}; + let buildTarget = {}; + let buildTargetClean = {}; + let buildTargetScrub = {}; + + example_make.name = `${property.name}_${buildOption.board}_${buildOption.cpu}_${buildOption.os}_${buildOption.cgt}`; + example_make.relpath = common.path.relative(path.normalize(__dirname + `/../${genFolder}`), makefileOutPath); + + if(property.isSkipTopLevelBuild === true) + { + example_make.isSkipTopLevelBuild = true; + } + + if(property.isBootLoader === true) + { + example_make.isBootLoader = true; + } + + buildTarget =` ${property.name}_${buildOption.board}_${buildOption.cpu}_${buildOption.os}_${buildOption.cgt}`; + buildTargetClean =` ${property.name}_${buildOption.board}_${buildOption.cpu}_${buildOption.os}_${buildOption.cgt}_clean`; + buildTargetScrub =` ${property.name}_${buildOption.board}_${buildOption.cpu}_${buildOption.os}_${buildOption.cgt}_scrub`; + + example_make.buildTarget = buildTarget; + example_make.buildTargetClean = buildTargetClean; + example_make.buildTargetScrub = buildTargetScrub; + if(property.isInternal == isInternal) { + let isPartOfSystemProject = false; + if(buildOption.isPartOfSystemProject && buildOption.isPartOfSystemProject === true) + { + isPartOfSystemProject = true; + } + if(isPartOfSystemProject === false) + { + example_make_list.push(example_make); + if(property.skipProjectSpec) { + /* no need to output project spec make commands */ + } + else { + example_make_projectspec_list.push(example_make); + } + } + } + } + } + + for(example of example_file_list) { + + example = require(`../${example}`); + + if( ! example.getSystemProjects) + continue; + + let property = example.getComponentProperty(device); + let systemProjects = example.getSystemProjects(device); + + for ( project of systemProjects) + { + let outPath = `${property.dirPath}/${project.board}/system_${project.tag}` + + let system_example_make = {}; + + system_example_make.name = `${project.name}_${project.board}_system_${project.tag}`; + system_example_make.relpath = common.path.relative(path.normalize(__dirname + `/../${genFolder}`), outPath); + system_example_make.buildTarget = " " + system_example_make.name; + system_example_make.buildTargetClean = " " + system_example_make.name + "_clean"; + system_example_make.buildTargetScrub = " " + system_example_make.name + "_scrub"; + + if(property.isSkipTopLevelBuild === true) + { + system_example_make.isSkipTopLevelBuild = true; + } + + if(property.isInternal == isInternal) { + system_example_make_list.push(system_example_make); + + if( project.skipProjectSpec && project.skipProjectSpec === true) + { + /* skip project spec */ + } + else + { + system_example_make_projectspec_list.push(system_example_make); + } + } + + + } + } + + let args = { + component_list: component_make_list, + example_list: example_make_list, + system_example_list: system_example_make_list, + device: device, + }; + + common.convertTemplateToFile( + `.project/templates/makefile_device_top.xdt`, + `${genFolder}/makefile.${device}`, + args); + + args = { + example_list: example_make_projectspec_list, + system_example_list: system_example_make_projectspec_list, + device: device, + sdkPath: "MOTOR_CONTROL_SDK_PATH", + relPath: relPath + }; + + common.convertTemplateToFile( + `.project/templates/makefile_device_projectspec_top.xdt`, + `${genFolder}/makefile_projectspec.${device}`, + args); +} + +function genMakefileLibrary(component_file_list, device) { + + for(component of component_file_list) { + property = require(`../${component}`).getComponentProperty(device); + for(buildOption of property.buildOptionCombos) { + let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device); + let common_build_property = require(`./device/project_${device}`).getProperty(); + build_property = require(`../${component}`).getComponentBuildProperty(buildOption); + + let project = []; + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), property.dirPath); + project = _.merge({}, project, buildOption); + project = _.merge({}, project, build_property); + project = common.mergeCgtOptions(project, commonCgtOptions); + project = common.mergeCgtOptions(project, common_build_property); + + let args = { + sdkPath: "MOTOR_CONTROL_SDK_PATH", + relPath: common.path.relative(project.dirPath, "."), + project: project, + cgtOptions: require(`./cgt/cgt_${project.cgt}`).getCgtOptions(buildOption.cpu, device), + }; + + let tag=""; + if(property.tag) + { + tag = `.${property.tag}`; + } + common.convertTemplateToFile( + `.project/templates/makefile_${project.type}.xdt`, + `${project.dirPath}/makefile${tag}.${project.device}.${project.cpu}.${project.cgt}`, + args); + } + } +} + +function cleanMakefileLibrary(component_file_list, device) { + + for(component of component_file_list) { + property = require(`../${component}`).getComponentProperty(device); + for(buildOption of property.buildOptionCombos) { + build_property = require(`../${component}`).getComponentBuildProperty(buildOption); + + let project = []; + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), property.dirPath); + + common.deleteFile(`${project.dirPath}/makefile.${buildOption.device}.${buildOption.cpu}.${buildOption.cgt}`); + } + } +} + +function genMakefileExample(example_file_list, device) { + + for(example of example_file_list) { + property = require(`../${example}`).getComponentProperty(device); + for(buildOption of property.buildOptionCombos) { + let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device); + let common_build_property = require(`./device/project_${device}`).getProperty(); + let project = []; + let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + + fs.mkdirSync(makefileOutPath, { recursive: true }); + + build_property = require(`../${example}`).getComponentBuildProperty(buildOption); + + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath); + project = _.merge({}, project, buildOption); + project = _.merge({}, project, build_property); + project = common.mergeCgtOptions(project, commonCgtOptions); + project = common.mergeCgtOptions(project, common_build_property); + project.dirPath = makefileOutPath; + + let isInstrumentationMode = false; + if(common.isInstrumentationMode()) { + isInstrumentationMode = true; + } + let args = { + sdkPath: "MOTOR_CONTROL_SDK_PATH", + relPath: common.path.relative(project.dirPath, "."), + project: project, + cgtOptions: require(`./cgt/cgt_${project.cgt}`).getCgtOptions(buildOption.cpu, device), + syscfg: { + device: require(`./device/project_${device}.js`).getSysCfgDevice(buildOption.board), + cpu: require(`./device/project_${device}.js`).getSysCfgCpu(buildOption.cpu), + pkg: require(`./device/project_${device}.js`).getSysCfgPkg(buildOption.board), + part: require(`./device/project_${device}.js`).getSysCfgPart(buildOption.board), + }, + linuxFwName: require(`./device/project_${device}`).getLinuxFwName(project.cpu), + isInstrumentationMode: isInstrumentationMode, + flashAddr: require(`./device/project_${device}.js`).getFlashAddr(), + }; + + if(project.makefile) { + common.convertTemplateToFile( + `.project/templates/makefile_${project.makefile}.xdt`, + `${project.dirPath}/makefile`, + args); + } else + common.convertTemplateToFile( + `.project/templates/makefile_${project.type}.xdt`, + `${project.dirPath}/makefile`, + args); + } + } +} + +function cleanMakefileExample(example_file_list, device) { + + for(example of example_file_list) { + property = require(`../${example}`).getComponentProperty(device); + for(buildOption of property.buildOptionCombos) { + let project = []; + let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + fs.mkdirSync(makefileOutPath, { recursive: true }); + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath); + project.dirPath = makefileOutPath; + + common.deleteFile(`${project.dirPath}/makefile`); + } + } +} + +function genMakefileProjectSpec(example_file_list, device) { + + for(example of example_file_list) { + property = require(`../${example}`).getComponentProperty(device); + + if(property.skipProjectSpec) + continue; + + for(buildOption of property.buildOptionCombos) { + let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device); + let common_build_property = require(`./device/project_${device}`).getProperty(); + let project = []; + let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + + fs.mkdirSync(makefileOutPath, { recursive: true }); + + build_property = require(`../${example}`).getComponentBuildProperty(buildOption); + + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath); + project = _.merge({}, project, buildOption); + project = common.mergeCgtOptions(project, common_build_property); + project = _.merge({}, project, build_property); + project.dirPath = makefileOutPath; + + let args = { + sdkPath: "MOTOR_CONTROL_SDK_PATH", + relPath: common.path.relative(project.dirPath, "."), + project: project + }; + + common.convertTemplateToFile( + `.project/templates/makefile_projectspec.xdt`, + `${project.dirPath}/makefile_projectspec`, + args); + } + } +} + +function cleanMakefileProjectSpec(example_file_list, device) { + + for(example of example_file_list) { + property = require(`../${example}`).getComponentProperty(device); + + if(property.skipProjectSpec) + continue; + + for(buildOption of property.buildOptionCombos) { + let project = []; + let makefileOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + fs.mkdirSync(makefileOutPath, { recursive: true }); + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath); + project.dirPath = makefileOutPath; + + common.deleteFile(`${project.dirPath}/makefile_projectspec`); + } + } +} + +function genMakeImport(device) { + let args = { + device: device, + utils: require(`./genProjectSpec.js`).utils, + common: common, + }; + + common.convertTemplateToFile( + `.project/templates/imports.mak.xdt`, + `imports.mak`, + args); +} + +function genMakefilesDevice(device) { + let component_file_list = require(`./device/project_${device}`).getComponentList(); + let example_file_list = require(`./device/project_${device}`).getExampleList(); + + genMakefileDeviceTop(component_file_list, example_file_list, device, false); /* External libs/examples */ + genMakefileDeviceTop(component_file_list, example_file_list, device, false); /* Internal libs/examples */ + genMakefileLibrary(component_file_list, device); + genMakefileExample(example_file_list, device); + genMakefileProjectSpec(example_file_list, device); + genMakeImport(device); +} + +function cleanMakefilesDevice(device) { + let component_file_list = require(`./device/project_${device}`).getComponentList(); + let example_file_list = require(`./device/project_${device}`).getExampleList(); + + /* Remove top level files */ + common.deleteFile(`./makefile.${device}`); + common.deleteFile(`./makefile_projectspec.${device}`); + common.deleteFile(`./test/makefile.${device}`); + common.deleteFile(`./test/makefile_projectspec.${device}`); + + cleanMakefileLibrary(component_file_list, device); + cleanMakefileExample(example_file_list, device); + cleanMakefileProjectSpec(example_file_list, device); +} + +module.exports = { + genMakefilesDevice, + cleanMakefilesDevice, +} diff --git a/.project/genProjectSpec.js b/.project/genProjectSpec.js new file mode 100644 index 0000000..2f31221 --- /dev/null +++ b/.project/genProjectSpec.js @@ -0,0 +1,323 @@ +const common = require(`./common.js`); +const path = require(`path`); +const _ = require('lodash'); +const fs = require('fs'); + +const utils = { + + capitalize: (s) => { + if (typeof s !== 'string') return '' + return s.charAt(0).toUpperCase() + s.slice(1) + }, + replace: (s, a, b) => { + return s.replace(a, b); + }, + getDeviceFamilyProjectSpec: (cpu) => { + let cpuFamily = 'ARM'; + + if (cpu.includes('r5f') == true) { + cpuFamily = 'ARM'; + } + if (cpu.includes('c66') == true) { + cpuFamily = 'C6000'; + } + if (cpu.includes('pru') == true) { + cpuFamily = 'PRU'; + } + return cpuFamily; + }, + getOutputTypeProjectSpec: (type) => { + let outputType = 'executable'; + + if(type == "executable") + outputType = 'executable'; + if(type == "library") + outputType = 'staticLibrary'; + return outputType; + }, + getSysCfgDeviceProjectSpec: (device, board) => { + return require(`./device/project_${device}`).getSysCfgDevice(board); + }, + getSysCfgCpuProjectSpec: (cpu) => { + return require(`./device/project_${device}`).getSysCfgCpu(cpu); + }, + getProjectSpecDevice: (device) => { + return require(`./device/project_${device}`).getProjectSpecDevice(device); + }, + getProjectSpecCpu: (device, cpu) => { + return require(`./device/project_${device}`).getProjectSpecCpu(cpu); + }, + getDeviceIdProjectSpec: (device, cpu, board) => { + let deviceName = ''; + let cpuName = ''; + + deviceName = require(`./device/project_${device}`).getProjectSpecDevice(board); + + if (cpu.includes('r5f') == true) { + cpuName = 'Cortex R'; + } + + if (cpu.includes('a53') == true) { + cpuName = 'Cortex A'; + } + + if (cpu.includes('m4f') == true) { + cpuName = 'Cortex M'; + } + + if (cpu.includes('c66') == true) { + cpuName = 'TMS320C66XX'; + } + + if (cpu.includes('pru') == true) { + if (board == "am64x-evm") { + return "AM64x_GP_EVM"; // check for other devices + } else if (board == "am243x-evm") { + return "AM243x_GP_EVM"; + } else if (board == "am243x-lp") { + return "AM243x_LAUNCHPAD"; + } else if (board == "am263x-cc") { + return "AM263x_CC"; + } else if (board == "am263x-lp") { + return "AM263x_LAUNCHPAD"; + } + } + + return cpuName + '.' + deviceName; + }, + getFileListProjectSpec: (files, filedirs, projectabspath) => { + + let filelist = []; + + for (prop in files) { + if (files.hasOwnProperty(prop) && Array.isArray(files[prop])) { + for (let file of files[prop]) { + let foundFile = false; + for (filedir of filedirs[prop]) { + let checkPath = path.normalize(projectabspath + '/' + filedir + '/' + file); + if (fs.existsSync(checkPath) == true) { + filelist.push(filedir + '/' + file); + foundFile = true; + } + } + if(foundFile == false) { + console.log(`ERROR : Couldn't find ${file} in given source directories for ${projectabspath} ...`) + } + } + } + } + return filelist; + }, + + getToolChainProjectSpec: (cgt) => { + let toolchain = '' + + switch(cgt) { + case 'ti-arm-clang': + toolchain = 'TICLANG' + break; + case 'ti-arm-cgt': + toolchain = 'TI' + break; + case 'gcc-armv7': + toolchain = 'GNU' + break; + case 'gcc-aarch64': + toolchain = 'GNU' + break; + case 'ti-pru-cgt': + toolchain = 'TI' + break; + default: + toolchain = 'TI' + } + + return toolchain; + }, + + getProductNameProjectSpec: (device) => { + + if(common.isDevelopmentMode()) + return "MOTOR_CONTROL_SDK_AMXXX" + + return require(`./device/project_${device}`).getProductNameProjectSpec(); + }, + + getDependentProductNameProjectSpec: (device) => { + + if(common.isDevelopmentMode()) + return "MCU_PLUS_SDK_AMXXX" + + return require(`./device/project_${device}`).getDependentProductNameProjectSpec(); + }, + /* default action for files in project spec, i.e copy or link */ + getDefaultActionProjectSpec: () => { + + if(common.isDevelopmentMode()) + return "copy"; /* use copy for development mode as well */ + + return "copy"; + }, + getToolChainVersionProjectSpec: (cgt) => { + let toolchainVersion = '' + + switch(cgt) { + case 'ti-arm-clang': + toolchainVersion = '2.1.2' + break; + case 'gcc-aarch64': + toolchainVersion = '9.2' + break; + case 'gcc-armv7': + toolchainVersion = '7.2' + break; + case 'ti-c6000': + toolchainVersion = '8.3.12' + break; + case 'ti-pru-cgt': + toolchainVersion = '2.3.3' + break; + } + + return toolchainVersion; + }, + + getSysCfgVersionProjectSpec: () => { + return "1.14.0"; + }, + + getCCSVersionProjectSpec: () => { + return "1210"; + }, + + getTiClangVersionProjectSpec: () => { + return "2.1.2"; + }, + + getGCCAarch64NoneVersionProjectSpec: () => { + return "9.2.1"; + }, + + getGCCArmv7NoneVersionProjectSpec: () => { + return "10"; + }, + + getTitleProjectSpec: (name) => { + let title = name.replace(/_/g, ' '); + + // Title Case : Converts "hello world" to "Hello World" using regex + return title.replace( + /\w\S*/g, + function (s) { + return s.charAt(0).toUpperCase() + s.substr(1).toLowerCase(); + } + ); + } +} + +function genProjectSpecExample(device) { + let example_file_list = require(`./device/project_${device}`).getExampleList(); + + for(example of example_file_list) { + let property = require(`../${example}`).getComponentProperty(device); + + if(property.skipProjectSpec) + continue; + + for(buildOption of property.buildOptionCombos) { + let commonCgtOptions = require(`./cgt/cgt_${buildOption.cgt}`).getCgtOptions(buildOption.cpu, device); + let common_build_property = require(`./device/project_${device}`).getProperty(); + let project = []; + let projectSpecOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + + fs.mkdirSync(projectSpecOutPath, { recursive: true }); + + buildOption.isProjectSpecBuild = true; + build_property = require(`../${example}`).getComponentBuildProperty(buildOption); + + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath); + project = _.merge({}, project, buildOption); + project = _.merge({}, project, build_property); + project = common.mergeCgtOptions(project, commonCgtOptions); + project = common.mergeCgtOptions(project, common_build_property); + project.dirPath = projectSpecOutPath; + + let args = { + sdkName: "MOTOR_CONTROL_SDK_PATH", + sdkPath: common.path.relative(projectSpecOutPath, path.normalize(__dirname + "/..")), + relPath: common.path.relative(project.dirPath, "."), + project: project, + utils: utils, + cgtOptions: require(`./cgt/cgt_${project.cgt}`).getCgtOptions(buildOption.cpu, device), + linuxFwName: require(`./device/project_${device}`).getLinuxFwName(buildOption.cpu), + syscfg: { + device: require(`./device/project_${device}.js`).getSysCfgDevice(buildOption.board), + cpu: require(`./device/project_${device}.js`).getSysCfgCpu(buildOption.cpu), + pkg: require(`./device/project_${device}.js`).getSysCfgPkg(buildOption.board), + part: require(`./device/project_${device}.js`).getSysCfgPart(buildOption.board), + }, + flashAddr: require(`./device/project_${device}.js`).getFlashAddr(), + }; + + common.convertTemplateToFile( + `.project/templates/projectspec_${project.type}.xdt`, + `${project.dirPath}/example.projectspec`, + args); + if("syscfgfile" in args.project) { + common.convertTemplateToFile( + `.project/templates/syscfg_c.rov.xs.xdt`, + `${project.dirPath}/syscfg_c.rov.xs`, + args); + } + if(args.project.skipMakefileCcsBootimageGen) { + // skip makefile_ccs_bootimage_gen + } + else{ + common.convertTemplateToFile( + `.project/templates/makefile_ccs_bootimage_gen.xdt`, + `${project.dirPath}/makefile_ccs_bootimage_gen`, + args); + } + } + } +} + +function genProjectSpecsDevice(device) { + genProjectSpecExample(device); +} + +function cleanProjectSpecsDevice(device) { + let example_file_list = require(`./device/project_${device}`).getExampleList(); + for(example of example_file_list) { + let property = require(`../${example}`).getComponentProperty(device); + + if(property.skipProjectSpec) + continue; + + for(buildOption of property.buildOptionCombos) { + let project = []; + let projectSpecOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + + fs.mkdirSync(projectSpecOutPath, { recursive: true }); + + build_property = require(`../${example}`).getComponentBuildProperty(buildOption); + + project = _.merge({}, project, property); + project.relpath = common.path.relative(path.normalize(__dirname + "/.."), project.dirPath); + project = _.merge({}, project, buildOption); + project = _.merge({}, project, build_property); + project.dirPath = projectSpecOutPath; + + common.deleteFile(`${project.dirPath}/example.projectspec`); + common.deleteFile(`${project.dirPath}/makefile_ccs_bootimage_gen`); + common.deleteFile(`${project.dirPath}/syscfg_c.rov.xs`); + } + } +} + +module.exports = { + genProjectSpecsDevice, + cleanProjectSpecsDevice, + utils, +} diff --git a/.project/genSystemProject.js b/.project/genSystemProject.js new file mode 100644 index 0000000..4fe28e6 --- /dev/null +++ b/.project/genSystemProject.js @@ -0,0 +1,88 @@ +const common = require(`./common.js`); +const fs = require('fs'); + +function genSystemProjectDevice(device) { + let example_file_list = require(`./device/project_${device}`).getExampleList(); + for(example of example_file_list) { + + example = require(`../${example}`); + + if( ! example.getSystemProjects) + continue; + + let property = example.getComponentProperty(device); + let systemProjects = example.getSystemProjects(device); + + for ( project of systemProjects) + { + let outPath = `${property.dirPath}/${project.board}/system_${project.tag}` + + project.device = device; + + let args = { + sdkName: "MOTOR_CONTROL_SDK_PATH", + relPath: common.path.relative(outPath, "."), + project: project, + utils: require(`./genProjectSpec.js`).utils, + device: require(`./device/project_${device}.js`), + }; + + fs.mkdirSync(outPath, { recursive: true }); + + common.convertTemplateToFile( + ".project/templates/makefile_system.xdt", + `${outPath}/makefile`, + args); + + if( project.skipProjectSpec && project.skipProjectSpec === true) + continue; + + common.convertTemplateToFile( + ".project/templates/makefile_system_projectspec.xdt", + `${outPath}/makefile_projectspec`, + args); + common.convertTemplateToFile( + ".project/templates/projectspec_system.xdt", + `${outPath}/system.projectspec`, + args); + common.convertTemplateToFile( + ".project/templates/system.xml.xdt", + `${outPath}/system.xml`, + args); + common.convertTemplateToFile( + ".project/templates/makefile_system_ccs_bootimage_gen.xdt", + `${outPath}/makefile_system_ccs_bootimage_gen`, + args); + } + } +} + +function cleanSystemProjectDevice(device) { + let example_file_list = require(`./device/project_${device}`).getExampleList(); + for(example of example_file_list) { + + example = require(`../${example}`); + + if( ! example.getSystemProjects) + continue; + + let property = example.getComponentProperty(device); + let systemProjects = example.getSystemProjects(device); + + for ( project of systemProjects) + { + let outPath = `${property.dirPath}/${project.board}/system_${project.tag}` + + common.deleteFile(`${outPath}/makefile`); + common.deleteFile(`${outPath}/makefile_system_ccs_bootimage_gen`); + common.deleteFile(`${outPath}/makefile_projectspec`); + common.deleteFile(`${outPath}/system.projectspec`); + common.deleteFile(`${outPath}/system.xml`); + } + } +} + +module.exports = { + genSystemProjectDevice, + cleanSystemProjectDevice, +} diff --git a/.project/genTirex.js b/.project/genTirex.js new file mode 100644 index 0000000..45018a1 --- /dev/null +++ b/.project/genTirex.js @@ -0,0 +1,190 @@ +const common = require(`./common.js`); + +function genTirexSystemProjectContent(example, device) { + let deviceData = require(`./device/project_${device}.js`); + let property = require(`../${example}`).getComponentProperty(device); + let systemProjects = require(`../${example}`).getSystemProjects(device); + let folder_list = common.path.relative("examples", property.dirPath).split("/"); + + let tirex_content = {}; + + tirex_content.resourceType = `project.ccs`; + tirex_content.resourceClass = [ `example` ]; + if(property.tirexResourceSubClass) + { + tirex_content.resourceSubClass = property.tirexResourceSubClass; + } + else + { + tirex_content.resourceSubClass = [ "example.general" ]; + } + if(property.description) + { + tirex_content.description = property.description + " System project."; + } + else + { + tirex_content.description = common.getDefaultSystemProjectDescription(property.name); + } + + tirex_content.name = property.name; + tirex_content.location = common.path.relative(".metadata/.tirex", `${property.dirPath}/${project.board}/system_${project.tag}`) + "/system.projectspec"; + tirex_content.devtools = [ deviceData.getDevToolTirex(project.board) ]; + tirex_content.kernel = []; + /* Temp fix: TIREX doesn't support multiple compiler for a project. System project doesn't need this. So keep it empty */ + //tirex_content.compiler = []; + + /* Temp fix: Push only one kernel as TIREX doesn't support a list yet. Remove when this is fixed */ + tirex_content.kernel.push(project.projects[0].os); + for (subproject of project.projects) + { + /* Temp fix: see above */ + //tirex_content.kernel.push(subproject.os); + /* Temp fix: see above */ + //switch(subproject.cgt) + //{ + // case "ti-arm-clang": + // tirex_content.compiler.push("ticlang"); + // break; + // case "gcc-aarch64": + // tirex_content.compiler.push("gcc"); + // break; + // case "gcc-armv7": + // tirex_content.compiler.push("gcc"); + // break; + //} + } + /* Remove duplicates */ + tirex_content.kernel = [...new Set(tirex_content.kernel)]; + /* Temp fix: see above */ + //tirex_content.compiler = [...new Set(tirex_content.compiler)]; + tirex_content.subCategories = [ ...folder_list, "system_" + `${project.tag}`]; + tirex_content.mainCategories = [[ `Examples`, `Development Tools` ]]; + + return (tirex_content); +} + +function genTirexExampleContentList(example_file_list, device) { + + let tirex_content_list = []; + let deviceData = require(`./device/project_${device}.js`); + let devtools_list = []; /* For userguide */ + + for(example of example_file_list) { + + let property = require(`../${example}`).getComponentProperty(device); + + if(property.skipUpdatingTirex || property.skipProjectSpec || property.isInternal) + continue; + + for(buildOption of property.buildOptionCombos) { + + let projectSpecOutPath = common.path.makeExampleOutPath(property.dirPath, buildOption); + let folder_list = common.path.relative("examples", property.dirPath).split("/"); + let tirex_content = {}; + + tirex_content.resourceType = `project.ccs`; + tirex_content.resourceClass = [ `example` ]; + if(property.tirexResourceSubClass) + { + tirex_content.resourceSubClass = property.tirexResourceSubClass; + } + else + { + tirex_content.resourceSubClass = [ "example.general" ]; + } + if(property.description) + { + tirex_content.description = property.description + " CPU is " + buildOption.cpu.toUpperCase() + " running " + buildOption.os.toUpperCase() + "."; + } + else + { + tirex_content.description = common.getDefaultProjectDescription(property.name, buildOption.cpu, buildOption.os); + } + + tirex_content.name = property.name; + tirex_content.location = common.path.relative(".metadata/.tirex", projectSpecOutPath) + "/example.projectspec"; + let devtools = deviceData.getDevToolTirex(buildOption.board); + tirex_content.devtools = [ devtools ]; + devtools_list.push(devtools); + tirex_content.kernel = []; + tirex_content.compiler = []; + + tirex_content.kernel.push(buildOption.os); + switch(buildOption.cgt) + { + case "ti-arm-clang": + tirex_content.compiler.push("ticlang"); + break; + case "gcc-aarch64": + tirex_content.compiler.push("gcc"); + break; + case "gcc-armv7": + tirex_content.compiler.push("gcc"); + break; + case "ti-c6000": + tirex_content.compiler.push("ccs"); + break; + } + + tirex_content.subCategories = [ ...folder_list, `${buildOption.cpu}` + "_" +`${buildOption.os}`]; + tirex_content.mainCategories = [[ `Examples`, `Development Tools` ]]; + + if (buildOption.os == "freertos-smp") + { + + } + else + { + tirex_content_list.push(tirex_content); + } + } + } + + for(example of example_file_list) { + let tirex_content = {}; + + example_js = require(`../${example}`); + if( ! example_js.getSystemProjects) + continue; + + let property = require(`../${example}`).getComponentProperty(device); + if(property.skipUpdatingTirex || property.skipProjectSpec || property.isInternal) + continue; + let systemProjects = require(`../${example}`).getSystemProjects(device); + for(project of systemProjects) { + tirex_content = genTirexSystemProjectContent(example, device); + tirex_content_list.push(tirex_content); + } + } + + let tirex_content = {}; + + tirex_content.resourceType = `web.page` + tirex_content.resourceClass = [ `document` ]; + tirex_content.name = "User Guide"; + tirex_content.location = `../../docs/api_guide_${device}/index.html`; + tirex_content.devtools = [ ...new Set(devtools_list) ]; + tirex_content.mainCategories = [[ `Documents` ]]; + + tirex_content_list.push(tirex_content); + + let args = { + tirex_content_list + }; + + common.convertTemplateToFile( + `.project/templates/tirex_content.xdt`, + `.metadata/.tirex/${device}.content.tirex.json`, + args); + +} + +function genTirexDevice(device) { + let example_file_list = require(`./device/project_${device}`).getExampleList(); + genTirexExampleContentList(example_file_list, device); +} + +module.exports = { + genTirexDevice +} diff --git a/.project/project.js b/.project/project.js new file mode 100644 index 0000000..2f6c7a2 --- /dev/null +++ b/.project/project.js @@ -0,0 +1,49 @@ +const common = require("./common.js"); +const yargs = require('yargs'); + +const argv = yargs + .usage('Usage: node $0 [OPTIONS]') + .option('device', { + alias: 's', + description: 'DEVICE to generate buildfiles', + type: 'string', + choices: [ "am64x", "am243x", "am263x", "am273x", "awr294x", "am62x" ], + default: "am64x", + array: true + }) + .option('target', { + alias: 't', + description: 'Build target', + type: 'string', + choices: [ "development", "production", "clean" ], + default: "development", + array: false + }) + .option('instrumentation', { + alias: 'i', + description: 'Code Coverage Instrumentation', + type: 'string', + choices: [ "enable", "disable" ], + default: "disable", + array: false + }) + .help() + .alias('help', 'h') + .argv; + +if(argv.target == "clean") { + for(device of argv.device) { + console.log(`Cleaning build files for ${device} ...`); + common.cleanBuildfiles(device); + } + console.log("Cleaning build files ... Done !!!") +} +else { + common.setGenBuildFilesMode(argv.target); + common.setInstrumentationMode(argv.instrumentation); + for(device of argv.device) { + console.log(`Generating build files for ${device} in ${argv.target} mode ...`); + common.genBuildfiles(device); + } + console.log("Generating build files ... Done !!!") +} diff --git a/.project/templateCompiler.js b/.project/templateCompiler.js new file mode 100644 index 0000000..8ca41f3 --- /dev/null +++ b/.project/templateCompiler.js @@ -0,0 +1,95 @@ +let _ = require("lodash"); + +// Returns the compiled source from the template source. The compiled source +// is in the form of a exports = templateFunction(argsObj); so it can be used +// just like a script would. + +function compileTemplate(templateSource) { + + templateSource = adaptSource(templateSource); + + let compiled; + try { + compiled = _.template(templateSource, templateSettings).source; + } catch (err) { + if (!err.source || !_.startsWith(err.toString(), "SyntaxError")) { + throw err; + } + compiled = err; + } + compiled = "return " + compiled + " ;" + return compiled; +} + +const templateSettings = { + + // Setup _.template to work just like RTSC/XDC + // %%{\n + // stmt ...\n + // stmt ...\n + // %%}\n + // Multiple lines of script to be evaluated at this point. + + // Some notes about the regex: + // %%\{ matches %%{ + // ([\s\S]*?) captures whatever is next as few times as possible + // %%\} matches %%} + // \r?\n? matches a eol on any OS if there, this way the block doesn't + // include a newline in the output + + evaluate: /%%\{([\s\S]*?)%%\}\r?\n?/g, + + // text`script`text ... \n + // A line of text to be output by the template at this + // point. If present, all script between and including the + // `` quotes is replaced with its (textual) value in the + // current context. + + interpolate: /`([\s\S]*?)`/g, + + // This prevents lodash from generating a "with" statement to make the keys + // of the passed in object instantiated. Instead, "args" is the name of the + // object passed in + + variable: "args", +}; + +function adaptSource(templateSource) { + + // % script ... \n + // a single line of script evaluated by the template at + // this point + + // Now, regex replace "% ..." with "%%{ ... %%}" + // Some notes about the regex: + // ^ matches a new line + // [\t\f ] matches any tab, form feed or space + // we use this because \s would match \r\n + // % matches % + // (?!%) excludes matching if a % follows the first $ (to exclude %%{ and %%}) + // (.*?) matches and captures everything except the line terminator + // $ matches the line terminator + + templateSource = templateSource.replace(/^[\t\f ]*%(?!%)(.*?)$/gm, "%%{$1\n%%}"); + + // Next, if we have adjacent escaped blocks (ie adjacent %%} and %%{), + // we shoudl combine them into one block. This allows people to escape + // adjacent lines using % but still have it be logically inline. If we + // don't do this, then _ will add a ; between the blocks. + + templateSource = templateSource.replace(/%%}\r?\n%%{/g, ""); + + return templateSource; +} + +function executeTemplate(templateSource, args) { + let compile = compileTemplate(templateSource); + let func1 = new Function(compile); + let func2 = func1(); + + return func2(args); +} + +module.exports = { + executeTemplate, +} diff --git a/.project/templates/am243x/common/linker_m4f.cmd.xdt b/.project/templates/am243x/common/linker_m4f.cmd.xdt new file mode 100644 index 0000000..6c91290 --- /dev/null +++ b/.project/templates/am243x/common/linker_m4f.cmd.xdt @@ -0,0 +1,74 @@ +%%{ + let options = args.options; + + let stackSize = 16*1024; + let heapSize = 32*1024; + + /* if no options given use defaults */ + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.heapSize) + heapSize = options.heapSize; +%%} + +/* make sure below retain is there in your linker command file, it keeps the vector table in the final binary */ +--retain="*(.vectors)" +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=`stackSize` +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=`heapSize` + + +SECTIONS +{ + /* This has the M4F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > M4F_VECS + .text: {} palign(8) > M4F_IRAM /* This is where code resides */ + + .bss: {} palign(8) > M4F_DRAM /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + + .data: {} palign(8) > M4F_DRAM /* This is where initialized globals and static go */ + .rodata: {} palign(8) > M4F_DRAM /* This is where const's go */ + .sysmem: {} palign(8) > M4F_IRAM /* This is where the malloc heap goes */ + .stack: {} palign(8) > M4F_IRAM /* This is where the main() stack goes */ + + /* Sections needed for C++ projects */ + .ARM.exidx: {} palign(8) > M4F_IRAM /* Needed for C++ exception handling */ + .init_array: {} palign(8) > M4F_IRAM /* Contains function pointers called before main */ + .fini_array: {} palign(8) > M4F_IRAM /* Contains function pointers called after main */ + + /* General purpose user shared memory */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > IPC_VRING_MEM +} + +MEMORY +{ + M4F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000200 + M4F_IRAM : ORIGIN = 0x00000200 , LENGTH = 0x0002FE00 + M4F_DRAM : ORIGIN = 0x00030000 , LENGTH = 0x00010000 + + /* shared memories that are used by all cores */ + /* On M4F, + * - By default MSMC RAM is not accessible to M4F, a RAT entry is needed to make it + * accessible on M4F + * - So make sure there is a RAT entry which has a 1:1 mapping from 0x70000000 to 0x70200000 + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + IPC_VRING_MEM: ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/.project/templates/am243x/common/linker_r5f.cmd.xdt b/.project/templates/am243x/common/linker_r5f.cmd.xdt new file mode 100644 index 0000000..7a279a8 --- /dev/null +++ b/.project/templates/am243x/common/linker_r5f.cmd.xdt @@ -0,0 +1,342 @@ +%%{ + let options = args.options; + + let stackSize = 16*1024; + let heapSize = 32*1024; + /* with nested interrupts logic added, IRQ stack is only used minimally, instead + * SVC stack is used, hence IRQ stack size is less as compared to SVC stack + */ + let irqStackSize = 256; + let svcStackSize = 4*1024; + let fiqStackSize = 256; + let abortStackSize = 256; + let undefinedStackSize = 256; + let codeDataAddr = 0; + let codeDataSize = 0; + let nocacheDataSize = 0; + let codeDataAddrDdr = 0; + let codeDataSizeDdr = 0; + let codeDataAddrFlash = 0; + let codeDataSizeFlash = 0; + let nocacheDataAddr = 0; + let useDdr = false; + let useFlash = false; + let addrBase = 0; + let addrBaseDdr = 0; + let addrBaseFlash = 0; + let nocacheAddrBase = 0; + let isSingleCore = false; + /* Temp change till we support DDR - alloc all memory to single core + * as we don't plan to run code coverage for system project */ + if(args.isInstrumentation) + { + isSingleCore = true; + } + let isIcssPktBufEnable = false; + + if(options && options.isXip) + { + useFlash = true; + } + + /* if no options given use defaults */ + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.heapSize) + heapSize = options.heapSize; + if(options && options.irqStackSize) + irqStackSize = options.irqStackSize; + if(options && options.fiqStackSize) + fiqStackSize = options.fiqStackSize; + if(options && options.svcStackSize) + svcStackSize = options.svcStackSize; + if(options && options.abortStackSize) + abortStackSize = options.abortStackSize; + if(options && options.undefinedStackSize) + undefinedStackSize = options.undefinedStackSize; + if(options && options.isSingleCore) + isSingleCore = options.isSingleCore; + if(options && options.isIcssPktBufEnable) + isIcssPktBufEnable = options.isIcssPktBufEnable; + + if(isSingleCore === true) { + codeDataSize = 0x40000 * 4; + codeDataSizeFlash = 0x80000; + codeDataSizeDdr = 0x1000000 * 4; + nocacheDataSize = 0x8000; + } + else { + codeDataSize = 0x40000; + codeDataSizeFlash = 0x80000; + codeDataSizeDdr = 0x1000000; + nocacheDataSize = 0x8000; + } + + /* offset from top of codeDataAddrDdr where the code/data is actually placed, + the first codeDataOffsetDdr bytes are used for IPC in linux + */ + codeDataOffsetDdr = 0x100000; + + if(args.project.isLinuxInSystem === true) { + addrBase = 0x70040000; + addrBaseDdr = 0xA0000000; + addrBaseFlash = 0x60100000; + useDdr = true; + } else { + addrBase = 0x70080000; + addrBaseFlash = 0x60100000; + nocacheAddrBase = 0x70060000; + } + if(isSingleCore === true) { + codeDataAddr = addrBase; + codeDataAddrDdr = addrBaseDdr; + codeDataAddrFlash = addrBaseFlash; + nocacheDataAddr = nocacheAddrBase; + } + else { + if(args.project.cpu == "r5fss0-0") { + codeDataAddr = addrBase + codeDataSize*0; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*0; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*0; + } + if(args.project.cpu == "r5fss0-1") { + codeDataAddr = addrBase + codeDataSize*1; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*1; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*1; + } + if(args.project.cpu == "r5fss1-0") { + codeDataAddr = addrBase + codeDataSize*2; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*2; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*2; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*2; + } + if(args.project.cpu == "r5fss1-1") { + codeDataAddr = addrBase + codeDataSize*3; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*3; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*3; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*3; + } + } + if(options && options.codeDataAddr) + codeDataAddr = options.codeDataAddr; + if(options && options.codeDataSize) + codeDataSize = options.codeDataSize; + if(options && options.codeDataAddrFlash) + codeDataAddrFlash = options.codeDataAddrFlash; + if(options && options.codeDataSizeFlash) + codeDataSizeFlash = options.codeDataSizeFlash; +%%} + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=`stackSize` +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=`heapSize` +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = `irqStackSize`; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = `fiqStackSize`; +__SVC_STACK_SIZE = `svcStackSize`; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = `abortStackSize`; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = `undefinedStackSize`; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + % if(useDdr) { + } > DDR + % } else if(useFlash) { + } > FLASH + % } else { + } > MSRAM + % } + + % if(useFlash) { + GROUP { + .rodata.cfg: {} palign(8) /* This is to keep the MPU config, Cache config and other consts */ + } > MSRAM + % } + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + % if(useDdr) { + /* This is the resource table used by linux to know where the IPC "VRINGs" are located */ + .resource_table: {} palign(4096) + % } + .data: {} palign(8) /* This is where initialized globals and static go */ + % if(useDdr) { + } > DDR + % } else { + } > MSRAM + % } + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + % if(useDdr) { + } > DDR + % } else { + } > MSRAM + % } + + % if(args.isInstrumentation) { + GROUP { + __llvm_prf_cnts: {} align(8) + RUN_START(__start___llvm_prf_cnts) + RUN_END(__stop___llvm_prf_cnts) + } > MSRAM + + % } + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + % if(useDdr) { + } > DDR + % } else { + } > MSRAM + % } + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + % if(useDdr) { + } > DDR + % } else if(useFlash) { + } > FLASH + % } else { + } > MSRAM + % } + + % if (isIcssPktBufEnable) { + /* Packet buffer memory used by ICCS */ + .bss.icss_emac_pktbuf_mem (NOLOAD): {} > ICSS_PKT_BUF_MEM + % } + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + % if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */ + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM + % } +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + % if (isIcssPktBufEnable) { + /* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */ + ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000 + + % } + % if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */ + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x`nocacheDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`nocacheDataSize.toString(16).toUpperCase()` + + % } + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x`codeDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSize.toString(16).toUpperCase()` + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x`codeDataAddrFlash.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSizeFlash.toString(16).toUpperCase()` + + % if(useDdr) { + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + DDR : ORIGIN = 0x`(codeDataAddrDdr+codeDataOffsetDdr).toString(16).toUpperCase()` , LENGTH = 0x`(codeDataSizeDdr - codeDataOffsetDdr).toString(16).toUpperCase()` + + % } + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 + % if(args.project.isLinuxInSystem) { + LINUX_IPC_SHM_MEM : ORIGIN = 0x`codeDataAddrDdr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataOffsetDdr.toString(16).toUpperCase()` + % } +} diff --git a/.project/templates/am243x/common/pru/hexpru.cmd.xdt b/.project/templates/am243x/common/pru/hexpru.cmd.xdt new file mode 100644 index 0000000..7115335 --- /dev/null +++ b/.project/templates/am243x/common/pru/hexpru.cmd.xdt @@ -0,0 +1,3 @@ +-b +-map=pru_project.map +SECTIONS {.text} diff --git a/.project/templates/am243x/common/pru/linker_pru0.cmd.xdt b/.project/templates/am243x/common/pru/linker_pru0.cmd.xdt new file mode 100644 index 0000000..105f52d --- /dev/null +++ b/.project/templates/am243x/common/pru/linker_pru0.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM243x_PRU0.cmd + * + * Example Linker command file for linking programs built with the TI-PRU-CGT + * on AM243x PRU0 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 12 KB PRU Instruction RAM */ + PRU_IMEM : org = 0x00000000 len = 0x00003000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve + * the second 4 KB for RTU0 and Tx_PRU0 */ + PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1, + * RTU1 and Tx_PRU1; do not use for any Slice0 cores */ + PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU0_DMEM_0 : org = 0x00001000 len = 0x00000800 + TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800 + RTU0_DMEM_1 : org = 0x00003000 len = 0x00000800 + TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > PRU_IMEM, PAGE 0 + .stack > PRU_IMEM, PAGE 0 + .bss > PRU0_DMEM_0, PAGE 1 + /* + .cio > PRU0_DMEM_0, PAGE 1 + .data > PRU0_DMEM_0, PAGE 1 + .switch > PRU0_DMEM_0, PAGE 1 + .sysmem > PRU0_DMEM_0, PAGE 1 + .cinit > PRU0_DMEM_0, PAGE 1 + .rodata > PRU0_DMEM_0, PAGE 1 + .rofardata > PRU0_DMEM_0, PAGE 1 + .farbss > PRU0_DMEM_0, PAGE 1 + .fardata > PRU0_DMEM_0, PAGE 1 + */ +} diff --git a/.project/templates/am243x/common/pru/linker_pru1.cmd.xdt b/.project/templates/am243x/common/pru/linker_pru1.cmd.xdt new file mode 100644 index 0000000..1afbd14 --- /dev/null +++ b/.project/templates/am243x/common/pru/linker_pru1.cmd.xdt @@ -0,0 +1,88 @@ +/* + * AM243x_PRU1.cmd + * + * Example Linker command file for linking programs built with the C compiler + * on AM243x PRU1 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 12 KB PRU Instruction RAM */ + PRU_IMEM : org = 0x00000000 len = 0x00003000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve + * the second 4 KB for RTU1 and Tx_PRU1 */ + PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0, + * RTU0 and Tx_PRU0; do not use for any Slice1 cores */ + PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800 + TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800 + RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800 + TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > PRU_IMEM, PAGE 0 + .stack > PRU_IMEM, PAGE 1 + /* TODO: review if this should be PRU1_DMEM_1 */ + .bss > PRU1_DMEM_0, PAGE 1 + /* + .cio > PRU1_DMEM_0, PAGE 1 + .data > PRU1_DMEM_0, PAGE 1 + .switch > PRU1_DMEM_0, PAGE 1 + .sysmem > PRU1_DMEM_0, PAGE 1 + .cinit > PRU1_DMEM_0, PAGE 1 + .rodata > PRU1_DMEM_0, PAGE 1 + .rofardata > PRU1_DMEM_0, PAGE 1 + .farbss > PRU1_DMEM_0, PAGE 1 + .fardata > PRU1_DMEM_0, PAGE 1 + */ +} \ No newline at end of file diff --git a/.project/templates/am243x/common/pru/linker_rtu_pru0.cmd.xdt b/.project/templates/am243x/common/pru/linker_rtu_pru0.cmd.xdt new file mode 100644 index 0000000..1517670 --- /dev/null +++ b/.project/templates/am243x/common/pru/linker_rtu_pru0.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM243x_RTU_PRU0.cmd + * + * Example Linker command file for linking programs built with the TI-PRU-CGT + * on AM243x RTU_PRU0 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 8 KB PRU Instruction RAM */ + RTU_PRU_IMEM : org = 0x00000000 len = 0x00002000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve + * the second 4 KB for RTU0 and Tx_PRU0 */ + PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1, + * RTU1 and Tx_PRU1; do not use for any Slice0 cores */ + PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800 + TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800 + RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800 + TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > RTU_PRU_IMEM, PAGE 0 + .stack > RTU_PRU_IMEM, PAGE 0 + .bss > RTU_PRU0_DMEM_0, PAGE 1 + /* + .cio > RTU_PRU0_DMEM_0, PAGE 1 + .data > RTU_PRU0_DMEM_0, PAGE 1 + .switch > RTU_PRU0_DMEM_0, PAGE 1 + .sysmem > RTU_PRU0_DMEM_0, PAGE 1 + .cinit > RTU_PRU0_DMEM_0, PAGE 1 + .rodata > RTU_PRU0_DMEM_0, PAGE 1 + .rofardata > RTU_PRU0_DMEM_0, PAGE 1 + .farbss > RTU_PRU0_DMEM_0, PAGE 1 + .fardata > RTU_PRU0_DMEM_0, PAGE 1 + */ +} \ No newline at end of file diff --git a/.project/templates/am243x/common/pru/linker_rtu_pru1.cmd.xdt b/.project/templates/am243x/common/pru/linker_rtu_pru1.cmd.xdt new file mode 100644 index 0000000..1bec835 --- /dev/null +++ b/.project/templates/am243x/common/pru/linker_rtu_pru1.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM243x_RTU_PRU1.cmd + * + * Example Linker command file for linking programs built with the C compiler + * on AM243x RTU_PRU1 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 8 KB PRU Instruction RAM */ + RTU_PRU_IMEM : org = 0x00000000 len = 0x00002000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve + * the second 4 KB for RTU1 and Tx_PRU1 */ + PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0, + * RTU0 and Tx_PRU0; do not use for any Slice1 cores */ + PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800 + TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800 + RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800 + TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > RTU_PRU_IMEM, PAGE 0 + .stack > RTU_PRU_IMEM, PAGE 1 + .bss > RTU_PRU1_DMEM_0, PAGE 1 + /* + .cio > RTU_PRU1_DMEM_0, PAGE 1 + .data > RTU_PRU1_DMEM_0, PAGE 1 + .switch > RTU_PRU1_DMEM_0, PAGE 1 + .sysmem > RTU_PRU1_DMEM_0, PAGE 1 + .cinit > RTU_PRU1_DMEM_0, PAGE 1 + .rodata > RTU_PRU1_DMEM_0, PAGE 1 + .rofardata > RTU_PRU1_DMEM_0, PAGE 1 + .farbss > RTU_PRU1_DMEM_0, PAGE 1 + .fardata > RTU_PRU1_DMEM_0, PAGE 1 + */ +} \ No newline at end of file diff --git a/.project/templates/am243x/common/pru/linker_tx_pru0.cmd.xdt b/.project/templates/am243x/common/pru/linker_tx_pru0.cmd.xdt new file mode 100644 index 0000000..1ae7484 --- /dev/null +++ b/.project/templates/am243x/common/pru/linker_tx_pru0.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM243x_TX_PRU0.cmd + * + * Example Linker command file for linking programs built with the TI-PRU-CGT + * on AM243x TX_PRU0 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 6 KB PRU Instruction RAM */ + TX_PRU_IMEM : org = 0x00000000 len = 0x00001800 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve + * the second 4 KB for RTU0 and Tx_PRU0 */ + PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1, + * RTU1 and Tx_PRU1; do not use for any Slice0 cores */ + PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800 + TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800 + RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800 + TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > TX_PRU_IMEM, PAGE 0 + .stack > TX_PRU_IMEM, PAGE 0 + .bss > TX_PRU0_DMEM_0, PAGE 1 + /* + .cio > TX_PRU0_DMEM_0, PAGE 1 + .data > TX_PRU0_DMEM_0, PAGE 1 + .switch > TX_PRU0_DMEM_0, PAGE 1 + .sysmem > TX_PRU0_DMEM_0, PAGE 1 + .cinit > TX_PRU0_DMEM_0, PAGE 1 + .rodata > TX_PRU0_DMEM_0, PAGE 1 + .rofardata > TX_PRU0_DMEM_0, PAGE 1 + .farbss > TX_PRU0_DMEM_0, PAGE 1 + .fardata > TX_PRU0_DMEM_0, PAGE 1 + */ +} diff --git a/.project/templates/am243x/common/pru/linker_tx_pru1.cmd.xdt b/.project/templates/am243x/common/pru/linker_tx_pru1.cmd.xdt new file mode 100644 index 0000000..13a0db3 --- /dev/null +++ b/.project/templates/am243x/common/pru/linker_tx_pru1.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM243x_TX_PRU1.cmd + * + * Example Linker command file for linking programs built with the C compiler + * on AM243x TX_PRU1 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 6 KB TX_PRU Instruction RAM */ + TX_PRU_IMEM : org = 0x00000000 len = 0x00001800 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve + * the second 4 KB for RTU1 and Tx_PRU1 */ + PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0, + * RTU0 and Tx_PRU0; do not use for any Slice1 cores */ + PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800 + TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800 + RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800 + TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of Tx_PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > TX_PRU_IMEM, PAGE 0 + .stack > TX_PRU_IMEM, PAGE 1 + .bss > TX_PRU1_DMEM_0, PAGE 1 + /* + .cio > TX_PRU1_DMEM_0, PAGE 1 + .data > TX_PRU1_DMEM_0, PAGE 1 + .switch > TX_PRU1_DMEM_0, PAGE 1 + .sysmem > TX_PRU1_DMEM_0, PAGE 1 + .cinit > TX_PRU1_DMEM_0, PAGE 1 + .rodata > TX_PRU1_DMEM_0, PAGE 1 + .rofardata > TX_PRU1_DMEM_0, PAGE 1 + .farbss > TX_PRU1_DMEM_0, PAGE 1 + .fardata > TX_PRU1_DMEM_0, PAGE 1 + */ +} \ No newline at end of file diff --git a/.project/templates/am243x/freertos/FreeRTOSConfig.h.xdt b/.project/templates/am243x/freertos/FreeRTOSConfig.h.xdt new file mode 100644 index 0000000..ec6f827 --- /dev/null +++ b/.project/templates/am243x/freertos/FreeRTOSConfig.h.xdt @@ -0,0 +1,179 @@ +%%{ + let cpu = args.project.cpu; +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef TI_FREERTOS_CONFIG_H +#define TI_FREERTOS_CONFIG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE + * FreeRTOS REFERENCE MANUAL. + *----------------------------------------------------------*/ + +/* Keep below as 1 if the most optimized task switching latency is needed. + * This disables tracing, logging, assert and other error checks. + * So unless every last cycle of task switching is important leave this as 0. + * + * This is not a FreeRTOS defined config and is defined by TI to quickly switch + * between optimized and not-so-optimized config + */ +#define configOPTIMIZE_FOR_LATENCY (0) + +#define configUSE_PREEMPTION (1) +#define configUSE_PORT_OPTIMISED_TASK_SELECTION (`(cpu === "r5f") ? 0 : 1`) +#define configUSE_TICKLESS_IDLE (0) +#define configUSE_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationIdleHook(void) as the hook function */ +#define configUSE_MALLOC_FAILED_HOOK (0) +#define configUSE_DAEMON_TASK_STARTUP_HOOK (0) +#define configUSE_TICK_HOOK (0) +#define configCPU_CLOCK_HZ (0) /* NOT USED in TI ports */ +#define configSYSTICK_CLOCK_HZ (0) /* NOT USED in TI ports */ +#define configTICK_RATE_HZ (1000) +#define configMAX_PRIORITIES (32) +#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */ +#define configMAX_TASK_NAME_LEN (32) +#define configUSE_TRACE_FACILITY (1) +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configUSE_STATS_FORMATTING_FUNCTIONS (1) +#else +#define configUSE_STATS_FORMATTING_FUNCTIONS (0) +#endif +#define configUSE_16_BIT_TICKS (0) +#define configIDLE_SHOULD_YIELD (1) +#define configUSE_TASK_NOTIFICATIONS (1) +#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1) +#define configUSE_MUTEXES (1) +#define configUSE_RECURSIVE_MUTEXES (1) +#define configUSE_COUNTING_SEMAPHORES (1) +#define configUSE_ALTERNATIVE_API (0) + +/* when = 1, Need to provied below, + * void vApplicationStackOverflowHook( TaskHandle_t xTask, + * char *pcTaskName ); + */ +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configCHECK_FOR_STACK_OVERFLOW (1) +#else +#define configCHECK_FOR_STACK_OVERFLOW (0) +#endif +#define configQUEUE_REGISTRY_SIZE (32) +#define configUSE_QUEUE_SETS (0) +#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */ +#define configUSE_NEWLIB_REENTRANT (0) +#define configENABLE_BACKWARD_COMPATIBILITY (1) +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4) +#define configSTACK_DEPTH_TYPE UBaseType_t +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below, + * + * void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, + * StackType_t **ppxTimerTaskStackBuffer, + * uint32_t *pulTimerTaskStackSize ); + * + * void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, + * StackType_t **ppxIdleTaskStackBuffer, + * uint32_t *pulIdleTaskStackSize ); + */ +#define configSUPPORT_DYNAMIC_ALLOCATION (1) +#define configTOTAL_HEAP_SIZE (4*1024) /* not used when heap_3.c is the selected heap */ +#define configAPPLICATION_ALLOCATED_HEAP (0) + +/* run-time stats config */ +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configGENERATE_RUN_TIME_STATS (1) +#else +#define configGENERATE_RUN_TIME_STATS (0) +#endif +void vPortConfigTimerForRunTimeStats(); +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats() +uint32_t uiPortGetRunTimeCounterValue(); +#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue() + +/* co-routine related config */ +#define configUSE_CO_ROUTINES (0) +#define configMAX_CO_ROUTINE_PRIORITIES (0) + +/* timer related config */ +#define configUSE_TIMERS (1) +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH (16) +#define configTIMER_TASK_STACK_DEPTH (256) + +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U) +#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY) +#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY) + +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configASSERT(x) DebugP_assert( (uint32_t)(x)) +#endif + +/* MPU aware FreeRTOS, not supported as TI */ +#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0) +#define configTOTAL_MPU_REGIONS (0) +#undef configTEX_S_C_B_FLASH +#undef configTEX_S_C_B_SRAM +#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0) + +/* defines need for FreeRTOS+POSIX*/ +#define configUSE_POSIX_ERRNO (1) +#define configUSE_APPLICATION_TASK_TAG (1) + +/* include specific functions */ +#define INCLUDE_vTaskDelete (1) +#define INCLUDE_vTaskDelay (1) +#define INCLUDE_vTaskSuspend (1) +#define INCLUDE_xTimerDelete (1) +#define INCLUDE_vSemaphoreDelete (1) +#define INCLUDE_xTimerPendFunctionCall (1) +#define INCLUDE_xTaskGetIdleTaskHandle (1) + +#ifdef __cplusplus +} +#endif + +#endif /* TI_FREERTOS_CONFIG_H */ diff --git a/.project/templates/am243x/freertos/main_freertos.c.xdt b/.project/templates/am243x/freertos/main_freertos.c.xdt new file mode 100644 index 0000000..a87517c --- /dev/null +++ b/.project/templates/am243x/freertos/main_freertos.c.xdt @@ -0,0 +1,98 @@ +%%{ + let options = args.options; + let stackSize = 16*1024; + let taskPri = "configMAX_PRIORITIES-1" + let entryFunction = "example_main"; + + if(options && options.entryFunction) + entryFunction = options.entryFunction; + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.taskPri) + taskPri = options.taskPri; + +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (`taskPri`) + +#define MAIN_TASK_SIZE (`stackSize`U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void `entryFunction`(void *args); + +void freertos_main(void *args) +{ + `entryFunction`(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/.project/templates/am243x/gpio/board_gpio.c.xdt b/.project/templates/am243x/gpio/board_gpio.c.xdt new file mode 100644 index 0000000..6ca99c1 --- /dev/null +++ b/.project/templates/am243x/gpio/board_gpio.c.xdt @@ -0,0 +1,186 @@ +%%{ + let options = args.options; + + exampleType = "input_interrupt"; + if(options && options.exampleType) + exampleType = options.exampleType; + +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +% if ( exampleType == "input_interrupt" ) { +#include +% } +#include "ti_drivers_config.h" + +/* + * Board info + */ +% if ( exampleType == "input_interrupt" ) { +/* This is based on DMSC board config and core */ +#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8) +#define BOARD_BUTTON_GPIO_SWITCH_NUM (5) + +/** \brief bank interrupt source index base */ +#define TISCI_BANK_SRC_IDX_BASE_GPIO0 (90U) +#define TISCI_BANK_SRC_IDX_BASE_GPIO1 (90U) +#define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (90U) + +static void Sciclient_gpioIrqSet(void); +static void Sciclient_gpioIrqRelease(void); + +void Board_gpioInit(void) +{ + Sciclient_gpioIrqSet(); +} + +void Board_gpioDeinit(void) +{ + Sciclient_gpioIrqRelease(); +} + +uint32_t Board_getGpioButtonIntrNum(void) +{ + return (BOARD_BUTTON_GPIO_INTR_NUM); +} + +uint32_t Board_getGpioButtonSwitchNum(void) +{ + return (BOARD_BUTTON_GPIO_SWITCH_NUM); +} + +static void Sciclient_gpioIrqSet(void) +{ + int32_t retVal; + struct tisci_msg_rm_irq_set_req rmIrqReq; + struct tisci_msg_rm_irq_set_resp rmIrqResp; + + /* For setting the IRQ for GPIO using sciclient APIs, we need to populate + * a structure, tisci_msg_rm_irq_set_req instantiated above. The definition + * of this struct and details regarding the struct members can be found in + * the tisci_rm_irq.h. + */ + /* Initialize all flags to zero since we'll be setting only a few */ + rmIrqReq.valid_params = 0U; + /* Our request has a destination id, so enable the flag for DST ID */ + rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID; + /* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */ + rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID; + /* This is not a global event */ + rmIrqReq.global_event = 0U; + /* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW. + * The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/. + * In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt, + * we need to choose the TISCI_DEV_GPIO1 + */ + rmIrqReq.src_id = TISCI_DEV_GPIO1; + /* This is the interrupt source index within the GPIO peripheral */ + rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN); + /* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core. + * For a different core, the corresponding TISCI device id has to be provided */ + rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0; + /* This is the output index of the interrupt router. This depends on the core and board configuration */ + rmIrqReq.dst_host_irq = Board_getGpioButtonIntrNum(); + /* Rest of the struct members are unused for GPIO interrupt */ + rmIrqReq.ia_id = 0U; + rmIrqReq.vint = 0U; + rmIrqReq.vint_status_bit_index = 0U; + rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST; + + /* To set the interrupt we now invoke the Sciclient_rmIrqSet function which + * will find out the route to configure the interrupt and request DMSC to + * grant the resource + */ + retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER); + if(0 != retVal) + { + DebugP_log("[Error] Sciclient event config failed!!!\r\n"); + DebugP_assert(FALSE); + } + + return; +} + +static void Sciclient_gpioIrqRelease(void) +{ + int32_t retVal; + struct tisci_msg_rm_irq_release_req rmIrqReq; + /* For releasing the IRQ for GPIO using sciclient APIs, we need to populate + * a structure, tisci_msg_rm_irq_release_req instantiated above. The definition + * of this struct and details regarding the struct members can be found in + * the tisci_rm_irq.h. These are similar to the struct members for the set request + * used above. + */ + /* Initialize all flags to zero since we'll be setting only a few */ + rmIrqReq.valid_params = 0U; + /* Our request has a destination id, so enable the flag for DST ID */ + rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID; + /* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */ + rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID; + /* This is not a global event */ + rmIrqReq.global_event = 0U; + /* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW. + * The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/. + * In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt, + * we need to choose the TISCI_DEV_GPIO1 + */ + rmIrqReq.src_id = TISCI_DEV_GPIO1; + /* This is the interrupt source index within the GPIO peripheral */ + rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN); + /* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core. + * For a different core, the corresponding TISCI device id has to be provided */ + rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0; + /* This is the output index of the interrupt router. This depends on the core and board configuration */ + rmIrqReq.dst_host_irq = Board_getGpioButtonIntrNum(); + /* Rest of the struct members are unused for GPIO interrupt */ + rmIrqReq.ia_id = 0U; + rmIrqReq.vint = 0U; + rmIrqReq.vint_status_bit_index = 0U; + rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST; + + /* To set the interrupt we now invoke the Sciclient_rmIrqRelease function which + * will find specifics about the route and request DMSC/SYSFW to relase/clear the interrupt + */ + retVal = Sciclient_rmIrqRelease(&rmIrqReq, SystemP_WAIT_FOREVER); + if(0 != retVal) + { + DebugP_log("[Error] Sciclient event reset failed!!!\r\n"); + DebugP_assert(FALSE); + } + + return; +} +% } diff --git a/.project/templates/am243x/i2c/board_i2c.c.xdt b/.project/templates/am243x/i2c/board_i2c.c.xdt new file mode 100644 index 0000000..cf7804d --- /dev/null +++ b/.project/templates/am243x/i2c/board_i2c.c.xdt @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_board_open_close.h" + +/* + * Board info + */ +uint32_t Board_getnumLedPerGroup(void) +{ +%if(args.project.board == "am243x-lp") { + /* For AM243x-LP board only 4 leds are connected */ + uint32_t ledCount = 4U; +%} +%else { + uint32_t ledCount; + const LED_Attrs *attrs; + + attrs = LED_getAttrs(CONFIG_LED0); + DebugP_assert(NULL != attrs); + /* For AM243x-EVM all LEDs are connected, so return + * the driver atrributes value of 8 */ + ledCount = attrs->numLedPerGroup; +%} + + return ledCount; +} diff --git a/.project/templates/am243x/nortos/main_nortos.c.xdt b/.project/templates/am243x/nortos/main_nortos.c.xdt new file mode 100644 index 0000000..84b7af3 --- /dev/null +++ b/.project/templates/am243x/nortos/main_nortos.c.xdt @@ -0,0 +1,58 @@ +%%{ + let options = args.options; + + entryFunction = "example_main"; + + if(options && options.entryFunction) + entryFunction = options.entryFunction; +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" + +void `entryFunction`(void *args); + +int main(void) +{ + System_init(); + Board_init(); + + `entryFunction`(NULL); + + Board_deinit(); + System_deinit(); + + return 0; +} diff --git a/.project/templates/am263x/common/linker_r5f.cmd.xdt b/.project/templates/am263x/common/linker_r5f.cmd.xdt new file mode 100644 index 0000000..4c5cc2d --- /dev/null +++ b/.project/templates/am263x/common/linker_r5f.cmd.xdt @@ -0,0 +1,266 @@ +%%{ + let options = args.options; + + let stackSize = 16*1024; + let heapSize = 32*1024; + /* with nested interrupts logic added, IRQ stack is only used minimally, instead + * SVC stack is used, hence IRQ stack size is less as compared to SVC stack + */ + let irqStackSize = 256; + let svcStackSize = 4*1024; + let fiqStackSize = 256; + let abortStackSize = 256; + let undefinedStackSize = 256; + let codeDataAddr = 0; + let codeDataSize = 0; + let codeDataAddrFlash = 0; + let codeDataSizeFlash = 0; + let useFlash = false; + let addrBase = 0; + let addrBaseFlash = 0; + let isSingleCore = false; + /* Temp change till we support DDR - alloc all memory to single core + * as we don't plan to run code coverage for system project */ + if(args.isInstrumentation) + { + isSingleCore = true; + } + let isIcssPktBufEnable = false; + + if(options && options.isXip) + { + useFlash = true; + } + + /* if no options given use defaults */ + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.heapSize) + heapSize = options.heapSize; + if(options && options.irqStackSize) + irqStackSize = options.irqStackSize; + if(options && options.fiqStackSize) + fiqStackSize = options.fiqStackSize; + if(options && options.svcStackSize) + svcStackSize = options.svcStackSize; + if(options && options.abortStackSize) + abortStackSize = options.abortStackSize; + if(options && options.undefinedStackSize) + undefinedStackSize = options.undefinedStackSize; + if(options && options.isSingleCore) + isSingleCore = options.isSingleCore; + if(options && options.isIcssPktBufEnable) + isIcssPktBufEnable = options.isIcssPktBufEnable; + + if(isSingleCore === true) { + codeDataSize = 0x40000 * 4; + codeDataSizeFlash = 0x80000; + } + else { + codeDataSize = 0x40000; + codeDataSizeFlash = 0x80000; + } + + /* MSS mailbox memory */ + let ipcShmAddrBase = 0x72000000; + + /* offset from top of codeDataAddrDdr where the code/data is actually placed, + the first codeDataOffsetDdr bytes are used for IPC in linux + */ + + addrBase = 0x70040000; + addrBaseFlash = 0x60100000; + + if(isSingleCore === true) { + codeDataAddr = addrBase; + codeDataAddrFlash = addrBaseFlash; + } + else { + if(args.project.cpu == "r5fss0-0") { + codeDataAddr = addrBase + codeDataSize*0; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*0; + } + if(args.project.cpu == "r5fss0-1") { + codeDataAddr = addrBase + codeDataSize*1; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*1; + } + if(args.project.cpu == "r5fss1-0") { + codeDataAddr = addrBase + codeDataSize*2; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*2; + } + if(args.project.cpu == "r5fss1-1") { + codeDataAddr = addrBase + codeDataSize*3; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*3; + } + } + if(options && options.codeDataAddr) + codeDataAddr = options.codeDataAddr; + if(options && options.codeDataSize) + codeDataSize = options.codeDataSize; + if(options && options.codeDataAddrFlash) + codeDataAddrFlash = options.codeDataAddrFlash; + if(options && options.codeDataSizeFlash) + codeDataSizeFlash = options.codeDataSizeFlash; +%%} + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=`stackSize` +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=`heapSize` +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is enabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = `irqStackSize`; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = `fiqStackSize`; +__SVC_STACK_SIZE = `svcStackSize`; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = `abortStackSize`; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = `undefinedStackSize`; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > OCRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + % if(useFlash) { + } > FLASH + % } else { + } > OCRAM + % } + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + + .data: {} palign(8) /* This is where initialized globals and static go */ + } > OCRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > OCRAM + + % if(args.isInstrumentation) { + GROUP { + __llvm_prf_cnts: {} align(8) + RUN_START(__start___llvm_prf_cnts) + RUN_END(__stop___llvm_prf_cnts) + } > OCRAM + + % } + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > OCRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + % if(useFlash) { + } > FLASH + % } else { + } > OCRAM + % } + + % if (isIcssPktBufEnable) { + /* Packet buffer memory used by ICCS */ + .bss.icss_emac_pktbuf_mem (NOLOAD): {} > ICSS_PKT_BUF_MEM + % } + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* this is used only when Secure IPC is enabled */ + .bss.sipc_hsm_queue_mem (NOLOAD) : {} > MAILBOX_HSM + .bss.sipc_r5f_queue_mem (NOLOAD) : {} > MAILBOX_R5F +} + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB : ORIGIN = 0x00080000 , LENGTH = 0x00008000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + OCRAM : ORIGIN = 0x`codeDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSize.toString(16).toUpperCase()` + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x`codeDataAddrFlash.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSizeFlash.toString(16).toUpperCase()` + + + % if (isIcssPktBufEnable) { + /* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */ + ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000 + + % } + /* shared memories that are used by RTOS/NORTOS cores */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x00004000 + LOG_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x00004000 + /* MSS mailbox memory is used as shared memory, we dont use bottom 32*12 bytes, since its used as SW queue by ipc_notify */ + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x`ipcShmAddrBase.toString(16).toUpperCase()`, LENGTH = 0x3E80 + MAILBOX_HSM: ORIGIN = 0x44000000 , LENGTH = 0x000003CE + MAILBOX_R5F: ORIGIN = 0x44000400 , LENGTH = 0x000003CE + } diff --git a/.project/templates/am263x/common/pru/hexpru.cmd.xdt b/.project/templates/am263x/common/pru/hexpru.cmd.xdt new file mode 100644 index 0000000..7115335 --- /dev/null +++ b/.project/templates/am263x/common/pru/hexpru.cmd.xdt @@ -0,0 +1,3 @@ +-b +-map=pru_project.map +SECTIONS {.text} diff --git a/.project/templates/am263x/common/pru/linker_pru0.cmd.xdt b/.project/templates/am263x/common/pru/linker_pru0.cmd.xdt new file mode 100644 index 0000000..c90676e --- /dev/null +++ b/.project/templates/am263x/common/pru/linker_pru0.cmd.xdt @@ -0,0 +1,67 @@ +/* + * AM263x_PRU0.cmd + * + * Example Linker command file for linking programs built with the TI-PRU-CGT + * on AM263x PRU0 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 12 KB PRU Instruction RAM */ + PRU_IMEM : org = 0x00000000 len = 0x00003000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 0 */ + PRU0_DMEM_0 : org = 0x00000000 len = 0x00002000 + /* 8 KB PRU Data RAM 1 */ + PRU0_DMEM_1 : org = 0x00002000 len = 0x00002000 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 32 KB Shared general purpose memory RAM with ECC, shared between PRU0 and PRU1 */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00008000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > PRU_IMEM, PAGE 0 + .bss > PRU0_DMEM_0, PAGE 1 + .stack > PRU0_DMEM_0, PAGE 1 +} diff --git a/.project/templates/am263x/common/pru/linker_pru1.cmd.xdt b/.project/templates/am263x/common/pru/linker_pru1.cmd.xdt new file mode 100644 index 0000000..caea8fb --- /dev/null +++ b/.project/templates/am263x/common/pru/linker_pru1.cmd.xdt @@ -0,0 +1,67 @@ +/* + * AM263x_PRU1.cmd + * + * Example Linker command file for linking programs built with the C compiler + * on AM263x PRU1 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 12 KB PRU Instruction RAM */ + PRU_IMEM : org = 0x00000000 len = 0x00003000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 1 */ + PRU1_DMEM_1 : org = 0x00000000 len = 0x00002000 + /* 8 KB PRU Data RAM 0 */ + PRU1_DMEM_0 : org = 0x00002000 len = 0x00002000 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 32 KB Shared general purpose memory RAM with ECC, shared between PRU0 and PRU1 */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00008000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > PRU_IMEM, PAGE 0 + .bss > PRU1_DMEM_0, PAGE 1 + .stack > PRU1_DMEM_0, PAGE 1 +} \ No newline at end of file diff --git a/.project/templates/am263x/freertos/FreeRTOSConfig.h.xdt b/.project/templates/am263x/freertos/FreeRTOSConfig.h.xdt new file mode 100644 index 0000000..5f05d76 --- /dev/null +++ b/.project/templates/am263x/freertos/FreeRTOSConfig.h.xdt @@ -0,0 +1,179 @@ +%%{ + let cpu = args.project.cpu; +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef TI_FREERTOS_CONFIG_H +#define TI_FREERTOS_CONFIG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE + * FreeRTOS REFERENCE MANUAL. + *----------------------------------------------------------*/ + +/* Keep below as 1 if the most optimized task switching latency is needed. + * This disables tracing, logging, assert and other error checks. + * So unless every last cycle of task switching is important leave this as 0. + * + * This is not a FreeRTOS defined config and is defined by TI to quickly switch + * between optimized and not-so-optimized config + */ +#define configOPTIMIZE_FOR_LATENCY (0) + +#define configUSE_PREEMPTION (1) +#define configUSE_PORT_OPTIMISED_TASK_SELECTION (`(cpu === "r5f") ? 0 : 1`) +#define configUSE_TICKLESS_IDLE (0) +#define configUSE_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationIdleHook(void) as the hook function */ +#define configUSE_MALLOC_FAILED_HOOK (0) +#define configUSE_DAEMON_TASK_STARTUP_HOOK (0) +#define configUSE_TICK_HOOK (0) +#define configCPU_CLOCK_HZ (0) /* NOT USED in TI ports */ +#define configSYSTICK_CLOCK_HZ (0) /* NOT USED in TI ports */ +#define configTICK_RATE_HZ (1000) +#define configMAX_PRIORITIES (32) +#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */ +#define configMAX_TASK_NAME_LEN (32) +#define configUSE_TRACE_FACILITY (1) +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configUSE_STATS_FORMATTING_FUNCTIONS (1) +#else +#define configUSE_STATS_FORMATTING_FUNCTIONS (0) +#endif +#define configUSE_16_BIT_TICKS (0) +#define configIDLE_SHOULD_YIELD (1) +#define configUSE_TASK_NOTIFICATIONS (1) +#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1) +#define configUSE_MUTEXES (1) +#define configUSE_RECURSIVE_MUTEXES (1) +#define configUSE_COUNTING_SEMAPHORES (1) +#define configUSE_ALTERNATIVE_API (0) + +/* when = 1, Need to provied below, + * void vApplicationStackOverflowHook( TaskHandle_t xTask, + * char *pcTaskName ); + */ +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configCHECK_FOR_STACK_OVERFLOW (1) +#else +#define configCHECK_FOR_STACK_OVERFLOW (0) +#endif +#define configQUEUE_REGISTRY_SIZE (32) +#define configUSE_QUEUE_SETS (0) +#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */ +#define configUSE_NEWLIB_REENTRANT (0) +#define configENABLE_BACKWARD_COMPATIBILITY (1) +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4) +#define configSTACK_DEPTH_TYPE UBaseType_t +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below, + * + * void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, + * StackType_t **ppxTimerTaskStackBuffer, + * uint32_t *pulTimerTaskStackSize ); + * + * void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, + * StackType_t **ppxIdleTaskStackBuffer, + * uint32_t *pulIdleTaskStackSize ); + */ +#define configSUPPORT_DYNAMIC_ALLOCATION (1) +#define configTOTAL_HEAP_SIZE (4*1024) /* not used when heap_3.c is the selected heap */ +#define configAPPLICATION_ALLOCATED_HEAP (0) + +/* run-time stats config */ +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configGENERATE_RUN_TIME_STATS (1) +#else +#define configGENERATE_RUN_TIME_STATS (0) +#endif +void vPortConfigTimerForRunTimeStats(); +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats() +uint32_t uiPortGetRunTimeCounterValue(); +#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue() + +/* co-routine related config */ +#define configUSE_CO_ROUTINES (0) +#define configMAX_CO_ROUTINE_PRIORITIES (0) + +/* timer related config */ +#define configUSE_TIMERS (1) +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH (16) +#define configTIMER_TASK_STACK_DEPTH (256) + +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U) +#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY) +#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY) + +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configASSERT(x) DebugP_assert( (uint32_t)(x)) +#endif + +/* MPU aware FreeRTOS, not supported as TI */ +#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0) +#define configTOTAL_MPU_REGIONS (0) +#undef configTEX_S_C_B_FLASH +#undef configTEX_S_C_B_SRAM +#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0) + +/* defines need for FreeRTOS+POSIX*/ +#define configUSE_POSIX_ERRNO (1) +#define configUSE_APPLICATION_TASK_TAG (1) + +/* include specific functions */ +#define INCLUDE_vTaskDelete (1) +#define INCLUDE_vTaskDelay (1) +#define INCLUDE_vTaskSuspend (1) +#define INCLUDE_xTimerDelete (1) +#define INCLUDE_vSemaphoreDelete (1) +#define INCLUDE_xTimerPendFunctionCall (1) +#define INCLUDE_xTaskGetIdleTaskHandle (1) + +#ifdef __cplusplus +} +#endif + +#endif /* TI_FREERTOS_CONFIG_H */ diff --git a/.project/templates/am263x/freertos/main_freertos.c.xdt b/.project/templates/am263x/freertos/main_freertos.c.xdt new file mode 100644 index 0000000..c3face0 --- /dev/null +++ b/.project/templates/am263x/freertos/main_freertos.c.xdt @@ -0,0 +1,110 @@ +%%{ + let options = args.options; + let stackSize = 16*1024; + let taskPri = "configMAX_PRIORITIES-1" + let entryFunction = "example_main"; + + if(options && options.entryFunction) + entryFunction = options.entryFunction; + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.taskPri) + taskPri = options.taskPri; + if(options.license == "ti_commercial") + license = `/* + * TIFS-MCU Source File + * + * Example main.c + * + * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/ + * ALL RIGHTS RESERVED + */ +` + + else + license = `/* + * Copyright (C) 2018-2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +` +%%} +`license` +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (`taskPri`) + +#define MAIN_TASK_SIZE (`stackSize`U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void `entryFunction`(void *args); + +void freertos_main(void *args) +{ + `entryFunction`(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/.project/templates/am263x/gpio/board_gpio.c.xdt b/.project/templates/am263x/gpio/board_gpio.c.xdt new file mode 100644 index 0000000..b283522 --- /dev/null +++ b/.project/templates/am263x/gpio/board_gpio.c.xdt @@ -0,0 +1,77 @@ +%%{ + let options = args.options; + + exampleType = "input_interrupt"; + if(options && options.exampleType) + exampleType = options.exampleType; + +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "ti_drivers_config.h" + +/* + * Board info + */ +% if ( exampleType == "input_interrupt" ) { +/* This is based on DMSC board config and core */ +%if(args.project.board == "am263x-lp") { +#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_GPIO_INTRXBAR_OUT_14) +#define BOARD_BUTTON_GPIO_SWITCH_NUM (4) +%} +%else { +#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_GPIO_INTRXBAR_OUT_14) +#define BOARD_BUTTON_GPIO_SWITCH_NUM (1) +%} + +void Board_gpioInit(void) +{ +} + +void Board_gpioDeinit(void) +{ +} + +uint32_t Board_getGpioButtonIntrNum(void) +{ + return (BOARD_BUTTON_GPIO_INTR_NUM); +} + +uint32_t Board_getGpioButtonSwitchNum(void) +{ + return (BOARD_BUTTON_GPIO_SWITCH_NUM); +} +% } diff --git a/.project/templates/am263x/i2c/board_i2c.c.xdt b/.project/templates/am263x/i2c/board_i2c.c.xdt new file mode 100644 index 0000000..12ec484 --- /dev/null +++ b/.project/templates/am263x/i2c/board_i2c.c.xdt @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_board_open_close.h" + +/* + * Board info + */ +uint32_t Board_getnumLedPerGroup(void) +{ + uint32_t ledCount; + const LED_Attrs *attrs; + + attrs = LED_getAttrs(CONFIG_LED0); + DebugP_assert(NULL != attrs); + /* All LEDs are connected, so return + * the driver atrributes value of 8 */ + ledCount = attrs->numLedPerGroup; + + return (ledCount); +} diff --git a/.project/templates/am263x/nortos/main_nortos.c.xdt b/.project/templates/am263x/nortos/main_nortos.c.xdt new file mode 100644 index 0000000..7983ac9 --- /dev/null +++ b/.project/templates/am263x/nortos/main_nortos.c.xdt @@ -0,0 +1,71 @@ +%%{ + let options = args.options; + + entryFunction = "example_main"; + + if(options && options.entryFunction) + entryFunction = options.entryFunction; + if(options.license == "ti_commercial") + license = `/* + * TIFS-MCU Source File + * + * Example main.c + * + * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/ + * ALL RIGHTS RESERVED + */ +` + + else + license = `/* + * Copyright (C) 2018-2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +` +%%} +`license` +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" + +void `entryFunction`(void *args); + +int main(void) +{ + System_init(); + Board_init(); + + `entryFunction`(NULL); + + Board_deinit(); + System_deinit(); + + return 0; +} diff --git a/.project/templates/am64x/common/linker_a53.cmd.xdt b/.project/templates/am64x/common/linker_a53.cmd.xdt new file mode 100644 index 0000000..6ae52c0 --- /dev/null +++ b/.project/templates/am64x/common/linker_a53.cmd.xdt @@ -0,0 +1,105 @@ +%%{ + let options = args.options; + + let stackSize = 0x10000; + let heapSize = 0x20000; + + let isSingleCore = true; + let useDdr = true; + let addrBaseDdr = 0x80000000; + let codeDataSizeDdr = 0x1000000; + + /* if no options given use defaults */ + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.heapSize) + heapSize = options.heapSize; + + if(isSingleCore == true) { + codeDataAddrDdr = addrBaseDdr; + codeDataSizeDdr = 0x1000000 * 2; + } + else { + if(args.project.cpu == "a53ss0-0") + { + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0; + } + if(args.project.cpu == "a53ss0-1") + { + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1; + } + } + + if(options && options.addrBaseDdr) + addrBaseDdr = options.addrBaseDdr; + if(options && options.codeDataSizeDdr) + codeDataSizeDdr = options.codeDataSizeDdr; + +%%} + +ENTRY(_c_int00) + +__TI_STACK_SIZE = `stackSize`; +__TI_HEAP_SIZE = `heapSize`; + +MEMORY +{ + % if(useDdr) { + DDR : ORIGIN = 0x`(codeDataAddrDdr).toString(16).toUpperCase()`, LENGTH = 0x`(codeDataSizeDdr).toString(16).toUpperCase()` + % } + + /* shared memory segments */ + /* On A53, + * - make sure there is a MMU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} + +SECTIONS { + + .vecs : {} > DDR + .text : {} > DDR + .rodata : {} > DDR + + .data : ALIGN (8) { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + *(.data) + *(.data*) + . = ALIGN (8); + __data_end__ = .; + } > DDR + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM + + .bss : { + __bss_start__ = .; + *(.bss) + *(.bss.*) + . = ALIGN (8); + *(COMMON) + __bss_end__ = .; + . = ALIGN (8); + } > DDR + + .heap (NOLOAD) : { + __heap_start__ = .; + KEEP(*(.heap)) + . = . + __TI_HEAP_SIZE; + __heap_end__ = .; + } > DDR + + .stack (NOLOAD) : ALIGN(16) { + __TI_STACK_BASE = .; + KEEP(*(.stack)) + . = . + __TI_STACK_SIZE; + } > DDR + +} \ No newline at end of file diff --git a/.project/templates/am64x/common/linker_a53_smp.cmd.xdt b/.project/templates/am64x/common/linker_a53_smp.cmd.xdt new file mode 100644 index 0000000..8bbfed1 --- /dev/null +++ b/.project/templates/am64x/common/linker_a53_smp.cmd.xdt @@ -0,0 +1,108 @@ +%%{ + let options = args.options; + + let stackSize = 0x10000; + let heapSize = 0x20000; + + let isSingleCore = true; + let useDdr = true; + let addrBaseDdr = 0x80000000; + let codeDataSizeDdr = 0x1000000; + + /* if no options given use defaults */ + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.heapSize) + heapSize = options.heapSize; + + if(isSingleCore == true) { + codeDataAddrDdr = addrBaseDdr; + codeDataSizeDdr = 0x1000000 * 2; + } + else { + if(args.project.cpu == "a53ss0-0") + { + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0; + } + if(args.project.cpu == "a53ss0-1") + { + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1; + } + } + + if(options && options.addrBaseDdr) + addrBaseDdr = options.addrBaseDdr; + if(options && options.codeDataSizeDdr) + codeDataSizeDdr = options.codeDataSizeDdr; + +%%} + +ENTRY(_c_int00) + +__TI_STACK_SIZE = `stackSize`; +__TI_HEAP_SIZE = `heapSize`; + +MEMORY +{ + % if(useDdr) { + DDR : ORIGIN = 0x`(codeDataAddrDdr).toString(16).toUpperCase()`, LENGTH = 0x`(codeDataSizeDdr).toString(16).toUpperCase()` + % } + + /* shared memory segments */ + /* On A53, + * - make sure there is a MMU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} + +SECTIONS { + + .vecs : {} > DDR + .text : {} > DDR + .rodata : {} > DDR + + .data : ALIGN (8) { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + *(.data) + *(.data*) + . = ALIGN (8); + __data_end__ = .; + } > DDR + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM + + .bss : { + __bss_start__ = .; + *(.bss) + *(.bss.*) + . = ALIGN (8); + *(COMMON) + __bss_end__ = .; + . = ALIGN (8); + } > DDR + + .heap (NOLOAD) : { + __heap_start__ = .; + KEEP(*(.heap)) + . = . + __TI_HEAP_SIZE; + __heap_end__ = .; + } > DDR + + .stack (NOLOAD) : ALIGN(16) { + __TI_STACK_BASE = .; + KEEP(*(.stack)) + . = . + __TI_STACK_SIZE; + __TI_STACK_BASE1 = .; + KEEP(*(.stack)) + . = . + __TI_STACK_SIZE; + } > DDR + +} \ No newline at end of file diff --git a/.project/templates/am64x/common/linker_m4f.cmd.xdt b/.project/templates/am64x/common/linker_m4f.cmd.xdt new file mode 100644 index 0000000..1d0fd9a --- /dev/null +++ b/.project/templates/am64x/common/linker_m4f.cmd.xdt @@ -0,0 +1,95 @@ +%%{ + let options = args.options; + + let stackSize = 16*1024; + let heapSize = 32*1024; + + /* if no options given use defaults */ + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.heapSize) + heapSize = options.heapSize; +%%} + +/* make sure below retain is there in your linker command file, it keeps the vector table in the final binary */ +--retain="*(.vectors)" +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=`stackSize` +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=`heapSize` + + +SECTIONS +{ + /* This has the M4F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > M4F_VECS + .text: {} palign(8) > M4F_IRAM /* This is where code resides */ + + .bss: {} palign(8) > M4F_DRAM /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + + .data: {} palign(8) > M4F_DRAM /* This is where initialized globals and static go */ + .rodata: {} palign(8) > M4F_DRAM /* This is where const's go */ + .sysmem: {} palign(8) > M4F_IRAM /* This is where the malloc heap goes */ + .stack: {} palign(8) > M4F_IRAM /* This is where the main() stack goes */ + + % if(args.project.isLinuxInSystem === true) { + GROUP { + /* This is the resource table used by linux to know where the IPC "VRINGs" are located */ + .resource_table: {} palign(4096) + } > DDR_0 + + % } + /* Sections needed for C++ projects */ + .ARM.exidx: {} palign(8) > M4F_IRAM /* Needed for C++ exception handling */ + .init_array: {} palign(8) > M4F_IRAM /* Contains function pointers called before main */ + .fini_array: {} palign(8) > M4F_IRAM /* Contains function pointers called after main */ + + /* General purpose user shared memory */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > IPC_VRING_MEM +} + +MEMORY +{ + M4F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000200 + M4F_IRAM : ORIGIN = 0x00000200 , LENGTH = 0x0002FE00 + M4F_DRAM : ORIGIN = 0x00030000 , LENGTH = 0x00010000 + + % if(args.project.isLinuxInSystem === true) { + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with R5F's + */ + /* Resource table must be placed at the start of DDR_0 when M4 core is early booting with Linux */ + DDR_0 : ORIGIN = 0xA4100000 , LENGTH = 0x1000 + + % } + % if(args.project.isLinuxInSystem) { + USER_SHM_MEM : ORIGIN = 0xA5000000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0xA5000000 + 0x80, LENGTH = 0x00004000 - 0x80 + IPC_VRING_MEM : ORIGIN = 0xA5004000, LENGTH = 0x0000C000 + % } else { + /* shared memories that are used by all cores */ + /* On M4F, + * - By default MSMC RAM is not accessible to M4F, a RAT entry is needed to make it + * accessible on M4F + * - So make sure there is a RAT entry which has a 1:1 mapping from 0x70000000 to 0x70200000 + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + IPC_VRING_MEM: ORIGIN = 0x701D4000, LENGTH = 0x0000C000 + % } +} diff --git a/.project/templates/am64x/common/linker_r5f.cmd.xdt b/.project/templates/am64x/common/linker_r5f.cmd.xdt new file mode 100644 index 0000000..61f58e5 --- /dev/null +++ b/.project/templates/am64x/common/linker_r5f.cmd.xdt @@ -0,0 +1,362 @@ +%%{ + let options = args.options; + + let stackSize = 16*1024; + let heapSize = 32*1024; + /* with nested interrupts logic added, IRQ stack is only used minimally, instead + * SVC stack is used, hence IRQ stack size is less as compared to SVC stack + */ + let irqStackSize = 256; + let svcStackSize = 4*1024; + let fiqStackSize = 256; + let abortStackSize = 256; + let undefinedStackSize = 256; + let codeDataAddr = 0; + let codeDataSize = 0; + let nocacheDataSize = 0; + let codeDataAddrDdr = 0; + let codeDataSizeDdr = 0; + let codeDataAddrFlash = 0; + let codeDataSizeFlash = 0; + let nocacheDataAddr = 0; + let useDdr = false; + let usetcma = false; + let resourceTableSizeDdr = 0; + let useFlash = false; + let addrBase = 0; + let addrBaseDdr = 0; + let addrBaseFlash = 0; + let nocacheAddrBase = 0; + let isSingleCore = false; + /* Temp change till we support DDR - alloc all memory to single core + * as we don't plan to run code coverage for system project */ + if(args.isInstrumentation) + { + isSingleCore = true; + } + let isIcssPktBufEnable = false; + + if(options && options.isXip) + { + useFlash = true; + } + + /* if no options given use defaults */ + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.heapSize) + heapSize = options.heapSize; + if(options && options.irqStackSize) + irqStackSize = options.irqStackSize; + if(options && options.fiqStackSize) + fiqStackSize = options.fiqStackSize; + if(options && options.svcStackSize) + svcStackSize = options.svcStackSize; + if(options && options.abortStackSize) + abortStackSize = options.abortStackSize; + if(options && options.undefinedStackSize) + undefinedStackSize = options.undefinedStackSize; + if(options && options.isSingleCore) + isSingleCore = options.isSingleCore; + if(options && options.isIcssPktBufEnable) + isIcssPktBufEnable = options.isIcssPktBufEnable; + + if(isSingleCore === true) { + codeDataSize = 0x40000 * 4; + codeDataSizeFlash = 0x80000; + codeDataSizeDdr = 0x1000000 * 4; + nocacheDataSize = 0x8000; + resourceTableSizeDdr = 0x1000 * 4; + } + else { + codeDataSize = 0x40000; + codeDataSizeFlash = 0x80000; + codeDataSizeDdr = 0x1000000; + nocacheDataSize = 0x8000; + resourceTableSizeDdr = 0x1000; + } + + /* offset from top of codeDataAddrDdr where the code/data is actually placed, + the first codeDataOffsetDdr bytes are used for IPC in linux + */ + codeDataOffsetDdr = 0x100000; + + if(args.project.isLinuxInSystem === true) { + addrBase = 0x70080000; + addrBaseDdr = 0xA0000000; + addrBaseFlash = 0x60100000; + useDdr = true; + usetcma = true; + } else { + addrBase = 0x70080000; + addrBaseFlash = 0x60100000; + nocacheAddrBase = 0x70060000; + } + if(isSingleCore === true) { + codeDataAddr = addrBase; + codeDataAddrDdr = addrBaseDdr; + codeDataAddrFlash = addrBaseFlash; + nocacheDataAddr = nocacheAddrBase; + } + else { + if(args.project.cpu == "r5fss0-0") { + codeDataAddr = addrBase + codeDataSize*0; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*0; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*0; + } + if(args.project.cpu == "r5fss0-1") { + codeDataAddr = addrBase + codeDataSize*1; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*1; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*1; + } + if(args.project.cpu == "r5fss1-0") { + codeDataAddr = addrBase + codeDataSize*2; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*2; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*2; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*2; + } + if(args.project.cpu == "r5fss1-1") { + codeDataAddr = addrBase + codeDataSize*3; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*3; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*3; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*3; + } + } + if(options && options.codeDataAddr) + codeDataAddr = options.codeDataAddr; + if(options && options.codeDataSize) + codeDataSize = options.codeDataSize; + if(options && options.codeDataAddrFlash) + codeDataAddrFlash = options.codeDataAddrFlash; + if(options && options.codeDataSizeFlash) + codeDataSizeFlash = options.codeDataSizeFlash; +%%} + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=`stackSize` +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=`heapSize` +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = `irqStackSize`; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = `fiqStackSize`; +__SVC_STACK_SIZE = `svcStackSize`; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = `abortStackSize`; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = `undefinedStackSize`; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + % if(usetcma) { + } > R5F_TCMA + % } else { + } > MSRAM + % } + + % if(useFlash) { + GROUP { + .rodata.cfg: {} palign(8) /* This is to keep the MPU config, Cache config and other consts */ + } > MSRAM + % } + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + % if(useDdr) { + } > DDR_1 + % } else if(useFlash) { + } > FLASH + % } else { + } > MSRAM + % } + + % if (useDdr) { + GROUP { + /* This is the resource table used by linux to know where the IPC "VRINGs" are located */ + .resource_table: {} palign(4096) + } > DDR_0 + + % } + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + % if(useDdr) { + } > DDR_1 + % } else { + } > MSRAM + % } + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + % if(useDdr) { + } > DDR_1 + % } else { + } > MSRAM + % } + + % if(args.isInstrumentation) { + GROUP { + __llvm_prf_cnts: {} align(8) + RUN_START(__start___llvm_prf_cnts) + RUN_END(__stop___llvm_prf_cnts) + } > MSRAM + + % } + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + % if(useDdr) { + } > DDR_1 + % } else { + } > MSRAM + % } + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + % if(useDdr) { + } > DDR_1 + % } else if(useFlash) { + } > FLASH + % } else { + } > MSRAM + % } + + % if (isIcssPktBufEnable) { + /* Packet buffer memory used by ICCS */ + .bss.icss_emac_pktbuf_mem (NOLOAD): {} > ICSS_PKT_BUF_MEM + % } + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + % if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */ + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM + % } +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + % if (isIcssPktBufEnable) { + /* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */ + ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000 + + % } + % if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */ + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x`nocacheDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`nocacheDataSize.toString(16).toUpperCase()` + + % } + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x`codeDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSize.toString(16).toUpperCase()` + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x`codeDataAddrFlash.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSizeFlash.toString(16).toUpperCase()` + + % if(useDdr) { + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + /* Resource table must be placed at the start of DDR_0 when R5 cores are early booting with Linux */ + DDR_0 : ORIGIN = 0x`(codeDataAddrDdr+codeDataOffsetDdr).toString(16).toUpperCase()` , LENGTH = 0x`(resourceTableSizeDdr).toString(16).toUpperCase()` + DDR_1 : ORIGIN = 0x`(codeDataAddrDdr+codeDataOffsetDdr+resourceTableSizeDdr).toString(16).toUpperCase()` , LENGTH = 0x`(codeDataSizeDdr - codeDataOffsetDdr -resourceTableSizeDdr).toString(16).toUpperCase()` + + % } + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + % if(args.project.isLinuxInSystem) { + USER_SHM_MEM : ORIGIN = 0xA5000000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0xA5000000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0xA5004000, LENGTH = 0x0000C000 + % } else { + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 + % } + % if(args.project.isLinuxInSystem) { + LINUX_IPC_SHM_MEM : ORIGIN = 0x`codeDataAddrDdr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataOffsetDdr.toString(16).toUpperCase()` + % } +} diff --git a/.project/templates/am64x/common/linker_r5f_gcc.cmd.xdt b/.project/templates/am64x/common/linker_r5f_gcc.cmd.xdt new file mode 100644 index 0000000..e5f7d73 --- /dev/null +++ b/.project/templates/am64x/common/linker_r5f_gcc.cmd.xdt @@ -0,0 +1,396 @@ +%%{ + let options = args.options; + + let stackSize = 16*1024; + let heapSize = 32*1024; + /* with nested interrupts logic added, IRQ stack is only used minimally, instead + * SVC stack is used, hence IRQ stack size is less as compared to SVC stack + */ + let irqStackSize = 256; + let svcStackSize = 4*1024; + let fiqStackSize = 256; + let abortStackSize = 256; + let undefinedStackSize = 256; + let codeDataAddr = 0; + let codeDataSize = 0; + let nocacheDataSize = 0; + let codeDataAddrDdr = 0; + let codeDataSizeDdr = 0; + let codeDataAddrFlash = 0; + let codeDataSizeFlash = 0; + let nocacheDataAddr = 0; + let useDdr = false; + let useFlash = false; + let addrBase = 0; + let addrBaseDdr = 0; + let addrBaseFlash = 0; + let nocacheAddrBase = 0; + let isSingleCore = false; + /* Temp change till we support DDR - alloc all memory to single core + * as we don't plan to run code coverage for system project */ + if(args.isInstrumentation) + { + isSingleCore = true; + } + let isIcssPktBufEnable = false; + + if(options && options.isXip) + { + useFlash = true; + } + + /* if no options given use defaults */ + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.heapSize) + heapSize = options.heapSize; + if(options && options.irqStackSize) + irqStackSize = options.irqStackSize; + if(options && options.fiqStackSize) + fiqStackSize = options.fiqStackSize; + if(options && options.svcStackSize) + svcStackSize = options.svcStackSize; + if(options && options.abortStackSize) + abortStackSize = options.abortStackSize; + if(options && options.undefinedStackSize) + undefinedStackSize = options.undefinedStackSize; + if(options && options.isSingleCore) + isSingleCore = options.isSingleCore; + if(options && options.isIcssPktBufEnable) + isIcssPktBufEnable = options.isIcssPktBufEnable; + + if(isSingleCore === true) { + codeDataSize = 0x40000 * 4; + codeDataSizeFlash = 0x80000; + codeDataSizeDdr = 0x1000000 * 4; + nocacheDataSize = 0x8000; + } + else { + codeDataSize = 0x40000; + codeDataSizeFlash = 0x80000; + codeDataSizeDdr = 0x1000000; + nocacheDataSize = 0x8000; + } + + /* offset from top of codeDataAddrDdr where the code/data is actually placed, + the first codeDataOffsetDdr bytes are used for IPC in linux + */ + codeDataOffsetDdr = 0x100000; + + if(args.project.isLinuxInSystem === true) { + addrBase = 0x70080000; + addrBaseDdr = 0xA0000000; + addrBaseFlash = 0x60100000; + useDdr = true; + } else { + addrBase = 0x70080000; + addrBaseFlash = 0x60100000; + nocacheAddrBase = 0x70060000; + } + if(isSingleCore === true) { + codeDataAddr = addrBase; + codeDataAddrDdr = addrBaseDdr; + codeDataAddrFlash = addrBaseFlash; + nocacheDataAddr = nocacheAddrBase; + } + else { + if(args.project.cpu == "r5fss0-0") { + codeDataAddr = addrBase + codeDataSize*0; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*0; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*0; + } + if(args.project.cpu == "r5fss0-1") { + codeDataAddr = addrBase + codeDataSize*1; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*1; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*1; + } + if(args.project.cpu == "r5fss1-0") { + codeDataAddr = addrBase + codeDataSize*2; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*2; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*2; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*2; + } + if(args.project.cpu == "r5fss1-1") { + codeDataAddr = addrBase + codeDataSize*3; + codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*3; + codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*3; + nocacheDataAddr = nocacheAddrBase + nocacheDataSize*3; + } + } + if(options && options.codeDataAddr) + codeDataAddr = options.codeDataAddr; + if(options && options.codeDataSize) + codeDataSize = options.codeDataSize; + if(options && options.codeDataAddrFlash) + codeDataAddrFlash = options.codeDataAddrFlash; + if(options && options.codeDataSizeFlash) + codeDataSizeFlash = options.codeDataSizeFlash; +%%} + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +__TI_STACK_SIZE = 16384; +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +__TI_HEAP_SIZE = 32768; +ENTRY(_vectors) /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is disabled as of now + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is enabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = `irqStackSize`; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = `fiqStackSize`; +__SVC_STACK_SIZE = `svcStackSize`; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = `abortStackSize`; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = `undefinedStackSize`; /* This is the size of stack when R5 is in UNDEF mode */ + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + % if (isIcssPktBufEnable) { + /* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */ + ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000 + + % } + % if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */ + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x`nocacheDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`nocacheDataSize.toString(16).toUpperCase()` + + % } + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x`codeDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSize.toString(16).toUpperCase()` + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x`codeDataAddrFlash.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSizeFlash.toString(16).toUpperCase()` + + % if(useDdr) { + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + DDR : ORIGIN = 0x`(codeDataAddrDdr+codeDataOffsetDdr).toString(16).toUpperCase()` , LENGTH = 0x`(codeDataSizeDdr - codeDataOffsetDdr).toString(16).toUpperCase()` + + % } + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 + % if(args.project.isLinuxInSystem) { + LINUX_IPC_SHM_MEM : ORIGIN = 0x`codeDataAddrDdr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataOffsetDdr.toString(16).toUpperCase()` + % } +} + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors : ALIGN (8) {} > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + .text.hwi : ALIGN (8) {} > MSRAM + .text.cache : ALIGN (8) {} > MSRAM + .text.mpu : ALIGN (8) {} > MSRAM + .text.boot : ALIGN (8) {} > MSRAM + .text:abort : ALIGN (8) {} > MSRAM /* this helps in loading symbols when using XIP mode */ + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + % if(useDdr) { + .text : ALIGN (8) {} > DDR /* This is where code resides */ + .rodata : ALIGN (8) {} > DDR /* This is where const's go */ + % } else if(useFlash) { + .text : ALIGN (8) {} > FLASH /* This is where code resides */ + .rodata : ALIGN (8) {} > FLASH /* This is where const's go */ + % } else { + .text : ALIGN (8) {} > MSRAM /* This is where code resides */ + .rodata : ALIGN (8) {} > MSRAM /* This is where const's go */ + % } + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + % if(useDdr) { + /* This is the resource table used by linux to know where the IPC "VRINGs" are located */ + .resource_table : ALIGN (4096) {} > DDR + .data : ALIGN (8) {} > DDR /* This is where initialized globals and static go */ + % } else { + .data : ALIGN (8) {} > MSRAM /* This is where initialized globals and static go */ + % } + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + % if(useDdr) { + .bss : { + __bss_start__ = .; + __BSS_START = .; + *(.bss) + *(.bss.*) + . = ALIGN (8); + __BSS_END = .; + __bss_end__ = .; + . = ALIGN (8); + } > DDR + % } else { + .bss : { + __bss_start__ = .; + __BSS_START = .; + *(.bss) + *(.bss.*) + . = ALIGN (8); + __BSS_END = .; + __bss_end__ = .; + . = ALIGN (8); + } > MSRAM + % } + + /* This is where the stacks for different R5F modes go */ + % if(useDdr) { + .irqstack : ALIGN(16) { + __IRQ_STACK_START = .; + . = . + __IRQ_STACK_SIZE; + __IRQ_STACK_END = .; + . = ALIGN (8); + } > DDR + .fiqstack : ALIGN(16) { + __FIQ_STACK_START = .; + . = . + __FIQ_STACK_SIZE; + __FIQ_STACK_END = .; + } > DDR + .svcstack : ALIGN(16) { + __SVC_STACK_START = .; + . = . + __SVC_STACK_SIZE; + __SVC_STACK_END = .; + } > DDR + .abortstack : ALIGN(16) { + __ABORT_STACK_START = .; + . = . + __ABORT_STACK_SIZE; + __ABORT_STACK_END = .; + } > DDR + .undefinedstack : ALIGN(16) { + __UNDEFINED_STACK_START = .; + . = . + __UNDEFINED_STACK_SIZE; + __UNDEFINED_STACK_END = .; + } > DDR + + .heap (NOLOAD) : { + end = .; + KEEP(*(.heap)) + . = . + __TI_HEAP_SIZE; + } > DDR + + .stack (NOLOAD) : ALIGN(16) { + __TI_STACK_BASE = .; + KEEP(*(.stack)) + . = . + __TI_STACK_SIZE; + __STACK_END = .; + } > DDR + % } else { + .irqstack : ALIGN(16) { + __IRQ_STACK_START = .; + . = . + __IRQ_STACK_SIZE; + __IRQ_STACK_END = .; + . = ALIGN (8); + } > MSRAM + .fiqstack : ALIGN(16) { + __FIQ_STACK_START = .; + . = . + __FIQ_STACK_SIZE; + __FIQ_STACK_END = .; + } > MSRAM + .svcstack : ALIGN(16) { + __SVC_STACK_START = .; + . = . + __SVC_STACK_SIZE; + __SVC_STACK_END = .; + } > MSRAM + .abortstack : ALIGN(16) { + __ABORT_STACK_START = .; + . = . + __ABORT_STACK_SIZE; + __ABORT_STACK_END = .; + } > MSRAM + .undefinedstack : ALIGN(16) { + __UNDEFINED_STACK_START = .; + . = . + __UNDEFINED_STACK_SIZE; + __UNDEFINED_STACK_END = .; + } > MSRAM + + .heap (NOLOAD) : { + end = .; + KEEP(*(.heap)) + . = . + __TI_HEAP_SIZE; + } > MSRAM + + .stack (NOLOAD) : ALIGN(16) { + __TI_STACK_BASE = .; + KEEP(*(.stack)) + . = . + __TI_STACK_SIZE; + __STACK_END = .; + } > MSRAM + % } + + /* Sections needed for C++ projects */ + % if(useDdr) { + .ARM.exidx : ALIGN (8) {} > DDR /* Needed for C++ exception handling */ + .init_array : ALIGN (8) {} > DDR /* Contains function pointers called before main */ + .fini_array : ALIGN (8) {} > DDR /* Contains function pointers called after main */ + % } else if(useFlash) { + .ARM.exidx : ALIGN (8) {} > FLASH /* Needed for C++ exception handling */ + .init_array : ALIGN (8) {} > FLASH /* Contains function pointers called before main */ + .fini_array : ALIGN (8) {} > FLASH /* Contains function pointers called after main */ + % } else { + .ARM.exidx : ALIGN (8) {} > MSRAM /* Needed for C++ exception handling */ + .init_array : ALIGN (8) {} > MSRAM /* Contains function pointers called before main */ + .fini_array : ALIGN (8) {} > MSRAM /* Contains function pointers called after main */ + % } + + % if (isIcssPktBufEnable) { + /* Packet buffer memory used by ICCS */ + .bss.icss_emac_pktbuf_mem (NOLOAD) : { KEEP(*(.bss.icss_emac_pktbuf_mem)) } > ICSS_PKT_BUF_MEM + % } + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM + % if ( ! args.project.isLinuxInSystem) { /* This is not used when Linux is there */ + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : { KEEP(*(.bss.nocache)) } > NON_CACHE_MEM + % } +} diff --git a/.project/templates/am64x/common/pru/hexpru.cmd.xdt b/.project/templates/am64x/common/pru/hexpru.cmd.xdt new file mode 100644 index 0000000..7115335 --- /dev/null +++ b/.project/templates/am64x/common/pru/hexpru.cmd.xdt @@ -0,0 +1,3 @@ +-b +-map=pru_project.map +SECTIONS {.text} diff --git a/.project/templates/am64x/common/pru/linker_pru0.cmd.xdt b/.project/templates/am64x/common/pru/linker_pru0.cmd.xdt new file mode 100644 index 0000000..ffae676 --- /dev/null +++ b/.project/templates/am64x/common/pru/linker_pru0.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM64x_PRU0.cmd + * + * Example Linker command file for linking programs built with the TI-PRU-CGT + * on AM64x PRU0 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 12 KB PRU Instruction RAM */ + PRU_IMEM : org = 0x00000000 len = 0x00003000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve + * the second 4 KB for RTU0 and Tx_PRU0 */ + PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1, + * RTU1 and Tx_PRU1; do not use for any Slice0 cores */ + PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800 + TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800 + RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800 + TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > PRU_IMEM, PAGE 0 + .stack > PRU_IMEM, PAGE 0 + .bss > PRU0_DMEM_0, PAGE 1 + /* + .cio > PRU0_DMEM_0, PAGE 1 + .data > PRU0_DMEM_0, PAGE 1 + .switch > PRU0_DMEM_0, PAGE 1 + .sysmem > PRU0_DMEM_0, PAGE 1 + .cinit > PRU0_DMEM_0, PAGE 1 + .rodata > PRU0_DMEM_0, PAGE 1 + .rofardata > PRU0_DMEM_0, PAGE 1 + .farbss > PRU0_DMEM_0, PAGE 1 + .fardata > PRU0_DMEM_0, PAGE 1 + */ +} diff --git a/.project/templates/am64x/common/pru/linker_pru1.cmd.xdt b/.project/templates/am64x/common/pru/linker_pru1.cmd.xdt new file mode 100644 index 0000000..c4a16d3 --- /dev/null +++ b/.project/templates/am64x/common/pru/linker_pru1.cmd.xdt @@ -0,0 +1,88 @@ +/* + * AM64x_PRU1.cmd + * + * Example Linker command file for linking programs built with the C compiler + * on AM64x PRU1 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 12 KB PRU Instruction RAM */ + PRU_IMEM : org = 0x00000000 len = 0x00003000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve + * the second 4 KB for RTU1 and Tx_PRU1 */ + PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0, + * RTU0 and Tx_PRU0; do not use for any Slice1 cores */ + PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800 + TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800 + RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800 + TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > PRU_IMEM, PAGE 0 + .stack > PRU_IMEM, PAGE 1 + /* TODO: review if this should be PRU1_DMEM_1 */ + .bss > PRU1_DMEM_0, PAGE 1 + /* + .cio > PRU1_DMEM_0, PAGE 1 + .data > PRU1_DMEM_0, PAGE 1 + .switch > PRU1_DMEM_0, PAGE 1 + .sysmem > PRU1_DMEM_0, PAGE 1 + .cinit > PRU1_DMEM_0, PAGE 1 + .rodata > PRU1_DMEM_0, PAGE 1 + .rofardata > PRU1_DMEM_0, PAGE 1 + .farbss > PRU1_DMEM_0, PAGE 1 + .fardata > PRU1_DMEM_0, PAGE 1 + */ +} \ No newline at end of file diff --git a/.project/templates/am64x/common/pru/linker_rtu_pru0.cmd.xdt b/.project/templates/am64x/common/pru/linker_rtu_pru0.cmd.xdt new file mode 100644 index 0000000..351ab4a --- /dev/null +++ b/.project/templates/am64x/common/pru/linker_rtu_pru0.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM64x_RTU_PRU0.cmd + * + * Example Linker command file for linking programs built with the TI-PRU-CGT + * on AM64x RTU_PRU0 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 8 KB PRU Instruction RAM */ + RTU_PRU_IMEM : org = 0x00000000 len = 0x00002000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve + * the second 4 KB for RTU0 and Tx_PRU0 */ + PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1, + * RTU1 and Tx_PRU1; do not use for any Slice0 cores */ + PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800 + TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800 + RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800 + TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > RTU_PRU_IMEM, PAGE 0 + .stack > RTU_PRU_IMEM, PAGE 0 + .bss > RTU_PRU0_DMEM_0, PAGE 1 + /* + .cio > RTU_PRU0_DMEM_0, PAGE 1 + .data > RTU_PRU0_DMEM_0, PAGE 1 + .switch > RTU_PRU0_DMEM_0, PAGE 1 + .sysmem > RTU_PRU0_DMEM_0, PAGE 1 + .cinit > RTU_PRU0_DMEM_0, PAGE 1 + .rodata > RTU_PRU0_DMEM_0, PAGE 1 + .rofardata > RTU_PRU0_DMEM_0, PAGE 1 + .farbss > RTU_PRU0_DMEM_0, PAGE 1 + .fardata > RTU_PRU0_DMEM_0, PAGE 1 + */ +} \ No newline at end of file diff --git a/.project/templates/am64x/common/pru/linker_rtu_pru1.cmd.xdt b/.project/templates/am64x/common/pru/linker_rtu_pru1.cmd.xdt new file mode 100644 index 0000000..939150f --- /dev/null +++ b/.project/templates/am64x/common/pru/linker_rtu_pru1.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM64x_RTU_PRU1.cmd + * + * Example Linker command file for linking programs built with the C compiler + * on AM64x RTU_PRU1 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 8 KB PRU Instruction RAM */ + RTU_PRU_IMEM : org = 0x00000000 len = 0x00002000 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve + * the second 4 KB for RTU1 and Tx_PRU1 */ + PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0, + * RTU0 and Tx_PRU0; do not use for any Slice1 cores */ + PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800 + TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800 + RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800 + TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > RTU_PRU_IMEM, PAGE 0 + .stack > RTU_PRU_IMEM, PAGE 1 + .bss > RTU_PRU1_DMEM_0, PAGE 1 + /* + .cio > RTU_PRU1_DMEM_0, PAGE 1 + .data > RTU_PRU1_DMEM_0, PAGE 1 + .switch > RTU_PRU1_DMEM_0, PAGE 1 + .sysmem > RTU_PRU1_DMEM_0, PAGE 1 + .cinit > RTU_PRU1_DMEM_0, PAGE 1 + .rodata > RTU_PRU1_DMEM_0, PAGE 1 + .rofardata > RTU_PRU1_DMEM_0, PAGE 1 + .farbss > RTU_PRU1_DMEM_0, PAGE 1 + .fardata > RTU_PRU1_DMEM_0, PAGE 1 + */ +} \ No newline at end of file diff --git a/.project/templates/am64x/common/pru/linker_tx_pru0.cmd.xdt b/.project/templates/am64x/common/pru/linker_tx_pru0.cmd.xdt new file mode 100644 index 0000000..402e1cc --- /dev/null +++ b/.project/templates/am64x/common/pru/linker_tx_pru0.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM64x_TX_PRU0.cmd + * + * Example Linker command file for linking programs built with the TI-PRU-CGT + * on AM64x TX_PRU0 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 6 KB PRU Instruction RAM */ + TX_PRU_IMEM : org = 0x00000000 len = 0x00001800 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve + * the second 4 KB for RTU0 and Tx_PRU0 */ + PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1, + * RTU1 and Tx_PRU1; do not use for any Slice0 cores */ + PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800 + TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800 + RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800 + TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > TX_PRU_IMEM, PAGE 0 + .stack > TX_PRU_IMEM, PAGE 0 + .bss > TX_PRU0_DMEM_0, PAGE 1 + /* + .cio > TX_PRU0_DMEM_0, PAGE 1 + .data > TX_PRU0_DMEM_0, PAGE 1 + .switch > TX_PRU0_DMEM_0, PAGE 1 + .sysmem > TX_PRU0_DMEM_0, PAGE 1 + .cinit > TX_PRU0_DMEM_0, PAGE 1 + .rodata > TX_PRU0_DMEM_0, PAGE 1 + .rofardata > TX_PRU0_DMEM_0, PAGE 1 + .farbss > TX_PRU0_DMEM_0, PAGE 1 + .fardata > TX_PRU0_DMEM_0, PAGE 1 + */ +} diff --git a/.project/templates/am64x/common/pru/linker_tx_pru1.cmd.xdt b/.project/templates/am64x/common/pru/linker_tx_pru1.cmd.xdt new file mode 100644 index 0000000..a19715b --- /dev/null +++ b/.project/templates/am64x/common/pru/linker_tx_pru1.cmd.xdt @@ -0,0 +1,87 @@ +/* + * AM64x_TX_PRU1.cmd + * + * Example Linker command file for linking programs built with the C compiler + * on AM64x TX_PRU1 cores + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + /* 6 KB TX_PRU Instruction RAM */ + TX_PRU_IMEM : org = 0x00000000 len = 0x00001800 + + PAGE 1: + /* Data RAMs */ + /* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve + * the second 4 KB for RTU1 and Tx_PRU1 */ + PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000 + /* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0, + * RTU0 and Tx_PRU0; do not use for any Slice1 cores */ + PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000 + /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1 + * split equally between the corresponding RTU and Tx_PRU cores in + * each slice */ + RTU_PRU1_DMEM_1 : org = 0x00001000 len = 0x00000800 + TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800 + RTU_PRU1_DMEM_0 : org = 0x00003000 len = 0x00000800 + TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800 + + PAGE 2: + /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ + /* 64 KB PRU Shared RAM */ + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of Tx_PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + .text:_c_int00* > 0x0, PAGE 0 + + .text > TX_PRU_IMEM, PAGE 0 + .stack > TX_PRU_IMEM, PAGE 1 + .bss > TX_PRU1_DMEM_0, PAGE 1 + /* + .cio > TX_PRU1_DMEM_0, PAGE 1 + .data > TX_PRU1_DMEM_0, PAGE 1 + .switch > TX_PRU1_DMEM_0, PAGE 1 + .sysmem > TX_PRU1_DMEM_0, PAGE 1 + .cinit > TX_PRU1_DMEM_0, PAGE 1 + .rodata > TX_PRU1_DMEM_0, PAGE 1 + .rofardata > TX_PRU1_DMEM_0, PAGE 1 + .farbss > TX_PRU1_DMEM_0, PAGE 1 + .fardata > TX_PRU1_DMEM_0, PAGE 1 + */ +} \ No newline at end of file diff --git a/.project/templates/am64x/freertos/FreeRTOSConfig.h.xdt b/.project/templates/am64x/freertos/FreeRTOSConfig.h.xdt new file mode 100644 index 0000000..5cc1411 --- /dev/null +++ b/.project/templates/am64x/freertos/FreeRTOSConfig.h.xdt @@ -0,0 +1,180 @@ +%%{ + let cpu = args.project.cpu; +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef TI_FREERTOS_CONFIG_H +#define TI_FREERTOS_CONFIG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE + * FreeRTOS REFERENCE MANUAL. + *----------------------------------------------------------*/ + +/* Keep below as 1 if the most optimized task switching latency is needed. + * This disables tracing, logging, assert and other error checks. + * So unless every last cycle of task switching is important leave this as 0. + * + * This is not a FreeRTOS defined config and is defined by TI to quickly switch + * between optimized and not-so-optimized config + */ +#define configOPTIMIZE_FOR_LATENCY (0) + +#define configUSE_PREEMPTION (1) +#define configUSE_PORT_OPTIMISED_TASK_SELECTION (`(cpu === "r5f") ? 0 : 1`) +#define configUSE_TICKLESS_IDLE (0) +#define configUSE_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationIdleHook(void) as the hook function */ +#define configUSE_MALLOC_FAILED_HOOK (0) +#define configUSE_DAEMON_TASK_STARTUP_HOOK (0) +#define configUSE_TICK_HOOK (0) +#define configCPU_CLOCK_HZ (0) /* NOT USED in TI ports */ +#define configSYSTICK_CLOCK_HZ (0) /* NOT USED in TI ports */ +#define configTICK_RATE_HZ (1000) +#define configMAX_PRIORITIES (32) +#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */ +#define configMAX_TASK_NAME_LEN (32) +#define configUSE_TRACE_FACILITY (1) +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configUSE_STATS_FORMATTING_FUNCTIONS (1) +#else +#define configUSE_STATS_FORMATTING_FUNCTIONS (0) +#endif +#define configUSE_16_BIT_TICKS (0) +#define configIDLE_SHOULD_YIELD (1) +#define configUSE_TASK_NOTIFICATIONS (1) +#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1) +#define configUSE_MUTEXES (1) +#define configUSE_RECURSIVE_MUTEXES (1) +#define configUSE_COUNTING_SEMAPHORES (1) +#define configUSE_ALTERNATIVE_API (0) + +/* when = 1, Need to provied below, + * void vApplicationStackOverflowHook( TaskHandle_t xTask, + * char *pcTaskName ); + */ +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configCHECK_FOR_STACK_OVERFLOW (1) +#else +#define configCHECK_FOR_STACK_OVERFLOW (0) +#endif +#define configQUEUE_REGISTRY_SIZE (32) +#define configUSE_QUEUE_SETS (0) +#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */ +#define configUSE_NEWLIB_REENTRANT (0) +#define configENABLE_BACKWARD_COMPATIBILITY (1) +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4) +#define configSTACK_DEPTH_TYPE UBaseType_t +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below, + * + * void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, + * StackType_t **ppxTimerTaskStackBuffer, + * uint32_t *pulTimerTaskStackSize ); + * + * void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, + * StackType_t **ppxIdleTaskStackBuffer, + * uint32_t *pulIdleTaskStackSize ); + */ +#define configSUPPORT_DYNAMIC_ALLOCATION (1) +#define configTOTAL_HEAP_SIZE (4*1024) /* not used when heap_3.c is the selected heap */ +#define configAPPLICATION_ALLOCATED_HEAP (0) + +/* run-time stats config */ +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configGENERATE_RUN_TIME_STATS (1) +#else +#define configGENERATE_RUN_TIME_STATS (0) +#endif +void vPortConfigTimerForRunTimeStats(); +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats() +uint32_t uiPortGetRunTimeCounterValue(); +#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue() + +/* co-routine related config */ +#define configUSE_CO_ROUTINES (0) +#define configMAX_CO_ROUTINE_PRIORITIES (0) + +/* timer related config */ +#define configUSE_TIMERS (1) +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH (16) +#define configTIMER_TASK_STACK_DEPTH (256) + +/* used in M4F, not applicable in R5F, C66x, A53 */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U) +#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY) +#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY) + +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configASSERT(x) DebugP_assert( (uint32_t)(x)) +#endif + +/* MPU aware FreeRTOS, not supported as TI */ +#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0) +#define configTOTAL_MPU_REGIONS (0) +#undef configTEX_S_C_B_FLASH +#undef configTEX_S_C_B_SRAM +#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0) + +/* defines need for FreeRTOS+POSIX*/ +#define configUSE_POSIX_ERRNO (1) +#define configUSE_APPLICATION_TASK_TAG (1) + +/* include specific functions */ +#define INCLUDE_vTaskDelete (1) +#define INCLUDE_vTaskDelay (1) +#define INCLUDE_vTaskSuspend (1) +#define INCLUDE_xTimerDelete (1) +#define INCLUDE_vSemaphoreDelete (1) +#define INCLUDE_xTimerPendFunctionCall (1) +#define INCLUDE_xTaskGetIdleTaskHandle (1) + +#ifdef __cplusplus +} +#endif + +#endif /* TI_FREERTOS_CONFIG_H */ diff --git a/.project/templates/am64x/freertos/FreeRTOSConfig_smp.h.xdt b/.project/templates/am64x/freertos/FreeRTOSConfig_smp.h.xdt new file mode 100644 index 0000000..f01c94a --- /dev/null +++ b/.project/templates/am64x/freertos/FreeRTOSConfig_smp.h.xdt @@ -0,0 +1,184 @@ +%%{ + let cpu = args.project.cpu; +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef TI_FREERTOS_CONFIG_H +#define TI_FREERTOS_CONFIG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE + * FreeRTOS REFERENCE MANUAL. + *----------------------------------------------------------*/ + +/* Keep below as 1 if the most optimized task switching latency is needed. + * This disables tracing, logging, assert and other error checks. + * So unless every last cycle of task switching is important leave this as 0. + * + * This is not a FreeRTOS defined config and is defined by TI to quickly switch + * between optimized and not-so-optimized config + */ +#define configOPTIMIZE_FOR_LATENCY (0) + +#define configUSE_PREEMPTION (1) +#define configUSE_PORT_OPTIMISED_TASK_SELECTION (0) +#define configNUM_CORES (2) +#define configRUN_MULTIPLE_PRIORITIES (1) +#define configUSE_CORE_AFFINITY (1) +#define configUSE_TICKLESS_IDLE (0) +#define configUSE_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationIdleHook(void) as the hook function */ +#define configUSE_MINIMAL_IDLE_HOOK (1) /* when 1, make sure to implement void vApplicationMinimalIdleHook(void) as the hook function */ +#define configUSE_MALLOC_FAILED_HOOK (0) +#define configUSE_DAEMON_TASK_STARTUP_HOOK (0) +#define configUSE_TICK_HOOK (0) +#define configCPU_CLOCK_HZ (0) /* NOT USED in TI ports */ +#define configSYSTICK_CLOCK_HZ (0) /* NOT USED in TI ports */ +#define configTICK_RATE_HZ (1000) +#define configMAX_PRIORITIES (32) +#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */ +#define configMAX_TASK_NAME_LEN (32) +#define configUSE_TRACE_FACILITY (1) +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configUSE_STATS_FORMATTING_FUNCTIONS (1) +#else +#define configUSE_STATS_FORMATTING_FUNCTIONS (0) +#endif +#define configUSE_16_BIT_TICKS (0) +#define configIDLE_SHOULD_YIELD (1) +#define configUSE_TASK_NOTIFICATIONS (1) +#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1) +#define configUSE_MUTEXES (1) +#define configUSE_RECURSIVE_MUTEXES (1) +#define configUSE_COUNTING_SEMAPHORES (1) +#define configUSE_ALTERNATIVE_API (0) + +/* when = 1, Need to provied below, + * void vApplicationStackOverflowHook( TaskHandle_t xTask, + * char *pcTaskName ); + */ +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configCHECK_FOR_STACK_OVERFLOW (1) +#else +#define configCHECK_FOR_STACK_OVERFLOW (0) +#endif +#define configQUEUE_REGISTRY_SIZE (32) +#define configUSE_QUEUE_SETS (0) +#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */ +#define configUSE_NEWLIB_REENTRANT (0) +#define configENABLE_BACKWARD_COMPATIBILITY (1) +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4) +#define configSTACK_DEPTH_TYPE UBaseType_t +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below, + * + * void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, + * StackType_t **ppxTimerTaskStackBuffer, + * uint32_t *pulTimerTaskStackSize ); + * + * void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, + * StackType_t **ppxIdleTaskStackBuffer, + * uint32_t *pulIdleTaskStackSize ); + */ +#define configSUPPORT_DYNAMIC_ALLOCATION (1) +#define configTOTAL_HEAP_SIZE (0xF80000) /* not used when heap_3.c is the selected heap */ +#define configAPPLICATION_ALLOCATED_HEAP (0) + +/* run-time stats config */ +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configGENERATE_RUN_TIME_STATS (1) +#else +#define configGENERATE_RUN_TIME_STATS (0) +#endif +void vPortConfigTimerForRunTimeStats(); +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats() +uint32_t uiPortGetRunTimeCounterValue(); +#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue() + +/* co-routine related config */ +#define configUSE_CO_ROUTINES (0) +#define configMAX_CO_ROUTINE_PRIORITIES (0) + +/* timer related config */ +#define configUSE_TIMERS (1) +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH (16) +#define configTIMER_TASK_STACK_DEPTH (256) + +/* used in M4F, not applicable in R5F, C66x, A53 */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U) +#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY) +#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY) + +#if (configOPTIMIZE_FOR_LATENCY==0) +#define configASSERT(x) DebugP_assert( (uint32_t)(x)) +#endif + +/* MPU aware FreeRTOS, not supported as TI */ +#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0) +#define configTOTAL_MPU_REGIONS (0) +#undef configTEX_S_C_B_FLASH +#undef configTEX_S_C_B_SRAM +#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0) + +/* defines need for FreeRTOS+POSIX*/ +#define configUSE_POSIX_ERRNO (1) +#define configUSE_APPLICATION_TASK_TAG (1) + +/* include specific functions */ +#define INCLUDE_vTaskDelete (1) +#define INCLUDE_vTaskDelay (1) +#define INCLUDE_vTaskSuspend (1) +#define INCLUDE_xTimerDelete (1) +#define INCLUDE_vSemaphoreDelete (1) +#define INCLUDE_xTimerPendFunctionCall (1) +#define INCLUDE_xTaskGetIdleTaskHandle (1) + +#ifdef __cplusplus +} +#endif + +#endif /* TI_FREERTOS_CONFIG_H */ diff --git a/.project/templates/am64x/freertos/main_freertos.c.xdt b/.project/templates/am64x/freertos/main_freertos.c.xdt new file mode 100644 index 0000000..a87517c --- /dev/null +++ b/.project/templates/am64x/freertos/main_freertos.c.xdt @@ -0,0 +1,98 @@ +%%{ + let options = args.options; + let stackSize = 16*1024; + let taskPri = "configMAX_PRIORITIES-1" + let entryFunction = "example_main"; + + if(options && options.entryFunction) + entryFunction = options.entryFunction; + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.taskPri) + taskPri = options.taskPri; + +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (`taskPri`) + +#define MAIN_TASK_SIZE (`stackSize`U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void `entryFunction`(void *args); + +void freertos_main(void *args) +{ + `entryFunction`(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/.project/templates/am64x/freertos/main_freertos_smp.c.xdt b/.project/templates/am64x/freertos/main_freertos_smp.c.xdt new file mode 100644 index 0000000..dd05b43 --- /dev/null +++ b/.project/templates/am64x/freertos/main_freertos_smp.c.xdt @@ -0,0 +1,114 @@ +%%{ + let options = args.options; + let stackSize = 16*1024; + let taskPri = "configMAX_PRIORITIES-1" + let entryFunction = "example_main"; + + if(options && options.entryFunction) + entryFunction = options.entryFunction; + if(options && options.stackSize) + stackSize = options.stackSize; + if(options && options.taskPri) + taskPri = options.taskPri; + +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +extern volatile uint64_t ullPortSchedularRunning; + +#define MAIN_TASK_PRI (`taskPri`) + +#define MAIN_TASK_SIZE (`stackSize`U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void `entryFunction`(void *args); + +void frertos_main(void *args) +{ + `entryFunction`(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + if (0 == Armv8_getCoreId()) + { + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( frertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + vTaskCoreAffinitySet(gMainTask, 1); + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + } + else + { + while(ullPortSchedularRunning == 0) + { + ; + } + xPortStartScheduler(); + } + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/.project/templates/am64x/gpio/board_gpio.c.xdt b/.project/templates/am64x/gpio/board_gpio.c.xdt new file mode 100644 index 0000000..6ca99c1 --- /dev/null +++ b/.project/templates/am64x/gpio/board_gpio.c.xdt @@ -0,0 +1,186 @@ +%%{ + let options = args.options; + + exampleType = "input_interrupt"; + if(options && options.exampleType) + exampleType = options.exampleType; + +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +% if ( exampleType == "input_interrupt" ) { +#include +% } +#include "ti_drivers_config.h" + +/* + * Board info + */ +% if ( exampleType == "input_interrupt" ) { +/* This is based on DMSC board config and core */ +#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8) +#define BOARD_BUTTON_GPIO_SWITCH_NUM (5) + +/** \brief bank interrupt source index base */ +#define TISCI_BANK_SRC_IDX_BASE_GPIO0 (90U) +#define TISCI_BANK_SRC_IDX_BASE_GPIO1 (90U) +#define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (90U) + +static void Sciclient_gpioIrqSet(void); +static void Sciclient_gpioIrqRelease(void); + +void Board_gpioInit(void) +{ + Sciclient_gpioIrqSet(); +} + +void Board_gpioDeinit(void) +{ + Sciclient_gpioIrqRelease(); +} + +uint32_t Board_getGpioButtonIntrNum(void) +{ + return (BOARD_BUTTON_GPIO_INTR_NUM); +} + +uint32_t Board_getGpioButtonSwitchNum(void) +{ + return (BOARD_BUTTON_GPIO_SWITCH_NUM); +} + +static void Sciclient_gpioIrqSet(void) +{ + int32_t retVal; + struct tisci_msg_rm_irq_set_req rmIrqReq; + struct tisci_msg_rm_irq_set_resp rmIrqResp; + + /* For setting the IRQ for GPIO using sciclient APIs, we need to populate + * a structure, tisci_msg_rm_irq_set_req instantiated above. The definition + * of this struct and details regarding the struct members can be found in + * the tisci_rm_irq.h. + */ + /* Initialize all flags to zero since we'll be setting only a few */ + rmIrqReq.valid_params = 0U; + /* Our request has a destination id, so enable the flag for DST ID */ + rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID; + /* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */ + rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID; + /* This is not a global event */ + rmIrqReq.global_event = 0U; + /* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW. + * The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/. + * In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt, + * we need to choose the TISCI_DEV_GPIO1 + */ + rmIrqReq.src_id = TISCI_DEV_GPIO1; + /* This is the interrupt source index within the GPIO peripheral */ + rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN); + /* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core. + * For a different core, the corresponding TISCI device id has to be provided */ + rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0; + /* This is the output index of the interrupt router. This depends on the core and board configuration */ + rmIrqReq.dst_host_irq = Board_getGpioButtonIntrNum(); + /* Rest of the struct members are unused for GPIO interrupt */ + rmIrqReq.ia_id = 0U; + rmIrqReq.vint = 0U; + rmIrqReq.vint_status_bit_index = 0U; + rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST; + + /* To set the interrupt we now invoke the Sciclient_rmIrqSet function which + * will find out the route to configure the interrupt and request DMSC to + * grant the resource + */ + retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER); + if(0 != retVal) + { + DebugP_log("[Error] Sciclient event config failed!!!\r\n"); + DebugP_assert(FALSE); + } + + return; +} + +static void Sciclient_gpioIrqRelease(void) +{ + int32_t retVal; + struct tisci_msg_rm_irq_release_req rmIrqReq; + /* For releasing the IRQ for GPIO using sciclient APIs, we need to populate + * a structure, tisci_msg_rm_irq_release_req instantiated above. The definition + * of this struct and details regarding the struct members can be found in + * the tisci_rm_irq.h. These are similar to the struct members for the set request + * used above. + */ + /* Initialize all flags to zero since we'll be setting only a few */ + rmIrqReq.valid_params = 0U; + /* Our request has a destination id, so enable the flag for DST ID */ + rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID; + /* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */ + rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID; + /* This is not a global event */ + rmIrqReq.global_event = 0U; + /* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW. + * The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/. + * In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt, + * we need to choose the TISCI_DEV_GPIO1 + */ + rmIrqReq.src_id = TISCI_DEV_GPIO1; + /* This is the interrupt source index within the GPIO peripheral */ + rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN); + /* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core. + * For a different core, the corresponding TISCI device id has to be provided */ + rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0; + /* This is the output index of the interrupt router. This depends on the core and board configuration */ + rmIrqReq.dst_host_irq = Board_getGpioButtonIntrNum(); + /* Rest of the struct members are unused for GPIO interrupt */ + rmIrqReq.ia_id = 0U; + rmIrqReq.vint = 0U; + rmIrqReq.vint_status_bit_index = 0U; + rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST; + + /* To set the interrupt we now invoke the Sciclient_rmIrqRelease function which + * will find specifics about the route and request DMSC/SYSFW to relase/clear the interrupt + */ + retVal = Sciclient_rmIrqRelease(&rmIrqReq, SystemP_WAIT_FOREVER); + if(0 != retVal) + { + DebugP_log("[Error] Sciclient event reset failed!!!\r\n"); + DebugP_assert(FALSE); + } + + return; +} +% } diff --git a/.project/templates/am64x/i2c/board_i2c.c.xdt b/.project/templates/am64x/i2c/board_i2c.c.xdt new file mode 100644 index 0000000..2f927c7 --- /dev/null +++ b/.project/templates/am64x/i2c/board_i2c.c.xdt @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_board_open_close.h" + +/* + * Board info + */ +uint32_t Board_getnumLedPerGroup(void) +{ + uint32_t ledCount; + const LED_Attrs *attrs; + + attrs = LED_getAttrs(CONFIG_LED0); + DebugP_assert(NULL != attrs); + /* For AM243x-EVM all LEDs are connected, so return + * the driver atrributes value of 8 */ + ledCount = attrs->numLedPerGroup; + + return (ledCount); +} diff --git a/.project/templates/am64x/nortos/main_nortos.c.xdt b/.project/templates/am64x/nortos/main_nortos.c.xdt new file mode 100644 index 0000000..84b7af3 --- /dev/null +++ b/.project/templates/am64x/nortos/main_nortos.c.xdt @@ -0,0 +1,58 @@ +%%{ + let options = args.options; + + entryFunction = "example_main"; + + if(options && options.entryFunction) + entryFunction = options.entryFunction; +%%} +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" + +void `entryFunction`(void *args); + +int main(void) +{ + System_init(); + Board_init(); + + `entryFunction`(NULL); + + Board_deinit(); + System_deinit(); + + return 0; +} diff --git a/.project/templates/imports.mak.xdt b/.project/templates/imports.mak.xdt new file mode 100644 index 0000000..a6b730e --- /dev/null +++ b/.project/templates/imports.mak.xdt @@ -0,0 +1,66 @@ +%%{ + isDevelopmentMode = args.common.isDevelopmentMode(); + deviceName = args.utils.getProjectSpecDevice(args.device); +%%} + +DEVICE ?= am64x + +ifeq ($(OS),Windows_NT) + TOOLS_PATH?=C:/ti + CCS_PATH?=$(TOOLS_PATH)/ccs1210/ccs + CCS_ECLIPSE=$(CCS_PATH)/eclipse/eclipsec + CYGWIN_PATH?=$(CCS_PATH)/utils/cygwin + MKDIR=$(CYGWIN_PATH)/mkdir -p + RMDIR=$(CYGWIN_PATH)/rm -rf + RM=$(CYGWIN_PATH)/rm -f + COPY=$(CYGWIN_PATH)/cp + TOUCH=$(CYGWIN_PATH)/touch + PATHSEP=\\ + CHMOD=$(CYGWIN_PATH)/echo + SHELL=cmd.exe +% if((args.device == "am64x") || (isDevelopmentMode)) { + CGT_GCC_AARCH64_PATH=$(TOOLS_PATH)/gcc-arm-9.2-2019.12-mingw-w64-i686-aarch64-none-elf + CGT_GCC_ARM_PATH=$(TOOLS_PATH)/gcc-arm-none-eabi-7-2017-q4-major-win32 + CGT_GCC_ARMV7_PATH=$(CGT_GCC_ARM_PATH) +% } +else + UNAME_S := $(shell uname -s) + ifeq ($(UNAME_S),Linux) + export TOOLS_PATH?=$(HOME)/ti + export CCS_PATH?=$(TOOLS_PATH)/ccs1210/ccs + export CCS_ECLIPSE=$(CCS_PATH)/eclipse/eclipse + export MKDIR=mkdir -p + export RMDIR=rm -rf + export RM=rm -f + export COPY=cp + export TOUCH=touch + export PATHSEP=/ + export CHMOD=chmod +% if((args.device == "am64x") || (isDevelopmentMode)) { + CGT_GCC_AARCH64_PATH=$(TOOLS_PATH)/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf + CGT_GCC_ARM_PATH=$(TOOLS_PATH)/gcc-arm-none-eabi-7-2017-q4-major + CGT_GCC_ARMV7_PATH=$(CGT_GCC_ARM_PATH) +% } + endif +endif + +# Variable pointing to location of MCU+ SDK +export MCU_PLUS_SDK_PATH?=$(TOOLS_PATH)/mcu_plus_sdk_`args.device`_09_00_00_01 + +CGT_TI_PRU_PATH=$(TOOLS_PATH)/ti-cgt-pru_2.3.3 +CGT_TI_SMART_PLACEMENT_TOOL_PATH=$(TOOLS_PATH)/ti-cgt-armllvm_3.0.0.STS +CGT_TI_ARM_CLANG_PATH=$(CCS_PATH)/tools/compiler/ti-cgt-armllvm_2.1.2.LTS +ifeq ($(wildcard $(CGT_TI_ARM_CLANG_PATH)),) + CGT_TI_ARM_CLANG_PATH=$(TOOLS_PATH)/ti-cgt-armllvm_2.1.2.LTS +endif +% if((args.device == "am273x") || (args.device == "awr294x") || (isDevelopmentMode)) { +CGT_TI_C6000_PATH=$(CCS_PATH)/tools/compiler/ti-cgt-c6000_8.3.12 +DSPLIB_PATH=$(MCU_PLUS_SDK_PATH)/source/dsplib_c66x_3_4_0_0 +% } +CCS_NODE = $(CCS_PATH)/tools/node/node +SYSCFG_PATH ?= $(TOOLS_PATH)/sysconfig_1.14.0 +SYSCFG_CLI_PATH ?= $(SYSCFG_PATH) +SYSCFG_NODE = $(SYSCFG_PATH)/nodejs/node +SYSCFG_NWJS = $(SYSCFG_PATH)/nw/nw +SYSCFG_SDKPRODUCT=$(MOTOR_CONTROL_SDK_PATH)/.metadata/product.json +SYSCFG_MCUPLUSSDKPRODUCT=$(MCU_PLUS_SDK_PATH)/.metadata/product.json diff --git a/.project/templates/makefile_ccs_bootimage_gen.xdt b/.project/templates/makefile_ccs_bootimage_gen.xdt new file mode 100644 index 0000000..a632bb2 --- /dev/null +++ b/.project/templates/makefile_ccs_bootimage_gen.xdt @@ -0,0 +1,293 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +% if (["am243x", "am64x", "am263x", "am273x"].includes(args.project.device)) { +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak +% } + +STRIP=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.strip` +OBJCOPY=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.objcopy` +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +% if (args.project.isBootLoader) { +% if (["am243x", "am64x", "am263x", "am273x"].includes(args.project.device)) { +BOOTIMAGE_NAME_GP:=$(BOOTIMAGE_PATH)/$(OUTNAME).tiimage +BOOTIMAGE_NAME_HS:=`args.project.name`.$(PROFILE).hs.tiimage +BOOTIMAGE_NAME_HS_FS:=`args.project.name`.$(PROFILE).hs_fs.tiimage +ifeq ($(DEVICE_TYPE),HS) + BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_HS) +else + BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_GP) +endif +% } else { +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).tiimage +% } +BOOTIMAGE_BIN_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).bin +% } else { +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +% if (args.project.device == "awr294x") { +BOOTIMAGE_NAME_QSPI:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_qspi +% } +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp +% } + +% if (args.project.isBootLoader) { +# +# Generation of boot image which can be loaded by ROM Boot Loader (RBL) +# +% } else { +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +% } +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +% if (args.project.isBootLoader) { +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) +BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/rom_image_gen.py +SYSFW_PATH=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/soc/am64x_am243x +SYSFW_LOAD_ADDR=0x44000 +BOARDCFG_LOAD_ADDR=0x7B000 +% if (args.project.name.includes("linux")) { +% if (args.project.device == "am64x") { +BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am64x/boardcfg_blob_linux.bin +% } else if (args.project.device == "am243x") { +BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am243x/boardcfg_blob_linux.bin +% } +% } else { +% if (args.project.device == "am64x") { +BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am64x/boardcfg_blob.bin +% } else if (args.project.device == "am243x") { +BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am243x/boardcfg_blob.bin +% } +% } +% } +% if ((args.project.device == "am273x") || (args.project.device == "awr294x") || (args.project.device == "am263x")) { +ifeq ($(DEVICE_TYPE),HS) +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) +else +BOOTIMAGE_CERT_KEY=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_gpkey.pem +endif +BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_rom_image_gen.py +% } + +% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) { +SBL_RUN_ADDRESS=0x10200000 +% } else if (args.project.device == "am263x") { +SBL_RUN_ADDRESS=0x70002000 +% } else { +SBL_RUN_ADDRESS=0x70000000 +% } + +SBL_PREBUILT_PATH=$(MCU_PLUS_SDK_PATH)/tools/boot/sbl_prebuilt/`args.project.board` + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME) ... + $(OBJCOPY) --strip-sections -O binary $(OUTFILE) $(BOOTIMAGE_BIN_NAME) +% if (args.project.device == "awr294x") { +ifeq ($(DEVICE_TYPE),HS) +ifeq ($(DBG_ENABLED),no) + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug DBG_PUBLIC_ENABLE +endif +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT +endif +% } else if ((args.project.device == "am263x") || (args.project.device == "am273x")) { +ifeq ($(DEVICE_TYPE),HS) +ifeq ($(DEBUG_TIFS), yes) +ifeq ($(ENC_SBL_ENABLED),yes) + $(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) +endif +else +ifeq ($(ENC_SBL_ENABLED),yes) + $(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION) +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION) +endif +endif +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT +endif +% } else { +ifeq ($(DEVICE_TYPE),HS) + $(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --debug DBG_FULL_ENABLE --rom-image $(BOOTIMAGE_NAME) +else + $(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-fs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-fs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) + $(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_NAME) +endif + $(COPY) $(BOOTIMAGE_NAME) $(BOOTIMAGE_PATH)/tiboot3.bin +ifeq ($(DEVICE_TYPE),GP) + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! +endif +% } + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME) Done !!! + @echo . +endif +% } else { +% if (args.project.device == "am64x") { +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) { +BOOTIMAGE_CORE_ID_a53ss0-1 = 1 +% } +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am243x") { +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am263x") { +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_r5fss1-0 = 2 +BOOTIMAGE_CORE_ID_r5fss1-1 = 3 +SBL_RUN_ADDRESS=0x70002000 +SBL_DEV_ID=55 +% } +% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) { +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_c66ss0 = 2 +% if (args.project.device == "awr294x") { +BOOTIMAGE_CORE_ID_r4 = 3 +R4_RPRC_PATH = $(MCU_PLUS_SDK_PATH)/source/drivers/bootloader/soc/awr294x/xwr2xxx_radarss_metarprc.bin +% } +SBL_RUN_ADDRESS=0x10200000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am62x") { +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_a53ss0-1 = 1 +BOOTIMAGE_CORE_ID_a53ss1-0 = 2 +BOOTIMAGE_CORE_ID_a53ss1-1 = 3 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_m4fss0-0 = 5 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) { +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py +% } + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_`args.project.cpu`) \ +% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) { + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_a53ss0-1) \ +% } + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_`args.project.cpu`) \ +% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) { + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_a53ss0-1) \ +% } + +% if (args.project.device == "awr294x") { +MULTI_CORE_IMAGE_PARAMS_QSPI = $(MULTI_CORE_IMAGE_PARAMS) $(R4_RPRC_PATH)@$(BOOTIMAGE_CORE_ID_r4) + +% } +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x`args.flashAddr.toString(16)` -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +% if (args.project.device == "awr294x") { + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_QSPI) $(MULTI_CORE_IMAGE_PARAMS_QSPI) >> $(BOOTIMAGE_TEMP_OUT_FILE) +% } +% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) { +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +% } +% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) { +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif +% } + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) +% if (args.project.isLinuxFwGen) { + $(RM) $(PROFILE)/`args.linuxFwName` + $(STRIP) -o=$(PROFILE)/`args.linuxFwName` $(OUTFILE) +% } + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME) Done !!! + @echo . +% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) { +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +% } +endif +% } diff --git a/.project/templates/makefile_device_projectspec_top.xdt b/.project/templates/makefile_device_projectspec_top.xdt new file mode 100644 index 0000000..ad2537b --- /dev/null +++ b/.project/templates/makefile_device_projectspec_top.xdt @@ -0,0 +1,184 @@ +# +# Auto generated makefile +# + +% if (["am243x", "am64x"].includes(args.device)) { +export `args.sdkPath`?=$(abspath `args.relPath`) +include $(`args.sdkPath`)/imports.mak + +% } +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL = +# Various Example Projectspec Build Targets +% for (example of args.example_list) { +% if(!example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL +=`example.buildTarget`_build +% } +% } +# Various System Example Projectspec Build Targets +% for (example of args.system_example_list) { +% if(!example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL +=`example.buildTarget`_build +% } +% } + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL = +# Various Private Example Projectspec Build Targets +% for (example of args.example_list) { +% if(example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL +=`example.buildTarget`_build +% } +% } +# Various Private System Example Projectspec Build Targets +% for (example of args.system_example_list) { +% if(example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL +=`example.buildTarget`_build +% } +% } + +all: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL) + +all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL) + +% for (example of args.example_list) { +`example.buildTarget`_build: + $(MAKE) -C `example.relpath` -f makefile_projectspec all + +% } +% for (example of args.system_example_list) { +`example.buildTarget`_build: + $(MAKE) -C `example.relpath` -f makefile_projectspec all + +% } + + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL = +# Various Example Projectspec Clean Targets +% for (example of args.example_list) { +% if(!example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL +=`example.buildTarget`_clean +% } +% } +# Various System Example Projectspec Clean Targets +% for (example of args.system_example_list) { +% if(!example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL +=`example.buildTarget`_clean +% } +% } + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL = +# Various Private Example Projectspec Clean Targets +% for (example of args.example_list) { +% if(example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL +=`example.buildTarget`_clean +% } +% } +# Various Private System Example Projectspec Clean Targets +% for (example of args.system_example_list) { +% if(example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL +=`example.buildTarget`_clean +% } +% } + +clean: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL) + +clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL) + +% for (example of args.example_list) { +`example.buildTarget`_clean: + $(MAKE) -C `example.relpath` -f makefile_projectspec clean + +% } +% for (example of args.system_example_list) { +`example.buildTarget`_clean: + $(MAKE) -C `example.relpath` -f makefile_projectspec clean + +% } + + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL = +# Various Example Projectspec Export Targets +% for (example of args.example_list) { +% if(!example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL +=`example.buildTarget`_export +% } +% } +# Various System Example Projectspec Export Targets +% for (example of args.system_example_list) { +% if(!example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL +=`example.buildTarget`_export +% } +% } + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL = +# Various Private Example Projectspec Export Targets +% for (example of args.example_list) { +% if(example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL +=`example.buildTarget`_export +% } +% } +# Various Private System Example Projectspec Export Targets +% for (example of args.system_example_list) { +% if(example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL +=`example.buildTarget`_export +% } +% } + +export: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL) + +export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL) + +% for (example of args.example_list) { +`example.buildTarget`_export: + $(MAKE) -C `example.relpath` -f makefile_projectspec export + +% } +% for (example of args.system_example_list) { +`example.buildTarget`_export: + $(MAKE) -C `example.relpath` -f makefile_projectspec export + +% } + +% if (["am243x", "am64x"].includes(args.device)) { +# Import extra components into CCS workspace before creating a project +# Setup dependency separately so that it runs if one or all projects are built via the makefile +$(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL) $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL): import_extra_components + +# Import extra components based on the configured makefile variables. +# Same CCS workspace used by the examples is used here. +import_extra_components: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.common.core.initialize -ccs.productDiscoveryPath $(COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR) -ccs.productDiscoveryPath $(COM_TI_MCU_PLUS_SDK_AMXXX_INSTALL_DIR) +% } + +help: + @echo Notes, + @echo - Use -j to invoke parallel builds + @echo - Use PROFILE=Debug or PROFILE=Release [default] to build in Debug or Release profile + @echo . + @echo Overall build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile_projectspec.`device` help + @echo . + @echo $(MAKE) -s -f makefile_projectspec.`device` [export all clean] + @echo . + @echo export = export projectspec to CCS project in the folder ./ccs_projects/, + @echo export MUST be called once before 'all' or 'clean' + @echo all = build the previously exported projectspecs + @echo clean = clean the previously exported projectspecs + @echo . + @echo Example ProjectSpec build targets, + @echo ================================== +% for (example of args.example_list) { + @echo $(MAKE) -s -C `example.relpath` -f makefile_projectspec [export all clean] +% } + @echo . + @echo System Example ProjectSpec build targets, + @echo ========================================= +% for (example of args.system_example_list) { + @echo $(MAKE) -s -C `example.relpath` -f makefile_projectspec [export all clean] +% } + @echo . + +.PHONY: all all-private +.PHONY: clean clean-private +.PHONY: help diff --git a/.project/templates/makefile_device_top.xdt b/.project/templates/makefile_device_top.xdt new file mode 100644 index 0000000..d0ff246 --- /dev/null +++ b/.project/templates/makefile_device_top.xdt @@ -0,0 +1,289 @@ +%%{ + let component_target_list_string = []; + let component_target_private_list_string = []; + let component_target_prebuilt_list_string = []; + let component_target_clean_list_string = []; + let component_target_scrub_list_string = []; + let component_target_prebuilt_clean_list_string = []; + let component_target_prebuilt_scrub_list_string = []; + for (component of args.component_list) { + if(component.isSkipTopLevelBuild) { + component_target_private_list_string +=` \$(BUILD_COMBO_${component.name})` + component_target_clean_list_string +=` \$(BUILD_COMBO_CLEAN_${component.name})` + component_target_scrub_list_string +=` \$(BUILD_COMBO_SCRUB_${component.name})` + } + else if(component.isPrebuilt) { + component_target_prebuilt_list_string +=` \$(BUILD_COMBO_${component.name})` + component_target_prebuilt_clean_list_string +=` \$(BUILD_COMBO_CLEAN_${component.name})` + component_target_prebuilt_scrub_list_string +=` \$(BUILD_COMBO_SCRUB_${component.name})` + } + else { + component_target_list_string +=` \$(BUILD_COMBO_${component.name})` + component_target_clean_list_string +=` \$(BUILD_COMBO_CLEAN_${component.name})` + component_target_scrub_list_string +=` \$(BUILD_COMBO_SCRUB_${component.name})` + } + } +%%} +# +# Auto generated makefile +# + +all: + $(MAKE) -f makefile.`device` libs + $(MAKE) -f makefile.`device` examples + +clean: libs-clean examples-clean +scrub: libs-scrub examples-scrub + +help: + @echo Notes, + @echo - Use -j to invoke parallel builds + @echo - Use PROFILE=debug or PROFILE=release [default] to build in debug or release profile + @echo . + @echo Overall build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.`device` help + @echo . + @echo $(MAKE) -s -f makefile.`device` all + @echo $(MAKE) -s -f makefile.`device` clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.`device` scrub # delete's all tmp files and folders for all profiles + @echo . + @echo $(MAKE) -s -f makefile.`device` libs + @echo $(MAKE) -s -f makefile.`device` libs-clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.`device` libs-scrub # delete's all tmp files and folders for all profiles + @echo . + @echo $(MAKE) -s -f makefile.`device` examples + @echo $(MAKE) -s -f makefile.`device` examples-clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.`device` examples-scrub # delete's all tmp files and folders for all profiles + @echo . + @echo Library build targets, + @echo ====================== +% for (component of args.component_list) { + @echo $(MAKE) -s -f makefile.`device``component.buildTarget` +% } + @echo . + @echo Library clean targets, + @echo ====================== +% for (component of args.component_list) { + @echo $(MAKE) -s -f makefile.`device``component.buildTargetClean` +% } + @echo . + @echo Example build targets, + @echo ====================== +% for (example of args.example_list) { + @echo $(MAKE) -s -C `example.relpath` [all clean syscfg-gui syscfg] +% } + @echo . + @echo System Example build targets, + @echo ============================= +% for (example of args.system_example_list) { + @echo $(MAKE) -s -C `example.relpath` [all clean syscfg-gui syscfg] +% } + @echo . + +# Various Component Targets +% for (component of args.component_list) { +BUILD_COMBO_`component.name` =`component.buildTarget` +% } + +# Combine all Components +BUILD_COMBO_ALL =`component_target_list_string` + +# Combine all Pre-built Components +BUILD_COMBO_PREBUILT_ALL =`component_target_prebuilt_list_string` + +# Combine all Private Components +BUILD_COMBO_PRIVATE_ALL =`component_target_private_list_string` + +libs: $(BUILD_COMBO_ALL) + +libs-prebuilt: $(BUILD_COMBO_PREBUILT_ALL) + +libs-private: $(BUILD_COMBO_PRIVATE_ALL) + +% for (component of args.component_list) { +$(BUILD_COMBO_`component.name`): + $(MAKE) -C `component.relpath` -f makefile`component.tag`.`args.device`.$(subst `component.name`_,,$@) all + +% } + +# Various Component Clean Targets +% for (component of args.component_list) { +BUILD_COMBO_CLEAN_`component.name` =`component.buildTargetClean` +% } + +# Combine all Components Clean +BUILD_COMBO_CLEAN_ALL =`component_target_clean_list_string` + +# Combine all Pre-built Components Clean +BUILD_COMBO_PREBUILT_CLEAN_ALL =`component_target_prebuilt_clean_list_string` + +libs-clean: $(BUILD_COMBO_CLEAN_ALL) + +libs-prebuilt-clean: $(BUILD_COMBO_PREBUILT_CLEAN_ALL) + +% for (component of args.component_list) { +$(BUILD_COMBO_CLEAN_`component.name`): + $(MAKE) -C `component.relpath` -f makefile`component.tag`.`args.device`.$(subst `component.name`_,,$(subst _clean,,$@)) clean + +% } + +# Various Component Scrub Targets +% for (component of args.component_list) { +BUILD_COMBO_SCRUB_`component.name` =`component.buildTargetScrub`_scrub +% } + +# Combine all Components Scrub Targets +BUILD_COMBO_SCRUB_ALL =`component_target_scrub_list_string` + +# Combine all Pre-built Components Scrub Targets +BUILD_COMBO_PREBUILT_SCRUB_ALL =`component_target_prebuilt_scrub_list_string` + +libs-scrub: $(BUILD_COMBO_SCRUB_ALL) + +libs-prebuilt-scrub: $(BUILD_COMBO_PREBUILT_SCRUB_ALL) + +% for (component of args.component_list) { +$(BUILD_COMBO_SCRUB_`component.name`): + $(MAKE) -C `component.relpath` -f makefile`component.tag`.`args.device`.$(subst `component.name`_,,$(subst _scrub,,$@)) scrub + +% } + +BUILD_COMBO_EXAMPLE_ALL = +# Various Example Targets +% for (example of args.example_list) { +% if(!example.isSkipTopLevelBuild && !example.isBootLoader) { +BUILD_COMBO_EXAMPLE_ALL +=`example.buildTarget` +% } +% } +# Various System Example Targets +% for (example of args.system_example_list) { +% if(!example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_ALL +=`example.buildTarget` +% } +% } + +BUILD_COMBO_EXAMPLE_PRIVATE_ALL = +# Various Private Example Targets +% for (example of args.example_list) { +% if(example.isSkipTopLevelBuild && !example.isBootLoader) { +BUILD_COMBO_EXAMPLE_PRIVATE_ALL +=`example.buildTarget` +% } +% } +# Various Private System Example Targets +% for (example of args.system_example_list) { +% if(example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PRIVATE_ALL +=`example.buildTarget` +% } +% } + +examples: $(BUILD_COMBO_EXAMPLE_ALL) + +examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) + +% for (example of args.example_list) { +`example.buildTarget`: + $(MAKE) -C `example.relpath` -f makefile all + +% } +% for (example of args.system_example_list) { +`example.buildTarget`: + $(MAKE) -C `example.relpath` -f makefile all + +% } + +BUILD_COMBO_EXAMPLE_CLEAN_ALL = +# Various Example Clean Targets +% for (example of args.example_list) { +% if(!example.isSkipTopLevelBuild && !example.isBootLoader) { +BUILD_COMBO_EXAMPLE_CLEAN_ALL +=`example.buildTargetClean` +% } +% } +# Various System Example Clean Targets +% for (example of args.system_example_list) { +% if(!example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_CLEAN_ALL +=`example.buildTargetClean` +% } +% } + +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL = +# Various Private Example Targets +% for (example of args.example_list) { +% if(example.isSkipTopLevelBuild && !example.isBootLoader) { +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL +=`example.buildTargetClean` +% } +% } +# Various Private System Example Targets +% for (example of args.system_example_list) { +% if(example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL +=`example.buildTargetClean` +% } +% } + +examples-clean: $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) + +examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) + +% for (example of args.example_list) { +`example.buildTargetClean`: + $(MAKE) -C `example.relpath` -f makefile clean + +% } +% for (example of args.system_example_list) { +`example.buildTargetClean`: + $(MAKE) -C `example.relpath` -f makefile clean + +% } + +BUILD_COMBO_EXAMPLE_SCRUB_ALL = +# Various Example Scrub Targets +% for (example of args.example_list) { +% if(!example.isSkipTopLevelBuild && !example.isBootLoader) { +BUILD_COMBO_EXAMPLE_SCRUB_ALL +=`example.buildTargetScrub` +% } +% } +# Various System Example Scrub Targets +% for (example of args.system_example_list) { +% if(!example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_SCRUB_ALL +=`example.buildTargetScrub` +% } +% } + +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL = +# Various Private Example Targets +% for (example of args.example_list) { +% if(example.isSkipTopLevelBuild && !example.isBootLoader) { +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL +=`example.buildTargetScrub` +% } +% } +# Various Private System Example Targets +% for (example of args.system_example_list) { +% if(example.isSkipTopLevelBuild) { +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL +=`example.buildTargetScrub` +% } +% } + +examples-scrub: $(BUILD_COMBO_EXAMPLE_SCRUB_ALL) + +examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) + +% for (example of args.example_list) { +`example.buildTargetScrub`: + $(MAKE) -C `example.relpath` -f makefile scrub + +% } +% for (example of args.system_example_list) { +`example.buildTargetScrub`: + $(MAKE) -C `example.relpath` -f makefile scrub + +% } + +.PHONY: all clean scrub help +.PHONY: libs libs-clean libs-scrub +.PHONY: libs-private +.PHONY: libs-prebuilt libs-prebuilt-clean libs-prebuilt-scrub +.PHONY: examples examples-clean examples-scrub +.PHONY: examples-private examples-private-clean examples-private-scrub +.PHONY: $(BUILD_COMBO_ALL) $(BUILD_COMBO_CLEAN_ALL) $(BUILD_COMBO_SCRUB_ALL) +.PHONY: $(BUILD_COMBO_EXAMPLE_ALL) $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_SCRUB_ALL) +.PHONY: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) diff --git a/.project/templates/makefile_executable.xdt b/.project/templates/makefile_executable.xdt new file mode 100644 index 0000000..2e035b8 --- /dev/null +++ b/.project/templates/makefile_executable.xdt @@ -0,0 +1,710 @@ +# +# Auto generated makefile +# + +export `args.sdkPath`?=$(abspath `args.relPath`) +include $(`args.sdkPath`)/imports.mak +include $(`args.sdkPath`)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(`args.cgtOptions.path`) + +CC=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.cc` +LNK=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.lnk` +STRIP=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.strip` +OBJCOPY=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.objcopy` +% if ((args.isInstrumentationMode) && (args.cgtOptions.cov)) { +COV=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.cov` +PROFDATA=$(CG_TOOL_ROOT)/bin/`args.cgtOptions.profdata` +COVERAGE_PATH=$(abspath .) +% } +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=`args.project.name`.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +% if (args.project.isBootLoader) { +% if ((args.project.device == "am64x") || (args.project.device == "am243x") || (args.project.device == "am263x") || (args.project.device == "am273x")) { +BOOTIMAGE_NAME_GP:=`args.project.name`.$(PROFILE).tiimage +BOOTIMAGE_NAME_HS:=`args.project.name`.$(PROFILE).hs.tiimage +BOOTIMAGE_NAME_HS_FS:=`args.project.name`.$(PROFILE).hs_fs.tiimage +% } else { +BOOTIMAGE_NAME:=`args.project.name`.$(PROFILE).tiimage +% } +BOOTIMAGE_BIN_NAME:=`args.project.name`.$(PROFILE).bin + +% if ((args.project.device == "am64x") || (args.project.device == "am243x") || (args.project.device == "am263x") || (args.project.device == "am273x")) { +ifeq ($(DEVICE_TYPE),HS) + BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_HS) +else + BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_GP) +endif +% } +% } else { +BOOTIMAGE_NAME:=`args.project.name`.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=`args.project.name`.$(PROFILE).appimage_xip +% if (args.project.device == "awr294x") { +BOOTIMAGE_NAME_QSPI:=`args.project.name`.$(PROFILE).appimage_qspi +% } +BOOTIMAGE_NAME_SIGNED:=`args.project.name`.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=`args.project.name`.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=`args.project.name`.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=`args.project.name`.$(PROFILE).rprc_tmp +% if (((args.project.device == "am64x") || (args.project.device == "am243x")) && (!args.project.isPartOfSystemProject)) { +BOOTIMAGE_NAME_HS:=`args.project.name`.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=`args.project.name`.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif +% } +% } + +% let linker_option_prefix = ""; +% if (args.project.cgt == "ti-arm-clang") { +% linker_option_prefix = "-Wl,"; +% } +% let obj = {} +% obj = args.project.files; +% if(obj["common"] == undefined) { +% obj.common = Array() +%} +% if (args.project.syscfgfile) { +% obj.common.push("ti_drivers_config.c", "ti_drivers_open_close.c", "ti_board_config.c", "ti_board_open_close.c", "ti_dpl_config.c", "ti_pinmux_config.c", "ti_power_clock_config.c"); +% } +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +FILES_`prop` := \ + % for(let val of obj[prop]) { + `val` \ + % } + % for(val of args.project.libs["common"]){ + % if (val.startsWith("enet")) { + ti_enet_config.c \ + ti_enet_open_close.c \ + ti_enet_soc.c \ + ti_enet_lwipif.c \ + % } + % } + + % } +% } +% obj = args.project.asmfiles; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +ASMFILES_`prop` := \ + % for(let val of obj[prop]) { + `val` \ + % } + + % } +% } +% obj = args.project.filedirs; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +FILES_PATH_`prop` = \ + % for(let val of obj[prop]) { + `val` \ + % } + % if ( prop == "common" && args.project.syscfgfile) { + generated \ + % } + + % } +% } +% obj = args.project.includes; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +INCLUDES_`prop` := \ + % for(let val of obj[prop]) { + -I`val` \ + % } + % if ( prop == "common" && args.project.syscfgfile) { + -Igenerated \ + % } + + % } +% } +% obj = args.project.defines; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +DEFINES_`prop` := \ + % for(let val of obj[prop]) { + -D`val` \ + % } + + % } +% } +% obj = args.project.cflags; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +CFLAGS_`prop` := \ + % for(let val of obj[prop]) { + `val` \ + % } + + % } +% } +% obj = args.project.lnkfiles; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +LNK_FILES_`prop` = \ + % for(let val of obj[prop]) { + `val` \ + % } + + % } +% } +% obj = args.project.libdirs; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +LIBS_PATH_`prop` = \ + % for(let val of obj[prop]) { + % if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) { + -L`val` \ + % } + % else { + `linker_option_prefix`-i`val` \ + % } + % } + + % } +% } +% obj = args.project.libs; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +LIBS_`prop` = \ + % for(let val of obj[prop]) { +% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) { + -l:`val` \ +% } +% else { + -l`val` \ +% } + % } + + % } +% } +% obj = args.project.lflags; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +LFLAGS_`prop` = \ + % for(let val of obj[prop]) { +% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) { + `val` \ +% } +% else { + `linker_option_prefix``val` \ +% } + % } + + % } +% } +% if ((args.project.cgt == 'ti-arm-clang')) { +% obj = args.project.loptflags; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +LNKOPTFLAGS_`prop` = \ + % for(let val of obj[prop]) { + `val` \ + % } + % } +% } +% } + +% obj = args.project.libs; +LIBS_NAME = \ +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { + % for(let val of obj[prop]) { + `val` \ + % } + % } +% } + +% obj = args.project.libdirs; +LIBS_PATH_NAME = \ +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { + % for(let val of obj[prop]) { + `val` \ + % } + % } +% } + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +% obj = args.project.files; +% if(args.project.files["cpp_common"] != undefined) { +CPPFILES := $(FILES_cpp_common) $(FILES_cpp_$(PROFILE)) +% } +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +% if(args.project.files["cpp_common"] != undefined) { +CPPFILES_PATH := $(FILES_PATH_cpp_common) $(FILES_PATH_$(PROFILE)) +CPPFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) $(CFLAGS_cpp_common) +% } +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +% if ((args.project.cgt == 'ti-arm-clang')) { +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +% } +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +% if(args.project.files["cpp_common"] != undefined) { +OBJS += $(CPPFILES:%.cpp=%.obj) +% } +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +% if(args.project.files["cpp_common"] != undefined) { +vpath %.cpp $(CPPFILES_PATH) +% } +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +% if(args.project.files["cpp_common"] != undefined) { +$(OBJDIR)/%.obj %.obj: %.cpp + @echo Compiling: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(OUTNAME): $< +% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") { + $(CC) $(CPPFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fc=$< +% } +% if (args.project.cgt == "ti-arm-clang") { + $(CC) -c $(CPPFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< +% } +% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) { + $(CC) -c $(CPPFLAGS) $(INCLUDES) $(DEFINES) -MMD -MT $@ -o $(OBJDIR)/$@ $< +% } + +% } +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(OUTNAME): $< +% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") { + $(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fc=$< +% } +% if (args.project.cgt == "ti-arm-clang") { + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< +% } +% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) { + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -MT $@ -o $(OBJDIR)/$@ $< +% } + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(LIBNAME): $< +% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") { + $(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$< +% } +% if (args.project.cgt == "ti-arm-clang") { + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< +% } +% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) { + $(CC) -c -x assembler-with-cpp $(CFLAGS) $(INCLUDES) $(DEFINES) -o $(OBJDIR)$@ $< +% } + +% if(((args.project.device == "am64x") || (args.project.device == "am243x")) && (!args.project.isBootLoader) && (!args.project.isPartOfSystemProject)) { +all: $(TARGETS) +% } else { +all: $(BOOTIMAGE_NAME) +% } + +% if ( args.project.syscfgfile ) { +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h +% for(val of args.project.libs["common"]){ + % if (val.startsWith("enet")) { +SYSCFG_GEN_FILES+=generated/ti_enet_config.c generated/ti_enet_config.h +SYSCFG_GEN_FILES+=generated/ti_enet_open_close.c generated/ti_enet_open_close.h +SYSCFG_GEN_FILES+=generated/ti_enet_soc.c +SYSCFG_GEN_FILES+=generated/ti_enet_lwipif.c generated/ti_enet_lwipif.h + % } + % } +% } + +% if ( args.project.syscfgfile ) { +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) +% } else { +$(OUTNAME): $(OBJS) $(LNK_FILES) $(LIBS_NAME) +% } + @echo . + @echo Linking: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $@ ... +% if (args.project.cgt == "ti-arm-clang" || args.project.cgt == "ti-c6000") { +% if (args.project.cgt == "ti-arm-clang") { + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) `linker_option_prefix`-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) +% } else { + $(LNK) $(LFLAGS) $(LIBS_PATH) `linker_option_prefix`-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) +% } +% if (args.project.isBootLoader) { +% } else { +% if (args.project.isLinuxFwGen) { + $(RM) `args.linuxFwName` + $(STRIP) -o=`args.linuxFwName` $@ +% } +% } +% } +% if ((args.project.cgt == 'gcc-aarch64') || (args.project.cgt == 'gcc-armv7')) { + $(LNK) $(LIBS_PATH) -Wl,-Map=$(OUTNAME:%.out=%.map) -o $@ -Wl,--start-group $(LFLAGS) $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) -Wl,--end-group -Wl,-T,$(LNK_FILES) +% } + @echo Linking: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $@ Done !!! + @echo . + +clean: + @echo Cleaning: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) +% if (args.project.isBootLoader) { +% } else { +% if (args.project.isLinuxFwGen) { + $(RM) `args.linuxFwName` +% } +% } +% if (args.project.isBootLoader) { + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_BIN_NAME) +% } else { + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) +% if (args.project.device == "awr294x") { + $(RM) $(BOOTIMAGE_NAME_QSPI) +% } + $(RM) $(BOOTIMAGE_NAME_SIGNED) +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) +% } + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) +% } +% if (args.project.syscfgfile) { + $(RMDIR) generated/ +% } + +scrub: + @echo Scrubing: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` `args.project.name` ... + $(RMDIR) obj +% if (args.project.isBootLoader) { +% } else { +% if (args.project.isLinuxFwGen) { + $(RM) `args.linuxFwName` +% } +% } +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif +% if (args.project.syscfgfile) { + $(RMDIR) generated +% } + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + +% if (args.project.syscfgfile) { + +% // with syscfg enabled, parallel build does not work due to generated files dependancies +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: `args.project.syscfgfile` + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context `args.syscfg.cpu` --part `args.syscfg.part` --package `args.syscfg.pkg` --output generated/ `args.project.syscfgfile` + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device `args.syscfg.device` --context `args.syscfg.cpu` --part `args.syscfg.part` --package `args.syscfg.pkg` --output generated/ `args.project.syscfgfile` +% } + +% if (args.project.isBootLoader) { +# +# Generation of boot image which can be loaded by ROM Boot Loader (RBL) +# +% } else { +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +% } +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) +% } + +% if (args.project.isBootLoader) { +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) +BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/rom_image_gen.py +SYSFW_PATH=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/soc/am64x_am243x +SYSFW_LOAD_ADDR=0x44000 +BOARDCFG_LOAD_ADDR=0x7B000 +% if (args.project.name.includes("linux")) { +% if (args.project.device == "am64x") { +BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am64x/boardcfg_blob_linux.bin +% } else if (args.project.device == "am243x") { +BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am243x/boardcfg_blob_linux.bin +% } +% } else { +% if (args.project.device == "am64x") { +BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am64x/boardcfg_blob.bin +% } else if (args.project.device == "am243x") { +BOARDCFG_BLOB=$(MCU_PLUS_SDK_PATH)/source/drivers/sciclient/sciclient_default_boardcfg/am243x/boardcfg_blob.bin +% } +% } +% } + +% if ((args.project.device == "am273x") || (args.project.device == "awr294x") || (args.project.device == "am263x")) { +ifeq ($(DEVICE_TYPE),HS) +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) +else +BOOTIMAGE_CERT_KEY=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_gpkey.pem +endif +BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_rom_image_gen.py +% } + +% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) { +SBL_RUN_ADDRESS=0x10200000 +% } else if (args.project.device == "am263x") { +SBL_RUN_ADDRESS=0x70002000 +% } else { +SBL_RUN_ADDRESS=0x70000000 +% } + +SBL_PREBUILT_PATH=$(MCU_PLUS_SDK_PATH)/tools/boot/sbl_prebuilt/`args.project.board` + +$(BOOTIMAGE_BIN_NAME): $(OUTNAME) + $(OBJCOPY) --strip-sections -O binary $(OUTNAME) $(BOOTIMAGE_BIN_NAME) + +$(BOOTIMAGE_NAME): $(BOOTIMAGE_BIN_NAME) + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$@ ... +% if (args.project.device == "awr294x") { +ifeq ($(DEVICE_TYPE),HS) +ifeq ($(DBG_ENABLED),no) + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug DBG_PUBLIC_ENABLE +endif +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT +endif +% } else if ((args.project.device == "am263x") || (args.project.device == "am273x")) { +ifeq ($(DEVICE_TYPE),HS) +ifeq ($(DEBUG_TIFS), yes) +ifeq ($(ENC_SBL_ENABLED),yes) + $(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) +endif +else +ifeq ($(ENC_SBL_ENABLED),yes) + $(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION) +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION) +endif +endif +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT +endif +% } else { +ifeq ($(DEVICE_TYPE),HS) +ifeq ($(ENC_SBL_ENABLED),yes) + $(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --sbl-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --debug DBG_FULL_ENABLE --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) +else + $(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --debug DBG_FULL_ENABLE --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) +endif +else + $(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) + $(BOOTIMAGE_CERT_GEN_CMD) --swrv 1 --sbl-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --sysfw-bin $(SYSFW_PATH)/sysfw-hs-fs-enc.bin --sysfw-inner-cert $(SYSFW_PATH)/sysfw-hs-fs-enc-cert.bin --boardcfg-blob $(BOARDCFG_BLOB) --sbl-loadaddr $(SBL_RUN_ADDRESS) --sysfw-loadaddr $(SYSFW_LOAD_ADDR) --bcfg-loadaddr $(BOARDCFG_LOAD_ADDR) --key $(BOOTIMAGE_CERT_KEY) --rom-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) +endif + $(COPY) $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) tiboot3.bin +% } + $(COPY) $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) $(SBL_PREBUILT_PATH)/ + +% if ((args.project.device != "am64x") || (args.project.device != "am243x")) { + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) +% } + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$@ Done !!! +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { +ifeq ($(DEVICE_TYPE),GP) + $(COPY) $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) $(SBL_PREBUILT_PATH)/ + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! +endif +% } + + @echo . + +% } else { +% if (args.project.device == "am64x") { +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) { +BOOTIMAGE_CORE_ID_a53ss0-1 = 1 +% } +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am243x") { +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am263x") { +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_r5fss1-0 = 2 +BOOTIMAGE_CORE_ID_r5fss1-1 = 3 +SBL_RUN_ADDRESS=0x70002000 +SBL_DEV_ID=55 +% } +% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) { +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_c66ss0 = 2 +% if (args.project.device == "awr294x") { +BOOTIMAGE_CORE_ID_r4 = 3 +R4_RPRC_PATH = $(MCU_PLUS_SDK_PATH)/source/drivers/bootloader/soc/awr294x/xwr2xxx_radarss_metarprc.bin +% } +SBL_RUN_ADDRESS=0x10200000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am62x") { +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_a53ss0-1 = 1 +BOOTIMAGE_CORE_ID_a53ss1-0 = 2 +BOOTIMAGE_CORE_ID_a53ss1-1 = 3 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_m4fss0-0 = 5 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) { +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py +% } + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_`args.project.cpu`) \ +% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) { + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_a53ss0-1) \ +% } + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_`args.project.cpu`) \ +% if((args.project.os == "freertos-smp") && (args.project.cpu == "a53ss0-0")) { + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_a53ss0-1) \ +% } + +% if (args.project.device == "awr294x") { +MULTI_CORE_IMAGE_PARAMS_QSPI = $(MULTI_CORE_IMAGE_PARAMS) $(R4_RPRC_PATH)@$(BOOTIMAGE_CORE_ID_r4) + +% } +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x`args.flashAddr.toString(16)` -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +% if (args.project.device == "awr294x") { + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_QSPI) $(MULTI_CORE_IMAGE_PARAMS_QSPI) >> $(BOOTIMAGE_TEMP_OUT_FILE) +% } +% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) { +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) +% } + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . +% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) { + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . +% } + +% if (((args.project.device == "am243x") || (args.project.device == "am64x")) && (!args.project.isPartOfSystemProject)) { +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: `args.project.device`:`args.project.cpu`:`args.project.os`:`args.project.cgt` $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +% } +% } +% if (args.isInstrumentationMode && args.project.cgt == "ti-arm-clang") { +.PHONY: coverage +coverage: + @echo Creating Coverage Report for `args.project.name`.$(PROFILE) ... + $(MKDIR) coverage + $(PROFDATA) merge -sparse -obj-file=$(OUTNAME) $(OUTNAME).cnt -o `args.project.name`.$(PROFILE).profdata + $(COV) show --format=html --show-expansions --show-instantiations --show-branches=count --object=$(OUTNAME) -instr-profile=`args.project.name`.$(PROFILE).profdata --output-dir=$(COVERAGE_PATH)/coverage + $(COV) export --format=text --object=$(OUTNAME) --instr-profile=`args.project.name`.$(PROFILE).profdata > coverage/`args.project.name`.$(PROFILE).profdata.json + node $(MCU_PLUS_SDK_PATH)/docs_src/code_coverage/clang_coverage_analyse.js --input=coverage/`args.project.name`.$(PROFILE).profdata.json --output-json=coverage/`args.project.name`.$(PROFILE).analysis.json --output-lnk=linker_xip.cmd --top-function-count=500 + @echo Coverage Report Generated at $(COVERAGE_PATH)/coverage folder !!! + +% } +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/.project/templates/makefile_library.xdt b/.project/templates/makefile_library.xdt new file mode 100644 index 0000000..cb7493b --- /dev/null +++ b/.project/templates/makefile_library.xdt @@ -0,0 +1,206 @@ +# +# Auto generated makefile +# + +export `args.sdkPath`?=$(abspath `args.relPath`) +include $(`args.sdkPath`)/imports.mak + +CG_TOOL_ROOT=$(`args.cgtOptions.path`) + +CC=$(`args.cgtOptions.path`)/bin/`args.cgtOptions.cc` +AR=$(`args.cgtOptions.path`)/bin/`args.cgtOptions.ar` + +PROFILE?=release +ConfigName:=$(PROFILE) + +% if (args.project.name == "drivers" && (args.project.device == "am243x" || args.project.device == "am64x")) { +DEVICE_TYPE?=GP +% } +LIBNAME:=`args.project.name`.`args.project.device`.`args.project.cpu`.`args.project.cgt`.$(PROFILE).lib + +% let obj = {} +% obj = args.project.files; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +FILES_`prop` := \ + % for(let val of obj[prop]) { + `val` \ + % } + + % } +% } +% obj = args.project.asmfiles; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +ASMFILES_`prop` := \ + % for(let val of obj[prop]) { + `val` \ + % } + + % } +% } +% if (args.project.device == "awr294x") { +% obj = args.project.asmextnfiles; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +ASMEXTNFILES_`prop` := \ + % for(let val of obj[prop]) { + `val` \ + % } + + % } +% } +% } +% obj = args.project.filedirs; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +FILES_PATH_`prop` = \ + % for(let val of obj[prop]) { + `val` \ + % } + + % } +% } +% obj = args.project.includes; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +INCLUDES_`prop` := \ + % for(let val of obj[prop]) { + -I`val` \ + % } + + % } +% } +% obj = args.project.defines; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +DEFINES_`prop` := \ + % for(let val of obj[prop]) { + -D`val` \ + % } + + % } +% } +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == "common" && args.project.name == "drivers" && (args.project.device == "am243x" || args.project.device == "am64x") ) { +# Remove later with combined boot +ifeq ($(DEVICE_TYPE),$(filter $(DEVICE_TYPE), HS)) +DEFINES_`prop` += -DBUILD_HS +endif + + % } +% } +% obj = args.project.cflags; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +CFLAGS_`prop` := \ + % for(let val of obj[prop]) { + `val` \ + % } + + % } +% } +% obj = args.project.arflags; +% for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) ) { +ARFLAGS_`prop` := \ + % for(let val of obj[prop]) { + `val` \ + % } + + % } +% } +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +% if (args.project.device == "awr294x") { +ASMEXTNFILES := $(ASMEXTNFILES_common) $(ASMEXTNFILES_$(PROFILE)) +% } +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ifeq ($(CPLUSPLUS_BUILD), yes) +CFLAGS += $(CFLAGS_cpp_common) +endif +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE)) + +LIBDIR := lib +OBJDIR := obj/`args.project.device`/`args.project.cgt`/$(PROFILE)/`args.project.cpu`/`args.project.name`/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +% if (args.project.device == "awr294x") { +OBJS += $(ASMEXTNFILES:%.asm=%.obj) +% } +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +% if (args.project.device == "awr294x") { +vpath %.asm $(FILES_PATH) +% } + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: $(LIBNAME): $< +% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") { + $(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fc=$< +% } +% if (args.project.cgt == "ti-arm-clang") { + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< +% } +% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) { + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -MT $@ -o $(OBJDIR)/$@ $< +% } + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: $(LIBNAME): $< +% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") { + $(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$< +% } +% if (args.project.cgt == "ti-arm-clang") { + $(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $< +% } +% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) { + $(CC) -c -x assembler-with-cpp $(CFLAGS) $(INCLUDES) $(DEFINES) -o $(OBJDIR)$@ $< +% } +% if (args.project.device == "awr294x") { + +$(OBJDIR)/%.obj %.obj: %.asm + @echo Compiling: $(LIBNAME): $< +% if (args.project.cgt == "ti-arm" || args.project.cgt == "ti-c6000") { + $(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$< +% } +% if (args.project.cgt == "ti-arm-clang") { + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< +% } +% if ((args.project.cgt == "gcc-aarch64") || (args.project.cgt == "gcc-armv7")) { + $(CC) -c -x assembler-with-cpp $(CFLAGS) $(INCLUDES) $(DEFINES) -o $(OBJDIR)$@ $< +% } +% } + +all: $(LIBDIR)/$(LIBNAME) + +$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR) + @echo . + @echo Archiving: $(LIBNAME) to $@ ... + $(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS)) + @echo Archiving: $(LIBNAME) Done !!! + @echo . + +clean: + @echo Cleaning: $(LIBNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(LIBDIR)/$(LIBNAME) + +scrub: + @echo Scrubing: $(LIBNAME) ... + -$(RMDIR) obj/ + -$(RMDIR) lib/ + +$(OBJS): | $(OBJDIR) + +$(LIBDIR) $(OBJDIR): + $(MKDIR) $@ + +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/.project/templates/makefile_projectspec.xdt b/.project/templates/makefile_projectspec.xdt new file mode 100644 index 0000000..c000fea --- /dev/null +++ b/.project/templates/makefile_projectspec.xdt @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export `args.sdkPath`?=$(abspath `args.relPath`) +include $(`args.sdkPath`)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=`args.project.name`_`args.project.board`_`args.project.cpu`_`args.project.os`_`args.project.cgt` + +all: + $(CCS_ECLIPSE) -noSplash -data $(`args.sdkPath`)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(`args.sdkPath`)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(`args.sdkPath`)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(`args.sdkPath`)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/.project/templates/makefile_pru.xdt b/.project/templates/makefile_pru.xdt new file mode 100644 index 0000000..70d450e --- /dev/null +++ b/.project/templates/makefile_pru.xdt @@ -0,0 +1,163 @@ +% let obj = args.project; +% let projectName = `${obj.name}_${obj.board}_${obj.cpu}_${obj.os}_${obj.cgt}`; +% let projectPath = `${obj.relpath}/${obj.board}/${obj.cpu}_${obj.os}/${obj.cgt}`; +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./`obj.pru_main_file`.obj" \ +"$(MCU_PLUS_SDK_PATH)/`projectPath`/`obj.pru_linker_file`.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +% // review these include files +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/`projectPath`/`obj.pru_linker_file`.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/`obj.relpath`/`obj.pru_main_file`.asm + +OBJS += \ +./`obj.pru_main_file`.obj + +ASM_DEPS += \ +./`obj.pru_main_file`.d + +OBJS__QUOTED += \ +"`obj.pru_main_file`.obj" + +ASM_DEPS__QUOTED += \ +"`obj.pru_main_file`.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/`obj.relpath`/`obj.pru_main_file`.asm" + +% let commandString = ""; +% let cflags = obj.cflags; +% for (let prop in cflags) { + % if ( cflags.hasOwnProperty(prop) && Array.isArray(cflags[prop]) && prop == 'common') { + % for(let val of cflags[prop]) { + % commandString += `${val} `; + % } + % } +% } +% let defines = obj.defines; +% for (let prop in defines) { + % if ( defines.hasOwnProperty(prop) && Array.isArray(defines[prop]) && prop == 'common') { + % for(let val of defines[prop]) { + % commandString += `--define=${val} `; + % } + % } +% } +% let cmdSubStr = commandString; +% commandString += `--include_path="$(CCS_PATH)" `; +% if ("postBuildSteps" in obj || obj["defaultPruPostBuildSteps"]) { + % commandString += `--include_path="$(SYSCFG_DIR)" `; +% } +% let includes = obj.includes; +% for (let prop in includes) { + % if ( includes.hasOwnProperty(prop) && Array.isArray(includes[prop]) && prop == 'common') { + % for(let val of includes[prop]) { + % commandString += `--include_path="${val}" `; + % } + % } +% } +# Each subdirectory must supply rules for building sources it contributes +`obj.pru_main_file`.obj: $(MCU_PLUS_SDK_PATH)/`obj.relpath`/`obj.pru_main_file`.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" `commandString` --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(=0; i--) { + $(CORE_`i`) \ +% } + +all: syscfg +% for (let project of args.project.projects) { + $(MAKE) -C ../`project.cpu`_`project.os`/`project.cgt`/ all +% } + $(MAKE) $(MULTI_CORE_BOOTIMAGE_NAME) +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { +ifeq ($(DEVICE_TYPE), HS) + $(MAKE) $(MULTI_CORE_BOOTIMAGE_NAME_HS) +endif +% } +% for (let project of args.project.projects) { +% if (project.isLinuxFwGen) { + $(COPY) ../`project.cpu`_`project.os`/`project.cgt`/`args.device.getLinuxFwName(project.cpu)` . +% } +% } + +clean: +% for (let project of args.project.projects) { + $(MAKE) -C ../`project.cpu`_`project.os`/`project.cgt`/ clean +% } + $(RM) $(MULTI_CORE_BOOTIMAGE_NAME) + $(RM) $(MULTI_CORE_BOOTIMAGE_NAME_SIGNED) + $(RM) $(MULTI_CORE_BOOTIMAGE_NAME_XIP) +% if (args.project.device == "awr294x") { + $(RM) $(MULTI_CORE_BOOTIMAGE_NAME_QSPI) +% } +% for (let project of args.project.projects) { +% if (project.isLinuxFwGen) { + $(RM) `args.device.getLinuxFwName(project.cpu)` +% } +% } + +scrub: +% for (let project of args.project.projects) { + $(MAKE) -C ../`project.cpu`_`project.os`/`project.cgt`/ scrub +% } +% for (let project of args.project.projects) { +% if (project.isLinuxFwGen) { + $(RM) `args.device.getLinuxFwName(project.cpu)` +% } +% } +ifeq ($(OS),Windows_NT) + $(RM) \*.appimage + $(RM) \*.appimage.signed +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { + $(RM) \*.appimage.hs +% } + $(RM) \*.appimage_xip +else + $(RM) *.appimage + $(RM) *.appimage.signed +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { + $(RM) \*.appimage.hs +% } + $(RM) *.appimage_xip +endif + +syscfg: + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) $(CORES) + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device `args.device.getSysCfgDevice(args.project.board)` --part `args.device.getSysCfgPart(args.project.board)` --package `args.device.getSysCfgPkg(args.project.board)` $(CORES) + +# +# Generation of multi-core boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +% if (args.project.device == "am64x") { +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am243x") { +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am263x") { +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_r5fss1-0 = 2 +BOOTIMAGE_CORE_ID_r5fss1-1 = 3 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) { +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_c66ss0 = 2 +% if (args.project.device == "awr294x") { +BOOTIMAGE_CORE_ID_r4 = 3 +R4_RPRC_PATH = $(MCU_PLUS_SDK_PATH)/source/drivers/bootloader/soc/awr294x/xwr2xxx_radarss_metarprc.bin +% } +SBL_RUN_ADDRESS=0x10200000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am62x") { +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_a53ss0-1 = 1 +BOOTIMAGE_CORE_ID_a53ss1-0 = 2 +BOOTIMAGE_CORE_ID_a53ss1-1 = 3 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_m4fss0-0 = 5 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +% if ((args.project.device == "am243x") || (args.project.device == "am64x")) { +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py +% } + +MULTI_CORE_APP_PARAMS = \ +% for (let project of args.project.projects) { + ../`project.cpu`_`project.os`/`project.cgt`/`args.project.name`.$(PROFILE).rprc@$(BOOTIMAGE_CORE_ID_`project.cpu`) \ +% } + +MULTI_CORE_APP_PARAMS_XIP = \ +% for (let project of args.project.projects) { + ../`project.cpu`_`project.os`/`project.cgt`/`args.project.name`.$(PROFILE).rprc_xip@$(BOOTIMAGE_CORE_ID_`project.cpu`) \ +% } + +% if (args.project.device == "awr294x") { +MULTI_CORE_APP_PARAMS_QSPI = $(MULTI_CORE_APP_PARAMS) $(R4_RPRC_PATH)@$(BOOTIMAGE_CORE_ID_r4) + +% } +MULTI_CORE_BOOTIMAGE_DEPENDENCY = \ +% for (let project of args.project.projects) { + ../`project.cpu`_`project.os`/`project.cgt`/`args.project.name`.$(PROFILE).rprc \ +% } + +$(MULTI_CORE_BOOTIMAGE_DEPENDENCY): + +$(MULTI_CORE_BOOTIMAGE_NAME): $(MULTI_CORE_BOOTIMAGE_DEPENDENCY) + @echo Boot multi-core image: $@ ... + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME) $(MULTI_CORE_APP_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME_XIP) $(MULTI_CORE_APP_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +% if (args.project.device == "awr294x") { + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME_QSPI) $(MULTI_CORE_APP_PARAMS_QSPI) >> $(BOOTIMAGE_TEMP_OUT_FILE) +% } + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_PATH)/$@ Done !!! + @echo . +% if ((args.project.device == "am243x") || (args.project.device == "am64x")) { + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME).hs_fs + @echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_PATH)/$(MULTI_CORE_BOOTIMAGE_NAME).hs_fs Done !!! + @echo . + +$(MULTI_CORE_BOOTIMAGE_NAME_HS): $(MULTI_CORE_BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME_HS) + $(RM) $(MULTI_CORE_BOOTIMAGE_NAME)-enc +endif + @echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_PATH)/$@ Done !!! + @echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_PATH)/$(MULTI_CORE_BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +% } diff --git a/.project/templates/makefile_system_ccs_bootimage_gen.xdt b/.project/templates/makefile_system_ccs_bootimage_gen.xdt new file mode 100644 index 0000000..050adac --- /dev/null +++ b/.project/templates/makefile_system_ccs_bootimage_gen.xdt @@ -0,0 +1,153 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - OUTNAME +# - CCS_INSTALL_DIR + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(`args.sdkName`)/imports.mak +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { +include $(`args.sdkName`)/devconfig/devconfig.mak +% } + +% if ((args.project.device == "am64x") || (args.project.device == "am243x")) { +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif +% } + +MULTI_CORE_BOOTIMAGE_PATH=$(abspath $(PROFILE)) +MULTI_CORE_BOOTIMAGE_NAME:=$(PROFILE)/$(OUTNAME).appimage +MULTI_CORE_BOOTIMAGE_NAME_SIGNED:=$(PROFILE)/$(OUTNAME).appimage.signed +MULTI_CORE_BOOTIMAGE_NAME_XIP:=$(PROFILE)/$(OUTNAME).appimage_xip +% if (args.project.device == "awr294x") { +MULTI_CORE_BOOTIMAGE_NAME_QSPI:=$(PROFILE)/$(OUTNAME).appimage_qspi +% } + +# +# Generation of multi-core boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +% if (args.project.device == "am64x") { +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am243x") { +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am263x") { +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_r5fss1-0 = 2 +BOOTIMAGE_CORE_ID_r5fss1-1 = 3 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } +% if ((args.project.device == "am273x") || (args.project.device == "awr294x")) { +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_c66ss0 = 2 +% if (args.project.device == "awr294x") { +BOOTIMAGE_CORE_ID_r4 = 3 +R4_RPRC_PATH = $(MCU_PLUS_SDK_PATH)/source/drivers/bootloader/soc/awr294x/xwr2xxx_radarss_metarprc.bin +% } +SBL_RUN_ADDRESS=0x10200000 +SBL_DEV_ID=55 +% } +% if (args.project.device == "am62x") { +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_a53ss0-1 = 1 +BOOTIMAGE_CORE_ID_a53ss1-0 = 2 +BOOTIMAGE_CORE_ID_a53ss1-1 = 3 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_m4fss0-0 = 5 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 +% } + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +% if ((args.project.device == "am243x") || (args.project.device == "am64x")) { +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py +% } + +MULTI_CORE_APP_PARAMS = \ +% for (let project of args.project.projects) { + ../`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`/$(PROFILE)/`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`.rprc@$(BOOTIMAGE_CORE_ID_`project.cpu`) \ +% } + +MULTI_CORE_APP_PARAMS_XIP = \ +% for (let project of args.project.projects) { + ../`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`/$(PROFILE)/`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`.rprc_xip@$(BOOTIMAGE_CORE_ID_`project.cpu`) \ +% } + +% if (args.project.device == "awr294x") { +MULTI_CORE_APP_PARAMS_QSPI = $(MULTI_CORE_APP_PARAMS) $(R4_RPRC_PATH)@$(BOOTIMAGE_CORE_ID_r4) + +% } +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME) ... + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME) $(MULTI_CORE_APP_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME_XIP) $(MULTI_CORE_APP_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +% if (args.project.device == "awr294x") { + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(MULTI_CORE_BOOTIMAGE_NAME_QSPI) $(MULTI_CORE_APP_PARAMS_QSPI) >> $(BOOTIMAGE_TEMP_OUT_FILE) +% } +% if ((args.project.device == "am243x") || (args.project.device == "am64x")) { +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME).hs_fs +% } +% if ((args.project.device == "am243x") || (args.project.device == "am64x")) { +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(MULTI_CORE_BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(MULTI_CORE_BOOTIMAGE_NAME).hs + $(RM) $(MULTI_CORE_BOOTIMAGE_NAME)-enc +endif +endif +% } +% for (let project of args.project.projects) { +% if (project.isLinuxFwGen) { + $(COPY) ../`args.project.name`_`project.board`_`project.cpu`_`project.os`_`project.cgt`/$(PROFILE)/`args.device.getLinuxFwName(project.cpu)` $(PROFILE)/ +% } +% } +% if ((args.project.device == "am243x") || (args.project.device == "am64x")) { +ifeq ($(DEVICE_TYPE),HS) + @echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME).hs Done !!! +else + @echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME) Done !!! + @echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME).hs_fs Done !!! +endif +% } else { + @echo Boot multi-core image: $(MULTI_CORE_BOOTIMAGE_NAME) Done !!! +% } + @echo . +endif diff --git a/.project/templates/makefile_system_projectspec.xdt b/.project/templates/makefile_system_projectspec.xdt new file mode 100644 index 0000000..0707671 --- /dev/null +++ b/.project/templates/makefile_system_projectspec.xdt @@ -0,0 +1,23 @@ +# +# Auto generated makefile +# + +export `args.sdkName`?=$(abspath `args.relPath`) +include $(`args.sdkName`)/imports.mak + +export PROFILE?=Release + +PROJECT_NAME=`args.project.name`_`args.project.board`_system_`args.project.tag` + +all: + $(CCS_ECLIPSE) -noSplash -data $(`args.sdkName`)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(`args.sdkName`)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean +% for (let project of args.project.projects) { + $(MAKE) -C ../`project.cpu`_`project.os`/`project.cgt`/ -f makefile_projectspec clean +% } + +export: + $(MKDIR) $(`args.sdkName`)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(`args.sdkName`)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec system.projectspec -ccs.overwrite full diff --git a/.project/templates/package.ccs.json.xdt b/.project/templates/package.ccs.json.xdt new file mode 100644 index 0000000..e7567c0 --- /dev/null +++ b/.project/templates/package.ccs.json.xdt @@ -0,0 +1,21 @@ +%%{ + productName = args.utils.getProductNameProjectSpec(args.device); +%%} +[ + { + "rootMacroName": "COM_TI_`productName`_INSTALL_DIR", + "compilerIncludePath": [ ], + "compilerSymbols": [ ], + "linkerSearchPath": [ ], + "properties": { + "rtsc.repositories": [ + "source", + "." + ] + }, + "helpTocs": [ + ], + "docs": [ + ] + } +] diff --git a/.project/templates/package.tirex.json.xdt b/.project/templates/package.tirex.json.xdt new file mode 100644 index 0000000..f519748 --- /dev/null +++ b/.project/templates/package.tirex.json.xdt @@ -0,0 +1,38 @@ +%%{ + productName = args.utils.getProductNameProjectSpec(args.device); + isDevelopmentMode = args.common.isDevelopmentMode(); + deviceName = args.utils.getProjectSpecDevice(args.device); + if(args.device == "am273x") + deviceName = "AM273x" + if(args.device == "am62x") + deviceName = "AM62x" + if(isDevelopmentMode) + deviceName = "AMXXX"; +%%} +[ + { + "metadataVersion": "3.01.00", + "id": "com.ti.`productName`", + "name": "MOTOR CONTROL SDK for `deviceName`", + "rootCategory": [ "MOTOR CONTROL SDK", "MOTOR CONTROL SDK for `deviceName`" ], + "version": "09.00.00.01", + "type": "software", + "image": "./mcu_plus_sdk.png", + % if ((args.device == "am64x") || (args.device == "am243x") || (isDevelopmentMode)) { + "license": "../../license.txt", + % } + "devices": ["`deviceName`"], + "tags": ["SDK", "Baremetal", "FreeRTOS"], + "description": "Welcome to MOTOR CONTROL SDK for `deviceName`. This SDK contains examples, libraries and tools to develop RTOS and no-RTOS based applications for ARM R5F, ARM M4F CPUs and related peripherals.", + "dependencies": [ + { "packageId": "sysconfig", "version": "`args.utils.getSysCfgVersionProjectSpec()`", "require": "mandatory" }, + % if (args.device == "am64x" || (isDevelopmentMode)) { + { "packageId": "ti_cgt_tiarmclang", "version": "`args.utils.getTiClangVersionProjectSpec()`", "require": "mandatory" }, + { "packageId": "arm.gnu.aarch64-none", "version": "`args.utils.getGCCAarch64NoneVersionProjectSpec()`", "require": "mandatory" } + % } + % else { + { "packageId": "ti_cgt_tiarmclang", "version": "`args.utils.getTiClangVersionProjectSpec()`", "require": "mandatory" } + % } + ] + } +] diff --git a/.project/templates/product.json.xdt b/.project/templates/product.json.xdt new file mode 100644 index 0000000..23da80d --- /dev/null +++ b/.project/templates/product.json.xdt @@ -0,0 +1,127 @@ +%%{ + isDevelopmentMode = args.common.isDevelopmentMode(); + deviceName = args.utils.getProjectSpecDevice(args.device); + if(args.device == "am62x") + deviceName = "AM62x" + sysCfgVersion = args.utils.getSysCfgVersionProjectSpec(); +%%} +{ +% if(isDevelopmentMode) { + "name": "MOTOR_CONTROL_SDK", + "displayName": "MOTOR CONTROL SDK", +% } else { + "name": "MOTOR_CONTROL_SDK_`deviceName`", + "displayName": "MOTOR CONTROL SDK for `deviceName`", +% } + "version": "09.00.00", + "documentationPath": "../docs", + "includePaths": [ + "../source", + ], + "components": [ +% if((args.device == "am64x") || (args.device == "am243x")) { + "/motor_control/motor_control", +% } +% if(args.device == "am263x") { + "/motor_control/motor_control", +% } +% if((args.device == "am273x") || (args.device == "awr294x")) { + "/kernel/dpl", + "/drivers/drivers", + "/board/board", + "/networking/networking", +% } +% if(args.device == "am62x") { + "/kernel/dpl", + "/drivers/drivers", + "/board/board", +% } + ], + "devices": [ +% if((args.device == "am64x") || (isDevelopmentMode)) { + "AM64x_beta", +% } +% if((args.device == "am243x") || (isDevelopmentMode)) { + "AM243x_ALV_beta", + "AM243x_ALX_beta", +% } +% if((args.device == "am273x") || (isDevelopmentMode)) { + "AM273x", +% } +% if((args.device == "awr294x") || (isDevelopmentMode)) { + "AWR294X", +% } +% if((args.device == "am263x") || (isDevelopmentMode)) { + "AM263x_beta", +% } +% if((args.device == "am62x") || (isDevelopmentMode)) { + "AM62x", +% } + ], + "contexts": { +% if((args.device == "am64x") || (isDevelopmentMode)) { + "AM64x_beta": [ + "r5fss0-0", + "r5fss0-1", + "r5fss1-0", + "r5fss1-1", + "m4fss0-0", + "a53ss0-0", + ], +% } +% if((args.device == "am243x") || (isDevelopmentMode)) { + "AM243x_ALV_beta": [ + "r5fss0-0", + "r5fss0-1", + "r5fss1-0", + "r5fss1-1", + "m4fss0-0", + ], + "AM243x_ALX_beta": [ + "r5fss0-0", + "r5fss0-1", + "r5fss1-0", + "r5fss1-1", + "m4fss0-0", + ], +% } +% if((args.device == "am273x") || (isDevelopmentMode)) { + "AM273x": [ + "r5fss0-0", + "r5fss0-1", + "c66ss0", + "hsm0-0", + ], +% } +% if((args.device == "awr294x") || (isDevelopmentMode)) { + "AWR294X": [ + "r5fss0-0", + "r5fss0-1", + "c66ss0", + "hsm0-0", + ], +% } +% if((args.device == "am263x") || (isDevelopmentMode)) { + "AM263x_beta": [ + "r5fss0-0", + "r5fss0-1", + "r5fss1-0", + "r5fss1-1", + "hsm0-0", + ], +% } +% if((args.device == "am62x") || (isDevelopmentMode)) { + "AM62x": [ + "m4fss0-0", + ], +% } + }, + "pinmuxUIOptions": { + "group": "merged", + "hidePeripheralTab": false, + "showPinTable": true, + "showSignals": true, + "showUsed": true + }, + "minToolVersion" : "`sysCfgVersion`" +} diff --git a/.project/templates/projectspec_executable.xdt b/.project/templates/projectspec_executable.xdt new file mode 100644 index 0000000..db24b39 --- /dev/null +++ b/.project/templates/projectspec_executable.xdt @@ -0,0 +1,303 @@ +%%{ + let profile_list = ["debug", "release"]; + + products = ""; + if("syscfgfile" in args.project) { + products+=`sysconfig;` + } + products+=`com.ti.${args.utils.getProductNameProjectSpec(args.project.device)};` + productName = args.utils.getProductNameProjectSpec(args.project.device); + products+=`com.ti.${args.utils.getDependentProductNameProjectSpec(args.project.device)}` + dependentProductName = args.utils.getDependentProductNameProjectSpec(args.project.device); + if(args.project.projecspecFileAction) // should be renamed to projectspecFileAction + { + defaultAction = args.project.projecspecFileAction; + } + else + { + defaultAction = args.utils.getDefaultActionProjectSpec(); + } +%%} + + + + + + + + + % if("importOtherProject" in args.project) { + + + % } + + + % for (profile of profile_list ) { + + % } + % if(args.project.device == "am273x") { + + % } + + + % filelist = args.utils.getFileListProjectSpec(args.project.files, args.project.filedirs, args.project.dirPath) + % for (file of filelist) { + + + % } + % filelist = args.utils.getFileListProjectSpec(args.project.projectspecfiles, args.project.filedirs, args.project.dirPath) + % for (file of filelist) { + + + % } + % obj = args.project.lnkfiles + % for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') { + % for(let val of obj[prop]) { + + + % } + % } + % } + % if("syscfgfile" in args.project) { + + + % } + % if("readmeDoxygenPageTag" in args.project) { + + + % } + % obj = args.project.projectspec_files + % for (prop in obj) { + % if ( obj.hasOwnProperty(prop) && Array.isArray(obj[prop]) && prop == 'common') { + % for(let val of obj[prop]) { + + + % } + % } + % } + % if("syscfgfile" in args.project) { + + + % } + % if(args.project.skipMakefileCcsBootimageGen) {} else { + + + % } + + diff --git a/.project/templates/projectspec_system.xdt b/.project/templates/projectspec_system.xdt new file mode 100644 index 0000000..48171e2 --- /dev/null +++ b/.project/templates/projectspec_system.xdt @@ -0,0 +1,36 @@ +%%{ + products = ""; + products+=`com.ti.${args.utils.getProductNameProjectSpec(args.project.projects[0].device)}` + productName = args.utils.getProductNameProjectSpec(args.project.projects[0].device); +%%} + + +% for (let project of args.project.projects) { + +% } + + + % if("readmeDoxygenPageTag" in args.project) { + + + % } + + + + + + diff --git a/.project/templates/syscfg_c.rov.xs.xdt b/.project/templates/syscfg_c.rov.xs.xdt new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/.project/templates/syscfg_c.rov.xs.xdt @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/.project/templates/system.xml.xdt b/.project/templates/system.xml.xdt new file mode 100644 index 0000000..560078c --- /dev/null +++ b/.project/templates/system.xml.xdt @@ -0,0 +1,16 @@ + + +% let num = 0; +% for (let project of args.project.projects) { + + + + % num = num + 1; +% } + + + + + + + diff --git a/.project/templates/tirex_content.xdt b/.project/templates/tirex_content.xdt new file mode 100644 index 0000000..85d7200 --- /dev/null +++ b/.project/templates/tirex_content.xdt @@ -0,0 +1 @@ +`JSON.stringify(args.tirex_content_list, null, " ")` diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 0000000..afdc248 --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,6 @@ +# Contributing to this project + +This project is currently not accepting any contributions. + +We expect to accept contributions in 2Q23. + diff --git a/LICENSE.md b/LICENSE.md new file mode 100644 index 0000000..ea67a14 --- /dev/null +++ b/LICENSE.md @@ -0,0 +1 @@ +Please refer to docs/manifest.html for license information. diff --git a/README.md b/README.md new file mode 100644 index 0000000..0d362a7 --- /dev/null +++ b/README.md @@ -0,0 +1,269 @@ +
+ +
+# Motor Control SDK + +[Introduction](#introduction) | [Features](#features) | [Overview](#overview) | [Learn](#learn) | [Usage](#usage) | [Contribute](#contributing-to-the-project) + +
+ +## Introduction + +The Motor Control SDK enables real-time industrial communications for TI processors. Industrial communication is typically handled by the Programmable Real-Time Unit Industrial Communication Subsystem (PRU-ICSS). The PRU-ICSS is a co-processor subsystem containing Programmable Real-Time (PRU) cores and Ethernet media access controllers (EMACs), which implement the low level industrial Ethernet and fieldbus protocols through firmware. + +These devices currently include + +- [AM2431](https://www.ti.com/product/AM2431), [AM2432](https://www.ti.com/product/AM2432), [AM2434](https://www.ti.com/product/AM2434) +- [AM2634](https://www.ti.com/product/AM2634), [AM2634-Q1](https://www.ti.com/product/AM2634-Q1) +- [AM6411](https://www.ti.com/product/AM6411), [AM6412](https://www.ti.com/product/AM6412), [AM6421](https://www.ti.com/product/AM6421), [AM6422](https://www.ti.com/product/AM6422), [AM6441](https://www.ti.com/product/AM6441), [AM6442](https://www.ti.com/product/AM6442) + +## Features + +- Out of Box peripheral and application Examples + - Application Level Examples: Motor Drives, Industrial Communications etc. + +- Protocol stacks and middleware + - Various Industrial Protocol Stacks + +- Industrial protocol firmware + - ICCSG, ICSSM etc. + +## Overview + +## Learn + +## Usage + +### Prerequisites + +#### Supported HOST environments + +- Windows 10 64bit +- Ubuntu 18.04 64bit + +### Clone and build from GIT + +#### Repo Tool Setup + +Motor Control SDK has multiple components (in multiple repositories) and dependencies +(like compiler, CCS and other tools). We use repo tool from Google to manage these +multiple repositories. Currently there is no support for native windows shells like +CMD or Powershell. This will be added at a later point. Windows users can rely on +Git Bash for the repo setup. Follow the below mentioned steps to setup repo tool: + +Make sure [python3 is installed](https://wiki.python.org/moin/BeginnersGuide/Download) and is in your OS path. + +- Linux: + Do the following in terminal + ```bash + curl https://storage.googleapis.com/git-repo-downloads/repo > ~/bin/repo + chmod a+x ~/bin/repo + echo "PATH=$HOME/bin:$PATH" >> ~/.bashrc + source ~/.bashrc + ``` + +- Git-Bash (Windows) + Make sure that python 3 is callable as `python` from CMD. Do below in Git-Bash + ```bash + mkdir -p /c/ti + curl https://storage.googleapis.com/git-repo-downloads/repo > /c/ti/repo + echo "alias repo=\"winpty python /c/ti/repo\"" >> ~/.bashrc + source ~/.bashrc + ``` + +#### Cloning The Repositories + +To clone the repositories using repo tool, do below in your workarea folder: + +Note that depending on the SoC you're working with, the components you clone might be +slightly different. So please choose the manifest folder according to the SoC of your +interest. For example, we are showing for am263x below. + +```bash +repo init -u https://github.com/TexasInstruments/industrial-comms-manifests.git -m am243x/dev.xml -b main +``` + +Note that repo uses symbolic links. So if you're on Windows and do not have permissions +to create symbolic links, the above command might fail for you. So you can either enable them +([refer this link](https://portal.perforce.com/s/article/3472)) or use the experimental +worktree feature of repo. To do this, initialize the repo like so: + +```bash +repo init --worktree -u https://github.com/TexasInstruments/industrial-comms-manifests.git -m am243x/dev.xml -b main +``` + +After the repo is initialized, do a + +```bash +repo sync +``` + +This should clone all the repositories required for Motor Control SDK development. Now download and install the dependencies. + +#### Downloading And Installing Dependencies + +Note that the dependencies are also soc specific, here we take an example of am263x. +You can replace that with the SoC of your choice like the `repo init` step. + +**To download and install dependencies in linux, follow the below steps**: + +Run the following from the same location where you have `industrial_comms` and `industrial_comms_setup` +folders. + +```bash +./industrial_comms_setup/am243x/download_components.sh +``` + +This will install all the required dependencies including Code Composer Studio (CCS). +The script assumes that `industrial_comms` folder is in the same location from where +you have invoked the script, and that dependencies are installed into `${HOME}/ti` +location. If these defaults don't work for you, please pass these as arguments to +the script like + +```bash +./industrial_comms_setup/am243x/download_components.sh --install_dir=/path/to/tools + +OR + +./industrial_comms_setup/am243x/download_components.sh --industrial_comms_sdk_folder=/path/to/industrial_comms/folder +``` +and so on. For a complete list of arguments you can pass to the script, please run + +```bash +./industrial_comms_setup/am243x/download_components.sh -h +``` + +**In windows the dependencies has to be manually installed. Given below are the steps**: + +1. Download and install Code Composer Studio v12.1 from [here](https://www.ti.com/tool/download/CCSTUDIO "Code Composer Studio") + - Install at default folder, C:\ti + +2. Download and install SysConfig 1.14.0 from [here](https://www.ti.com/tool/download/SYSCONFIG/1.14.0.2667 "SYSCONFIG 1.14.0") + - Install at default folder, C:/ti + +3. Download and install GCC for Cortex A53 and ARM R5 from below link (only needed for AM64x developers) + - [GNU-A](https://developer.arm.com/-/media/Files/downloads/gnu-a/9.2-2019.12/binrel/gcc-arm-9.2-2019.12-mingw-w64-i686-aarch64-none-elf.tar.xz) + - [GNU-RM](https://developer.arm.com/-/media/Files/downloads/gnu-rm/7-2017q4/gcc-arm-none-eabi-7-2017-q4-major-win32.zip) + - Install at default folder, C:/ti + +4. Download and install Node.js v12.18.4 LTS + - Go to the [NodeJS Website](https://nodejs.org/en/) and use the installer to + download and install v12.18.4 of node. Install in the default directory. + - After successful installation, run an `npm ci` inside the `industrial_comms` folder like so: + ```bash + $ cd industrial_comms/ + $ npm ci + $ cd ../ + ``` + This should install the node packages required for the SDK. + +1. Download and install doxygen, + - Tested with 1.8.20 + - Download the correct version of doxygen for windows from [here](https://www.doxygen.nl/download.html) + - Install and add the install path, typically, C:/Program Files/doxygen/bin to your windows PATH + - Test by doing below on the command prompt + ``` + $ doxygen -v + 1.8.20 () + ``` + +**Installing OpenSSL** + +Some of the SDK signing scripts are dependent on OpenSSL v1.1.1. The v1.1.1 is +important, OpenSSL 3.0 is not compatible with the current signing scripts of SDK. + +In Windows, + - Download v1.1.1 from [here](https://slproweb.com/products/Win32OpenSSL.html) + - You can install the "light" version which is smaller download size + - Install to default path, which is C:/Program Files/OpenSSL-Win64/ + - When prompted select option to install binaries to /bin folder of installed path instead of Windows system path. + - Add path to OpenSSL, to your environment "Path" variable in windows + - `C:\Program Files\OpenSSL-Win64\bin` + +In Linux, + - There is a chance that OpenSSL is already installed. If not, here are the steps: + - If you have Ubuntu 18.04, do below in Linux Ubuntu shell to install openssl + -`$ sudo apt install openssl` + + If you have an Ubuntu version higher than that, make sure that you install the 1.1.1 version. + You can get the 1.1.1 packages from [here](http://security.ubuntu.com/ubuntu/pool/main/o/openssl/). + The packages required are openssl, libssl and libssl-dev + +Test openssl version by running `openssl version` on a command prompt and make sure there is no error. +Example output is shown below, + +```bash + C:\> openssl version + OpenSSL 1.1.1k 25 Mar 2021 +``` + +Now that the dependencies are installed, you can start the repositories with a +default branch `dev` by doing below: + +```bash +repo start dev --all +``` + +--- + +**NOTE** + +- In Linux, you will need to run `$HOME/ti/ccs{version}/ccs/install_scripts/install_drivers.sh` script for setting COM + port accesses correctly. Also add your user to groups `tty` and `dialout`. You can do + + ``` + sudo adduser $USER tty + sudo adduser $USER dialout + ``` + +- Please use the industrial communication libraries from the sdk installer due licensing restrictions. + +--- + +### Building the SDK + +#### Basic Building With Makefiles + +--- + +**NOTE** + +- Use `gmake` in windows, add path to gmake present in CCS at `C:\ti\ccsxxxx\ccs\utils\bin` to your windows PATH. We have + used `make` in below instructions. +- Unless mentioned otherwise, all below commands are invoked from root folder of the "industrial_comms" repository. +- Current supported device names are am64x, am243x, am263x, am273x and awr294x +- Pass one of these values to `"DEVICE="` +- You can also build components (examples, tests or libraries) in `release` or `debug` + profiles. To do this pass one of these values to `"PROFILE="` + +--- + +1. Run the following command to create makefiles, this step is optional since this is invoked as part of other steps as well, + + ```bash + make gen-buildfiles DEVICE=am263x + ``` + +2. To see all granular build options, run + + ```bash + make -s help DEVICE=am263x + ``` + This should show you commands to build specific libraries, examples or tests. + +3. Make sure to build the libraries before attempting to build an example. For example, + to build a Hello World example for AM263x, run the following: + ```bash + make -s -j4 libs DEVICE=am263x PROFILE=debug + ``` + Once the library build is complete, to build the example run: + ```bash + make -s -C examples/hello_world/am263x-cc/r5fss0-0_nortos/ti-arm-clang all PROFILE=debug + ``` + +4. Following are the commands to build **all libraries** and **all examples**. Valid PROFILE's are "release" or "debug" + + ```bash + make -s -j4 clean DEVICE=am263x PROFILE=debug + make -s -j4 all DEVICE=am263x PROFILE=debug + ``` \ No newline at end of file diff --git a/README_FIRST_AM243X.html b/README_FIRST_AM243X.html new file mode 100644 index 0000000..75bed27 --- /dev/null +++ b/README_FIRST_AM243X.html @@ -0,0 +1,12 @@ + + +Texas Instruments + + + + +If your browser doesn't automatically go to the SDK homepage within a few seconds, +please click +HERE + + diff --git a/README_FIRST_AM263X.html b/README_FIRST_AM263X.html new file mode 100644 index 0000000..83b43f3 --- /dev/null +++ b/README_FIRST_AM263X.html @@ -0,0 +1,12 @@ + + +Texas Instruments + + + + +If your browser doesn't automatically go to the SDK homepage within a few seconds, +please click +HERE + + diff --git a/README_FIRST_AM64X.html b/README_FIRST_AM64X.html new file mode 100644 index 0000000..7e8c95e --- /dev/null +++ b/README_FIRST_AM64X.html @@ -0,0 +1,12 @@ + + +Texas Instruments + + + + +If your browser doesn't automatically go to the SDK homepage within a few seconds, +please click +HERE + + diff --git a/devconfig/devconfig.mak b/devconfig/devconfig.mak new file mode 100644 index 0000000..de84394 --- /dev/null +++ b/devconfig/devconfig.mak @@ -0,0 +1,45 @@ +# Device type (HS/GP) +DEVICE_TYPE?=GP + +# Path to the signing tools, keys etc +SIGNING_TOOL_PATH=$(MCU_PLUS_SDK_PATH)/tools/boot/signing + +# Path to the keys +ROM_DEGENERATE_KEY:=$(SIGNING_TOOL_PATH)/rom_degenerateKey.pem +ifeq ($(DEVICE),am263x) + CUST_MPK=$(SIGNING_TOOL_PATH)/mcu_custMpk.pem +else ifeq ($(DEVICE),am273x) + CUST_MPK=$(SIGNING_TOOL_PATH)/mcu_custMpk.pem +else ifeq ($(DEVICE),awr294x) + CUST_MPK=$(SIGNING_TOOL_PATH)/mcu_custMpk.pem +else + CUST_MPK=$(SIGNING_TOOL_PATH)/custMpk_am64x_am243x.pem + CUST_MEK=$(SIGNING_TOOL_PATH)/custMek_am64x_am243x.txt +endif + +# Encryption option for application (yes/no) +ENC_ENABLED?=no + +# Encryption option for SBL (yes/no) +ENC_SBL_ENABLED?=yes + +# Debug Enable (yes/no) +DBG_ENABLED?=no + +# Debug control with TIFS (yes/no) +DEBUG_TIFS?=yes + +# Debug options for HS (DBG_PERM_DISABLE / DBG_SOC_DEFAULT / DBG_PUBLIC_ENABLE / DBG_FULL_ENABLE) +# This option is valid only if DEBUG_TIFS is false +DEBUG_OPTION?=DBG_SOC_DEFAULT + +# Generic macros to be used depending on the device type +APP_SIGNING_KEY= +APP_ENCRYPTION_KEY= + +ifeq ($(DEVICE_TYPE),HS) + APP_SIGNING_KEY=$(CUST_MPK) + APP_ENCRYPTION_KEY=$(CUST_MEK) +else + APP_SIGNING_KEY=$(ROM_DEGENERATE_KEY) +endif diff --git a/docs/manifest.html b/docs/manifest.html new file mode 100644 index 0000000..c5ec7e5 --- /dev/null +++ b/docs/manifest.html @@ -0,0 +1,671 @@ + + + + + + + + + + + Manifest File + + + + + +
+
+ +
+
+
+
+
+ +

+Industrial Communications Open Source SDK Manifest +

+ +

+2023-15-05 +

+ +

+Manifest ID - SRAS00009864 +

+ +
+ +

Legend

+

(explanation of the fields in the Manifest Table below)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Software Name + +The name of the application or file +
+Version + +Version of the application or file +
+License Type + +Type of license(s) under which TI will be providing + +software to the licensee (e.g. BSD-3-Clause, GPL-2.0, TI TSPA License, TI + +Commercial License). The license could be under Commercial terms or Open Source. See Open Source Reference License Disclaimer in + +the Disclaimers Section. Whenever possible, TI will use an SPDX Short Identifier for an Open Source + +License. TI Commercial license terms are not usually included in the manifest and are conveyed through a variety + +of means such as a clickwrap license upon install, + +a signed license agreement and so forth. +
+Location + +The directory name and path on the media or a specific file where the Software is located. Typically fully qualified path names + +are not used and instead the relevant top level directory of the application is given. + +A notation often used in the manifests is [as installed]/directory/*. Note that the asterisk implies that all + +files under that directory are licensed as the License Type field denotes. Any exceptions to this will + +generally be denoted as [as installed]/directory/* except as noted below which means as shown in subsequent rows of + +the manifest. +
+Delivered As + +This field will either be “Source”, “Binary” or “Source + +and Binary” and is the primary form the content of the Software is delivered + +in. If the Software is delivered in an archive format, this field + +applies to the contents of the archive. If the word Limited is used + +with Source, as in “Limited Source” or “Limited Source and Binary” then + +only portions of the Source for the application are provided. +
+Modified by TI + +This field will either be “Yes” or “No”. A “Yes” means + +TI has made changes to the Software. A “No” means TI has not made any + +changes. Note: This field is not applicable for Software “Obtained + +from” TI. +
+Obtained from + +This field specifies from where or from whom TI obtained + +the Software. It may be a URL to an Open Source site, a 3rd + +party licensor, or TI. See Links Disclaimer in the Disclaimers + +Section. +
+ +
+ +

Disclaimers

+ +

Export Control Classification Number (ECCN)

+ +

Any use of ECCNs listed in the Manifest is at the user’s risk + +and without recourse to TI. Your + +company, as the exporter of record, is responsible for determining the + +correct classification of any item at + +the time of export. Any export classification by TI of Software is for + +TI’s internal use only and shall not be construed as a representation + +or warranty + +regarding the proper export classification for such Software or whether + +an export + +license or other documentation is required for exporting such Software

+ +

Links in the Manifest

+ +

Any + +links appearing on this Manifest + +(for example in the “Obtained from” field) were verified at the time + +the Manifest was created. TI makes no guarantee that any listed links + +will + +remain active in the future.

+ +

Open Source License References

+ +

Your company is responsible for confirming the + +applicable license terms for any open source Software + +listed in this Manifest that was not “Obtained from” TI. Any open + +source license + +specified in this Manifest for Software that was + +not “Obtained from” TI is for TI’s internal use only and shall not be + +construed as a representation or warranty regarding the proper open + +source license terms + +for such Software.

+ + +

Export Information

+ +

ECCN for Software included in this release:

+Publicly Available + +
+ + + + + + + +

+ Industrial Communications Open Source SDK Manifest Table +

+ +

+ See the Legend above for a description of these columns. +

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Software NameVersionLicense TypeDelivered AsModified by TI
+ Industrial Communications SDK + + 09.00.00 + + BSD-3-Clause + + Source and Binary + + N/A + Location + [as installed]/* +
Obtained from + Texas Instruments +
+ ICSS Firmware for EtherCAT Slave + + 6.5.x + + TI Text File + + Binary as a C array in header file + + N/A + Location + [as_installed]/source/industrial_comms/ethercat_slave/icss_fwhal/firmware/* +
Obtained from + Texas Instruments +
+ ICSS Firmware for EthernetIP Adapter + + 5.2.x + + TI Text File + + Binary as a C array in header file + + N/A + Location + [as_installed]/source/industrial_comms/ethernetip_adapter/icss_fwhal/firmware/* +
Obtained from + Texas Instruments +
+ ICSS Firmware for Profinet Device + + 0.15.x + + TI Text File + + Binary as a C array in header file + + N/A + Location + [as_installed]/source/industrial_comms/profinet_device/icss_fwhal/firmware/* +
Obtained from + Texas Instruments +
+ ICSS Firmware for HSR-PRP + + 2.20.x + + TI Text File + + Binary as a C array in header file + + N/A + Location + [as_installed]/source/industrial_comms/hsr_prp/icss_fwhal/firmware/* +
Obtained from + Texas Instruments +
+ EtherCAT Slave Examples + + 1.12.x + + BSD-3-Clause + + Source + + No + Location + [as_installed]/examples/industrial_comms/ethercat_slave_demo/* +
Obtained from + KUNBUS GmbH +
+ EtherNet/IP Adapter Examples + + 3.2.x + + BSD-3-Clause + + Source + + No + Location + [as_installed]/examples/industrial_comms/ethernetip_adapter_demo/* +
Obtained from + KUNBUS GmbH +
+ IO-Link Master Example + + 1.9.x + + BSD-3-Clause + + Source + + No + Location + [as_installed]/examples/industrial_comms/iolink_master_demo/* +
Obtained from + KUNBUS GmbH +
+ EtherCAT-IOLink Gateway Examples + + 2.2.x + + BSD-3-Clause + + Source + + No + Location + [as_installed]/examples/industrial_comms/ethercat_iolink_gateway_demo/* +
Obtained from + KUNBUS GmbH +
+ EtherCAT Slave Stack Headers + + 1.12.x + + BSD-3-Clause + + Source + + No + Location + [as_installed]/source/industrial_comms/ethercat_slave/stack/* +
Obtained from + KUNBUS GmbH +
+ EtherNet/IP Adapter Stack Headers + + 3.2.x + + BSD-3-Clause + + Source + + No + Location + [as_installed]/source/industrial_comms/ethernetip_adapter/stack/*.h +
Obtained from + KUNBUS GmbH +
+ IO-Link Stack Headers + + 1.9.x + + BSD-3-Clause + + Source + + No + Location + [as_installed]/source/industrial_comms/iolink/*.h +
Obtained from + KUNBUS GmbH +
+ EtherCAT-IOLink Gateway Stack Headers + + 2.2.x + + BSD-3-Clause + + Source + + No + Location + [as_installed]/source/industrial_comms/ethercat_iolink_gateway/*.h +
Obtained from + KUNBUS GmbH +
+ +

+

+

+ + +

+ +

Credits

+ + + +
+ +

Licenses

+
+

+ Industrial Communications Open Source SDK Licenses +


+
Industrial Communications SDK (BSD-3-Clause License)
-------------------------------
/*
* Copyright (C) 2022 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/


ICSS Firmware (TI TEXT FILE License)
------------------------------------------------------------------
Copyright (C) 2017-2022 Texas Instruments Incorporated

All rights reserved not granted herein.

Limited License.

Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive license under copyrights and patents it now or hereafter owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") this software subject to the terms herein. With respect to the foregoing patent license, such license is granted solely to the extent that any such patent is necessary to Utilize the software alone. The patent license shall not apply to any combinations which include this software, other than combinations with devices manufactured by or for TI ("TI Devices"). No hardware patent is licensed hereunder.

Redistributions must preserve existing copyright notices and reproduce this license (including the above copyright notice and the disclaimer and (if applicable) source code license limitations below) in the documentation and/or other materials provided with the distribution

Redistribution and use in binary form, without modification, are permitted provided that the following conditions are met:

* No reverse engineering, decompilation, or disassembly of this software is permitted with respect to any software provided in binary form.

* any redistribution and use are licensed by TI for use only with TI Devices.

* Nothing shall obligate TI to provide you with source code for the software licensed and provided to you in object code.

If software source code is provided to you, modification and redistribution of the source code are permitted provided that the following conditions are met:

* any redistribution and use of the source code, including any resulting derivative works, are licensed by TI for use only with TI Devices.

* any redistribution and use of any object code compiled from the source code and any resulting derivative works, are licensed by TI for use only with TI Devices.

Neither the name of Texas Instruments Incorporated nor the names of its suppliers may be used to endorse or promote products derived from this software without specific prior written permission.

DISCLAIMER.

THIS SOFTWARE IS PROVIDED BY TI AND TI"S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND TI"S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

KUNBUS Sources (BSD-3-Clause License)
-------------------------------------
/*
* Copyright (c) 2020, Kunbus GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

+
+ + +
+ +
+

TI is a global semiconductor design and manufacturing company. Innovate + + with 100,000+ analog ICs and embedded processors, along with software, tools + + and the industry's largest sales/support staff.

+
+ + diff --git a/examples/motor_control/endat_diagnostic/endat_diagnostic.c b/examples/motor_control/endat_diagnostic/endat_diagnostic.c new file mode 100644 index 0000000..b601ef9 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/endat_diagnostic.c @@ -0,0 +1,2091 @@ +/* + * Copyright (C) 2021-23 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include "ti_drivers_open_close.h" +#include "ti_board_open_close.h" +#include +#if PRU_ICSSGx_PRU_SLICE +#define PRUICSS_PRUx PRUICSS_PRU1 +#define PRUICSS_TXPRUx PRUICSS_TX_PRU1 +#define PRUICSS_RTUPRUx PRUICSS_RTU_PRU1 +#else +#define PRUICSS_PRUx PRUICSS_PRU0 +#define PRUICSS_TXPRUx PRUICSS_TX_PRU0 +#define PRUICSS_RTUPRUx PRUICSS_RTU_PRU0 +#endif +#define PRUICSS_SLICEx PRU_ICSSGx_PRU_SLICE + +#if CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_SINGLE_PRU +#include +#endif + +#if (CONFIG_ENDAT0_CHANNEL0) && (CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_MULTI_PRU) +#include +#endif + +#if (CONFIG_ENDAT0_CHANNEL1) && (CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_MULTI_PRU) +#include +#endif + +#if (CONFIG_ENDAT0_CHANNEL2) && (CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_MULTI_PRU) +#include +#endif + +#if CONFIG_ENDAT0_MODE == ENDAT_MODE_SINGLE_CHANNEL_SINGLE_PRU +#include +#endif + + + +#define WAIT_5_SECOND (5000) +#define TASK_STACK_SIZE (4096) +#define TASK_PRIORITY (6) + +#define ENDAT_RX_SAMPLE_SIZE 7 +#define ENDAT_RX_SESQUI_DIV (1 << 15) + +#define MRS_POS_VAL2_WORD1 0x42 +#define MRS_POS_VAL2_WORD2 0x43 +#define MRS_POS_VAL2_WORD3 0x44 + + +static union endat_format_data gEndat_format_data_mtrctrl[3]; +static uint32_t gEndat_mtrctrl_crc_err[3]; +static uint32_t gEndat_2_2_crc_position_err_cnt[3]; +static uint32_t gEndat_2_2_crc_addinfo1_err_cnt[3]; +static uint64_t gEndat_2_2_pos_val2[3]; +static int32_t gEndat_2_2_loop_mrs; +static void (*endat_fn_position_loop)(unsigned int); + +uint32_t gTaskFxnStack[TASK_STACK_SIZE/sizeof(uint32_t)] __attribute__((aligned(32))); +TaskP_Object gTaskObject; + +#define VALID_HOST_CMD(x) ((x == 100) || ((x) == 101) || ((x) == 102) || ((x) == 103) || ((x) == 104) || ((x) == 105) || \ + ((x) == 106) || ((x) == 107) || ((x) == 108) || ((x) == 109) || ((x) == 110)) + +#define HAVE_COMMAND_SUPPLEMENT(x) (((x) == 2) || ((x) == 3) || ((x) == 4) || ((x) == 7) || \ + ((x) == 9) || ((x) == 10) || ((x) == 11) || ((x) == 13) || ((x) == 14) || \ + ((x) == 100) || ((x) == 101) || ((x)== 103) || ((x) == 105) || ((x) == 106) || ((x) == 107) || ((x) == 108) || ((x) == 109)) + +#define ENDAT_INPUT_CLOCK_UART_FREQUENCY 192000000 +/* use uart clock only to start with */ +#define ENDAT_INPUT_CLOCK_FREQUENCY ENDAT_INPUT_CLOCK_UART_FREQUENCY + +#define ENDAT_POSITION_LOOP_STOP 0 +#define ENDAT_POSITION_LOOP_START 1 + +union position +{ + float angle; + uint64_t length; +}; + +struct endat_priv *priv; + +#define PRUSS_PRU1_CTRL_CTPPR1 (CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE + 0x2C) + +#define ENDAT_MULTI_CH0 (1 << 0) +#define ENDAT_MULTI_CH1 (1 << 1) +#define ENDAT_MULTI_CH2 (1 << 2) +static uint32_t gEndat_prop_delay[3]; +static uint32_t gEndat_prop_delay_max; +static uint8_t gEndat_is_multi_ch; +static uint8_t gEndat_multi_ch_mask; +static uint8_t gEndat_is_load_share_mode; +static char gUart_buffer[256]; + +/** \brief Global Structure pointer holding PRUSS1 memory Map. */ +PRUICSS_Handle gPruIcssXHandle; + +/* buffer to handle long long printf */ +char gPrintf_dump_buffer[21]; + +/* This function is used to convert uint64_t + * variable tp a string as printf doesn't support + * printing 64-bit variables + */ +char * uint64_to_str (uint64_t x) +{ + char *b = gPrintf_dump_buffer + sizeof(gPrintf_dump_buffer); + *(--b) = '\0'; + do + { + *(--b) = '0' + (x % 10); + x /= 10; + } while (x); + + return b; +} + + +static void endat_pruss_init(void) +{ + gPruIcssXHandle = PRUICSS_open(CONFIG_PRU_ICSS0); + /* Configure g_mux_en to 1 in ICSSG_SA_MX_REG Register. */ + PRUICSS_setSaMuxMode(gPruIcssXHandle, PRUICSS_SA_MUX_MODE_SD_ENDAT); + + /* Set in constant table C30 to shared RAM 0x40300000 */ + PRUICSS_setConstantTblEntry(gPruIcssXHandle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C30, ((0x40300000 & 0x00FFFF00) >> 8)); + if(gEndat_is_load_share_mode) + { + PRUICSS_setConstantTblEntry(gPruIcssXHandle, PRUICSS_TXPRUx, PRUICSS_CONST_TBL_ENTRY_C30, ((0x40300000 & 0x00FFFF00) >> 8)); + PRUICSS_setConstantTblEntry(gPruIcssXHandle, PRUICSS_RTUPRUx, PRUICSS_CONST_TBL_ENTRY_C30, ((0x40300000 & 0x00FFFF00) >> 8)); + /*Set in constant table C29 for tx pru*/ + PRUICSS_setConstantTblEntry(gPruIcssXHandle, PRUICSS_TXPRUx, PRUICSS_CONST_TBL_ENTRY_C28, 0x258); + + } + /* clear ICSS0 PRU1 data RAM */ + PRUICSS_initMemory(gPruIcssXHandle, PRUICSS_DATARAM(PRUICSS_SLICEx)); + if(gEndat_is_load_share_mode) + { + PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_RTUPRUx); + PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_TXPRUx); + } + PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_PRUx); + +} + +void endat_pre_init(void) +{ + endat_pruss_init(); +} + +uint32_t endat_pruss_load_run_fw(struct endat_priv *priv) +{ + + uint32_t status = SystemP_FAILURE; + +#if CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_MULTI_PRU /*enable loadshare mode*/ + +#if(CONFIG_ENDAT0_CHANNEL0) + + status = PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_RTUPRUx); + DebugP_assert(SystemP_SUCCESS == status); + status=PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_RTU_PRU(PRUICSS_SLICEx), + 0, (uint32_t *) EnDatFirmwareMultiMakeRTU, + sizeof(EnDatFirmwareMultiMakeRTU)); + DebugP_assert(0 != status); + status = PRUICSS_resetCore(gPruIcssXHandle, PRUICSS_RTUPRUx); + DebugP_assert(SystemP_SUCCESS == status); + status = PRUICSS_enableCore(gPruIcssXHandle, PRUICSS_RTUPRUx); + DebugP_assert(SystemP_SUCCESS == status); + +#endif + +#if(CONFIG_ENDAT0_CHANNEL1) + + status=PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_PRUx ); + DebugP_assert(SystemP_SUCCESS == status); + status = PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_PRU(PRUICSS_SLICEx), + 0, (uint32_t *) EnDatFirmwareMultiMakePRU, + sizeof(EnDatFirmwareMultiMakePRU)); + DebugP_assert(0 != status); + status = PRUICSS_resetCore(gPruIcssXHandle, PRUICSS_PRUx); + DebugP_assert(SystemP_SUCCESS == status); + status = PRUICSS_enableCore(gPruIcssXHandle, PRUICSS_PRUx); + DebugP_assert(SystemP_SUCCESS == status); + +#endif + +#if(CONFIG_ENDAT0_CHANNEL2) + + status = PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_TXPRUx); + DebugP_assert(SystemP_SUCCESS == status); + status = PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_TX_PRU(PRUICSS_SLICEx), + 0, (uint32_t *) EnDatFirmwareMultiMakeTXPRU, + sizeof(EnDatFirmwareMultiMakeTXPRU)); + DebugP_assert(0 != status); + status = PRUICSS_resetCore(gPruIcssXHandle, PRUICSS_TXPRUx); + DebugP_assert(SystemP_SUCCESS == status); + status = PRUICSS_enableCore(gPruIcssXHandle, PRUICSS_TXPRUx); + DebugP_assert(SystemP_SUCCESS == status); + +#endif + status=endat_wait_initialization(priv, WAIT_5_SECOND, gEndat_multi_ch_mask); + + +#else + + status = PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_PRUx); + DebugP_assert(SystemP_SUCCESS == status); + +#if(CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_SINGLE_PRU) + + status = PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_PRU(PRUICSS_SLICEx), + 0, (uint32_t *) EnDatFirmwareMulti, + sizeof(EnDatFirmwareMulti)); + +#else + + status = PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_PRU(PRUICSS_SLICEx), + 0, (uint32_t *) EnDatFirmware, + sizeof(EnDatFirmware)); +#endif + DebugP_assert(0 != status); + + status = PRUICSS_resetCore(gPruIcssXHandle, PRUICSS_PRUx); + DebugP_assert(SystemP_SUCCESS == status); + + /*Run firmware */ + status = PRUICSS_enableCore(gPruIcssXHandle, PRUICSS_PRUx); + DebugP_assert(SystemP_SUCCESS == status); + + /* check initialization ack from firmware, with a timeout of 5 second */ + status = endat_wait_initialization(priv, WAIT_5_SECOND, gEndat_multi_ch_mask); +#endif + + return status; +} + +uint64_t endat_get_fw_version(void) +{ +#if CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_SINGLE_PRU + return *((unsigned long *)EnDatFirmwareMulti + 2); +#endif + +#if (CONFIG_ENDAT0_CHANNEL0) && (CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_MULTI_PRU) + return *((unsigned long *)EnDatFirmwareMultiMakeRTU + 2); +#endif + +#if (CONFIG_ENDAT0_CHANNEL1) && (CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_MULTI_PRU) + return *((unsigned long *)EnDatFirmwareMultiMakePRU + 2); +#endif + +#if (CONFIG_ENDAT0_CHANNEL2) && (CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_MULTI_PRU) + return *((unsigned long *)EnDatFirmwareMultiMakeTXPRU + 2); +#endif + +#if CONFIG_ENDAT0_MODE == ENDAT_MODE_SINGLE_CHANNEL_SINGLE_PRU + return *((unsigned long *)EnDatFirmware + 2); +#endif + +} + +static void endat_print_menu(void) +{ + DebugP_log("\r|------------------------------------------------------------------------------|\n"); + DebugP_log("\r| Select value for the encoder command from following |\n"); + DebugP_log("\r|------------------------------------------------------------------------------|\n"); + DebugP_log("\r| 1 : Encoder send position values |\n"); + DebugP_log("\r| 2 : Selection of memory area |\n"); + DebugP_log("\r| 3 : Encoder receive parameter |\n"); + DebugP_log("\r| 4 : Encoder send parameter |\n"); + DebugP_log("\r| 5 : Encoder receive reset |\n"); + DebugP_log("\r| 6 : Encoder send test values |\n"); + DebugP_log("\r| 7 : Encoder receive test command |\n"); + + if(priv->cmd_set_2_2) + { + DebugP_log("\r| 8 : Encoder to send position + AI(s) |\n"); + DebugP_log("\r| 9 : Encoder to send position + AI(s) and receive selection of memory area |\n"); + DebugP_log("\r| 10: Encoder to send position + AI(s) and receive parameter |\n"); + DebugP_log("\r| 11: Encoder to send position + AI(s) and send parameter |\n"); + DebugP_log("\r| 12: Encoder to send position + AI(s) and receive error reset |\n"); + DebugP_log("\r| 13: Encoder to send position + AI(s) and receive test command |\n"); + DebugP_log("\r| 14: Encoder receive communication command |\n"); + } + + DebugP_log("\r| |\n"); + DebugP_log("\r|100: Configure clock |\n"); + DebugP_log("\r|101: Simulate motor control 2.1 position loop |\n"); + DebugP_log("\r|102: Toggle raw data display |\n"); + DebugP_log("\r|103: Configure tST delay |\n"); + + if((!gEndat_is_multi_ch) && (!gEndat_is_load_share_mode)) + { + DebugP_log("\r|104: Start continuous mode |\n"); + } + + DebugP_log("\r|105: Configure rx arm counter (account tD) |\n"); + DebugP_log("\r|106: Configure rx clock disable time (for tD) |\n"); + + if(priv->cmd_set_2_2) + { + DebugP_log("\r|107: Simulate motor control 2.2 position loop %s |\n", + gEndat_is_multi_ch || gEndat_is_load_share_mode ? " " : "(safety)"); + } + + DebugP_log("\r|108: Configure propagation delay (tD) |\n"); + + if((gEndat_is_multi_ch) || (gEndat_is_load_share_mode)) + { + DebugP_log("\r|109: Configure wire delay |\n"); + } + + DebugP_log("\r|110: Recovery Time (RT) |\n"); + + DebugP_log("\r|------------------------------------------------------------------------------|\n\r|\n"); + DebugP_log("\r| enter value: "); +} + +static inline int32_t endat_get_command(void) +{ + volatile int32_t cmd = -1; + + + if(DebugP_scanf("%d", &cmd) < 0) + { + cmd = -1; + } + + if(VALID_2_1_CMD(cmd) || (priv->cmd_set_2_2 && VALID_2_2_CMD(cmd)) + || VALID_HOST_CMD(cmd)) + { + return cmd; + } + + DebugP_log("\r| WARNING: invalid command, EnDat 2.1 send position values command will be sent\n"); + return 1; +} + +static void endat_recvd_print(int32_t cmd, struct endat_priv *priv, + union endat_format_data *u, int32_t crc) +{ + uint32_t addinfo, byte1; + uint64_t max = pow(2, priv->single_turn_res); + union position position; + + /* this would give wrong values if cmd is not position related, but that is okay as then this value won't be used */ + if(priv->type == rotary) + { + position.angle = ((float) u->position_addinfo.position.position) / + (float)max * (float)360; + } + + else + { + position.length = u->position_addinfo.position.position * priv->step; + } + + + DebugP_log("\r|\n\r|\n"); + + switch(cmd) + { + case 2: + case 3: + case 5: + case 7: + case 14: + DebugP_log("\r| crc: %s\n", crc & 0x1 ? "success" : "failure"); + DebugP_logInfo("| crc: %x\n", u->addr_params.crc); + break; + + case 4: + DebugP_log("\r| parameter: 0x%x, crc: %s\n", u->addr_params.params, + crc & 0x1 ? "success" : "failure"); + DebugP_logInfo("\r| crc: %x\n", u->addr_params.crc); + break; + + case 6: + DebugP_log("\r| test value: 0x%02x%08x, crc: %s\n", + (uint32_t)((u->test.value & 0xFF00000000) >> 32), + (uint32_t)(u->test.value & 0xFFFFFFFF), crc & 0x1 ? "success" : "failure"); + DebugP_logInfo("\r| crc: %x\n", u->test.crc); + break; + + case 1: + if(priv->multi_turn_res) + { + sprintf(gUart_buffer, "\r| position: %.12f, revolution: %s, ", + position.angle, uint64_to_str(u->position_addinfo.position.revolution)); + } + else + { + if(priv->type == rotary) + { + sprintf(gUart_buffer, "\r| position: %.12f ", position.angle); + } + else + { + sprintf(gUart_buffer, "\r| position: %s ", uint64_to_str(position.length)); + } + } + + DebugP_log("%s", gUart_buffer); + + DebugP_log("f1: %x, crc: %s\n", u->position_addinfo.position.f1, + crc & 0x1 ? "success" : "failure"); + + DebugP_logInfo("| crc: %x\n", u->position_addinfo.position.crc); + break; + + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + if(priv->multi_turn_res) + { + sprintf(gUart_buffer, "\r| position: %.12f, revolution: %s, ", + position.angle, uint64_to_str(u->position_addinfo.position.revolution)); + } + else + { + if(priv->type == rotary) + { + sprintf(gUart_buffer, "\r| position: %.12f ", position.angle); + } + else + { + sprintf(gUart_buffer, "\r| position: %s ", uint64_to_str(position.length)); + } + } + + DebugP_log("%s", gUart_buffer); + + DebugP_log("f1/f2: %x/%x, crc: %s\n", u->position_addinfo.position.f1, + u->position_addinfo.position.f2, + crc & 0x1 ? "success" : "failure"); + + DebugP_logInfo("| crc: %x\n", u->position_addinfo.position.crc); + + if(priv->flags.info1) + { + addinfo = u->position_addinfo.addinfo1.addinfo; + byte1 = (addinfo >> 16) & ((1 << 8) - 1); + + DebugP_log("\r|\n| WRN: %x RM: %x Busy: %x I4-I0: %x\n", + (byte1 & ENDAT_STATUS_WARN_MASK) >> ENDAT_STATUS_WARN_SHIFT, + (byte1 & ENDAT_STATUS_RM_MASK) >> ENDAT_STATUS_RM_SHIFT, + (byte1 & ENDAT_STATUS_BUSY_MASK) >> ENDAT_STATUS_BUSY_SHIFT, + byte1 & ENDAT_INFORMATION_MASK); + DebugP_log("\r|\n| Additional Information 1: 0x%x, crc: %s\n", addinfo, + crc & 0x2 ? "success" : "failure"); + DebugP_logInfo("| addinfo1 crc: %x\n", + u->position_addinfo.addinfo1.crc); + } + + if(priv->flags.info2) + { + addinfo = u->position_addinfo.addinfo2.addinfo; + byte1 = (addinfo >> 16) & ((1 << 8) - 1); + + DebugP_log("\r|\n| Additional Information 2: 0x%x, crc: %s\n", addinfo, + crc & 0x4 ? "success" : "failure"); + DebugP_logInfo("| addinfo2 crc: %x\n", + u->position_addinfo.addinfo2.crc); + } + + break; + + default: + DebugP_log("\r|\n| ERROR: print requested for invalid command\n"); + break; + } + + DebugP_log("\r|\n\r|\n"); +} + +static void endat_display_raw_data(int32_t cmd, struct endat_priv *priv) +{ + int32_t ch = priv->channel; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + switch(cmd) + { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + DebugP_log("\r|\n| raw data: %x %x %x %x\n|\n", + pruss_xchg->ch[ch].pos_word0, pruss_xchg->ch[ch].pos_word1, + pruss_xchg->ch[ch].pos_word2, pruss_xchg->ch[ch].pos_word3); + break; + + default: + DebugP_log("\r|\n| Nothing raw to display - this is not a valid command\n|\n"); + break; + } +} + +/* + * check 2.2 command case with 2.2 capability in encoder, can live w/o as endat_get_command + * will handle and it is assumed that this function will be called after endat_get_command + */ +static int32_t endat_get_command_supplement(int32_t cmd, + struct cmd_supplement *cmd_supplement) +{ + /* erase previous cmd supplements */ + memset(cmd_supplement, 0, sizeof(*cmd_supplement)); + + switch(cmd) + { + case 2: + DebugP_log("\r| enter MRS code (hex value): "); + + if(DebugP_scanf("%x\n", &cmd_supplement->address) < 0) + { + DebugP_log("\r| ERROR: invalid MRS code\n|\n|\n|\n"); + return -EINVAL; + } + + if(cmd_supplement->address > 0xFF) + { + DebugP_log("\r| ERROR: invalid MRS code\n|\n|\n|\n"); + return -EINVAL; + } + + break; + + case 9: + DebugP_log("\r| enter MRS code (hex value): "); + + if(DebugP_scanf("%x\n", &cmd_supplement->address) < 0) + { + DebugP_log("\r| ERROR: invalid MRS code\n|\n|\n|\n"); + return -EINVAL; + } + + if(cmd_supplement->address > 0xFF) + { + DebugP_log("\r| ERROR: invalid MRS code\n|\n|\n|\n"); + return -EINVAL; + } + + if(cmd_supplement->address == ENDAT_SECTION2_MEMORY) + { + DebugP_log("\r| enter block address (hex value): "); + + if(DebugP_scanf("%x\n", &cmd_supplement->block) < 0) + { + DebugP_log("\r| ERROR: invalid block address\n|\n|\n|\n"); + return -EINVAL; + } + + /* better compare it with number of blocks information available in eeprom */ + if(cmd_supplement->block > 0xFF) + { + DebugP_log("\r| ERROR: invalid block address\n|\n|\n|\n"); + return -EINVAL; + } + + cmd_supplement->has_block_address = TRUE; + } + + break; + + case 3: + case 10: + DebugP_log("\r| enter parameter address (hex value): "); + + if(DebugP_scanf("%x\n", &cmd_supplement->address) < 0) + { + DebugP_log("\r| ERROR: invalid parameter address\n|\n|\n|\n"); + return -EINVAL; + } + + if(cmd_supplement->address > 0xFF) + { + DebugP_log("\r| ERROR: invalid parameter address\n|\n|\n|\n"); + return -EINVAL; + } + + DebugP_log("\r| enter parameter (hex value): "); + + if(DebugP_scanf("%x\n", &cmd_supplement->data) < 0) + { + DebugP_log("\r| ERROR: invalid parameter\n|\n|\n|\n"); + return -EINVAL; + } + + if(cmd_supplement->data > 0xFFFF) + { + DebugP_log("\r| ERROR: invalid parameter\n|\n|\n|\n"); + return -EINVAL; + } + + break; + + case 4: + case 11: + DebugP_log("\r| enter parameter address (hex value): "); + + if(DebugP_scanf("%x\n", &cmd_supplement->address) < 0) + { + DebugP_log("\r| ERROR: invalid parameter address\n|\n|\n|\n"); + return -EINVAL; + } + + if(cmd_supplement->address > 0xFF) + { + DebugP_log("\r| ERROR: invalid parameter address\n|\n|\n|\n"); + return -EINVAL; + } + + break; + + case 7: + case 13: + DebugP_log("\r| enter port address (hex value):"); + + if(DebugP_scanf("%x\n", &cmd_supplement->address) < 0) + { + DebugP_log("\r| ERROR: invalid port address\n|\n|\n|\n"); + return -EINVAL; + } + + if(cmd_supplement->address > 0xFF) + { + DebugP_log("| ERROR: invalid port address\n|\n|\n|\n"); + return -EINVAL; + } + + break; + + case 14: + DebugP_log("\r| enter encoder address (hex value): "); + + if(DebugP_scanf("%x\n", &cmd_supplement->address) < 0) + { + DebugP_log("\r| ERROR: invalid encoder address\n|\n|\n|\n"); + return -EINVAL; + } + + if(cmd_supplement->address > 0xFF) + { + DebugP_log("\r| ERROR: invalid encoder address\n|\n|\n|\n"); + return -EINVAL; + } + + DebugP_log("\r| enter instruction (hex value): "); + + if(DebugP_scanf("%x\n", &cmd_supplement->data) < 0) + { + DebugP_log("\r| ERROR: invalid instruction\n|\n|\n|\n"); + return -EINVAL; + } + + if(cmd_supplement->data > 0xFFFF) + { + DebugP_log("\r| ERROR: invalid instruction\n|\n|\n|\n"); + return -EINVAL; + } + + break; + + case 100: + case 101: + case 107: + DebugP_log("\r| enter frequency in Hz: "); + + if(DebugP_scanf("%u\n", &cmd_supplement->frequency) < 0) + { + DebugP_log("\r| ERROR: invalid frequency\n|\n|\n|\n"); + return -EINVAL; + } + + break; + + case 103: + DebugP_log("\r| enter tST delay counter value in ns: "); + + if(DebugP_scanf("%u\n", &cmd_supplement->frequency) < 0) + { + DebugP_log("\r| ERROR: invalid value\n|\n|\n|\n"); + return -EINVAL; + } + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + DebugP_log("\r| Select Channel: "); + if(DebugP_scanf("%u\n", &priv->channel) < 0) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + + if(!((gEndat_multi_ch_mask) & (1<channel))) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + } + break; + + case 105: + DebugP_log("\r| enter rx arm counter in ns: "); + + if(DebugP_scanf("%u\n", &cmd_supplement->frequency) < 0) + { + DebugP_log("\r| ERROR: invalid value\n|\n|\n|\n"); + return -EINVAL; + } + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + DebugP_log("\r| Select Channel: "); + if(DebugP_scanf("%u\n", &priv->channel) < 0) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + + if(!((gEndat_multi_ch_mask) & (1<channel))) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + } + break; + + + case 106: + DebugP_log("\r| enter rx clock disable time (for tD) in ns: "); + + if(DebugP_scanf("%u\n", &cmd_supplement->frequency) < 0) + { + DebugP_log("\r| ERROR: invalid value\n|\n|\n|\n"); + return -EINVAL; + } + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + DebugP_log("\r| Select Channel: "); + if(DebugP_scanf("%u\n", &priv->channel) < 0) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + + if(!((gEndat_multi_ch_mask) & (1<channel))) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + } + break; + + case 108: + DebugP_log("\r| enter propagation delay in ns: "); + + if(DebugP_scanf("%u\n", &cmd_supplement->frequency) < 0) + { + DebugP_log("\r| ERROR: invalid value\n|\n|\n|\n"); + return -EINVAL; + } + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + DebugP_log("\r| Select Channel: "); + if(DebugP_scanf("%u\n", &priv->channel) < 0) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + + if(!((gEndat_multi_ch_mask) & (1<channel))) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + } + + break; + + case 109: + DebugP_log("\r| enter channel number: "); + + if(DebugP_scanf("%x\n", &cmd_supplement->address) < 0) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + + if(!(gEndat_multi_ch_mask & 1 << cmd_supplement->address)) + { + DebugP_log("\r| ERROR: invalid channel\n|\n|\n|\n"); + return -EINVAL; + } + + DebugP_log("\r| enter wire delay in ns: "); + + if(DebugP_scanf("%u\n", &cmd_supplement->frequency) < 0) + { + DebugP_log("\r| ERROR: invalid value\n|\n|\n|\n"); + return -EINVAL; + } + + break; + + default: + cmd = -EINVAL; + DebugP_log("\r| ERROR: no command data required for the command\n"); + break; + } + + return cmd; +} + +static int32_t endat_handle_user(struct cmd_supplement *cmd_supplement) +{ + int32_t cmd; + + endat_print_menu(); + cmd = endat_get_command(); + + if(HAVE_COMMAND_SUPPLEMENT(cmd)) + { + return endat_get_command_supplement(cmd, cmd_supplement); + } + + return cmd; +} + +static int32_t endat_calc_clock(uint32_t freq, struct endat_clk_cfg *clk_cfg) +{ + uint32_t ns; + + if(freq > 16000000 || (freq > 12000000 && freq < 16000000)) + { + DebugP_log("\r| ERROR: frequency above 16MHz, between 12 & 16MHz not allowed\n|\n|\n"); + return -1; + } + + if((freq != 16000000) && (ENDAT_INPUT_CLOCK_FREQUENCY % (freq * 8))) + DebugP_log("\r| WARNING: exact clock divider is not possible, frequencies set would be tx: %u\trx: %u\n", + ENDAT_INPUT_CLOCK_FREQUENCY / (ENDAT_INPUT_CLOCK_FREQUENCY / freq), + ENDAT_INPUT_CLOCK_FREQUENCY / (ENDAT_INPUT_CLOCK_FREQUENCY / (freq * 8))); + + ns = 2 * 1000000000 / freq; /* rx arm >= 2 clock */ + + /* should be divisible by 5 */ + if(ns % 5) + { + ns /= 5, ns += 1, ns *= 5; + } + + clk_cfg->tx_div = ENDAT_INPUT_CLOCK_FREQUENCY / freq - 1; + clk_cfg->rx_div = ENDAT_INPUT_CLOCK_FREQUENCY / (freq * 8) - 1; + clk_cfg->rx_en_cnt = ns; + clk_cfg->rx_div_attr = ENDAT_RX_SAMPLE_SIZE; + + if(freq == 16000000) + { + clk_cfg->rx_div_attr |= ENDAT_RX_SESQUI_DIV; + } + + DebugP_logInfo("\r| clock config values - tx_div: %u\trx_div: %u\trx_en_cnt: %u\trx_div_attr: %x\n", + clk_cfg->tx_div, clk_cfg->rx_div, clk_cfg->rx_en_cnt, clk_cfg->rx_div_attr); + + return 0; +} + +static uint32_t endat_do_sanity_tst_delay(uint32_t delay) +{ + /* (unsigned short)~0 is also a multiple of 5 */ + if(delay > (unsigned short)~0) + { + DebugP_log("\r| ERROR: delay greater than %uns, enter lesser value\n|\n|\n", + (unsigned short)~0); + return delay; + } + + if(delay % 5) + { + delay += 5, delay /= 5, delay *= 5; + DebugP_log("\r| WARNING: delay not multiple of 5ns, rounding to %uns\n|\n|\n", + delay); + } + + return delay; +} + +static int32_t endat_position_loop_status; + +/* position period in microsecond */ +static int32_t endat_calc_position_period(uint32_t freq) +{ + /* 16KHz limitation due to the timer */ + if(freq > 16000) + { + DebugP_log("\r| ERROR: enter frequency less than or equal 16KHz\n|\n|\n"); + return -1; + } + else if((gEndat_is_multi_ch || gEndat_is_load_share_mode)&& freq > 8000) + { + DebugP_log("\r| ERROR: enter frequency less than or equal 8KHz in multi channel configuration\n|\n|\n"); + return -1; + } + + return 1000000 / freq; +} + +static void endat_position_loop_decide_termination(void *args) +{ + char c; + + while(1) + { + DebugP_scanf("%c", &c); + endat_position_loop_status = ENDAT_POSITION_LOOP_STOP; + break; + } + TaskP_exit(); +} + +void endat_process_position_command(uint32_t a0) +{ + uint32_t crc; + + endat_command_process(priv, 1, NULL); + endat_recvd_process(priv, 1, &gEndat_format_data_mtrctrl[a0]); + crc = endat_recvd_validate(priv, 1, &gEndat_format_data_mtrctrl[a0]); + + if(!(crc & 0x1)) + { + gEndat_mtrctrl_crc_err[a0]++; + } +} + +uint16_t _endat_process_2_2_position_command(int32_t cmd, + struct cmd_supplement *cmd_supplement, uint32_t a0) +{ + uint32_t crc; + + endat_command_process(priv, cmd, cmd_supplement); + endat_recvd_process(priv, cmd, &gEndat_format_data_mtrctrl[a0]); + crc = endat_recvd_validate(priv, cmd, &gEndat_format_data_mtrctrl[a0]); + + if(!(crc & 0x1)) + { + gEndat_2_2_crc_position_err_cnt[a0]++; + } + + if(priv->flags.info1 && !(crc & 0x2)) + { + gEndat_2_2_crc_addinfo1_err_cnt[a0]++; + } + + endat_addinfo_track(priv, cmd, cmd_supplement); + + return gEndat_format_data_mtrctrl[a0].position_addinfo.addinfo1.addinfo & 0xFFFF; +} + +void endat_process_2_2_position_command(uint32_t a0) +{ + uint32_t cmd; + struct cmd_supplement cmd_supplement; + uint16_t pos_word; + + if(((!gEndat_is_multi_ch || !gEndat_is_load_share_mode) && priv->has_safety) ) + { + cmd = 9, cmd_supplement.address = gEndat_2_2_loop_mrs; + } + else + { + cmd = 8; + } + + pos_word = _endat_process_2_2_position_command(cmd, &cmd_supplement, a0); + + if((gEndat_is_multi_ch) || (!priv->has_safety) || (gEndat_is_load_share_mode)) + { + return; + } + + /* WORD3 in addinfo1 */ + if(gEndat_2_2_loop_mrs == MRS_POS_VAL2_WORD1) + { + gEndat_2_2_pos_val2[a0] &= 0xFFFF0000FFFFFFFF; + gEndat_2_2_pos_val2[a0] |= (unsigned long long)pos_word << 32; + gEndat_2_2_loop_mrs = MRS_POS_VAL2_WORD2; + /* WORD1 in addinfo1 */ + } + else if(gEndat_2_2_loop_mrs == MRS_POS_VAL2_WORD2) + { + gEndat_2_2_pos_val2[a0] &= 0xFFFFFFFFFFFF0000; + gEndat_2_2_pos_val2[a0] |= pos_word; + gEndat_2_2_loop_mrs = MRS_POS_VAL2_WORD3; + /* WORD2 in addinfo1 */ + } + else if(gEndat_2_2_loop_mrs == MRS_POS_VAL2_WORD3) + { + gEndat_2_2_pos_val2[a0] &= 0xFFFFFFFF0000FFFF; + gEndat_2_2_pos_val2[a0] |= (unsigned long long)pos_word << 16; + gEndat_2_2_loop_mrs = MRS_POS_VAL2_WORD1; + } +} + +void endat_position_loop(uint32_t a0) +{ + if(endat_fn_position_loop != NULL) + { + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + + for(j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + endat_multi_channel_set_cur(priv, j); + endat_fn_position_loop(j); + } + } + } + else + { + endat_fn_position_loop(0); + } + } +} + +static int32_t endat_loop_task_create(void) +{ + uint32_t status; + TaskP_Params taskParams; + + TaskP_Params_init(&taskParams); + taskParams.name = "endat_position_loop_decide_termination"; + taskParams.stackSize = TASK_STACK_SIZE; + taskParams.stack = (uint8_t *)gTaskFxnStack; + taskParams.priority = TASK_PRIORITY; + taskParams.taskMain = (TaskP_FxnMain)endat_position_loop_decide_termination; + status = TaskP_construct(&gTaskObject, &taskParams); + + if(status != SystemP_SUCCESS) + { + DebugP_log("\rTask2 creation failed\n"); + } + + return status ; +} + +static void endat_loop_timer_create(int32_t us) +{ + TimerP_Params timerParams; + + TimerP_Params_init(&timerParams); + timerParams.inputPreScaler = CONFIG_TIMER0_INPUT_PRE_SCALER; + timerParams.inputClkHz = CONFIG_TIMER0_INPUT_CLK_HZ; + timerParams.periodInUsec = us; + timerParams.oneshotMode = 0; + timerParams.enableOverflowInt = 1; + TimerP_setup(gTimerBaseAddr[CONFIG_TIMER0], &timerParams); + + return ; +} + +static int32_t endat_get_position_loop_chars(struct endat_priv *priv, + int32_t continuous, int32_t is_2_2) +{ + int32_t i; + + if(priv->multi_turn_res) + { + i = 34; + } + else + { + i = 16; + } + + if(!continuous) + { + i += 12; + } + + i += 4; + + if(!continuous && is_2_2) + { + i += 4; + } + + return i; +} + +static void endat_print_position_loop(struct endat_priv *priv, int32_t continuous, + int32_t is_2_2, int32_t ch) +{ + uint64_t max = pow(2, priv->single_turn_res); + union position position; + + if(priv->type == rotary) + { + position.angle = ((float) + gEndat_format_data_mtrctrl[ch].position_addinfo.position.position) / + (float)max * (float)360; + } + else + { + position.length = + gEndat_format_data_mtrctrl[ch].position_addinfo.position.position * priv->step; + } + + /* max value is 2x48, has 15 digits, so 16 is safe */ + if(priv->multi_turn_res) + { + sprintf(gUart_buffer, "%16.12f, %16s", position.angle, + uint64_to_str(gEndat_format_data_mtrctrl[ch].position_addinfo.position.revolution)); + } + else + { + if(priv->type == rotary) + { + sprintf(gUart_buffer, "%16.12f", position.angle); + } + else + { + sprintf(gUart_buffer, "%16s", uint64_to_str(position.length)); + } + } + + DebugP_log("\r%s", gUart_buffer); + + if(!continuous) + { + if(is_2_2) + { + DebugP_log(", %10u", gEndat_2_2_crc_position_err_cnt[ch]); + } + else + { + DebugP_log(", %10u", gEndat_mtrctrl_crc_err[ch]); + } + } + + DebugP_log(",%3u", + gEndat_format_data_mtrctrl[ch].position_addinfo.position.f1); + + if(!continuous && is_2_2) + { + DebugP_log(",%3u", + gEndat_format_data_mtrctrl[ch].position_addinfo.position.f2); + } +} + +static void endat_print_position_loop_channel_info(struct endat_priv *priv, + int32_t is_2_2) +{ + int32_t k, j, i = endat_get_position_loop_chars(priv, 0, is_2_2); + + /* add 3 extra to account for spacing b/n channels */ + i += 3; + /* find mid point */ + i /= 2; + /* account for "CHANNEL x" display */ + i -= 4; + + for(k = i, j = 0; j < 3; j++, k = i) + if(gEndat_multi_ch_mask & 1 << j) + { + while(k--) + { + DebugP_log("%c", ' '); + } + + DebugP_log("\rCHANNEL %d", j); + + /* 3 - extra to account for spacing b/n channels, 9 - "CHANNEL x" length */ + k = endat_get_position_loop_chars(priv, 0, is_2_2) + 3 - i - 9; + + while(k--) + { + DebugP_log("%c", ' '); + } + } +} + +static void endat_handle_prop_delay(struct endat_priv *priv, + uint16_t prop_delay) +{ + if(prop_delay > priv->rx_en_cnt) + { + uint16_t dis = (prop_delay - priv->rx_en_cnt) * 2 / priv->rx_en_cnt; + + endat_config_rx_arm_cnt(priv, prop_delay); + /* propagation delay - 2T */ + endat_config_rx_clock_disable(priv, dis); + } + else + { + endat_config_rx_arm_cnt(priv, priv->rx_en_cnt); + endat_config_rx_clock_disable(priv, 0); + } +} + +static void endat_process_host_command(int32_t cmd, + struct cmd_supplement *cmd_supplement, struct endat_priv *priv) +{ + struct endat_clk_cfg clk_cfg; + static int32_t timer_init; + + /* clock configuration */ + if(cmd == 100) + { + if(endat_calc_clock(cmd_supplement->frequency, &clk_cfg) < 0) + { + return; + } + + endat_config_clock(priv, &clk_cfg); + + priv->rx_en_cnt = clk_cfg.rx_en_cnt; + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + uint16_t d; + + for(j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + endat_multi_channel_set_cur(priv, j); + endat_handle_prop_delay(priv, gEndat_prop_delay[priv->channel]); + d = gEndat_prop_delay_max - gEndat_prop_delay[j]; + endat_config_wire_delay(priv, d); + } + } + } + else + { + endat_handle_prop_delay(priv, gEndat_prop_delay[priv->channel]); + } + + /* set tST to 2us if frequency > 1MHz, else turn it off */ + if(cmd_supplement->frequency >= 1000000) + { + cmd_supplement->frequency = 2000; + } + else + { + cmd_supplement->frequency = 0; + } + + /* control loop */ + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + for(j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + endat_multi_channel_set_cur(priv, j); + endat_process_host_command(103, cmd_supplement, priv); + } + } + } + else + { + endat_process_host_command(103, cmd_supplement, priv); + } + + } + else if(cmd == 101) + { + int32_t us = endat_calc_position_period(cmd_supplement->frequency); + + if(us < 0) + { + return; + } + + if(endat_loop_task_create() != SystemP_SUCCESS) + { + DebugP_log("\r| ERROR: OS not allowing position loop as related Task creation failed\n|\n|\n"); + DebugP_log("\rTask_create() failed!\n"); + return; + } + + endat_fn_position_loop = endat_process_position_command; + + if(!timer_init) + { + endat_loop_timer_create(us); + timer_init = 1; + } + + TimerP_start(gTimerBaseAddr[CONFIG_TIMER0]); + endat_position_loop_status = ENDAT_POSITION_LOOP_START; + + if(priv->multi_turn_res) + { + DebugP_log("\r|\r\n| press enter to stop the position display|\n"); + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + + DebugP_log("\r|\n\r|"); + endat_print_position_loop_channel_info(priv, 0); + DebugP_log("\r\n|\n"); + + for(j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + DebugP_log("| "); + DebugP_log(" position, revolution, crc errors, f1\n"); + DebugP_log(" "); + } + } + DebugP_log("\n"); + } + else + { + DebugP_log("\r| position, revolution, crc errors, f1|\r\n "); + } + } + else + { + DebugP_log("|\n| press enter to stop the position display\n|\n"); + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + + DebugP_log("\r|\n\r|"); + endat_print_position_loop_channel_info(priv, 0); + DebugP_log("\r\n|\n"); + + for(j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + DebugP_log("| "); + DebugP_log(" position, crc errors, f1\n"); + DebugP_log(" "); + } + } + DebugP_log("\n"); + } + else + { + DebugP_log("| position, crc errors, f1\n| "); + } + } + + while(1) + if(endat_position_loop_status == ENDAT_POSITION_LOOP_STOP) + { + TimerP_stop(gTimerBaseAddr[CONFIG_TIMER0]); + return; + } + else + { + int32_t i; + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + + for(i = 0, j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + endat_multi_channel_set_cur(priv, j); + i += endat_get_position_loop_chars(priv, 0, 0); + DebugP_log("| "); + endat_print_position_loop(priv, 0, 0, j); + DebugP_log(" "); + DebugP_log("\n"); + i += 3; + } + } + } + else + { + i = endat_get_position_loop_chars(priv, 0, 0); + endat_print_position_loop(priv, 0, 0, 0); + } + + /* increase sleep value if glitches in display to be prevented (and would result in slower position display freq) */ + ClockP_usleep(500); + + while(i--) + { + DebugP_log("%c", 8); + } + } + } + + else if(cmd == 102) + { + priv->raw_data ^= 1; + } + else if(cmd == 103) + { + uint32_t delay; + + delay = endat_do_sanity_tst_delay(cmd_supplement->frequency); + + if(delay <= (uint16_t)~0) + { + endat_config_tst_delay(priv, (uint16_t) delay); + } + } + else if(cmd == 104) + { + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + DebugP_log("\r| ERROR: Multi channel configuration does not support continuous clock mode\r\n|\r\n|\n"); + return; + } + + if(endat_loop_task_create() != SystemP_SUCCESS) + { + DebugP_log("\r| ERROR: OS not allowing continuous mode as related Task creation failed\r\n|\r\n|\n"); + DebugP_log("Task_create() failed!\n"); + return; + } + + endat_start_continuous_mode(priv); + endat_position_loop_status = ENDAT_POSITION_LOOP_START; + + if(priv->multi_turn_res) + { + DebugP_log("\r|\n\r| press enter to stop the continuous mode\r\n|\r\n| position, revolution, f1\r\n| "); + } + else + { + DebugP_log("\r|\n\r| press enter to stop the continuous mode\r\n|\r\n| position, f1\r\n| "); + } + + while(1) + if(endat_position_loop_status == ENDAT_POSITION_LOOP_STOP) + { + endat_stop_continuous_mode(priv); + return; + } + else + { + int i; + + endat_recvd_process(priv, 1, &gEndat_format_data_mtrctrl[0]); + + i = endat_get_position_loop_chars(priv, 1, 0); + endat_print_position_loop(priv, 1, 0, 0); + + /* increase sleep value if glitches in display to be prevented (and would result in slower position display freq) */ + ClockP_usleep(100); + + while(i--) + { + DebugP_log("%c", 8); + } + } + } + else if(cmd == 105) + { + uint32_t val; + + /* reuse tST delay sanity check */ + val = endat_do_sanity_tst_delay(cmd_supplement->frequency); + + if(val <= (uint16_t)~0) + { + endat_config_rx_arm_cnt(priv, (uint16_t)val); + } + } + else if(cmd == 106) + { + uint16_t dis = cmd_supplement->frequency * 2 / priv->rx_en_cnt; + + endat_config_rx_clock_disable(priv, dis); + } + else if(cmd == 108) + { + /* reuse tST delay sanity check */ + uint32_t val = endat_do_sanity_tst_delay(cmd_supplement->frequency); + + if(val > (uint16_t)~0) + { + return; + } + endat_handle_prop_delay(priv, (uint16_t)val); + + } + else if(cmd == 109) + { + /* reuse tST delay sanity check */ + uint32_t val = endat_do_sanity_tst_delay(cmd_supplement->frequency); + + endat_multi_channel_set_cur(priv, cmd_supplement->address); + endat_config_wire_delay(priv, val); + } + else if(cmd == 107) + { + int32_t us = endat_calc_position_period(cmd_supplement->frequency); + + if(us < 0) + { + return; + } + if(endat_loop_task_create() != SystemP_SUCCESS) + { + DebugP_log("\r| ERROR: OS not allowing position loop as related Task creation failed\n|\n|\n"); + DebugP_log("\rTask_create() failed!\n"); + return; + } + + endat_fn_position_loop = endat_process_2_2_position_command; + + if(!timer_init) + { + endat_loop_timer_create(us); + timer_init = 1; + } + + /* reset additional info's if present */ + endat_command_process(priv, 5, NULL); + endat_addinfo_track(priv, 5, NULL); + + gEndat_2_2_loop_mrs = MRS_POS_VAL2_WORD1; + + TimerP_start(gTimerBaseAddr[CONFIG_TIMER0]); + endat_position_loop_status = ENDAT_POSITION_LOOP_START; + + /* so that proper position value 2 is displayed from the begining */ + ClockP_usleep(us * 3); + + if((!gEndat_is_multi_ch && !priv->has_safety) || (!gEndat_is_load_share_mode && !priv->has_safety)) + { + DebugP_log("\r|\n| encoder does not support safety, position value 2 would not be displayed\n|\n"); + } + + DebugP_log("\r|\n\r| press enter to stop the position display\n\r|\n"); + + if(priv->multi_turn_res) + { + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + + DebugP_log("\r|\n\r|"); + endat_print_position_loop_channel_info(priv, 1); + DebugP_log("\n\r|\n"); + + for(j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + DebugP_log("\r| "); + DebugP_log(" position, revolution, crc errors, f1, f2"); + DebugP_log(" "); + } + } + DebugP_log("\r\n"); + } + else + { + DebugP_log("\r| position, revolution, crc errors, f1, f2"); + + if(priv->has_safety) + { + DebugP_log(", position(2), revolution(2), crc errors(2)"); + } + DebugP_log("\r\n| "); + } + } + else + { + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + + DebugP_log("\r|\n\r|"); + endat_print_position_loop_channel_info(priv, 1); + DebugP_log("\r\n|\r\n"); + + for(j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + DebugP_log("| "); + DebugP_log(" position, crc errors, f1"); + DebugP_log(" "); + } + } + DebugP_log("\n"); + } + else + { + DebugP_log("| position, crc errors, f1, f2 "); + + if(priv->has_safety) + { + DebugP_log(", position(2), crc errors(2)"); + } + DebugP_log("\r\n| "); + } + } + + while(1) + if(endat_position_loop_status == ENDAT_POSITION_LOOP_STOP) + { + TimerP_stop(gTimerBaseAddr[CONFIG_TIMER0]); + + /* reset additional info1 */ + endat_command_process(priv, 5, NULL); + endat_addinfo_track(priv, 5, NULL); + return; + } + else + { + int32_t i; + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + + for(i = 0, j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + endat_multi_channel_set_cur(priv, j); + i += endat_get_position_loop_chars(priv, 0, 1); + DebugP_log("| "); + endat_print_position_loop(priv, 0, 1, j); + DebugP_log(" "); + DebugP_log("\n"); + i += 3; + } + } + } + else + { + i = endat_get_position_loop_chars(priv, 0, 1); + endat_print_position_loop(priv, 0, 1, 0); + } + + if((!gEndat_is_multi_ch && priv->has_safety) || (!gEndat_is_load_share_mode && priv->has_safety)) + { + uint64_t multi_turn, single_turn; + union position position2; + uint64_t max = pow(2, priv->single_turn_res); + + multi_turn = ENDAT_GET_POS_MULTI_TURN(gEndat_2_2_pos_val2[0], priv); + single_turn = ENDAT_GET_POS_SINGLE_TURN(gEndat_2_2_pos_val2[0], priv); + + if(priv->type == rotary) + { + position2.angle = (float)single_turn / (float)max * (float)360; + } + else + { + position2.length = single_turn * priv->step; + } + + DebugP_log(", "); + + if(priv->multi_turn_res) + { + sprintf(gUart_buffer, "%16.12f, %16s", position2.angle, uint64_to_str(multi_turn)); + } + else + { + if(priv->type == rotary) + { + sprintf(gUart_buffer, "%16.12f", position2.angle); + } + else + { + sprintf(gUart_buffer, "%16s", uint64_to_str(position2.length)); + } + } + + DebugP_log("%s", gUart_buffer); + + DebugP_log(", %10u", gEndat_2_2_crc_addinfo1_err_cnt[0]); + } + + /* increase sleep value if glitches in display to be prevented (and would result in slower position display freq) */ + ClockP_usleep(100); + + if((!gEndat_is_multi_ch && priv->has_safety) || (!gEndat_is_load_share_mode && priv->has_safety)) + { + if(priv->multi_turn_res) + { + i += 2 + 46 + 3; + } + else + { + i += 2 + 28 + 3; + } + } + + while(i--) + { + DebugP_log("%c", 8); + } + } + } + else if(cmd == 110) + { + uint32_t recovery_time; + if(gEndat_is_multi_ch||gEndat_is_load_share_mode) + { + int32_t j; + for( j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + endat_multi_channel_set_cur(priv, j); + DebugP_log("channel: %d",priv->channel); + DebugP_log("\t"); + recovery_time = endat_get_recovery_time(priv); + DebugP_log("Recovery Time: %d ns", recovery_time); + DebugP_log("\n"); + } + } + } + else + { + recovery_time = endat_get_recovery_time(priv); + DebugP_log("Recovery Time: %d ns", recovery_time); + DebugP_log("\n"); + } + + } + else + { + DebugP_log("\r| ERROR: non host command being requested to be handled as host command\n|\n|\n"); + } +} + +static void endat_handle_rx(struct endat_priv *priv, int32_t cmd) +{ + uint32_t crc; + union endat_format_data endat_format_data; + + if(priv->raw_data) + { + endat_display_raw_data(cmd, priv); + } + + endat_recvd_process(priv, cmd, &endat_format_data); + crc = endat_recvd_validate(priv, cmd, &endat_format_data); + endat_recvd_print(cmd, priv, &endat_format_data, crc); + + return; +} + +static void endat_print_encoder_info(struct endat_priv *priv) +{ + DebugP_log("EnDat 2.%d %s encoder\tID: %u %s\tSN: %c %u %c\n\n", + priv->cmd_set_2_2 ? 2 : 1, + (priv->type == rotary) ? "rotary" : "linear", + priv->id.binary, (char *)&priv->id.ascii, + (char)priv->sn.ascii_msb, priv->sn.binary, (char)priv->sn.ascii_lsb); + DebugP_log("\rPosition: %d bits ", priv->pos_res); + + if(priv->type == rotary) + { + DebugP_log("(singleturn: %d, multiturn: %d) ", priv->single_turn_res, + priv->multi_turn_res); + } + + DebugP_log("[resolution: %d %s]", priv->step, + priv->type == rotary ? "M/rev" : "nm"); + DebugP_log("\r\n\nPropagation delay: %dns", + gEndat_prop_delay[priv->channel]); + DebugP_log("\n\n\n"); +} + +void endat_main(void *args) +{ + int32_t i; + struct cmd_supplement cmd_supplement; + + uint64_t icssgclk; + + void *pruss_cfg; + + /* Open drivers to open the UART driver for console */ + Drivers_open(); + Board_driversOpen(); + +/*C16 pin High for Enabling ch0 in booster pack */ +#if (CONFIG_ENDAT0_BOOSTER_PACK) + GPIO_setDirMode(ENC1_EN_BASE_ADDR, ENC1_EN_PIN, ENC1_EN_DIR); + GPIO_pinWriteHigh(ENC1_EN_BASE_ADDR, ENC1_EN_PIN); +#endif + + + i = endat_get_fw_version(); + + DebugP_log("\n\n\n"); + DebugP_log("EnDat firmware \t: %x.%x.%x (%s)\n\n", (i >> 24) & 0x7F, + (i >> 16) & 0xFF, i & 0xFFFF, i & (1 << 31) ? "internal" : "release"); + + gEndat_is_multi_ch = CONFIG_ENDAT0_MODE & 1; + gEndat_is_load_share_mode = CONFIG_ENDAT0_MODE & 2; + endat_pre_init(); + + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + + gEndat_multi_ch_mask=(CONFIG_ENDAT0_CHANNEL0<<0|CONFIG_ENDAT0_CHANNEL1<<1|CONFIG_ENDAT0_CHANNEL2<<2); + + DebugP_log("\r\nchannels %s %s %s selected\n", + gEndat_multi_ch_mask & ENDAT_MULTI_CH0 ? "0" : "", + gEndat_multi_ch_mask & ENDAT_MULTI_CH1 ? "1" : "", + gEndat_multi_ch_mask & ENDAT_MULTI_CH2 ? "2" : ""); + + if(!gEndat_multi_ch_mask) + { + DebugP_log("\r\nERROR: please select channels to be used in multi channel configuration -\n\n"); + DebugP_log("\rexit %s as no channel selected in multichannel configuration\n", + __func__); + return; + } + } + else + { + + i = CONFIG_ENDAT0_CHANNEL0 & 0; + + i += CONFIG_ENDAT0_CHANNEL1; + + i += CONFIG_ENDAT0_CHANNEL2<<1; + + if(i < 0 || i > 2) + { + DebugP_log("\r\nWARNING: invalid channel selected, defaulting to Channel 0\n"); + i = 0; + } + } + + DebugP_log("\r\n\n"); + + pruss_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcssXHandle->hwAttrs))->cfgRegBase); + + #if PRU_ICSSGx_PRU_SLICE + priv = endat_init((struct endat_pruss_xchg *)((PRUICSS_HwAttrs *)( + gPruIcssXHandle->hwAttrs))->pru1DramBase, pruss_cfg, PRUICSS_SLICEx); + + #else + priv = endat_init((struct endat_pruss_xchg *)((PRUICSS_HwAttrs *)( + gPruIcssXHandle->hwAttrs))->pru0DramBase, pruss_cfg, PRUICSS_SLICEx); + #endif + + + + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + endat_config_multi_channel_mask(priv, gEndat_multi_ch_mask, gEndat_is_load_share_mode); + } + else + { + endat_config_channel(priv, i); + } + + endat_config_host_trigger(priv); + /* Read the ICSSG configured clock frequency. */ + if(gPruIcssXHandle->hwAttrs->instance) + { + SOC_moduleGetClockFrequency(TISCI_DEV_PRU_ICSSG1, TISCI_DEV_PRU_ICSSG1_CORE_CLK, &icssgclk); + } + else + { + SOC_moduleGetClockFrequency(TISCI_DEV_PRU_ICSSG0, TISCI_DEV_PRU_ICSSG0_CORE_CLK, &icssgclk); + } + + /* Configure Delays based on the ICSSG frequency*/ + /* Count = ((required delay * icssgclk)/1000) */ + priv->pruss_xchg->endat_delay_125ns = ((icssgclk*125)/1000000000); + priv->pruss_xchg->endat_delay_51us = ((icssgclk*51)/1000000 ); + priv->pruss_xchg->endat_delay_5us = ((icssgclk*5)/1000000); + priv->pruss_xchg->endat_delay_1ms = ((icssgclk/1000) * 1); + priv->pruss_xchg->endat_delay_2ms = ((icssgclk/1000) * 2); + priv->pruss_xchg->endat_delay_12ms = ((icssgclk/1000) * 12); + priv->pruss_xchg->endat_delay_50ms = ((icssgclk/1000) * 50); + priv->pruss_xchg->endat_delay_380ms = ((icssgclk/1000) * 380); + priv->pruss_xchg->endat_delay_900ms = ((icssgclk/1000) * 900); + priv->pruss_xchg->icssg_clk = icssgclk; + + + i = endat_pruss_load_run_fw(priv); + + if(i < 0) + { + DebugP_log("\rERROR: EnDat initialization failed -\n\n"); + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + uint8_t tmp; + + tmp = endat_multi_channel_detected(priv) & gEndat_multi_ch_mask; + tmp ^= gEndat_multi_ch_mask; + DebugP_log("\r\tunable to detect encoder in channel %s %s %s\n", + tmp & ENDAT_MULTI_CH0 ? "0" : "", + tmp & ENDAT_MULTI_CH1 ? "1" : "", + tmp & ENDAT_MULTI_CH2 ? "2" : ""); + } + else + { + DebugP_log("\r\tcheck whether encoder is connected and ensure proper connections\n"); + } + + DebugP_log("\rexit %s due to failed firmware initialization\n", __func__); + return; + } + + /* read encoder info at low frequency so that cable length won't affect */ + cmd_supplement.frequency = 200 * 1000; + endat_process_host_command(100, &cmd_supplement, priv); + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + + for(j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + endat_multi_channel_set_cur(priv, j); + if(endat_get_encoder_info(priv) < 0) + { + DebugP_log("\rEnDat initialization channel %d failed\n", j); + DebugP_log("\rexit %s due to failed initialization\n", __func__); + return; + } + /*convert cnt to time in ns ((cnt*1000000000)/icssgclk) before use*/ + gEndat_prop_delay[priv->channel] = endat_get_prop_delay(priv)*((float)(1000000000)/icssgclk); + DebugP_log("\n\t\t\t\tCHANNEL %d\n\n", j); + endat_print_encoder_info(priv); + } + } + + gEndat_prop_delay_max = gEndat_prop_delay[0] > gEndat_prop_delay[1] ? + gEndat_prop_delay[0] : gEndat_prop_delay[1]; + gEndat_prop_delay_max = gEndat_prop_delay_max > gEndat_prop_delay[2] ? + gEndat_prop_delay_max : gEndat_prop_delay[2]; + + } + else + { + if(endat_get_encoder_info(priv) < 0) + { + DebugP_log("\rEnDat initialization failed\n"); + DebugP_log("\rexit %s due to failed initialization\n", __func__); + return; + } + /*convert cnt to time in ns ((cnt*1000000000)/icssgclk) before use*/ + gEndat_prop_delay[priv->channel] = endat_get_prop_delay(priv)*((float)(1000000000)/icssgclk); + + endat_print_encoder_info(priv); + } + + /* default frequency - 8MHz for 2.2 encoders, 1MHz for 2.1 encoders */ + if(priv->cmd_set_2_2) + { + cmd_supplement.frequency = 8 * 1000 * 1000; + } + else + { + cmd_supplement.frequency = 1 * 1000 * 1000; + } + + endat_process_host_command(100, &cmd_supplement, priv); + + + while(1) + { + int32_t cmd; + + cmd = endat_handle_user(&cmd_supplement); + + if(cmd < 0) + { + continue; + } + + if(VALID_HOST_CMD(cmd)) + { + endat_process_host_command(cmd, &cmd_supplement, priv); + DebugP_log("\r|\n\r|\n"); + continue; + } + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + continue; + } + + if(gEndat_is_multi_ch || gEndat_is_load_share_mode) + { + int32_t j; + + DebugP_log("\r|\n"); + + for(j = 0; j < 3; j++) + { + if(gEndat_multi_ch_mask & 1 << j) + { + endat_multi_channel_set_cur(priv, j); + DebugP_log("\r|\n|\t\t\t\tCHANNEL %d\n", j); + endat_handle_rx(priv, cmd); + } + } + } + else + { + endat_handle_rx(priv, cmd); + } + + /* this cannot be done except as last in loop; additional info becomes applicable from next command onwards only */ + endat_addinfo_track(priv, cmd, &cmd_supplement); + } + + Board_driversClose(); + Drivers_close(); +} + diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project.js b/examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project_am243x.js b/examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project_am243x.js new file mode 100644 index 0000000..8a207fe --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project_am243x.js @@ -0,0 +1,123 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "endat_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM243X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_ENDAT"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am243x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am243x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "endat_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "endat_diagnostic_multi_channel_load_share"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project_am64x.js b/examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project_am64x.js new file mode 100644 index 0000000..1e64258 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/.project/project_am64x.js @@ -0,0 +1,123 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "endat_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM64X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_ENDAT"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am64x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am64x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "endat_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "endat_diagnostic_multi_channel_load_share"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..7a4a599 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,102 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const timer = scripting.addModule("/kernel/dpl/timer", {}, false); +const timer1 = timer.addInstance(); +const endat = scripting.addModule("/motor_control/position_sense/endat", {}, false); +const endat1 = endat.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +debug_log.enableCssLog = false; +debug_log.enableUartLog = true; +debug_log.uartLog.$name = "CONFIG_UART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv72.size = 15; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.size = 15; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.size = 21; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.size = 28; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.size = 31; +mpu_armv76.baseAddr = 0x80000000; + +timer1.$name = "CONFIG_TIMER0"; +timer1.timerCallback = "endat_position_loop"; +timer1.intrPriority = 0; +timer1.TIMER.$assign = "DMTIMER0"; + +endat1.$name = "CONFIG_ENDAT0"; +endat1.Channel_1 = true; +endat1.Channel_2 = true; +endat1.Multi_Channel_Load_Share = true; +endat1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +pruicss1.$name = "CONFIG_PRU_ICSS0"; +endat1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.$suggestSolution = "USART0"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +endat1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +endat1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +endat1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +endat1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +endat1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +endat1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +endat1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +endat1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +endat1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +endat1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +endat1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +endat1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..068a9ba --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void endat_main(void *args); + +void freertos_main(void *args) +{ + endat_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..52012a1 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..69640f4 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..e00081c --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,308 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=endat_diagnostic_multi_channel_load_share.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=endat_diagnostic_multi_channel_load_share.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=endat_diagnostic_multi_channel_load_share.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=endat_diagnostic_multi_channel_load_share.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + endat_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang endat_diagnostic_multi_channel_load_share ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..f2e0ada --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..f741707 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,103 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const timer = scripting.addModule("/kernel/dpl/timer", {}, false); +const timer1 = timer.addInstance(); +const endat = scripting.addModule("/motor_control/position_sense/endat", {}, false); +const endat1 = endat.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +timer1.$name = "CONFIG_TIMER0"; +timer1.timerCallback = "endat_position_loop"; +timer1.intrPriority = 0; +timer1.TIMER.$assign = "DMTIMER0"; + +endat1.$name = "CONFIG_ENDAT0"; +endat1.Channel_2 = true; +endat1.Multi_Channel_Load_Share = true; +endat1.Channel_1 = true; +endat1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +pruicss1.$name = "CONFIG_PRU_ICSS0"; +endat1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +endat1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +endat1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +endat1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +endat1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +endat1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +endat1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +endat1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +endat1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +endat1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +endat1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +endat1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +endat1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..068a9ba --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void endat_main(void *args); + +void freertos_main(void *args) +{ + endat_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..e0e331b --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..c4848c3 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..8d80f8c --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,309 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=endat_diagnostic_multi_channel_load_share.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=endat_diagnostic_multi_channel_load_share.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=endat_diagnostic_multi_channel_load_share.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=endat_diagnostic_multi_channel_load_share.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=endat_diagnostic_multi_channel_load_share.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + endat_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM64X \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang endat_diagnostic_multi_channel_load_share ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM64x_beta --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..17e86fd --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,107 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..dcfe42c --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project.js b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project_am243x.js b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project_am243x.js new file mode 100644 index 0000000..f92977f --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project_am243x.js @@ -0,0 +1,123 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "endat_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM243X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_ENDAT"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am243x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am243x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "endat_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "endat_diagnostic_multi_channel_single_pru"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project_am64x.js b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project_am64x.js new file mode 100644 index 0000000..409a30b --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/.project/project_am64x.js @@ -0,0 +1,123 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "endat_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM64X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_ENDAT"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am64x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am64x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "endat_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "endat_diagnostic_multi_channel_single_pru"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..ecad04a --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,101 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const timer = scripting.addModule("/kernel/dpl/timer", {}, false); +const timer1 = timer.addInstance(); +const endat = scripting.addModule("/motor_control/position_sense/endat", {}, false); +const endat1 = endat.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +debug_log.enableCssLog = false; +debug_log.enableUartLog = true; +debug_log.uartLog.$name = "CONFIG_UART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv72.size = 15; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.size = 15; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.size = 21; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.size = 28; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.size = 31; +mpu_armv76.baseAddr = 0x80000000; + +timer1.$name = "CONFIG_TIMER0"; +timer1.timerCallback = "endat_position_loop"; +timer1.intrPriority = 0; +timer1.TIMER.$assign = "DMTIMER0"; + +endat1.$name = "CONFIG_ENDAT0"; +endat1.Channel_1 = true; +endat1.Channel_2 = true; +endat1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +pruicss1.$name = "CONFIG_PRU_ICSS0"; +endat1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.$suggestSolution = "USART0"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +endat1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +endat1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +endat1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +endat1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +endat1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +endat1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +endat1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +endat1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +endat1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +endat1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +endat1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +endat1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..068a9ba --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void endat_main(void *args); + +void freertos_main(void *args) +{ + endat_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..5a6b9c1 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..69640f4 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..36eed6d --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,308 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + endat_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang endat_diagnostic_multi_channel_single_pru ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..3d1016b --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..0ad8a5a --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,102 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const timer = scripting.addModule("/kernel/dpl/timer", {}, false); +const timer1 = timer.addInstance(); +const endat = scripting.addModule("/motor_control/position_sense/endat", {}, false); +const endat1 = endat.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +timer1.$name = "CONFIG_TIMER0"; +timer1.timerCallback = "endat_position_loop"; +timer1.intrPriority = 0; +timer1.TIMER.$assign = "DMTIMER0"; + +endat1.$name = "CONFIG_ENDAT0"; +endat1.Channel_2 = true; +endat1.Channel_1 = true; +endat1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +pruicss1.$name = "CONFIG_PRU_ICSS0"; +endat1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +endat1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +endat1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +endat1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +endat1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +endat1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +endat1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +endat1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +endat1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +endat1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +endat1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +endat1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +endat1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..068a9ba --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void endat_main(void *args); + +void freertos_main(void *args) +{ + endat_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..172889b --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..c4848c3 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..d319ce6 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,309 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=endat_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + endat_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM64X \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang endat_diagnostic_multi_channel_single_pru ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM64x_beta --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..17e86fd --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,107 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..55abff0 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/endat_diagnostic/single_channel/.project/project.js b/examples/motor_control/endat_diagnostic/single_channel/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/endat_diagnostic/single_channel/.project/project_am243x.js b/examples/motor_control/endat_diagnostic/single_channel/.project/project_am243x.js new file mode 100644 index 0000000..4cdbcdb --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/.project/project_am243x.js @@ -0,0 +1,125 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "endat_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM243X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_ENDAT"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am243x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am243x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "endat_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"}, + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-lp", os: "freertos"}, + +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "endat_diagnostic_single_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/endat_diagnostic/single_channel/.project/project_am64x.js b/examples/motor_control/endat_diagnostic/single_channel/.project/project_am64x.js new file mode 100644 index 0000000..e5ee867 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/.project/project_am64x.js @@ -0,0 +1,123 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "endat_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM64X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_ENDAT"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am64x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am64x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "endat_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "endat_diagnostic_single_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..99cf8b4 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,99 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const timer = scripting.addModule("/kernel/dpl/timer", {}, false); +const timer1 = timer.addInstance(); +const endat = scripting.addModule("/motor_control/position_sense/endat", {}, false); +const endat1 = endat.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +debug_log.enableCssLog = false; +debug_log.enableUartLog = true; +debug_log.uartLog.$name = "CONFIG_UART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv72.size = 15; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.size = 15; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.size = 21; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.size = 28; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.size = 31; +mpu_armv76.baseAddr = 0x80000000; + +timer1.$name = "CONFIG_TIMER0"; +timer1.timerCallback = "endat_position_loop"; +timer1.intrPriority = 0; +timer1.TIMER.$assign = "DMTIMER0"; + +endat1.$name = "CONFIG_ENDAT0"; +endat1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +pruicss1.$name = "CONFIG_PRU_ICSS0"; +endat1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.$suggestSolution = "USART0"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +endat1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +endat1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +endat1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +endat1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +endat1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +endat1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +endat1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +endat1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +endat1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +endat1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +endat1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +endat1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..068a9ba --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void endat_main(void *args); + +void freertos_main(void *args) +{ + endat_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..188f21c --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..69640f4 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..0158277 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,308 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=endat_diagnostic_single_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=endat_diagnostic_single_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=endat_diagnostic_single_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=endat_diagnostic_single_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=endat_diagnostic_single_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=endat_diagnostic_single_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=endat_diagnostic_single_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=endat_diagnostic_single_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=endat_diagnostic_single_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + endat_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang endat_diagnostic_single_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..6c5f70d --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..09a1fd4 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,98 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const timer = scripting.addModule("/kernel/dpl/timer", {}, false); +const timer1 = timer.addInstance(); +const endat = scripting.addModule("/motor_control/position_sense/endat", {}, false); +const endat1 = endat.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +timer1.$name = "CONFIG_TIMER0"; +timer1.intrPriority = 0; +timer1.timerCallback = "endat_position_loop"; +timer1.TIMER.$assign = "DMTIMER0"; + +endat1.$name = "CONFIG_ENDAT0"; +endat1.Booster_Pack = true; +endat1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; +endat1.PRU_ICSSG0_PRU.GPO2.$assign = "ball.M2"; +endat1.PRU_ICSSG0_PRU.GPO1.$assign = "ball.J2"; +endat1.PRU_ICSSG0_PRU.GPO0.$assign = "ball.L5"; +endat1.PRU_ICSSG0_PRU.GPI13.$assign = "ball.T4"; +endat1.PRU_ICSSG0_PRU.GPO5.$used = false; +endat1.PRU_ICSSG0_PRU.GPO4.$used = false; +endat1.PRU_ICSSG0_PRU.GPO3.$used = false; +endat1.PRU_ICSSG0_PRU.GPI14.$used = false; +endat1.PRU_ICSSG0_PRU.GPO8.$used = false; +endat1.PRU_ICSSG0_PRU.GPO12.$used = false; +endat1.PRU_ICSSG0_PRU.GPO6.$used = false; +endat1.PRU_ICSSG0_PRU.GPI11.$used = false; + +endat1.ENC1_EN = gpio1; +gpio1.$name = "ENC1_EN"; +gpio1.GPIO.$assign = "GPIO1"; +gpio1.GPIO.gpioPin.pu_pd = "pu"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "ball.C16"; + +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance({}, false); +pruicss1.$name = "CONFIG_PRU_ICSS0"; +endat1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +debug_log.uartLog.UART.RXD.$suggestSolution = "ball.B10"; +debug_log.uartLog.UART.TXD.$suggestSolution = "ball.B11"; diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..068a9ba --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void endat_main(void *args); + +void freertos_main(void *args) +{ + endat_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..6ceb15a --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..69640f4 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..8ecba4a --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,308 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=endat_diagnostic_single_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=endat_diagnostic_single_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=endat_diagnostic_single_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=endat_diagnostic_single_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=endat_diagnostic_single_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=endat_diagnostic_single_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=endat_diagnostic_single_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=endat_diagnostic_single_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=endat_diagnostic_single_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + endat_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_endat.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang endat_diagnostic_single_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALX_beta --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..3fc1c13 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..6ae47b6 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,100 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const timer = scripting.addModule("/kernel/dpl/timer", {}, false); +const timer1 = timer.addInstance(); +const endat = scripting.addModule("/motor_control/position_sense/endat", {}, false); +const endat1 = endat.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +timer1.$name = "CONFIG_TIMER0"; +timer1.timerCallback = "endat_position_loop"; +timer1.intrPriority = 0; +timer1.TIMER.$assign = "DMTIMER0"; + +endat1.$name = "CONFIG_ENDAT0"; +endat1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +pruicss1.$name = "CONFIG_PRU_ICSS0"; +endat1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +endat1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +endat1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +endat1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +endat1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +endat1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +endat1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +endat1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +endat1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +endat1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +endat1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +endat1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +endat1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..068a9ba --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void endat_main(void *args); + +void freertos_main(void *args) +{ + endat_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..5f17407 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..c4848c3 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..6fc1450 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,309 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=endat_diagnostic_single_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=endat_diagnostic_single_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=endat_diagnostic_single_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=endat_diagnostic_single_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=endat_diagnostic_single_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=endat_diagnostic_single_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=endat_diagnostic_single_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=endat_diagnostic_single_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=endat_diagnostic_single_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + endat_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM64X \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_endat.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang endat_diagnostic_single_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM64x_beta --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..17e86fd --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,107 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..a260784 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/hdsl_diagnostic/hdsl_diagnostic.c b/examples/motor_control/hdsl_diagnostic/hdsl_diagnostic.c new file mode 100644 index 0000000..8400551 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/hdsl_diagnostic.c @@ -0,0 +1,1244 @@ +/* + * Copyright (C) 2021-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "ti_drivers_config.h" +#include "ti_drivers_open_close.h" +#include "ti_board_open_close.h" + +#include "hdsl_diagnostic.h" +#include +#include + +#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) +#include +#include +/* Divide factor for normal clock (default value for 225 MHz=23) */ +#define DIV_FACTOR_NORMAL 23 +/* Divide factor for oversampled clock (default value for 225 MHz=2) */ +#define DIV_FACTOR_OVERSAMPLED 2 +#endif +#if(CONFIG_HDSL0_CHANNEL0 + CONFIG_HDSL0_CHANNEL1 >1) +#define MULTICHANNEL 1 +#endif +#if(CONFIG_HDSL0_CHANNEL0 + CONFIG_HDSL0_CHANNEL1 <=1) +#define MULTICHANNEL 0 +#endif + + +#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + +#if (MULTICHANNEL==0) +#include +#endif + +#if (MULTICHANNEL==1) +#include +#include +#endif + +/* Divide factor for normal clock (default value for 300 MHz=31) */ +#define DIV_FACTOR_NORMAL 31 +/* Divide factor for oversampled clock (default value for 300 MHz=3) */ +#define DIV_FACTOR_OVERSAMPLED 3 +#endif + +#ifdef HDSL_AM64xE1_TRANSCEIVER +#include +#endif + +#define PRUICSS_PRUx PRUICSS_PRU1 +/* Oversample rate 8*/ +#define OVERSAMPLE_RATE 7 + +#define HDSL_EN (0x1 << 26) +/* OCP as clock, div 32 */ +#define HDSL_TX_CFG (0x10 | (DIV_FACTOR_NORMAL << 16)) +/* OCP as clock, div 4, 8x OSR */ +#define HDSL_RX_CFG (0x10 | (DIV_FACTOR_OVERSAMPLED << 16) | OVERSAMPLE_RATE | 0x08) +#define CTR_EN (1 << 3) +#define MAX_WAIT 20000 + +/*Timeout in micorseconds for short message read/write*/ +#define SHORT_MSG_TIMEOUT (1000) + +/*Register Addresses for Short Messages (Parameter Channel)*/ + +#define ENCODER_STATUS0_REG_ADDRESS (0x40) +#define ENCODER_RSSI_REG_ADDRESS (0x7C) +#define ENCODER_PING_REG_ADDRESS (0x7F) + +extern PRUICSS_Config gPruicssConfig[2]; + +struct hdslvariables *hdslvariables; + +HwiP_Object gPRUHwiObject; +/** \brief Global Structure pointer holding PRUSS1 memory Map. */ +PRUICSS_Handle gPruIcss0Handle; +HDSL_Handle gHdslHandleCh0; +HDSL_Handle gHdslHandleCh1; +HDSL_Handle gHdslHandleCh2; +PRUICSS_IntcInitData gPruss0_intc_initdata = PRU_ICSS0_INTC_INITDATA; +PRUICSS_Handle gPruIcss1Handle; +PRUICSS_IntcInitData gPruss1_intc_initdata = PRU_ICSS1_INTC_INITDATA; + + +static char gUart_buffer[256]; +static void *gPru_cfg; +void *gPru_dramx; + +int get_pos=1; + +uint32_t gMulti_turn, gRes; +uint64_t gMask; + +uint8_t gPc_data; + +uint8_t gPc_addrh, gPc_addrl, gPc_offh, gPc_offl, gPc_buf0, gPc_buf1, gPc_buf2, gPc_buf3, gPc_buf4, gPc_buf5, gPc_buf6, gPc_buf7; + + +#ifdef HDSL_AM64xE1_TRANSCEIVER +static TCA6424_Config gTCA6424_Config; +#endif + +void sync_calculation(void) +{ + uint8_t ES; + uint16_t wait_before_start; + uint32_t counter, period, index; + volatile uint32_t cap6_rise0, cap6_rise1, cap6_fall0, cap6_fall1; + uint8_t EXTRA_EDGE_ARR[8] = {0x00 ,0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xFE}; + uint32_t minm_bits = 112, cycle_per_bit = 24, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =3, minm_extra_size = 4, sync_param_mem_start = 0xDC; + uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles; + + /*measure of SYNC period starts*/ + ES = HDSL_get_sync_ctrl(gHdslHandleCh0); + volatile uint32_t* carp6_rise_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPR6_REG0); + volatile uint32_t* carp6_fall_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPF6_REG0); + cap6_rise0 = *(carp6_rise_addr); + cap6_fall0 = *(carp6_fall_addr); + cap6_rise1 = cap6_rise0; + cap6_fall1 = cap6_fall0; + counter = 0; + + for(index = 0 ; index <2 ; index++) + { + cap6_rise0 = cap6_rise1; + cap6_fall0 = cap6_fall1; + while((cap6_fall0 == cap6_fall1) || (cap6_rise0 == cap6_rise1)) + { + cap6_rise1 = *(carp6_rise_addr); + cap6_fall1 = *(carp6_fall_addr); + counter++; + if(counter > MAX_WAIT) + { + DebugP_log("\r\n SYNC PULSE NOT FOUND, WAITING FOR SYNC PULSE"); + counter = 0; + } + } + } + + period = cap6_rise1 - cap6_rise0; + /*measure of SYNC period ends*/ + + minm_cycles = minm_bits * ES * cycle_per_bit; + cycles_left = period - minm_cycles; + time_gRest = (cycles_left % cycle_per_bit) / cycle_per_overclock_bit; + additional_bits = cycles_left / cycle_per_bit; + extra_edge = EXTRA_EDGE_ARR[time_gRest]; + num_of_stuffing = additional_bits / stuffing_size; + extra_size = additional_bits % stuffing_size; + extra_size = extra_size + minm_extra_size * ES; + if(num_of_stuffing > ES * max_stuffing) + { + extra_size = extra_size + (((num_of_stuffing) - (max_stuffing * ES)) * stuffing_size); + num_of_stuffing = ES * max_stuffing; + } + extra_size_remainder = extra_size % ES; + extra_size = extra_size / ES; + stuffing_remainder = num_of_stuffing % ES; + num_of_stuffing = num_of_stuffing / ES; + bottom_up_cycles = (minm_cycles - minm_extra_size * ES * cycle_per_bit); + bottom_up_cycles = bottom_up_cycles + (stuffing_size * (ES * num_of_stuffing + stuffing_remainder))*cycle_per_bit; + bottom_up_cycles = bottom_up_cycles + ((ES * extra_size + extra_size_remainder) * cycle_per_bit ) + time_gRest * cycle_per_overclock_bit; + wait_before_start = (84 * cycle_per_bit)+((8 - time_gRest)*cycle_per_overclock_bit)+(num_of_stuffing * stuffing_size * cycle_per_bit); + if(stuffing_remainder != 0) + { + wait_before_start = wait_before_start+(stuffing_size * cycle_per_bit); + } + wait_before_start = wait_before_start - 51; + if(extra_size < 4 || extra_size > 9) + { + DebugP_log("\r\n ERROR: ES or period selected is Invalid "); + } + DebugP_log("\r\n ********************************************************************"); + DebugP_log("\r\n SYNC MODE: period = %d", period); + DebugP_log("\r\n SYNC MODE: ES = %d", ES); + DebugP_log("\r\n SYNC MODE: counter = %d", counter); + DebugP_log("\r\n SYNC MODE: wait_before_start = %d", wait_before_start); + DebugP_log("\r\n SYNC MODE: bottom_up_cycles = %d", bottom_up_cycles); + DebugP_log("\r\n SYNC MODE: extra_size = %d", extra_size); + DebugP_log("\r\n SYNC MODE: temp_gRest = %d", time_gRest); + DebugP_log("\r\n SYNC MODE: extra_edge = %d", extra_edge); + DebugP_log("\r\n SYNC MODE: num_of_stuffing = %d", num_of_stuffing); + DebugP_log("\r\n SYNC MODE: extra_size_remainder = %d", extra_size_remainder); + DebugP_log("\r\n SYNC MODE: stuffing_remainder = %d", stuffing_remainder); + DebugP_log("\r\n ********************************************************************"); + sync_param_mem_start =sync_param_mem_start + (uint32_t)gPru_dramx; + HWREGB(sync_param_mem_start) = extra_size; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = num_of_stuffing; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = extra_edge; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = time_gRest; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = extra_size_remainder; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = stuffing_remainder; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGH(sync_param_mem_start) = wait_before_start; + +} + +void process_request(HDSL_Handle hdslHandle,int menu){ + uint64_t ret_status=0; + uint64_t val0, val1, val2; + uint8_t ureg, ureg1; + float pos0, pos1, pos2; + uint64_t turn0, turn1, turn2; + + switch(menu) + { + case MENU_SAFE_POSITION: + + val0 = HDSL_get_pos(hdslHandle,0); + if(val0 != -1) + { + + DebugP_log("\r\n Fast Position read successfully"); + } + + val1 = HDSL_get_pos(hdslHandle,1); + if(val1 != -1) + { + DebugP_log("\r\n Safe Position 1 read successfully"); + } + + val2 = HDSL_get_pos(hdslHandle,2); + if(val2 != -1) + { + DebugP_log("\r\n Safe Position 2 read successfully"); + } + + pos0 = (float)(val0 & hdslHandle->mask) / (float)(hdslHandle->mask + 1) * (float)360; + pos1 = (float)(val1 & hdslHandle->mask) / (float)(hdslHandle->mask + 1) * (float)360; + pos2 = (float)(val2 & hdslHandle->mask) / (float)(hdslHandle->mask + 1) * (float)360; + + ureg = HDSL_get_rssi(hdslHandle); + ureg1 = HDSL_get_qm(hdslHandle); + + if (hdslHandle->multi_turn) + { + + turn0 = val0 & ~hdslHandle->mask; + turn0 >>= hdslHandle->res; + + turn1 = val1 & ~hdslHandle->mask; + turn1 >>= hdslHandle->res; + + turn2 = val2 & ~hdslHandle->mask; + turn2 >>= hdslHandle->res; + DebugP_log("\r\n Angle: %10.6f\tTurn: %llu\t", pos0, turn0); + DebugP_log("\r\n SafePos1: %10.6f\tTurn: %llu", pos1, turn1); + DebugP_log("\r\n SafePos2: %10.6f\tTurn: %llu", pos2, turn2); + DebugP_log("\r\n RSSI: %u\t QM: %u", ureg, ureg1 ); + + } + else + { + DebugP_log("\r\n Angle: %10.6f", pos0); + } + break; + case MENU_QUALITY_MONITORING: + ret_status= HDSL_get_qm(hdslHandle); + if(ret_status!=-1) + { + DebugP_log("\r\n Quality monitoring value: %u", ret_status); + } + break; + case MENU_EVENTS: + ret_status=HDSL_get_events(hdslHandle); + if(ret_status!=-1) + { + DebugP_log("\r\n EVENT_H and EVENT_L: 0x%x", ret_status); + } + ret_status=HDSL_get_safe_events(hdslHandle); + if(ret_status!=-1) + { + DebugP_log("\r\n EVENT_S: 0x%x", ret_status); + } + ret_status=HDSL_get_online_status_d(hdslHandle); + if(ret_status!=-1) + { + DebugP_log("\r\n ONLINE_STATUS_D: 0x%x", ret_status); + } + ret_status=HDSL_get_online_status_1(hdslHandle); + if(ret_status!=-1) + { + DebugP_log("\r\n ONLINE_STATUS_1: 0x%x", ret_status); + } + ret_status=HDSL_get_online_status_2(hdslHandle); + if(ret_status!=-1) + { + DebugP_log("\r\n ONLINE_STATUS_2: 0x%x", ret_status); + } + break; + case MENU_SUMMARY: + ret_status= HDSL_get_sum(hdslHandle); + if(ret_status!=-1) + { + DebugP_log("\r\n Summarized slave status: 0x%x", ret_status); + } + break; + case MENU_ACC_ERR_CNT: + ret_status= HDSL_get_acc_err_cnt(hdslHandle); + if(ret_status!=-1) + { + DebugP_log("\r\n Acceleration error counter: %u", ret_status); + } + break; + case MENU_RSSI: + ret_status=HDSL_get_rssi(hdslHandle); + if(ret_status!=-1) + { + DebugP_log("\r\n RSSI: %u", ret_status); + } + break; + case MENU_PC_SHORT_MSG_WRITE: + TC_write_pc_short_msg(hdslHandle); + break; + case MENU_PC_SHORT_MSG_READ: + TC_read_pc_short_msg(hdslHandle); + break; + case MENU_DIRECT_READ_RID0_LENGTH8: + direct_read_rid0_length8(hdslHandle); + break; + case MENU_DIRECT_READ_RID0_LENGTH8_OFFSET6: + direct_read_rid0_length8_offset6(hdslHandle); + break; + case MENU_DIRECT_READ_RID81_LENGTH8: + direct_read_rid81_length8(hdslHandle); + break; + case MENU_DIRECT_READ_RID81_LENGTH2: + direct_read_rid81_length2(hdslHandle); + break; + case MENU_INDIRECT_WRITE_RID0_LENGTH8: + indirect_write_rid0_length8(hdslHandle); + break; + case MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0: + indirect_write_rid0_length8_offset0(hdslHandle); + break; + + default: + DebugP_log( "\r\n ERROR: invalid request"); + break; + } +} +void hdsl_pruss_init(void) +{ + #if (MULTICHANNEL==0) + PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore); + + /* clear ICSS0 PRU data RAM */ + gPru_dramx = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRUx)); + memset(gPru_dramx, 0, (4 * 1024)); + + gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG); + + PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata); + + PRUICSS_intcInit(gPruIcss1Handle, &gPruss1_intc_initdata); + + /* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */ + /*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/ + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240); + /*IEP1 base */ + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000); + + /* enable cycle counter */ + HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN); + #endif + + #if(MULTICHANNEL==1) + PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore); + PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh1->icssCore); + + /* Clear PRU_DRAM0 and PRU_DRAM1 memory */ + memset((void *) CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 0, (16 * 1024)); + memset((void *) CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, 0, (16 * 1024)); + + gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG); + + PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata); + + + /* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */ + /*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/ + HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000238; // Address = 0x30023828 + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240); + HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000258; // Address = 0x30025828 + /*IEP1 base */ + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000); + + HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x0000; // RTU Core + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C24, 0x0007); // PRU Core + HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x000E; // TX_PRU Core + + /* enable cycle counter */ + HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE), CTR_EN); // RTU_PRU Core + HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN); + HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE), CTR_EN); // TX_PRU Core + + #endif +} + +void hdsl_pruss_load_run_fw(HDSL_Handle hdslHandle) +{ + #if (MULTICHANNEL==0) + PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRUx); + #endif + #if(MULTICHANNEL==1) + PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); // ch0 + PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRU1); // ch1 + + /* Enable Load Share mode */ + gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase); + hdsl_enable_load_share_mode(gPru_cfg,PRUICSS_PRUx); + + #endif + if(HDSL_get_sync_ctrl(hdslHandle) == 0) + { + /*free run*/ + #if (MULTICHANNEL==0) + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), + 0, (uint32_t *) Hiperface_DSL2_0, + sizeof(Hiperface_DSL2_0)); + #endif + #if (MULTICHANNEL==1) + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_RTU_PRU(1), + 0, (uint32_t *) Hiperface_DSL2_0_RTU, + sizeof(Hiperface_DSL2_0_RTU)); + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(1), + 0, (uint32_t *) Hiperface_DSL2_0_PRU, + sizeof(Hiperface_DSL2_0_PRU)); + #endif + } + else + { + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ!=300000000) + /*sync_mode*/ + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), + 0, (uint32_t *) Hiperface_DSL_SYNC2_0, + sizeof(Hiperface_DSL_SYNC2_0)); + #endif + } + #if (MULTICHANNEL==0) + PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRUx); + /*Run firmware*/ + PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRUx); + #endif + #if(MULTICHANNEL==1) + PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); + PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRU1); + /*Run firmware*/ + PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); + PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRU1); + #endif + +} + +void hdsl_init(void) +{ + uint8_t ES; + uint32_t period; + + hdsl_pruss_init(); + + HDSL_iep_init(gHdslHandleCh0); + DebugP_log("\r\nPress Enter to start application\n"); + DebugP_scanf("%d",&ES); + ClockP_usleep(5000); + if(CONFIG_HDSL0_MODE==0) + { + ES=0; + } + else + { + ES=1; + } + HDSL_set_sync_ctrl(gHdslHandleCh0, ES); + if (MULTICHANNEL==1) + { + HDSL_set_sync_ctrl(gHdslHandleCh1, ES); + } + if(ES != 0) + { + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + DebugP_log("\r\n Sync mode with 300 MHz is not available"); + while(1); + #endif + DebugP_log("\r\nSYNC MODE\n"); + DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 4.44ns):"); + DebugP_scanf("%d",&period); + + HDSL_enable_sync_signal(ES,period); + HDSL_generate_memory_image(gHdslHandleCh0); + if (MULTICHANNEL==1) + { + HDSL_generate_memory_image(gHdslHandleCh1); + } + sync_calculation(); + } + else + { + DebugP_log( "\r\nFREE RUN MODE\n"); + HDSL_generate_memory_image(gHdslHandleCh0); + if (MULTICHANNEL==1) + { + HDSL_generate_memory_image(gHdslHandleCh1); + } + } +} + +void TC_read_pc_short_msg(HDSL_Handle hdslHandle) +{ + int32_t status = SystemP_FAILURE; + status = HDSL_read_pc_short_msg(hdslHandle,ENCODER_RSSI_REG_ADDRESS, &gPc_data, SHORT_MSG_TIMEOUT); + if(SystemP_SUCCESS != status) + { + DebugP_log("\r\n FAIL: HDSL_read_pc_short_msg() did not return success"); + return; + } + + DebugP_log("\r\n Parameter channel short message read : Slave RSSI (address 0x7C) = %x (should be 0x7 which indicates best signal strength)", gPc_data); + + status = HDSL_read_pc_short_msg(hdslHandle,ENCODER_STATUS0_REG_ADDRESS, &gPc_data, SHORT_MSG_TIMEOUT); + if(SystemP_SUCCESS != status) + { + DebugP_log("\r\n FAIL: HDSL_read_pc_short_msg() did not return success"); + return; + } + + DebugP_log("\r\n Parameter channel short message read : Address 0x40 = %x (should be 0x1)", gPc_data); +} + +void TC_write_pc_short_msg(HDSL_Handle hdslHandle) +{ + int32_t status = SystemP_FAILURE; + + DebugP_log("\r\n Parameter channel short message write : 0xab to PING register (address 0x7F)"); + + status = HDSL_write_pc_short_msg(hdslHandle,ENCODER_PING_REG_ADDRESS, 0xab, SHORT_MSG_TIMEOUT); + if(SystemP_SUCCESS != status) + { + DebugP_log("\r\n FAIL: HDSL_write_pc_short_msg() did not return success"); + return; + } + + status = HDSL_read_pc_short_msg(hdslHandle,ENCODER_PING_REG_ADDRESS, &gPc_data, SHORT_MSG_TIMEOUT); + if(SystemP_SUCCESS != status) + { + DebugP_log("\r\n FAIL: HDSL_read_pc_short_msg() did not return success"); + return; + } + DebugP_log("\r\n Parameter channel short message read : PING register (address 0x7F) = %x (should be 0xab) ", gPc_data); + + + DebugP_log("\r\n Parameter channel short message write : 0xcd to PING register (address 0x7F)"); + + status = HDSL_write_pc_short_msg(hdslHandle,ENCODER_PING_REG_ADDRESS, 0xcd, SHORT_MSG_TIMEOUT); + if(SystemP_SUCCESS != status) + { + DebugP_log("\r\n FAIL: HDSL_write_pc_short_msg() did not return success"); + return; + } + + status = HDSL_read_pc_short_msg(hdslHandle,ENCODER_PING_REG_ADDRESS, &gPc_data, SHORT_MSG_TIMEOUT); + if(SystemP_SUCCESS != status) + { + DebugP_log("\r\n FAIL: HDSL_read_pc_short_msg() did not return success"); + return; + } + DebugP_log("\r\n Parameter channel short message read : PING register (address 0x7F) = %x (should be 0xcd) ", gPc_data); +} + +static void display_menu(void) +{ + DebugP_log("\r\n"); + DebugP_log("\r\n |------------------------------------------------------------------------------|"); + DebugP_log("\r\n | MENU |"); + DebugP_log("\r\n |------------------------------------------------------------------------------|"); + DebugP_log("\r\n | %2d : Safe Position |", MENU_SAFE_POSITION); + DebugP_log("\r\n | %2d : Quality Monitoring |", MENU_QUALITY_MONITORING); + DebugP_log("\r\n | %2d : Events |", MENU_EVENTS); + DebugP_log("\r\n | %2d : Summarized Slave Status |", MENU_SUMMARY); + DebugP_log("\r\n | %2d : Acceleration Error Counter |", MENU_ACC_ERR_CNT); + DebugP_log("\r\n | %2d : RSSI |", MENU_RSSI); + DebugP_log("\r\n | %2d : Parameter Channel Short Message Write |", MENU_PC_SHORT_MSG_WRITE); + DebugP_log("\r\n | %2d : Parameter Channel Short Message Read |", MENU_PC_SHORT_MSG_READ); + DebugP_log("\r\n | %2d : Access on RID 0h, direct read access with length 8 |", MENU_DIRECT_READ_RID0_LENGTH8); + DebugP_log("\r\n | %2d : Access on RID 81h, direct read access with length 8 |", MENU_DIRECT_READ_RID81_LENGTH8); + DebugP_log("\r\n | %2d : Access on RID 81h, direct read access with length 2 |", MENU_DIRECT_READ_RID81_LENGTH2); + DebugP_log("\r\n | %2d : Access on RID 0h, indirect write, length 8, with offset 0 |", MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0); + DebugP_log("\r\n | %2d : Access on RID 0h; indirect write, length 8, without offset value |", MENU_INDIRECT_WRITE_RID0_LENGTH8); + DebugP_log("\r\n | %2d : Access on RID 0h, direct read, length 8, with offset 6 |", MENU_DIRECT_READ_RID0_LENGTH8_OFFSET6); + DebugP_log("\r\n |------------------------------------------------------------------------------|\n"); + DebugP_log("\r\n Enter value: "); +} + +void direct_read_rid0_length8(HDSL_Handle hdslHandle) +{ + uint8_t dir = 0x01; + + gPc_addrh = 0xec; + gPc_addrl = 0x00; + gPc_offh = 0x80; + gPc_offl = 0x00; + + HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + + HDSL_set_pc_ctrl(hdslHandle,dir); + + ClockP_sleep(1); + + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); + + if(gPc_buf0 == 82) + { + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); + if(gPc_buf1 == 79) + { + gPc_buf2 = HDSL_read_pc_buffer(hdslHandle,2); + if(gPc_buf2 == 79) + { + gPc_buf3 = HDSL_read_pc_buffer(hdslHandle,3); + if(gPc_buf3 == 84) + { + DebugP_log("\r\n PASS"); + } + else + { + DebugP_log("\r\n FAIL: gPc_buf3 != T = %u", gPc_buf3); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf2 != O = %u", gPc_buf2); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf1 != O = %u", gPc_buf1); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf0 != R = %u", gPc_buf0); + } +} + +void direct_read_rid81_length8(HDSL_Handle hdslHandle) +{ + uint8_t dir = 0x01; + gPc_addrh = 0xec; + gPc_addrl = 0x81; + gPc_offh = 0x80; + gPc_offl = 0x00; + + HDSL_set_pc_addr( hdslHandle,gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + + HDSL_set_pc_ctrl(hdslHandle,dir); + + ClockP_sleep(1); + + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); + if(gPc_buf0 == 82) + { + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); + if(gPc_buf1 == 69) + { + gPc_buf2 = HDSL_read_pc_buffer(hdslHandle,2); + if(gPc_buf2 == 83) + { + gPc_buf3 = HDSL_read_pc_buffer(hdslHandle,3); + if(gPc_buf3 == 79) + { + gPc_buf4 = HDSL_read_pc_buffer(hdslHandle,4); + if(gPc_buf4 == 76) + { + gPc_buf5 = HDSL_read_pc_buffer(hdslHandle,5); + if(gPc_buf5 == 85) + { + gPc_buf6 = HDSL_read_pc_buffer(hdslHandle,6); + if(gPc_buf6 == 84) + { + gPc_buf7 = HDSL_read_pc_buffer(hdslHandle,7); + if(gPc_buf7 == 78) + { + DebugP_log("\r\n PASS "); + } + else + { + DebugP_log("\r\n FAIL: gPc_buf7 != N ", gPc_buf7); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf6 != T ", gPc_buf6); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf5 != U ", gPc_buf5); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf4 != L ", gPc_buf4); + } + + } + else + { + DebugP_log("\r\n FAIL: gPc_buf3 != O ", gPc_buf3); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf2 != S = %u", gPc_buf2); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf1 != E = %u", gPc_buf1); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf0 != R = %u", gPc_buf0); + } +} + +void direct_read_rid81_length2(HDSL_Handle hdslHandle) +{ + uint8_t dir = 0x01; + + gPc_addrh = 0xe4; + gPc_addrl = 0x81; + gPc_offh = 0x80; + gPc_offl = 0x03; + + HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + + HDSL_set_pc_ctrl(hdslHandle,dir); + + ClockP_sleep(1); + + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); + + if(gPc_buf0 == 0x00) + { + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); + if(gPc_buf1 == 0x0f) + { + DebugP_log("\r\n PASS "); + + } + else + { + DebugP_log("\r\n FAIL: gPc_buf1 != 0x0f = %u", gPc_buf1); + } + + } + else + { + DebugP_log("\r\n FAIL: gPc_buf0 != 0x00 = %u", gPc_buf0); + } +} + +void indirect_write_rid0_length8_offset0(HDSL_Handle hdslHandle) +{ + uint8_t dir = 0x01; + + gPc_addrh = 0xbc; + gPc_addrl = 0x00; + gPc_offh = 0x80; + gPc_offl = 0x00; + + HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + + HDSL_set_pc_ctrl(hdslHandle,dir); + + ClockP_sleep(1); + + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); + if(gPc_buf0 == 0x41) + { + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); + if(gPc_buf1 == 0x10) + { + DebugP_log("\r\n PASS "); + } + else + { + DebugP_log("\r\n FAIL: gPc_buf1 != 0x10 = %u", gPc_buf1); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf0 != 0x41 = %u", gPc_buf0); + } + +} + +void indirect_write_rid0_length8(HDSL_Handle hdslHandle) +{ + uint8_t dir = 0x01; + + gPc_addrh = 0x9c; + gPc_addrl = 0x00; + gPc_offh = 0x80; + gPc_offl = 0x00; + + HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + + HDSL_set_pc_ctrl(hdslHandle,dir); + + ClockP_sleep(1); + + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); + if(gPc_buf0 == 0x41) + { + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); + if(gPc_buf1 == 0x10) + { + DebugP_log("\r\n PASS "); + } + else + { + DebugP_log("\r\n FAIL: gPc_buf1 != 0x10 = %u", gPc_buf1); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf0 != 0x41 = %u", gPc_buf0); + } +} + +void direct_read_rid0_length8_offset6(HDSL_Handle hdslHandle) +{ + uint8_t dir=0x00; + + gPc_addrh = 0xec; + gPc_addrl = 0x00; + gPc_offh = 0x80; + gPc_offl = 0x06; + + HDSL_set_pc_addr(hdslHandle, gPc_addrh, gPc_addrl, gPc_offh, gPc_offl); + + HDSL_set_pc_ctrl(hdslHandle,dir); + + ClockP_sleep(1); + + gPc_buf0 = HDSL_read_pc_buffer(hdslHandle,0); + if(gPc_buf0 == 0x41) + { + gPc_buf1 = HDSL_read_pc_buffer(hdslHandle,1); + if(gPc_buf1 == 0x10) + { + DebugP_log("\r\n PASS "); + } + else + { + DebugP_log("\r\n FAIL: gPc_buf1 != 0x10 = %u", gPc_buf1); + } + } + else + { + DebugP_log("\r\n FAIL: gPc_buf0 != 0x41 = %u", gPc_buf0); + } +} +static int get_menu(void) +{ + unsigned int cmd; + + + if(DebugP_scanf("%d\n", &cmd) < 0 || cmd >= MENU_LIMIT) + { + DebugP_log("\r\n WARNING: invalid option, Safe position selected"); + cmd = MENU_SAFE_POSITION; + DebugP_log( "\r\n Enter 0 :Fast Position \r\n Enter 1: Safe Position 1 \r\n Enter 2: Safe Position 2 \r"); + + if((DebugP_scanf("%d", &get_pos) < 0) || get_pos > 2) + { + DebugP_log("\r\n WARNING: invalid position value"); + } + } + + if (cmd == MENU_PC_LONG_MSG_WRITE) + { + + DebugP_log("\r\n Enter addgRess High (hex value): "); + if(DebugP_scanf("%x\n", &gPc_addrh) < 0 || gPc_addrh > 0x3f) + { + DebugP_log("\r\n WARNING: invalid addgRess High"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter addgRess Low (hex value): "); + if(DebugP_scanf("%x\n", &gPc_addrl) < 0 || gPc_addrl > 0x3f) + { + DebugP_log("\r\n WARNING: invalid addgRess Low"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter parameter channel offset high (hex value): "); + if(DebugP_scanf("%x\n", &gPc_offh) < 0 || gPc_offh > 0x3f) + { + DebugP_log("\r\n WARNING: invalid parameter channel offset high"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter parameter channel offset low (hex value): "); + if(DebugP_scanf("%x\n", &gPc_offl) < 0 || gPc_offl > 0x3f) + { + DebugP_log("\r\n WARNING: invalid parameter channel offset low"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter buffer 0 data (hex value): "); + if (DebugP_scanf("%x\n", &gPc_buf0) < 0 || gPc_buf0 > 0xff) + { + DebugP_log("\r\n WARNING: invalid buffer 0 data"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter buffer 1 data (hex value): "); + if (DebugP_scanf("%x\n", &gPc_buf1) < 0 || gPc_buf1 > 0xff) + { + DebugP_log("\r\n WARNING: invalid buffer 1 data"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter buffer 2 data (hex value): "); + if (DebugP_scanf("%x\n", &gPc_buf2) < 0 || gPc_buf2 > 0xff) + { + DebugP_log("\r\n WARNING: invalid buffer 2 data"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter buffer 3 data (hex value): "); + if (DebugP_scanf("%x\n", &gPc_buf3) < 0 || gPc_buf3 > 0xff) + { + DebugP_log("\r\n WARNING: invalid buffer 3 data"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter buffer 4 data (hex value): "); + if (DebugP_scanf("%x\n", &gPc_buf4) < 0 || gPc_buf4 > 0xff) + { + DebugP_log("\r\n WARNING: invalid buffer 4 data"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter buffer 5 data (hex value): "); + if (DebugP_scanf("%x\n", &gPc_buf5) < 0 || gPc_buf5 > 0xff) + { + DebugP_log("\r\n WARNING: invalid buffer 5 data"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter buffer 6 data (hex value): "); + if (DebugP_scanf("%x\n", &gPc_buf6) < 0 || gPc_buf6 > 0xff) + { + DebugP_log("\r\n WARNING: invalid buffer 6 data"); + return MENU_INVALID; + } + + DebugP_log("\r\n Enter buffer 7 data (hex value): "); + if (DebugP_scanf("%x\n", &gPc_buf7) < 0 || gPc_buf7 > 0xff) + { + DebugP_log("\r\n WARNING: invalid buffer 7 data"); + return MENU_INVALID; + } + } + + return cmd; +} + + + +#ifdef HDSL_AM64xE1_TRANSCEIVER +static void hdsl_i2c_io_expander(void *args) +{ + int32_t status = SystemP_SUCCESS; + /* P20 = LED 3 bits, pin, 2 bits port.*/ + uint32_t ioIndex = 0x10; + TCA6424_Params tca6424Params; + + TCA6424_Params_init(&tca6424Params); + + status = TCA6424_open(&gTCA6424_Config, &tca6424Params); + + if(status == SystemP_SUCCESS) + { + /* Set output to HIGH before config so that LED start with On state */ + status = TCA6424_setOutput( + &gTCA6424_Config, + ioIndex, + TCA6424_OUT_STATE_HIGH); + + /* Configure as output */ + status += TCA6424_config( + &gTCA6424_Config, + ioIndex, + TCA6424_MODE_OUTPUT); + /* set P12 high which controls CPSW_FET_SEL -> enable PRU1 and PRU0 GPIOs */ + ioIndex = 0x0a; + status = TCA6424_setOutput( + &gTCA6424_Config, + ioIndex, + TCA6424_OUT_STATE_HIGH); + + /* Configure as output */ + status += TCA6424_config( + &gTCA6424_Config, + ioIndex, + TCA6424_MODE_OUTPUT); + + + } + TCA6424_close(&gTCA6424_Config); +} +#endif + +void hdsl_diagnostic_main(void *arg) +{ + uint32_t val, acc_bits, pos_bits; + uint8_t ureg; + + /* Open drivers to open the UART driver for console */ + Drivers_open(); + Board_driversOpen(); +/*C16 pin High for Enabling ch0 in booster pack */ + #if (CONFIG_HDSL0_BOOSTER_PACK) + GPIO_setDirMode(ENC1_EN_BASE_ADDR, ENC1_EN_PIN, ENC1_EN_DIR); + GPIO_pinWriteHigh(ENC1_EN_BASE_ADDR, ENC1_EN_PIN); + #endif + + #ifndef HDSL_AM64xE1_TRANSCEIVER + /* Configure g_mux_en to 1 in ICSSG_SA_MX_REG Register. This is required to remap EnDAT signals correctly via Interface card.*/ + HW_WR_REG32((CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE+0x40), (0x80)); + + /*Configure GPIO42 for HDSL mode.*/ + GPIO_setDirMode(CONFIG_GPIO0_BASE_ADDR, CONFIG_GPIO0_PIN, CONFIG_GPIO0_DIR); + GPIO_pinWriteHigh(CONFIG_GPIO0_BASE_ADDR, CONFIG_GPIO0_PIN); + #else + /* Configure g_mux_en to 0 in ICSSG_SA_MX_REG Register. */ + HW_WR_REG32((CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE+0x40), (0x00)); + /*Configure GPIO42 for HDSL mode. New transceiver card needs the pin to be configured as input*/ + HW_WR_REG32(0x000F41D4, 0x00050001); /* PRG0_PRU1_GPI9 as input */ + hdsl_i2c_io_expander(NULL); + #endif + gPruIcss0Handle = PRUICSS_open(CONFIG_PRU_ICSS0); + // initialize hdsl handle + #if (MULTICHANNEL==0) + gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx,0); + #endif + #if(MULTICHANNEL==1) + gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_RTU_PRU1,1); + gHdslHandleCh1 = HDSL_open(gPruIcss0Handle, PRUICSS_PRU1,1); + #endif + DebugP_log( "\n\n Hiperface DSL diagnostic\n"); + hdsl_init(); + DebugP_log( "\r\n HDSL setup finished\n"); + /*need some extra time for SYNC mode since frames are longer*/ + hdsl_pruss_load_run_fw(gHdslHandleCh0); + + ClockP_usleep(1000); + for (ureg = HDSL_get_master_qm(gHdslHandleCh0), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh0), val++, ClockP_usleep(10)) + { + if (val > 100) + { /* wait 1ms to detect, increase if reqd. */ + DebugP_log( "\r\nHiperface DSL encoder not detected on gHdslHandleCh0 \n\n"); + ClockP_usleep(5000); + } + } + + DebugP_log( "\r\n"); + DebugP_log( "\r|------------------------------------------------------------------------------|\n"); + DebugP_log( "\r| Hiperface DSL diagnostic |\n"); + DebugP_log( "\r|------------------------------------------------------------------------------|\n"); + DebugP_log( "\r|========Channel 0: |\n"); + DebugP_log( "\r|\n"); + DebugP_log( "\r| Quality monitoring value: %u\n", ureg & 0xF); + + ureg = HDSL_get_edges(gHdslHandleCh0); + DebugP_log( "\r| Edges: 0x%x\n", ureg); + + ureg = HDSL_get_delay(gHdslHandleCh0); + DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF); + DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4); + + val =HDSL_get_enc_id(gHdslHandleCh0, 0) | (HDSL_get_enc_id(gHdslHandleCh0, 1) << 8) | + (HDSL_get_enc_id(gHdslHandleCh0, 2) << 16); + acc_bits = val & 0xF; + acc_bits += 8; + pos_bits = (val & 0x3F0) >> 4; + pos_bits += acc_bits; + DebugP_log("\r\n | Encoder ID: 0x%x", val); + DebugP_log( "("); + DebugP_log( "Acceleration bits: %u ,", acc_bits); + DebugP_log( "Position bits: %u,", pos_bits); + DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position"); + DebugP_log(")|"); + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); + + DebugP_log("\r\n Enter single turn bits: "); + if((DebugP_scanf("%d\n", &gHdslHandleCh0->res) < 0) || gHdslHandleCh0->res > pos_bits) + { + DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n"); + gHdslHandleCh0->res = pos_bits; + } + gHdslHandleCh0->multi_turn = pos_bits - gHdslHandleCh0->res; + gHdslHandleCh0->mask = pow(2, gHdslHandleCh0->res) - 1; + if (gHdslHandleCh0->multi_turn) + { + DebugP_log( "\r| Multi turn bits: %u\n", gHdslHandleCh0->multi_turn); + } + if (MULTICHANNEL==1) + { + //Channel 1 starts here: + ClockP_usleep(1000); + for (ureg = HDSL_get_master_qm(gHdslHandleCh1), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh1), val++, ClockP_usleep(10)) + { + if (val > 100) + { /* wait 1ms to detect, increase if reqd. */ + DebugP_log( "\r\nHiperface DSL encoder not detected on gHdslHandleCh1 \n\n"); + ClockP_usleep(5000); + } + } + DebugP_log( "\r\n"); + DebugP_log( "\r|------------------------------------------------------------------------------|\n"); + DebugP_log( "\r| Hiperface DSL diagnostic |\n"); + DebugP_log( "\r|------------------------------------------------------------------------------|\n"); + DebugP_log( "\r|========Channel 1: |\n"); + DebugP_log( "\r|\n"); + DebugP_log( "\r| Quality monitoring value: %u\n", ureg & 0xF); + ureg = HDSL_get_edges(gHdslHandleCh1); + DebugP_log( "\r| Edges: 0x%x\n", ureg); + ureg = HDSL_get_delay(gHdslHandleCh1); + DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF); + DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4); + val =HDSL_get_enc_id(gHdslHandleCh1, 0) | (HDSL_get_enc_id(gHdslHandleCh1, 1) << 8) | + (HDSL_get_enc_id(gHdslHandleCh1, 2) << 16); + acc_bits = val & 0xF; + acc_bits += 8; + pos_bits = (val & 0x3F0) >> 4; + pos_bits += acc_bits; + DebugP_log("\r\n | Encoder ID: 0x%x", val); + DebugP_log( "("); + DebugP_log( "Acceleration bits: %u ,", acc_bits); + DebugP_log( "Position bits: %u,", pos_bits); + DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position"); + DebugP_log(")|"); + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); + + DebugP_log("\r\n Enter single turn bits: "); + if((DebugP_scanf("%d\n", &gHdslHandleCh1->res) < 0) || gHdslHandleCh1->res > pos_bits) + { + DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n"); + gHdslHandleCh1->res = pos_bits; + } + gHdslHandleCh1->multi_turn = pos_bits - gHdslHandleCh1->res; + gHdslHandleCh1->mask = pow(2, gHdslHandleCh1->res) - 1; + if (gHdslHandleCh1->multi_turn) + { + DebugP_log( "\r| Multi turn bits: %u\n", gHdslHandleCh1->multi_turn); + } + } + while(1) + { + int menu; + display_menu(); + menu = get_menu(); + DebugP_log( "|\r\n Channel 0 "); + process_request(gHdslHandleCh0, menu); + DebugP_log( "\r%s", gUart_buffer); + #if (MULTICHANNEL==1) + DebugP_log( "|\r\n Channel 1"); + process_request(gHdslHandleCh1, menu); + DebugP_log( "\r%s", gUart_buffer); + #endif + } + Board_driversClose(); + Drivers_close(); +} diff --git a/examples/motor_control/hdsl_diagnostic/hdsl_diagnostic.h b/examples/motor_control/hdsl_diagnostic/hdsl_diagnostic.h new file mode 100644 index 0000000..b3c41da --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/hdsl_diagnostic.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2021-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef HDSL_APP_H_ +#define HDSL_APP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) + +/* for DDR trace*/ +#define DDR_START_OFFSET 0x80000000 +#define DDR_LIMIT 0x3FFFFFFF +#define DDR_END_OFFSET 0xBFFFFFF + +#define NUM_RESOURCES 5000 //4210752 (0x3fff_ffff div 0xff) +/* UDMA TR packet descriptor memory size - with one TR */ +#define UDMA_TEST_TRPD_SIZE (UDMA_GET_TRPD_TR15_SIZE(1U)) + +/* ISR for v-frame-reception */ +static void HDSL_IsrFxn(void); +void TC_read_pc_short_msg(); +void TC_write_pc_short_msg(); + +//void _copy_reg_into_ddr(); +void direct_read_rid0_length8(); +void direct_read_rid0_length8_offset6(); +void direct_read_rid81_length8(); +void direct_read_rid81_length2(); +void indirect_write_rid0_length8(); +void indirect_write_rid0_length8_offset0(); + +/** + * @name HDSL_sync_calculation + * @brief Measurement of syn period + */ +int HDSL_sync_calculation(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/.project/project.js b/examples/motor_control/hdsl_diagnostic/multi_channel/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/.project/project_am243x.js b/examples/motor_control/hdsl_diagnostic/multi_channel/.project/project_am243x.js new file mode 100644 index 0000000..2fc98e4 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/.project/project_am243x.js @@ -0,0 +1,121 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "hdsl_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", /* hdsl_diagnostic.c base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const projectspec_files = { + common: [ + "../../../../hdsl_diagnostic.h", + + ] +} + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_HDSL"; + +const templates_freertos_r5f = +[ + + { + input: ".project/templates/am243x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "hdsl_diagnostic_main", + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "hdsl_diagnostic_multi_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projectspec_files = projectspec_files; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/.project/project_am64x.js b/examples/motor_control/hdsl_diagnostic/multi_channel/.project/project_am64x.js new file mode 100644 index 0000000..28bd665 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/.project/project_am64x.js @@ -0,0 +1,119 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "hdsl_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", /* hdsl_diagnostic.c base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const projectspec_files = { + common: [ + "../../../../hdsl_diagnostic.h", + ] +} + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_HDSL"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am64x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "hdsl_diagnostic_main", + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "hdsl_diagnostic_multi_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projectspec_files = projectspec_files; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..a735cd2 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,108 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const hdsl = scripting.addModule("/motor_control/position_sense/hdsl", {}, false); +const hdsl1 = hdsl.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +gpio1.$name = "CONFIG_GPIO0"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "GPMC0_CSn1"; + +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +pruicss1.$name = "CONFIG_PRU_ICSS1"; +pruicss1.instance = "ICSSG1"; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +hdsl1.$name = "CONFIG_HDSL0"; +hdsl1.coreClk = 300000000; +hdsl1.channel_1 = true; +hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss2 = pruicss.addInstance({}, false); +pruicss2.$name = "CONFIG_PRU_ICSS0"; +hdsl1.pru = pruicss2; +pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +gpio1.GPIO.$suggestSolution = "GPIO0"; +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +hdsl1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +hdsl1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +hdsl1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +hdsl1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..d7b8bf5 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void hdsl_diagnostic_main(void *args); + +void freertos_main(void *args) +{ + hdsl_diagnostic_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..34e0853 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..aa81407 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,153 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +/* section identifier +*/ +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM + + .hdslInterface_ddr_mem (NOLOAD) > DDR +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x60000 + /* DDR segment of memory */ + DDR : ORIGIN = 0x80000000 , LENGTH = 0x3FFFFFFF + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..c68cc05 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,308 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=hdsl_diagnostic_multi_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_multi_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_multi_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_multi_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + hdsl_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_multi_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..0717b8c --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..cd1eb39 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,108 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const hdsl = scripting.addModule("/motor_control/position_sense/hdsl", {}, false); +const hdsl1 = hdsl.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +gpio1.$name = "CONFIG_GPIO0"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "GPMC0_CSn1"; + +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +pruicss1.$name = "CONFIG_PRU_ICSS1"; +pruicss1.instance = "ICSSG1"; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +hdsl1.$name = "CONFIG_HDSL0"; +hdsl1.coreClk = 300000000; +hdsl1.channel_1 = true; +hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss2 = pruicss.addInstance({}, false); +pruicss2.$name = "CONFIG_PRU_ICSS0"; +hdsl1.pru = pruicss2; +pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +gpio1.GPIO.$suggestSolution = "GPIO0"; +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +hdsl1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +hdsl1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +hdsl1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +hdsl1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..d7b8bf5 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void hdsl_diagnostic_main(void *args); + +void freertos_main(void *args) +{ + hdsl_diagnostic_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..1be66f5 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..aa81407 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,153 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +/* section identifier +*/ +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM + + .hdslInterface_ddr_mem (NOLOAD) > DDR +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x60000 + /* DDR segment of memory */ + DDR : ORIGIN = 0x80000000 , LENGTH = 0x3FFFFFFF + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..b7609e9 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,309 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=hdsl_diagnostic_multi_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_multi_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_multi_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_multi_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + hdsl_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_multi_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM64x_beta --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..17e86fd --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,107 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..40bee23 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/.project/project.js b/examples/motor_control/hdsl_diagnostic/single_channel/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/.project/project_am243x.js b/examples/motor_control/hdsl_diagnostic/single_channel/.project/project_am243x.js new file mode 100644 index 0000000..2993b90 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/.project/project_am243x.js @@ -0,0 +1,122 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "hdsl_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", /* hdsl_diagnostic.c base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const projectspec_files = { + common: [ + "../../../../hdsl_diagnostic.h", + + ] +} + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_HDSL"; + +const templates_freertos_r5f = +[ + + { + input: ".project/templates/am243x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "hdsl_diagnostic_main", + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"}, + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-lp", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "hdsl_diagnostic_single_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projectspec_files = projectspec_files; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/.project/project_am64x.js b/examples/motor_control/hdsl_diagnostic/single_channel/.project/project_am64x.js new file mode 100644 index 0000000..8a254f2 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/.project/project_am64x.js @@ -0,0 +1,119 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "hdsl_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", /* hdsl_diagnostic.c base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const projectspec_files = { + common: [ + "../../../../hdsl_diagnostic.h", + ] +} + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_HDSL"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am64x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "hdsl_diagnostic_main", + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "hdsl_diagnostic_single_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projectspec_files = projectspec_files; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..d22514f --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,107 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const hdsl = scripting.addModule("/motor_control/position_sense/hdsl", {}, false); +const hdsl1 = hdsl.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +gpio1.$name = "CONFIG_GPIO0"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "GPMC0_CSn1"; + +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +pruicss1.$name = "CONFIG_PRU_ICSS1"; +pruicss1.instance = "ICSSG1"; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +hdsl1.$name = "CONFIG_HDSL0"; +hdsl1.coreClk = 300000000; +hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss2 = pruicss.addInstance({}, false); +pruicss2.$name = "CONFIG_PRU_ICSS0"; +hdsl1.pru = pruicss2; +pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +gpio1.GPIO.$suggestSolution = "GPIO0"; +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +hdsl1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +hdsl1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +hdsl1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +hdsl1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..d7b8bf5 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void hdsl_diagnostic_main(void *args); + +void freertos_main(void *args) +{ + hdsl_diagnostic_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..5fb9f44 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..aa81407 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,153 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +/* section identifier +*/ +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM + + .hdslInterface_ddr_mem (NOLOAD) > DDR +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x60000 + /* DDR segment of memory */ + DDR : ORIGIN = 0x80000000 , LENGTH = 0x3FFFFFFF + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..5c688d6 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,308 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=hdsl_diagnostic_single_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=hdsl_diagnostic_single_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_single_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_single_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_single_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_single_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_single_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=hdsl_diagnostic_single_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_single_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + hdsl_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_single_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..c85a34f --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..8e90bdc --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,109 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const gpio2 = gpio.addInstance(); +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const hdsl = scripting.addModule("/motor_control/position_sense/hdsl", {}, false); +const hdsl1 = hdsl.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +gpio1.$name = "CONFIG_GPIO0"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "ball.R20"; + +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +pruicss1.$name = "CONFIG_PRU_ICSS1"; +pruicss1.instance = "ICSSG1"; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +hdsl1.$name = "CONFIG_HDSL0"; +hdsl1.Booster_Pack = true; +hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; +hdsl1.PRU_ICSSG0_PRU.GPO5.$used = false; +hdsl1.PRU_ICSSG0_PRU.GPO4.$used = false; +hdsl1.PRU_ICSSG0_PRU.GPO3.$used = false; +hdsl1.PRU_ICSSG0_PRU.GPI14.$used = false; +hdsl1.PRU_ICSSG0_PRU.GPO8.$used = false; +hdsl1.PRU_ICSSG0_PRU.GPO12.$used = false; +hdsl1.PRU_ICSSG0_PRU.GPO6.$used = false; +hdsl1.PRU_ICSSG0_PRU.GPI11.$used = false; + +hdsl1.ENC1_EN = gpio2; +gpio2.$name = "ENC1_EN"; +gpio2.GPIO.$assign = "GPIO1"; +gpio2.GPIO.gpioPin.rx = false; +gpio2.GPIO.gpioPin.$assign = "ball.C16"; + +const pruicss2 = pruicss.addInstance({}, false); +pruicss2.$name = "CONFIG_PRU_ICSS0"; +hdsl1.pru = pruicss2; +pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +gpio1.GPIO.$suggestSolution = "GPIO0"; +i2c1.I2C.SCL.$suggestSolution = "ball.A17"; +i2c1.I2C.SDA.$suggestSolution = "ball.B18"; +debug_log.uartLog.UART.RXD.$suggestSolution = "ball.B10"; +debug_log.uartLog.UART.TXD.$suggestSolution = "ball.B11"; +hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "ball.M2"; +hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "ball.J2"; +hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "ball.L5"; +hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "ball.T4"; diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..d7b8bf5 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void hdsl_diagnostic_main(void *args); + +void freertos_main(void *args) +{ + hdsl_diagnostic_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..4abde92 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..aa81407 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,153 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +/* section identifier +*/ +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM + + .hdslInterface_ddr_mem (NOLOAD) > DDR +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x60000 + /* DDR segment of memory */ + DDR : ORIGIN = 0x80000000 , LENGTH = 0x3FFFFFFF + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..902f19e --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,308 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=hdsl_diagnostic_single_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=hdsl_diagnostic_single_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_single_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_single_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_single_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_single_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_single_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=hdsl_diagnostic_single_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_single_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + hdsl_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_single_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALX_beta --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..d3b1a4d --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..3ea56b8 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,107 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const hdsl = scripting.addModule("/motor_control/position_sense/hdsl", {}, false); +const hdsl1 = hdsl.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +gpio1.$name = "CONFIG_GPIO0"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "GPMC0_CSn1"; + +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +pruicss1.$name = "CONFIG_PRU_ICSS1"; +pruicss1.instance = "ICSSG1"; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +hdsl1.$name = "CONFIG_HDSL0"; +hdsl1.coreClk = 300000000; +hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss2 = pruicss.addInstance({}, false); +pruicss2.$name = "CONFIG_PRU_ICSS0"; +hdsl1.pru = pruicss2; +pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +gpio1.GPIO.$suggestSolution = "GPIO0"; +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +hdsl1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +hdsl1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +hdsl1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +hdsl1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..d7b8bf5 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void hdsl_diagnostic_main(void *args); + +void freertos_main(void *args) +{ + hdsl_diagnostic_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..350e6fc --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..aa81407 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,153 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +/* section identifier +*/ +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM + + .hdslInterface_ddr_mem (NOLOAD) > DDR +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x60000 + /* DDR segment of memory */ + DDR : ORIGIN = 0x80000000 , LENGTH = 0x3FFFFFFF + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..8192090 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,309 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=hdsl_diagnostic_single_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=hdsl_diagnostic_single_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_single_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_single_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_single_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_single_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_single_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=hdsl_diagnostic_single_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_single_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + hdsl_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_single_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM64x_beta --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..17e86fd --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,107 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..638a08a --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/.project/project.js b/examples/motor_control/hdsl_diagnostic_with_traces/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/.project/project_am243x.js b/examples/motor_control/hdsl_diagnostic_with_traces/.project/project_am243x.js new file mode 100644 index 0000000..e2392db --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/.project/project_am243x.js @@ -0,0 +1,120 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "hdsl_diagnostic_ddr.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f", + + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const projectspec_files = { + common: [ + "../../../hdsl_diagnostic_ddr.h", + ] +} + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_HDSL"; + +const templates_freertos_r5f = +[ + + { + input: ".project/templates/am243x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "hdsl_diagnostic_main", + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "hdsl_diagnostic_ddr"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projectspec_files = projectspec_files; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/.project/project_am64x.js b/examples/motor_control/hdsl_diagnostic_with_traces/.project/project_am64x.js new file mode 100644 index 0000000..269013b --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/.project/project_am64x.js @@ -0,0 +1,118 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "hdsl_diagnostic_ddr.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const projectspec_files = { + common: [ + "../../../hdsl_diagnostic_ddr.h", + ] +} + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_HDSL"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am64x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "hdsl_diagnostic_main", + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "hdsl_diagnostic_ddr"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projectspec_files = projectspec_files; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..075e902 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,121 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.12.1+2446"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const gpio2 = gpio.addInstance(); +const gpio3 = gpio.addInstance(); +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const udma = scripting.addModule("/drivers/udma/udma", {}, false); +const udma1 = udma.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const hdsl = scripting.addModule("/motor_control/position_sense/hdsl", {}, false); +const hdsl1 = hdsl.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +gpio1.$name = "CONFIG_GPIO0"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "GPMC0_CSn1"; + +gpio2.$name = "CONFIG_GPIO_COPY"; +gpio2.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO17"; + +gpio3.$name = "CONFIG_GPIO_TEST_COPY"; +gpio3.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO18"; +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +pruicss1.$name = "CONFIG_PRU_ICSS1"; +pruicss1.instance = "ICSSG1"; + +udma1.$name = "CONFIG_UDMA0"; +udma1.udmaBlkCopyChannel.create(1); +udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0"; +udma1.udmaBlkCopyChannel[0].intrEnable = true; +udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +hdsl1.$name = "CONFIG_HDSL0"; +hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss2 = pruicss.addInstance({}, false); +pruicss2.$name = "CONFIG_PRU_ICSS0"; +hdsl1.pru = pruicss2; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +gpio1.GPIO.$suggestSolution = "GPIO0"; +gpio2.GPIO.$suggestSolution = "GPIO0"; +gpio3.GPIO.$suggestSolution = "GPIO0"; +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +hdsl1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +hdsl1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +hdsl1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +hdsl1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..d7b8bf5 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void hdsl_diagnostic_main(void *args); + +void freertos_main(void *args) +{ + hdsl_diagnostic_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..39835fe --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..aa81407 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,153 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +/* section identifier +*/ +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM + + .hdslInterface_ddr_mem (NOLOAD) > DDR +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x60000 + /* DDR segment of memory */ + DDR : ORIGIN = 0x80000000 , LENGTH = 0x3FFFFFFF + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..fba2a73 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,307 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=hdsl_diagnostic_ddr.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=hdsl_diagnostic_ddr.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_ddr.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_ddr.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_ddr.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_ddr.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_ddr.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=hdsl_diagnostic_ddr.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_ddr.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + hdsl_diagnostic_ddr.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_ddr ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..e24ac01 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..c1b3c8d --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,121 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM64x@08.03.00" + * @versions {"tool":"1.13.0+2553"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const gpio2 = gpio.addInstance(); +const gpio3 = gpio.addInstance(); +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const udma = scripting.addModule("/drivers/udma/udma", {}, false); +const udma1 = udma.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const hdsl = scripting.addModule("/motor_control/position_sense/hdsl", {}, false); +const hdsl1 = hdsl.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +gpio1.$name = "CONFIG_GPIO0"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "GPMC0_CSn1"; + +gpio2.$name = "CONFIG_GPIO_COPY"; +gpio2.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO17"; + +gpio3.$name = "CONFIG_GPIO_TEST_COPY"; +gpio3.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO18"; +i2c1.$name = "CONFIG_I2C0"; +i2c1.I2C.$assign = "I2C1"; + +pruicss1.$name = "CONFIG_PRU_ICSS1"; +pruicss1.instance = "ICSSG1"; + +udma1.$name = "CONFIG_UDMA0"; +udma1.udmaBlkCopyChannel.create(1); +udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0"; +udma1.udmaBlkCopyChannel[0].intrEnable = true; +udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +hdsl1.$name = "CONFIG_HDSL0"; +hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss2 = pruicss.addInstance({}, false); +pruicss2.$name = "CONFIG_PRU_ICSS0"; +hdsl1.pru = pruicss2; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +gpio1.GPIO.$suggestSolution = "GPIO0"; +gpio2.GPIO.$suggestSolution = "GPIO0"; +gpio3.GPIO.$suggestSolution = "GPIO0"; +i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL"; +i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA"; +debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD"; +hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2"; +hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1"; +hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0"; +hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13"; +hdsl1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5"; +hdsl1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4"; +hdsl1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3"; +hdsl1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14"; +hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8"; +hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12"; +hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6"; +hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11"; diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..d7b8bf5 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void hdsl_diagnostic_main(void *args); + +void freertos_main(void *args) +{ + hdsl_diagnostic_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..ad84e2c --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..aa81407 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,153 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +/* section identifier +*/ +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM + + .hdslInterface_ddr_mem (NOLOAD) > DDR +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x60000 + /* DDR segment of memory */ + DDR : ORIGIN = 0x80000000 , LENGTH = 0x3FFFFFFF + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..1af9d29 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,308 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=hdsl_diagnostic_ddr.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=hdsl_diagnostic_ddr.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_ddr.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_ddr.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_ddr.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_ddr.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_ddr.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=hdsl_diagnostic_ddr.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_ddr.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + hdsl_diagnostic_ddr.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_ddr ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM64x_beta --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..17e86fd --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,107 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..9c5c18c --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c b/examples/motor_control/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c new file mode 100644 index 0000000..6f29bb1 --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c @@ -0,0 +1,797 @@ +/* + * Copyright (C) 2021-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "ti_drivers_config.h" +#include "ti_drivers_open_close.h" +#include "ti_board_open_close.h" + +#include "hdsl_diagnostic_ddr.h" + +#include +#include + +#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) +#include +#include +/* Divide factor for normal clock (default value for 225 MHz=23) */ +#define DIV_FACTOR_NORMAL 23 +/* Divide factor for oversampled clock (default value for 225 MHz=2) */ +#define DIV_FACTOR_OVERSAMPLED 2 +#endif +#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) +#include +//#include + +/* Divide factor for normal clock (default value for 300 MHz=31) */ +#define DIV_FACTOR_NORMAL 31 +/* Divide factor for oversampled clock (default value for 300 MHz=3) */ +#define DIV_FACTOR_OVERSAMPLED 3 +#endif + + +#ifdef HDSL_AM64xE1_TRANSCEIVER +#include +#endif + +#define PRUICSS_PRUx PRUICSS_PRU1 + +/* Oversample rate 8*/ +#define OVERSAMPLE_RATE 7 + +#define HDSL_EN (0x1 << 26) +/* OCP as clock, div 32 */ +#define HDSL_TX_CFG (0x10 | (DIV_FACTOR_NORMAL << 16)) +/* OCP as clock, div 4, 8x OSR */ +#define HDSL_RX_CFG (0x10 | (DIV_FACTOR_OVERSAMPLED << 16) | OVERSAMPLE_RATE | 0x08) +#define CTR_EN (1 << 3) +#define MAX_WAIT 20000 + +/* DDR Trace is triggered for each H-Frame. SYS_EVENT_21 is triggered for each + H-Frame from PRU. SYS_EVENT_21 is mapped to PRU_ICSSG0_PR1_HOST_INTR_PEND_3 of R5F + in INTC Mapping. */ + +/*Event number for SYS_EVENT_21 (pr1_pru_mst_intr<5>_int_req) */ +#define HDSL_DDR_TRACE_ICSS_INTC_EVENT_NUM (21U) + +/* R5F Interrupt number for DDR Traces */ +#define HDSL_DDR_TRACE_R5F_IRQ_NUM (CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_3) + +extern PRUICSS_Config gPruicssConfig[2]; + +Udma_ChHandle chHandle; + +/* To store user input to start DDR copy*/ +volatile uint8_t start_copy; + +/* To store user input number of count of DDR copy*/ +uint16_t ddr_trace_count; + +/* To save log count during DDR copy*/ +uint32_t temp_count_arr[NUM_RESOURCES]; + +/* To save log v-frame count during DDR copy*/ +uint32_t v_frames_count_arr[NUM_RESOURCES]; + +/* To copy HDSL Interface structure ddr location */ +HDSL_Interface gHdslInterface_ddr[NUM_RESOURCES] __attribute__((aligned(128), section(".hdslInterface_ddr_mem"))); + +HwiP_Object gPRUHwiObject; +/** \brief Global Structure pointer holding PRUSS1 memory Map. */ +PRUICSS_Handle gPruIcss0Handle; +PRUICSS_IntcInitData gPruss0_intc_initdata = PRU_ICSS0_INTC_INITDATA; +PRUICSS_Handle gPruIcss1Handle; +PRUICSS_IntcInitData gPruss1_intc_initdata = PRU_ICSS1_INTC_INITDATA; + +HDSL_Handle gHdslHandleCh0; + +static void *gPru_cfg, *gPru_ctrl; + +static char gUart_buffer[256]; + +void *gPru_dramx; + +int get_pos=1; + +uint32_t gMulti_turn, gRes; +uint64_t gMask; + +uint8_t gPc_data; + +uint8_t gPc_addrh, gPc_addrl, gPc_offh, gPc_offl, gPc_buf0, gPc_buf1, gPc_buf2, gPc_buf3, gPc_buf4, gPc_buf5, gPc_buf6, gPc_buf7; + + +#ifdef HDSL_AM64xE1_TRANSCEIVER +static TCA6424_Config gTCA6424_Config; +#endif + +/* Semaphore to indicate transfer completion */ +static SemaphoreP_Object gUdmaTestDoneSem; +/* UDMA TRPD Memory */ +uint8_t gUdmaTestTrpdMem[UDMA_TEST_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT))); + +void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData); +static void App_udmaTrpdInit(Udma_ChHandle chHandle, + uint8_t *trpdMem, + const void *destBuf, + const void *srcBuf, + uint32_t length); + +void sync_calculation(void) +{ + uint8_t ES; + uint16_t wait_before_start; + uint32_t counter, period, index; + volatile uint32_t cap6_rise0, cap6_rise1, cap6_fall0, cap6_fall1; + uint8_t EXTRA_EDGE_ARR[8] = {0x00 ,0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xFE}; + uint32_t minm_bits = 112, cycle_per_bit = 24, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =3, minm_extra_size = 4, sync_param_mem_start = 0xDC; + uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles; + + /*measure of SYNC period starts*/ + ES = HDSL_get_sync_ctrl(gHdslHandleCh0); + volatile uint32_t* carp6_rise_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPR6_REG0); + volatile uint32_t* carp6_fall_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPF6_REG0); + cap6_rise0 = *(carp6_rise_addr); + cap6_fall0 = *(carp6_fall_addr); + cap6_rise1 = cap6_rise0; + cap6_fall1 = cap6_fall0; + counter = 0; + + for(index = 0 ; index <2 ; index++) + { + cap6_rise0 = cap6_rise1; + cap6_fall0 = cap6_fall1; + while((cap6_fall0 == cap6_fall1) || (cap6_rise0 == cap6_rise1)) + { + cap6_rise1 = *(carp6_rise_addr); + cap6_fall1 = *(carp6_fall_addr); + counter++; + if(counter > MAX_WAIT) + { + DebugP_log("\r\n SYNC PULSE NOT FOUND, WAITING FOR SYNC PULSE"); + counter = 0; + } + } + } + + period = cap6_rise1 - cap6_rise0; + /*measure of SYNC period ends*/ + + minm_cycles = minm_bits * ES * cycle_per_bit; + cycles_left = period - minm_cycles; + time_gRest = (cycles_left % cycle_per_bit) / cycle_per_overclock_bit; + additional_bits = cycles_left / cycle_per_bit; + extra_edge = EXTRA_EDGE_ARR[time_gRest]; + num_of_stuffing = additional_bits / stuffing_size; + extra_size = additional_bits % stuffing_size; + extra_size = extra_size + minm_extra_size * ES; + if(num_of_stuffing > ES * max_stuffing) + { + extra_size = extra_size + (((num_of_stuffing) - (max_stuffing * ES)) * stuffing_size); + num_of_stuffing = ES * max_stuffing; + } + extra_size_remainder = extra_size % ES; + extra_size = extra_size / ES; + stuffing_remainder = num_of_stuffing % ES; + num_of_stuffing = num_of_stuffing / ES; + bottom_up_cycles = (minm_cycles - minm_extra_size * ES * cycle_per_bit); + bottom_up_cycles = bottom_up_cycles + (stuffing_size * (ES * num_of_stuffing + stuffing_remainder))*cycle_per_bit; + bottom_up_cycles = bottom_up_cycles + ((ES * extra_size + extra_size_remainder) * cycle_per_bit ) + time_gRest * cycle_per_overclock_bit; + wait_before_start = (84 * cycle_per_bit)+((8 - time_gRest)*cycle_per_overclock_bit)+(num_of_stuffing * stuffing_size * cycle_per_bit); + if(stuffing_remainder != 0) + { + wait_before_start = wait_before_start+(stuffing_size * cycle_per_bit); + } + wait_before_start = wait_before_start - 51; + if(extra_size < 4 || extra_size > 9) + { + DebugP_log("\r\n ERROR: ES or period selected is Invalid "); + } + + DebugP_log("\r\n ********************************************************************"); + DebugP_log("\r\n SYNC MODE: period = %d", period); + DebugP_log("\r\n SYNC MODE: ES = %d", ES); + DebugP_log("\r\n SYNC MODE: counter = %d", counter); + DebugP_log("\r\n SYNC MODE: wait_before_start = %d", wait_before_start); + DebugP_log("\r\n SYNC MODE: bottom_up_cycles = %d", bottom_up_cycles); + DebugP_log("\r\n SYNC MODE: extra_size = %d", extra_size); + DebugP_log("\r\n SYNC MODE: temp_gRest = %d", time_gRest); + DebugP_log("\r\n SYNC MODE: extra_edge = %d", extra_edge); + DebugP_log("\r\n SYNC MODE: num_of_stuffing = %d", num_of_stuffing); + DebugP_log("\r\n SYNC MODE: extra_size_remainder = %d", extra_size_remainder); + DebugP_log("\r\n SYNC MODE: stuffing_remainder = %d", stuffing_remainder); + DebugP_log("\r\n ********************************************************************"); + + sync_param_mem_start =sync_param_mem_start + (uint32_t)gPru_dramx; + HWREGB(sync_param_mem_start) = extra_size; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = num_of_stuffing; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = extra_edge; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = time_gRest; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = extra_size_remainder; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGB(sync_param_mem_start) = stuffing_remainder; + sync_param_mem_start = sync_param_mem_start + 1; + HWREGH(sync_param_mem_start) = wait_before_start; + +} + +void udma_copy(uint8_t *srcBuf,uint8_t *destBuf,uint32_t length) +{ + int32_t retVal = UDMA_SOK; + uint64_t pDesc; + uint32_t trRespStatus; + uint8_t *trpdMem = &gUdmaTestTrpdMem[0U]; + uint64_t trpdMemPhy = (uint64_t) Udma_defaultVirtToPhyFxn(trpdMem, 0U, NULL); + + /* Init TR packet descriptor */ + App_udmaTrpdInit(chHandle, trpdMem, destBuf, srcBuf, length); + + /* Submit TRPD to channel */ + retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(chHandle), trpdMemPhy); + DebugP_assert(UDMA_SOK == retVal); + + /* Wait for return descriptor in completion ring - this marks transfer completion */ + SemaphoreP_pend(&gUdmaTestDoneSem, SystemP_WAIT_FOREVER); + + retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(chHandle), &pDesc); + DebugP_assert(UDMA_SOK == retVal); + + /* Check TR response status */ + CacheP_inv(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD); + + trRespStatus = UdmaUtils_getTrpdTr15Response(trpdMem, 1U, 0U); + //DebugP_log("\r\n.trRespStatus = %u ", trRespStatus); + DebugP_assert(CSL_UDMAP_TR_RESPONSE_STATUS_COMPLETE == trRespStatus); + + + /* Validate data in ddr */ + CacheP_inv(destBuf, length, CacheP_TYPE_ALLD); +} + +void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData) +{ + + if(UDMA_EVENT_TYPE_DMA_COMPLETION == eventType) + { + + SemaphoreP_post(&gUdmaTestDoneSem); + + } +} + +static void App_udmaTrpdInit(Udma_ChHandle chHandle, + uint8_t *trpdMem, + const void *destBuf, + const void *srcBuf, + uint32_t length) +{ + CSL_UdmapTR15 *pTr; + uint32_t cqRingNum = Udma_chGetCqRingNum(chHandle); + + /* Make TRPD with TR15 TR type */ + UdmaUtils_makeTrpdTr15(trpdMem, 1U, cqRingNum); + + /* Setup TR */ + pTr = UdmaUtils_getTrpdTr15Pointer(trpdMem, 0U); + pTr->flags = CSL_FMK(UDMAP_TR_FLAGS_TYPE, CSL_UDMAP_TR_FLAGS_TYPE_4D_BLOCK_MOVE_REPACKING_INDIRECTION); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_STATIC, 0U); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOL, CSL_UDMAP_TR_FLAGS_EOL_MATCH_SOL_EOL); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EVENT_SIZE, CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_CMD_ID, 0x25U); /* This will come back in TR response */ + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_SA_INDIRECT, 0U); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_DA_INDIRECT, 0U); + pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOP, 1U); + pTr->icnt0 = length; + pTr->icnt1 = 1U; + pTr->icnt2 = 1U; + pTr->icnt3 = 1U; + pTr->dim1 = pTr->icnt0; + pTr->dim2 = (pTr->icnt0 * pTr->icnt1); + pTr->dim3 = (pTr->icnt0 * pTr->icnt1 * pTr->icnt2); + pTr->addr = (uint64_t) Udma_defaultVirtToPhyFxn(srcBuf, 0U, NULL); + pTr->fmtflags = 0x00000000U; /* Linear addressing, 1 byte per elem */ + pTr->dicnt0 = length; + pTr->dicnt1 = 1U; + pTr->dicnt2 = 1U; + pTr->dicnt3 = 1U; + pTr->ddim1 = pTr->dicnt0; + pTr->ddim2 = (pTr->dicnt0 * pTr->dicnt1); + pTr->ddim3 = (pTr->dicnt0 * pTr->dicnt1 * pTr->dicnt2); + pTr->daddr = (uint64_t) Udma_defaultVirtToPhyFxn(destBuf, 0U, NULL); + + /* Perform cache writeback */ + CacheP_wb(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD); + + return; +} + +void process_request(int menu){ + + switch(menu) + { + + case MENU_HDSL_REG_INTO_DDR: + traces_into_ddr(); + break; + case MENU_HDSL_REG_INTO_DDR_GPIO: + TC_input_start_copy(); + break; + default: + DebugP_log( "\r\n ERROR: invalid request"); + break; + } +} + +void hdsl_pruss_init(void) +{ + + PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore); + + /* clear ICSS0 PRU data RAM */ + gPru_dramx = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRUx)); + memset(gPru_dramx, 0, (4 * 1024)); + + gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG); + + PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata); + + PRUICSS_intcInit(gPruIcss1Handle, &gPruss1_intc_initdata); + + /* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */ + /*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/ + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240); + /*IEP1 base */ + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000); + + /* enable cycle counter */ + gPru_ctrl = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE); + + HW_WR_REG32(gPru_ctrl, CTR_EN); + +} + +void hdsl_pruss_load_run_fw(HDSL_Handle hdslHandle) +{ + PRUICSS_disableCore(gPruIcss0Handle, hdslHandle->icssCore); + + if(HDSL_get_sync_ctrl(hdslHandle) == 0) + { + /*free run*/ + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), + 0, (uint32_t *) Hiperface_DSL2_0, + sizeof(Hiperface_DSL2_0)); + } + else + { + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ!=300000000) + /*sync_mode*/ + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), + 0, (uint32_t *) Hiperface_DSL_SYNC2_0, + sizeof(Hiperface_DSL_SYNC2_0)); + #endif + } + + PRUICSS_resetCore(gPruIcss0Handle, hdslHandle->icssCore); + /*Run firmware*/ + PRUICSS_enableCore(gPruIcss0Handle, hdslHandle->icssCore); +} + +void hdsl_init(void) +{ + uint8_t ES; + uint32_t period; + HwiP_Params hwiPrms; + uint32_t intrNum; + intrNum = HDSL_DDR_TRACE_R5F_IRQ_NUM; + + hdsl_pruss_init(); + + /* Register PRU interrupt */ + HwiP_Params_init(&hwiPrms); + hwiPrms.intNum = intrNum; + hwiPrms.callback = (void*)&HDSL_IsrFxn; + HwiP_construct(&gPRUHwiObject, &hwiPrms); + + HDSL_iep_init(gHdslHandleCh0); + DebugP_log("\r\nPress Enter to start application\n"); + DebugP_scanf("%d",&ES); + ClockP_usleep(5000); + + if(CONFIG_HDSL0_MODE==0) + { + ES=0; + } + else + { + ES=1; + } + + HDSL_set_sync_ctrl(gHdslHandleCh0, ES); + + if(ES != 0) + { + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + DebugP_log("\r\n Sync mode with 300 MHz is not available"); + while(1); + #endif + DebugP_log("\r\nSYNC MODE\n"); + DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 4.44ns):"); + DebugP_scanf("%d",&period); + HDSL_enable_sync_signal(ES,period); + HDSL_generate_memory_image(gHdslHandleCh0); + sync_calculation(); + } + else + { + DebugP_log( "\r\nFREE RUN MODE\n"); + HDSL_generate_memory_image(gHdslHandleCh0); + } +} + +static void HDSL_IsrFxn() +{ + static uint64_t v_frames_count=0; + static int temp = 0; + uint8_t *srcBuf;//= (uint8_t*)gHdslInterface; + uint8_t *destBuf = (uint8_t*)&gHdslInterface_ddr[0U]; + uint32_t length;// = sizeof(hdslInterface); + + srcBuf = (uint8_t*)HDSL_get_src_loc(gHdslHandleCh0); + length = HDSL_get_length(gHdslHandleCh0); + PRUICSS_clearEvent(gPruIcss0Handle, HDSL_DDR_TRACE_ICSS_INTC_EVENT_NUM); + /* No of v-frames count */ + v_frames_count++; + + if((start_copy == 1) && (temp < ddr_trace_count)) + { + + /* Init buffers and TR packet descriptor */ + destBuf = (uint8_t*)&gHdslInterface_ddr[temp]; + + /* start UDMA copying data from src to dest */ + udma_copy(srcBuf,destBuf,length); + + //temp_count_arr[temp] = temp_count++; + v_frames_count_arr[temp] = v_frames_count; + temp++; + } + else + { + start_copy = 0; + temp = 0; + } + +} + +static void display_menu(void) +{ + DebugP_log("\r\n"); + DebugP_log("\r\n |------------------------------------------------------------------------------|"); + DebugP_log("\r\n | MENU |"); + DebugP_log("\r\n |------------------------------------------------------------------------------|"); + DebugP_log("\r\n | %2d : HDSL registers into DDR |", MENU_HDSL_REG_INTO_DDR); + DebugP_log("\r\n | %2d : HDSL registers into DDR using GPIO |", MENU_HDSL_REG_INTO_DDR_GPIO); + DebugP_log("\r\n |------------------------------------------------------------------------------|"); + DebugP_log("\r\n Enter value: "); +} + +void traces_into_ddr(void) +{ + int i= 0; + uint32_t length; + length = HDSL_get_length(gHdslHandleCh0); + + DebugP_log("\r\n sizeof(hdslInterface)_count = %u", length); + DebugP_log("\r\n Start address of DDR location = %u", DDR_START_OFFSET); + DebugP_log("\r\n End address of DDR location = %u", DDR_END_OFFSET); + DebugP_log("\r\n No of HDSL-Interface-Register-Structure to copy = %u", ddr_trace_count); + + start_copy = 1; + + /* Testing: + * To test this input use function TC_input_start_copy() + * Connect the header pins J16 and J17 together + * J16 is used as input for copy start + * J17 is used to create high/low pulses each second + */ + + while(start_copy) + { + ClockP_sleep(1); + } + + for(i=0;i< ddr_trace_count; i++) + { + DebugP_log("\r\n %u .....v_frames_count = %u ",i, v_frames_count_arr[i]); + } + +} + +/* run this test case function to continuously make the start copy input pin high and low every 1 second */ +void TC_input_start_copy() +{ + int i= 0, j =0; + + /* Read the value of J16 header on board */ + start_copy = (uint8_t) GPIO_pinRead(CONFIG_GPIO_COPY_BASE_ADDR, CONFIG_GPIO_COPY_PIN); + + while(j < 10) + { + /* Set the J17 header pin on board as LOW (Active low) */ + GPIO_pinWriteLow(CONFIG_GPIO_TEST_COPY_BASE_ADDR, CONFIG_GPIO_TEST_COPY_PIN); + /* Wait for 1 second */ + ClockP_sleep(1); + + for(i=0;i< ddr_trace_count; i++) + { + DebugP_log("\r\n %u .....v_frames_count = %u ",(j*ddr_trace_count + i), v_frames_count_arr[i]); + } + + /* Set the J17 header pin on board as HIGH */ + GPIO_pinWriteHigh(CONFIG_GPIO_TEST_COPY_BASE_ADDR, CONFIG_GPIO_TEST_COPY_PIN); + /* Wait for 1 second */ + ClockP_sleep(1); + + j++; + } +} + +static int get_menu(void) +{ + unsigned int cmd; + + + if(DebugP_scanf("%d\n", &cmd) < 0 || cmd >= MENU_LIMIT) + { + DebugP_log("\r\n WARNING: invalid option, Safe position selected"); + cmd = MENU_SAFE_POSITION; + DebugP_log( "\r\n Enter 0 :Fast Position \r\n Enter 1: Safe Position 1 \r\n Enter 2: Safe Position 2 \r"); + + if((DebugP_scanf("%d", &get_pos) < 0) || get_pos > 2) + { + DebugP_log("\r\n WARNING: invalid position value"); + } + } + + if (cmd == MENU_HDSL_REG_INTO_DDR) + { + DebugP_log("\r\n| How many traces you want to copy : "); + if(DebugP_scanf("%u\n", &ddr_trace_count) < 0 || ddr_trace_count >= NUM_RESOURCES) + { + DebugP_log("\r\n| WARNING: invalid data\n|\n|\n"); + return MENU_INVALID; + } + } + if (cmd == MENU_HDSL_REG_INTO_DDR_GPIO) + { + DebugP_log("\r\n| How many traces you want to copy : "); + if(DebugP_scanf("%u\n", &ddr_trace_count) < 0 || ddr_trace_count >= NUM_RESOURCES) + { + DebugP_log("\r\n| WARNING: invalid data\n|\n|\n"); + return MENU_INVALID; + } + } + return cmd; +} + + + +#ifdef HDSL_AM64xE1_TRANSCEIVER +static void hdsl_i2c_io_expander(void *args) +{ + int32_t status = SystemP_SUCCESS; + /* P20 = LED 3 bits, pin, 2 bits port.*/ + uint32_t ioIndex = 0x10; + TCA6424_Params tca6424Params; + + TCA6424_Params_init(&tca6424Params); + + status = TCA6424_open(&gTCA6424_Config, &tca6424Params); + + if(status == SystemP_SUCCESS) + { + /* Set output to HIGH before config so that LED start with On state */ + status = TCA6424_setOutput( + &gTCA6424_Config, + ioIndex, + TCA6424_OUT_STATE_HIGH); + + /* Configure as output */ + status += TCA6424_config( + &gTCA6424_Config, + ioIndex, + TCA6424_MODE_OUTPUT); + /* set P12 high which controls CPSW_FET_SEL -> enable PRU1 and PRU0 GPIOs */ + ioIndex = 0x0a; + status = TCA6424_setOutput( + &gTCA6424_Config, + ioIndex, + TCA6424_OUT_STATE_HIGH); + + /* Configure as output */ + status += TCA6424_config( + &gTCA6424_Config, + ioIndex, + TCA6424_MODE_OUTPUT); + + + } + TCA6424_close(&gTCA6424_Config); +} +#endif + +void hdsl_diagnostic_main(void *arg) +{ + uint32_t val, acc_bits, pos_bits; + uint8_t ureg; + int32_t retVal = UDMA_SOK, status; + + /* Open drivers to open the UART driver for console */ + Drivers_open(); + Board_driversOpen(); + + /* UDMA initialization */ + chHandle = gConfigUdma0BlkCopyChHandle[0]; /* Has to be done after driver open */ + + /* Make the J16 pin on board as input for copy start */ + GPIO_setDirMode(CONFIG_GPIO_COPY_BASE_ADDR, CONFIG_GPIO_COPY_PIN, GPIO_DIRECTION_INPUT); + + /* For Testing copy input: */ + /* Make the J17 header pin on board as output as copy start test pin */ + GPIO_setDirMode(CONFIG_GPIO_TEST_COPY_BASE_ADDR, CONFIG_GPIO_TEST_COPY_PIN, GPIO_DIRECTION_OUTPUT); + + /* Channel enable */ + retVal = Udma_chEnable(chHandle); + DebugP_assert(UDMA_SOK == retVal); + status = SemaphoreP_constructBinary(&gUdmaTestDoneSem, 0); + DebugP_assert(SystemP_SUCCESS == status); + + #ifndef HDSL_AM64xE1_TRANSCEIVER + /* Configure g_mux_en to 1 in ICSSG_SA_MX_REG Register. This is required to remap EnDAT signals correctly via Interface card.*/ + HW_WR_REG32((CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE+0x40), (0x80)); + + /*Configure GPIO42 for HDSL mode.*/ + GPIO_setDirMode(CONFIG_GPIO0_BASE_ADDR, CONFIG_GPIO0_PIN, CONFIG_GPIO0_DIR); + GPIO_pinWriteHigh(CONFIG_GPIO0_BASE_ADDR, CONFIG_GPIO0_PIN); + #else + /* Configure g_mux_en to 0 in ICSSG_SA_MX_REG Register. */ + HW_WR_REG32((CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE+0x40), (0x00)); + /*Configure GPIO42 for HDSL mode. New transceiver card needs the pin to be configured as input*/ + HW_WR_REG32(0x000F41D4, 0x00050001); /* PRG0_PRU1_GPI9 as input */ + hdsl_i2c_io_expander(NULL); + #endif + + gPruIcss0Handle = PRUICSS_open(CONFIG_PRU_ICSS0); + gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx,0); + + DebugP_log("\r\n Hiperface DSL Diagnostic"); + hdsl_init(); + DebugP_log("\r\n HDSL Setup finished"); + /*need some extra time for SYNC mode since frames are longer*/ + hdsl_pruss_load_run_fw(gHdslHandleCh0); + ClockP_usleep(1000); + + for (ureg = HDSL_get_master_qm(gHdslHandleCh0), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh0), val++, ClockP_usleep(10)) + { + if (val > 100) + { /* wait 1ms to detect, increase if reqd. */ + while(1) + { + DebugP_log( "\r\n Hiperface DSL encoder not detected\n"); + ClockP_usleep(5000); + } + } + } + + DebugP_log("\r\n "); + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); + DebugP_log("\r\n | Hiperface DSL diagnostic |"); + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); + DebugP_log("\r\n | Quality monitoring value: %u |", ureg & 0xF); + + ureg = HDSL_get_edges(gHdslHandleCh0); + DebugP_log("\r\n | Edges: 0x%x |", ureg); + + ureg = HDSL_get_delay(gHdslHandleCh0); + DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF); + DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4); + + val = HDSL_get_enc_id(gHdslHandleCh0, 0) | (HDSL_get_enc_id(gHdslHandleCh0, 1) << 8) | (HDSL_get_enc_id(gHdslHandleCh0, 2) << 16); + + acc_bits = val & 0xF; + acc_bits += 8; + pos_bits = (val & 0x3F0) >> 4; + pos_bits += acc_bits; + DebugP_log("\r\n | Encoder ID: 0x%x", val); + DebugP_log("("); + DebugP_log("Acceleration bits: %u, ", acc_bits); + DebugP_log("Position bits: %u,", pos_bits); + DebugP_log("%s", val & 0x400 ? " Bipolar position" : " Unipolar position"); + DebugP_log(")|"); + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); + + DebugP_log("\r\n Enter single turn bits: "); + if((DebugP_scanf("%d", &gRes) < 0) || gRes > pos_bits) + { + DebugP_log("\r\n WARNING: invalid single turn bits, assuming single turn encoder"); + gRes = pos_bits; + } + gMulti_turn = pos_bits - gRes; + gMask = pow(2, gRes) - 1; + if (gMulti_turn) + { + DebugP_log("\r\n Multi turn bits: %u", gMulti_turn); + } + while(1) + { + + int menu; + display_menu(); + + menu = get_menu(); + process_request(menu); + DebugP_log( "\r%s", gUart_buffer); + } + + Board_driversClose(); + Drivers_close(); +} diff --git a/examples/motor_control/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.h b/examples/motor_control/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.h new file mode 100644 index 0000000..aef83ed --- /dev/null +++ b/examples/motor_control/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2021-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef MENU_HDSL_REG_INTO_DDR_H_ +#define MENU_HDSL_REG_INTO_DDR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) + +/* for DDR trace*/ +#define DDR_START_OFFSET 0x80000000 +#define DDR_LIMIT 0x3FFFFFFF +#define DDR_END_OFFSET 0xBFFFFFF + +#define NUM_RESOURCES 5000 //4210752 (0x3fff_ffff div 0xff) +/* UDMA TR packet descriptor memory size - with one TR */ +#define UDMA_TEST_TRPD_SIZE (UDMA_GET_TRPD_TR15_SIZE(1U)) + +/* ISR for v-frame-reception */ +static void HDSL_IsrFxn(void); +/* + * @brief It will test DDR traces into DDR + * \n Here user will decide how many copies of HDSL_Interface_Register + * \n will be copied into DDR + */ +void traces_into_ddr(); +/* + * @brief It will test DDR traces into DDR using GPIO pins + * \ connect J17 and J16 pint on AM64x board using wire + * \n Set the J17 header pin on board as LOW (Active low) + * \n wait for 1 second and print traces on UART + * \n Set the J17 header pin on board as HIGH + */ +void TC_input_start_copy(); +int HDSL_sync_calculation(void); +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/examples/motor_control/icss_sdfm/.project/project.js b/examples/motor_control/icss_sdfm/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/icss_sdfm/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/icss_sdfm/.project/project_am243x.js b/examples/motor_control/icss_sdfm/.project/project_am243x.js new file mode 100644 index 0000000..2dfa174 --- /dev/null +++ b/examples/motor_control/icss_sdfm/.project/project_am243x.js @@ -0,0 +1,124 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "app_sddf.c", + "epwm_dc.c", + "epwm_drv_aux.c", + "epwm_mod.c", + "sddf.c", + "cfg_pad.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/include", + "${MCU_PLUS_SDK_PATH}/examples/motor_control/icss_sdfm", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_SDFM"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am243x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am243x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "sddf_main", + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "icss_sdfm"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/icss_sdfm/.project/project_am64x.js b/examples/motor_control/icss_sdfm/.project/project_am64x.js new file mode 100644 index 0000000..bf39d4b --- /dev/null +++ b/examples/motor_control/icss_sdfm/.project/project_am64x.js @@ -0,0 +1,125 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "app_sddf.c", + "epwm_dc.c", + "epwm_drv_aux.c", + "epwm_mod.c", + "sddf.c", + "cfg_pad.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/include", + "${MCU_PLUS_SDK_PATH}/examples/motor_control/icss_sdfm", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_sdfm.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + + + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_SDFM"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am64x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am64x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "sddf_main", + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "icss_sdfm"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..5f0a1db --- /dev/null +++ b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,133 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const epwm = scripting.addModule("/drivers/epwm/epwm", {}, false); +const epwm1 = epwm.addInstance(); +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const gpio2 = gpio.addInstance(); +const gpio3 = gpio.addInstance(); +const gpio4 = gpio.addInstance(); +const gpio5 = gpio.addInstance(); +const gpio6 = gpio.addInstance(); +const gpio7 = gpio.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +epwm1.$name = "CONFIG_EPWM0"; +epwm1.EPWM.$assign = "EHRPWM0"; +epwm1.EPWM.A.$assign = "ball.U20"; +epwm1.EPWM.B.$assign = "ball.U18"; +epwm1.EPWM.SYNCO.$assign = "ball.U21"; +epwm1.EPWM.SYNCI.$used = false; + +gpio1.$name = "GPIO_MTR_1_PWM_EN"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.$assign = "GPIO0"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "ball.Y20"; + +gpio2.$name = "GPIO_HIGH_TH_CH0"; +gpio2.pinDir = "OUTPUT"; +gpio2.useMcuDomainPeripherals = true; +gpio2.MCU_GPIO.$assign = "MCU_GPIO0"; +gpio2.MCU_GPIO.gpioPin.rx = false; +gpio2.MCU_GPIO.gpioPin.$assign = "ball.B6"; + +gpio3.$name = "GPIO_LOW_TH_CH0"; +gpio3.pinDir = "OUTPUT"; +gpio3.useMcuDomainPeripherals = true; +gpio3.MCU_GPIO.gpioPin.rx = false; +gpio3.MCU_GPIO.gpioPin.$assign = "ball.C7"; + +gpio4.$name = "GPIO_HIGH_TH_CH1"; +gpio4.pinDir = "OUTPUT"; +gpio4.useMcuDomainPeripherals = true; +gpio4.MCU_GPIO.gpioPin.rx = false; +gpio4.MCU_GPIO.gpioPin.$assign = "ball.A7"; + +gpio5.$name = "GPIO_LOW_TH_CH1"; +gpio5.pinDir = "OUTPUT"; +gpio5.useMcuDomainPeripherals = true; +gpio5.MCU_GPIO.gpioPin.rx = false; +gpio5.MCU_GPIO.gpioPin.$assign = "ball.D7"; + +gpio6.$name = "GPIO_HIGH_TH_CH2"; +gpio6.pinDir = "OUTPUT"; +gpio6.useMcuDomainPeripherals = true; +gpio6.MCU_GPIO.gpioPin.$assign = "ball.C8"; + +gpio7.$name = "GPIO_LOW_TH_CH2"; +gpio7.pinDir = "OUTPUT"; +gpio7.useMcuDomainPeripherals = true; +gpio7.MCU_GPIO.gpioPin.rx = false; +gpio7.MCU_GPIO.gpioPin.$assign = "ball.E6"; + +pruicss1.$name = "CONFIG_PRU_ICSS0"; +pruicss1.coreClk = 300000000; +pruicss1.iepClk = 300000000; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +debug_log.enableUartLog = true; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +gpio3.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +gpio4.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +gpio5.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +gpio6.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +gpio7.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +debug_log.uartLog.UART.RXD.$suggestSolution = "ball.D15"; +debug_log.uartLog.UART.TXD.$suggestSolution = "ball.C16"; diff --git a/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..bfe4e13 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void sddf_main(void *args); + +void freertos_main(void *args) +{ + sddf_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..64747f6 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..69640f4 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..5e647b9 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,314 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=icss_sdfm.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=icss_sdfm.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=icss_sdfm.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=icss_sdfm.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=icss_sdfm.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=icss_sdfm.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=icss_sdfm.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=icss_sdfm.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=icss_sdfm.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + app_sddf.c \ + epwm_dc.c \ + epwm_drv_aux.c \ + epwm_mod.c \ + sddf.c \ + cfg_pad.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -I${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/include \ + -I${MCU_PLUS_SDK_PATH}/examples/motor_control/icss_sdfm \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang icss_sdfm ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..e23c971 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..6ac1b2f --- /dev/null +++ b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,134 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const epwm = scripting.addModule("/drivers/epwm/epwm", {}, false); +const epwm1 = epwm.addInstance(); +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const gpio2 = gpio.addInstance(); +const gpio3 = gpio.addInstance(); +const gpio4 = gpio.addInstance(); +const gpio5 = gpio.addInstance(); +const gpio6 = gpio.addInstance(); +const gpio7 = gpio.addInstance(); +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +epwm1.$name = "CONFIG_EPWM0"; +epwm1.EPWM.$assign = "EHRPWM0"; +epwm1.EPWM.A.$assign = "ball.U20"; +epwm1.EPWM.B.$assign = "ball.U18"; +epwm1.EPWM.SYNCO.$assign = "ball.U21"; +epwm1.EPWM.SYNCI.$used = false; + +gpio1.$name = "GPIO_MTR_1_PWM_EN"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.$assign = "GPIO0"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "ball.Y20"; + +gpio2.pinDir = "OUTPUT"; +gpio2.useMcuDomainPeripherals = true; +gpio2.$name = "GPIO_HIGH_TH_CH0"; +gpio2.MCU_GPIO.gpioPin.rx = false; +gpio2.MCU_GPIO.gpioPin.$assign = "ball.B6"; + +gpio3.pinDir = "OUTPUT"; +gpio3.$name = "GPIO_LOW_TH_CH0"; +gpio3.useMcuDomainPeripherals = true; +gpio3.MCU_GPIO.gpioPin.rx = false; +gpio3.MCU_GPIO.gpioPin.$assign = "ball.C7"; + +gpio4.$name = "GPIO_HIGH_TH_CH1"; +gpio4.pinDir = "OUTPUT"; +gpio4.useMcuDomainPeripherals = true; +gpio4.MCU_GPIO.gpioPin.rx = false; +gpio4.MCU_GPIO.gpioPin.$assign = "ball.A7"; + +gpio5.$name = "GPIO_LOW_TH_CH1"; +gpio5.pinDir = "OUTPUT"; +gpio5.useMcuDomainPeripherals = true; +gpio5.MCU_GPIO.gpioPin.rx = false; +gpio5.MCU_GPIO.gpioPin.$assign = "ball.D7"; + +gpio6.$name = "GPIO_HIGH_TH_CH2"; +gpio6.pinDir = "OUTPUT"; +gpio6.useMcuDomainPeripherals = true; +gpio6.MCU_GPIO.gpioPin.rx = false; +gpio6.MCU_GPIO.gpioPin.$assign = "ball.C8"; + +gpio7.$name = "GPIO_LOW_TH_CH2"; +gpio7.pinDir = "OUTPUT"; +gpio7.useMcuDomainPeripherals = true; +gpio7.MCU_GPIO.gpioPin.rx = false; +gpio7.MCU_GPIO.gpioPin.$assign = "ball.E6"; + +pruicss1.$name = "CONFIG_PRU_ICSS0"; +pruicss1.iepClk = 300000000; +pruicss1.coreClk = 300000000; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +debug_log.enableUartLog = true; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +gpio2.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +gpio3.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +gpio4.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +gpio5.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +gpio6.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +gpio7.MCU_GPIO.$suggestSolution = "MCU_GPIO0"; +debug_log.uartLog.UART.RXD.$suggestSolution = "ball.D15"; +debug_log.uartLog.UART.TXD.$suggestSolution = "ball.C16"; diff --git a/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..bfe4e13 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void sddf_main(void *args); + +void freertos_main(void *args) +{ + sddf_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..ea096bd --- /dev/null +++ b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..c4848c3 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..39e299a --- /dev/null +++ b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,315 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=icss_sdfm.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=icss_sdfm.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=icss_sdfm.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=icss_sdfm.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=icss_sdfm.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=icss_sdfm.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=icss_sdfm.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=icss_sdfm.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=icss_sdfm.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + app_sddf.c \ + epwm_dc.c \ + epwm_drv_aux.c \ + epwm_mod.c \ + sddf.c \ + cfg_pad.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f \ + -I${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/include \ + -I${MCU_PLUS_SDK_PATH}/examples/motor_control/icss_sdfm \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_sdfm.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_sdfm.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang icss_sdfm ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM64x_beta --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..17e86fd --- /dev/null +++ b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,107 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..8de5880 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/icss_sdfm/app_sddf.c b/examples/motor_control/icss_sdfm/app_sddf.c new file mode 100644 index 0000000..4a5a16e --- /dev/null +++ b/examples/motor_control/icss_sdfm/app_sddf.c @@ -0,0 +1,349 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "ti_drivers_config.h" +#include "ti_drivers_open_close.h" +#include "ti_board_open_close.h" + +#include "epwm_dc.h" +#include "cfg_pad.h" +#include "sddf.h" + +/* Output channel - A or B */ +#define APP_EPWM_OUT_CH_EN ( 0x1 ) /* ChA enabled */ + +/* EPWM functional clock */ +/* Functional clock is the same for all EPWMs */ +#define APP_EPWM_FCLK ( CONFIG_EPWM0_FCLK ) + +/* EPWM functional clock dividers */ +#define APP_EPWM_FCLK_HSPCLKDIV ( 0x0 ) /* EPWM_TBCTL:HSPCLKDIV, High-Speed Time-base Clock Prescale Bits */ +#define APP_EPWM_FCLK_CLKDIV ( 0x0 ) /* EPWM_TBCTL:CLKDIV, Time-base Clock Prescale Bits */ + +#if (APP_EPWM_FCLK_HSPCLKDIV != 0x0) +/* EPWM Time Base clock -- all EPWM TB clocks set the same */ +#define APP_EPWM_TB_FREQ ( APP_EPWM_FCLK / ( 2*APP_EPWM_FCLK_HSPCLKDIV * (1 << APP_EPWM_FCLK_CLKDIV))) +#else +/* EPWM Time Base clock -- all EPWM TB clocks set the same */ +#define APP_EPWM_TB_FREQ ( APP_EPWM_FCLK / ( 1 * (1 << APP_EPWM_FCLK_CLKDIV))) +#endif + +/* Initial Duty Cycle of PWM output signal in %, 0 to 100 */ +#define APP_EPWM0_DUTY_CYCLE ( 50U ) + +/* Frequency of PWM output signal in Hz */ +#define APP_EPWM_OUTPUT_FREQ_4K ( 1U * 4000U ) +#define APP_EPWM_OUTPUT_FREQ_8K ( 1U * 8000U ) +#define APP_EPWM_OUTPUT_FREQ_16K ( 1U * 16000U ) +#define APP_EPWM_OUTPUT_FREQ_20K ( 1U * 20000U ) +#define APP_EPWM_OUTPUT_FREQ ( APP_EPWM_OUTPUT_FREQ_8K ) /* init freq */ + +/*sample Read time */ +#define SAMPLE_READ_TIME ((float)(1000000/(2*APP_EPWM_OUTPUT_FREQ))) //Middle of PWM loop + +/* PWM count direction (Up, Down, Up/Down) */ +#define APP_EPWM_TB_COUNTER_DIR ( EPWM_TB_COUNTER_DIR_UP_DOWN ) + +/* Test ICSSG instance ID */ +#define TEST_ICSSG_INST_ID ( CONFIG_PRU_ICSS0 ) +/* Test ICSSG slice ID */ +#define TEST_ICSSG_SLICE_ID ( ICSSG_SLICE_ID_0 ) +/* Test PRU core instance IDs */ +#define TEST_PRU_INST_ID ( PRUICSS_PRU0 ) +#define TEST_RTU_INST_ID ( PRUICSS_RTU_PRU0 ) + +/* R5F interrupt settings for ICSSG */ +#define ICSSG_PRU_SDDF_INT_NUM ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_0 ) /* VIM interrupt number */ +#define ICSSG_RTU_SDDF_INT_NUM ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_1 ) /* VIM interrupt number */ + +/* EPWM0 IRQ handler */ +static void epwmIrqHandler(void *handle); + +/* HWI global variables */ +static HwiP_Object gIcssgPruSddfHwiObject; /* ICSSG PRU SDDF FW HWI */ +//static HwiP_Object gIcssgRtuSddfHwiObject; /* ICSSG RTU SDDF FW HWI */ +static HwiP_Object gEpwm0HwiObject; /* EPWM0 HWI */ + +/* EPWM global variables */ +uint32_t gEpwm0BaseAddr; /* EPWM0 base address */ +EPwmObj_t gEpwm0Obj; /* EPWM0 object */ +Epwm_Handle hEpwm0; /* EPWM0 handle */ +volatile uint32_t gEpwmOutFreq = APP_EPWM_OUTPUT_FREQ; /* EPWM output frequency */ + +/* ICSSG PRU SDDF FW IRQ handler */ +static void pruSddfIrqHandler(void *handle); + + +/* Test ICSSG handle */ +PRUICSS_Handle gPruIcssHandle; + +/* Test SDDF handles */ +sdfm_handle gHPruSddf; + + +/* Test SDDF parameters */ +SddfPrms gTestSddfPrms = { + SAMPLE_READ_TIME, // trigSampTime in us; always middel of PWM cycle + APP_EPWM_OUTPUT_FREQ, // PWM output frequency + {{3500,2500,0}, //threshold parameters(High, low & reserevd) + {3500,2500,0}, + {3500,2500,0}}, + {{0,0}, //clock sourse & clock inversion for all channels + {0,0}, + {0,0}}, + 32, //OC osr + 64, //NC osr + 1 //comparator enable +}; + +#define PRUICSS_G_MUX_EN ( 0x1 ) /* ICSSG_SA_MX_REG:G_MUX_EN */ + +/* GPIO enable signal for EPWM0-2 on 3-axis breakout board */ +uint32_t gMtr1PwnEnGpioBaseAddr = GPIO_MTR_1_PWM_EN_BASE_ADDR; +uint32_t gMtr1PwnEnGpioPin = GPIO_MTR_1_PWM_EN_PIN; +uint32_t gMtr1PwnEnGpioPinDir = GPIO_MTR_1_PWM_EN_DIR; + +/* Flag for continuing to execute test */ +volatile Bool gRunFlag = TRUE; + + +/* SDFM Output sample for Channel 0 */ +/*Sample size*/ +#define MAX_SAMPLES (128) +uint32_t sdfm_ch0_samples[MAX_SAMPLES] = {0}; +uint32_t sdfm_ch0_idx = 0; +/* SDFM Output sample for Channel 1 */ +uint32_t sdfm_ch1_samples[MAX_SAMPLES] = {0}; +uint32_t sdfm_ch1_idx = 0; +/* SDFM Output sample for Channel 2 */ +uint32_t sdfm_ch2_samples[MAX_SAMPLES] = {0}; +uint32_t sdfm_ch2_idx = 0; + + +/* IRQ counters */ +volatile uint32_t gPruSddfIrqCnt=0; /* PRU SDDF FW IRQ count */ +volatile uint32_t gEpwmIsrCnt=0; /* EPWM0 IRQ count */ + +/*PWM Parameters*/ +HwiP_Params hwiPrms; +EPwmCfgPrms_t epwmCfgPrms; + +void init_pwm() +{ + int32_t status; + /* Initialize EPWM0 base address, perform address translation */ + gEpwm0BaseAddr = (uint32_t)AddrTranslateP_getLocalAddr(CONFIG_EPWM0_BASE_ADDR); + + /* Register & enable EPWM0 interrupt */ + HwiP_Params_init(&hwiPrms); + hwiPrms.intNum = CONFIG_EPWM0_INTR; + hwiPrms.callback = &epwmIrqHandler; + hwiPrms.args = 0; + hwiPrms.isPulse = CONFIG_EPWM0_INTR_IS_PULSE; + hwiPrms.isFIQ = FALSE; + status = HwiP_construct(&gEpwm0HwiObject, &hwiPrms); + DebugP_assert(status == SystemP_SUCCESS); + + /* Configure EPWM0 */ + epwmCfgPrms.epwmId = EPWM_ID_0; + epwmCfgPrms.epwmBaseAddr = gEpwm0BaseAddr; + epwmCfgPrms.epwmOutChEn = APP_EPWM_OUT_CH_EN; + epwmCfgPrms.hspClkDiv = APP_EPWM_FCLK_HSPCLKDIV; + epwmCfgPrms.clkDiv = APP_EPWM_FCLK_CLKDIV; + epwmCfgPrms.epwmTbFreq = APP_EPWM_TB_FREQ; + epwmCfgPrms.epwmOutFreq = gEpwmOutFreq; + epwmCfgPrms.epwmDutyCycle[EPWM_OUTPUT_CH_A] = APP_EPWM0_DUTY_CYCLE; + epwmCfgPrms.epwmTbCounterDir = APP_EPWM_TB_COUNTER_DIR; + epwmCfgPrms.cfgTbSyncIn = TRUE; + epwmCfgPrms.tbPhsValue = 0; + epwmCfgPrms.tbSyncInCounterDir = EPWM_TB_COUNTER_DIR_UP; + epwmCfgPrms.cfgTbSyncOut = TRUE; + epwmCfgPrms.tbSyncOutMode = EPWM_TB_SYNC_OUT_EVT_CNT_EQ_ZERO; + epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].zeroAction = EPWM_AQ_ACTION_DONOTHING; + epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].prdAction = EPWM_AQ_ACTION_DONOTHING; + epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpAUpAction = EPWM_AQ_ACTION_HIGH; + epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpADownAction = EPWM_AQ_ACTION_LOW; + epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpBUpAction = EPWM_AQ_ACTION_DONOTHING; + epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpBDownAction = EPWM_AQ_ACTION_DONOTHING; + epwmCfgPrms.cfgDb = FALSE; + epwmCfgPrms.cfgEt = TRUE; + epwmCfgPrms.intSel = EPWM_ET_INTR_EVT_CNT_EQ_ZRO; + epwmCfgPrms.intPrd = EPWM_ET_INTR_PERIOD_FIRST_EVT; + hEpwm0 = epwmInit(&epwmCfgPrms, &gEpwm0Obj); + DebugP_assert(hEpwm0 != NULL); + +} + +void init_sdfm() +{ + int32_t status; + /* Initialize ICSSG */ + status = initIcss(TEST_ICSSG_INST_ID, TEST_ICSSG_SLICE_ID, PRUICSS_G_MUX_EN, &gPruIcssHandle); + if (status != SDDF_ERR_NERR) { + DebugP_log("Error: initIcss() fail.\r\n"); + return; + } + + /* Register & enable ICSSG PRU SDDF FW interrupt */ + HwiP_Params_init(&hwiPrms); + hwiPrms.intNum = ICSSG_PRU_SDDF_INT_NUM; + hwiPrms.callback = &pruSddfIrqHandler; + hwiPrms.args = 0; + hwiPrms.isPulse = FALSE; + hwiPrms.isFIQ = FALSE; + status = HwiP_construct(&gIcssgPruSddfHwiObject, &hwiPrms); + DebugP_assert(status == SystemP_SUCCESS); + + /* Initialize PRU core for SDDF */ + status = initPruSddf(gPruIcssHandle, TEST_PRU_INST_ID, &gTestSddfPrms, &gHPruSddf); + if (status != SDDF_ERR_NERR) { + DebugP_log("Error: initPruSddf() fail.\r\n"); + return; + } + +} +void sddf_main(void *args) +{ + + /* Open drivers to open the UART driver for console */ + Drivers_open(); + Board_driversOpen(); + + DebugP_log("Sample SDFM example running!...\r\n"); + + /* Output build time */ + DebugP_log("Build timestamp : %s %s\r\n", __DATE__, __TIME__); + + + /* Enable EPWM0-2 on 3-axis Breakout Board */ + GPIO_setDirMode(gMtr1PwnEnGpioBaseAddr, gMtr1PwnEnGpioPin, gMtr1PwnEnGpioPinDir); + GPIO_pinWriteHigh(gMtr1PwnEnGpioBaseAddr, gMtr1PwnEnGpioPin); + GPIO_pinWriteLow(gMtr1PwnEnGpioBaseAddr, gMtr1PwnEnGpioPin); + + /* + * Configure EPWM0 + */ + init_pwm(); + DebugP_log("EPWM Configured!\r\n"); + /* + * Configure SDDF + */ + + /* Configure SOC pads for SDDF. + Normally handled via Pinmux_init(), + but currently no way to pads for ICSSG from Sysconfig. */ + cfgPad(); + + /* Configure SDFM */ + init_sdfm(); + DebugP_log("SDFM Configured!\r\n"); + + /* Start EPWM0 clock */ + CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN, 1); + + /* Force SW sync for EPWM0 */ + EPWM_tbTriggerSwSync(gEpwm0BaseAddr); + + while(gRunFlag == TRUE) + { + ; + } + + /* Disable and clear interrupts for EPWM0 */ + EPWM_etIntrDisable(gEpwm0BaseAddr); /* Disable interrupts */ + EPWM_etIntrClear(gEpwm0BaseAddr); /* Clear pending interrupts */ + + /* Destroy EPWM0 HWI */ + HwiP_destruct(&gEpwm0HwiObject); + + /* Destroy PRU SDDF HWI */ + HwiP_destruct(&gIcssgPruSddfHwiObject); + + /* Destroy RTU SDDF HWI */ + //HwiP_destruct(&gIcssgRtuSddfHwiObject); + + DebugP_log("All tests have passed!!\r\n"); + + Board_driversClose(); + Drivers_close(); +} + +/* PRU SDDF FW IRQ handler */ +void pruSddfIrqHandler(void *args) +{ + /* debug, inncrement PRU SDDF IRQ count */ + gPruSddfIrqCnt++; + /* Clear interrupt at source */ + /* Write 18 to ICSSG_STATUS_CLR_INDEX_REG + Firmware: TRIGGER_HOST_SDDF_IRQ defined as 18 + 18 = 16+2, 2 is Host Interrupt Number. See AM64x TRM. + */ + PRUICSS_clearEvent(gPruIcssHandle, PRU_TRIGGER_HOST_SDDF_EVT); + + /* SDFM Output sample for Channel 0 */ + sdfm_ch0_samples[sdfm_ch0_idx++] = SDFM_getFilterData(0); + /* SDFM Output sample for Channel 1 */ + sdfm_ch1_samples[sdfm_ch1_idx++] = SDFM_getFilterData(1); + /* SDFM Output sample for Channel 2 */ + sdfm_ch2_samples[sdfm_ch2_idx++] = SDFM_getFilterData(2); + + + if(sdfm_ch0_idx >= MAX_SAMPLES) + { + sdfm_ch0_idx = 0; + sdfm_ch1_idx = 0; + sdfm_ch2_idx = 0; + } + + +} + + +/* EPWM0 IRQ handler */ +static void epwmIrqHandler(void *args) +{ + volatile uint16_t status; + + /* debug, inncrement EPWM0 IRQ count */ + gEpwmIsrCnt++; + + status = EPWM_etIntrStatus(gEpwm0BaseAddr); + if (status & EPWM_ETFLG_INT_MASK) { + EPWM_etIntrClear(gEpwm0BaseAddr); + } + return; +} diff --git a/examples/motor_control/icss_sdfm/cfg_pad.c b/examples/motor_control/icss_sdfm/cfg_pad.c new file mode 100644 index 0000000..e1ff722 --- /dev/null +++ b/examples/motor_control/icss_sdfm/cfg_pad.c @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "cfg_pad.h" + +static Pinmux_PerCfg_t gPinMuxMainDomainCfgSddf[] = { + + /* PRG0_ECAP0_IN_APWM_OUT, + PRG0_PRU1_GPO15, PRG0_ECAP0_IN_APWM_OUT, U5, J2.C11 */ + { + PIN_PRG0_PRU1_GPO15, + ( PIN_MODE(10) | PIN_PULL_DISABLE ) + }, + /* SD8_CLK, + PRG0_PRU0_GPI16, SD8_CLK, U4, J2E:P9 */ + { + PIN_PRG0_PRU0_GPO16, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + /* SD0_D, + PRG0_PRU0_GPI1, SD0_D, R4, J2E:P8 */ + { + PIN_PRG0_PRU0_GPO1, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + /* SD1_D, + PRG0_PRU0_GPI3, SD1_D, V2, J2A:P9 */ + { + PIN_PRG0_PRU0_GPO3, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + /* SD2_D, + PRG0_PRU0_GPI5, SD2_D, R3, J2C:P6 */ + { + PIN_PRG0_PRU0_GPO5, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + /* SD3_D, + PRG0_PRU0_GPI7, SD3_D, T1, J2B:P7 */ + { + PIN_PRG0_PRU0_GPO7, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + /* SD4_D, + PRG0_PRU0_GPI18, SD4_D, V1, J2B:P9 */ + { + PIN_PRG0_PRU0_GPO18, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + /* SD5_D, + PRG0_PRU0_GPI11, SD5_D, Y3, J2B:P14 */ + { + PIN_PRG0_PRU0_GPO11, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + /* SD6_D, + PRG0_PRU0_GPI13, SD6_D, R6, J2C:P5 */ + { + PIN_PRG0_PRU0_GPO13, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + /* SD7_D, + PRG0_PRU0_GPI15, SD7_D, T5, J2D:P12 */ + { + PIN_PRG0_PRU0_GPO15, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + /* SD8_D, + PRG0_PRU0_GPI17, SD8_D, U1, J2B:P8 */ + { + PIN_PRG0_PRU0_GPO17, + ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE ) + }, + + {PINMUX_END, PINMUX_END} +}; + +/* Configure SOC pads */ +void cfgPad(void) +{ + Pinmux_config(gPinMuxMainDomainCfgSddf, PINMUX_DOMAIN_ID_MAIN); +} diff --git a/examples/motor_control/icss_sdfm/cfg_pad.h b/examples/motor_control/icss_sdfm/cfg_pad.h new file mode 100644 index 0000000..31acbcc --- /dev/null +++ b/examples/motor_control/icss_sdfm/cfg_pad.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CFG_PAD_H_ +#define _CFG_PAD_H_ + +/* Configure SOC pads. + Normally handled via Pinmux_init(), + but currently no way to pads for ICSSG from Sysconfig. */ +void cfgPad(void); + +#endif /* _CFG_PAD_H_ */ diff --git a/examples/motor_control/icss_sdfm/epwm_dc.c b/examples/motor_control/icss_sdfm/epwm_dc.c new file mode 100644 index 0000000..4217fd6 --- /dev/null +++ b/examples/motor_control/icss_sdfm/epwm_dc.c @@ -0,0 +1,306 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "epwm_drv_aux.h" +#include "epwm_mod.h" +#include "epwm_dc.h" + +Epwm_Handle epwmInit( + EPwmCfgPrms_t *pEpwmCfgPrms, + EPwmObj_t *pEpwmObj +) +{ + Epwm_Handle hEpwm; /* EPWM handle */ + uint32_t epwmBaseAddr; /* EPWM base address */ + uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */ + uint32_t epwmTbFreq; /* EPWM time base clock */ + uint32_t epwmOutFreq; /* EPWM output frequency */ + uint32_t epwmTbCounterDir; /* EPWM TB counter direction */ + uint32_t epwmPrdVal; + uint32_t epwmCmpAVal, epwmCmpBVal; + + /* Get configuration parameters */ + epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr; + epwmOutChEn = pEpwmCfgPrms->epwmOutChEn; + epwmTbFreq = pEpwmCfgPrms->epwmTbFreq; + epwmOutFreq = pEpwmCfgPrms->epwmOutFreq; + epwmTbCounterDir = pEpwmCfgPrms->epwmTbCounterDir; + + /* Configure Time Base submodule */ + writeTbClkDiv(epwmBaseAddr, pEpwmCfgPrms->hspClkDiv, pEpwmCfgPrms->clkDiv); + tbPwmFreqCfg(epwmBaseAddr, epwmTbFreq, epwmOutFreq, + epwmTbCounterDir, EPWM_SHADOW_REG_CTRL_ENABLE, &epwmPrdVal); + + /* Configure TB Sync In Mode */ + if (pEpwmCfgPrms->cfgTbSyncIn == FALSE) { + EPWM_tbSyncDisable(epwmBaseAddr); + } + else { + EPWM_tbSyncEnable(epwmBaseAddr, pEpwmCfgPrms->tbPhsValue, pEpwmCfgPrms->tbSyncInCounterDir); + } + + /* Configure TB Sync Out Mode */ + if (pEpwmCfgPrms->cfgTbSyncOut == FALSE) { + EPWM_tbSetSyncOutMode(epwmBaseAddr, EPWM_TB_SYNC_OUT_EVT_DISABLE ); + } + else { + EPWM_tbSetSyncOutMode(epwmBaseAddr, pEpwmCfgPrms->tbSyncOutMode); + } + + /* Configure emulation mode */ + EPWM_tbSetEmulationMode(epwmBaseAddr, EPWM_TB_EMU_MODE_FREE_RUN); + + if ((epwmOutChEn >> 0) & 0x1) { + /* + * COMPA value - this determines the duty cycle + * COMPA = (PRD - ((dutycycle * PRD) / 100) + */ + epwmCmpAVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A] * epwmPrdVal) / 100U)); + //epwmCmpAVal = 1; // FL: force max duty cycle just before 100% DC to see where EPWM period occurs + + /* Configure counter compare submodule */ + EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_A, + epwmCmpAVal, EPWM_SHADOW_REG_CTRL_ENABLE, + EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE); + /* Configure Action Qualifier Submodule */ + EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_A, + &pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_A]); + } + + if ((epwmOutChEn >> 1) & 0x1) { + /* + * COMPB value - this determines the duty cycle + * COMPB = (PRD - ((dutycycle * PRD) / 100) + */ + epwmCmpBVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B] * epwmPrdVal) / 100U)); + + /* Configure counter compare submodule */ + EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_B, + epwmCmpBVal, EPWM_SHADOW_REG_CTRL_ENABLE, + EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE); + /* Configure Action Qualifier Submodule */ + EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_B, + &pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_B]); + } + + if (pEpwmCfgPrms->cfgDb == TRUE) { + /* Configure Dead Band Submodule */ + EPWM_deadbandCfg(epwmBaseAddr, &pEpwmCfgPrms->dbCfg); + } + else { + /* Configure Dead Band Submodule */ + EPWM_deadbandBypass(epwmBaseAddr); + } + + /* Configure Chopper Submodule */ + EPWM_chopperEnable(epwmBaseAddr, FALSE); + + /* Configure trip zone Submodule */ + EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_ONE_SHOT, 0U); + EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_CYCLE_BY_CYCLE, 0U); + + if (pEpwmCfgPrms->cfgEt == TRUE) { + /* Configure event trigger Submodule */ + EPWM_etIntrCfg(epwmBaseAddr, pEpwmCfgPrms->intSel, + pEpwmCfgPrms->intPrd); + EPWM_etIntrEnable(epwmBaseAddr); + } + + /* Init PWM object */ + hEpwm = (Epwm_Handle)pEpwmObj; + hEpwm->epwmId = pEpwmCfgPrms->epwmId; + hEpwm->epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr; + hEpwm->epwmOutChEn = pEpwmCfgPrms->epwmOutChEn; + hEpwm->hspClkDiv = pEpwmCfgPrms->hspClkDiv; + hEpwm->clkDiv = pEpwmCfgPrms->clkDiv; + hEpwm->epwmTbFreq = pEpwmCfgPrms->epwmTbFreq; + hEpwm->epwmOutFreq = pEpwmCfgPrms->epwmOutFreq; + hEpwm->epwmPrdVal = epwmPrdVal; + hEpwm->toggleEpwmPrd = FALSE; + hEpwm->toggleEpwmPrdState = 0; + hEpwm->epwmPrdValL = 0; + hEpwm->epwmPrdValU = 0; + if ((epwmOutChEn >> 0) & 0x1) { + hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_A] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A]; + hEpwm->cmpAVal = epwmCmpAVal; + hEpwm->cmpANzToZ = FALSE; + hEpwm->cmpAZToNz = FALSE; + } + if ((epwmOutChEn >> 1) & 0x1) { + hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_B] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B]; + hEpwm->cmpBVal = epwmCmpBVal; + hEpwm->cmpBNzToZ = FALSE; + hEpwm->cmpBZToNz = FALSE; + } + + return hEpwm; +} + +/* Update EPWM period */ +int32_t epwmUpdatePrd( + Epwm_Handle hEpwm, + uint32_t epwmOutFreqSet +) +{ + float epwmPrdVal_f; + uint32_t epwmPrdVal; + uint32_t rem; + + /* Check for EPWM period toggle */ + if (hEpwm->toggleEpwmPrd == TRUE) { + hEpwm->epwmPrdVal = (hEpwm->toggleEpwmPrdState == 0) ? hEpwm->epwmPrdValL : hEpwm->epwmPrdValU; + hEpwm->toggleEpwmPrdState ^= 0x1; + + /* Write next period count */ + writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal); + } + + /* Check for PWM frequency change */ + if (hEpwm->epwmOutFreq != epwmOutFreqSet) { + epwmPrdVal_f = (float)hEpwm->epwmTbFreq / epwmOutFreqSet; + epwmPrdVal_f = roundf(epwmPrdVal_f); + + epwmPrdVal = (uint32_t)epwmPrdVal_f; + rem = epwmPrdVal - epwmPrdVal/2*2; + if (rem == 0) { + /* Period is divisible by 2, + alternating period not employed */ + hEpwm->toggleEpwmPrd = FALSE; + hEpwm->toggleEpwmPrdState = 0; + hEpwm->epwmPrdValL = 0; + hEpwm->epwmPrdValU = 0; + hEpwm->epwmPrdVal = epwmPrdVal/2; + } else { + /* Period is not divisible by 2, + alternating period employed to provide correct average EPWM frequency: + EPWM period 2*n : TBPRD <- 'Lower' period + EPWM period 2*n+1 : TBPRD <- 'Upper' period + */ + hEpwm->toggleEpwmPrd = TRUE; + hEpwm->toggleEpwmPrdState = 1; + hEpwm->epwmPrdValL = epwmPrdVal/2; + hEpwm->epwmPrdValU = epwmPrdVal/2+1; + hEpwm->epwmPrdVal = hEpwm->epwmPrdValL; + } + + /* Write next period count */ + writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal); + + hEpwm->epwmOutFreq = epwmOutFreqSet; + } + + return EPWM_DC_SOK; +} + +/* Update EPWM A/B outputs */ +int32_t epwmUpdateOut( + Epwm_Handle hEpwm, + float VrefA, + float VrefB +) +{ + float dcVal; /* EPWM duty cycle value */ + uint16_t cmpVal; /* EPWM CMP value */ + + if ((hEpwm->epwmOutChEn >> 0) & 0x1) { + /* Compute next Duty Cycle and CMP values */ + computeCmpx(VrefA, hEpwm->epwmPrdVal, &dcVal, &cmpVal); + + /* Write next CMPA value */ + writeCmpA(hEpwm->epwmBaseAddr, cmpVal); + + /* EPWM 100% Duty Cycle */ + /* Handle transition to 100% Duty Cycle */ + if (hEpwm->cmpANzToZ == TRUE) { + /* restore original AQ */ + cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); + hEpwm->cmpANzToZ = FALSE; + } + if ((hEpwm->cmpAVal != 0) && (cmpVal == 0)) { + /* set AQ to set for next period */ + cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH); + hEpwm->cmpANzToZ = TRUE; + } + + /* Handle transition from 100% Duty Cycle */ + if (hEpwm->cmpAZToNz == TRUE) { + /* restore original AQ */ + cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); + hEpwm->cmpAZToNz = FALSE; + } + if ((hEpwm->cmpAVal == 0) && (cmpVal != 0)) { + /* set AQ to clear for next period */ + cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW); + hEpwm->cmpAZToNz = TRUE; + } + hEpwm->cmpAVal = cmpVal; + } + + if ((hEpwm->epwmOutChEn >> 1) & 0x1) { + /* Compute next Duty Cycle and CMP values */ + computeCmpx(VrefB, hEpwm->epwmPrdVal, &dcVal, &cmpVal); + + /* Write next CMPB value */ + writeCmpB(hEpwm->epwmBaseAddr, cmpVal); + + /* EPWM 100% Duty Cycle */ + /* Handle transition to 100% Duty Cycle */ + if (hEpwm->cmpBNzToZ == TRUE) { + /* restore original AQ */ + cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); + hEpwm->cmpBNzToZ = FALSE; + } + if ((hEpwm->cmpBVal != 0) && (cmpVal == 0)) { + /* set AQ to set for next period */ + cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH); + hEpwm->cmpBNzToZ = TRUE; + } + + /* Handle transition from 100% Duty Cycle */ + if (hEpwm->cmpBZToNz == TRUE) { + /* restore original AQ */ + cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); + hEpwm->cmpBZToNz = FALSE; + } + if ((hEpwm->cmpBVal == 0) && (cmpVal != 0)) { + /* set AQ to clear for next period */ + cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW); + hEpwm->cmpBZToNz = TRUE; + } + hEpwm->cmpBVal = cmpVal; + } + + return EPWM_DC_SOK; +} diff --git a/examples/motor_control/icss_sdfm/epwm_dc.h b/examples/motor_control/icss_sdfm/epwm_dc.h new file mode 100644 index 0000000..077f5a5 --- /dev/null +++ b/examples/motor_control/icss_sdfm/epwm_dc.h @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _EPWM_DC_H_ +#define _EPWM_DC_H_ + +#include +#include +#include + +/* Status return values */ +#define EPWM_DC_SOK ( 0 ) + +#define EPWM_ID_0 ( 0 ) +#define EPWM_ID_1 ( 1 ) +#define EPWM_ID_2 ( 2 ) + +#define EPWM_NUM_OUT_CH ( EPWM_OUTPUT_CH_MAX + 1 ) + +/* EPWM configuration parameters */ +typedef struct _EPwmCfgPrms_t +{ + uint32_t epwmId; /* EPWM ID */ + uint32_t epwmBaseAddr; /* EPWM base address */ + uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */ + uint32_t hspClkDiv; /* EPWM High-Speed Time-base Clock Prescale Bits */ + uint32_t clkDiv; /* EPWM Time-base Clock Prescale Bits */ + uint32_t epwmTbFreq; /* EPWM timebase clock */ + uint32_t epwmOutFreq; /* EPWM output frequency */ + /* EPWM duty cycle */ + uint32_t epwmDutyCycle[EPWM_NUM_OUT_CH]; + uint32_t epwmTbCounterDir; /* EPWM counter direction (Up, Down, Up/Down) */ + + /* TB sync in config */ + Bool cfgTbSyncIn; /* config TB sync in flag (true/false) */ + uint32_t tbPhsValue; /* cfgTbSyncIn==TRUE: timer phase value to load on Sync In event */ + uint32_t tbSyncInCounterDir; /* cfgTbSyncIn==TRUE: counter direction on Sync In event */ + + /* TB sync out config */ + Bool cfgTbSyncOut; /* config TB sync output flag (true/false) */ + uint32_t tbSyncOutMode; /* cfgTbSyncOut==TRUE: Sync Out mode */ + + /* AQ config */ + EPWM_AqActionCfg aqCfg[EPWM_NUM_OUT_CH]; + + /* DB config */ + Bool cfgDb; /* config DB flag (true/false) */ + EPWM_DeadbandCfg dbCfg; /* Deadband config */ + + /* ET config */ + Bool cfgEt; /* config ET module */ + uint32_t intSel; /* ET interrupt select */ + uint32_t intPrd; /* ET interrupt period */ +} EPwmCfgPrms_t; + +/* EPWM object */ +typedef struct _EPwmObj_t +{ + uint32_t epwmId; /* EPWM ID */ + uint32_t epwmBaseAddr; /* EPWM base address */ + uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */ + uint32_t hspClkDiv; /* EPWM High-Speed Time-base Clock Prescale Bits */ + uint32_t clkDiv; /* EPWM Time-base Clock Prescale Bits */ + uint32_t epwmTbFreq; /* EPWM timebase clock */ + uint32_t epwmOutFreq; /* EPWM output frequency */ + /* EPWM duty cycle */ + uint32_t epwmDutyCycle[EPWM_NUM_OUT_CH]; + + uint32_t epwmPrdVal; /* EPWM period value */ + +// Bool updateOut; /* Flag indicates whether to update EPWM A/B outputs */ + + /* For handling up-down count alternating period + when period isn't divisible by 2 */ + Bool toggleEpwmPrd; /* Flag for EPWM in alternating period mode */ + uint8_t toggleEpwmPrdState; /* Alternating period state: + 'Lower' or 'Upper' period written on alternate ISRs */ + uint32_t epwmPrdValL; /* 'Lower' EPWM period value written in 'Lower' state */ + uint32_t epwmPrdValU; /* 'Upper' EPWM period value written in 'Upper' state */ + + /* For handling ChA 100% Duty Cycle */ + uint32_t cmpAVal; /* Current CMPA value */ + Bool cmpANzToZ; /* Flag for EPWM transition CMPA!=0 to CMPA=0 */ + Bool cmpAZToNz; /* Flag for EPWM transition CMPA=0 to CMPA!=0 */ + + /* For handling ChB 100% Duty Cycle */ + uint32_t cmpBVal; /* Current CMPB value */ + Bool cmpBNzToZ; /* Flag for EPWM transition CMPB!=0 to CMPB=0 */ + Bool cmpBZToNz; /* Flag for EPWM transition CMPB=0 to CMPB!=0 */ +} EPwmObj_t; + +/* EPWM Handle */ +typedef EPwmObj_t * Epwm_Handle; + +/* Initialize EPWM */ +Epwm_Handle epwmInit( + EPwmCfgPrms_t *pEpwmCfgPrms, + EPwmObj_t *pEpwmObj +); + +/* Update EPWM period */ +int32_t epwmUpdatePrd( + Epwm_Handle hEpwm, + uint32_t epwmOutFreqSet +); + +/* Update EPWM A/B outputs */ +int32_t epwmUpdateOut( + Epwm_Handle hEpwm, + float VrefA, + float VrefB +); + +#endif /* _EPWM_DC_H_ */ diff --git a/examples/motor_control/icss_sdfm/epwm_drv_aux.c b/examples/motor_control/icss_sdfm/epwm_drv_aux.c new file mode 100644 index 0000000..1b240d3 --- /dev/null +++ b/examples/motor_control/icss_sdfm/epwm_drv_aux.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "epwm_drv_aux.h" + +#include + +/* Configure PWM Time base counter Frequency/Period */ +void tbPwmFreqCfg( + uint32_t baseAddr, + uint32_t tbClk, + uint32_t pwmFreq, + uint32_t counterDir, + uint32_t enableShadowWrite, + uint32_t *pPeriodCount +) +{ + uint32_t tbPeriodCount; + float tbPeriodCount_f; + uint32_t regVal = 0U; + + regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL); + HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_PRDLD, enableShadowWrite); + HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CTRMODE, counterDir); + HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), + (uint16_t)regVal); + + /* compute period using floating point */ + tbPeriodCount_f = (float)tbClk / pwmFreq; + if (EPWM_TB_COUNTER_DIR_UP_DOWN == counterDir) { + tbPeriodCount_f = tbPeriodCount_f / 2.0; + } + tbPeriodCount_f = roundf(tbPeriodCount_f); + tbPeriodCount = (uint32_t)tbPeriodCount_f; + +#if 0 /* use this in case there is some reason not to use floating point */ + /* compute period using fixed point */ + tbPeriodCount = tbClk << 4; /* U32Q4 */ + tbPeriodCount /= pwmFreq; + if (EPWM_TB_COUNTER_DIR_UP_DOWN == counterDir) { + tbPeriodCount /= 2; + } + tbPeriodCount += 1<<3; /* biased rouding to 0.5 */ + tbPeriodCount >>= 4; /* U32Q0 */ +#endif + + regVal = (counterDir == EPWM_TB_COUNTER_DIR_UP_DOWN) ? + tbPeriodCount : tbPeriodCount-1; + HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPRD), + (uint16_t)regVal); + + *pPeriodCount = tbPeriodCount; +} diff --git a/examples/motor_control/icss_sdfm/epwm_drv_aux.h b/examples/motor_control/icss_sdfm/epwm_drv_aux.h new file mode 100644 index 0000000..39a992e --- /dev/null +++ b/examples/motor_control/icss_sdfm/epwm_drv_aux.h @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _EPWM_DRV_AUX_H_ +#define _EPWM_DRV_AUX_H_ + +#include +#include +#include + +/* Write EPWM CMPA */ +static inline void writeCmpA( + uint32_t baseAddr, + uint32_t cmpVal +) +{ + HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA, + (uint16_t)cmpVal); +} + +/* Write EPWM CMPB */ +static inline void writeCmpB( + uint32_t baseAddr, + uint32_t cmpVal +) +{ + HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB, + (uint16_t)cmpVal); +} + +/* Write EPWM CMPA/CMPB */ +static inline void writeCmpAB( + uint32_t baseAddr, + uint32_t cmpAVal, + uint32_t cmpBVal +) +{ + /* Write CMPA */ + HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA, + (uint16_t)cmpAVal); + + /* Write CMPB */ + HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB, + (uint16_t)cmpBVal); +} + +/* Configure Output ChannelA AQ Zero */ +static inline void cfgOutChAAqZero( + uint32_t baseAddr, + uint32_t zeroAction +) +{ + uint32_t regVal = 0U; + + regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); + HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_ZRO, zeroAction); + HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); +} + +/* Configure Output ChannelA AQ CMPA Up */ +static inline void cfgOutChAAqCAU( + uint32_t baseAddr, + uint32_t cmpAUpAction +) +{ + uint32_t regVal = 0U; + + regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); + HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAU, cmpAUpAction); + HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); +}; + +/* Configure Output ChannelA AQ CMPA Down */ +static inline void cfgOutChAAqCAD( + uint32_t baseAddr, + uint32_t cmpADownAction +) +{ + uint32_t regVal = 0U; + + regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); + HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAD, cmpADownAction); + HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); +} + +/* Configure Output ChannelB AQ Zero */ +static inline void cfgOutChBAqZero( + uint32_t baseAddr, + uint32_t zeroAction +) +{ + uint32_t regVal = 0U; + + regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLB); + HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLB_ZRO, zeroAction); + HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLB), (uint16_t)regVal); +} + +/* Configure Output ChannelA AQ CMPB Up */ +static inline void cfgOutChAAqCBU( + uint32_t baseAddr, + uint32_t cmpBUpAction +) +{ + uint32_t regVal = 0U; + + regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); + HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CBU, cmpBUpAction); + HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); +} + +/* Write TB Period */ +static inline void writeTbPrd( + uint32_t baseAddr, + uint32_t tbPeriodCount +) +{ + HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPRD), (uint16_t)tbPeriodCount); +} + +/* Write TB Phase */ +static inline void writeTbPhase( + uint32_t baseAddr, + uint32_t tbPhsValue +) +{ + HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPHS), (uint16_t)tbPhsValue); +} + +/* Write TBCTL HSPDIV & CLKDIV */ +static inline void writeTbClkDiv( + uint32_t baseAddr, + uint32_t hspClkDiv, + uint32_t clkDiv +) +{ + uint32_t regVal = 0U; + + regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL); + HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CLKDIV, clkDiv); + HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_HSPCLKDIV, hspClkDiv); + HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal); +} + +/* Write TBCTL CTRMODE */ +static inline void writeTbCtrMode( + uint32_t baseAddr, + uint32_t ctrMode +) +{ + uint32_t regVal = 0U; + + regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL); + HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CTRMODE, ctrMode); + HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal); +} + +/* Configure PWM Time base counter Frequency/Period */ +void tbPwmFreqCfg( + uint32_t baseAddr, + uint32_t tbClk, + uint32_t pwmFreq, + uint32_t counterDir, + uint32_t enableShadowWrite, + uint32_t *pPeriodCount +); + +#endif /* _EPWM_DRV_AUX_H_ */ diff --git a/examples/motor_control/icss_sdfm/epwm_mod.c b/examples/motor_control/icss_sdfm/epwm_mod.c new file mode 100644 index 0000000..7a13302 --- /dev/null +++ b/examples/motor_control/icss_sdfm/epwm_mod.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "epwm_mod.h" + +#include +#include + + +/* Min / max output amplitude. + Waveform amplitude values beyond these thresholds are saturated. */ +#define VREF_MAX ( 1.0f ) +#define VREF_MIN ( -1.0f ) + +/* Compute Duty Cycle & CMPx given Vref & EPWM period */ +void computeCmpx( + float Vref, + uint32_t epwmPrdVal, + float *pEpwmDutyCycle, + uint16_t *pEpwmCmpVal +) +{ + float dc_f; + float cmp_f; + uint16_t cmp; + + if (Vref >= VREF_MAX) { + /* 100% duty cycle */ + dc_f = 1.0; + } + else if (Vref <= VREF_MIN) { + /* 0% duty cycle */ + dc_f = 0.0; + } + else { + /* compute Duty Cycle */ + dc_f = 0.5*(Vref + 1.0); + } + + /* compute CMPx */ + cmp_f = (1.0 - dc_f)*epwmPrdVal; /* up-down count */ + cmp = (uint16_t)roundf(cmp_f); + + *pEpwmDutyCycle = dc_f; + *pEpwmCmpVal = cmp; +} diff --git a/examples/motor_control/icss_sdfm/epwm_mod.h b/examples/motor_control/icss_sdfm/epwm_mod.h new file mode 100644 index 0000000..8f9506e --- /dev/null +++ b/examples/motor_control/icss_sdfm/epwm_mod.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _EPWM_MOD_H_ +#define _EPWM_MOD_H_ + +#include + +/* Compute Duty Cycle & CMPx given Vref */ +void computeCmpx( + float Vref, + uint32_t epwmPrdVal, + float *pEpwmDutyCycle, + uint16_t *pEpwmCmpVal +); + +#endif /* _EPWM_MOD_H_ */ diff --git a/examples/motor_control/icss_sdfm/sddf.c b/examples/motor_control/icss_sdfm/sddf.c new file mode 100644 index 0000000..127f411 --- /dev/null +++ b/examples/motor_control/icss_sdfm/sddf.c @@ -0,0 +1,340 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_drivers_open_close.h" +#include "ti_board_open_close.h" + +#include +#include +#include +#include + +#include "tisddf_pruss_intc_mapping.h" /* INTC configuration */ +#include "motor_control/current_sense/sdfm/firmware/sdfm_bin.h" /* SDDF image data */ +#include "sddf.h" +#include "motor_control/current_sense/sdfm/include/sddf_api.h" +/* PRU SDDF FW image info */ +typedef struct PRUSDDF_PruFwImageInfo_s { + const uint32_t *pPruImemImg; + const uint32_t pruImemImgSz; +} PRUSDDF_PruFwImageInfo; + +/* Number of PRU images */ +#define PRU_SDDF_NUM_PRU_IMAGE ( 3 ) + +/* PRU SDDF image info */ +static PRUSDDF_PruFwImageInfo gPruFwImageInfo[PRU_SDDF_NUM_PRU_IMAGE] = +{ + {pru_SDDF_PRU0_image_0, sizeof(pru_SDDF_PRU0_image_0)}, /* PRU FW */ + {NULL, 0} +}; + +/* ICSS INTC configuration */ +static const PRUICSS_IntcInitData gPruicssIntcInitdata = PRUICSS_INTC_INITDATA; + +/* + * ======== initIcss ======== + */ +/* Initialize ICSSG */ +int32_t initIcss( + uint8_t icssInstId, + uint8_t sliceId, + uint8_t saMuxMode, + PRUICSS_Handle *pPruIcssHandle +) +{ + PRUICSS_Handle pruIcssHandle; + int32_t size; + int32_t status; + + /* Open ICSS PRU instance */ + pruIcssHandle = PRUICSS_open(icssInstId); + if (pruIcssHandle == NULL) { + return SDDF_ERR_INIT_ICSSG; + } + + /* Disable slice PRU cores */ + if (sliceId == ICSSG_SLICE_ID_0) + { + status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU0); + if (status != SystemP_SUCCESS) { + return SDDF_ERR_INIT_ICSSG; + } + } + else if (sliceId == ICSSG_SLICE_ID_1) + { + status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU1); + if (status != SystemP_SUCCESS) { + return SDDF_ERR_INIT_ICSSG; + } + } + else + { + return SDDF_ERR_INIT_ICSSG; + } + + /* Reset slice memories */ + size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_IRAM_PRU(sliceId)); + if (size == 0) + { + return SDDF_ERR_INIT_ICSSG; + } + size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_DATARAM(sliceId)); + if (size == 0) + { + return SDDF_ERR_INIT_ICSSG; + } + + /* Set ICSS pin mux */ + PRUICSS_setSaMuxMode(pruIcssHandle, saMuxMode); + + /* Initialize ICSS INTC */ + status = PRUICSS_intcInit(pruIcssHandle, &gPruicssIntcInitdata); + if (status != SystemP_SUCCESS) { + return SDDF_ERR_INIT_ICSSG; + } + + *pPruIcssHandle = pruIcssHandle; + + return SDDF_ERR_NERR; +} +void sdfm_configure_gpio_pin(sdfm_handle h_sdfm) +{ + /*ch0 GPIO configuration*/ + uint32_t gpioBaseAddrCh0Hi = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_HIGH_TH_CH0_BASE_ADDR); + uint32_t pinNumCh0Hi = GPIO_HIGH_TH_CH0_PIN; + GPIO_setDirMode(gpioBaseAddrCh0Hi, pinNumCh0Hi, GPIO_HIGH_TH_CH0_DIR); + SDFM_configComparatorGpioPins(h_sdfm, 0, gpioBaseAddrCh0Hi, pinNumCh0Hi, 0); + + uint32_t gpioBaseAddrCh0Lo = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_LOW_TH_CH0_BASE_ADDR); + uint32_t pinNumCh0Lo = GPIO_LOW_TH_CH0_PIN; + GPIO_setDirMode(gpioBaseAddrCh0Lo, pinNumCh0Lo, GPIO_LOW_TH_CH0_DIR); + SDFM_configComparatorGpioPins(h_sdfm, 0, gpioBaseAddrCh0Lo, pinNumCh0Lo, 1); + + + /*ch1 GPIO configuration*/ + uint32_t gpioBaseAddrCh1Hi = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_HIGH_TH_CH1_BASE_ADDR); + uint32_t pinNumCh1Hi = GPIO_HIGH_TH_CH1_PIN; + GPIO_setDirMode(gpioBaseAddrCh1Hi, pinNumCh1Hi, GPIO_HIGH_TH_CH1_DIR); + SDFM_configComparatorGpioPins(h_sdfm, 1, gpioBaseAddrCh1Hi, pinNumCh1Hi, 0); + + uint32_t gpioBaseAddrCh1Lo = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_LOW_TH_CH1_BASE_ADDR); + uint32_t pinNumCh1Lo = GPIO_LOW_TH_CH1_PIN; + GPIO_setDirMode(gpioBaseAddrCh1Lo, pinNumCh1Lo, GPIO_LOW_TH_CH1_DIR); + SDFM_configComparatorGpioPins(h_sdfm, 1, gpioBaseAddrCh1Lo, pinNumCh1Lo, 1); + + + /*ch2 GPIO configuration*/ + uint32_t gpioBaseAddrCh2Hi = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_HIGH_TH_CH2_BASE_ADDR); + uint32_t pinNumCh2Hi = GPIO_HIGH_TH_CH2_PIN; + GPIO_setDirMode(gpioBaseAddrCh2Hi, pinNumCh2Hi, GPIO_HIGH_TH_CH2_DIR); + SDFM_configComparatorGpioPins(h_sdfm, 2, gpioBaseAddrCh2Hi, pinNumCh2Hi, 0); + + uint32_t gpioBaseAddrCh2Lo = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_LOW_TH_CH2_BASE_ADDR); + uint32_t pinNumCh2Lo = GPIO_LOW_TH_CH2_PIN; + GPIO_setDirMode(gpioBaseAddrCh2Lo, pinNumCh2Lo, GPIO_LOW_TH_CH2_DIR); + SDFM_configComparatorGpioPins(h_sdfm, 2, gpioBaseAddrCh2Lo, pinNumCh2Lo, 1); + + +} +/* Initialize SDDF PRU FW */ +int32_t init_sdfm_pru_fw(uint8_t pruId, SddfPrms *pSddfPrms, sdfm_handle *pHSddf) +{ + sdfm_handle hSddf; + + /* Initialize SDDF instance */ + hSddf = SDFM_init(pruId); + if (hSddf == NULL) + { + return SDDF_ERR_INIT_SDDF; + } + + uint8_t SDFM_CH; + hSddf->iep_clock = 300000000; //300MHz + hSddf->sdfm_clock = 20000000; //20MHz + hSddf->iep_inc = 1; // Default IEP increment 1 + + uint8_t acc_osr = 13; + uint8_t acc_filter = 0; //SINC3 filter + uint8_t ecap_divider = 0x0F; //IEP at 300MHz: SD clock = 300/15=20Mhz + + /*configure IEP count for one epwm period*/ + SDFM_configIepCount(hSddf, pSddfPrms->epwm_out_freq); + + /*configure ecap as PWM code for generate 20 MHz sdfm clock*/ + SDFM_configEcap(hSddf, ecap_divider); + + /*set comparator osr or OC osr*/ + SDFM_setCompFilterOverSamplingRatio(hSddf, pSddfPrms->ComFilterOsr); + + /*set OC sample count for NC & NC OSR */ + SDFM_setFilterOverSamplingRatio(hSddf, pSddfPrms->FilterOsr, pSddfPrms->ComFilterOsr); + + /*below configuration for all three channel*/ + for(SDFM_CH = 0; SDFM_CH < NUM_CH_SUPPORTED; SDFM_CH++) + { + SDFM_setEnableChannel(hSddf, SDFM_CH); + + SDFM_setAccOverSamplingRatio(hSddf, SDFM_CH, acc_osr); + + /*set ACC source or filter type*/ + SDFM_configDataFilter(hSddf, SDFM_CH, acc_filter); + + /*set clock inversion & clock source for all three channel*/ + SDFM_selectClockSource(hSddf, SDFM_CH, pSddfPrms->clkPrms[SDFM_CH]); + + /*set threshold values */ + SDFM_setCompFilterThresholds(hSddf, SDFM_CH, pSddfPrms->threshold_parms[SDFM_CH]); + + + + if(pSddfPrms->en_com) + { + SDFM_enableComparator(hSddf, SDFM_CH); + } + else + { + SDFM_disableComparator(hSddf, SDFM_CH); + } + + } + + /*GPIO pin configuration for threshold measurment*/ + sdfm_configure_gpio_pin(hSddf); + + SDFM_setSampleReadingTime(hSddf, pSddfPrms->trigSampTime); + + /* Enable (global) SDDF */ + SDFM_enable(hSddf); + + pHSddf = &hSddf; + + return SDDF_ERR_NERR; +} + +/* + * ======== initPruSddf ======== + */ +/* Initialize PRU core for SDDF */ +int32_t initPruSddf( + PRUICSS_Handle pruIcssHandle, + uint8_t pruInstId, + SddfPrms *pSddfPrms, + sdfm_handle *pHSddf +) +{ + uint8_t sliceId; + uint32_t pruIMem; + PRUSDDF_PruFwImageInfo *pPruFwImageInfo; + int32_t size; + const uint32_t *sourceMem; /* Source memory[ Array of uint32_t ] */ + uint32_t imemOffset; /* Offset at which write will happen */ + uint32_t byteLen; /* Total number of bytes to be written */ + uint8_t pruId; + int32_t status; + + /* Reset PRU */ + status = PRUICSS_resetCore(pruIcssHandle, pruInstId); + if (status != SystemP_SUCCESS) { + return SDDF_ERR_INIT_PRU_SDDF; + } + + /* Calculate slice ID */ + sliceId = pruInstId - (uint8_t)pruInstId/ICSSG_NUM_SLICE * ICSSG_NUM_SLICE; + /* Determine PRU DMEM address */ + /* Determine PRU FW image and PRU IMEM address */ + switch (pruInstId) + { + case PRUICSS_PRU0: + case PRUICSS_PRU1: + pPruFwImageInfo = &gPruFwImageInfo[0]; + pruIMem = PRUICSS_IRAM_PRU(sliceId); + break; + case PRUICSS_RTU_PRU0: + case PRUICSS_RTU_PRU1: + pPruFwImageInfo = &gPruFwImageInfo[1]; + pruIMem = PRUICSS_IRAM_RTU_PRU(sliceId); + break; + case PRUICSS_TX_PRU0: + case PRUICSS_TX_PRU1: + pPruFwImageInfo = NULL; + break; + default: + pPruFwImageInfo = NULL; + break; + } + + if ((pPruFwImageInfo == NULL) || + (pPruFwImageInfo->pPruImemImg == NULL)) + { + return SDDF_ERR_INIT_PRU_SDDF; + } + + /* Write IMEM */ + imemOffset = 0; + sourceMem = (uint32_t *)pPruFwImageInfo->pPruImemImg; + byteLen = pPruFwImageInfo->pruImemImgSz; + size = PRUICSS_writeMemory(pruIcssHandle, pruIMem, imemOffset, sourceMem, byteLen); + if (size == 0) + { + return SDDF_ERR_INIT_PRU_SDDF; + } + + /* Enable PRU */ + status = PRUICSS_enableCore(pruIcssHandle, pruInstId); + if (status != SystemP_SUCCESS) { + return SDDF_ERR_INIT_PRU_SDDF; + } +/* Translate PRU ID to SDDF API */ + if (pruInstId == PRUICSS_PRU0) { + pruId = PRU_ID_0; + } + else if (pruInstId == PRUICSS_PRU1) { + pruId = PRU_ID_1; + } + else { + return SDDF_ERR_INIT_PRU_SDDF; + } + + /* Initialize SDDF PRU FW */ + status = init_sdfm_pru_fw(pruId, pSddfPrms, pHSddf); + if (status != SDDF_ERR_NERR) { + return SDDF_ERR_INIT_PRU_SDDF; + } + return SDDF_ERR_NERR; + +} + + diff --git a/examples/motor_control/icss_sdfm/sddf.h b/examples/motor_control/icss_sdfm/sddf.h new file mode 100644 index 0000000..2d6d78d --- /dev/null +++ b/examples/motor_control/icss_sdfm/sddf.h @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SDDF_H_ +#define _SDDF_H_ + +#include +#include +#include "motor_control/current_sense/sdfm/include/sddf_api.h" + +/* Status codes */ +#define SDDF_ERR_NERR ( 0 ) /* no error */ +#define SDDF_ERR_CFG_PIN_MUX ( -1 ) /* pin mux configuration error */ +#define SDDF_ERR_CFG_ICSSG_CLKCFG ( -2 ) /* ICSSG clock configuration error */ +#define SDDF_ERR_INIT_ICSSG ( -3 ) /* initialize ICSSG error */ +#define SDDF_ERR_CFG_MCU_INTR ( -4 ) /* interrupt configuration error */ +#define SDDF_ERR_INIT_PRU_SDDF ( -5 ) /* initialize PRU for SDDF error */ +#define SDDF_ERR_INIT_SDDF ( -6 ) /* initialize SDDF error */ + +/* Bit for SDDF configuration mask */ +#define SDDF_CFG_CLK ( 1<<0 ) +#define SDDF_CFG_OSR ( 1<<1 ) +#define SDDF_CFG_TRIG_SAMP_TIME ( 1<<2 ) +#define SDDF_CFG_TRIG_SAMP_CNT ( 1<<3 ) +#define SDDF_CFG_CH_EN ( 1<<4 ) +#define SDDF_CFG_FD ( 1<<5 ) +#define SDDF_CFG_TRIG_OUT_SAMP_BUF ( 1<<6 ) + +/* SDDF mode */ +#define SDDF_MODE_TRIG ( 0 ) +#define SDDF_MODE_CONT ( 1 ) + +/* ICSSG Core clock source selection options */ +#define CORE_CLK_SEL_ICSSGn_CORE_CLK ( 0 ) /* Mux Output */ +#define CORE_CLK_SEL_ICSSGn_ICLK ( 1 ) /* ICSSGn_ICLK = MAIN_SYSCLK0/2 = 250 MHz */ +/* ICSSG Core clock selections in case Mux Output selected */ +#define ICSSGn_CORE_CLK_SEL_MAIN_PLL2_HSDIV0_CLKOUT ( 0 ) /* 225 or 300 MHz, default 225 MHz */ +#define ICSSGn_CORE_CLK_SEL_MAIN_PLL0_HSDIV9_CLKOUT ( 1 ) /* 200, 250, or 333 MHz, default 200 MHz */ +#define ICSSGn_CORE_CLK_SEL_NUMSEL ( 2 ) +/* ICSSG Core clock frequency in case Mux Output selected. + Set to 0 in case clock frequency configuration not desired. */ +#define ICSSGn_CORE_CLK_FREQ_225MHZ ( 225000000UL ) /* MAIN PLL2 HSDIV0, 225 MHz */ +#define ICSSGn_CORE_CLK_FREQ_300MHZ ( 300000000UL ) /* MAIN PLL2 HSDIV0, 300 MHz */ +#define ICSSGn_CORE_CLK_FREQ_200MHZ ( 200000000UL ) /* MAIN PLL0 HSDIV9, 200 MHz */ +#define ICSSGn_CORE_CLK_FREQ_250MHZ ( 250000000UL ) /* MAIN PLL0 HSDIV9, 250 MHz */ +#define ICSSGn_CORE_CLK_FREQ_333MHZ ( 333333333UL ) /* MAIN PLL0 HSDIV9, 333 MHz */ +#define ICSSGn_CORE_CLK_FREQ_NOCFG ( 0UL ) /* No clock frequency reconfig */ +//#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_NOCFG ) +#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_300MHZ ) +//#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_333MHZ ) + +/* ICSSG IEP clock source selection options */ +#define IEP_CLK_SEL_ICSSGn_IEP_CLK ( 0 ) /* Mux Output */ +#define IEP_CLK_SEL_CORE_CLK ( 1 ) /* CORE_CLK */ +/* ICSSG IEP clock selections in case Mux output selected */ +#define ICSSGn_IEP_CLK_SEL_MAIN_PLL2_HSDIV5_CLKOUT ( 0 ) /* Default 225 MHz */ +#define ICSSGn_IEP_CLK_SEL_MAIN_PLL0_HSDIV6_CLKOUT ( 1 ) /* 200 or 250 MHz, default 200 MHz */ +#define ICSSGn_IEP_CLK_SEL_CPSW0_CPTS_RFT_CLK ( 2 ) +#define ICSSGn_IEP_CLK_SEL_CPTS_RFT_CLK ( 3 ) +#define ICSSGn_IEP_CLK_SEL_MCU_EXT_REFCLK0 ( 4 ) +#define ICSSGn_IEP_CLK_SEL_EXT_REFCLK1 ( 5 ) +#define ICSSGn_IEP_CLK_SEL_SERDES0_IP1_LN0_TXMCLK ( 6 ) +#define ICSSGn_IEP_CLK_SEL_SYSCLK0 ( 7 ) +#define ICSSGn_IEP_CLK_SEL_NUMSEL ( 8 ) +/* ICSSG IEP clock frequency in case Mux Output selected. + Set to 0 in case clock frequency configuration not desired. */ +#define ICSSGn_IEP_CLK_FREQ_200MHZ ( 200000000UL ) /* MAIN PLL0 HSDIV6, 200 MHz */ +#define ICSSGn_IEP_CLK_FREQ_250MHZ ( 250000000UL ) /* MAIN PLL0 HSDIV6, 250 MHz */ +#define ICSSGn_IEP_CLK_FREQ_NOCFG ( 0UL ) /* No clock frequency reconfig */ +#define ICSSGn_IEP_CLK_FREQ ( ICSSGn_IEP_CLK_FREQ_NOCFG ) + +/* Default ICSS pin mux setting */ +#define PRUICSS_G_MUX_EN_DEF ( 0x0 ) /* ICSSG_SA_MX_REG:G_MUX_EN */ + +/* Translate the TCM local view addr to SoC view addr */ +#define CPU0_ATCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_ATCM_BASE+(x)) +#define CPU1_ATCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_ATCM_BASE+(x)) +#define CPU0_BTCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_BTCM_BASE+(x - CSL_R5FSS0_BTCM_BASE)) +#define CPU1_BTCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_BTCM_BASE+(x - CSL_R5FSS1_BTCM_BASE)) + +#define ICSSG_SLICE_ID_0 ( 0 ) /* ICSSG slide ID 0 */ +#define ICSSG_SLICE_ID_1 ( 1 ) /* ICSSG slide ID 1 */ +#define ICSSG_NUM_SLICE ( 2 ) /* ICSSG number of slices */ + +/*! + * @brief PRUICSS Instance IDs + */ +typedef enum PRUICSS_MaxInstances_s +{ + PRUICSS_INSTANCE_ONE=0, + PRUICSS_INSTANCE_TWO=1, + PRUICSS_INSTANCE_MAX=2 +} PRUICSS_MaxInstances; + +/* SDDF configuration parameters */ +typedef struct SddfPrms_s { + float trigSampTime; + uint32_t epwm_out_freq; + SDFM_ThresholdParms threshold_parms[NUM_CH_SUPPORTED]; + SDFM_ClkSourceParms clkPrms[3]; + uint16_t ComFilterOsr; + uint16_t FilterOsr; + uint8_t en_com; +} SddfPrms; + + +/* Initialize ICSSG */ +int32_t initIcss( + uint8_t icssInstId, + uint8_t sliceId, + uint8_t saMuxMode, + PRUICSS_Handle *pPruIcssHandle +); + +/* Initialize PRU core for SDDF */ +int32_t initPruSddf( + PRUICSS_Handle pruIcssHandle, + uint8_t pruInstId, + SddfPrms *pSddfPrms, + sdfm_handle *pHSddf +); + + +#endif /* _SDDF_H_ */ diff --git a/examples/motor_control/icss_sdfm/tisddf_pruss_intc_mapping.h b/examples/motor_control/icss_sdfm/tisddf_pruss_intc_mapping.h new file mode 100644 index 0000000..f88ac6c --- /dev/null +++ b/examples/motor_control/icss_sdfm/tisddf_pruss_intc_mapping.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/** +* @file ti_uart_pruss_intc_mapping.h +* +* @brief Pruss interrupt mapping related macros +* +*/ + +#ifndef TI_UART_PRUSS_INTC_MAPPING_H +#define TI_UART_PRUSS_INTC_MAPPING_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define IEP_TIM_CAP_CMP_EVENT 7 +#define SYNC1_OUT_EVENT 13 +#define SYNC0_OUT_EVENT 14 + +/* SYS_EVT_16-31 can be used for generating interrupts for IPC with hosts/prus etc */ +#define PRU_ARM_EVENT00 16 +#define PRU_ARM_EVENT01 17 +#define PRU_ARM_EVENT02 18 +#define PRU_ARM_EVENT03 19 +#define PRU_ARM_EVENT04 20 +#define PRU_ARM_EVENT05 21 +#define PRU_ARM_EVENT06 22 +#define PRU_ARM_EVENT07 23 +#define PRU_ARM_EVENT08 24 +#define PRU_ARM_EVENT09 25 +#define PRU_ARM_EVENT10 26 +#define PRU_ARM_EVENT11 27 +#define PRU_ARM_EVENT12 28 +#define PRU_ARM_EVENT13 29 +#define PRU_ARM_EVENT14 30 +#define PRU_ARM_EVENT15 31 + +#define PRU0_RX_ERR32_EVENT 33 +#define PORT1_TX_UNDERFLOW 39 +#define PORT1_TX_OVERFLOW 40 +#define MII_LINK0_EVENT 41 +#define PORT1_RX_EOF_EVENT 42 +#define PRU1_RX_ERR32_EVENT 45 +#define PORT2_TX_UNDERFLOW 51 +#define PORT2_TX_OVERFLOW 53 +#define PORT2_RX_EOF_EVENT 54 +#define MII_LINK1_EVENT 53 + +#define CHANNEL0 0 +#define CHANNEL1 1 +#define CHANNEL2 2 +#define CHANNEL3 3 +#define CHANNEL4 4 +#define CHANNEL5 5 +#define CHANNEL6 6 +#define CHANNEL7 7 +#define CHANNEL8 8 +#define CHANNEL9 9 + +#define PRU0 0 +#define PRU1 1 +#define PRU_EVTOUT0 2 +#define PRU_EVTOUT1 3 +#define PRU_EVTOUT2 4 +#define PRU_EVTOUT3 5 +#define PRU_EVTOUT4 6 +#define PRU_EVTOUT5 7 +#define PRU_EVTOUT6 8 +#define PRU_EVTOUT7 9 + +#define PRU0_HOSTEN_MASK ((uint32_t)0x0001) +#define PRU1_HOSTEN_MASK ((uint32_t)0x0002) +#define PRU_EVTOUT0_HOSTEN_MASK ((uint32_t)0x0004) +#define PRU_EVTOUT1_HOSTEN_MASK ((uint32_t)0x0008) +#define PRU_EVTOUT2_HOSTEN_MASK ((uint32_t)0x0010) +#define PRU_EVTOUT3_HOSTEN_MASK ((uint32_t)0x0020) +#define PRU_EVTOUT4_HOSTEN_MASK ((uint32_t)0x0040) +#define PRU_EVTOUT5_HOSTEN_MASK ((uint32_t)0x0080) +#define PRU_EVTOUT6_HOSTEN_MASK ((uint32_t)0x0100) +#define PRU_EVTOUT7_HOSTEN_MASK ((uint32_t)0x0200) + +#define SYS_EVT_POLARITY_LOW 0 +#define SYS_EVT_POLARITY_HIGH 1 + +#define SYS_EVT_TYPE_PULSE 0 +#define SYS_EVT_TYPE_EDGE 1 + +#define PRUICSS_INTC_INITDATA { \ +{ IEP_TIM_CAP_CMP_EVENT, PRU_ARM_EVENT02, PRU_ARM_EVENT03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, /* initializing member [0-15] for Misra C standards */ \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, /* initializing member [16-31] for Misra C standards */ \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, /* initializing member [32-47] for Misra C standards */ \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* initializing member [48-63] for Misra C standards */ \ +{ {IEP_TIM_CAP_CMP_EVENT, CHANNEL1, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_PULSE},\ + {PRU_ARM_EVENT02, CHANNEL2, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_PULSE},\ + {PRU_ARM_EVENT03, CHANNEL3, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_PULSE},\ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [3] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [4] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [5] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [6] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [7] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [8] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [9] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [10] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [11] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [12] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [13] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [14] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [15] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [16] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [17] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [18] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [19] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [20] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [21] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [22] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [23] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [24] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [25] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [26] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [27] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [28] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [29] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [30] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [31] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [32] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [33] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [34] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [35] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [36] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [37] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [38] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [39] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [40] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [41] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [42] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [43] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [44] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [45] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [46] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [47] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [48] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [49] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [50] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [51] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [52] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [53] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [54] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [55] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [56] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [57] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [58] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [59] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [60] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [61] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}, /* initializing member [62] for Misra C standards */ \ + {0xFF,0xFF,0xFF,0xFF}}, /* initializing member [63] for Misra C standards */ \ + { {CHANNEL1, PRU1}, {CHANNEL2, PRU_EVTOUT0}, {CHANNEL3, PRU_EVTOUT1},\ + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, /* Initializing members [3,4,5] of array for Misra C standards */ \ + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF} }, /* Initializing members [6,7,8,9] of array for Misra C standards */ \ + (PRU1_HOSTEN_MASK | PRU_EVTOUT0_HOSTEN_MASK | PRU_EVTOUT1_HOSTEN_MASK) \ +} + +#ifdef __cplusplus +} +#endif + + +#endif /* TI_UART_PRUSS_INTC_MAPPING_H */ diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project.js b/examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project_am243x.js b/examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project_am243x.js new file mode 100644 index 0000000..e818139 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project_am243x.js @@ -0,0 +1,124 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "tamagawa_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", /* tamagawa_diagnostic.c base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_tamagawa.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM243X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_TAMAGAWA"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am243x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am243x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "tamagawa_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "tamagawa_diagnostic_multi_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project_am64x.js b/examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project_am64x.js new file mode 100644 index 0000000..b146e59 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/.project/project_am64x.js @@ -0,0 +1,124 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "tamagawa_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", /* tamagawa_diagnostic.c base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_tamagawa.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM64X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_TAMAGAWA"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am64x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am64x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "tamagawa_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "tamagawa_diagnostic_multi_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..7879e22 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,88 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const tamagawa = scripting.addModule("/motor_control/position_sense/tamagawa", {}, false); +const tamagawa1 = tamagawa.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +tamagawa1.$name = "CONFIG_TAMAGAWA0"; +tamagawa1.channel_1 = true; +tamagawa1.channel_2 = true; +tamagawa1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance({}, false); +pruicss1.$name = "CONFIG_PRU_ICSS0"; +tamagawa1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +debug_log.uartLog.UART.RXD.$suggestSolution = "ball.D15"; +debug_log.uartLog.UART.TXD.$suggestSolution = "ball.C16"; +tamagawa1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "ball.V3"; +tamagawa1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "ball.W2"; +tamagawa1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "ball.Y2"; +tamagawa1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "ball.T6"; +tamagawa1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "ball.P4"; +tamagawa1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "ball.W3"; +tamagawa1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "ball.T4"; +tamagawa1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "ball.U6"; +tamagawa1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "ball.R1"; +tamagawa1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "ball.Y4"; +tamagawa1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "ball.R5"; +tamagawa1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "ball.W4"; diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..fb99fec --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void tamagawa_main(void *args); + +void freertos_main(void *args) +{ + tamagawa_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..0e3c14f --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..69640f4 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..a141995 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,309 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=tamagawa_diagnostic_multi_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=tamagawa_diagnostic_multi_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=tamagawa_diagnostic_multi_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=tamagawa_diagnostic_multi_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + tamagawa_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_tamagawa.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_tamagawa.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang tamagawa_diagnostic_multi_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..8f8bca5 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..a648803 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,88 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const tamagawa = scripting.addModule("/motor_control/position_sense/tamagawa", {}, false); +const tamagawa1 = tamagawa.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +tamagawa1.$name = "CONFIG_TAMAGAWA0"; +tamagawa1.channel_1 = true; +tamagawa1.channel_2 = true; +tamagawa1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance({}, false); +pruicss1.$name = "CONFIG_PRU_ICSS0"; +tamagawa1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +debug_log.uartLog.UART.RXD.$suggestSolution = "ball.D15"; +debug_log.uartLog.UART.TXD.$suggestSolution = "ball.C16"; +tamagawa1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "ball.V3"; +tamagawa1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "ball.W2"; +tamagawa1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "ball.Y2"; +tamagawa1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "ball.T6"; +tamagawa1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "ball.P4"; +tamagawa1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "ball.W3"; +tamagawa1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "ball.T4"; +tamagawa1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "ball.U6"; +tamagawa1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "ball.R1"; +tamagawa1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "ball.Y4"; +tamagawa1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "ball.R5"; +tamagawa1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "ball.W4"; diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..fb99fec --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void tamagawa_main(void *args); + +void freertos_main(void *args) +{ + tamagawa_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..0bfbae9 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..c4848c3 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..9660dcf --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,310 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=tamagawa_diagnostic_multi_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=tamagawa_diagnostic_multi_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=tamagawa_diagnostic_multi_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=tamagawa_diagnostic_multi_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=tamagawa_diagnostic_multi_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + tamagawa_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM64X \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_tamagawa.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_tamagawa.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang tamagawa_diagnostic_multi_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM64x_beta --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..17e86fd --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,107 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..6a20b72 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/.project/project.js b/examples/motor_control/tamagawa_diagnostic/single_channel/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/.project/project_am243x.js b/examples/motor_control/tamagawa_diagnostic/single_channel/.project/project_am243x.js new file mode 100644 index 0000000..b1824ae --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/.project/project_am243x.js @@ -0,0 +1,125 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "tamagawa_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", /* tamagawa_diagnostic.c base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_tamagawa.am243x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM243X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_TAMAGAWA"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am243x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am243x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "tamagawa_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"}, + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-lp", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "tamagawa_diagnostic_single_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/.project/project_am64x.js b/examples/motor_control/tamagawa_diagnostic/single_channel/.project/project_am64x.js new file mode 100644 index 0000000..46d52fd --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/.project/project_am64x.js @@ -0,0 +1,124 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "tamagawa_diagnostic.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", /* tamagawa_diagnostic.c base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib", + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_tamagawa.am64x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM64X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_TAMAGAWA"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am64x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am64x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "tamagawa_main", + taskPri: 5, + }, + } +]; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "tamagawa_diagnostic_single_channel"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + build_property.defines = defines_r5f; + } + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..b839ce5 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,86 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const tamagawa = scripting.addModule("/motor_control/position_sense/tamagawa", {}, false); +const tamagawa1 = tamagawa.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +tamagawa1.$name = "CONFIG_TAMAGAWA0"; +tamagawa1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance({}, false); +pruicss1.$name = "CONFIG_PRU_ICSS0"; +tamagawa1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +debug_log.uartLog.UART.RXD.$suggestSolution = "ball.D15"; +debug_log.uartLog.UART.TXD.$suggestSolution = "ball.C16"; +tamagawa1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "ball.V3"; +tamagawa1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "ball.W2"; +tamagawa1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "ball.Y2"; +tamagawa1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "ball.T6"; +tamagawa1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "ball.P4"; +tamagawa1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "ball.W3"; +tamagawa1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "ball.T4"; +tamagawa1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "ball.U6"; +tamagawa1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "ball.R1"; +tamagawa1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "ball.Y4"; +tamagawa1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "ball.R5"; +tamagawa1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "ball.W4"; diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..fb99fec --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void tamagawa_main(void *args); + +void freertos_main(void *args) +{ + tamagawa_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..7078a74 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..69640f4 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..4fc24ac --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,309 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=tamagawa_diagnostic_single_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=tamagawa_diagnostic_single_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=tamagawa_diagnostic_single_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=tamagawa_diagnostic_single_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + tamagawa_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_tamagawa.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_tamagawa.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang tamagawa_diagnostic_single_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..bc7576a --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..5d6c093 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,90 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const tamagawa = scripting.addModule("/motor_control/position_sense/tamagawa", {}, false); +const tamagawa1 = tamagawa.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +tamagawa1.$name = "CONFIG_TAMAGAWA0"; +tamagawa1.Booster_Pack = true; +tamagawa1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; +tamagawa1.PRU_ICSSG0_PRU.GPO5.$used = false; +tamagawa1.PRU_ICSSG0_PRU.GPO4.$used = false; +tamagawa1.PRU_ICSSG0_PRU.GPO3.$used = false; +tamagawa1.PRU_ICSSG0_PRU.GPI14.$used = false; +tamagawa1.PRU_ICSSG0_PRU.GPO8.$used = false; +tamagawa1.PRU_ICSSG0_PRU.GPO12.$used = false; +tamagawa1.PRU_ICSSG0_PRU.GPO6.$used = false; +tamagawa1.PRU_ICSSG0_PRU.GPI11.$used = false; + +tamagawa1.ENC1_EN = gpio1; +gpio1.$name = "ENC1_EN"; +gpio1.GPIO.$assign = "GPIO1"; +gpio1.GPIO.gpioPin.rx = false; +gpio1.GPIO.gpioPin.$assign = "ball.C16"; + +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance({}, false); +pruicss1.$name = "CONFIG_PRU_ICSS0"; +tamagawa1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +debug_log.uartLog.UART.RXD.$suggestSolution = "ball.B10"; +debug_log.uartLog.UART.TXD.$suggestSolution = "ball.B11"; +tamagawa1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "ball.M2"; +tamagawa1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "ball.J2"; +tamagawa1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "ball.L5"; +tamagawa1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "ball.T4"; diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..fb99fec --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void tamagawa_main(void *args); + +void freertos_main(void *args) +{ + tamagawa_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..da6c2ec --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..69640f4 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..19cc906 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,309 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=tamagawa_diagnostic_single_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=tamagawa_diagnostic_single_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=tamagawa_diagnostic_single_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=tamagawa_diagnostic_single_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + tamagawa_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am243x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM243X \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_tamagawa.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_tamagawa.am243x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang tamagawa_diagnostic_single_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALX_beta --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..b8b417e --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,106 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..93ab654 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..979f1c1 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,86 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const mpu_armv76 = mpu_armv7.addInstance(); +const tamagawa = scripting.addModule("/motor_control/position_sense/tamagawa", {}, false); +const tamagawa1 = tamagawa.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.UART.$assign = "USART0"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x41010000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.baseAddr = 0x60000000; +mpu_armv75.size = 28; +mpu_armv75.accessPermissions = "Supervisor RD, User RD"; + +mpu_armv76.$name = "CONFIG_MPU_REGION5"; +mpu_armv76.baseAddr = 0x80000000; +mpu_armv76.size = 31; + +tamagawa1.$name = "CONFIG_TAMAGAWA0"; +tamagawa1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; + +const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false); +const pruicss1 = pruicss.addInstance({}, false); +pruicss1.$name = "CONFIG_PRU_ICSS0"; +tamagawa1.pru = pruicss1; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +debug_log.uartLog.UART.RXD.$suggestSolution = "ball.D15"; +debug_log.uartLog.UART.TXD.$suggestSolution = "ball.C16"; +tamagawa1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "ball.V3"; +tamagawa1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "ball.W2"; +tamagawa1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "ball.Y2"; +tamagawa1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "ball.T6"; +tamagawa1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "ball.P4"; +tamagawa1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "ball.W3"; +tamagawa1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "ball.T4"; +tamagawa1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "ball.U6"; +tamagawa1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "ball.R1"; +tamagawa1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "ball.Y4"; +tamagawa1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "ball.R5"; +tamagawa1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "ball.W4"; diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/main.c b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..fb99fec --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (5) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void tamagawa_main(void *args); + +void freertos_main(void *args) +{ + tamagawa_main(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..dcb4e25 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..c4848c3 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,148 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is disabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > MSRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > MSRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .data: {} palign(8) /* This is where initialized globals and static go */ + } > MSRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > MSRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > MSRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* General purpose non cacheable memory, used in some examples */ + .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM +} + +/* +NOTE: Below memory is reserved for DMSC usage + - During Boot till security handoff is complete + 0x701E0000 - 0x701FFFFF (128KB) + - After "Security Handoff" is complete (i.e at run time) + 0x701F4000 - 0x701FFFFF (48KB) + + Security handoff is complete when this message is sent to the DMSC, + TISCI_MSG_SEC_HANDOVER + + This should be sent once all cores are loaded and all application + specific firewall calls are setup. +*/ + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000 + + /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */ + NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + /* shared memory segments */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80 + LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80 + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000 +} diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..2dc2c00 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,310 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=tamagawa_diagnostic_single_channel.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=tamagawa_diagnostic_single_channel.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=tamagawa_diagnostic_single_channel.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=tamagawa_diagnostic_single_channel.$(PROFILE).rprc_tmp +BOOTIMAGE_NAME_HS:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage.hs +BOOTIMAGE_NAME_HS_FS:=tamagawa_diagnostic_single_channel.$(PROFILE).appimage.hs_fs +TARGETS := $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) + TARGETS += $(BOOTIMAGE_NAME_HS) +endif + +FILES_common := \ + tamagawa_diagnostic.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am64x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM64X \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_tamagawa.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_tamagawa.am64x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(TARGETS) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang tamagawa_diagnostic_single_channel ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM64x_beta --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!! + @echo . + +$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME) +ifeq ($(DEVICE_TYPE), HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS) +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS) + $(RM) $(BOOTIMAGE_NAME)-enc +endif + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!! + @echo . +endif +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..17e86fd --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,107 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_a53ss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-0 = 4 +BOOTIMAGE_CORE_ID_r5fss0-1 = 5 +BOOTIMAGE_CORE_ID_r5fss1-0 = 6 +BOOTIMAGE_CORE_ID_r5fss1-1 = 7 +BOOTIMAGE_CORE_ID_m4fss0-0 = 14 +SBL_RUN_ADDRESS=0x70000000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js +APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) +# Sign the appimage for HS-FS using appimage signing script + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs +ifeq ($(DEVICE_TYPE),HS) +# Sign the appimage using appimage signing script +ifeq ($(ENC_ENABLED),no) + @echo Boot image signing: Encryption is disabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs +else + @echo Boot image signing: Encryption is enabled. + $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs + $(RM) $(BOOTIMAGE_NAME)-enc +endif +endif + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +ifeq ($(DEVICE_TYPE),HS) + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!! + @echo . +else + @echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!! + @echo . +endif +endif diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..35596bd --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/tamagawa_diagnostic/tamagawa_diagnostic.c b/examples/motor_control/tamagawa_diagnostic/tamagawa_diagnostic.c new file mode 100644 index 0000000..689f642 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic/tamagawa_diagnostic.c @@ -0,0 +1,437 @@ +/** + * tamagawa_diagnostic.c + * + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * */ + + + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include "ti_drivers_open_close.h" +#include "ti_drivers_config.h" +#include "ti_board_open_close.h" +#include +#if ((CONFIG_TAMAGAWA0_CHANNEL0 + CONFIG_TAMAGAWA0_CHANNEL1 + CONFIG_TAMAGAWA0_CHANNEL2) == 1) +#include +#endif +#if ((CONFIG_TAMAGAWA0_CHANNEL0 + CONFIG_TAMAGAWA0_CHANNEL1 + CONFIG_TAMAGAWA0_CHANNEL2) > 1) +#include +#endif + +static uint8_t gTamagawa_multi_ch_mask; +static uint32_t gTamagawa_is_multi_ch; +struct tamagawa_priv *priv; + +/** \brief Global Structure pointer holding PRU-ICSSx memory Map. */ +PRUICSS_Handle gPruIcssXHandle; +void *gPru_dramx; + +void tamagawa_pruicss_init(void) +{ + gPruIcssXHandle = PRUICSS_open(CONFIG_PRU_ICSS0); + /* PRUICSS_PRUx holds value 0 or 1 depending on whether we are using PRU0 or PRU1 slice */ + PRUICSS_initMemory(gPruIcssXHandle, PRUICSS_DATARAM(PRUICSS_PRUx)); + PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_PRUx); + PRUICSS_setSaMuxMode(gPruIcssXHandle, PRUICSS_SA_MUX_MODE_SD_ENDAT); +} + +void tamagawa_pruicss_load_run_fw(void) +{ + PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_PRUx); + /*Load firmware. Set buffer = write to Pru memory */ + PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_PRU(PRUICSS_PRUx),0, (uint32_t *) TamagawaFirmware,sizeof(TamagawaFirmware)); + PRUICSS_resetCore(gPruIcssXHandle, PRUICSS_PRUx); + /*Run firmware */ + PRUICSS_enableCore(gPruIcssXHandle, PRUICSS_PRUx); +} + +void tamagawa_display_result(struct tamagawa_priv *priv, int32_t cmd) +{ + /* Prints the position value returned by the encoder for a particular command ID */ + switch(cmd) + { + case DATA_ID_7: + /* Reset */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.abs, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.sf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.cf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.crc); + break; + + case DATA_ID_8: + /* Reset */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.abs, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.sf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.cf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.crc); + break; + + case DATA_ID_C: + /* Reset */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.abs, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.sf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.cf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.crc); + break; + + case DATA_ID_0: + /* Data readout: data in one revolution */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.abs, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.sf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.cf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.crc); + break; + + case DATA_ID_1: + /* Data readout: multi-turn data */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABM: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.abm, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.sf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.cf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.crc); + break; + + case DATA_ID_2: + /* Data readout: encoder ID */ + DebugP_log("\r\n| "); + DebugP_log("\r\nENID: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.enid, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.sf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.cf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.crc); + break; + + case DATA_ID_3: + /* Data readout: data in one revolution, encoder ID, multi-turn, encoder error */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tENID: 0x%x\tABM: 0x%x\tALMC: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.abs, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.enid, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.abm, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.almc, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.sf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.cf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.crc); + break; + + case DATA_ID_6: + /* EEPROM Write */ + DebugP_log("\r\n| "); + DebugP_log("\r\nEDF: 0x%x\tADF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.edf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.adf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.cf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.crc); + break; + + case DATA_ID_D: + /* EEPROM Read */ + DebugP_log("\r\n| "); + DebugP_log("\r\nEDF: 0x%x\tADF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.edf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.adf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.cf, priv->tamagawa_xchg->tamagawa_interface.rx_frames_received.crc); + break; + + default: + DebugP_log("\r\n| ERROR: unknown Data ID\n"); + break; + } +} + + +static void tamagawa_handle_rx(struct tamagawa_priv *priv, int32_t cmd) +{ + DebugP_log("\r\n Parsing process started\n"); + /* Case of parsing failure */ + if (tamagawa_parse(cmd, priv) == -1) + { + DebugP_log("\r\n ERROR: Parsing failure\n"); + return; + } + /* Case of successful parsing, display the results after CRC check*/ + DebugP_log("\r\n Channel is %x \n",priv->channel); + DebugP_log("\r\n data id is %x \n",cmd); + if (tamagawa_crc_verify(priv) == 1) + { + DebugP_log("\r\n CRC success \n"); + tamagawa_display_result(priv, cmd); + return; + } + else + { + DebugP_log("\r\n CRC Failure \n"); + } + + return; +} + +static enum data_id tamagawa_get_command(uint8_t *adf, uint8_t *edf) +{ + int32_t cmd; + uint32_t val; + /* Check to make sure that the command issued is correct */ + if(DebugP_scanf("%d\n", &cmd) < 0) + { + cmd = DATA_ID_0; + DebugP_log("\r\n| WARNING: invalid Data ID, Data readout Data ID 0 will be sent\n"); + } + /* Check to make sure that the command issued is correct */ + if(cmd >= DATA_ID_NUM) + { + cmd = DATA_ID_0; + DebugP_log("\r\n| WARNING: invalid Data ID, Data readout Data ID 0 will be sent\n"); + } + /* In case of EEPROM commands, take input for Address field for different channels selected*/ + if((cmd == DATA_ID_D) || (cmd == DATA_ID_6)) + { + uint32_t ch = 0; + for(ch = 0 ; ch < MAX_CHANNELS ; ch++) + { + if(gTamagawa_multi_ch_mask & 1 << ch) + { + if(gTamagawa_is_multi_ch != 1) + { + DebugP_log("\r\n| Enter EEPROM address (hex value) : "); + } + else + { + DebugP_log("\r\n| Enter EEPROM address (hex value) for ch %d : ", ch); + } + if(DebugP_scanf("%x\n", &val) < 0) + { + cmd = DATA_ID_NUM; + DebugP_log("\r\n| ERROR: invalid EEPROM address\n|\n"); + break; + } + + if(val > MAX_EEPROM_ADDRESS) + { + cmd = DATA_ID_NUM; + DebugP_log("\r\n| ERROR: invalid EEPROM address\n|\n"); + break; + } + + *adf = (uint8_t)val; + tamagawa_update_adf(priv, val, ch); + } + } + } + /* In case of EEPROM Write, take input for Address field for different channels selected*/ + if(cmd == DATA_ID_6) + { + uint32_t ch = 0; + for(ch = 0 ; ch < MAX_CHANNELS ; ch++) + { + if(gTamagawa_multi_ch_mask & 1 << ch) + { + if(gTamagawa_is_multi_ch != 1) + { + DebugP_log("\r\n| Enter EEPROM data (hex value) : "); + } + else + { + DebugP_log("\r\n| Enter EEPROM data (hex value) for ch %d : ", ch); + } + if(DebugP_scanf("%x\n", &val) < 0) + { + cmd = DATA_ID_NUM; + DebugP_log("\r\n| ERROR: invalid EEPROM data\n|\n"); + break; + } + + if(val > MAX_EEPROM_WRITE_DATA) + { + cmd = DATA_ID_NUM; + DebugP_log("\r\n| ERROR: invalid EEPROM data\n|\n"); + break; + } + + *edf = (uint8_t)val; + tamagawa_update_edf(priv, val, ch); + } + } + } + return cmd; +} + +static void tamagawa_display_menu(void) +{ + DebugP_log("\r\n|------------------------------------------------------------------------------|"); + DebugP_log("\r\n| Select DATA ID Code |"); + DebugP_log("\r\n|------------------------------------------------------------------------------|"); + DebugP_log("\r\n| 0 : Data readout, Absolute (Data ID 0) |"); + DebugP_log("\r\n| 1 : Data readout, Multi-turn (Data ID 1) |"); + DebugP_log("\r\n| 2 : Data readout, Encoder-ID (Data ID 2) |"); + DebugP_log("\r\n| 3 : Data readout, Absolute & Multi-turn (Data ID 3) |"); + DebugP_log("\r\n| 4 : Writing to EEPROM (Data ID 6) |"); + DebugP_log("\r\n| 5 : Reset (Data ID 7) |"); + DebugP_log("\r\n| 6 : Reset (Data ID 8) |"); + DebugP_log("\r\n| 7 : Reset (Data ID C) |"); + DebugP_log("\r\n| 8 : Readout from EEPROM (Data ID D) |"); + DebugP_log("\r\n|------------------------------------------------------------------------------|\n|\n"); + DebugP_log("\r\n| enter value: "); +} + + +uint32_t tamagawa_get_fw_version(void) +{ + /* Returns the firmware version, depending on Single or Multi-channel configuration */ + return *((uint32_t *)TamagawaFirmware + 1); +} + + +void tamagawa_main(void *args) +{ + /* Open drivers to open the UART driver for console */ + Drivers_open(); + Board_driversOpen(); +/*C16 pin High for Enabling ch0 in booster pack */ +#if (CONFIG_TAMAGAWA0_BOOSTER_PACK) + GPIO_setDirMode(ENC1_EN_BASE_ADDR, ENC1_EN_PIN, ENC1_EN_DIR); + GPIO_pinWriteHigh(ENC1_EN_BASE_ADDR, ENC1_EN_PIN); +#endif + void *pruicss_cfg; + uint32_t slice_value = 1; + uint32_t selected_ch; + + tamagawa_pruicss_init(); + + pruicss_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcssXHandle->hwAttrs))->cfgRegBase); + + if(PRUICSS_PRUx == 0) + { + slice_value = 0; + } + + /* Initialize the priv structure according to the PRUx slice selected */ + priv = tamagawa_init((struct tamagawa_xchg *)((PRUICSS_HwAttrs *)( + gPruIcssXHandle->hwAttrs))->pru1DramBase, pruicss_cfg, slice_value); + + + tamagawa_set_baudrate(priv, CONFIG_TAMAGAWA0_BAUDRATE); + + DebugP_log("\r\n\nTamagawa PRU-ICSS init done\n\n"); + + /* Set the value of gTamagawa_multi_ch_mask based on the channels selected */ + gTamagawa_multi_ch_mask = (CONFIG_TAMAGAWA0_CHANNEL0<<0|CONFIG_TAMAGAWA0_CHANNEL1<<1|CONFIG_TAMAGAWA0_CHANNEL2<<2); + + if (CONFIG_TAMAGAWA0_CHANNEL0 + CONFIG_TAMAGAWA0_CHANNEL1 + CONFIG_TAMAGAWA0_CHANNEL2 > 1) + { + gTamagawa_is_multi_ch = 1; + } + + if(gTamagawa_is_multi_ch) + { + tamagawa_config_multi_channel_mask(priv, gTamagawa_multi_ch_mask); + } + + else + { + if (CONFIG_TAMAGAWA0_CHANNEL0 == 1) + { + selected_ch = 0; + } + + if (CONFIG_TAMAGAWA0_CHANNEL1 == 1) + { + selected_ch = 1; + } + + if (CONFIG_TAMAGAWA0_CHANNEL2 == 1) + { + selected_ch = 2; + } + tamagawa_config_channel(priv, selected_ch); + } + + uint32_t firmware_ver; + firmware_ver = tamagawa_get_fw_version(); + + DebugP_log("\r\nTamagawa firmware \t: %x.%x.%x (%s)\n\n", (firmware_ver >> 24) & 0x7F, + (firmware_ver >> 16) & 0xFF, firmware_ver & 0xFFFF, firmware_ver & (1 << 31) ? "internal" : "release"); + + DebugP_log("\r\nChannel(s) selected: %s %s %s \n\n\n", + gTamagawa_multi_ch_mask & TAMAGAWA_MULTI_CH0 ? "0" : "", + gTamagawa_multi_ch_mask & TAMAGAWA_MULTI_CH1 ? "1" : "", + gTamagawa_multi_ch_mask & TAMAGAWA_MULTI_CH2 ? "2" : ""); + + /*Updating the channel mask in interface*/ + priv->tamagawa_xchg->tamagawa_interface.ch_mask =gTamagawa_multi_ch_mask; + + tamagawa_config_host_trigger(priv); + + tamagawa_pruicss_load_run_fw(); + DebugP_log("\r\nTamagawa PRU-ICSS firmware loaded and running\n\n\n"); + + while(1) + { + /* + * Initialized to zero to remove the compiler warning about the variable being uninitialized. + */ + uint8_t adf = 0, edf = 0; + enum data_id cmd; + + tamagawa_display_menu(); + cmd = tamagawa_get_command(&adf, &edf); + + if(cmd >= DATA_ID_NUM) + { + continue; + } + + tamagawa_update_data_id(priv, cmd); + + /* In case of EEPROM commands, calculate the CRC for the different channels selected */ + if((cmd == DATA_ID_6) || (cmd == DATA_ID_D)) + { + uint32_t ch = 0; + for(ch = 0 ; ch < MAX_CHANNELS ; ch++) + { + if(gTamagawa_multi_ch_mask & 1 << ch) + { + tamagawa_update_crc(priv, cmd, ch); + } + } + + } + + tamagawa_command_process(priv, cmd, gTamagawa_multi_ch_mask); + + if(gTamagawa_is_multi_ch) + { + DebugP_log("\r\n Multi-channel mode is enabled\n\n"); + + uint32_t ch; + for(ch = 0; ch < MAX_CHANNELS; ch++) + { + if(gTamagawa_multi_ch_mask & 1 << ch) + { + tamagawa_multi_channel_set_cur(priv, ch); + DebugP_log("\r\n\r|\n|\t\t\t\tCHANNEL %d\n", ch); + tamagawa_handle_rx(priv, cmd); + } + } + } + else + { + DebugP_log("\r\n Single-channel mode is enabled\n\n"); + tamagawa_handle_rx(priv, cmd); + } + +} + Board_driversClose(); + Drivers_close(); +} diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/.project/project.js b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/.project/project_am263x.js b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/.project/project_am263x.js new file mode 100644 index 0000000..a0af3b6 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/.project/project_am263x.js @@ -0,0 +1,127 @@ +let path = require('path'); + +let device = "am263x"; + +const files = { + common: [ + "uart_tamagawa.c", + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", /*Tamagawa Example base */ + ], +}; + +const libdirs_freertos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa_over_soc_uart/lib" + ], +}; + +const includes_freertos_r5f = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F", + "${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am263x/r5f", + ], +}; + +const libs_freertos_r5f = { + common: [ + "freertos.am263x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am263x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am263x.r5f.ti-arm-clang.${ConfigName}.lib", + "motorcontrol_tamagawa_over_soc_uart.am263x.r5f.ti-arm-clang.${ConfigName}.lib", + + ], +}; + +const defines_r5f = { + common: [ + "SOC_AM263X", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_TAMAGAWA_OVER_UART"; + +const templates_freertos_r5f = +[ + { + input: ".project/templates/am263x/common/linker_r5f.cmd.xdt", + output: "linker.cmd", + }, + { + input: ".project/templates/am263x/freertos/main_freertos.c.xdt", + output: "../main.c", + options: { + entryFunction: "uart_tamagawa", + }, + } +]; + + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am263x-lp", os: "freertos"}, +]; + + + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "tamagawa_diagnostic_soc_uart"; + property.isInternal = false; + property.description = "An Example of tamagawa single channel with soc uart" + property.buildOptionCombos = buildOptionCombos; + property.isSkipTopLevelBuild = false; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + if(buildOption.cpu.match(/r5f*/)) { + if(buildOption.os.match(/freertos*/) ) + { + build_property.includes = includes_freertos_r5f; + build_property.libdirs = libdirs_freertos; + build_property.libs = libs_freertos_r5f; + build_property.templates = templates_freertos_r5f; + } + } + + return build_property; +} + + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/example.syscfg b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/example.syscfg new file mode 100644 index 0000000..f671761 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/example.syscfg @@ -0,0 +1,67 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM263x_beta" --package "ZCZ" --part "AM263x" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.14.0+2667"} + */ + +/** + * Import the modules used in this configuration. + */ +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const uart = scripting.addModule("/drivers/uart/uart", {}, false); +const uart1 = uart.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +gpio1.$name = "CONFIG_GPIO0"; +gpio1.pinDir = "OUTPUT"; +gpio1.GPIO.$assign = "GPIO0"; +gpio1.GPIO.gpioPin.$assign = "ball.J2"; + +uart1.$name = "CONFIG_UART0"; +uart1.operMode = "13X"; +uart1.intrEnable = "DISABLE"; +uart1.inputClkFreq = 192000000; +uart1.baudRate = 2500000; +uart1.UART.$assign = "UART1"; +uart1.UART.RXD.$assign = "ball.L3"; +uart1.UART.TXD.$assign = "ball.M3"; + +debug_log.enableUartLog = true; +debug_log.enableCssLog = false; +debug_log.uartLog.operMode = "13X"; +debug_log.uartLog.$name = "CONFIG_UART_CONSOLE"; +debug_log.uartLog.inputClkFreq = 192000000; +debug_log.uartLog.baudRate = 2500000; +debug_log.uartLog.UART.$assign = "UART0"; +debug_log.uartLog.UART.RXD.$assign = "ball.A7"; +debug_log.uartLog.UART.TXD.$assign = "ball.A6"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x80000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/main.c b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/main.c new file mode 100644 index 0000000..a25111a --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018-2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_board_config.h" +#include "FreeRTOS.h" +#include "task.h" + +#define MAIN_TASK_PRI (configMAX_PRIORITIES-1) + +#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE)) +StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32))); + +StaticTask_t gMainTaskObj; +TaskHandle_t gMainTask; + +void uart_tamagawa(void *args); + +void freertos_main(void *args) +{ + uart_tamagawa(NULL); + + vTaskDelete(NULL); +} + + +int main(void) +{ + /* init SOC specific modules */ + System_init(); + Board_init(); + + /* This task is created at highest priority, it should create more tasks and then delete itself */ + gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */ + "freertos_main", /* Text name for the task. This is to facilitate debugging only. */ + MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */ + NULL, /* We are not using the task parameter. */ + MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */ + gMainTaskStack, /* pointer to stack base */ + &gMainTaskObj ); /* pointer to statically allocated task object memory */ + configASSERT(gMainTask != NULL); + + /* Start the scheduler to start the tasks executing. */ + vTaskStartScheduler(); + + /* The following line should never be reached because vTaskStartScheduler() + will only return if there was not enough FreeRTOS heap memory available to + create the Idle and (if configured) Timer tasks. Heap management, and + techniques for trapping heap exhaustion, are described in the book text. */ + DebugP_assertNoLog(0); + + return 0; +} diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec new file mode 100644 index 0000000..89a680e --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -0,0 +1,114 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd new file mode 100644 index 0000000..7a34f5e --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd @@ -0,0 +1,137 @@ + +/* This is the stack that is used by code running within main() + * In case of NORTOS, + * - This means all the code outside of ISR uses this stack + * In case of FreeRTOS + * - This means all the code until vTaskStartScheduler() is called in main() + * uses this stack. + * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack + */ +--stack_size=16384 +/* This is the heap size for malloc() API in NORTOS and FreeRTOS + * This is also the heap used by pvPortMalloc in FreeRTOS + */ +--heap_size=32768 +-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */ + +/* This is the size of stack when R5 is in IRQ mode + * In NORTOS, + * - Here interrupt nesting is enabled + * - This is the stack used by ISRs registered as type IRQ + * In FreeRTOS, + * - Here interrupt nesting is enabled + * - This is stack that is used initally when a IRQ is received + * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks + * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more + */ +__IRQ_STACK_SIZE = 256; +/* This is the size of stack when R5 is in IRQ mode + * - In both NORTOS and FreeRTOS nesting is disabled for FIQ + */ +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */ +__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */ +__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */ + +SECTIONS +{ + /* This has the R5F entry point and vector table, this MUST be at 0x0 */ + .vectors:{} palign(8) > R5F_VECS + + /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000 + * i.e this cannot be placed in DDR + */ + GROUP { + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */ + } > OCRAM + + /* This is rest of code. This can be placed in DDR if DDR is available and needed */ + GROUP { + .text: {} palign(8) /* This is where code resides */ + .rodata: {} palign(8) /* This is where const's go */ + } > OCRAM + + /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + + .data: {} palign(8) /* This is where initialized globals and static go */ + } > OCRAM + + /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */ + GROUP { + .bss: {} palign(8) /* This is where uninitialized globals go */ + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) /* This is where the malloc heap goes */ + .stack: {} palign(8) /* This is where the main() stack goes */ + } > OCRAM + + /* This is where the stacks for different R5F modes go */ + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > OCRAM + + /* Sections needed for C++ projects */ + GROUP { + .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */ + .init_array: {} palign(8) /* Contains function pointers called before main */ + .fini_array: {} palign(8) /* Contains function pointers called after main */ + } > OCRAM + + /* General purpose user shared memory, used in some examples */ + .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM + /* this is used when Debug log's to shared memory are enabled, else this is not used */ + .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM + /* this is used only when IPC RPMessage is enabled, else this is not used */ + .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM + /* this is used only when Secure IPC is enabled */ + .bss.sipc_hsm_queue_mem (NOLOAD) : {} > MAILBOX_HSM + .bss.sipc_r5f_queue_mem (NOLOAD) : {} > MAILBOX_R5F +} + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040 + R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0 + R5F_TCMB : ORIGIN = 0x00080000 , LENGTH = 0x00008000 + + /* when using multi-core application's i.e more than one R5F/M4F active, make sure + * this memory does not overlap with other R5F's + */ + OCRAM : ORIGIN = 0x70040000 , LENGTH = 0x40000 + + /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with + * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable + */ + FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000 + + + /* shared memories that are used by RTOS/NORTOS cores */ + /* On R5F, + * - make sure there is a MPU entry which maps below regions as non-cache + */ + USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x00004000 + LOG_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x00004000 + /* MSS mailbox memory is used as shared memory, we dont use bottom 32*12 bytes, since its used as SW queue by ipc_notify */ + RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x72000000, LENGTH = 0x3E80 + MAILBOX_HSM: ORIGIN = 0x44000000 , LENGTH = 0x000003CE + MAILBOX_R5F: ORIGIN = 0x44000400 , LENGTH = 0x000003CE + } diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/makefile new file mode 100644 index 0000000..c3bfe8c --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/makefile @@ -0,0 +1,279 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak +include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=tamagawa_diagnostic_soc_uart.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME:=tamagawa_diagnostic_soc_uart.$(PROFILE).appimage +BOOTIMAGE_NAME_XIP:=tamagawa_diagnostic_soc_uart.$(PROFILE).appimage_xip +BOOTIMAGE_NAME_SIGNED:=tamagawa_diagnostic_soc_uart.$(PROFILE).appimage.signed +BOOTIMAGE_RPRC_NAME:=tamagawa_diagnostic_soc_uart.$(PROFILE).rprc +BOOTIMAGE_RPRC_NAME_XIP:=tamagawa_diagnostic_soc_uart.$(PROFILE).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=tamagawa_diagnostic_soc_uart.$(PROFILE).rprc_tmp + +FILES_common := \ + uart_tamagawa.c \ + main.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + ../../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ + -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am263x/r5f \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM263X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa_over_soc_uart/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lfreertos.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lmotorcontrol_tamagawa_over_soc_uart.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + + +LIBS_NAME = \ + freertos.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + motorcontrol_tamagawa_over_soc_uart.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa_over_soc_uart/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am263x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am263x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(BOOTIMAGE_NAME) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am263x:r5fss0-0:freertos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am263x:r5fss0-0:freertos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am263x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_NAME_XIP) + $(RM) $(BOOTIMAGE_NAME_SIGNED) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(RM) $(BOOTIMAGE_RPRC_NAME_XIP) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am263x:r5fss0-0:freertos:ti-arm-clang tamagawa_diagnostic_soc_uart ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part AM263x --package ZCZ --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_MCUPLUSSDKPRODUCT) --product $(SYSCFG_SDKPRODUCT) --device AM263x_beta --context r5fss0-0 --part AM263x --package ZCZ --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + + +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_r5fss1-0 = 2 +BOOTIMAGE_CORE_ID_r5fss1-1 = 3 +SBL_RUN_ADDRESS=0x70002000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +$(BOOTIMAGE_NAME): $(OUTNAME) + @echo Boot image: am263x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifneq ($(OS),Windows_NT) + $(CHMOD) a+x $(XIPGEN_CMD) +endif + $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am263x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + @echo . + +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 0000000..7e5331d --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,84 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage +BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip +BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed +BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc +BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip +BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp + +# +# Generation of boot image which can be loaded by Secondary Boot Loader (SBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +BOOTIMAGE_CORE_ID_r5fss0-0 = 0 +BOOTIMAGE_CORE_ID_r5fss0-1 = 1 +BOOTIMAGE_CORE_ID_r5fss1-0 = 2 +BOOTIMAGE_CORE_ID_r5fss1-1 = 3 +SBL_RUN_ADDRESS=0x70002000 +SBL_DEV_ID=55 + +MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js +OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js + +ifeq ($(OS),Windows_NT) + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe +else + XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out +endif + +MULTI_CORE_IMAGE_PARAMS = \ + $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +MULTI_CORE_IMAGE_PARAMS_XIP = \ + $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \ + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am263x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME) + $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP) + $(RM) $(BOOTIMAGE_RPRC_NAME) + $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE) + $(RM) $(BOOTIMAGE_RPRC_NAME_TMP) + @echo Boot image: am263x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +endif diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec new file mode 100644 index 0000000..028f196 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 0000000..472ab38 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/examples/motor_control/tamagawa_diagnostic_over_soc_uart/uart_tamagawa.c b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/uart_tamagawa.c new file mode 100644 index 0000000..3e8fba9 --- /dev/null +++ b/examples/motor_control/tamagawa_diagnostic_over_soc_uart/uart_tamagawa.c @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* This example demonstrates the UART RX and TX operation by echoing char + * that it recieves in blocking, interrupt mode of operation. + * When user types 'quit', the application ends. + */ +#include +#include +#include + +#include +#include "ti_drivers_config.h" +#include "ti_drivers_open_close.h" +#include "ti_board_open_close.h" +#include + +extern UART_Handle gUartHandle[CONFIG_UART_NUM_INSTANCES]; +volatile struct tamagawa_uart_interface TamagawaInterfaceInstance; + +volatile struct tamagawa_uart_interface *tamagawa_interface = &TamagawaInterfaceInstance; + +void tamagawa_display_result(int32_t cmd) +{ + /* Prints the position value returned by the encoder for a particular command ID */ + switch(cmd) + { + case DATA_ID_7: + /* Reset */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", tamagawa_interface->rx.abs, tamagawa_interface->rx.sf, tamagawa_interface->rx.cf, tamagawa_interface->rx.crc); + break; + + case DATA_ID_8: + /* Reset */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", tamagawa_interface->rx.abs, tamagawa_interface->rx.sf, tamagawa_interface->rx.cf, tamagawa_interface->rx.crc); + break; + + case DATA_ID_C: + /* Reset */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", tamagawa_interface->rx.abs, tamagawa_interface->rx.sf, tamagawa_interface->rx.cf, tamagawa_interface->rx.crc); + break; + + case DATA_ID_0: + /* Data readout: data in one revolution */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", tamagawa_interface->rx.abs, tamagawa_interface->rx.sf, tamagawa_interface->rx.cf, tamagawa_interface->rx.crc); + break; + + case DATA_ID_1: + /* Data readout: multi-turn data */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABM: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", tamagawa_interface->rx.abm, tamagawa_interface->rx.sf, tamagawa_interface->rx.cf, tamagawa_interface->rx.crc); + break; + + case DATA_ID_2: + /* Data readout: encoder ID */ + DebugP_log("\r\n| "); + DebugP_log("\r\nENID: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", tamagawa_interface->rx.enid, tamagawa_interface->rx.sf, tamagawa_interface->rx.cf, tamagawa_interface->rx.crc); + break; + + case DATA_ID_3: + /* Data readout: data in one revolution, encoder ID, multi-turn, encoder error */ + DebugP_log("\r\n| "); + DebugP_log("\r\nABS: 0x%x\tENID: 0x%x\tABM: 0x%x\tALMC: 0x%x\tSF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", tamagawa_interface->rx.abs, tamagawa_interface->rx.enid, tamagawa_interface->rx.abm, tamagawa_interface->rx.almc, tamagawa_interface->rx.sf, tamagawa_interface->rx.cf, tamagawa_interface->rx.crc); + break; + + case DATA_ID_6: + /* EEPROM Write */ + DebugP_log("\r\n| "); + DebugP_log("\r\nEDF: 0x%x\tADF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", tamagawa_interface->rx.edf, tamagawa_interface->rx.adf, tamagawa_interface->rx.cf, tamagawa_interface->rx.crc); + break; + + case DATA_ID_D: + /* EEPROM Read */ + DebugP_log("\r\n| "); + DebugP_log("\r\nEDF: 0x%x\tADF: 0x%x\tCF: 0x%x\tCRC: 0x%x\t\n", tamagawa_interface->rx.edf, tamagawa_interface->rx.adf, tamagawa_interface->rx.cf, tamagawa_interface->rx.crc); + break; + + default: + DebugP_log("\r\n| ERROR: unknown Data ID\n"); + break; + } +} + +static enum data_id tamagawa_get_command() +{ + int32_t cmd; + uint32_t val; + /* Check to make sure that the command issued is correct */ + if(DebugP_scanf("%d\n", &cmd) < 0) + { + cmd = DATA_ID_0; + DebugP_log("\r\n| WARNING: invalid Data ID, Data readout Data ID 0 will be sent\n"); + } + /* Check to make sure that the command issued is correct */ + if(cmd >= DATA_ID_NUM) + { + cmd = DATA_ID_0; + DebugP_log("\r\n| WARNING: invalid Data ID, Data readout Data ID 0 will be sent\n"); + } + /* In case of EEPROM commands */ + if((cmd == DATA_ID_D) || (cmd == DATA_ID_6)) + { + DebugP_log("\r| enter EEPROM address (hex value): "); + if(DebugP_scanf("%x\n", &val) < 0) + { + cmd = DATA_ID_NUM; + DebugP_log("\r| ERROR: invalid EEPROM address\n|\n"); + } + if(val > MAX_EEPROM_ADDRESS) + { + cmd = DATA_ID_NUM; + DebugP_log("\r| ERROR: invalid EEPROM address\n|\n"); + } + tamagawa_interface->tx.adf = (uint8_t)val; + + } + /* In case of EEPROM Write */ + if(cmd == DATA_ID_6) + { + DebugP_log("\r| enter EEPROM data (hex value): "); + if(DebugP_scanf("%x\n", &val) < 0) + { + cmd = DATA_ID_NUM; + DebugP_log("\r| ERROR: invalid EEPROM address\n|\n"); + } + if(val > MAX_EEPROM_WRITE_DATA) + { + cmd = DATA_ID_NUM; + DebugP_log("\r| ERROR: invalid EEPROM address\n|\n"); + } + tamagawa_interface->tx.edf = (uint8_t)val; + + } + return cmd; +} +static void tamagawa_display_menu(void) +{ + DebugP_log("\r\n|------------------------------------------------------------------------------|"); + DebugP_log("\r\n| Select DATA ID Code |"); + DebugP_log("\r\n|------------------------------------------------------------------------------|"); + DebugP_log("\r\n| 0 : Data readout, Absolute (Data ID 0) |"); + DebugP_log("\r\n| 1 : Data readout, Multi-turn (Data ID 1) |"); + DebugP_log("\r\n| 2 : Data readout, Encoder-ID (Data ID 2) |"); + DebugP_log("\r\n| 3 : Data readout, Absolute & Multi-turn (Data ID 3) |"); + DebugP_log("\r\n| 4 : Writing to EEPROM (Data ID 6) |"); + DebugP_log("\r\n| 5 : Reset (Data ID 7) |"); + DebugP_log("\r\n| 6 : Reset (Data ID 8) |"); + DebugP_log("\r\n| 7 : Reset (Data ID C) |"); + DebugP_log("\r\n| 8 : Readout from EEPROM (Data ID D) |"); + DebugP_log("\r\n|------------------------------------------------------------------------------|\n|\n"); + DebugP_log("\r\n| enter value: "); +} + +void uart_tamagawa(void *args) +{ + Drivers_open(); + Board_driversOpen(); + + + uint32_t uart_communication_instance = CONFIG_UART0; + uint32_t uart_gpio_base_address = CSL_GPIO0_U_BASE; + uint32_t uart_gpio_pin_number = CONFIG_GPIO0_PIN; + uint32_t uart_gpio_pin_direction = GPIO_DIRECTION_OUTPUT; + + tamagawa_init(tamagawa_interface, uart_communication_instance, uart_gpio_base_address, uart_gpio_pin_number, uart_gpio_pin_direction); + DebugP_log("[UART] Tamagawa example started ...\r\n"); + while(1) + { + enum data_id cmd; + int32_t status; + + tamagawa_display_menu(); + cmd = tamagawa_get_command(); + + if(cmd >= DATA_ID_NUM) + { + continue; + } + + status = tamagawa_command_process(tamagawa_interface, gUartHandle, cmd); + /* Case of command process failure */ + + if (status < 0) + { + DebugP_log("\r\n ERROR: Command process failure \n"); + continue; + } + + if (tamagawa_crc_verify(tamagawa_interface) == 1) + { + DebugP_log("\r\n CRC success \n"); + tamagawa_display_result(cmd); + } + else + { + DebugP_log("\r\n CRC Failure \n"); + } + + } + + Board_driversClose(); + Drivers_close(); + + return; + +} diff --git a/imports.mak b/imports.mak new file mode 100644 index 0000000..5db0cc4 --- /dev/null +++ b/imports.mak @@ -0,0 +1,56 @@ + +DEVICE ?= am64x + +ifeq ($(OS),Windows_NT) + TOOLS_PATH?=C:/ti + CCS_PATH?=$(TOOLS_PATH)/ccs1210/ccs + CCS_ECLIPSE=$(CCS_PATH)/eclipse/eclipsec + CYGWIN_PATH?=$(CCS_PATH)/utils/cygwin + MKDIR=$(CYGWIN_PATH)/mkdir -p + RMDIR=$(CYGWIN_PATH)/rm -rf + RM=$(CYGWIN_PATH)/rm -f + COPY=$(CYGWIN_PATH)/cp + TOUCH=$(CYGWIN_PATH)/touch + PATHSEP=\\ + CHMOD=$(CYGWIN_PATH)/echo + SHELL=cmd.exe + CGT_GCC_AARCH64_PATH=$(TOOLS_PATH)/gcc-arm-9.2-2019.12-mingw-w64-i686-aarch64-none-elf + CGT_GCC_ARM_PATH=$(TOOLS_PATH)/gcc-arm-none-eabi-7-2017-q4-major-win32 + CGT_GCC_ARMV7_PATH=$(CGT_GCC_ARM_PATH) +else + UNAME_S := $(shell uname -s) + ifeq ($(UNAME_S),Linux) + export TOOLS_PATH?=$(HOME)/ti + export CCS_PATH?=$(TOOLS_PATH)/ccs1210/ccs + export CCS_ECLIPSE=$(CCS_PATH)/eclipse/eclipse + export MKDIR=mkdir -p + export RMDIR=rm -rf + export RM=rm -f + export COPY=cp + export TOUCH=touch + export PATHSEP=/ + export CHMOD=chmod + CGT_GCC_AARCH64_PATH=$(TOOLS_PATH)/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf + CGT_GCC_ARM_PATH=$(TOOLS_PATH)/gcc-arm-none-eabi-7-2017-q4-major + CGT_GCC_ARMV7_PATH=$(CGT_GCC_ARM_PATH) + endif +endif + +# Variable pointing to location of MCU+ SDK +export MCU_PLUS_SDK_PATH?=$(TOOLS_PATH)/mcu_plus_sdk_am64x_09_00_00_01 + +CGT_TI_PRU_PATH=$(TOOLS_PATH)/ti-cgt-pru_2.3.3 +CGT_TI_SMART_PLACEMENT_TOOL_PATH=$(TOOLS_PATH)/ti-cgt-armllvm_3.0.0.STS +CGT_TI_ARM_CLANG_PATH=$(CCS_PATH)/tools/compiler/ti-cgt-armllvm_2.1.2.LTS +ifeq ($(wildcard $(CGT_TI_ARM_CLANG_PATH)),) + CGT_TI_ARM_CLANG_PATH=$(TOOLS_PATH)/ti-cgt-armllvm_2.1.2.LTS +endif +CGT_TI_C6000_PATH=$(CCS_PATH)/tools/compiler/ti-cgt-c6000_8.3.12 +DSPLIB_PATH=$(MCU_PLUS_SDK_PATH)/source/dsplib_c66x_3_4_0_0 +CCS_NODE = $(CCS_PATH)/tools/node/node +SYSCFG_PATH ?= $(TOOLS_PATH)/sysconfig_1.14.0 +SYSCFG_CLI_PATH ?= $(SYSCFG_PATH) +SYSCFG_NODE = $(SYSCFG_PATH)/nodejs/node +SYSCFG_NWJS = $(SYSCFG_PATH)/nw/nw +SYSCFG_SDKPRODUCT=$(MOTOR_CONTROL_SDK_PATH)/.metadata/product.json +SYSCFG_MCUPLUSSDKPRODUCT=$(MCU_PLUS_SDK_PATH)/.metadata/product.json diff --git a/license.txt b/license.txt new file mode 100644 index 0000000..341a2b1 --- /dev/null +++ b/license.txt @@ -0,0 +1,176 @@ + +Texas Instruments Incorporated +Evaluation Software License Agreement + +IMPORTANT – PLEASE CAREFULLY READ THIS AGREEMENT, WHICH IS DISPLAYED FOR YOU TO READ PRIOR TO USING THE LICENSED MATERIALS (DEFINED BELOW). YOU WILL BE ASKED WHETHER YOU ACCEPT AND AGREE TO ITS TERMS. BY CLICKING “I ACCEPT” OR “I AGREE,” OR BY USING THE LICENSED MATERIALS, YOU (1) REPRESENT THAT YOU HAVE THE LEGAL CAPACITY AND AUTHORITY TO BIND YOURSELF OR YOUR COMPANY, AS APPLICABLE, TO THE TERMS OF THIS AGREEMENT AND (2) AGREE ON BEHALF OF YOURSELF OR YOUR COMPANY, AS APPLICABLE, TO BE BOUND BY THE TERMS OF THIS AGREEMENT. IF YOU CHOOSE NOT TO ACCEPT OR AGREE WITH ANY OF THESE PROVISIONS, YOU HAVE NO RIGHT TO DOWNLOAD, INSTALL, OR USE THE LICENSED MATERIALS. + +In certain instances, TI may deliver the Licensed Materials with Other Software not subject to the terms of this Agreement. Your use of Other Software is subject to the terms of the applicable software license(s) listed in the accompanying software manifest, header files, text files, or other location customarily used for licensing terms. You must agree to the terms of each applicable license, or You cannot use the Other Software. TI provides Other Software on an “as is” basis, without any representation, warranty, or liability to TI of any kind. + +1. Definitions. As used in this Agreement, the following capitalized terms will have the meanings set forth below: + +a. “Agreement” means this Software License Agreement. + +b. “Company” means the entity on whose behalf You are acting, if applicable. + +c. “Derived Patents” means any of Your patents issuing from a patent application that discloses and claims an invention conceived of by You after delivery of the Licensed Materials, and derived by You from Your access to the Licensed Materials. + +d. “Evaluation Licensed Materials” means Licensed Materials other than Software Tools or Output. + +e. “High-Risk Application” means any application where the failure of such application could lead to death, personal injury, or severe physical, property, or environmental damage, including, without limitation, any safety-critical application or Life-Critical-Medical Application. + +f. “Licensed Materials” means each of the following (in whole or in part): (i) the software programs, configuration files, any real time operating system, and/or data files listed in the accompanying software manifest with a license type of “TI Commercial”, (ii) documentation related to these programs, (iii) any updates or upgrades to such software programs or documentation provided to You at TI’s sole discretion; (iv) Software Tools; and (v) any portions of the aforementioned software and documentation included in any Output, whether in original form or as transformed by compiling, linking, or other operation. + +g. “Licensee Product” means Your product that incorporates (i) hardware components, including one or more TI Devices, and (ii) software components, including only binary or other executable versions of the Licensed Materials. + +h. “Life-Critical-Medical Application” means any medical application where failure of such application would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such applications include, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. + +i. “Other Software” means any software components identified in the accompanying software manifest with a license type other than “TI Commercial” including but not limited to open source software and certain third-party software. + +j. “Output” means any binary, textual, or other output produced or generated by Software Tools. + +k. “Software Tools” means programs that may be used to develop, debug, maintain, or otherwise support other programs and applications. + +l. “TI Devices” means semiconductor devices or evaluation kits (EVMs) manufactured by or for TI and sold or otherwise provided to You by TI or a TI-authorized distributor. + +m. “You” means you personally if you will exercise the rights granted for your own benefit, but it means your Company, if you will exercise the rights granted herein for your Company’s benefit. + +2. License Grant and Use Restrictions. + +a. Evaluation Licensed Materials. For Evaluation Licensed Materials the following license grants apply. Subject to the terms of this Agreement: + +(i) Source Code Internal Use License. If any of the Evaluation Licensed Materials are provided to You in source code form, TI grants to You a limited, non-transferable, non-exclusive, non-assignable, non-sublicensable, fully paid-up, royalty-free license to copy, prepare derivative works, and use internally such Evaluation Licensed Materials, only to develop versions of such Evaluation Licensed Materials that execute solely and exclusively on or in connection with TI Devices, for end use (in object and executable form only) in Licensee Products. + +(ii) Object Code Internal Use License. TI grants to You a limited, non-transferable, non-exclusive, non-assignable, non-sublicensable, fully paid-up, royalty-free license to copy and use internally the Evaluation Licensed Materials in object code only for evaluating and testing the Evaluation Licensed Materials and designing and developing the Licensee Products. + +(iii) Demonstration License. TI grants to You a limited, non-transferable, non-exclusive, non-assignable, non-sublicensable, fully paid-up, royalty-free license to demonstrate to third parties the Evaluation Licensed Materials when used solely and exclusively on or in connection with TI Devices as they are used in TI evaluation kits and Licensee Products, provided that such Evaluation Licensed Materials are demonstrated in binary or executable versions only and are not left with or retained by such third parties. + +b. Software Tools. If any Software Tools are included in the Licensed Materials, the following license grants apply. Subject to the terms of this Agreement: + +(i) Internal Use License. TI grants to You a limited, non-transferable, non-exclusive, non-assignable, non-sublicensable, fully paid-up, royalty-free license to copy and use internally the Software Tools solely and exclusively in connection with the design, development, production, sale, maintenance, and support of Licensee Products. + +(ii) Output License Grant. To the extent necessary to enable distribution of the Output, TI grants to You a non-transferable, non-assignable, non-exclusive, fully paid-up, royalty-free license to use, copy, distribute, and sublicense (in binary or executable form) the portions of the Software Tool included in the Output (“Included Tool SW”), solely in conjunction with the design, development, production, sale, support, and use of Licensee Products, provided You distribute and sublicense the Included Tool SW under a written license with terms at least as restrictive and protective as, and not inconsistent with, the terms of this Agreement. + + +c. Contractors. The licenses granted to You in this Agreement include Your on-site and off-site contractors (either an individual or entity), while such contractors are performing work for or providing services to You, provided that such contractors have executed work-for-hire agreements with You containing applicable terms and conditions consistent with the terms and conditions set forth in this Agreement and provided further that You are liable to TI for any breach by Your contractors of the terms of this Agreement to the same extent as You would be if You had breached the terms of this Agreement Yourself. + +d. No Other License. Nothing in this Agreement will be construed as a license to any intellectual property rights of TI other than those rights embodied in the Licensed Materials provided to You by TI. EXCEPT AS PROVIDED HEREIN, NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY TI INTELLECTUAL PROPERTY RIGHTS IS GRANTED HEREIN. + +NOTWITHSTANDING ANYTHING TO THE CONTRARY, THIS AGREEMENT DOES NOT CONVEY ANY LICENSE TO USE THE EVALUATION LICENSED MATERIALS IN PRODUCTION, OR TO DISTRIBUTE THE EVALUATION LICENSED MATERIALS TO ANY THIRD PARTY. + +YOU ARE REQUIRED TO EXECUTE A SEPARATE LICENSE AGREEMENT BEFORE MANUFACTURING OR DISTRIBUTING THE EVALUATION LICENSED MATERIALS OR ANY PRODUCTS THAT CONTAIN THE EVALUATION LICENSED MATERIALS. + +e. Indemnification. No unauthorized use or distribution of the Licensed Materials will impose any liability on TI, or any of its licensors, whether implied, by estoppel, through course of dealing, or otherwise. You agree to indemnify TI, its affiliates, and its licensors against any claims, losses, and damages based on Your unauthorized use or distribution of, or modifications to, the Licensed Materials. + +f. Limited License to TI. + +(i) You grant to TI, TI’s affiliates, and their respective licensees of the Licensed Materials, under all intellectual property rights that You own or control, a non-transferable, non-exclusive, non-assignable, worldwide, free license to make, use, sell, offer to sell, import, export, and distribute the Licensed Materials, the Output, or portions of either, including any of Your patents enforceable during the term of this Agreement to the extent such patents contain claims that read on the Licensed Materials or any portion thereof. The foregoing license will automatically terminate upon termination of this Agreement and Your compliance with Section 2.h below. + +(ii) If the Licensed Materials include source code, You further grant to TI and its affiliates and licensees a license to Your Derived Patents. If You assign a Derived Patent, You will require as a condition of any such assignment that the assignee agree to be bound by the provisions in this Section 2.f with respect to such Derived Patent. Any attempted assignment or transfer in violation of this Section 2.f will be void. + +g. Restrictions. Nothing in the licenses granted by this Agreement may be construed to allow You to, and You also agree that You will not encourage, allow, or facilitate any third party to: + + +(i) disclose source code versions of the Licensed Materials to any person other than Your employees and contractors (if permitted) whose job performance requires access; + +(ii) use the Licensed Materials with a processing device other than a TI Device; + +(iii) use Output other than in connection with the design, development, production, sale, and support of Licensee Products; + +(iv) use the Licensed Materials to analyze or prove infringement of any of Your patents by either TI or TI’s customers; + +(v) copy, publish, disclose, display, provide, transfer or make available the Licensed Materials to any third party, except as provided in this Agreement; + +(vi) sublicense, transfer, or assign the Licensed Materials or Your rights under this Agreement to any third party, except as provided in this Agreement; + +(vii) mortgage, pledge or encumber the Licensed Materials; + +(viii) incorporate, combine or distribute the Licensed Materials in a manner that subjects the Licensed Materials to any license obligations or any other intellectual property related terms of any open source license; or + +(ix) use the Licensed Materials in the development of a product or technology that competes with a TI product or technology. + +Any additional third-party license restrictions in Exhibit A (which is attached and incorporated herein), will apply to Your use of the applicable Licensed Materials and You must comply with such restrictions. To the extent there is a conflict between this Agreement and Exhibit A, the terms of Exhibit A will prevail. + +h. Termination. This Agreement is effective as of the date the Licensed Materials are delivered to You and will remain in full force and effect until terminated. You may terminate this Agreement by written notice to TI. Without prejudice to any other rights, TI may terminate Your right to use the Licensed Materials upon written notice to You if (i) You breach this Agreement, (ii) You are acquired or You transfer ownership of substantially all Your assets, or (iii) at any time after two (2) years following the date the Licensed Materials are delivered to You. Upon termination of this Agreement, You will promptly terminate all sub-licenses and destroy all copies of the Licensed Materials and any Output in Your possession, custody, or control, and upon TI’s request, provide to TI a written statement signed by Your authorized representative certifying such termination and destruction. Except for Sections 2.a and 2.b, and 2.f(i), all provisions of this Agreement will survive termination of this Agreement. Section 2.f(i) will survive termination, but only until compliance with this Section 2.h. + +3. Licensed Materials Ownership. The Licensed Materials are licensed, not sold to You, and may only be used under the terms of this Agreement. Subject to the licenses granted to You under this Agreement, TI and TI’s licensors own and will continue to own all right, title, and interest in and to the Licensed Materials, including all copies thereof. You agree that all fixes, modifications, and improvements to the Licensed Materials that are conceived of or made by TI based, in whole or in part, on Your feedback, suggestions, or recommendations are the exclusive property of TI, and all right, title, and interest in and to such fixes, modifications, or improvements to the Licensed Materials will vest solely in TI. You acknowledge and agree that when Your independently developed software or hardware components are combined, in whole or in part, with the Licensed Materials, Your right to use the combined work that includes the Licensed Materials remains subject to the terms of this Agreement. + +4. Intellectual Property Rights. + +a. The Licensed Materials contain copyrighted material, trade secrets, and other proprietary information of TI and its licensors and are protected by copyright, trade secret, and other intellectual property laws and international treaties. To protect TI’s and its licensors’ rights in the Licensed Materials, You agree, except as specifically permitted by any statutory provision that cannot be contractually waived, not to unlock, decompile, reverse engineer, disassemble, or otherwise translate to a human-perceivable form any portions of the Licensed Materials provided to You in object code format only, nor encourage, allow, or facilitate any third party to do so. Unless a TI-authorized representative provides prior written consent, You will not remove, alter, cover, or obscure any confidentiality, trade secret, trade mark, patent, copyright, or other proprietary notice or other identifying marks or designs from any component of the Licensed Materials and You will reproduce and include in all copies of the Licensed Materials the copyright notice(s) and proprietary legend(s) of TI and its licensors as they appear in the Licensed Materials. TI reserves all rights not specifically granted under this Agreement. + +b. You acknowledge and agree that, except as expressly stated, this Agreement conveys no license to any third party patents, copyrights, or other intellectual property rights and that You are solely responsible for any patent, copyright, or other intellectual property right claim that relates to Your use or distribution of the Licensed Materials or Your use or distribution of Your products that include or incorporate the Licensed Materials. You acknowledge that You are responsible for any fees or royalties that may be payable to any third party based on such third party’s interests in the Licensed Materials or any intellectual property rights that cover implementation of any industry recognized standard, any software program published by any industry recognized standards bodies, or any other proprietary technology. + +5. Audit Right. At TI's request, and within thirty (30) calendar days after receiving written notice, You will permit an internal or independent auditor selected by TI to have access, no more than twice each calendar year (unless the immediately preceding audit revealed a discrepancy) and during Your regular business hours, to all of Your equipment, records, and documents as may contain information bearing upon the use of the Licensed Materials. You will keep full, complete, clear, and accurate records with respect to Your use and distribution of the Licensed Materials for a period beginning with the then-current calendar year and going back three (3) years. + +6. Confidential Information. You acknowledge and agree that the Licensed Materials, including their structure and organization, contain trade secrets and other confidential information of TI and its licensors. You agree: (i) to use the Licensed Materials solely within the scope of the licenses set forth herein; (ii) to maintain the Licensed Materials in strict confidence; (iii) to use at least the same procedures and degree of care that You use to prevent disclosure of Your own confidential information of like importance but in no instance less than reasonable care; (iv) to maintain any source code versions of the Licensed Materials under password control protection; and (v) to prevent disclosure of the Licensed Materials to any third party, except as may be necessary and required in connection with Your rights and obligations hereunder; provided, however, that You may not provide the Licensed Materials to any business organization or group within Your Company or to customers or contractors (if permitted) that design or manufacture semiconductors or spatial light modulators unless TI gives written consent. You may use the Licensed Materials for benchmarking internally against competing products under normal conditions, but will not publish or disclose any benchmarking data to any person other than Your employees who have a need to know. You agree to obtain executed confidentiality agreements with Your employees and contractors (if permitted) having access to the Licensed Materials and to diligently enforce such agreements. You grant permission to TI to disclose Your contact information to TI’s licensors. + +7. Disclaimer of Warranties and Limitations. THE LICENSED MATERIALS ARE PROVIDED “AS IS.” TI AND ITS LICENSORS MAKE NO REPRESENTATIONS, AND DISCLAIM ALL WARRANTIES EXPRESS, IMPLIED, AND STATUTORY, REGARDING THE LICENSED MATERIALS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, SECURITY OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. NO ORAL OR WRITTEN INFORMATION OR ADVICE GIVEN BY TI WILL CREATE ANY WARRANTY. + +NOTHING CONTAINED IN THIS AGREEMENT WILL BE CONSTRUED AS A WARRANTY OR REPRESENTATION BY TI TO MAINTAIN PRODUCTION OF ANY TI DEVICE OR OTHER HARDWARE OR SOFTWARE WITH WHICH THE LICENSED MATERIALS MAY BE USED. + +YOU ACKNOWLEDGE AND AGREE THAT THE LICENSED MATERIALS HAVE NOT BEEN TESTED OR CERTIFIED BY ANY GOVERNMENT AGENCY OR INDUSTRY REGULATORY ORGANIZATION OR ANY OTHER THIRD PARTY ORGANIZATION. YOU AGREE TO USE YOUR INDEPENDENT JUDGMENT IN DEVELOPING YOUR PRODUCTS. YOU AGREE THAT PRIOR TO USING OR INCORPORATING OR DISTRIBUTING THE LICENSED MATERIALS IN OR WITH ANY COMMERCIAL PRODUCT THAT YOU WILL THOROUGHLY TEST THE PRODUCT AND THE FUNCTIONALITY OF THE LICENSED MATERIALS IN OR WITH THAT PRODUCT AND BE SOLELY RESPONSIBLE FOR ANY PROBLEMS OR FAILURES. + +CERTAIN LICENSED MATERIALS MAY BE PRE-RELEASE VERSIONS. PRE-RELEASE VERSIONS DO NOT REPRESENT A FINAL AND GENERALLY AVAILABLE VERSION OF THE LICENSED MATERIALS, AND MAY BE UNDERGOING TESTING AND FURTHER MODIFICATION BY TI. THE PRE-RELEASE VERSIONS ARE NOT AT THE LEVEL OF PERFORMANCE AND COMPATIBILITY OF A FINAL RELEASE VERSION. YOU ACKNOWLEDGE THAT SUCH PRE-RELEASE VERSIONS MAY CONTAIN IRREGULARITIES NOT FOUND IN A FINAL RELEASE VERSION, SUCH AS BUGS, ERRORS, INCONSISTENCIES AND OTHER PROBLEMS, AND THEREFORE ARE NOT INTENDED FOR USE IN PRODUCTION ACTIVITIES OR PRODUCTION PRODUCTS. YOU ARE ADVISED WHEN USING PRE-RELEASE VERSIONS TO SAFEGUARD YOUR COMPUTER SYSTEMS AND BACKUP IMPORTANT DATA, TO USE CAUTION, AND NOT TO RELY IN ANY WAY ON THE CORRECT FUNCTIONING OR PERFORMANCE OF THE PRE-RELEASE VERSIONS. FINAL RELEASE VERSIONS MAY BE DIFFERENT FROM THE PRE-RELEASE VERSIONS, INCLUDING BUT NOT LIMITED TO HAVING DIFFERENT OPERATION OR DIFFERENT FUNCTIONALITY. NOTHING CONTAINED IN THIS AGREEMENT WILL BE CONSTRUED AS A WARRANTY OR REPRESENTATION BY TI TO RELEASE A FINAL RELEASE VERSION OF A PRE-RELEASE VERSION IN THE FUTURE. + +IN NO EVENT WILL TI OR TI’S LICENSORS BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, PUNITIVE OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED, ON ANY THEORY OF LIABILITY, IN CONNECTION WITH OR ARISING OUT OF THIS AGREEMENT OR THE USE OF THE LICENSED MATERIALS, REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF DATA, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, OR LOSS OF USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI’S OR TI’S LICENSORS’ AGGREGATE LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF YOUR USE OF THE LICENSED MATERIALS EXCEED FIVE HUNDRED U.S. DOLLARS (US$500). + +Because some jurisdictions do not allow the exclusion or limitation of incidental or consequential damages or limitation on how long an implied warranty lasts, the above limitations or exclusions may not apply to You. + +8. Data Collection and Sharing. The Licensed Materials may monitor and collect technical data and other information related to Your use of the Licensed Materials, Your computer system or device, and related activity. You hereby agree and acknowledge that TI may freely use and share that information and data (including with or through its affiliates, partners, and service providers) to, among other things, support the Licensed Materials, use to make improvements or enhancements to the Licensed Materials, and develop, promote, support, and enhance TI products and offerings. + +9. Security. + +a. Security. Neither TI nor its licensors will be liable or responsible in any way if unauthorized persons gain access to, copy, change, delete, or damage data, information, applications, code, functions, features, or operation of the Licensee Products. You are responsible for properly configuring and using TI Devices or Licensed Materials and taking Your own independent steps to maintain appropriate security and protection of Your Licensee Products and any associated data from unauthorized access. + +b. Security Keys. If the Licensed Materials are used to embed security keys in TI Devices via e-fusing, this provision applies. You may not use development keys in production. You are solely responsible for evaluating the adequacy of, selecting, obtaining, or generating any keys that may be used in Licensee Products, including obtaining all necessary rights, licenses, and authorizations in and to those keys. TI is not responsible for the integrity, operation, or security of Your keys in TI Devices or their use in Licensee Products, or for the consequences of third parties using, gaining access, overcoming or bypassing such keys. You accept that use of the Licensed Materials to e-fuse (or to attempt to e-fuse) security keys into the TI Devices permanently alters them and, consequently, TI will have no liability (warranty or otherwise) for any such altered TI Devices. + +10. High-Risk Applications. + +a. Safety-Critical Applications. Licensed Materials promoted for safety applications are designed and intended to assist You in Your efforts to develop and create applications that comply with the requirements of certain safety standards. However, Your use of the Licensed Materials does not ensure that Your application will meet the requirements of such safety standards or that it will qualify for certification to any particular safety standard. Furthermore, You remain responsible for using Your knowledge and independent judgment to determine the requirements for performance and testing of Your applications as may be (i) required to meet applicable state, national, international and regulatory safety standards, or (ii) required or recommended by functional safety standards. Licensed Materials that are not promoted for safety applications are not designed or intended for use in safety-critical applications and any such use is at Your own risk. + +b. Life-Critical-Medical Applications. You may not use the Licensed Materials in or with Life-Critical-Medical Applications unless authorized officers of the parties have executed a special contract specifically governing such use. + +c. Indemnification. If You use the Licensed Materials in a High-Risk Application, You will defend, indemnify, and hold TI harmless against any and all loss, liability, cost, or damage that TI incurs as a result of such use. + +11. Indemnification Disclaimer. YOU ACKNOWLEDGE AND AGREE THAT TI AND TI’S LICENSORS WILL NOT BE LIABLE FOR AND WILL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY THIRD-PARTY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON YOUR MANUFACTURE, USE, OR DISTRIBUTION OF THE LICENSED MATERIALS OR YOUR MANUFACTURE, USE, OFFER FOR SALE, SALE, IMPORTATION OR DISTRIBUTION OF YOUR PRODUCTS THAT INCLUDE OR INCORPORATE THE LICENSED MATERIALS. + +12. No Technical Support Obligation. TI and TI’s licensors have no obligation to install, maintain or support the Licensed Materials. + +13. Notices. All notices to TI will be delivered to Texas Instruments Incorporated, 13588 N. Central Expressway, Mail Station 3999, Dallas, Texas 75243, Attention: Contracts Administration, with a copy to TILegalNotices@list.TI.com. All notices will be deemed served when received by TI. + +14. U.S. Government Contracts. If You intend to use the Licensed Materials in the performance of a U.S. Government contract or subcontract subject to Federal Acquisition Regulation (FAR), TI agrees to comply only with the commercial-item subcontractor flowdown provisions identified in FAR 52.244-6 (July 2021) to the extent such provisions apply to the types of Licensed Materials provided by TI to You. Unless otherwise agreed in writing by an authorized TI representative, no other FAR provisions, FAR supplement provisions, or other government procurement rules will apply to TI by virtue of any sale of provision of TI goods and services. Specifically, and without derogation to the foregoing limitation, TI will not provide, and no submission should be deemed as providing, certified cost or pricing data, and TI will not be subject to provisions governing cost allowability, cost accounting, and/or audit rights that may be found in Your U.S. Government contract or subcontract. + +TI technical data and computer software are generally developed at TI’s private expense and not in performance of a U.S. Government contract. TI asserts and should be understood by You and the U.S. Government as retaining proprietary rights in all technical data and computer software provided to You under a U.S. Government contract. Unless separately and expressly agreed in writing by an authorized TI representative, neither the U.S. Government nor any higher-tier contractor under a U.S. Government contract will obtain any rights in TI technical data and computer software beyond the rights provided to TI’s commercial customers for such technical data and computer software. +. +15. Export Control. + +a. Exports, re-exports, and transfers of Licensed Materials may be subject to U.S. export controls and sanctions. You acknowledge and agree that: i) You will comply with all applicable laws and regulations; ii) Licensed Materials may not be exported, re-exported, sold or transferred to U.S. embargoed, sanctioned, or restricted destinations, persons, or entities without first obtaining any necessary governmental authorization; and iii) You will provide notice of these compliance obligations to any party obtaining Licensed Materials from You. + +b. Unless any necessary U.S. and other applicable government authorizations are obtained in advance, You may not export, re-export, transfer, purchase, or sell (including, without limitation, by permitting the Licensed Materials to be downloaded) any Licensed Materials: (i) for a military end use; (ii) to a military end user; or (iii) for the design, development, fabrication, or use of nuclear, chemical, or biological weapons or missile technology. For additional information, see Part 744 of the U.S. Export Administration Regulations. + +c. Each party shall, at its own expense, secure export and import authorizations necessary to fulfill its obligations under this Section 15. You will indemnify and hold TI (including its agents and representatives) harmless against any damages, costs, losses, and/or liabilities arising out of any non-compliance by You with this section. If any required authorization cannot be obtained, or in the event You breach this Section 15, TI may terminate, cancel, or otherwise be excused from any obligations that it may have under this Agreement. Licensed Materials classifications are for TI convenience only and shall not be construed as a representation or warranty of any kind; You are responsible for your own compliance obligations. This section will survive any termination or expiration of this Agreement. + +16. Governing Law; Remedies. This Agreement will be governed by and interpreted under the laws of the State of Texas, without reference to conflict of laws principles. This Agreement will not be governed by the United Nations Convention on Contracts for the International Sale of Goods, or by the Uniform Computer Information Transactions Act (UCITA). The parties agree that non-exclusive jurisdiction for any dispute arising out of or relating to this Agreement lies within the courts in the State of Texas. Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and either party may seek injunctive relief in any United States or foreign court. You agree that any breach of the Agreement or use of the Licensed Materials beyond the scope of the license granted hereunder would cause irreparable harm for which TI’s remedies at law would be inadequate. You agree that TI will be entitled, in addition to any other remedies available to it at law or in equity, to injunctive relief to prevent the breach or threatened breach of any of Your obligations under this Agreement, without the posting of any bond. + +17. Severability; Waiver. If a court of competent jurisdiction finds any provision of the Agreement unenforceable, that provision will be enforced to the maximum extent possible to effectuate the intent of the parties, and the remainder of the Agreement will continue in full force and effect. Failure by TI to enforce any provision of this Agreement will not be deemed a waiver of future enforcement of that or any other provision in this Agreement or any other agreement that may be in place between the parties. + +18. Contingencies. TI will not be in breach of this Agreement and will not be liable for any non-performance or delay in performance if such non-performance or delay is due to a force majeure event or other circumstances beyond TI’s reasonable control. + +19. Entire Agreement. This is the entire agreement between You and TI, and this Agreement supersedes any prior agreement between the parties related to the subject matter of this Agreement. Notwithstanding the foregoing, any signed and effective software license agreement relating to the subject matter will take precedence over this Agreement if such agreement states it will control regardless of any prior or subsequent click-wrap, shrink-wrap, or web-wrap software license agreement. No amendment or modification of this Agreement will be effective unless in writing and signed by a duly authorized representative of TI. You warrant and represent that You have obtained all authorizations and other applicable consents required empowering You to enter into this Agreement. + + +Exhibit A +Additional Third-Party License Restrictions + +For Beckhoff EtherCAT SSC Library, the following terms shall apply: + +"The EtherCAT Slave Stack is licensed for evaluation only. Subject to the terms of this Agreement, TI hereby grants to you a limited, non-transferable, worldwide, non-exclusive, non-sublicensable license to use the Licensed Materials as part of the software development kit containing EtherCAT Slave Stack software licensed by Beckhoff Automation GmBH, in connection with the Demo Board, for the sole purpose of evaluating the Licensee Product. For purposes of this Agreement, (A) “EtherCAT Slave Stack” shall be construed to refer to ""EtherCAT® software, which is a registered trademark and patented software, licensed by Beckhoff Automation GmbH, Germany; and (B) “Demo Board” means Generic EtherCAT Slave Controller demonstration hardware consisting of (i) a PCB including electronic circuitry, e.g. microprocessors of TI, and a Generic EtherCAT Slave Controller, designed, developed and manufactured by or on behalf of TI, and (ii) the EtherCAT Slave Stack software provided as part of the Licensed Materials. +The following additional restrictions apply to the use of the EtherCAT Slave Stack: +i. You shall not distribute Licensee Products that contain the EtherCAT Technology without a separate agreement with Beckhoff Automation GmbH. +ii. You shall have no right to further sub-license the Licensed Materials. +iii. You shall obtain a separate production license from Beckhoff Automation GmbH as per paragraph 3(c)(i) above. +iv. You agree that the Licensed Materials are provided to you “AS IS” and without any warranty and Beckhoff Automation GmbH and TI disclaim any and all liabilities to you with respect to the Licensed Materials; +v. You may not create, distribute and/or sell derivative works of the Licensed Materials or instruct any third party to do this; +vi. You may not sublicense, rent, lease, loan, timeshare, sell, distribute, disclose, publish, assign or transfer any rights, grant a security interest in, transfer possession of the Licensed Materials or its components; and +vii. You may not reengineer, translate, reverse engineer, decompile, disassemble or attempt to derive the source code of the Licensed Materials or components of the Licensed Materials or any algorithms, concepts, techniques, methods or processes embodied herein provided to you in object code, or create derivative works of the Licensed Materials or instruct any third party do any of the foregoing.""" + diff --git a/makefile b/makefile new file mode 100644 index 0000000..eccf955 --- /dev/null +++ b/makefile @@ -0,0 +1,117 @@ +MOTOR_CONTROL_SDK_PATH?=$(abspath .) +include imports.mak + +# Default device +DEVICE ?= am64x + +# debug, release +PROFILE?=release + +# GP, HS +DEVICE_TYPE?=GP + +ifeq ($(DEVICE),$(filter $(DEVICE), am64x)) + SYSCFG_DEVICE = AM64x_beta + # default syscfg CPU to use, + # options on am64x are r5fss0-0, r5fss0-1, r5fss1-0, r5fss1-1, m4fss0-0 + SYSCFG_CPU = r5fss0-0 +endif +ifeq ($(DEVICE),$(filter $(DEVICE), am243x)) + SYSCFG_DEVICE = AM243x_ALV_beta + # default syscfg CPU to use, + # options on am64x are r5fss0-0, r5fss0-1, r5fss1-0, r5fss1-1, m4fss0-0 + SYSCFG_CPU = r5fss0-0 +endif +ifeq ($(DEVICE),$(filter $(DEVICE), am263x)) + SYSCFG_DEVICE = AM263x_beta + # default syscfg CPU to use, + # options on am263x are r5fss0-0, r5fss0-1, r5fss1-0, r5fss1-1 + SYSCFG_CPU = r5fss0-0 +endif + +all: + $(MAKE) -C . -f makefile.$(DEVICE) all PROFILE=$(PROFILE) + +clean: + $(MAKE) -C . -f makefile.$(DEVICE) clean PROFILE=$(PROFILE) + +scrub: + $(MAKE) -C . -f makefile.$(DEVICE) scrub PROFILE=$(PROFILE) + +libs: + $(MAKE) -C . -f makefile.$(DEVICE) libs PROFILE=$(PROFILE) DEVICE_TYPE=$(DEVICE_TYPE) + +libs-clean: + $(MAKE) -C . -f makefile.$(DEVICE) libs-clean PROFILE=$(PROFILE) + +libs-scrub: + $(MAKE) -C . -f makefile.$(DEVICE) libs-scrub PROFILE=$(PROFILE) + +examples: + $(MAKE) -C . -f makefile.$(DEVICE) examples PROFILE=$(PROFILE) + +examples-clean: + $(MAKE) -C . -f makefile.$(DEVICE) examples-clean PROFILE=$(PROFILE) + +examples-scrub: + $(MAKE) -C . -f makefile.$(DEVICE) examples-scrub PROFILE=$(PROFILE) + +help: + $(MAKE) -C . -f makefile.$(DEVICE) -s help PROFILE=$(PROFILE) + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device $(SYSCFG_DEVICE) --context $(SYSCFG_CPU) + +devconfig: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.json --device $(SYSCFG_DEVICE) --context $(SYSCFG_CPU) --output devconfig/ $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.syscfg + +.PHONY: all clean scrub +.PHONY: libs libs-clean libs-scrub +.PHONY: examples examples-clean examples-scrub +.PHONY: help +.PHONY: syscfg-gui +.PHONY: devconfig + + +################ Internal make targets - not to be used by customers ################ +NODE=node + +GEN_BUILDFILES_TARGET?=development +INSTRUMENTATION_MODE?=disable + +DOC_COMBO = r5f.ti-arm-clang +# default combo for doc generation +ifeq ($(DEVICE),$(filter $(DEVICE), am62x)) + DOC_COMBO = m4f.ti-arm-clang +endif + +projectspec-help: + $(MAKE) -C . -f makefile_projectspec.$(DEVICE) -s help PROFILE=$(PROFILE) + +docs: + $(MAKE) -C docs_src/docs/api_guide all DEVICE=$(DEVICE) DOC_COMBO=$(DOC_COMBO) + +docs-clean: + $(MAKE) -C docs_src/docs/api_guide clean DEVICE=$(DEVICE) DOC_COMBO=$(DOC_COMBO) + +gen-buildfiles: + $(NODE) ./.project/project.js --device $(DEVICE) --target $(GEN_BUILDFILES_TARGET) --instrumentation $(INSTRUMENTATION_MODE) + +gen-buildfiles-clean: + $(NODE) ./.project/project.js --device $(DEVICE) --target clean + +syscfg-tests: +ifeq ($(DEVICE),$(filter $(DEVICE), am64x)) + -$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/tests/sanityTests.js -s $(SYSCFG_SDKPRODUCT) -d $(SYSCFG_DEVICE) -c a53ss0-0 +endif +ifeq ($(DEVICE),$(filter $(DEVICE), am64x am243x am62x)) + -$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/tests/sanityTests.js -s $(SYSCFG_SDKPRODUCT) -d $(SYSCFG_DEVICE) -c m4fss0-0 +endif + -$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/tests/sanityTests.js -s $(SYSCFG_SDKPRODUCT) -d $(SYSCFG_DEVICE) -c r5fss0-0 +ifeq ($(DEVICE),$(filter $(DEVICE), am273x awr294x)) + -$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/tests/sanityTests.js -s $(SYSCFG_SDKPRODUCT) -d $(SYSCFG_DEVICE) -c c66ss0 +endif + +.PHONY: projectspec-help docs docs-clean +.PHONY: gen-buildfiles gen-buildfiles-clean +.PHONY: syscfg-tests diff --git a/makefile.am243x b/makefile.am243x new file mode 100644 index 0000000..3c39a80 --- /dev/null +++ b/makefile.am243x @@ -0,0 +1,531 @@ +# +# Auto generated makefile +# + +all: + $(MAKE) -f makefile.am243x libs + $(MAKE) -f makefile.am243x examples + +clean: libs-clean examples-clean +scrub: libs-scrub examples-scrub + +help: + @echo Notes, + @echo - Use -j to invoke parallel builds + @echo - Use PROFILE=debug or PROFILE=release [default] to build in debug or release profile + @echo . + @echo Overall build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.am243x help + @echo . + @echo $(MAKE) -s -f makefile.am243x all + @echo $(MAKE) -s -f makefile.am243x clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.am243x scrub # delete's all tmp files and folders for all profiles + @echo . + @echo $(MAKE) -s -f makefile.am243x libs + @echo $(MAKE) -s -f makefile.am243x libs-clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.am243x libs-scrub # delete's all tmp files and folders for all profiles + @echo . + @echo $(MAKE) -s -f makefile.am243x examples + @echo $(MAKE) -s -f makefile.am243x examples-clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.am243x examples-scrub # delete's all tmp files and folders for all profiles + @echo . + @echo Library build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.am243x motorcontrol_sdfm_r5f.ti-arm-clang + @echo $(MAKE) -s -f makefile.am243x motorcontrol_endat_r5f.ti-arm-clang + @echo $(MAKE) -s -f makefile.am243x motorcontrol_hdsl_r5f.ti-arm-clang + @echo $(MAKE) -s -f makefile.am243x motorcontrol_tamagawa_r5f.ti-arm-clang + @echo . + @echo Library clean targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.am243x motorcontrol_sdfm_r5f.ti-arm-clang_clean + @echo $(MAKE) -s -f makefile.am243x motorcontrol_endat_r5f.ti-arm-clang_clean + @echo $(MAKE) -s -f makefile.am243x motorcontrol_hdsl_r5f.ti-arm-clang_clean + @echo $(MAKE) -s -f makefile.am243x motorcontrol_tamagawa_r5f.ti-arm-clang_clean + @echo . + @echo Example build targets, + @echo ====================== + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo . + @echo System Example build targets, + @echo ============================= + @echo . + +# Various Component Targets +BUILD_COMBO_motorcontrol_sdfm = motorcontrol_sdfm_r5f.ti-arm-clang +BUILD_COMBO_motorcontrol_endat = motorcontrol_endat_r5f.ti-arm-clang +BUILD_COMBO_motorcontrol_hdsl = motorcontrol_hdsl_r5f.ti-arm-clang +BUILD_COMBO_motorcontrol_tamagawa = motorcontrol_tamagawa_r5f.ti-arm-clang + +# Combine all Components +BUILD_COMBO_ALL = $(BUILD_COMBO_motorcontrol_sdfm) $(BUILD_COMBO_motorcontrol_endat) $(BUILD_COMBO_motorcontrol_hdsl) $(BUILD_COMBO_motorcontrol_tamagawa) + +# Combine all Pre-built Components +BUILD_COMBO_PREBUILT_ALL = + +# Combine all Private Components +BUILD_COMBO_PRIVATE_ALL = + +libs: $(BUILD_COMBO_ALL) + +libs-prebuilt: $(BUILD_COMBO_PREBUILT_ALL) + +libs-private: $(BUILD_COMBO_PRIVATE_ALL) + +$(BUILD_COMBO_motorcontrol_sdfm): + $(MAKE) -C source/motor_control/current_sense/sdfm -f makefile.am243x.$(subst motorcontrol_sdfm_,,$@) all + +$(BUILD_COMBO_motorcontrol_endat): + $(MAKE) -C source/motor_control/position_sense/endat -f makefile.am243x.$(subst motorcontrol_endat_,,$@) all + +$(BUILD_COMBO_motorcontrol_hdsl): + $(MAKE) -C source/motor_control/position_sense/hdsl -f makefile.am243x.$(subst motorcontrol_hdsl_,,$@) all + +$(BUILD_COMBO_motorcontrol_tamagawa): + $(MAKE) -C source/motor_control/position_sense/tamagawa -f makefile.am243x.$(subst motorcontrol_tamagawa_,,$@) all + + +# Various Component Clean Targets +BUILD_COMBO_CLEAN_motorcontrol_sdfm = motorcontrol_sdfm_r5f.ti-arm-clang_clean +BUILD_COMBO_CLEAN_motorcontrol_endat = motorcontrol_endat_r5f.ti-arm-clang_clean +BUILD_COMBO_CLEAN_motorcontrol_hdsl = motorcontrol_hdsl_r5f.ti-arm-clang_clean +BUILD_COMBO_CLEAN_motorcontrol_tamagawa = motorcontrol_tamagawa_r5f.ti-arm-clang_clean + +# Combine all Components Clean +BUILD_COMBO_CLEAN_ALL = $(BUILD_COMBO_CLEAN_motorcontrol_sdfm) $(BUILD_COMBO_CLEAN_motorcontrol_endat) $(BUILD_COMBO_CLEAN_motorcontrol_hdsl) $(BUILD_COMBO_CLEAN_motorcontrol_tamagawa) + +# Combine all Pre-built Components Clean +BUILD_COMBO_PREBUILT_CLEAN_ALL = + +libs-clean: $(BUILD_COMBO_CLEAN_ALL) + +libs-prebuilt-clean: $(BUILD_COMBO_PREBUILT_CLEAN_ALL) + +$(BUILD_COMBO_CLEAN_motorcontrol_sdfm): + $(MAKE) -C source/motor_control/current_sense/sdfm -f makefile.am243x.$(subst motorcontrol_sdfm_,,$(subst _clean,,$@)) clean + +$(BUILD_COMBO_CLEAN_motorcontrol_endat): + $(MAKE) -C source/motor_control/position_sense/endat -f makefile.am243x.$(subst motorcontrol_endat_,,$(subst _clean,,$@)) clean + +$(BUILD_COMBO_CLEAN_motorcontrol_hdsl): + $(MAKE) -C source/motor_control/position_sense/hdsl -f makefile.am243x.$(subst motorcontrol_hdsl_,,$(subst _clean,,$@)) clean + +$(BUILD_COMBO_CLEAN_motorcontrol_tamagawa): + $(MAKE) -C source/motor_control/position_sense/tamagawa -f makefile.am243x.$(subst motorcontrol_tamagawa_,,$(subst _clean,,$@)) clean + + +# Various Component Scrub Targets +BUILD_COMBO_SCRUB_motorcontrol_sdfm = motorcontrol_sdfm_r5f.ti-arm-clang_scrub_scrub +BUILD_COMBO_SCRUB_motorcontrol_endat = motorcontrol_endat_r5f.ti-arm-clang_scrub_scrub +BUILD_COMBO_SCRUB_motorcontrol_hdsl = motorcontrol_hdsl_r5f.ti-arm-clang_scrub_scrub +BUILD_COMBO_SCRUB_motorcontrol_tamagawa = motorcontrol_tamagawa_r5f.ti-arm-clang_scrub_scrub + +# Combine all Components Scrub Targets +BUILD_COMBO_SCRUB_ALL = $(BUILD_COMBO_SCRUB_motorcontrol_sdfm) $(BUILD_COMBO_SCRUB_motorcontrol_endat) $(BUILD_COMBO_SCRUB_motorcontrol_hdsl) $(BUILD_COMBO_SCRUB_motorcontrol_tamagawa) + +# Combine all Pre-built Components Scrub Targets +BUILD_COMBO_PREBUILT_SCRUB_ALL = + +libs-scrub: $(BUILD_COMBO_SCRUB_ALL) + +libs-prebuilt-scrub: $(BUILD_COMBO_PREBUILT_SCRUB_ALL) + +$(BUILD_COMBO_SCRUB_motorcontrol_sdfm): + $(MAKE) -C source/motor_control/current_sense/sdfm -f makefile.am243x.$(subst motorcontrol_sdfm_,,$(subst _scrub,,$@)) scrub + +$(BUILD_COMBO_SCRUB_motorcontrol_endat): + $(MAKE) -C source/motor_control/position_sense/endat -f makefile.am243x.$(subst motorcontrol_endat_,,$(subst _scrub,,$@)) scrub + +$(BUILD_COMBO_SCRUB_motorcontrol_hdsl): + $(MAKE) -C source/motor_control/position_sense/hdsl -f makefile.am243x.$(subst motorcontrol_hdsl_,,$(subst _scrub,,$@)) scrub + +$(BUILD_COMBO_SCRUB_motorcontrol_tamagawa): + $(MAKE) -C source/motor_control/position_sense/tamagawa -f makefile.am243x.$(subst motorcontrol_tamagawa_,,$(subst _scrub,,$@)) scrub + + +BUILD_COMBO_EXAMPLE_ALL = +# Various Example Targets +BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang +# Various System Example Targets + +BUILD_COMBO_EXAMPLE_PRIVATE_ALL = +# Various Private Example Targets +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt +# Various Private System Example Targets + +examples: $(BUILD_COMBO_EXAMPLE_ALL) + +examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) + + endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all + + endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all + + hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all + + icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + +BUILD_COMBO_EXAMPLE_CLEAN_ALL = +# Various Example Clean Targets +BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +# Various System Example Clean Targets + +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL = +# Various Private Example Targets +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean +# Various Private System Example Targets + +examples-clean: $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) + +examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) + + endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + +BUILD_COMBO_EXAMPLE_SCRUB_ALL = +# Various Example Scrub Targets +BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +# Various System Example Scrub Targets + +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL = +# Various Private Example Targets +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_scrub +# Various Private System Example Targets + +examples-scrub: $(BUILD_COMBO_EXAMPLE_SCRUB_ALL) + +examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) + + endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + +.PHONY: all clean scrub help +.PHONY: libs libs-clean libs-scrub +.PHONY: libs-private +.PHONY: libs-prebuilt libs-prebuilt-clean libs-prebuilt-scrub +.PHONY: examples examples-clean examples-scrub +.PHONY: examples-private examples-private-clean examples-private-scrub +.PHONY: $(BUILD_COMBO_ALL) $(BUILD_COMBO_CLEAN_ALL) $(BUILD_COMBO_SCRUB_ALL) +.PHONY: $(BUILD_COMBO_EXAMPLE_ALL) $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_SCRUB_ALL) +.PHONY: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) diff --git a/makefile.am263x b/makefile.am263x new file mode 100644 index 0000000..cb7772e --- /dev/null +++ b/makefile.am263x @@ -0,0 +1,164 @@ +# +# Auto generated makefile +# + +all: + $(MAKE) -f makefile.am263x libs + $(MAKE) -f makefile.am263x examples + +clean: libs-clean examples-clean +scrub: libs-scrub examples-scrub + +help: + @echo Notes, + @echo - Use -j to invoke parallel builds + @echo - Use PROFILE=debug or PROFILE=release [default] to build in debug or release profile + @echo . + @echo Overall build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.am263x help + @echo . + @echo $(MAKE) -s -f makefile.am263x all + @echo $(MAKE) -s -f makefile.am263x clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.am263x scrub # delete's all tmp files and folders for all profiles + @echo . + @echo $(MAKE) -s -f makefile.am263x libs + @echo $(MAKE) -s -f makefile.am263x libs-clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.am263x libs-scrub # delete's all tmp files and folders for all profiles + @echo . + @echo $(MAKE) -s -f makefile.am263x examples + @echo $(MAKE) -s -f makefile.am263x examples-clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.am263x examples-scrub # delete's all tmp files and folders for all profiles + @echo . + @echo Library build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.am263x motorcontrol_tamagawa_over_soc_uart_r5f.ti-arm-clang + @echo . + @echo Library clean targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.am263x motorcontrol_tamagawa_over_soc_uart_r5f.ti-arm-clang_clean + @echo . + @echo Example build targets, + @echo ====================== + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo . + @echo System Example build targets, + @echo ============================= + @echo . + +# Various Component Targets +BUILD_COMBO_motorcontrol_tamagawa_over_soc_uart = motorcontrol_tamagawa_over_soc_uart_r5f.ti-arm-clang + +# Combine all Components +BUILD_COMBO_ALL = $(BUILD_COMBO_motorcontrol_tamagawa_over_soc_uart) + +# Combine all Pre-built Components +BUILD_COMBO_PREBUILT_ALL = + +# Combine all Private Components +BUILD_COMBO_PRIVATE_ALL = + +libs: $(BUILD_COMBO_ALL) + +libs-prebuilt: $(BUILD_COMBO_PREBUILT_ALL) + +libs-private: $(BUILD_COMBO_PRIVATE_ALL) + +$(BUILD_COMBO_motorcontrol_tamagawa_over_soc_uart): + $(MAKE) -C source/motor_control/position_sense/tamagawa_over_soc_uart -f makefile.am263x.$(subst motorcontrol_tamagawa_over_soc_uart_,,$@) all + + +# Various Component Clean Targets +BUILD_COMBO_CLEAN_motorcontrol_tamagawa_over_soc_uart = motorcontrol_tamagawa_over_soc_uart_r5f.ti-arm-clang_clean + +# Combine all Components Clean +BUILD_COMBO_CLEAN_ALL = $(BUILD_COMBO_CLEAN_motorcontrol_tamagawa_over_soc_uart) + +# Combine all Pre-built Components Clean +BUILD_COMBO_PREBUILT_CLEAN_ALL = + +libs-clean: $(BUILD_COMBO_CLEAN_ALL) + +libs-prebuilt-clean: $(BUILD_COMBO_PREBUILT_CLEAN_ALL) + +$(BUILD_COMBO_CLEAN_motorcontrol_tamagawa_over_soc_uart): + $(MAKE) -C source/motor_control/position_sense/tamagawa_over_soc_uart -f makefile.am263x.$(subst motorcontrol_tamagawa_over_soc_uart_,,$(subst _clean,,$@)) clean + + +# Various Component Scrub Targets +BUILD_COMBO_SCRUB_motorcontrol_tamagawa_over_soc_uart = motorcontrol_tamagawa_over_soc_uart_r5f.ti-arm-clang_scrub_scrub + +# Combine all Components Scrub Targets +BUILD_COMBO_SCRUB_ALL = $(BUILD_COMBO_SCRUB_motorcontrol_tamagawa_over_soc_uart) + +# Combine all Pre-built Components Scrub Targets +BUILD_COMBO_PREBUILT_SCRUB_ALL = + +libs-scrub: $(BUILD_COMBO_SCRUB_ALL) + +libs-prebuilt-scrub: $(BUILD_COMBO_PREBUILT_SCRUB_ALL) + +$(BUILD_COMBO_SCRUB_motorcontrol_tamagawa_over_soc_uart): + $(MAKE) -C source/motor_control/position_sense/tamagawa_over_soc_uart -f makefile.am263x.$(subst motorcontrol_tamagawa_over_soc_uart_,,$(subst _scrub,,$@)) scrub + + +BUILD_COMBO_EXAMPLE_ALL = +# Various Example Targets +BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang +# Various System Example Targets + +BUILD_COMBO_EXAMPLE_PRIVATE_ALL = +# Various Private Example Targets +# Various Private System Example Targets + +examples: $(BUILD_COMBO_EXAMPLE_ALL) + +examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) + + tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all + + +BUILD_COMBO_EXAMPLE_CLEAN_ALL = +# Various Example Clean Targets +BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_clean +# Various System Example Clean Targets + +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL = +# Various Private Example Targets +# Various Private System Example Targets + +examples-clean: $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) + +examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) + + tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + +BUILD_COMBO_EXAMPLE_SCRUB_ALL = +# Various Example Scrub Targets +BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_scrub +# Various System Example Scrub Targets + +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL = +# Various Private Example Targets +# Various Private System Example Targets + +examples-scrub: $(BUILD_COMBO_EXAMPLE_SCRUB_ALL) + +examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) + + tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + +.PHONY: all clean scrub help +.PHONY: libs libs-clean libs-scrub +.PHONY: libs-private +.PHONY: libs-prebuilt libs-prebuilt-clean libs-prebuilt-scrub +.PHONY: examples examples-clean examples-scrub +.PHONY: examples-private examples-private-clean examples-private-scrub +.PHONY: $(BUILD_COMBO_ALL) $(BUILD_COMBO_CLEAN_ALL) $(BUILD_COMBO_SCRUB_ALL) +.PHONY: $(BUILD_COMBO_EXAMPLE_ALL) $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_SCRUB_ALL) +.PHONY: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) diff --git a/makefile.am64x b/makefile.am64x new file mode 100644 index 0000000..0db0114 --- /dev/null +++ b/makefile.am64x @@ -0,0 +1,479 @@ +# +# Auto generated makefile +# + +all: + $(MAKE) -f makefile.am64x libs + $(MAKE) -f makefile.am64x examples + +clean: libs-clean examples-clean +scrub: libs-scrub examples-scrub + +help: + @echo Notes, + @echo - Use -j to invoke parallel builds + @echo - Use PROFILE=debug or PROFILE=release [default] to build in debug or release profile + @echo . + @echo Overall build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.am64x help + @echo . + @echo $(MAKE) -s -f makefile.am64x all + @echo $(MAKE) -s -f makefile.am64x clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.am64x scrub # delete's all tmp files and folders for all profiles + @echo . + @echo $(MAKE) -s -f makefile.am64x libs + @echo $(MAKE) -s -f makefile.am64x libs-clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.am64x libs-scrub # delete's all tmp files and folders for all profiles + @echo . + @echo $(MAKE) -s -f makefile.am64x examples + @echo $(MAKE) -s -f makefile.am64x examples-clean # delete's tmp files for current profile + @echo $(MAKE) -s -f makefile.am64x examples-scrub # delete's all tmp files and folders for all profiles + @echo . + @echo Library build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.am64x motorcontrol_sdfm_r5f.ti-arm-clang + @echo $(MAKE) -s -f makefile.am64x motorcontrol_endat_r5f.ti-arm-clang + @echo $(MAKE) -s -f makefile.am64x motorcontrol_hdsl_r5f.ti-arm-clang + @echo $(MAKE) -s -f makefile.am64x motorcontrol_tamagawa_r5f.ti-arm-clang + @echo . + @echo Library clean targets, + @echo ====================== + @echo $(MAKE) -s -f makefile.am64x motorcontrol_sdfm_r5f.ti-arm-clang_clean + @echo $(MAKE) -s -f makefile.am64x motorcontrol_endat_r5f.ti-arm-clang_clean + @echo $(MAKE) -s -f makefile.am64x motorcontrol_hdsl_r5f.ti-arm-clang_clean + @echo $(MAKE) -s -f makefile.am64x motorcontrol_tamagawa_r5f.ti-arm-clang_clean + @echo . + @echo Example build targets, + @echo ====================== + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo . + @echo System Example build targets, + @echo ============================= + @echo . + +# Various Component Targets +BUILD_COMBO_motorcontrol_sdfm = motorcontrol_sdfm_r5f.ti-arm-clang +BUILD_COMBO_motorcontrol_endat = motorcontrol_endat_r5f.ti-arm-clang +BUILD_COMBO_motorcontrol_hdsl = motorcontrol_hdsl_r5f.ti-arm-clang +BUILD_COMBO_motorcontrol_tamagawa = motorcontrol_tamagawa_r5f.ti-arm-clang + +# Combine all Components +BUILD_COMBO_ALL = $(BUILD_COMBO_motorcontrol_sdfm) $(BUILD_COMBO_motorcontrol_endat) $(BUILD_COMBO_motorcontrol_hdsl) $(BUILD_COMBO_motorcontrol_tamagawa) + +# Combine all Pre-built Components +BUILD_COMBO_PREBUILT_ALL = + +# Combine all Private Components +BUILD_COMBO_PRIVATE_ALL = + +libs: $(BUILD_COMBO_ALL) + +libs-prebuilt: $(BUILD_COMBO_PREBUILT_ALL) + +libs-private: $(BUILD_COMBO_PRIVATE_ALL) + +$(BUILD_COMBO_motorcontrol_sdfm): + $(MAKE) -C source/motor_control/current_sense/sdfm -f makefile.am64x.$(subst motorcontrol_sdfm_,,$@) all + +$(BUILD_COMBO_motorcontrol_endat): + $(MAKE) -C source/motor_control/position_sense/endat -f makefile.am64x.$(subst motorcontrol_endat_,,$@) all + +$(BUILD_COMBO_motorcontrol_hdsl): + $(MAKE) -C source/motor_control/position_sense/hdsl -f makefile.am64x.$(subst motorcontrol_hdsl_,,$@) all + +$(BUILD_COMBO_motorcontrol_tamagawa): + $(MAKE) -C source/motor_control/position_sense/tamagawa -f makefile.am64x.$(subst motorcontrol_tamagawa_,,$@) all + + +# Various Component Clean Targets +BUILD_COMBO_CLEAN_motorcontrol_sdfm = motorcontrol_sdfm_r5f.ti-arm-clang_clean +BUILD_COMBO_CLEAN_motorcontrol_endat = motorcontrol_endat_r5f.ti-arm-clang_clean +BUILD_COMBO_CLEAN_motorcontrol_hdsl = motorcontrol_hdsl_r5f.ti-arm-clang_clean +BUILD_COMBO_CLEAN_motorcontrol_tamagawa = motorcontrol_tamagawa_r5f.ti-arm-clang_clean + +# Combine all Components Clean +BUILD_COMBO_CLEAN_ALL = $(BUILD_COMBO_CLEAN_motorcontrol_sdfm) $(BUILD_COMBO_CLEAN_motorcontrol_endat) $(BUILD_COMBO_CLEAN_motorcontrol_hdsl) $(BUILD_COMBO_CLEAN_motorcontrol_tamagawa) + +# Combine all Pre-built Components Clean +BUILD_COMBO_PREBUILT_CLEAN_ALL = + +libs-clean: $(BUILD_COMBO_CLEAN_ALL) + +libs-prebuilt-clean: $(BUILD_COMBO_PREBUILT_CLEAN_ALL) + +$(BUILD_COMBO_CLEAN_motorcontrol_sdfm): + $(MAKE) -C source/motor_control/current_sense/sdfm -f makefile.am64x.$(subst motorcontrol_sdfm_,,$(subst _clean,,$@)) clean + +$(BUILD_COMBO_CLEAN_motorcontrol_endat): + $(MAKE) -C source/motor_control/position_sense/endat -f makefile.am64x.$(subst motorcontrol_endat_,,$(subst _clean,,$@)) clean + +$(BUILD_COMBO_CLEAN_motorcontrol_hdsl): + $(MAKE) -C source/motor_control/position_sense/hdsl -f makefile.am64x.$(subst motorcontrol_hdsl_,,$(subst _clean,,$@)) clean + +$(BUILD_COMBO_CLEAN_motorcontrol_tamagawa): + $(MAKE) -C source/motor_control/position_sense/tamagawa -f makefile.am64x.$(subst motorcontrol_tamagawa_,,$(subst _clean,,$@)) clean + + +# Various Component Scrub Targets +BUILD_COMBO_SCRUB_motorcontrol_sdfm = motorcontrol_sdfm_r5f.ti-arm-clang_scrub_scrub +BUILD_COMBO_SCRUB_motorcontrol_endat = motorcontrol_endat_r5f.ti-arm-clang_scrub_scrub +BUILD_COMBO_SCRUB_motorcontrol_hdsl = motorcontrol_hdsl_r5f.ti-arm-clang_scrub_scrub +BUILD_COMBO_SCRUB_motorcontrol_tamagawa = motorcontrol_tamagawa_r5f.ti-arm-clang_scrub_scrub + +# Combine all Components Scrub Targets +BUILD_COMBO_SCRUB_ALL = $(BUILD_COMBO_SCRUB_motorcontrol_sdfm) $(BUILD_COMBO_SCRUB_motorcontrol_endat) $(BUILD_COMBO_SCRUB_motorcontrol_hdsl) $(BUILD_COMBO_SCRUB_motorcontrol_tamagawa) + +# Combine all Pre-built Components Scrub Targets +BUILD_COMBO_PREBUILT_SCRUB_ALL = + +libs-scrub: $(BUILD_COMBO_SCRUB_ALL) + +libs-prebuilt-scrub: $(BUILD_COMBO_PREBUILT_SCRUB_ALL) + +$(BUILD_COMBO_SCRUB_motorcontrol_sdfm): + $(MAKE) -C source/motor_control/current_sense/sdfm -f makefile.am64x.$(subst motorcontrol_sdfm_,,$(subst _scrub,,$@)) scrub + +$(BUILD_COMBO_SCRUB_motorcontrol_endat): + $(MAKE) -C source/motor_control/position_sense/endat -f makefile.am64x.$(subst motorcontrol_endat_,,$(subst _scrub,,$@)) scrub + +$(BUILD_COMBO_SCRUB_motorcontrol_hdsl): + $(MAKE) -C source/motor_control/position_sense/hdsl -f makefile.am64x.$(subst motorcontrol_hdsl_,,$(subst _scrub,,$@)) scrub + +$(BUILD_COMBO_SCRUB_motorcontrol_tamagawa): + $(MAKE) -C source/motor_control/position_sense/tamagawa -f makefile.am64x.$(subst motorcontrol_tamagawa_,,$(subst _scrub,,$@)) scrub + + +BUILD_COMBO_EXAMPLE_ALL = +# Various Example Targets +BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang +BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang +# Various System Example Targets + +BUILD_COMBO_EXAMPLE_PRIVATE_ALL = +# Various Private Example Targets +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +# Various Private System Example Targets + +examples: $(BUILD_COMBO_EXAMPLE_ALL) + +examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) + + endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang: + $(MAKE) -C examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all + + sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + +BUILD_COMBO_EXAMPLE_CLEAN_ALL = +# Various Example Clean Targets +BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +# Various System Example Clean Targets + +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL = +# Various Private Example Targets +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +# Various Private System Example Targets + +examples-clean: $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) + +examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) + + endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean + + sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + +BUILD_COMBO_EXAMPLE_SCRUB_ALL = +# Various Example Scrub Targets +BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub +# Various System Example Scrub Targets + +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL = +# Various Private Example Targets +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +# Various Private System Example Targets + +examples-scrub: $(BUILD_COMBO_EXAMPLE_SCRUB_ALL) + +examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) + + endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub: + $(MAKE) -C examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub + + sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + +.PHONY: all clean scrub help +.PHONY: libs libs-clean libs-scrub +.PHONY: libs-private +.PHONY: libs-prebuilt libs-prebuilt-clean libs-prebuilt-scrub +.PHONY: examples examples-clean examples-scrub +.PHONY: examples-private examples-private-clean examples-private-scrub +.PHONY: $(BUILD_COMBO_ALL) $(BUILD_COMBO_CLEAN_ALL) $(BUILD_COMBO_SCRUB_ALL) +.PHONY: $(BUILD_COMBO_EXAMPLE_ALL) $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_SCRUB_ALL) +.PHONY: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) diff --git a/makefile_projectspec.am243x b/makefile_projectspec.am243x new file mode 100644 index 0000000..8082cde --- /dev/null +++ b/makefile_projectspec.am243x @@ -0,0 +1,422 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath .) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL = +# Various Example Projectspec Build Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build +# Various System Example Projectspec Build Targets + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL = +# Various Private Example Projectspec Build Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_build +# Various Private System Example Projectspec Build Targets + +all: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL) + +all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL) + + endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL = +# Various Example Projectspec Clean Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean +# Various System Example Projectspec Clean Targets + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL = +# Various Private Example Projectspec Clean Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean +# Various Private System Example Projectspec Clean Targets + +clean: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL) + +clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL) + + endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL = +# Various Example Projectspec Export Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export +# Various System Example Projectspec Export Targets + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL = +# Various Private Example Projectspec Export Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_export +# Various Private System Example Projectspec Export Targets + +export: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL) + +export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL) + + endat_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + endat_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + endat_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + +# Import extra components into CCS workspace before creating a project +# Setup dependency separately so that it runs if one or all projects are built via the makefile +$(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL) $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL): import_extra_components + +# Import extra components based on the configured makefile variables. +# Same CCS workspace used by the examples is used here. +import_extra_components: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.common.core.initialize -ccs.productDiscoveryPath $(COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR) -ccs.productDiscoveryPath $(COM_TI_MCU_PLUS_SDK_AMXXX_INSTALL_DIR) + +help: + @echo Notes, + @echo - Use -j to invoke parallel builds + @echo - Use PROFILE=Debug or PROFILE=Release [default] to build in Debug or Release profile + @echo . + @echo Overall build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile_projectspec.am243x help + @echo . + @echo $(MAKE) -s -f makefile_projectspec.am243x [export all clean] + @echo . + @echo export = export projectspec to CCS project in the folder ./ccs_projects/, + @echo export MUST be called once before 'all' or 'clean' + @echo all = build the previously exported projectspecs + @echo clean = clean the previously exported projectspecs + @echo . + @echo Example ProjectSpec build targets, + @echo ================================== + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo . + @echo System Example ProjectSpec build targets, + @echo ========================================= + @echo . + +.PHONY: all all-private +.PHONY: clean clean-private +.PHONY: help diff --git a/makefile_projectspec.am263x b/makefile_projectspec.am263x new file mode 100644 index 0000000..14e72e9 --- /dev/null +++ b/makefile_projectspec.am263x @@ -0,0 +1,85 @@ +# +# Auto generated makefile +# + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL = +# Various Example Projectspec Build Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_build +# Various System Example Projectspec Build Targets + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL = +# Various Private Example Projectspec Build Targets +# Various Private System Example Projectspec Build Targets + +all: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL) + +all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL) + + tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL = +# Various Example Projectspec Clean Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_clean +# Various System Example Projectspec Clean Targets + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL = +# Various Private Example Projectspec Clean Targets +# Various Private System Example Projectspec Clean Targets + +clean: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL) + +clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL) + + tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL = +# Various Example Projectspec Export Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_export +# Various System Example Projectspec Export Targets + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL = +# Various Private Example Projectspec Export Targets +# Various Private System Example Projectspec Export Targets + +export: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL) + +export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL) + + tamagawa_diagnostic_soc_uart_am263x-lp_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + + +help: + @echo Notes, + @echo - Use -j to invoke parallel builds + @echo - Use PROFILE=Debug or PROFILE=Release [default] to build in Debug or Release profile + @echo . + @echo Overall build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile_projectspec.am263x help + @echo . + @echo $(MAKE) -s -f makefile_projectspec.am263x [export all clean] + @echo . + @echo export = export projectspec to CCS project in the folder ./ccs_projects/, + @echo export MUST be called once before 'all' or 'clean' + @echo all = build the previously exported projectspecs + @echo clean = clean the previously exported projectspecs + @echo . + @echo Example ProjectSpec build targets, + @echo ================================== + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic_over_soc_uart/am263x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo . + @echo System Example ProjectSpec build targets, + @echo ========================================= + @echo . + +.PHONY: all all-private +.PHONY: clean clean-private +.PHONY: help diff --git a/makefile_projectspec.am64x b/makefile_projectspec.am64x new file mode 100644 index 0000000..e20b324 --- /dev/null +++ b/makefile_projectspec.am64x @@ -0,0 +1,370 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath .) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL = +# Various Example Projectspec Build Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build +# Various System Example Projectspec Build Targets + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL = +# Various Private Example Projectspec Build Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +# Various Private System Example Projectspec Build Targets + +all: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL) + +all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL) + + endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build: + $(MAKE) -C examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all + + sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL = +# Various Example Projectspec Clean Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean +# Various System Example Projectspec Clean Targets + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL = +# Various Private Example Projectspec Clean Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +# Various Private System Example Projectspec Clean Targets + +clean: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL) + +clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL) + + endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean: + $(MAKE) -C examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean + + sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL = +# Various Example Projectspec Export Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export +# Various System Example Projectspec Export Targets + +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL = +# Various Private Example Projectspec Export Targets +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +# Various Private System Example Projectspec Export Targets + +export: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL) + +export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL) + + endat_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + endat_diagnostic_multi_channel_load_share_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export: + $(MAKE) -C examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export + + sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + +# Import extra components into CCS workspace before creating a project +# Setup dependency separately so that it runs if one or all projects are built via the makefile +$(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL) $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL): import_extra_components + +# Import extra components based on the configured makefile variables. +# Same CCS workspace used by the examples is used here. +import_extra_components: + $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.common.core.initialize -ccs.productDiscoveryPath $(COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR) -ccs.productDiscoveryPath $(COM_TI_MCU_PLUS_SDK_AMXXX_INSTALL_DIR) + +help: + @echo Notes, + @echo - Use -j to invoke parallel builds + @echo - Use PROFILE=Debug or PROFILE=Release [default] to build in Debug or Release profile + @echo . + @echo Overall build targets, + @echo ====================== + @echo $(MAKE) -s -f makefile_projectspec.am64x help + @echo . + @echo $(MAKE) -s -f makefile_projectspec.am64x [export all clean] + @echo . + @echo export = export projectspec to CCS project in the folder ./ccs_projects/, + @echo export MUST be called once before 'all' or 'clean' + @echo all = build the previously exported projectspecs + @echo clean = clean the previously exported projectspecs + @echo . + @echo Example ProjectSpec build targets, + @echo ================================== + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C examples/motor_control/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo . + @echo System Example ProjectSpec build targets, + @echo ========================================= + @echo . + +.PHONY: all all-private +.PHONY: clean clean-private +.PHONY: help diff --git a/package-lock.json b/package-lock.json new file mode 100644 index 0000000..8e9c750 --- /dev/null +++ b/package-lock.json @@ -0,0 +1,180 @@ +{ + "name": "MOTOR_CONTROL_SDK", + "version": "09.00.00", + "lockfileVersion": 3, + "requires": true, + "packages": { + "": { + "name": "MOTOR_CONTROL_SDK", + "version": "09.00.00", + "license": "BSD-2-Clause", + "dependencies": { + "lodash": "^4.17.21", + "yargs": "^16.2.0" + } + }, + "node_modules/ansi-regex": { + "version": "5.0.1", + "resolved": "https://registry.npmjs.org/ansi-regex/-/ansi-regex-5.0.1.tgz", + "integrity": "sha512-quJQXlTSUGL2LH9SUXo8VwsY4soanhgo6LNSm84E1LBcE8s3O0wpdiRzyR9z/ZZJMlMWv37qOOb9pdJlMUEKFQ==", + "engines": { + "node": ">=8" + } + }, + "node_modules/ansi-styles": { + "version": "4.3.0", + "resolved": "https://registry.npmjs.org/ansi-styles/-/ansi-styles-4.3.0.tgz", + "integrity": "sha512-zbB9rCJAT1rbjiVDb2hqKFHNYLxgtk8NURxZ3IZwD3F6NtxbXZQCnnSi1Lkx+IDohdPlFp222wVALIheZJQSEg==", + "dependencies": { + "color-convert": "^2.0.1" + }, + "engines": { + "node": ">=8" + }, + "funding": { + "url": "https://github.com/chalk/ansi-styles?sponsor=1" + } + }, + "node_modules/cliui": { + "version": "7.0.4", + "resolved": "https://registry.npmjs.org/cliui/-/cliui-7.0.4.tgz", + "integrity": "sha512-OcRE68cOsVMXp1Yvonl/fzkQOyjLSu/8bhPDfQt0e0/Eb283TKP20Fs2MqoPsr9SwA595rRCA+QMzYc9nBP+JQ==", + "dependencies": { + "string-width": "^4.2.0", + "strip-ansi": "^6.0.0", + "wrap-ansi": "^7.0.0" + } + }, + "node_modules/color-convert": { + "version": "2.0.1", + "resolved": "https://registry.npmjs.org/color-convert/-/color-convert-2.0.1.tgz", + "integrity": "sha512-RRECPsj7iu/xb5oKYcsFHSppFNnsj/52OVTRKb4zP5onXwVF3zVmmToNcOfGC+CRDpfK/U584fMg38ZHCaElKQ==", + "dependencies": { + "color-name": "~1.1.4" + }, + "engines": { + "node": ">=7.0.0" + } + }, + "node_modules/color-name": { + "version": "1.1.4", + "resolved": "https://registry.npmjs.org/color-name/-/color-name-1.1.4.tgz", + "integrity": "sha512-dOy+3AuW3a2wNbZHIuMZpTcgjGuLU/uBL/ubcZF9OXbDo8ff4O8yVp5Bf0efS8uEoYo5q4Fx7dY9OgQGXgAsQA==" + }, + "node_modules/emoji-regex": { + "version": "8.0.0", + "resolved": "https://registry.npmjs.org/emoji-regex/-/emoji-regex-8.0.0.tgz", + "integrity": "sha512-MSjYzcWNOA0ewAHpz0MxpYFvwg6yjy1NG3xteoqz644VCo/RPgnr1/GGt+ic3iJTzQ8Eu3TdM14SawnVUmGE6A==" + }, + "node_modules/escalade": { + "version": "3.1.1", + "resolved": "https://registry.npmjs.org/escalade/-/escalade-3.1.1.tgz", + "integrity": "sha512-k0er2gUkLf8O0zKJiAhmkTnJlTvINGv7ygDNPbeIsX/TJjGJZHuh9B2UxbsaEkmlEo9MfhrSzmhIlhRlI2GXnw==", + "engines": { + "node": ">=6" + } + }, + "node_modules/get-caller-file": { + "version": "2.0.5", + "resolved": "https://registry.npmjs.org/get-caller-file/-/get-caller-file-2.0.5.tgz", + "integrity": "sha512-DyFP3BM/3YHTQOCUL/w0OZHR0lpKeGrxotcHWcqNEdnltqFwXVfhEBQ94eIo34AfQpo0rGki4cyIiftY06h2Fg==", + "engines": { + "node": "6.* || 8.* || >= 10.*" + } + }, + "node_modules/is-fullwidth-code-point": { + "version": "3.0.0", + "resolved": "https://registry.npmjs.org/is-fullwidth-code-point/-/is-fullwidth-code-point-3.0.0.tgz", + "integrity": "sha512-zymm5+u+sCsSWyD9qNaejV3DFvhCKclKdizYaJUuHA83RLjb7nSuGnddCHGv0hk+KY7BMAlsWeK4Ueg6EV6XQg==", + "engines": { + "node": ">=8" + } + }, + "node_modules/lodash": { + "version": "4.17.21", + "resolved": "https://registry.npmjs.org/lodash/-/lodash-4.17.21.tgz", + "integrity": "sha512-v2kDEe57lecTulaDIuNTPy3Ry4gLGJ6Z1O3vE1krgXZNrsQ+LFTGHVxVjcXPs17LhbZVGedAJv8XZ1tvj5FvSg==" + }, + "node_modules/require-directory": { + "version": "2.1.1", + "resolved": "https://registry.npmjs.org/require-directory/-/require-directory-2.1.1.tgz", + "integrity": "sha1-jGStX9MNqxyXbiNE/+f3kqam30I=", + "engines": { + "node": ">=0.10.0" + } + }, + "node_modules/string-width": { + "version": "4.2.3", + "resolved": "https://registry.npmjs.org/string-width/-/string-width-4.2.3.tgz", + "integrity": "sha512-wKyQRQpjJ0sIp62ErSZdGsjMJWsap5oRNihHhu6G7JVO/9jIB6UyevL+tXuOqrng8j/cxKTWyWUwvSTriiZz/g==", + "dependencies": { + "emoji-regex": "^8.0.0", + "is-fullwidth-code-point": "^3.0.0", + "strip-ansi": "^6.0.1" + }, + "engines": { + "node": ">=8" + } + }, + "node_modules/strip-ansi": { + "version": "6.0.1", + "resolved": "https://registry.npmjs.org/strip-ansi/-/strip-ansi-6.0.1.tgz", + "integrity": "sha512-Y38VPSHcqkFrCpFnQ9vuSXmquuv5oXOKpGeT6aGrr3o3Gc9AlVa6JBfUSOCnbxGGZF+/0ooI7KrPuUSztUdU5A==", + "dependencies": { + "ansi-regex": "^5.0.1" + }, + "engines": { + "node": ">=8" + } + }, + "node_modules/wrap-ansi": { + "version": "7.0.0", + "resolved": "https://registry.npmjs.org/wrap-ansi/-/wrap-ansi-7.0.0.tgz", + "integrity": "sha512-YVGIj2kamLSTxw6NsZjoBxfSwsn0ycdesmc4p+Q21c5zPuZ1pl+NfxVdxPtdHvmNVOQ6XSYG4AUtyt/Fi7D16Q==", + "dependencies": { + "ansi-styles": "^4.0.0", + "string-width": "^4.1.0", + "strip-ansi": "^6.0.0" + }, + "engines": { + "node": ">=10" + }, + "funding": { + "url": "https://github.com/chalk/wrap-ansi?sponsor=1" + } + }, + "node_modules/y18n": { + "version": "5.0.8", + "resolved": "https://registry.npmjs.org/y18n/-/y18n-5.0.8.tgz", + "integrity": "sha512-0pfFzegeDWJHJIAmTLRP2DwHjdF5s7jo9tuztdQxAhINCdvS+3nGINqPd00AphqJR/0LhANUS6/+7SCb98YOfA==", + "engines": { + "node": ">=10" + } + }, + "node_modules/yargs": { + "version": "16.2.0", + "resolved": "https://registry.npmjs.org/yargs/-/yargs-16.2.0.tgz", + "integrity": "sha512-D1mvvtDG0L5ft/jGWkLpG1+m0eQxOfaBvTNELraWj22wSVUMWxZUvYgJYcKh6jGGIkJFhH4IZPQhR4TKpc8mBw==", + "dependencies": { + "cliui": "^7.0.2", + "escalade": "^3.1.1", + "get-caller-file": "^2.0.5", + "require-directory": "^2.1.1", + "string-width": "^4.2.0", + "y18n": "^5.0.5", + "yargs-parser": "^20.2.2" + }, + "engines": { + "node": ">=10" + } + }, + "node_modules/yargs-parser": { + "version": "20.2.9", + "resolved": "https://registry.npmjs.org/yargs-parser/-/yargs-parser-20.2.9.tgz", + "integrity": "sha512-y11nGElTIV+CT3Zv9t7VKl+Q3hTQoT9a1Qzezhhl6Rp21gJ/IVTW7Z3y9EWXhuUBC2Shnf+DX0antecpAwSP8w==", + "engines": { + "node": ">=10" + } + } + } +} diff --git a/package.json b/package.json new file mode 100644 index 0000000..624eb5e --- /dev/null +++ b/package.json @@ -0,0 +1,23 @@ +{ + "name": "MOTOR_CONTROL_SDK", + "version": "09.00.00", + "description": "MOTOR CONTROL SDK", + "main": "index.js", + "directories": { + "doc": "docs", + "example": "examples" + }, + "scripts": { + "test": "echo \"Error: no test specified\" && exit 1" + }, + "repository": { + "type": "git", + "url": "ssh://git@bitbucket.itg.ti.com/processor-sdk-mcu/sandbox.git" + }, + "author": "TI", + "license": "BSD-2-Clause", + "dependencies": { + "lodash": "^4.17.21", + "yargs": "^16.2.0" + } +} diff --git a/source/.meta/common.syscfg.js b/source/.meta/common.syscfg.js new file mode 100644 index 0000000..db714b8 --- /dev/null +++ b/source/.meta/common.syscfg.js @@ -0,0 +1,358 @@ + +function getSelfSysCfgCoreName() { + if(system.deviceData.core) + return system.deviceData.core.name; + + /* when system.deviceData.core is not defined return a valid core for current SoC */ + switch(getSocName()) { + case "am243x": + return "r5fss0-0"; + default: + case "am64x": + return "r5fss0-0"; + case "am263x": + return "r5fss0-0"; + case "am273x": + return "r5fss0-0"; + case "awr294x": + return "r5fss0-0"; + case "am62x": + return "m4fss0-0"; + } +}; + +function isSciClientSupported() { + switch(getSocName()) { + case "am243x": + return true; + case "am64x": + return true; + case "am62x": + return true; + default: + return false; + } +}; + + +function getNodePath() { + return system.getNodePath() +} + +function getSocName() { + if(system.deviceData.device == "AM64x_beta") + return "am64x"; + if((system.deviceData.device == "AM243x_ALV_beta") || (system.deviceData.device == "AM243x_ALX_beta")) + return "am243x"; + if(system.deviceData.device == "AM263x_beta") + return "am263x"; + if(system.deviceData.device == "AM273x") + return "am273x"; + if((system.deviceData.device == "AWR294X") || (system.deviceData.device == "AWR294XLOP")) + return "awr294x"; + if(system.deviceData.device == "AM62x") + return "am62x"; +}; + +function getDeviceName() { + if(system.deviceData.device == "AM64x_beta") + return "am64x-evm"; + if(system.deviceData.device == "AM243x_ALV_beta") + return "am243x-evm"; + if(system.deviceData.device == "AM243x_ALX_beta") + return "am243x-lp"; + if(system.deviceData.device == "AM263x_beta") + return "am263x-cc"; + if(system.deviceData.device == "AM273x") + return "am273x-evm"; + if(system.deviceData.device == "AWR294X") + return "awr294x-evm"; + if(system.deviceData.device == "AM62x") + return "am62x-sk"; +}; + +function isCName(id) { + if ( (id != null) && (id.match(/^[a-zA-Z_][0-9a-zA-Z_]*$/) != null) ) + { + return true; + } + return false; +} + +function camelSentence(str) { + return (" " + str).toLowerCase().replace(/[^a-zA-Z0-9]+(.)/g, function(match, chr) + { + return chr.toUpperCase(); + }); +} + +function getSysCfgCoreNames() +{ + let core_names = []; + + for( let core of system.deviceData.cores) + { + core_names.push(core.name); + } + return core_names; +} + +function getStaticModuleForCore(moduleName, coreName) +{ + let context = system.contexts[coreName]; + let modules = context ? context.system.modules : {}; + let module = modules[moduleName]; + + if(module && module.$static) + return module.$static; + + return undefined; +} + +function getModuleForCore(moduleName, coreName) +{ + let context = system.contexts[coreName]; + let modules = context ? context.system.modules : {}; + let module = modules[moduleName]; + + return module; +} + + +function makeConfig(staticConfigArr, fieldname, displayName) +{ + let config = {}; + + if(staticConfigArr.length == 0) + return undefined; + + config.name = `${fieldname}`; + config.displayName = `${displayName}`; + config.description = `Select ${displayName}`; + config.default = staticConfigArr[0].name; + config.options = []; + + for (let i = 0; i < staticConfigArr.length; i++) { + let option = {}; + + option.name = staticConfigArr[i].name; + if(staticConfigArr[i].description) + { + option.description = staticConfigArr[i].description; + } + config.options.push(option); + } + + return config; +} + +function checkSameFieldName(instance, fieldname, report) +{ + let moduleInstances = instance.$module.$instances; + + for (let i = 0; i < moduleInstances.length; i++) { + if (instance[fieldname] === moduleInstances[i][fieldname] && + instance !== moduleInstances[i]) { + report.logError(`Same ${fieldname} cannot be selected`, instance, fieldname); + } + } +} + +function checkSameFieldNameOnAllCores(moduleName, instance, fieldname, report) +{ + let coreNames = getSysCfgCoreNames(); + for ( let remoteCoreName of coreNames) + { + let remote_core_instance = getModuleForCore(moduleName, remoteCoreName); + if(remote_core_instance) + { + let moduleInstances = remote_core_instance.$instances; + for (let i = 0; i < moduleInstances.length; i++) { + if (instance[fieldname] === moduleInstances[i][fieldname] && + instance !== moduleInstances[i]) { + report.logError(`Same ${fieldname} cannot be selected`, instance, fieldname); + } + } + } + } +} + +function getUseMcuDomainPeripheralsConfig() +{ + let config = { + name: "useMcuDomainPeripherals", + displayName: "Use MCU Domain Peripherals", + default: false, + } + + if(getSelfSysCfgCoreName().includes("m4f")) { + config.default = true; + config.readOnly = true; + } + + return config; +} + +function isMcuDomainSupported() +{ + switch(getSocName()) { + case "am243x": + return true; + case "am64x": + return true; + case "am62x": + return true; + default: + return false; + } +} + +function findDuplicates(arrayToCheck) +{ + const count = arrayToCheck => + arrayToCheck.reduce((a, b) => ({ ...a, + [b]: (a[b] || 0) + 1 + }), {}) + + const duplicates = dict => + Object.keys(dict).filter((a) => dict[a] > 1) + + return {count: count(arrayToCheck), duplicates: duplicates(count(arrayToCheck))}; +} + +/* + * Checks whether a given string is empty and returns a string + * If stringToCheck is empty, an empty string is returned otherwise + * stringToAdd is returned + * + * stringToCheck - The string to be compared to empty string + * stringToAdd - The string to return when stringToCheck is non empty + * + */ +function stringOrEmpty(stringToCheck, stringToAdd) +{ + if (stringToCheck != "") + { + return stringToAdd; + } + return ""; +} + +/* + * Check that HW signal type matches a specified array of types + * + * Example: within a module's filterHardware(component) method: + * for (sig in component.signals) { + * let type = component.signals[sig].type; + * if (Common.typeMatches(type, ["PWM", "DOUT"])) { + * : + * } + * } + * + * type - a string or array of strings that are valid signal types + * nameArray - array of signal name types that must match one of the signal + * types named by type + * + * Returns true iff nameArray contains at least one type name that's + * specified the type parameter. + */ +function typeMatches(type, nameArray) +{ + let options = {}; + + if (type instanceof Array || typeof type == "object") { + for (var i = 0; i < type.length; i++) { + options[type[i]] = 1; + } + } + else if (typeof type == "string" || type instanceof String) { + options[type] = 1; + } + + for (var i = 0; i < nameArray.length; i++) { + let name = nameArray[i]; + if (name in options) { + return (true); + } + } + + return (false); +} + +exports = { + getSelfSysCfgCoreName, + isSciClientSupported, + getSocName, + getDeviceName, + camelSentence, + getStaticModuleForCore, + getModuleForCore, + getSysCfgCoreNames, + getUseMcuDomainPeripheralsConfig, + isMcuDomainSupported, + findDuplicates, + stringOrEmpty, + typeMatches, + getNodePath, + + validate: { + checkSameInstanceName : function (instance, report) { + checkSameFieldName(instance, "instance", report); + }, + checkSameInstanceNameOnAllCores : function (moduleName, instance, report) { + checkSameFieldNameOnAllCores(moduleName, instance, "instance", report); + }, + checkSameFieldName : checkSameFieldName, + checkSameFieldNameOnAllCores : checkSameFieldNameOnAllCores, + checkNumberRange: function(instance, report, property, min, max, displayFormat) { + if(instance[property] > max || instance[property] < min) { + let base = 10; + + if(displayFormat == "hex") { + base = 16; + + report.logError( `Value must be between 0x${min.toString(base).toUpperCase()}` + + ` .. 0x${max.toString(base).toUpperCase()}`, + instance, property); + } + else { + report.logError( `Value must be between ${min.toString(base).toUpperCase()}` + + ` .. ${max.toString(base).toUpperCase()}`, + instance, property); + } + } + }, + checkValidCName: function(instance, report, property) { + if(isCName((instance[property])) === false) { + report.logError(`Provide a valid C name`, instance, property); + } + }, + checkConfigurableValueMatchForAllCores(moduleName, instance, report, configurable, core_instances) + { + let coreNames = getSysCfgCoreNames(); + let selfCoreName = getSelfSysCfgCoreName(); + + for ( let remoteCoreName of coreNames) + { + if( remoteCoreName != selfCoreName) + { + let remote_core_instance = getStaticModuleForCore(moduleName, remoteCoreName); + + if(remote_core_instance && instance[configurable] != remote_core_instance[configurable]) + { + report.logError("Value MUST match with other cores", instance, configurable); + break; + } + } + } + }, + }, + + ui: + { + makeInstanceConfig: function(staticConfigArr) { + return makeConfig(staticConfigArr, "instance", "Instance"); + }, + makeConfig: makeConfig, + } +}; diff --git a/source/.meta/system_am243x.syscfg.js b/source/.meta/system_am243x.syscfg.js new file mode 100644 index 0000000..d4aa963 --- /dev/null +++ b/source/.meta/system_am243x.syscfg.js @@ -0,0 +1,24 @@ + +let common = system.getScript("/common"); + +let system_module = { + displayName: "System", + + moduleStatic: { + modules: function(inst) { + return [ + { + name: "clock", + moduleName: "/kernel/dpl/clock", + }, + { + name: "debug_log", + moduleName: "/kernel/dpl/debug_log", + }, + ] + }, + }, +}; + +exports = system_module; + diff --git a/source/.meta/system_am263x.syscfg.js b/source/.meta/system_am263x.syscfg.js new file mode 100644 index 0000000..d4aa963 --- /dev/null +++ b/source/.meta/system_am263x.syscfg.js @@ -0,0 +1,24 @@ + +let common = system.getScript("/common"); + +let system_module = { + displayName: "System", + + moduleStatic: { + modules: function(inst) { + return [ + { + name: "clock", + moduleName: "/kernel/dpl/clock", + }, + { + name: "debug_log", + moduleName: "/kernel/dpl/debug_log", + }, + ] + }, + }, +}; + +exports = system_module; + diff --git a/source/.meta/system_am273x.syscfg.js b/source/.meta/system_am273x.syscfg.js new file mode 100644 index 0000000..486f3af --- /dev/null +++ b/source/.meta/system_am273x.syscfg.js @@ -0,0 +1,24 @@ + +let common = system.getScript("/common"); + +let system_module = { + displayName: "System", + + moduleStatic: { + modules: function(inst) { + return [ + { + name: "clock", + moduleName: "/kernel/dpl/clock", + }, + { + name: "debug_log", + moduleName: "/kernel/dpl/debug_log", + }, + ] + }, + }, +}; + +exports = system_module; + diff --git a/source/.meta/system_am62x.syscfg.js b/source/.meta/system_am62x.syscfg.js new file mode 100644 index 0000000..d4aa963 --- /dev/null +++ b/source/.meta/system_am62x.syscfg.js @@ -0,0 +1,24 @@ + +let common = system.getScript("/common"); + +let system_module = { + displayName: "System", + + moduleStatic: { + modules: function(inst) { + return [ + { + name: "clock", + moduleName: "/kernel/dpl/clock", + }, + { + name: "debug_log", + moduleName: "/kernel/dpl/debug_log", + }, + ] + }, + }, +}; + +exports = system_module; + diff --git a/source/.meta/system_am64x.syscfg.js b/source/.meta/system_am64x.syscfg.js new file mode 100644 index 0000000..d4aa963 --- /dev/null +++ b/source/.meta/system_am64x.syscfg.js @@ -0,0 +1,24 @@ + +let common = system.getScript("/common"); + +let system_module = { + displayName: "System", + + moduleStatic: { + modules: function(inst) { + return [ + { + name: "clock", + moduleName: "/kernel/dpl/clock", + }, + { + name: "debug_log", + moduleName: "/kernel/dpl/debug_log", + }, + ] + }, + }, +}; + +exports = system_module; + diff --git a/source/.meta/system_awr294x.syscfg.js b/source/.meta/system_awr294x.syscfg.js new file mode 100644 index 0000000..486f3af --- /dev/null +++ b/source/.meta/system_awr294x.syscfg.js @@ -0,0 +1,24 @@ + +let common = system.getScript("/common"); + +let system_module = { + displayName: "System", + + moduleStatic: { + modules: function(inst) { + return [ + { + name: "clock", + moduleName: "/kernel/dpl/clock", + }, + { + name: "debug_log", + moduleName: "/kernel/dpl/debug_log", + }, + ] + }, + }, +}; + +exports = system_module; + diff --git a/source/.meta/system_common.syscfg.js b/source/.meta/system_common.syscfg.js new file mode 100644 index 0000000..80f5102 --- /dev/null +++ b/source/.meta/system_common.syscfg.js @@ -0,0 +1,8 @@ + +/* This file exports modules that are mandatory and always needed in any application. + * All modules just need to include this module and it will pull in all mandatory modules. + */ +let common = system.getScript("/common"); +let soc = system.getScript(`/system_${common.getSocName()}`); + +exports = soc; \ No newline at end of file diff --git a/source/motor_control/.meta/motor_control.syscfg.js b/source/motor_control/.meta/motor_control.syscfg.js new file mode 100644 index 0000000..44aeeae --- /dev/null +++ b/source/motor_control/.meta/motor_control.syscfg.js @@ -0,0 +1,8 @@ + +let common = system.getScript("/common"); +let soc = system.getScript(`/motor_control/soc/motor_control_${common.getSocName()}`); + +exports = { + displayName: "TI Motor Control Protocols", + topModules: soc.getTopModules(), +}; diff --git a/source/motor_control/.meta/position_sense/endat.syscfg.js b/source/motor_control/.meta/position_sense/endat.syscfg.js new file mode 100644 index 0000000..fb21ead --- /dev/null +++ b/source/motor_control/.meta/position_sense/endat.syscfg.js @@ -0,0 +1,128 @@ + +let common = system.getScript("/common"); +let hdsl_endat_pins = system.getScript("/motor_control/position_sense/hdsl_endat_pins.js"); +let endat_module_name = "/motor_control/position_sense/endat"; +let device = common.getDeviceName(); +function onValidate(inst, validation) { + + for (let instance_index in inst.$module.$instances) + { + let instance = inst.$module.$instances[instance_index]; + /* select atleast one cahnnel */ + if ((!instance.Channel_0)&&(!instance.Channel_2)&&(!instance.Channel_1)) + validation.logError("Select atleast one channel",inst,"Channel_0"); + /* validation for booster pack */ + if((device!="am243x-lp")&&(instance.Booster_Pack)) + { + validation.logError("Select only when using Booster Pack with LP",inst,"Booster_Pack"); + } + } + +} + + + +let endat_module = { + displayName: "EnDat Position Encoder", + templates: { + "/drivers/system/system_config.h.xdt": { + driver_config:"/motor_control/.meta/position_sense/templates/endat_templates.h.xdt", + moduleName: endat_module_name, + }, + "/drivers/pinmux/pinmux_config.c.xdt": { + moduleName: endat_module_name, + }, + }, + defaultInstanceName: "CONFIG_ENDAT", + config: [ + { + name: "instance", + displayName: "Instance", + default: "ICSSG0", + options: [ + { + name: "ICSSG0", + }, + { + name: "ICSSG1", + } + ], + }, + { + name: "Channel_0", + displayName: "Enable Channel 0", + description: "Channel 0 Selection", + default: true, + }, + { + name: "Channel_1", + displayName: "Enable Channel 1", + description: "Channel 1 Selection ", + default: false, + }, + { + name: "Channel_2", + displayName: "Enable Channel 2", + description: "Channel 2 Selection ", + default: false, + }, + + { + name: "Multi_Channel_Load_Share", + displayName: "Multi Channel Load Share", + description: "Selected Channels have different make", + default: false, + }, + { + name: "Booster_Pack", + displayName: "Booster Pack", + description: "Only for Booster Pack", + default: false, + }, + + ], + moduleStatic: { + modules: function(inst) { + return [{ + name: "system_common", + moduleName: "/system_common", + }] + }, + }, + pinmuxRequirements: hdsl_endat_pins.pinmuxRequirements, + getInterfaceName: hdsl_endat_pins.getInterfaceName, + getPeripheralPinNames: hdsl_endat_pins.getPeripheralPinNames, + sharedModuleInstances: sharedModuleInstances, + validate: onValidate, + +}; + +function sharedModuleInstances(instance) { + let modInstances = new Array(); + + modInstances.push({ + name: "pru", + displayName: "PRU ICSS Configuration", + moduleName: '/drivers/pruicss/pruicss', + requiredArgs: { + instance: instance.instance, + + }, + }); + if(device == "am243x-lp") + { + modInstances.push({ + name: "ENC1_EN", + displayName: "Booster Pack Ch0 Enable Pin", + moduleName: "/drivers/gpio/gpio", + requiredArgs: { + pinDir: "OUTPUT" + }, + }); + } + + + return (modInstances); +} + +exports = endat_module; diff --git a/source/motor_control/.meta/position_sense/hdsl.syscfg.js b/source/motor_control/.meta/position_sense/hdsl.syscfg.js new file mode 100644 index 0000000..71a93f1 --- /dev/null +++ b/source/motor_control/.meta/position_sense/hdsl.syscfg.js @@ -0,0 +1,139 @@ + +let common = system.getScript("/common"); +let hdsl_endat_pins = system.getScript("/motor_control/position_sense/hdsl_endat_pins.js"); +let device = common.getDeviceName(); +let hdsl_module_name = "/motor_control/position_sense/hdsl"; + +function onValidate(inst, validation) { + + for (let instance_index in inst.$module.$instances) + { + /* validation for booster pack */ + if((device!="am243x-lp")&&(instance.Booster_Pack)) + { + validation.logError("Select only when using Booster Pack with LP",inst,"Booster_Pack"); + } + } + +} + +let hdsl_module = { + + displayName: "HDSL Position Encoder", + templates: { + "/drivers/system/system_config.h.xdt": { + driver_config: "/motor_control/position_sense/templates/hdsl_templates.h.xdt", + moduleName: hdsl_module_name, + }, + "/drivers/pinmux/pinmux_config.c.xdt": { + moduleName: hdsl_module_name, + }, + }, + defaultInstanceName: "CONFIG_HDSL", + config: [ + { + name: "instance", + displayName: "Instance", + default: "ICSSG0", + options: [ + { + name: "ICSSG0", + }, + { + name: "ICSSG1", + } + ], + }, + { + name: "coreClk", + displayName: "PRU-ICSS Core Clk (Hz)", + default: 225*1000000, + options: [ + { + name: 225*1000000, + }, + + { + name: 300*1000000, + }, + + ], + }, + { + name: "Booster_Pack", + displayName: "Booster Pack", + description: "Only for Booster Pack", + default: false, + }, + { + name: "Mode", + displayName: "Select Mode", + description: "Mode selection", + default: "FREE_RUN", + options: [ + { + name: "FREE_RUN", + }, + { + name: "SYNC", + }, + ], + }, + { + name: "channel_0", + displayName: "Select Channel 0", + description: "Channel 0 Selection ", + default: true, + + }, + { + name: "channel_1", + displayName: "Select Channel 1", + description: "Channel 1 Selection ", + default: false, + + }, + ], + moduleStatic: { + modules: function(inst) { + return [{ + name: "system_common", + moduleName: "/system_common", + }] + }, + }, + pinmuxRequirements: hdsl_endat_pins.pinmuxRequirements, + getInterfaceName: hdsl_endat_pins.getInterfaceName, + getPeripheralPinNames: hdsl_endat_pins.getPeripheralPinNames, + sharedModuleInstances: sharedModuleInstances, +}; + +function sharedModuleInstances(instance) { + let modInstances = new Array(); + + modInstances.push({ + name: "pru", + displayName: "PRU ICSS Configuration", + moduleName: '/drivers/pruicss/pruicss', + requiredArgs: { + instance: instance.instance, + coreClk: instance.coreClk, + iepSyncMode: true, + }, + }); + if(device == "am243x-lp") + { + modInstances.push({ + name: "ENC1_EN", + displayName: "Booster Pack Ch0 Enable Pin", + moduleName: "/drivers/gpio/gpio", + requiredArgs: { + pinDir: "OUTPUT" + }, + }); + } + + return (modInstances); +} + +exports = hdsl_module; diff --git a/source/motor_control/.meta/position_sense/hdsl_endat_pins.js b/source/motor_control/.meta/position_sense/hdsl_endat_pins.js new file mode 100644 index 0000000..f90783e --- /dev/null +++ b/source/motor_control/.meta/position_sense/hdsl_endat_pins.js @@ -0,0 +1,79 @@ + +let common = system.getScript("/common"); +let pinmux = system.getScript("/drivers/pinmux/pinmux"); + + +function getInterfaceName(inst) +{ + return `PRU_${inst.instance}_PRU`; +} + +function getInterfacePinList(inst) +{ + let pinList = []; + + pinList.push({ pinName: "GPO2", displayName: "ENDAT0_OUT_EN", rx: false}); + pinList.push({ pinName: "GPO1", displayName: "ENDAT0_OUT", rx: false}); + pinList.push({ pinName: "GPO0", displayName: "ENDAT0_CLK", rx: false}); + pinList.push({ pinName: "GPI13", displayName: "ENDAT0_IN", rx: true}); + + pinList.push({ pinName: "GPO5", displayName: "ENDAT1_OUT_EN", rx: false}); + pinList.push({ pinName: "GPO4", displayName: "ENDAT1_OUT", rx: false}); + pinList.push({ pinName: "GPO3", displayName: "ENDAT1_CLK", rx: false}); + pinList.push({ pinName: "GPI14", displayName: "ENDAT1_IN", rx: true}); + + pinList.push({ pinName: "GPO8", displayName: "ENDAT2_OUT_EN", rx: false}); + pinList.push({ pinName: "GPO12", displayName: "ENDAT2_OUT", rx: false}); + pinList.push({ pinName: "GPO6", displayName: "ENDAT2_CLK", rx: false}); + pinList.push({ pinName: "GPI11", displayName: "ENDAT2_IN", rx: true}); + + return pinList; +} + +function pinmuxRequirements(inst) { + + let interfaceName = getInterfaceName(inst); + let pinList = getInterfacePinList(inst); + let resources = []; + + for(let pin of pinList) + { + let pinResource = pinmux.getPinRequirements(interfaceName, pin.pinName, pin.displayName); + + pinmux.setConfigurableDefault( pinResource, "rx", pin.rx ); + + resources.push( pinResource ); + } + + let peripheralRequirements = { + name: interfaceName, + displayName: interfaceName, + interfaceName: interfaceName, + resources: resources, + }; + + return [peripheralRequirements]; +} + +function getPeripheralPinNames(inst) +{ + let pinList = []; + let pinNameList = []; + + pinList = getInterfacePinList(inst); + + for(let pin of pinList) + { + pinNameList.push( pin.pinName ); + } + + return pinNameList; +} + + +exports = { + + pinmuxRequirements, + getInterfaceName, + getPeripheralPinNames, +}; diff --git a/source/motor_control/.meta/position_sense/tamagawa.syscfg.js b/source/motor_control/.meta/position_sense/tamagawa.syscfg.js new file mode 100644 index 0000000..5a070a6 --- /dev/null +++ b/source/motor_control/.meta/position_sense/tamagawa.syscfg.js @@ -0,0 +1,142 @@ + +let common = system.getScript("/common"); +let tamagawa_pins = system.getScript("/motor_control/position_sense/tamagawa_pins.js"); +let device = common.getDeviceName(); +let is_am243x_lp_device = (device === "am243x-lp") ? true : false; + +let tamagawa_module_name = "/motor_control/position_sense/tamagawa"; + +function onValidate(inst, validation) { + for (let instance_index in inst.$module.$instances) + { + let instance = inst.$module.$instances[instance_index]; + if ((!instance.channel_0)&&(!instance.channel_1)&&(!instance.channel_2)) + validation.logError( + "Select atleast one channel",inst,"channel_0" + ); + + if(is_am243x_lp_device && (instance.channel_1 || instance.channel_2)) + validation.logError( + "On AM243x-LP, only Channel 0 is supported",inst,"channel_0" + ); + + /* validation for booster pack */ + if((device!="am243x-lp")&&(instance.Booster_Pack)) + { + validation.logError("Select only when using Booster Pack with LP",inst,"Booster_Pack"); + } + } +} + +let tamagawa_module = { + + displayName: "Tamagawa Position Encoder", + templates: { + "/drivers/system/system_config.h.xdt": { + driver_config: "/motor_control/position_sense/tamagawa/tamagawa.h.xdt", + moduleName: tamagawa_module_name, + }, + + "/drivers/pinmux/pinmux_config.c.xdt": { + moduleName: tamagawa_module_name, + }, + }, + defaultInstanceName: "CONFIG_TAMAGAWA", + config: [ + { + name: "instance", + displayName: "Instance", + default: "ICSSG0", + options: [ + { + name: "ICSSG0", + }, + { + name: "ICSSG1", + } + ], + }, + { + name: "channel_0", + displayName: "Select Channel 0", + description: "Channel 0 Selection ", + default: true, + + }, + { + name: "channel_1", + displayName: "Select Channel 1", + description: "Channel 1 Selection ", + default: false, + + }, + { + name: "channel_2", + displayName: "Select Channel 2", + description: "Channel 2 Selection ", + default: false, + + }, + { + name: "baudrate", + displayName: "Select Baud Rate(in Mbps)", + description: "Data Speed Selection ", + default: 2.5, + options: [ + { + name: 2.5, + }, + { + name: 5, + }, + ], + }, + { + name: "Booster_Pack", + displayName: "Booster Pack", + description: "Only for Booster Pack", + default: false, + }, + ], + moduleStatic: { + modules: function(inst) { + return [{ + name: "system_common", + moduleName: "/system_common", + }] + }, + }, + pinmuxRequirements: tamagawa_pins.pinmuxRequirements, + getInterfaceName: tamagawa_pins.getInterfaceName, + getPeripheralPinNames: tamagawa_pins.getPeripheralPinNames, + sharedModuleInstances: sharedModuleInstances, + validate: onValidate, +}; + +function sharedModuleInstances(instance) { + let modInstances = new Array(); + + modInstances.push({ + name: "pru", + displayName: "PRU ICSS Configuration", + moduleName: '/drivers/pruicss/pruicss', + requiredArgs: { + instance: instance.instance, + coreClk: 200*1000000, + }, + }); + if(device == "am243x-lp") + { + modInstances.push({ + name: "ENC1_EN", + displayName: "Booster Pack Ch0 Enable Pin", + moduleName: "/drivers/gpio/gpio", + requiredArgs: { + pinDir: "OUTPUT" + }, + }); + } + return (modInstances); +} + +exports = tamagawa_module; diff --git a/source/motor_control/.meta/position_sense/tamagawa/tamagawa.h.xdt b/source/motor_control/.meta/position_sense/tamagawa/tamagawa.h.xdt new file mode 100644 index 0000000..016142c --- /dev/null +++ b/source/motor_control/.meta/position_sense/tamagawa/tamagawa.h.xdt @@ -0,0 +1,37 @@ +%%{ + let module = system.modules[args[0]]; +%%} +/* + * Tamagawa + */ + +/* Tamagawa Instance Macros */ +#define CONFIG_TAMAGAWA_NUM_INSTANCES `module.$instances.length` +% for(let i = 0; i < module.$instances.length; i++) { + % let instance = module.$instances[i]; + % let sliceVal = 1; + % let icssValue = 0; + % if(instance.instance === "ICSSG0") + % { + % if(instance.PRU_ICSSG0_PRU.$assign === "PRU_ICSSG0_PRU0") + % { + % sliceVal = 0; + % } + % } + % else if(instance.instance === "ICSSG1") + % { + % icssValue = 1; + % if(instance.PRU_ICSSG1_PRU.$assign === "PRU_ICSSG1_PRU0") + % { + % sliceVal = 0; + % } + % } +#define `instance.$name` (`i`) +#define `instance.$name`_CHANNEL0 (`instance.channel_0 & 1`) +#define `instance.$name`_CHANNEL1 (`instance.channel_1 & 1`) +#define `instance.$name`_CHANNEL2 (`instance.channel_2 & 1`) +#define `instance.$name`_BAUDRATE (`instance.baudrate`) +#define `instance.$name`_BOOSTER_PACK (`instance.Booster_Pack & 1`) +#define PRUICSS_PRUx (`sliceVal`) +#define PRUICSSx (`icssValue`) +% } \ No newline at end of file diff --git a/source/motor_control/.meta/position_sense/tamagawa_pins.js b/source/motor_control/.meta/position_sense/tamagawa_pins.js new file mode 100644 index 0000000..c0987e5 --- /dev/null +++ b/source/motor_control/.meta/position_sense/tamagawa_pins.js @@ -0,0 +1,79 @@ + +let common = system.getScript("/common"); +let pinmux = system.getScript("/drivers/pinmux/pinmux"); + + +function getInterfaceName(inst) +{ + return `PRU_${inst.instance}_PRU`; +} + +function getInterfacePinList(inst) +{ + let pinList = []; + + pinList.push({ pinName: "GPO2", displayName: "TAMAGAWA_CHANNEL0_TX_ENABLE", rx: false}); + pinList.push({ pinName: "GPO1", displayName: "TAMAGAWA_CHANNEL0_TX", rx: false}); + pinList.push({ pinName: "GPO0", displayName: "TAMAGAWA_CHANNEL0_CLK", rx: false}); + pinList.push({ pinName: "GPI13", displayName: "TAMAGAWA_CHANNEL0_RX", rx: true}); + + pinList.push({ pinName: "GPO5", displayName: "TAMAGAWA_CHANNEL1_TX_ENABLE", rx: false}); + pinList.push({ pinName: "GPO4", displayName: "TAMAGAWA_CHANNEL1_TX", rx: false}); + pinList.push({ pinName: "GPO3", displayName: "TAMAGAWA_CHANNEL1_CLK", rx: false}); + pinList.push({ pinName: "GPI14", displayName: "TAMAGAWA_CHANNEL1_RX", rx: true}); + + pinList.push({ pinName: "GPO8", displayName: "TAMAGAWA_CHANNEL2_TX_ENABLE", rx: false}); + pinList.push({ pinName: "GPO12", displayName: "TAMAGAWA_CHANNEL2_TX", rx: false}); + pinList.push({ pinName: "GPO6", displayName: "TAMAGAWA_CHANNEL2_CLK", rx: false}); + pinList.push({ pinName: "GPI11", displayName: "TAMAGAWA_CHANNEL2_RX", rx: true}); + + return pinList; +} + +function pinmuxRequirements(inst) { + + let interfaceName = getInterfaceName(inst); + let pinList = getInterfacePinList(inst); + let resources = []; + + for(let pin of pinList) + { + let pinResource = pinmux.getPinRequirements(interfaceName, pin.pinName, pin.displayName); + + pinmux.setConfigurableDefault( pinResource, "rx", pin.rx ); + + resources.push( pinResource ); + } + + let peripheralRequirements = { + name: interfaceName, + displayName: interfaceName, + interfaceName: interfaceName, + resources: resources, + }; + + return [peripheralRequirements]; +} + +function getPeripheralPinNames(inst) +{ + let pinList = []; + let pinNameList = []; + + pinList = getInterfacePinList(inst); + + for(let pin of pinList) + { + pinNameList.push( pin.pinName ); + } + + return pinNameList; +} + + +exports = { + + pinmuxRequirements, + getInterfaceName, + getPeripheralPinNames, +}; diff --git a/source/motor_control/.meta/position_sense/templates/endat_templates.h.xdt b/source/motor_control/.meta/position_sense/templates/endat_templates.h.xdt new file mode 100644 index 0000000..bde29b0 --- /dev/null +++ b/source/motor_control/.meta/position_sense/templates/endat_templates.h.xdt @@ -0,0 +1,50 @@ +%%{ + let module = system.modules[args[0]]; +%%} +/* + * EnDat + */ + +/* EnDat Instance Macros */ +#define CONFIG_ENDAT_NUM_INSTANCES `module.$instances.length` +%for(let i = 0; i < module.$instances.length; i++) { + % let instance = module.$instances[i]; + % let Mode = 0; + % let Slice = 0 ; + %if(instance.instance === "ICSSG1") + %{ + % if(instance.PRU_ICSSG1_PRU.$assign === "PRU_ICSSG1_PRU1") + %{ + % Slice = 1; + %} + + %} + %else + %{ + %if(instance.PRU_ICSSG0_PRU.$assign === "PRU_ICSSG0_PRU1") + %{ + % Slice = 1; + %} + + %} + %if(((instance.Channel_0 & 1)&&(instance.Channel_1 & 1))||((instance.Channel_1 & 1)&&(instance.Channel_2 & 1))||((instance.Channel_2 & 1)&&(instance.Channel_0 & 1))) + %{ + % Mode = 1; + %} + %if(instance.Multi_Channel_Load_Share & 1) + %{ + % Mode = 2; + %} + +#define `instance.$name` `i` +#define `instance.$name`_CHANNEL0 `instance.Channel_0 & 1` +#define `instance.$name`_CHANNEL1 `instance.Channel_1 & 1` +#define `instance.$name`_CHANNEL2 `instance.Channel_2 & 1` +#define `instance.$name`_load_share_mode `instance.Multi_Channel_Load_Share & 1` +#define `instance.$name`_MODE `Mode` +#define `instance.$name`_BOOSTER_PACK `instance.Booster_Pack & 1` +#define PRU_ICSSGx_PRU_SLICE `Slice` +% } + + + diff --git a/source/motor_control/.meta/position_sense/templates/hdsl_templates.h.xdt b/source/motor_control/.meta/position_sense/templates/hdsl_templates.h.xdt new file mode 100644 index 0000000..372aaef --- /dev/null +++ b/source/motor_control/.meta/position_sense/templates/hdsl_templates.h.xdt @@ -0,0 +1,28 @@ +%%{ + let module = system.modules[args[0]]; +%%} +/* + * HDSL + */ + +/* HDSL Instance Macros */ + +#define CONFIG_HDSL_NUM_INSTANCES `module.$instances.length` +% for(let i = 0; i < module.$instances.length; i++) { + % let instance = module.$instances[i]; + % let Mode = 0; + %if(instance.Mode === "FREE_RUN") + %{ + % Mode = 0; + + %} + %else + %{ + % Mode = 1; + %} +#define `instance.$name`_BOOSTER_PACK `instance.Booster_Pack & 1` +#define `instance.$name` (`i`) +#define `instance.$name`_CHANNEL0 (`instance.channel_0 & 1`) +#define `instance.$name`_CHANNEL1 (`instance.channel_1 & 1`) +#define `instance.$name`_MODE (`Mode`) +% } \ No newline at end of file diff --git a/source/motor_control/.meta/soc/motor_control_am243x.syscfg.js b/source/motor_control/.meta/soc/motor_control_am243x.syscfg.js new file mode 100644 index 0000000..e1ac97f --- /dev/null +++ b/source/motor_control/.meta/soc/motor_control_am243x.syscfg.js @@ -0,0 +1,26 @@ + +let common = system.getScript("/common"); + +const topModules_main = [ + "/motor_control/position_sense/endat", + "/motor_control/position_sense/hdsl", + "/motor_control/position_sense/tamagawa", + +]; + +const topModules_mcu = [ + +]; + +exports = { + getTopModules: function() { + + let topModules = topModules_main; + + if(common.getSelfSysCfgCoreName().includes("m4f")) { + topModules = topModules_mcu; + } + + return topModules; + }, +}; diff --git a/source/motor_control/.meta/soc/motor_control_am263x.syscfg.js b/source/motor_control/.meta/soc/motor_control_am263x.syscfg.js new file mode 100644 index 0000000..8daf6e0 --- /dev/null +++ b/source/motor_control/.meta/soc/motor_control_am263x.syscfg.js @@ -0,0 +1,14 @@ + +let common = system.getScript("/common"); + +const topModules = [ + +]; + + + +exports = { + getTopModules: function() { + return topModules; + }, +}; diff --git a/source/motor_control/.meta/soc/motor_control_am273x.syscfg.js b/source/motor_control/.meta/soc/motor_control_am273x.syscfg.js new file mode 100644 index 0000000..8daf6e0 --- /dev/null +++ b/source/motor_control/.meta/soc/motor_control_am273x.syscfg.js @@ -0,0 +1,14 @@ + +let common = system.getScript("/common"); + +const topModules = [ + +]; + + + +exports = { + getTopModules: function() { + return topModules; + }, +}; diff --git a/source/motor_control/.meta/soc/motor_control_am64x.syscfg.js b/source/motor_control/.meta/soc/motor_control_am64x.syscfg.js new file mode 100644 index 0000000..54733ba --- /dev/null +++ b/source/motor_control/.meta/soc/motor_control_am64x.syscfg.js @@ -0,0 +1,33 @@ + +let common = system.getScript("/common"); + +const topModules_main = [ + "/motor_control/position_sense/endat", + "/motor_control/position_sense/hdsl", + "/motor_control/position_sense/tamagawa", +]; + +const topModules_mcu = [ + +]; + +const topModules_a53 = [ + +]; + +exports = { + getTopModules: function() { + + let topModules = topModules_main; + + if(common.getSelfSysCfgCoreName().includes("m4f")) { + topModules = topModules_mcu; + } + if (common.getSelfSysCfgCoreName().match(/a53*/)) + { + topModules = topModules_a53; + } + + return topModules; + }, +}; diff --git a/source/motor_control/.meta/soc/motor_control_awr294x.syscfg.js b/source/motor_control/.meta/soc/motor_control_awr294x.syscfg.js new file mode 100644 index 0000000..47bf9e4 --- /dev/null +++ b/source/motor_control/.meta/soc/motor_control_awr294x.syscfg.js @@ -0,0 +1,12 @@ + +let common = system.getScript("/common"); + +const topModules = [ + +]; + +exports = { + getTopModules: function() { + return topModules; + }, +}; diff --git a/source/motor_control/current_sense/sdfm/.project/project.js b/source/motor_control/current_sense/sdfm/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/current_sense/sdfm/.project/project_am243x.js b/source/motor_control/current_sense/sdfm/.project/project_am243x.js new file mode 100644 index 0000000..5e4a2d6 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/.project/project_am243x.js @@ -0,0 +1,53 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "sdfm_drv.c", + ], +}; + +const filedirs = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/driver", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/include", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/firmware", + ], +}; + +const buildOptionCombos = [ + { device: device, cpu: "r5f", cgt: "ti-arm-clang"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "library"; + property.name = "motorcontrol_sdfm"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/current_sense/sdfm/.project/project_am64x.js b/source/motor_control/current_sense/sdfm/.project/project_am64x.js new file mode 100644 index 0000000..8101894 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/.project/project_am64x.js @@ -0,0 +1,53 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "sdfm_drv.c", + ], +}; + +const filedirs = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/driver", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/include", + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/firmware", + ], +}; + +const buildOptionCombos = [ + { device: device, cpu: "r5f", cgt: "ti-arm-clang"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "library"; + property.name = "motorcontrol_sdfm"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/current_sense/sdfm/driver/sdfm_drv.c b/source/motor_control/current_sense/sdfm/driver/sdfm_drv.c new file mode 100644 index 0000000..534fb8f --- /dev/null +++ b/source/motor_control/current_sense/sdfm/driver/sdfm_drv.c @@ -0,0 +1,344 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//! Macro to get the low threshold +#define SDFM_GET_LOW_THRESHOLD(C) ((uint16_t)(C)) + +//! Macro to get the high threshold +#define SDFM_GET_HIGH_THRESHOLD(C) ((uint16_t)((uint32_t)(C) >> 16U)) + +//! Macro to get the high threshold 1 & 2 to be passed as lowThreshold +//! parameter to SDFM_setCompFilterLowThreshold(). +#define SDFM_GET_LOW_THRESHOLD_BOTH(C1, C2) \ + ((((uint32_t)(SDFM_GET_LOW_THRESHOLD(C2))) << 16U) | \ + ((uint32_t)(SDFM_GET_LOW_THRESHOLD(C1)))) + +//! Macro to get the high threshold 1 & 2 to be passed as highThreshold +//! parameter to SDFM_setCompFilterHighThreshold(). +#define SDFM_GET_HIGH_THRESHOLD_BOTH(C1, C2) \ + ((((uint32_t)(SDFM_GET_HIGH_THRESHOLD(C2))) << 16U) | \ + ((uint32_t)(SDFM_GET_HIGH_THRESHOLD(C1)))) + +//! Macro to convert comparator over sampling ratio to acceptable bit location +#define SDFM_SET_OSR(X) (((X) - 1) << 8U) + +//! Macro to convert the data shift bit values to acceptable bit location +#define SDFM_SHIFT_VALUE(X) ((X) << 2U) + +//! Macro to combine high threshold and low threshold values +#define SDFM_THRESHOLD(H, L) ((((uint32_t)(H)) << 16U) | (L)) + +//! Macro to set the FIFO level to acceptable bit location +#define SDFM_SET_FIFO_LEVEL(X) ((X) << 7U) + +//! Macro to set and enable the zero cross threshold value. +#define SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) (0x8000 | (X)) + +//! Macros to enable or disable filter. +#define SDFM_FILTER_DISABLE (0x0U) +#define SDFM_FILTER_ENABLE (0x2U) + +//***************************************************************************** +// +//! Values that can be returned from SDFM_getThresholdStatus() +// +//***************************************************************************** +#define SDFM_OUTPUT_WITHIN_THRESHOLD (0) //!< SDFM output is within threshold +#define SDFM_OUTPUT_ABOVE_THRESHOLD (1) //!< SDFM output is above high threshold +#define SDFM_OUTPUT_BELOW_THRESHOLD (2) //!< SDFM output is below low threshold + +//! Filter output is in 16 bits 2's complement format. +#define SDFM_DATA_FORMAT_16_BIT (0) +//! Filter output is in 32 bits 2's complement format. +#define SDFM_DATA_FORMAT_32_BIT (1) + +//! Mask for Interrupt is generated if Modulator fails. +//! +#define SDFM_MODULATOR_FAILURE_INTERRUPT_MASK ( 0 ) +//! Mask for Interrupt on Comparator low-level threshold. +//! +#define SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT_MASK ( 1 ) +//! Mask for Interrupt on Comparator high-level threshold. +//! +#define SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT_MASK ( 2 ) +//! Mask for Interrupt on Acknowledge flag +//! +#define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT_MASK ( 3 ) + +/* Internal structure for managing each PRU SD */ +//static sdfm g_sdfm[NUM_PRU] = { +SDFM g_sdfm[NUM_PRU] = { + {PRU_ID_0,0,0,0, NULL}, + {PRU_ID_1,0,0,0, NULL}, +}; +// static sdfm g_sdfm[NUM_PRU]; + +/* Initialize SDFM instance */ +sdfm_handle SDFM_init(uint8_t pru_id) +{ + SDFM *p_sdfm; + uint8_t ctrl; + uint8_t stat; + uint8_t pru_id_ack; + + if (pru_id == PRU_ID_0) { + /* Initialize PRU 0 SD */ + + p_sdfm = &g_sdfm[pru_id]; + + /* Initialize SDFM control address */ + p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + 0x0); + + /* Set FW PRU ID */ + ctrl = p_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl; + ctrl &= ~SDDF_CTRL_BF_PRU_ID_MASK; + ctrl |= pru_id << SDDF_CTRL_BF_PRU_ID_SHIFT; + p_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl = ctrl; + + /* Wait for FW PRU ID ACK */ + do { + stat = p_sdfm->p_sdfm_interface->sdfm_ctrl.stat; + pru_id_ack = (stat & SDDF_STAT_BF_PRU_ID_ACK_MASK) >> SDDF_STAT_BF_PRU_ID_ACK_SHIFT; + } while (pru_id_ack != pru_id); + } + else if (pru_id == PRU_ID_1) { + /* Initialize PRU 1 SD */ + + p_sdfm = &g_sdfm[pru_id]; + + /* Initialize SDFM control address */ + p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM1_SLV_RAM + 0x0); + + /* Set FW PRU ID */ + ctrl = p_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl; + ctrl &= ~SDDF_CTRL_BF_PRU_ID_MASK; + ctrl |= pru_id << SDDF_CTRL_BF_PRU_ID_SHIFT; + p_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl = ctrl; + + /* Wait for FW PRU ID ACK */ + do { + stat = p_sdfm->p_sdfm_interface->sdfm_ctrl.stat; + pru_id_ack = (stat & SDDF_STAT_BF_PRU_ID_ACK_MASK) >> SDDF_STAT_BF_PRU_ID_ACK_SHIFT; + } while (pru_id_ack != pru_id); + } + else { + p_sdfm = NULL; + } + + return (sdfm_handle)p_sdfm; +} + +/*Configuration of iep & pwm time period */ +void SDFM_configIepCount(sdfm_handle h_sdfm, uint32_t epwm_out_freq) +{ + /*; IEP0 default increment=1*/ + h_sdfm->p_sdfm_interface->sdfm_cfg_iep_ptr.iep_inc_value = h_sdfm->iep_inc; + /* + IEP0 CMP0 count to simulate EPWM (FOC loop) period: + - IEP frequency = 300 MHz + - IEP Default Increment = 1 + - Simulated EPWM frequency = 8e3 + CMP0 = 300e6/1/8e3 = 37500 = 0x927C + */ + uint32_t cnt_epwm_prd = h_sdfm->iep_clock/epwm_out_freq; + h_sdfm->p_sdfm_interface->sdfm_cfg_iep_ptr.cnt_epwm_prd = cnt_epwm_prd; + +} + +/*ecap configuration for SD clock*/ +void SDFM_configEcap(sdfm_handle h_sdfm, uint8_t ecap_divider) +{ + /* SD_PRD_CLOCKS divider = 15; SDFM_CLOCK = IEP freq./SD_PRD_CLOCKS; 300/15 => 20 MHz, SD_CLK_INV==0 => No clock inversion*/ + h_sdfm->p_sdfm_interface->sd_clk.sd_prd_clocks = ecap_divider; + h_sdfm->p_sdfm_interface->sd_clk.sd_clk_inv = 0; +} + +/*sdfm Hw osr configuration */ + void SDFM_setAccOverSamplingRatio(sdfm_handle h_sdfm, uint8_t ch_id, uint8_t osr) + { + /*SD Hw OSR*/ + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].osr = osr; + } + +/*sdfm high, low threshold config */ +void SDFM_setCompFilterThresholds(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_ThresholdParms thresholdParms) +{ + /* SD OC high threshold = (OC OSR)^(OC SINC ORDER) = 14^3 = 2744*/ + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_threshold_parms.high_threshold = thresholdParms.high_threshold; + /* SD OC low threshold */ + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_threshold_parms.low_threshold = thresholdParms.low_threshold; + +} + +/*sdfm smapling time configuation */ +void SDFM_setSampleReadingTime(sdfm_handle h_sdfm, float trig_samp_time) +{ /*convert sample time into IEP count*/ + /*samp time in us */ + int32_t count = (h_sdfm->iep_clock /1000000)*((float)trig_samp_time); + h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.trig_samp_time = count; +} +/* Enable the channel specified by the channel number parameter*/ +void SDFM_setEnableChannel(sdfm_handle h_sdfm, uint8_t channel_number) +{ + + if(channel_number == 0) + { + h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number << SDDF_CFG_BF_SD_CH0_ID_SHIFT); + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[channel_number].ch_id = channel_number; + } + else if(channel_number == 1) + { + h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number<< SDDF_CFG_BF_SD_CH1_ID_SHIFT); + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[channel_number].ch_id = channel_number; + } + else + { + h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number << SDDF_CFG_BF_SD_CH2_ID_SHIFT); + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[channel_number].ch_id = channel_number; + } +} +/* set SDFM channel acc source */ +void SDFM_configDataFilter(sdfm_handle h_sdfm, uint8_t ch_id, uint8_t filter) +{ + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].filter_type = filter; +} + +/*set clock source & clock inversion for SDFM channel*/ +void SDFM_selectClockSource(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_ClkSourceParms clkPrams) +{ + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_clk_parms.clk_source = clkPrams.clk_source; + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_clk_parms.clk_inv = clkPrams.clk_inv; +} + +/* Enable the comparator feature for a specified filter/channel */ +void SDFM_enableComparator(sdfm_handle h_sdfm, uint8_t ch) +{ + h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.enable_comparator |= (1 << ch); +} + +/* Disable the comparator feature for a specified filter/channel */ +void SDFM_disableComparator(sdfm_handle h_sdfm, uint8_t ch) +{ + h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.enable_comparator &= (0xFFFF ^ (1<BANK_REGISTERS[reg_index].CLR_DATA; + uint32_t set_data_addr = (uint32_t)&hGpio->BANK_REGISTERS[reg_index].SET_DATA; + + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].sdfm_gpio_params[threshold_type].write_val = reg_val; + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].sdfm_gpio_params[threshold_type].set_val_addr = set_data_addr; + h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].sdfm_gpio_params[threshold_type].clr_val_addr = clr_data_addr; +} + +/* Get current (or latest) sample for the specified channel */ +uint32_t SDFM_getFilterData(uint8_t ch) +{ + SDFM *p_sdfm = NULL; + p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + 0x0); + return p_sdfm->p_sdfm_interface->curr_out_samp_buf[ch]; +} +/*Configure Over current OSR*/ +void SDFM_setCompFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t osr) +{ + /*; IEP0 counts in OC sampling period: + ; - IEP0 count = + ; (NC OSR * SD clock period)*(IEP0 frequency * IEP default count) = + ; (NC OSR * IEP0 frequency * IEP default count)/(SD clock frequency) = + ; 64*300e6*1/20e6 = 960*/ + //IEP freq. 300MHz //SDFM clock 20MHz + // IEP Count = (OSR *(1/SD clock))*(IEP freq.) + uint16_t count; + uint32_t iep_freq = h_sdfm->iep_clock; + uint32_t sd_clock = h_sdfm->sdfm_clock; + count = (osr*(iep_freq/sd_clock)); + h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.oc_prd_iep_cnt = count; + +} + +/*Configure normal current OSR*/ +void SDFM_setFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t nc_osr, uint16_t oc_osr) +{ + /*OC sample count for NC sampling */ + uint16_t count; + count = (nc_osr/oc_osr); + h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.sample_count = count; + + /*IEP0 counts in NC sampling period*/ + uint32_t iep_freq = h_sdfm->iep_clock; + uint32_t sd_clock = h_sdfm->sdfm_clock; + count = (nc_osr*(iep_freq/sd_clock)); + h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.nc_prd_iep_cnt = count; +} +/* SDFM global enable */ +void SDFM_enable(sdfm_handle h_sdfm) +{ + uint8_t sdfm_ctrl; + uint8_t sdfm_stat; + uint8_t sdfm_en_ack; + + sdfm_ctrl = h_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl; + sdfm_ctrl &= ~SDDF_CTRL_BF_SDDF_EN_MASK; + sdfm_ctrl |= BF_SDDF_EN_ENABLE << SDDF_CTRL_BF_SDDF_EN_SHIFT; + h_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl = sdfm_ctrl; + + /* wait for ACK */ + do { + sdfm_stat = h_sdfm->p_sdfm_interface->sdfm_ctrl.stat; + sdfm_en_ack = (sdfm_stat & SDDF_STAT_BF_SDDF_EN_ACK_MASK) >> SDDF_STAT_BF_SDDF_EN_ACK_SHIFT; + } while (sdfm_en_ack != BF_SDDF_EN_ENABLE); + + +} + + diff --git a/source/motor_control/current_sense/sdfm/firmware/.project/project.js b/source/motor_control/current_sense/sdfm/firmware/.project/project.js new file mode 100644 index 0000000..7522b8b --- /dev/null +++ b/source/motor_control/current_sense/sdfm/firmware/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; \ No newline at end of file diff --git a/source/motor_control/current_sense/sdfm/firmware/.project/project_am243x.js b/source/motor_control/current_sense/sdfm/firmware/.project/project_am243x.js new file mode 100644 index 0000000..40a3e16 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/firmware/.project/project_am243x.js @@ -0,0 +1,98 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "sddf.asm", + "icssg_pru.cmd", + ], +}; + +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/firmware", + ], +}; + +const readmeDoxygenPageTag = "SDFM_DESIGN"; + +const cflags_pru = { + common: [ + "-v4", + "-DSDDF_PRU_CORE", + "-o2", + "--display_error_number", + "--hardware_mac=on", + ], +}; + +const lflags_pru = { + common: [ + "--disable_auto_rts", + "--define=SDDF_PRU_CORE=1", + "--warn_sections", + "--entry_point=SDDF_ENTRY", + "--zero_init=off", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru0", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, + +]; + + + +let postBuildStepsPru = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDDF_PRU0_image -o sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out; move sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/firmware/sdfm_bin.h;" +]; + + + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "sdfm_firmware"; + property.isInternal = false; + property.description = "ICSS SDFM" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.cflags = cflags_pru; + build_property.lflags = lflags_pru; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + build_property.postBuildSteps = postBuildStepsPru; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; \ No newline at end of file diff --git a/source/motor_control/current_sense/sdfm/firmware/.project/project_am64x.js b/source/motor_control/current_sense/sdfm/firmware/.project/project_am64x.js new file mode 100644 index 0000000..8013ba1 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/firmware/.project/project_am64x.js @@ -0,0 +1,98 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "sddf.asm", + "icssg_pru.cmd", + ], +}; + +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/firmware", + ], +}; + +const readmeDoxygenPageTag = "SDFM_DESIGN"; + +const cflags_pru = { + common: [ + "-v4", + "-DSDDF_PRU_CORE", + "-o2", + "--display_error_number", + "--hardware_mac=on", + ], +}; + +const lflags_pru = { + common: [ + "--disable_auto_rts", + "--define=SDDF_PRU_CORE=1", + "--warn_sections", + "--entry_point=SDDF_ENTRY", + "--zero_init=off", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru0", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, + +]; + + + +let postBuildStepsPru = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDDF_PRU0_image -o sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out; move sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/firmware/sdfm_bin.h;" +]; + + + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "sdfm_firmware"; + property.isInternal = false; + property.description = "ICSS SDFM" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.cflags = cflags_pru; + build_property.lflags = lflags_pru; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + build_property.postBuildSteps = postBuildStepsPru; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; \ No newline at end of file diff --git a/source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/example.projectspec b/source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..a978026 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile b/source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..66bc15d --- /dev/null +++ b/source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDDF_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM243X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${CG_TOOL_ROOT}/include" --include_path="${MCU_PLUS_SDK_PATH}/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile b/source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..17f4ec2 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/current_sense/sdfm/firmware/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDDF_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM64X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${CG_TOOL_ROOT}/include" --include_path="${MCU_PLUS_SDK_PATH}/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/current_sense/sdfm/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( 20 MHz SD clock, SD_CLK_INV==0 => No clock inversion +INIT_SDDF_CFG_SD_CLK .set (SD_PRD_CLOCKS << SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT) | (SD_CLK_INV << SDDF_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT) +; SD OC OSR=(13+1)=14 +INIT_SDDF_CFG_OSR .set (OC_OSR << SDDF_CFG_OC_OSR_BF_OSR_SHIFT) +; SD OC positive threshold = (OC OSR)^(OC SINC ORDER) = 14^3 = 2744 +INIT_SDDF_CFG_OC_POS_THR .set (OC_POS_THR << SDDF_CFG_OC_POS_THR_SHIFT) +; SD OC negative threshold = 1 +INIT_SDDF_CFG_OC_NEG_THR .set (OC_NEG_THR << SDDF_CFG_OC_NEG_THR_SHIFT) +; For SD samp freq==20e6, OSR==64, EPWM (FOC) loop freq = 8e3, sddf_setup_time=0 (TBD) & +; IEP freq = 300e6, IEP counter increment=1: +; (1/2*(1/8e3) - 3/2*(64/20e6) - 0)*300e6*1 = 17310 +; () +; +;for 16KHz (1/2*(1/16e3)-3/2*(64/20e6)-0)*300e6 = 7935 +;for +INIT_SDDF_CFG_TRIG_SAMP_TIME .set (TRIG_SAMP_TIME << SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT) +; Generate 3 NC samples after trigger +INIT_SDDF_CFG_TRIG_SAMP_CNT .set (TRIG_SAMP_CNT << SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT) +; IEP0 counts in NC sampling period: +; - IEP0 count = +; (NC OSR * SD clock period)*(IEP0 frequency * IEP default count) = +; (NC OSR * IEP0 frequency * IEP default count)/(SD clock frequency) = +; 64*300e6*1/20e6 = 960 +; for NC OSR = 128 +; 128*15 = 1920 +; 256*15 = 3840 +INIT_SDDF_CFG_NC_PRD_IEP_CNT .set (NC_PRD_IEP_CNT << SDDF_CFG_NC_PRD_IEP_CNT_SHIFT) +INIT_SDDF_CFG_OUT_SAMP_BUF .set (NC_OUT_SAMP_BUF << SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT) + + ; SDDF Firmware Registers + .sect ".fwRegs" + .retain ".fwRegs" + .retainrefs ".fwRegs" + .byte INIT_SDDF_CTRL + .byte INIT_SDDF_STAT + .byte INIT_IEP_CFG + .byte 0 ; RESERVED + .word INIT_IEP_CFG_CMP0_CNT_EPWM_PRD + .word INIT_SDDF_CFG_SD_CH_ID + .short INIT_SDDF_CFG_SD_CLK + .byte INIT_SDDF_CFG_OSR + .byte 0 ; RESERVED + .short INIT_SDDF_CFG_OC_POS_THR + .short INIT_SDDF_CFG_OC_NEG_THR + .word INIT_SDDF_CFG_TRIG_SAMP_TIME + .short INIT_SDDF_CFG_TRIG_SAMP_CNT + .short INIT_SDDF_CFG_NC_PRD_IEP_CNT + .word INIT_SDDF_CFG_OUT_SAMP_BUF diff --git a/source/motor_control/current_sense/sdfm/firmware/icssg_pru.cmd b/source/motor_control/current_sense/sdfm/firmware/icssg_pru.cmd new file mode 100644 index 0000000..1f8a10c --- /dev/null +++ b/source/motor_control/current_sense/sdfm/firmware/icssg_pru.cmd @@ -0,0 +1,94 @@ +/****************************************************************************/ +/* ICSSG_PRU.cmd */ +/* Copyright (c) 2023 Texas Instruments Incorporated */ +/* */ +/* Description: This file is a linker command file that can be used for */ +/* linking PRU programs built with the C compiler and */ +/* the resulting .out file on an pru device. */ +/****************************************************************************/ + +/* -cr */ /* Link using C conventions */ +/* -stack 0x100 */ + +/* Specify the System Memory Map */ +MEMORY +{ + PAGE 0: + PRU_IMEM : org = 0x00000000 len = 0x00004000 /* 16kB ICSSG_PRU Instruction RAM */ + + PAGE 1: + + /* RAM */ + PRU_FWREGS : org = 0x00000000 len = 0x00000080 + RTU_FWREGS : org = 0x00000080 len = 0x00000080 + PRU_DMEM_0_1_LOW : org = 0x00000100 len = 0x00000F00 /* 4kB ICSSG Data RAM 0_1 for PRU*/ + PRU_DMEM_0_1_HIGH : org = 0x00001000 len = 0x00001000 /* 4kB ICSSG Data RAM 0_1 for RTU*/ + PRU_DMEM_1_0 : org = 0x00002000 len = 0x00002000 /* 8kB ICSSG Data RAM 1_0 */ + + PAGE 2: + PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 /* 64kB Shared RAM */ + + /* Peripherals */ + + PRU_CFG : org = 0x00026000 len = 0x00000120 CREGISTER=4 + + RSVD0 : org = 0x00020000 len = 0x00001504 CREGISTER=0 + RSVD1 : org = 0x48040000 len = 0x0000005C CREGISTER=1 + RSVD2 : org = 0x4802A000 len = 0x000000D8 CREGISTER=2 + RSVD3 : org = 0x00030000 len = 0x00000060 CREGISTER=3 + RSVD5 : org = 0x48060000 len = 0x00000300 CREGISTER=5 + RSVD6 : org = 0x48030000 len = 0x000001A4 CREGISTER=6 + RSVD7 : org = 0x00028000 len = 0x00000038 CREGISTER=7 + RSVD8 : org = 0x46000000 len = 0x00000100 CREGISTER=8 + RSVD9 : org = 0x4A100000 len = 0x0000128C CREGISTER=9 + RSVD10 : org = 0x48318000 len = 0x00000100 CREGISTER=10 + RSVD11 : org = 0x48022000 len = 0x00000088 CREGISTER=11 + RSVD12 : org = 0x48024000 len = 0x00000088 CREGISTER=12 + RSVD13 : org = 0x48310000 len = 0x00000100 CREGISTER=13 + RSVD14 : org = 0x481CC000 len = 0x000001E8 CREGISTER=14 + RSVD15 : org = 0x481D0000 len = 0x000001E8 CREGISTER=15 + RSVD16 : org = 0x481A0000 len = 0x000001A4 CREGISTER=16 + RSVD17 : org = 0x4819C000 len = 0x000000D8 CREGISTER=17 + RSVD18 : org = 0x48300000 len = 0x000002C4 CREGISTER=18 + RSVD19 : org = 0x48302000 len = 0x000002C4 CREGISTER=19 + RSVD20 : org = 0x48304000 len = 0x000002C4 CREGISTER=20 + RSVD21 : org = 0x00032400 len = 0x00000100 CREGISTER=21 + RSVD22 : org = 0x480C8000 len = 0x00000140 CREGISTER=22 + RSVD23 : org = 0x480CA000 len = 0x00000880 CREGISTER=23 + RSVD26 : org = 0x0002E000 len = 0x0000031C CREGISTER=26 + RSVD27 : org = 0x00032000 len = 0x00000100 CREGISTER=27 + RSVD29 : org = 0x49000000 len = 0x00001098 CREGISTER=29 +} + +/* Specify the sections allocation into memory */ +SECTIONS { + /* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading + an ELF file, but useful when loading a binary */ + /* .text:_c_int00* > 0x0, PAGE 0 */ + + /* .text > PRU_IMEM, PAGE 0 */ + /* .stack > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .bss > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .cio > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .data > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .switch > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .sysmem > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .cinit > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .rodata > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .rofardata > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .farbss > PRU_DMEM_0_1_LOW, PAGE 1 */ + /* .fardata > PRU_DMEM_0_1_LOW, PAGE 1 */ + + .text > PRU_IMEM, PAGE 0 +#if defined (SDDF_PRU_CORE) + .fwRegs > PRU_FWREGS, PAGE 1 + .data > PRU_DMEM_0_1_LOW, PAGE 1 + .outSamps > PRU_DMEM_0_1_LOW, PAGE 1 +#else + .fwRegs > RTU_FWREGS , PAGE 1 + .data > PRU_DMEM_0_1_HIGH, PAGE 1 + .outSamps > PRU_DMEM_0_1_HIGH, PAGE 1 +#endif + + .dbgBuf > PRU_SHAREDMEM, PAGE 2 +} diff --git a/source/motor_control/current_sense/sdfm/firmware/icssg_sddf.h b/source/motor_control/current_sense/sdfm/firmware/icssg_sddf.h new file mode 100644 index 0000000..00d16a0 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/firmware/icssg_sddf.h @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ICSS_SDDF_H_ +#define _ICSS_SDDF_H_ + +/* Number of SDDF channels per PRU */ +#define ICSSG_NUM_SD_CH ( 9 ) +/* Number of SDDF channels supported by PRU FW */ +#define ICSSG_NUM_SD_CH_FW ( 3 ) + +/* ICSSG INTC events */ +/* Compile-time Host event for SDDF samples available. + Ideally Host would provide this to FW via pseudo-register in DMEM. */ +#define PRU_TRIGGER_HOST_SDDF_EVT ( 2+16 ) /* pr0_pru_mst_intr[2]_intr_req */ +#define RTU_TRIGGER_HOST_SDDF_EVT ( 3+16 ) /* pr0_pru_mst_intr[3]_intr_req */ + + +/* + Firmware registers +*/ + +/* FW register base addresses */ +#define PRU_ICSSG_SDDF_CTRL_BASE ( 0x0000 ) +#define PRU_ICSSG_SDDF_CFG_BASE ( 0x0002 ) +#define RTU_ICSSG_SDDF_CTRL_BASE ( 0x0080 ) +#define RTU_ICSSG_SDDF_CFG_BASE ( 0x0082 ) + +#if defined (SDDF_PRU_CORE) +/* SDDF Control */ +#define ICSSG_SDDF_CTRL_BASE ( PRU_ICSSG_SDDF_CTRL_BASE ) +/* SDDF Configuration */ +#define ICSSG_SDDF_CFG_BASE ( PRU_ICSSG_SDDF_CFG_BASE ) +#elif defined (SDDF_RTU_CORE) +/* SDDF Control */ +#define ICSSG_SDDF_CTRL_BASE ( RTU_ICSSG_SDDF_CTRL_BASE ) +/* SDDF Configuration */ +#define ICSSG_SDDF_CFG_BASE ( RTU_ICSSG_SDDF_CFG_BASE ) +#else +#endif + +/* FW register sizes (in bytes) */ +/* SDDF Control */ +#define FW_REG_SDDF_CTRL_SZ ( 1 ) +#define FW_REG_SDDF_STAT_SZ ( 1 ) + +/* SDDF Configuration */ +#define FW_REG_SDDF_CFG_IEP_CFG_SZ ( 1 ) +#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_SZ ( 4 ) +#define FW_REG_SDDF_CFG_SD_CH_ID_SZ ( 4 ) +#define FW_REG_SDDF_CFG_SD_CLK_SZ ( 2 ) +#define FW_REG_SDFM_CFG_OSR_SZ ( 1 ) +#define FW_REG_SDFM_CFG_EN_COMP_SZ ( 2 ) +#define FW_REG_SDFM_CFG_OC_HIGH_THR_SZ ( 2 ) +#define FW_REG_SDFM_CFG_OC_LOW_THR_SZ ( 2 ) +#define FW_REG_SDFM_CFG_ZC_ENABLE_SZ ( 2 ) +#define FW_REG_SDFM_CFG_ZC_THR_SZ ( 4 ) +#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_SZ ( 1 ) +#define FW_REG_SDFM_CFG_ZC_PREV_VAL_SZ ( 4 ) +#define FW_REG_SDDF_CFG_OSR_SZ ( 1 ) +#define FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_SZ ( 4 ) +#define FW_REG_SDDF_CFG_TRIG_SAMPLE_CNT_SZ ( 2 ) +#define FW_REG_SDDF_CFG_NC_PRD_IEP_CNT_SZ ( 2 ) +#define FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_SZ ( 2 ) +#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_SZ ( 4 ) +#define FW_REG_SDDF_CFG_OUT_SAMP_BUF_SZ ( 4 ) +#define FW_REG_SDFM_CFG_GPIO_VALUE_SZ ( 4 ) +#define FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ ( 4 ) +#define FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ ( 4 ) +#define FW_REG_SDFM_CFG_CURR_VAL_SZ ( 4 ) + +/* FW register offsets from base (in bytes) */ +/* SDDF Control */ +#define FW_REG_SDDF_CTRL_OFFSET ( 0x00 ) +#define FW_REG_SDDF_STAT_OFFSET ( 0x01 ) + +/* SDDF Configuration */ +#define FW_REG_SDDF_CFG_IEP_CFG_OFFSET ( 0x00 ) +#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_OFFSET ( 0x06 ) +#define FW_REG_SDDF_CFG_SD_CLK_OFFSET ( 0x0A ) +#define FW_REG_SDDF_CFG_SD_CH_ID_OFFSET ( 0x0E ) +#define FW_REG_SDFM_CFG_SD_EN_COMP_OFFSET ( 0x12 ) +#define FW_REG_SDFM_CFG_SD_ZC_ENABLE_OFFSET ( 0x16 ) +#define FW_REG_SDFM_CFG_ZC_START_SZ ( 0x18 ) + +/*SDFM channel offsets*/ +/*ch0 offset*/ +#define FW_REG_SDDF_CFG_CH0_CH_ID_OFFSET ( 0x1A ) +#define FW_REG_SDDF_CFG_CH0_FILTER_TYPE_OFFSET ( 0x1B ) +#define FW_REG_SDDF_CFG_CH0_OSR_OFFSET ( 0x1C ) +#define FW_REG_SDFM_CFG_OC_HIGH_THR_CH0_OFFSET ( 0x1E ) +#define FW_REG_SDFM_CFG_OC_LOW_THR_CH0_OFFSET ( 0x22 ) +#define FW_REG_SDFM_CFG_OC_ZC_THR_CH0_OFFSET ( 0x26 ) +#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_CH0_OFFSET ( 0x2A ) +#define SDFM_CFG_ZC_CH0_PREV_VAL_OFFSET ( 0x2E ) +#define FW_REG_SDDF_CFG_CH0_CLOCK_SOURCE_OFFSET ( 0x32 ) +#define FW_REG_SDDF_CFG_CH0_CLOCK_INVERSION_OFFSET ( 0x36 ) +#define SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET ( 0x3A ) +#define SDFM_CFG_HIGH_THR_CH0_SET_VAL_ADDR_OFFSET ( 0x3E ) +#define SDFM_CFG_HIGH_THR_CH0_CLR_VAL_ADDR_OFFSET ( 0x42 ) +#define SDFM_CFG_LOW_THR_CH0_WRITE_VAL_OFFSET ( 0x46 ) +#define SDFM_CFG_LOW_THR_CH0_SET_VAL_ADDR_OFFSET ( 0x4A ) +#define SDFM_CFG_LOW_THR_CH0_CLR_VAL_ADDR_OFFSET ( 0x4E ) +#define SDFM_CFG_ZC_THR_CH0_WRITE_VAL_OFFSET ( 0x52 ) +#define SDFM_CFG_ZC_THR_CH0_SET_VAL_ADDR_OFFSET ( 0x56 ) +#define SDFM_CFG_ZC_THR_CH0_CLR_VAL_ADDR_OFFSET ( 0x5A ) + +/*ch1 offsets*/ +#define FW_REG_SDDF_CFG_CH1_CH_ID_OFFSET ( 0x5E ) +#define FW_REG_SDDF_CFG_CH1_FILTER_TYPE_OFFSET ( 0x5F ) +#define FW_REG_SDDF_CFG_CH1_OSR_OFFSET ( 0x60 ) +#define FW_REG_SDFM_CFG_OC_HIGH_THR_CH1_OFFSET ( 0x62 ) +#define FW_REG_SDFM_CFG_OC_LOW_THR_CH1_OFFSET ( 0x66 ) +#define FW_REG_SDFM_CFG_OC_ZC_THR_CH1_OFFSET ( 0x6A ) +#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_CH1_OFFSET ( 0x6E ) +#define SDFM_CFG_ZC_CH1_PREV_VAL_OFFSET ( 0x72 ) +#define FW_REG_SDDF_CFG_CH1_CLOCK_SOURCE_OFFSET ( 0x76 ) +#define FW_REG_SDDF_CFG_CH1_CLOCK_INVERSION_OFFSET ( 0x7A ) +#define SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET ( 0x7E ) +#define SDFM_CFG_HIGH_THR_CH1_SET_VAL_ADDR_OFFSET ( 0x82 ) +#define SDFM_CFG_HIGH_THR_CH1_CLR_VAL_ADDR_OFFSET ( 0x86 ) +#define SDFM_CFG_LOW_THR_CH1_WRITE_VAL_OFFSET ( 0x8A ) +#define SDFM_CFG_LOW_THR_CH1_SET_VAL_ADDR_OFFSET ( 0x8E ) +#define SDFM_CFG_LOW_THR_CH1_CLR_VAL_ADDR_OFFSET ( 0x92 ) +#define SDFM_CFG_ZC_THR_CH1_WRITE_VAL_OFFSET ( 0x96 ) +#define SDFM_CFG_ZC_THR_CH1_SET_VAL_ADDR_OFFSET ( 0x9A ) +#define SDFM_CFG_ZC_THR_CH1_CLR_VAL_ADDR_OFFSET ( 0x9E ) + + +/*ch2 offsets*/ +#define FW_REG_SDDF_CFG_CH2_CH_ID_OFFSET ( 0xA2 ) +#define FW_REG_SDDF_CFG_CH2_FILTER_TYPE_OFFSET ( 0xA3 ) +#define FW_REG_SDDF_CFG_CH2_OSR_OFFSET ( 0xA4 ) +#define FW_REG_SDFM_CFG_OC_HIGH_THR_CH2_OFFSET ( 0xA6 ) +#define FW_REG_SDFM_CFG_OC_LOW_THR_CH2_OFFSET ( 0xAA ) +#define FW_REG_SDFM_CFG_OC_ZC_THR_CH2_OFFSET ( 0xAE ) +#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_CH2_OFFSET ( 0xB2 ) +#define SDFM_CFG_ZC_CH2_PREV_VAL_OFFSET ( 0xB6 ) +#define FW_REG_SDDF_CFG_CH2_CLOCK_SOURCE_OFFSET ( 0xBA ) +#define FW_REG_SDDF_CFG_CH2_CLOCK_INVERSION_OFFSET ( 0xBE ) +#define SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET ( 0xC2 ) +#define SDFM_CFG_HIGH_THR_CH2_SET_VAL_ADDR_OFFSET ( 0xC6 ) +#define SDFM_CFG_HIGH_THR_CH2_CLR_VAL_ADDR_OFFSET ( 0xCA ) +#define SDFM_CFG_LOW_THR_CH2_WRITE_VAL_OFFSET ( 0xCE ) +#define SDFM_CFG_LOW_THR_CH2_SET_VAL_ADDR_OFFSET ( 0xD2 ) +#define SDFM_CFG_LOW_THR_CH2_CLR_VAL_ADDR_OFFSET ( 0xD6 ) +#define SDFM_CFG_ZC_THR_CH2_WRITE_VAL_OFFSET ( 0xDA) +#define SDFM_CFG_ZC_THR_CH2_SET_VAL_ADDR_OFFSET ( 0xDE ) +#define SDFM_CFG_ZC_THR_CH2_CLR_VAL_ADDR_OFFSET ( 0xE2 ) + +/*sample timing offset*/ +#define FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_OFFSET ( 0xE6 ) +#define FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_OFFSET ( 0xEA ) +#define FW_REG_SDDF_CFG_NC_PRD_IEP_CNT_OFFSET ( 0xEC ) +#define FW_REG_SDDF_CFG_SAMPLE_COUNT ( 0xEE ) +/*Sample output offset*/ +#define FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET ( 0xF2 ) + + +/*Debug Offset */ +#define DUBG_OFFSET (0x110) + +/* FW register addresses */ + +/* Sigma Delta Filter Control */ +#define FW_REG_SDDF_CTRL ( ICSSG_SDDF_CTRL_BASE + FW_REG_SDDF_CTRL_OFFSET ) +/* Sigma Delta Filter Status */ +#define FW_REG_SDDF_STAT ( ICSSG_SDDF_CTRL_BASE + FW_REG_SDDF_STAT_OFFSET ) + +/* Sigma Delta Filter Configuration, IEP configuration */ +#define FW_REG_SDDF_CFG_IEP_CFG ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_IEP_CFG_OFFSET ) +/* Sigma Delta Filter Configuration, IEP CMP0 count for simulated EPWM period */ +#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_OFFSET ) +/* Sigma Delta Filter Configuration, SD channel IDs */ +#define FW_REG_SDDF_CFG_SD_CH_ID ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_SD_CH_ID_OFFSET ) +/* Sigma Delta Filter Configuration, SD clock */ +#define FW_REG_SDDF_CFG_SD_CLK ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_SD_CLK_OFFSET ) +/* Sigma Delta Filter Configuration, OSR */ +#define FW_REG_SDDF_CFG_OSR ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OSR_OFFSET ) +/* Sigma Delta Filter Configuration, positive threshold for OC detect */ +#define FW_REG_SDDF_CFG_OC_POS_THR ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OC_POS_THR_OFFSET ) +/* Sigma Delta Filter Configuration, negative threshold for OC detect */ +#define FW_REG_SDDF_CFG_OC_NEG_THR ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OC_NEG_THR_OFFSET ) +/* Sigma Delta Filter Configuration, Trigger Sample Time */ +#define FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_OFFSET ) +/* Sigma Delta Filter Configuration, Trigger Sample Count */ +#define FW_REG_SDDF_CFG_OC_PRD_IEP_CNT ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_OFFSET ) +/* Sigma Delta Filter Configuration, NC sampling period IEP counts */ +#define FW_REG_SDDF_CFG_NC_PRD_IEP_CNT ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_NC_PRD_IEP_CNT_OFFSET ) +/* Sigma Delta Filter Configuration, Host Sample Output Buffer */ +#define FW_REG_SDDF_CFG_OUT_SAMP_BUF ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET ) + +/* + Firmware register bit fields +*/ + +/* SDDF_CTRL */ +#define BF_SDDF_EN_MASK ( 0x1 ) +#define BF_PRU_ID_MASK ( 0x3 ) +#define SDDF_CTRL_BF_SDDF_EN_SHIFT ( 0 ) +#define SDDF_CTRL_BF_SDDF_EN_MASK ( BF_SDDF_EN_MASK << SDDF_CTRL_BF_SDDF_EN_SHIFT ) +#define SDDF_CTRL_BF_PRU_ID_SHIFT ( 1 ) +#define SDDF_CTRL_BF_PRU_ID_MASK ( BF_PRU_ID_MASK << SDDF_CTRL_BF_PRU_ID_SHIFT ) +/* SDDF_EN bit field */ +#define BF_SDDF_EN_DISABLE ( 0 ) +#define BF_SDDF_EN_ENABLE ( 1 ) +/* PRU ID bit field */ +#define BF_PRU_ID_0 ( 0 ) +#define BR_PRU_ID_1 ( 1 ) +#define BF_PRU_ID_UNINIT ( 2 ) + +/* SDDF_STAT */ +#define BF_SDDF_EN_ACK_MASK ( 0x1 ) +#define BF_PRU_ID_ACK_MASK ( 0x3 ) +#define SDDF_STAT_BF_SDDF_EN_ACK_SHIFT ( 0 ) +#define SDDF_STAT_BF_SDDF_EN_ACK_MASK ( BF_SDDF_EN_ACK_MASK << SDDF_STAT_BF_SDDF_EN_ACK_SHIFT ) +#define SDDF_STAT_BF_PRU_ID_ACK_SHIFT ( 1 ) +#define SDDF_STAT_BF_PRU_ID_ACK_MASK ( BF_PRU_ID_ACK_MASK << SDDF_STAT_BF_PRU_ID_ACK_SHIFT ) + +/* IEP_CFG */ +#define BF_IEP_DEFAULT_INC_MASK ( 0xF ) +#define IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT ( 0 ) +#define IEP_CFG_BF_IEP_DEFAULT_INC_MASK ( BF_IEP_DEFAULT_INC_MASK << IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT ) + +/* IEP_CFG_EPWM_PRD */ +#define BF_CMP0_CNT_EPWM_PRD_MASK ( 0xFFFFFFFF ) +#define IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT ( 0 ) +#define IEP_CFG_BF_CMP0_CNT_EPWM_PRD_MASK ( BF_CMP0_CNT_EPWM_PRD_MASK << IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT ) + +/* SDDF_CFG_SD_CH_ID */ +#define BF_SD_CH0_ID_MASK ( 0xF ) +#define BF_SD_CH1_ID_MASK ( 0xF ) +#define BF_SD_CH2_ID_MASK ( 0xF ) +#define SDDF_CFG_BF_SD_CH0_ID_SHIFT ( 0 ) +#define SDDF_CFG_BF_SD_CH1_ID_SHIFT ( 4 ) +#define SDDF_CFG_BF_SD_CH2_ID_SHIFT ( 8 ) +#define SDDF_CFG_BF_SD_CH0_ID_MASK ( BF_SD_CH0_ID_MASK << SDDF_CFG_BF_SD_CH0_ID_SHIFT ) +#define SDDF_CFG_BF_SD_CH1_ID_MASK ( BF_SD_CH1_ID_MASK << SDDF_CFG_BF_SD_CH1_ID_SHIFT ) +#define SDDF_CFG_BF_SD_CH2_ID_MASK ( BF_SD_CH2_ID_MASK << SDDF_CFG_BF_SD_CH2_ID_SHIFT ) + +/* SDDF_CFG_SD_CLK */ +#define BF_SD_PRD_CLOCKS_MASK ( 0xFF ) +#define BF_SD_CLK_INV_MASK ( 0x1 ) +#define SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT ( 0 ) +#define SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_MASK ( BF_SD_PRD_CLOCKS_MASK << SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT ) +#define SDDF_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT ( 8 ) +#define SDDF_CFG_SD_CLK_BF_SD_CLK_INV_MASK ( BF_SD_CLK_INV_MASK << SDDF_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT ) + +/* SDDF_CFG_OSR */ +#define BF_OC_OSR_MASK ( 0xFF ) +#define SDDF_CFG_OC_OSR_BF_OSR_SHIFT ( 0 ) +#define SDDF_CFG_OC_OSR_BF_OSR_MASK ( BF_OC_OSR_MASK << SDDF_CFG_OC_OSR_BF_OSR_SHIFT ) + +/* SDDF_CFG_OC_POS_THR */ +#define BF_OC_POS_THR_MASK ( 0xFF ) +#define SDDF_CFG_OC_POS_THR_SHIFT ( 0 ) +#define SDDF_CFG_OC_POS_THR_MASK ( BF_OC_POS_THR_MASK << SDDF_CFG_OC_POS_THR_SHIFT ) + +/* SDDF_CFG_OC_NEG_THR */ +#define BF_OC_NEG_THR_MASK ( 0xFF ) +#define SDDF_CFG_OC_NEG_THR_SHIFT ( 0 ) +#define SDDF_CFG_OC_NEG_THR_MASK ( BF_OC_NEG_THR_MASK << SDDF_CFG_OC_NEG_THR_SHIFT ) + +/* SDFM_CFG_SD_EN_COMP */ +#define SDFM_CFG_BF_SD_CH0_EN_COMP_BIT ( 0x00 ) +#define SDFM_CFG_BF_SD_CH1_EN_COMP_BIT ( 0x01 ) +#define SDFM_CFG_BF_SD_CH2_EN_COMP_BIT ( 0x02 ) + +/* SDFM_CFG_ZC_ENABLE */ +#define SDFM_CFG_BF_SD_CH0_ZC_ENABLE_BIT ( 0x00 ) +#define SDFM_CFG_BF_SD_CH1_ZC_ENABLE_BIT ( 0x01 ) +#define SDFM_CFG_BF_SD_CH2_ZC_ENABLE_BIT ( 0x02 ) + + +/* SDFM_CFG_ZC_START */ +#define SDFM_CFG_BF_SD_CH0_ZC_START_BIT ( 0x00 ) +#define SDFM_CFG_BF_SD_CH1_ZC_START_BIT ( 0x01 ) +#define SDFM_CFG_BF_SD_CH2_ZC_START_BIT ( 0x02 ) + + +/* SDFM_CFG_TRIP_STATUS */ +#define SDFM_CFG_BF_SD_TRIP_STATUS_HIGH ( 0x01 ) +#define SDFM_CFG_BF_SD_TRIP_STATUS_LOW ( 0x00 ) + + +/* SDDF_CFG_TRIG_SAMP_TIME */ +#define BF_TRIG_SAMP_TIME_MASK ( 0xFFFF ) +#define SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT \ + ( 0 ) +#define SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_MASK \ + ( BF_TRIG_SAMP_TIME_MASK << SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT ) + +/* SDDF_CFG_TRIG_SAMPLE_CNT */ +#define BF_TRIG_SAMP_CNT_MASK ( 0xFFFF ) +#define SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT \ + ( 0 ) +#define SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_MASK \ + ( BF_TRIG_SAMP_CNT_MASK << SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT ) + +/* SDDF_CFG_NC_PRD_IEP_CNT */ +#define BF_NC_PRD_IEP_CNT_MASK ( 0xFF ) +#define SDDF_CFG_NC_PRD_IEP_CNT_SHIFT ( 0 ) +#define SDDF_CFG_NC_PRD_IEP_CNT_MASK ( BF_NC_PRD_IEP_CNT_MASK << SDDF_CFG_NC_PRD_IEP_CNT_SHIFT ) + +/* SDDF_CFG_NC_OUT_SAMP_BUF */ +#define BF_NC_OUT_SAMP_BUF_MASK ( 0xFFFF ) +#define SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT \ + ( 0 ) +#define SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_MASK \ + ( BF_NC_OUT_SAMP_BUF_MASK << SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT ) + +#endif \ No newline at end of file diff --git a/source/motor_control/current_sense/sdfm/firmware/sddf.asm b/source/motor_control/current_sense/sdfm/firmware/sddf.asm new file mode 100644 index 0000000..6c71253 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/firmware/sddf.asm @@ -0,0 +1,885 @@ +; +; Copyright (c) 2023, Texas Instruments Incorporated +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; +; * Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + + .cdecls C,NOLIST +%{ + #include "icssg_sddf.h" +%} + .include "sddf_cfg.h" + .include "sddf.h" + .include "sddf_macros.h" + + +; Compile-time Host event for SDDF samples available +; R31 event interface mapping, add pru_r31_vec_valid to system event number, + 1<<5 + .if $isdefed("SDDF_PRU_CORE") +TRIGGER_HOST_SDDF_IRQ .set PRU_TRIGGER_HOST_SDDF_EVT + 16 + .elseif $isdefed("SDDF_RTU_CORE") +TRIGGER_HOST_SDDF_IRQ .set RTU_TRIGGER_HOST_SDDF_EVT + 16 + .endif + +;SPAD Bank for SD Ch context storage +BANK_CTXT_NC .set BANK0 +BANK_CTXT_OC .set BANK1 +;differentiator state located in BANK locations 9-17 +NUM_REGS_DIFF_STATE .set 9 ; Number of PRU registers for differentiator state +OUT_SAMP_MASK .set 0x0FFFFFFF ; 28-bit mask applied to Integrator & Differentiator output + + +;registers R20 - R24 +;R20: contain address of NC local output +;R21; output mask +;R22.w0 channel ID +;R22.W1 required OC Sample count for NC +;R23 DMEM base address + (0x02) +;R24 PRUx CFG base address + + + ; local interleaved NC output sample buffer +OUT_SAMP_BUF: .usect ".outSamps", ICSSG_NUM_SD_CH_FW*4, 4 + .retain ".outSamps" + .retainrefs ".outSamps" + + .def SDDF_ENTRY ; global entry point + .ref dbg_setup_pinmux + + .sect ".text" + .retain ".text" + .retainrefs ".text" +SDDF_ENTRY: + ; Clear registers R0-R30 + ZERO &R0, 124 + + ; Disable Task Manager + .word 0x32000000 + + ; Clear Task Manager status which is sticky after debug halt + LDI TREG0.w0, 0x0fff + SBCO &TREG0.w0, CT_PRU_ICSSG_TM, 0, 2 + XIN TM_YIELD_XID, &R0.b3,1 + LDI TREG0.w0, 0 + SBCO &TREG0.w0, CT_PRU_ICSSG_TM, 0, 2 + + + ; Write C24 block index for access to FW registers + WRITE_C24_BLK_INDEX C24_BLK_INDEX_FW_REGS_VAL + +; +; Check PRU ID & set PRU ID acknowledge +; +check_pru_id: + ; Wait for Host to update PRU ID + LBCO &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CTRL, FW_REG_SDDF_CTRL_SZ ; Load TR0.b0 <- FW_REG_SDDF_CTRL + AND TREG0.b0, TREG0.b0, SDDF_CTRL_BF_PRU_ID_MASK ; Mask PRU_ID bit field in TR0.b0 + LDI TREG1.b0, BF_PRU_ID_UNINIT< FW_REG_SDDF_STAT + +; +; Check SDDF global enable & set SDDF global enable acknowledge. +; If SDDF global enable not set, allow re-selection of PRU ID. +; +check_sddf_en: + ; Check SDDF global enable + LBCO &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CTRL, FW_REG_SDDF_CTRL_SZ ; Load TR0.b0 <- FW_REG_SDDF_CTRL + QBBC check_pru_id, TREG0.b0, SDDF_CTRL_BF_SDDF_EN_SHIFT ; If SDDF_EN not set, re-check PRU_ID + + ; Set SDDF global enable acknowledge + LBCO &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_STAT, FW_REG_SDDF_STAT_SZ ; Load TR0.b0 <- FW_REG_SDDF_STAT + SET TREG0, TREG0, SDDF_CTRL_BF_SDDF_EN_SHIFT ; Set SDDF_EN_ACK bit + SBCO &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_STAT, FW_REG_SDDF_STAT_SZ ; Store FW_REG_SDDF_STAT -> TR0.b0 + +; +; Perform initialization +; +init_sddf: + ; Enable XIN/XOUT shifting. + ; Used for context & SD state save/restore in TM tasks. + LBCO &TREG0.b0, CT_PRU_ICSSG_CFG, ICSSG_CFG_SPPC, 1 + .if $isdefed("SDDF_PRU_CORE") + SET TREG0, TREG0, XFR_SHIFT_EN_BN ; ICSSG_SPP_REG:XFR_SHIFT_EN=1 + .elseif $isdefed("SDDF_RTU_CORE") + SET TREG0, TREG0, RTU_XFR_SHIFT_EN ; ICSSG_SPP_REG:RTU_XFR_SHIFT_EN=1 + .endif + SBCO &TREG0.b0, CT_PRU_ICSSG_CFG, ICSSG_CFG_SPPC, 1 + + ; Initialize Task Manager + JAL RET_ADDR_REG, tm_init + + ; Enable Task Manager + .word 0x32800000 + + .if $isdefed("SDDF_PRU_CORE") ; no IEP on RTU + ; Initialize IEP0 + JAL RET_ADDR_REG, iep0_init + .endif + + + ; Initialize SD mode + LDI32 TREG1, PR1_PRUn_GP_MUX_SEL_VAL<_pru_r31_in[16] Primary Input + JAL RET_ADDR_REG, config_sd_ch + + ; Global enable SD HW, + ; reset SD channel HW + JAL RET_ADDR_REG, reset_sd_ch_hw + SET R30.t25 ; R30[25] channel_en = 1, all channels enabled + + ; Initialize dedicated registers: + ; MASK register, + ; Local NC output sample buffer address, + ; clear sample count + LDI32 MASK_REG, OUT_SAMP_MASK + LDI32 OUT_SAMP_BUF_REG, OUT_SAMP_BUF + LDI SAMP_CNT_REG, 0 + + .if $isdefed("SDDF_PRU_CORE") ; no IEP on RTU + ; Start IEP + LBCO &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1 + SET TREG0, TREG0, CNT_ENABLE_BN ; ICSSG_IEP_GLOBAL_CFG_REG:CNT_ENABLE=1 + SBCO &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1 + .endif + + ; Generate OC output samples + ; + ; TR0.b0: ch ID + ; TR0.b1: channel ID FW register shift amount + ; TR0.w2: channel ID FW register + + ; Load TR0.w1 <- SDDF_CFG_SD_CH_ID + ;LBBO &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ + LBBO &SD_CH_ID, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ + ;LDI TREG0.b1, 0 ; init Ch ID shift + ;LDI TREG1.w2, 0 ; init OC detect count + +Waitloop: + JMP Waitloop + + + +ts1_oc_loop: + + + ; Save/restore context + ; restore differentiator state(R9-R17) + xchg BANK_CTXT_OC, &R9, 4*NUM_REGS_DIFF_STATE + + ; Clear IEP0 CMP4 events + .if $isdefed("SDDF_PRU_CORE") + LDI TREG0.b0, 0x10 + SBCO &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1 + .endif + + .if $isdefed("DEBUG_CODE") + ;Debug code :GPIO HIGH + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + ;debug code end + .endif + + ; update IEP0 CMP4 + .if $isdefed("SDDF_PRU_CORE") + LDI TREG0,0 + LBCO &TREG0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_OC_PRD_IEP_CNT, FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_SZ + LBCO &TREG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4 ; + MOV CURRENT_COMP4_REG_VALUE, TREG1 ; store current cmp4 register value for check time trigger + ADD TREG0, TREG1, TREG0 + ;read iep counter maximum value + LDI TREG1, 0 + LBCO &TREG1, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD, 2 + QBLE UPDATE_CMP4_FOR_IEP_RESET, TREG0, TREG1 + ;update Cmp4 with old value + next sample time value + SBCO &TREG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4 + JMP END_CMP4_UPDATE +UPDATE_CMP4_FOR_IEP_RESET: + ;Update cmp4 according to iep reset + SUB TREG0, TREG0, TREG1 + SBCO &TREG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4 + +END_CMP4_UPDATE: + .endif + + ;select ch0, enable all channel, set SD snoop=1 & sample_counter_select=1 + LDI R30.w2, (SD_CH0_ID<<10 | 1<<9 | 1<<6 | 1<<5) + NOP + + ; Snoop read Ch0 sample_counter, + ; wait for ChX sample count+1. + AND TREG1, R31, 0xFF ; snoop read LSB Ch0 sample_counter +wait_sample_count_incr_oc: + AND TREG2, R31, 0xFF ; snoop read LSB Ch0 sample_counter + QBEQ wait_sample_count_incr_oc, TREG2, TREG1 + + ; Snoop read Ch0 ACC3 + CLR R30.t21 ; set SD sample_counter_select=0 + NOP + AND TREG0, R31, MASK_REG ; TREG0 = Ch0 SD HW ACC3 output sample + CLR R30.t22 ; set SD snoop=0 + + ;select ch1, enable all channel & set SD snoop=1 + LDI R30.w2, (SD_CH1_ID<<10 | 1<<9 | 1<<6) + NOP + + ; Snoop read ACC3 for SD Ch1 + AND TREG1, R31, MASK_REG ; TREG1 = Ch1 SD HW ACC3 output sample + CLR R30.t22 ; set SD snoop=0 + + ;select ch2, enable all channel & set SD snoop=1 + LDI R30.w2, (SD_CH2_ID<<10 | 1<<9 | 1<<6) + NOP + + ; Snoop read ACC3 for SD Ch2 + AND TREG2, R31, MASK_REG ; TREG2 = Ch2 SD HW ACC3 output sample + CLR R30.t22 ; set SD snoop=0 + + ;NC sampling + ;One NC sample after every NC_PRD_CNT number of OC sample because NC OSR = NC_PRD_CNT * OC_OSR + ;read NC_PRD_CNT + LDI TREG3, 0 + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SAMPLE_COUNT, 2 + SUB TREG3, TREG3, 1 + QBLE read_nc_frame, SAMP_CNT_REG, TREG3 + ADD SAMP_CNT_REG, SAMP_CNT_REG, 1 ; increment OC sample count + QBA skip_nc_frame +read_nc_frame: + + .if $isdefed("DEBUG_CODE") + ;Debug code :GPIO HIGH + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + ;debug code end + .endif + + ; restore differentiator state(R9-R17) + xchg BANK_CTXT_NC, &R9, 4*NUM_REGS_DIFF_STATE + + ; Execute SINC3 differentiation for Ch0 + MOV DN0, TREG0 ; DN0 = Ch1 SD HW ACC3 output sample + M_ACC3_PROCESS ACC3_DN1_CH0, ACC3_DN3_CH0, ACC3_DN5_CH0 + ; Save NC output sample to local output sample buffer + SBBO &CN5, OUT_SAMP_BUF_REG, 0, 4 + + + ; Execute SINC3 differentiation for Ch1 + MOV DN0, TREG1 ; DN0 = Ch1 SD HW ACC3 output sample + M_ACC3_PROCESS ACC3_DN1_CH1, ACC3_DN3_CH1, ACC3_DN5_CH1 + ; Save output sample to local output sample buffer + SBBO &CN5, OUT_SAMP_BUF_REG, 4, 4 + + ; Execute SINC3 differentiation for Ch2 + MOV DN0, TREG2 ; DN0 = Ch2 SD HW ACC3 output sample + M_ACC3_PROCESS ACC3_DN1_CH2, ACC3_DN3_CH2, ACC3_DN5_CH2 + ; Save output sample to local output sample buffer + SBBO &CN5, OUT_SAMP_BUF_REG, 8, 4 + + + .if $isdefed("DEBUG_CODE") + ;Debug code + ; Write local interleaved output samples to Host buffer address + LBBO &TREG3, OUT_SAMP_BUF_REG, 0, ICSSG_NUM_SD_CH_FW*4 + SBBO &TREG3, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET, ICSSG_NUM_SD_CH_FW*4 + ; Trigger interrupt + LDI R31.w0, TRIGGER_HOST_SDDF_IRQ + .endif + + + ;sample read + LBCO &TREG3, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME, FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_SZ + QBLE sample_time_before_sample, CURRENT_COMP4_REG_VALUE, TREG3 + SUB CURRENT_COMP4_REG_VALUE, TREG3, CURRENT_COMP4_REG_VALUE + LBCO &TREG3, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_NC_PRD_IEP_CNT, FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_SZ + ;LDI TREG3, 0x780 + LSR TREG3, TREG3, 1 + QBGE skip_sample_read, TREG3, CURRENT_COMP4_REG_VALUE + QBA trigger_intruppt +sample_time_before_sample: + SUB CURRENT_COMP4_REG_VALUE, CURRENT_COMP4_REG_VALUE, TREG3 + LBCO &TREG3, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_NC_PRD_IEP_CNT, FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_SZ + ;LDI TREG3, 0x780 + LSR TREG3, TREG3, 1 + QBLE skip_sample_read, CURRENT_COMP4_REG_VALUE, TREG3 + QBA trigger_intruppt +trigger_intruppt: + + .if $isdefed("DEBUG_CODE") + ;GPIO HIGH + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + .endif + ; Write local interleaved output samples to Host buffer address + LBBO &TREG3, OUT_SAMP_BUF_REG, 0, ICSSG_NUM_SD_CH_FW*4 + SBBO &TREG3, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET, ICSSG_NUM_SD_CH_FW*4 + ; Trigger interrupt + LDI R31.w0, TRIGGER_HOST_SDDF_IRQ + + .if $isdefed("DEBUG_CODE") + ;GPIO LOW + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + .endif + +skip_sample_read: + + + + ;restore/save contex + ;save differentiator state(R9-R17) + xchg BANK_CTXT_NC, &R9, 4*NUM_REGS_DIFF_STATE + + .if $isdefed("DEBUG_CODE") + ;GPIO LOW + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + .endif + + LDI SAMP_CNT_REG, 0 ; reset sample count +skip_nc_frame: + + ; Execute SINC3 differentiation for Ch0 + MOV DN0, TREG0 ; DN0 = Ch1 SD HW ACC3 output sample + MOV TREG0, TREG1 ;move Ch1 data into TREG0 + MOV TREG1, TREG2 ; Move ch2 data into TREG1 + M_ACC3_PROCESS ACC3_DN1_CH0, ACC3_DN3_CH0, ACC3_DN5_CH0 + + + ;Comparator for Ch0 + MOV TREG2, CN5 + + .if $isdefed("DEBUG_CODE") + SBBO &CN5, OUT_SAMP_BUF_REG, 0, 4 + .endif + + ;For the current channel, compare against the High threshold, Low threshold and ZC thresholds (if enabled) + ;Load the positive threshold value for current channel + LBBO &OC_HIGH_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_HIGH_THR_CH0_OFFSET, FW_REG_SDFM_CFG_OC_HIGH_THR_SZ + ;Load the positive threshold value for current channel + LBBO &OC_LOW_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_LOW_THR_CH0_OFFSET, FW_REG_SDFM_CFG_OC_LOW_THR_SZ + ;Load the zero crossing threshold value for current channel + LBBO &OC_ZC_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_ZC_THR_CH0_OFFSET, FW_REG_SDFM_CFG_ZC_THR_SZ + + ;Check if the comparator is enabled for current channel + LBBO &COMPARATOR_EN, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_SD_EN_COMP_OFFSET, FW_REG_SDFM_CFG_EN_COMP_SZ + QBBC comp_ch0_end, COMPARATOR_EN, SDFM_CFG_BF_SD_CH0_EN_COMP_BIT + ;Check if the sample value is greater than the high threshold + QBGE over_threshold_start_ch0, OC_HIGH_THR, TREG2 + ;Check if the sample value is lower than the high threshold + QBLE over_threshold_end_ch0, OC_HIGH_THR, TREG2 +low_threshold_ch0_check: + ;Check if the sample value is greater than the low threshold + QBGE below_threshold_end_ch0, OC_LOW_THR, TREG2 + ;Check if the sample value is lower than the low threshold + QBLE below_threshold_start_ch0, OC_LOW_THR, TREG2 +over_threshold_start_ch0: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + QBA low_threshold_ch0_check + +over_threshold_end_ch0: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + QBA low_threshold_ch0_check + +below_threshold_end_ch0: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH0_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + QBA comp_ch0_end + +below_threshold_start_ch0: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH0_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + + +comp_ch0_end: + + + ; Execute SINC3 differentiation for Ch1 + MOV DN0, TREG0 ; DN0 = Ch1 SD HW ACC3 output sample + M_ACC3_PROCESS ACC3_DN1_CH1, ACC3_DN3_CH1, ACC3_DN5_CH1 + + + ;Comparator for ch1 + MOV TREG2, CN5 + + .if $isdefed("DEBUG_CODE") + SBBO &CN5, OUT_SAMP_BUF_REG, 4, 4 + .endif + + ;For the current channel, compare against the High threshold, Low threshold and ZC thresholds (if enabled) + ;Load the positive threshold value for current channel + LBBO &OC_HIGH_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_HIGH_THR_CH1_OFFSET, FW_REG_SDFM_CFG_OC_HIGH_THR_SZ + ;Load the positive threshold value for current channel + LBBO &OC_LOW_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_LOW_THR_CH1_OFFSET, FW_REG_SDFM_CFG_OC_LOW_THR_SZ + ;Load the zero crossing threshold value for current channel + LBBO &OC_ZC_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_ZC_THR_CH1_OFFSET, FW_REG_SDFM_CFG_ZC_THR_SZ + + ;Check if the comparator is enabled for current channel + LBBO &COMPARATOR_EN, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_SD_EN_COMP_OFFSET, FW_REG_SDFM_CFG_EN_COMP_SZ + QBBC comp_ch1_end, COMPARATOR_EN, SDFM_CFG_BF_SD_CH1_EN_COMP_BIT + ;Check if the sample value is greater than the high threshold + QBGE over_threshold_start_ch1, OC_HIGH_THR, TREG2 + ;Check if the sample value is lower than the high threshold + QBLE over_threshold_end_ch1, OC_HIGH_THR, TREG2 +low_threshold_ch1_check: + ;Check if the sample value is greater than the low threshold + QBGE below_threshold_end_ch1, OC_LOW_THR, TREG2 + ;Check if the sample value is lower than the low threshold + QBLE below_threshold_start_ch1, OC_LOW_THR, TREG2 +over_threshold_start_ch1: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + QBA low_threshold_ch1_check + +over_threshold_end_ch1: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + QBA low_threshold_ch1_check + +below_threshold_end_ch1: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH1_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + QBA comp_ch1_end + +below_threshold_start_ch1: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH1_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + +comp_ch1_end: + + ; Execute SINC3 differentiation for Ch2 + MOV DN0, TREG1 ; DN0 = Ch2 SD HW ACC3 output sample + M_ACC3_PROCESS ACC3_DN1_CH2, ACC3_DN3_CH2, ACC3_DN5_CH2 + + + ;Comparator for ch2 + MOV TREG2, CN5 + + .if $isdefed("DEBUG_CODE") + SBBO &CN5, OUT_SAMP_BUF_REG, 8, 4 + .endif + + ;For the current channel, compare against the High threshold, Low threshold and ZC thresholds (if enabled) + ;Load the positive threshold value for current channel + LBBO &OC_HIGH_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_HIGH_THR_CH2_OFFSET, FW_REG_SDFM_CFG_OC_HIGH_THR_SZ + ;Load the positive threshold value for current channel + LBBO &OC_LOW_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_LOW_THR_CH2_OFFSET, FW_REG_SDFM_CFG_OC_LOW_THR_SZ + ;Load the zero crossing threshold value for current channel + LBBO &OC_ZC_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_ZC_THR_CH2_OFFSET, FW_REG_SDFM_CFG_ZC_THR_SZ + + ;Check if the comparator is enabled for current channel + LBBO &COMPARATOR_EN, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_SD_EN_COMP_OFFSET, FW_REG_SDFM_CFG_EN_COMP_SZ + QBBC comp_ch2_end, COMPARATOR_EN, SDFM_CFG_BF_SD_CH2_EN_COMP_BIT + ;Check if the sample value is greater than the high threshold + QBGE over_threshold_start_ch2, OC_HIGH_THR, TREG2 + ;Check if the sample value is lower than the high threshold + QBLE over_threshold_end_ch2, OC_HIGH_THR, TREG2 + ;Check if the sample value is greater than the low threshold +low_threshold_ch2_check: + QBGE below_threshold_end_ch2, OC_LOW_THR, TREG2 + ;Check if the sample value is lower than the low threshold + QBLE below_threshold_start_ch2, OC_LOW_THR, TREG2 +over_threshold_start_ch2: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + QBA low_threshold_ch2_check + +over_threshold_end_ch2: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + QBA low_threshold_ch2_check + +below_threshold_end_ch2: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH2_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + QBA comp_ch2_end + +below_threshold_start_ch2: + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH2_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ +comp_ch2_end: + + .if $isdefed("DEBUG_CODE") + ;Debug code + ; Write local interleaved output samples to Host buffer address + LBBO &TREG3, OUT_SAMP_BUF_REG, 0, ICSSG_NUM_SD_CH_FW*4 + SBBO &TREG3, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET, ICSSG_NUM_SD_CH_FW*4 + ; Trigger interrupt + LDI R31.w0, TRIGGER_HOST_SDDF_IRQ + .endif + + + + .if $isdefed("DEBUG_CODE") + ;GPIO LOW + LBBO &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ + LBBO &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + SBBO &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ + .endif + + + ; Save/restore context + ; save differentiator state(R9-R17) + xchg BANK_CTXT_OC, &R9, 4*NUM_REGS_DIFF_STATE + + + + XIN TM_YIELD_XID, &R0.b3,1 ; exit task after two instructions/cycles + NOP + NOP + +; +; Initialize Task Manager +; +tm_init: +; Configure Task Manager tasks +; + ; TM general purpose mode + ; Enable T1_S1: IEP0 CMP4 task + LDI TREG0.b0, (1b<<3|0b<<2|11b<<0) ; enable T1_s1 + SBCO &TREG0.b0, CT_PRU_ICSSG_TM, 0, 1 + + ;set T1_S1 address + LDI TREG0.w0, $CODE(ts1_oc_loop) + SBCO &TREG0.w0, CT_PRU_ICSSG_TM, TASKS_MGR_TS1_PC_S1, 2 + + ; Set Task triggers + ; set T1_S1 trigger to IEP0 CMP4 event = 20 + LDI TREG0.w0, (COMP4_EVENT_NUMBER< CMP4 enabled + SBCO &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_CFG_REG, 1 ; TR0 -> ICSSG_CMP_CFG_REG Byte0 + + + + JMP RET_ADDR_REG + + +; +; Reset SDDF state +; +; Arguments: None +; +reset_sddf_state: + ZERO &R9, (4*NUM_REGS_DIFF_STATE) + XOUT BANK_CTXT_OC, &R9, (4*NUM_REGS_DIFF_STATE);clear OC differentiator state + + XOUT BANK_CTXT_NC, &R9, (4*NUM_REGS_DIFF_STATE) ;clear NC differentiator state + JMP RET_ADDR_REG + + +; +; Configure OC Over Sampling Rate for SD channels +; +; Arguments: +; SDDF_CFG_BASE_PTR_REG: base address of SD Configuration registers (&IEP_CFG_EPWM_PRD) +; SD_HW_BASE_PTR_REG: base address of SD HW configuration registers (&ICSSG_PRUn_SD_CLK_SEL_REG0) +; +config_oc_osr: + + ; Load TR1.w0 <- SDDF_CFG_SD_CH_ID = ;LDI TREG1.w0, 0x210 =001100010000 + + LBBO &TREG1.w0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ + + LOOP config_osr_loop_end, ICSSG_NUM_SD_CH_FW ; loop over SD channels + AND TREG2.b0, TREG1.b0, BF_SD_CH0_ID_MASK ; LS byte is ID for Ch0 + QBNE SDFM_SKIP0_CH0, TREG2.b0, 0 + ; Load TR0.b0 <- FW_REG_SDDF_CFG_OSR load osr from DMEM for ch0 + LBBO &TREG0.b0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH0_OSR_OFFSET, FW_REG_SDDF_CFG_OSR_SZ + JMP SDFM_SKIP0_CH2 +SDFM_SKIP0_CH0: + QBNE SDFM_SKIP0_CH1, TREG2.b0, 1 + ; Load TR0.b0 <- FW_REG_SDDF_CFG_OSR load osr from DMEM for ch1 + LBBO &TREG0.b0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH1_OSR_OFFSET, FW_REG_SDDF_CFG_OSR_SZ + JMP SDFM_SKIP0_CH2 +SDFM_SKIP0_CH1: + QBNE SDFM_SKIP0_CH2, TREG2.b0, 2 + ; Load TR0.b0 <- FW_REG_SDDF_CFG_OSR load osr from DMEM for ch2 + LBBO &TREG0.b0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH2_OSR_OFFSET, FW_REG_SDDF_CFG_OSR_SZ +SDFM_SKIP0_CH2: + + LSL TREG2, TREG2, 3 ; (ChID*8) bytes to Byte0 PRUn_SD_SAMPLE_SIZE_REG(ChID) + ADD TREG2, TREG2, 4 ; 4 bytes added for Byte0 PRUn_SD_SAMPLE_SIZE_REG0 + + SBBO &TREG0.b0, SD_HW_BASE_PTR_REG, TREG2, 1 ; TR0.b0 -> PRUn_SD_SAMPLE_SIZE_REG(ChID) + LSR TREG1, TREG1, 4 ; LS byte is ID for Ch(i+1) ; FL fix me +config_osr_loop_end: + + JMP RET_ADDR_REG + + +; +; Configure SD channels. For SD channels, initialize: +; ACC select = ACC3 +; Clock inversion +; Clock source: pr1_pru_pru_r31_in[16] Primary Input +; +; SDDF_CFG_BASE_PTR_REG: base address of SD Configuration registers (&IEP_CFG_EPWM_PRD) +; SD_HW_BASE_PTR_REG: base address of SD HW configuration registers (&ICSSG_PRUn_SD_CLK_SEL_REG0) +; +config_sd_ch: + ; Load TR1.w0 <- SDDF_CFG_SD_CH_ID ;LDI TREG1.w0, 0x210 =001100010000 + + LBBO &TREG1.w0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ + + LOOP config_sd_ch_loop_end, ICSSG_NUM_SD_CH_FW ; loop over SD channels + AND TREG2.b0, TREG1.b0, BF_SD_CH0_ID_MASK ; LS byte is ID for Chi + QBNE SDFM_SKIP1_CH0, TREG2.b0, 0 + ; Select clock inversion + LDI TREG0.w0, 0; + LBBO &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH0_CLOCK_INVERSION_OFFSET, 1 + LSL TREG0.b2, TREG0.b2, PRUn_SD_CLK_INVi_SHIFT + AND TREG0.b0, TREG0.b2, PRUn_SD_CLK_INVi_MASK< PRUn_SD_CLK_SEL_REGi + LSR TREG1, TREG1, 4 ; LS byte is ID for Ch(i+1) ; FL fix me +config_sd_ch_loop_end: + + JMP RET_ADDR_REG + + +; +; Reset SD channel hardware +; +; SDDF_CFG_BASE_PTR_REG: base address of SD Configuration registers (&IEP_CFG_EPWM_PRD) +; +reset_sd_ch_hw: + ; Load T01.w0 <- SDDF_CFG_SD_CH_ID + ;LDI TREG0.w0, 0x210 + LBBO &TREG0.w0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ + + LOOP reset_sd_ch_hw_loop_end, ICSSG_NUM_SD_CH_FW ; loop over SD channels + AND TREG1.b0, TREG0.b0, BF_SD_CH0_ID_MASK ; LS byte is ID for Chi + + ; Set R30[29-26]:channel_select = channel ID. + ; Set R30[25]:channel_en=1 (set Global Channel enable). + LSL TREG1.b0, TREG1.b0, 2 ; TR1.b0 = TR1.b0<<2 = (Ch ID)<<2 + SET TREG1.b0.t1 ; R30[25] channel_enable=1 + MOV R30.b3, TREG1.b0 ; R30.b3 = TR1.b0 + ; select SD Channel (Ch ID) + LSR TREG0, TREG0, 4 ; LS byte is ID for Ch(i+1) ; FL fix me + SET R31.t23 ; R31[23] re_init=1 +reset_sd_ch_hw_loop_end: + + JMP RET_ADDR_REG + + +; +; Initialize SD (eCAP PWM) clock +; +; Arguments: +; SDDF_CFG_BASE_PTR_REG: base address of SD Configuration registers (&IEP_CFG_EPWM_PRD) +; +init_sd_clock: + ; Set eCAP PWM mode + LDI32 TREG0, (SYNCI_EN_VAL< +#include "../firmware/icssg_sddf.h" +#include + + /** + * \defgroup MOTOR_CONTROL_API APIs for Motor Control Encoders + * + * This module contains APIs for device drivers for various motor control encoders supported in this SDK. + */ + +/** + * \defgroup SDFM_API_MODULE APIs for SDFM + * \ingroup MOTOR_CONTROL_API + * + * Here is the list of APIs used for Sigma Delta interface + * + * @{ + */ + + + +/* Number of ICSSG PRUs */ +#define NUM_PRU ( 2 ) + +/* PRU IDs */ +#define PRU_ID_0 ( 0 ) /* PRU 0 ID */ +#define PRU_ID_1 ( 1 ) /* PRU 1 ID */ + +/* Number of SD channels */ +#define NUM_SD_CH ( ICSSG_NUM_SD_CH ) +/* ICSSG INTC event */ +#define SDFM_EVT ( TRIGGER_HOST_SDFM_EVT ) + +/* SDFM handle */ +typedef SDFM *sdfm_handle; + +/** + * + * \brief Initialize SDFM instance + * + * \param[in] pru_id PRU (SD) ID + * + * \retval sdfm SDFM instance handle + * + */ +sdfm_handle SDFM_init(uint8_t pru_id); + +/** + * + * \brief Configure iep increment & iep count in one epwm cycle + * + * \param[in] h_sdfm SDFM handle + * \param[in] epwm_out_freq epwm output frequency + * + * + * + */ +void SDFM_configIepCount(sdfm_handle h_sdfm, uint32_t epwm_out_freq); + +/** + * + * \brief Configure ecap parameters for generate 20MHz SD clock + * + * \param[in] h_sdfm SDFM handle + * \param[in] ecap_divider ecap divider for sdfm clock + * + * + * + */ +void SDFM_configEcap(sdfm_handle h_sdfm, uint8_t ecap_divider); + +/** + * + * \brief Enable the channel specified by the channel number parameter + * + * \param[in] h_sdfm SDFM handle + * \param[in] channel_number channel number + * + * + * + * + */ +void SDFM_setEnableChannel(sdfm_handle h_sdfm, uint8_t channel_number); + +/** + * + * \brief Configure Accumulator over sampling ratio + * + * \param[in] h_sdfm SDFM handle + * \param[in] ch_id current ch number + * \param[in] osr over sampling ratio + * + * + * + */ +void SDFM_setAccOverSamplingRatio(sdfm_handle h_sdfm, uint8_t ch_id, uint8_t osr); + +/** + * + * \brief SDFM global enable + * + * \param[in] h_sdfm SDFM handle + * + * + * + */ +void SDFM_enable(sdfm_handle h_sdfm); + +/** + * + * \brief configuration of SDFM threshold values + * + * \param[in] h_sdfm SDFM handle + * \param[in] ch_id current ch number + * \param[in] thresholdParms thresholds parametrs (High and Low ) + * + * + * + */ +void SDFM_setCompFilterThresholds(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_ThresholdParms thresholdParms); + +/** + * + * \brief configuration of sample read time one Epwm cycle + * + * \param[in] h_sdfm SDFM handle + * \param[in] trig_samp_time sample read time in one pwm cycle + * + * + * + */ +void SDFM_setSampleReadingTime(sdfm_handle h_sdfm, float trig_samp_time); + +/** + * + * \brief configuration of SDFM channel Acc source (sync filter type).
+ * Current SDFM firmware implementation support only SYNC3 filter
+ * + * \param[in] h_sdfm SDFM handle + * \param[in] ch_id current ch number + * \param[in] filter filter type (acc source) + * + * + * + */ +void SDFM_configDataFilter(sdfm_handle h_sdfm, uint8_t ch_id, uint8_t filter); + +/** + * + * \brief configuration of SDFM channel clock source & clock inversion + * + * \param[in] h_sdfm SDFM handle + * \param[in] ch_id current ch number + * \param[in] clkPrams channel clock source type & clock inversion + * + * + * + */ +void SDFM_selectClockSource(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_ClkSourceParms clkPrams); + +/** + * + * \brief This API enables the Comparator for the selected channel. + * + * \param[in] h_sdfm SDFM handle + * \param[in] ch current ch number + * + * + * + * + */ +void SDFM_enableComparator(sdfm_handle h_sdfm, uint8_t ch); + +/** + * + * \brief This API disables the Comparator for the selected channel. + * + * \param[in] h_sdfm SDFM handle + * \param[in] ch current ch number + * + * + * + * + */ +void SDFM_disableComparator(sdfm_handle h_sdfm, uint8_t ch); + +/** + * + * \brief configure GPIO pin number and address for associate Channel Number + * + * \param[in] h_sdfm SDFM handle + * \param[in] ch current ch number + * \param[in] gpio_base_addr GPIO bas address + * \param[in] pin_number GPIO PIN number + * \param[in] threshold_type Threshold type: High(0), Low(1) + * + * + * + */ +void SDFM_configComparatorGpioPins(sdfm_handle h_sdfm, uint8_t ch,uint32_t gpio_base_addr, uint32_t pin_number, uint32_t threshold_type); + +/** + * + * \brief get sample data from DMEM + * + * \param[in] ch current ch number + * + * + * \retval current sample value + * + */ +uint32_t SDFM_getFilterData(uint8_t ch); + +/** + * + * \brief Configure iep count for over current sampling + * + * \param[in] h_sdfm SDFM handle + * \param[in] osr over current osr value + * + * + * + */ +void SDFM_setCompFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t osr); + +/** + * + * \brief Configure iep count for normal current sampling + * + * \param[in] h_sdfm SDFM handle + * \param[in] nc_osr normal current osr value + * \param[in] oc_osr over current osr value + * + * + */ +void SDFM_setFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t nc_osr, uint16_t oc_osr); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/motor_control/current_sense/sdfm/include/sdfm_drv.h b/source/motor_control/current_sense/sdfm/include/sdfm_drv.h new file mode 100644 index 0000000..fc567a1 --- /dev/null +++ b/source/motor_control/current_sense/sdfm/include/sdfm_drv.h @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SDDF_DRV_H_ +#define _SDDF_DRV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + + +/* ========================================================================== */ +/* Macros */ +/* ========================================================================== */ + + +/** \brief ICSSG DMEM0/1 base addresses */ +#define PRU_ICSSG_DRAM0_SLV_RAM ( CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE ) +#define PRU_ICSSG_DRAM1_SLV_RAM ( CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE ) + +/** \brief SD channel control, channel disable/enable */ +#define DEF_SD_CH_CTRL_CH_EN ( 0 ) /* default all chs disabled */ +#define BF_CH_EN_MASK ( 0x1 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH0_EN_SHIFT ( 0 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH0_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH0_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_BF_CH1_EN_SHIFT ( 1 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH1_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH1_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_BF_CH2_EN_SHIFT ( 2 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH2_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH2_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_BF_CH3_EN_SHIFT ( 3 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH3_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH3_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_BF_CH4_EN_SHIFT ( 4 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH4_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH4_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_BF_CH5_EN_SHIFT ( 5 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH5_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH5_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_BF_CH6_EN_SHIFT ( 6 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH6_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH6_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_BF_CH7_EN_SHIFT ( 7 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH7_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH7_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_BF_CH8_EN_SHIFT ( 8 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH8_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH8_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_BF_CH9_EN_SHIFT ( 9 ) +#define SDFM_CH_CTRL_CH_EN_BF_CH9_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH9_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_SHIFT ( SDFM_CH_CTRL_CH_EN_BF_CH0_EN_SHIFT ) +#define SDFM_CH_CTRL_CH_EN_MASK \ + ( SDFM_CH_CTRL_CH_EN_BF_CH0_EN_MASK | \ + SDFM_CH_CTRL_CH_EN_BF_CH1_EN_MASK | \ + SDFM_CH_CTRL_CH_EN_BF_CH2_EN_MASK | \ + SDFM_CH_CTRL_CH_EN_BF_CH3_EN_MASK | \ + SDFM_CH_CTRL_CH_EN_BF_CH4_EN_MASK | \ + SDFM_CH_CTRL_CH_EN_BF_CH5_EN_MASK | \ + SDFM_CH_CTRL_CH_EN_BF_CH6_EN_MASK | \ + SDFM_CH_CTRL_CH_EN_BF_CH7_EN_MASK | \ + SDFM_CH_CTRL_CH_EN_BF_CH8_EN_MASK | \ + SDFM_CH_CTRL_CH_EN_BF_CH9_EN_MASK ) + +#define SDFM_MAIN_FILTER_MASK ( 1 ) +#define SDFM_MAIN_FILTER_SHIFT ( 0 ) + +#define SDFM_MAIN_INTERRUPT_MASK ( 1 ) +#define SDFM_MAIN_INTERRUPT_SHIFT ( 1 ) + +/** \brief reinitialize PRU SDFM */ +#define SDFM_RECFG_REINIT ( SDFM_RECFG_BF_RECFG_REINIT_MASK ) +/** \brief reconfigure SD clock */ +#define SDFM_RECFG_CLK ( SDFM_RECFG_BF_RECFG_CLK_MASK ) +/** \brief reconfigure SD OSR */ +#define SDFM_RECFG_OSR ( SDFM_RECFG_BF_RECFG_OSR_MASK ) +/** \brief reconfigure Trigger mode sample time */ +#define SDFM_RECFG_TRIG_SAMP_TIME ( SDFM_RECFG_BF_RECFG_TRIG_SAMPLE_TIME_MASK ) +/** \brief reconfigure Trigger mode sample count */ +#define SDFM_RECFG_TRIG_SAMP_CNT ( SDFM_RECFG_BF_RECFG_TRIG_SAMPLE_CNT_MASK ) +/** \brief reconfigure SD channel disable/enable */ +#define SDFM_RECFG_CH_EN ( 1<<6 ) +/** \brief reconfigure SD channel disable/enable */ +#define SDFM_RECFG_FD ( SDFM_RECFG_BF_RECFG_FD_MASK ) +/** \brief reconfigure Trigger mode output sample buffer */ +#define SDFM_RECFG_TRIG_OUT_SAMP_BUF ( SDFM_RECFG_BF_RECFG_TRIG_OUT_SAMP_BUF_MASK ) +/** \brief IEP_CFG*/ +#define IEP_DEFAULT_INC 0x1 +/** \brief IEP_CFG_EPWM_PRD */ +#define CMP0_CNT_EPWM_PRD 0x927C + +/* SDFM output buffer size in 32-bit words */ + + +#define ICSSG_SD_SAMP_CH_BUF_SZ 128 +#define NUM_CH_SUPPORTED ( 3 ) + +/* ========================================================================== */ +/* Structures */ +/* ========================================================================== */ + +/** + * \brief Structure defining SDFM clock configuration parameters. + * + * \details Firmware SD clock configuration interface exposed through PRU data
+ * memory - used by driver to configure firmware parameters + */ +typedef struct SDFM_CfgSdClk_s +{ + /**< clock count to generate SD clock (eCAP PWM) with desired frequency */ + volatile uint8_t sd_prd_clocks; + /**< invert SD clock post clock selection mux */ + volatile uint8_t sd_clk_inv; +} SDFM_CfgSdClk; + +/** + * \brief Structure defining SDFM triggered mode trigger times + * + * \details Firmware trigger fields exposed through PRU data
+ * memory - used by driver to start sampling and
+ * generate optional output event after receiving
+ * input trigger + */ +typedef struct SDFM_CfgTrigger_s +{ + /**< time to start sampling after trigger input */ + volatile uint32_t trig_samp_time; + /**< IEP0 counts in OC sampling period*/ + volatile uint16_t oc_prd_iep_cnt; + /**< IEP0 counts in NC sampling period*/ + volatile uint16_t nc_prd_iep_cnt; + /**< OC Sample count for one NC sample*/ + volatile uint16_t sample_count; +} SDFM_CfgTrigger; + +/** + * \brief Structure defining SDFM IEP configuration + * + * \details Increment value of IEP counter (IEP0 default increment=1)
+ * IEP CMP0 count for simulated EPWM period
+ */ +typedef struct SDFM_CfgIep_s +{ + /**< bit-field containing flags indicating configurations to be executed, non-zero to enable */ + volatile uint8_t iep_inc_value; + + /**< IEP CMP0 count for simulated EPWM period */ + volatile uint32_t cnt_epwm_prd; + +}SDFM_CfgIep; + + +/** + * \brief Structure defining SDFM base address and values to toggle GPIO pins + * + * \details Used to toggle the gpio based on different threshold conditions + * + */ +typedef struct SDFM_GpioParams_s{ + volatile uint32_t write_val; + volatile uint32_t set_val_addr; + volatile uint32_t clr_val_addr; +} SDFM_GpioParams; + +/** + * \brief Structure defining SDFM channel control fields + * + * \details Used by driver to enable / disable individual SD
+ * channels. + */ +typedef struct SDFM_ChCtrl_s +{ + /**< stores the channel ids for different selected channel */ + volatile uint32_t sdfm_ch_id; + /**< bit-field to enable comparators for individual SDFM channels, BitN:ChN, non-zero to enable */ + volatile uint16_t enable_comparator; + /**< bit-field to set the output data format for individual SDFM channels, BitN:ChN */ + volatile uint16_t output_data_format; + /**< reserved */ + volatile uint16_t reserved1; + /**< reserved */ + volatile uint16_t reserved2; + +} SDFM_ChCtrl; + +/** + * \brief Structure defining clk source for sdfm ch + * + * \details clk source for channel
+ * iversion of clock + */ +typedef struct SDFM_ClkSourceParms_s +{ + /** < Channle clock source */ + volatile uint32_t clk_source; + /** + * + */ +typedef struct SDFM_ThresholdParms_s +{ + /**< High threshold value */ + volatile uint32_t high_threshold; + /**< Low threshold value */ + volatile uint32_t low_threshold; + /**< reserved for zero crossing*/ + volatile uint32_t reserved3; +}SDFM_ThresholdParms; + +/** + * \brief Structure defining SDFM configuration interface + * + * \details Firmware configuration interface exposed through PRU data
+ * memory - used by driver to configure firmware parameters + */ +typedef struct SDFM_Cfg_s +{ + /** < Channle id */ + volatile uint8_t ch_id; + /**< Filter type - sinc1, sinc2, sinc3 */ + volatile uint8_t filter_type; + /**< Accumulator Over Sampling Rate (OSR) */ + volatile uint8_t osr; + /**< sdfm threshold parms*/ + SDFM_ThresholdParms sdfm_threshold_parms; + /**< reserved*/ + volatile uint8_t reserved4; + /**< reserved*/ + volatile uint32_t reserved5; + /**< sdfm ch clock parms*/ + SDFM_ClkSourceParms sdfm_clk_parms; + /**< array to store the params for gpio toggle for different channels*/ + SDFM_GpioParams sdfm_gpio_params[3]; +} SDFM_Cfg; + +/** + * \brief Structure defining SDFM control fields + * + * \details Firmware control & status interface exposed through PRU data
+ * memory - used by driver to enable SDFM operations and to select
+ * between continuous and triggered mode
+ */ +typedef struct SDFM_Ctrl_s +{ + /**< SDFM control */ + volatile uint8_t ctrl; + /**< SDFM status */ + volatile uint8_t stat; +} SDFM_Ctrl; + +typedef struct SDFM_Interface_s{ + /**< control interface */ + SDFM_Ctrl sdfm_ctrl; + /** +#include +#include +#include +static struct endat_priv endat_priv; +/* + * check 2.2 command case with 2.2 capability in encoder, can live w/o as endat_get_command + * will handle and it is assumed that functions, + * endat_recvd_organize() + * endat_recvd_format() + * endat_recvd_validate() + * endat_recvd_print() + * will normally be called after endat_get_command + */ + +static int32_t endat_recvd_organize(int32_t cmd, struct endat_priv *priv, + struct endat_data *endat_data) +{ + uint32_t word0, word1, word2, word3; + uint32_t pos_bits, shift; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + memset(endat_data, 0, sizeof(*endat_data)); + + word0 = pruss_xchg->ch[priv->channel].pos_word0; + word1 = pruss_xchg->ch[priv->channel].pos_word1; + word2 = pruss_xchg->ch[priv->channel].pos_word2; + word3 = pruss_xchg->ch[priv->channel].pos_word3; + + switch(cmd) + { + case 2: + case 3: + case 4: + case 5: + case 7: + case 14: + endat_data->recvd1 = word0; + break; + + case 6: + shift = ENDAT_RX_46BITS % (sizeof(unsigned) * 8); + endat_data->recvd1 = (uint64_t) word0 << shift | word1; + break; + + case 1: + pos_bits = priv->pos_res + ENDAT_NUM_BITS_POSITION_CRC + ENDAT_NUM_BITS_F1; + + if(pos_bits <= sizeof(unsigned) * 8) + { + endat_data->recvd1 = word0; + } + else + { + shift = pos_bits % (sizeof(unsigned) * 8); + endat_data->recvd1 = (uint64_t) word0 << shift | word1; + } + break; + + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + pos_bits = priv->pos_res + ENDAT_NUM_BITS_POSITION_CRC + ENDAT_NUM_BITS_F1 + + ENDAT_NUM_BITS_F2; + + if(pos_bits <= sizeof(unsigned) * 8) + { + endat_data->recvd1 = word0; + } + else + { + shift = pos_bits % (sizeof(unsigned) * 8); + endat_data->recvd1 = (uint64_t) word0 << shift | word1; + } + if(priv->flags.info1 || priv->flags.info2) + { + endat_data->recvd2 = word2; + } + if(priv->flags.info1 && priv->flags.info2) + { + endat_data->recvd3 = word3; + } + break; + + default: + return -EINVAL; + break; + } + + return 0; +} + +/* value to be reflected should be aligned to lsb, relected value would be aligned to lsb */ +static uint64_t endat_reflect_ull_nbits(uint64_t input, + uint32_t n) +{ + uint32_t i; + uint64_t val = 0; + + /* val initialized to 0 above to handle n = 0 case, otherwise garbage would be returned */ + for(i = 0; i < n; i++) + { + val <<= 1; + + if(input & ((uint64_t) 1 << i)) + { + val |= 1; + } + } + + return val; +} + +static int64_t endat_recvd_format(int32_t cmd, struct endat_priv *priv, + struct endat_data *endat_data, union endat_format_data *u) +{ + uint64_t pos, rev; + + switch(cmd) + { + case 2: + case 3: + case 4: + case 5: + case 7: + case 14: + u->addr_params.params = (endat_data->recvd1 >> ENDAT_NUM_BITS_POSITION_CRC) + & ((1 << ENDAT_NUM_BITS_PARAMETER) - 1); + u->addr_params.address = (endat_data->recvd1 >> (ENDAT_NUM_BITS_POSITION_CRC + + ENDAT_NUM_BITS_PARAMETER)) & + ((1 << ENDAT_NUM_BITS_ADDRESS) - 1); + u->addr_params.crc = endat_data->recvd1 & ((1 << ENDAT_NUM_BITS_POSITION_CRC) + - 1); + break; + + case 6: + u->test.value = (endat_data->recvd1 >> ENDAT_NUM_BITS_POSITION_CRC) & ((( + uint64_t)1 << 40) - 1); + u->test.f1 = (endat_data->recvd1 >> (ENDAT_NUM_BITS_POSITION_CRC + 40)) & 1; + u->test.crc = endat_data->recvd1 & ((1 << ENDAT_NUM_BITS_POSITION_CRC) - 1); + break; + + case 1: + pos = endat_data->recvd1 >> ENDAT_NUM_BITS_POSITION_CRC; + pos = pos & (((uint64_t) 1 << priv->pos_res) - 1); /* mask F1 */ + pos = endat_reflect_ull_nbits(pos, priv->pos_res); + rev = (pos & (((uint64_t) 1 << priv->pos_res) - 1)) >> + priv->single_turn_res; + pos = pos & (((uint64_t) 1 << priv->single_turn_res) - 1); + u->position_addinfo.position.position = pos; + u->position_addinfo.position.revolution = rev; + u->position_addinfo.position.f1 = (endat_data->recvd1 >> + (ENDAT_NUM_BITS_POSITION_CRC + priv->pos_res)) & 1; + u->position_addinfo.position.crc = endat_data->recvd1 & (( + 1 << ENDAT_NUM_BITS_POSITION_CRC) - 1); + break; + + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + pos = endat_data->recvd1 >> ENDAT_NUM_BITS_POSITION_CRC; + pos = pos & (((uint64_t) 1 << priv->pos_res) - + 1); /* mask F1/F2 */ + pos = endat_reflect_ull_nbits(pos, priv->pos_res); + rev = (pos & (((uint64_t) 1 << priv->pos_res) - 1)) >> + priv->single_turn_res; + pos = pos & (((uint64_t) 1 << priv->single_turn_res) - 1); + u->position_addinfo.position.position = pos; + u->position_addinfo.position.revolution = rev; + u->position_addinfo.position.f1 = (endat_data->recvd1 >> + (ENDAT_NUM_BITS_POSITION_CRC + priv->pos_res + 1)) & 1; + u->position_addinfo.position.f2 = (endat_data->recvd1 >> + (ENDAT_NUM_BITS_POSITION_CRC + priv->pos_res)) & 1; + u->position_addinfo.position.crc = endat_data->recvd1 & (( + 1 << ENDAT_NUM_BITS_POSITION_CRC) - 1); + + if(priv->flags.info1 || priv->flags.info2) + { + if(endat_priv.flags.info2) + { + u->position_addinfo.addinfo2.addinfo = (endat_data->recvd2 >> + ENDAT_NUM_BITS_POSITION_CRC) & ((1 << 24) - 1); + u->position_addinfo.addinfo2.crc = endat_data->recvd2 & (( + 1 << ENDAT_NUM_BITS_POSITION_CRC) - 1); + } + else + { + u->position_addinfo.addinfo1.addinfo = (endat_data->recvd2 >> + ENDAT_NUM_BITS_POSITION_CRC) & ((1 << 24) - 1); + u->position_addinfo.addinfo1.crc = endat_data->recvd2 & (( + 1 << ENDAT_NUM_BITS_POSITION_CRC) - 1); + } + } + + if(priv->flags.info1 && priv->flags.info2) + { + u->position_addinfo.addinfo1.addinfo = (endat_data->recvd3 >> + ENDAT_NUM_BITS_POSITION_CRC) & ((1 << 24) - 1); + u->position_addinfo.addinfo1.crc = endat_data->recvd3 & (( + 1 << ENDAT_NUM_BITS_POSITION_CRC) - 1); + } + break; + + default: + return -EINVAL; + break; + } + + return 0; +} + +int32_t endat_recvd_process(struct endat_priv *priv, int32_t cmd, + union endat_format_data *u) +{ + struct endat_data endat_data; + int32_t ret; + + ret = endat_recvd_organize(cmd, priv, &endat_data); + + if(ret < 0) + { + return ret; + } + + return endat_recvd_format(cmd, priv, &endat_data, u); +} + +#define ENDAT_USE_OTF_CRC_STATUS + +#ifndef ENDAT_USE_OTF_CRC_STATUS +static uint32_t make_crc_norm(uint32_t param8, uint32_t param16) +{ + /* state of the 5 flip-flops */ + uint32_t ff[5]; + /* data bit array */ + uint32_t code[24]; + /* Auxiliary variable */ + uint32_t ex; + /* dtetermined CRC code */ + uint32_t crc = 0; + /* controlled variable for looping */ + int32_t i; + + /* set all flip-flops to 1 */ + for(i = 0; i < 5; i++) + { + ff[i] = 1; + } + + /* read 8 bit parameter into code array and convert bit sequence */ + for(i = 0; i < 8; i++) + { + code[i] = (param8 & 0x0080) ? 1 : 0; + param8 <<= 1; + } + + /* read 16 bit parameter into code array and convert bit sequence */ + for(i = 8; i < 24; i++) + { + code[i] = (param16 & 0x8000) ? 1 : 0; + param16 <<= 1; + } + + /* calculate crc analog to described h/w generator */ + for(i = 0; i < 24; i++) + { + ex = ff[4] ^ code[i]; + ff[4] = ff[3]; + ff[3] = ff[2] ^ ex; + ff[2] = ff[1]; + ff[1] = ff[0] ^ ex; + ff[0] = ex; + } + + /* store crc in variable */ + for(i = 4; i >= 0; i--) + { + ff[i] = ff[i] ? 0 : 1; + crc <<= 1; + crc |= ff[i]; + } + + return crc; +} + +static uint32_t make_crc_pos(uint32_t clocks, uint32_t error1, + uint32_t error2, uint32_t endat22, + uint64_t highpos, uint64_t lowpos) +{ + /* state of the 5 flip-flops */ + uint32_t ff[5]; + /* data bit array */ + uint32_t code[66]; + /* Auxiliary variable */ + uint32_t ex; + /* dtetermined CRC code */ + uint32_t crc = 0; + /* controlled variable for looping */ + int32_t i; + + /* set all flip-flops to 1 */ + for(i = 0; i < 5; i++) + { + ff[i] = 1; + } + + /* transfer alarm bits to code array */ + if(endat22) + { + code[0] = error1; + code[1] = error2; + } + else + { + code[1] = error1; + } + + /* transfer low pos bits to array */ + for(i = 2; i < 34; i++) + { + code[i] = (lowpos & 0x00000001L) ? 1 : 0; + lowpos >>= 1; + } + + /* transfer high pos bits to array */ + for(i = 34; i < 66; i++) + { + code[i] = (highpos & 0x00000001L) ? 1 : 0; + highpos >>= 1; + } + + /* calculate crc analog to described h/w generator */ + for(i = (endat22 ? 0 : 1); i <= (clocks + 1); i++) + { + ex = ff[4] ^ code[i]; + ff[4] = ff[3]; + ff[3] = ff[2] ^ ex; + ff[2] = ff[1]; + ff[1] = ff[0] ^ ex; + ff[0] = ex; + } + + /* store crc in variable */ + for(i = 4; i >= 0; i--) + { + ff[i] = ff[i] ? 0 : 1; + crc <<= 1; + crc |= ff[i]; + } + + return crc; +} +#endif + +/* return crc status: bit0 - position/address params/test, bit1 - additional info1, bit2 - additional info2. return -EINVAL on failure */ +uint32_t endat_recvd_validate(struct endat_priv *priv, int32_t cmd, + union endat_format_data *u) +{ + uint32_t status = 0; +#ifdef ENDAT_USE_OTF_CRC_STATUS + uint8_t val; +#else + uint32_t crc; + uint64_t highpos, lowpos; + uint64_t test; +#endif + +#ifdef ENDAT_USE_OTF_CRC_STATUS + val = priv->pruss_xchg->ch[priv->channel].crc.status; + + if(priv->flags.info2) + { + status = val & 0x1; + /* move bit 1 to bit 2 */ + status |= (val & 0x2) << 1; + + if(priv->flags.info1) + { + /* move bit 2 to bit 1 */ + status |= (val & 0x4) >> 1; + } + } + + else + { + /* either additional info1 only present or no additional info present */ + status = val & 0x3; + } + +#else + + switch(cmd) + { + case 1: + lowpos = (u->position_addinfo.position.revolution << priv->single_turn_res | + u->position_addinfo.position.position) & 0xFFFFFFFF; + highpos = (u->position_addinfo.position.revolution << priv->single_turn_res | + u->position_addinfo.position.position) >> 32; + crc = make_crc_pos(priv->pos_res, u->position_addinfo.position.f1, 0, 0, + highpos, lowpos); + + if(u->position_addinfo.position.crc == crc) + { + status = 0x1; + } + break; + + case 6: + test = endat_reflect_ull_nbits(u->test.value, 40); + lowpos = test & 0xFFFFFFFF; + highpos = test >> 32; + crc = make_crc_pos(40, u->position_addinfo.position.f1, 0, 0, highpos, + lowpos); + + if(u->test.crc == crc) + { + status = 0x1; + } + break; + + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + lowpos = (u->position_addinfo.position.revolution << priv->single_turn_res | + u->position_addinfo.position.position) & 0xFFFFFFFF; + highpos = (u->position_addinfo.position.revolution << priv->single_turn_res | + u->position_addinfo.position.position) >> 32; + crc = make_crc_pos(priv->pos_res, u->position_addinfo.position.f1, + u->position_addinfo.position.f2, 1, highpos, lowpos); + + if(u->position_addinfo.position.crc == crc) + { + status = 0x1; + } + + if(priv->flags.info1) + { + crc = make_crc_norm((u->position_addinfo.addinfo1.addinfo >> 16) & 0xFF, + u->position_addinfo.addinfo1.addinfo & 0xFFFF); + + if(u->position_addinfo.addinfo1.crc == crc) + { + status |= 0x1 << 1; + } + } + + if(priv->flags.info2) + { + crc = make_crc_norm((u->position_addinfo.addinfo2.addinfo >> 16) & 0xFF, + u->position_addinfo.addinfo2.addinfo & 0xFFFF); + + if(u->position_addinfo.addinfo2.crc == crc) + { + status |= 0x1 << 2; + } + } + + break; + + case 2: + case 3: + case 4: + case 5: + case 7: + crc = make_crc_norm(u->addr_params.address, u->addr_params.params); + + if(u->addr_params.crc == crc) + { + status = 0x1; + } + break; + + default: + break; + } + +#endif + + return status; +} + +/* + * XXX: check 2.2 command case with 2.2 capability in encoder, can live w/o as endat_get_command + * will handle and it is assumed that this function will be called either after endat_get_command + * or by diagnostic initialization code where it is only 2.1 commands used + */ +int32_t endat_command_build(struct endat_priv *priv, int32_t cmd, + struct cmd_supplement *cmd_supplement) +{ + uint32_t info; + struct endat_pruss_xchg *endat_pruss_xchg = priv->pruss_xchg; + + info = 0, priv->flags.info1 ? info++ : 0, priv->flags.info2 ? info++ : 0 ; + + /*first clear command parameters to be safe */ + memset(&endat_pruss_xchg->cmd, 0, sizeof(endat_pruss_xchg->cmd)); + + switch(cmd) + { + case 1: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEND_POSITION_VALUES; + endat_pruss_xchg->cmd[0].word1 = priv->pos_rx_bits_21_RTUPRU | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_NO_SUPPLEMENT | ENDAT_CMDTYP_POSITION) << 16); + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEND_POSITION_VALUES; + endat_pruss_xchg->cmd[1].word1 = priv->pos_rx_bits_21_PRU | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_NO_SUPPLEMENT | ENDAT_CMDTYP_POSITION) << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEND_POSITION_VALUES; + endat_pruss_xchg->cmd[2].word1 = priv->pos_rx_bits_21_TXPRU | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_NO_SUPPLEMENT | ENDAT_CMDTYP_POSITION) << 16); + } /* command build for ch1 and ch2 in load share mode*/ + break; + case 2: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEL_MEM_AREA; + endat_pruss_xchg->cmd[0].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[0].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + /*build separate command for all three channel in loadshare mode*/ + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEL_MEM_AREA; + endat_pruss_xchg->cmd[1].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[1].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEL_MEM_AREA; + endat_pruss_xchg->cmd[2].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[2].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + } + + break; + + case 3: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_RECEIVE_PARAMETERS; + endat_pruss_xchg->cmd[0].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[0].word0 |= ((cmd_supplement->data & 0x8000) >> 7) + | (((cmd_supplement->data << 1) & 0xFF00) << 8) | + (((cmd_supplement->data << 9) & 0xFE00) << 16); + endat_pruss_xchg->cmd[0].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + /*build separate command for all three channel in loadshare mode*/ + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_RECEIVE_PARAMETERS; + endat_pruss_xchg->cmd[1].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[1].word0 |= ((cmd_supplement->data & 0x8000) >> 7) + | (((cmd_supplement->data << 1) & 0xFF00) << 8) | + (((cmd_supplement->data << 9) & 0xFE00) << 16); + endat_pruss_xchg->cmd[1].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_RECEIVE_PARAMETERS; + endat_pruss_xchg->cmd[2].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[2].word0 |= ((cmd_supplement->data & 0x8000) >> 7) + | (((cmd_supplement->data << 1) & 0xFF00) << 8) | + (((cmd_supplement->data << 9) & 0xFE00) << 16); + endat_pruss_xchg->cmd[2].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + } + break; + + case 4: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEND_PARAMETERS; + endat_pruss_xchg->cmd[0].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[0].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + /*build separate command for all three channel in loadshare mode */ + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEND_PARAMETERS; + endat_pruss_xchg->cmd[1].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[1].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEND_PARAMETERS; + endat_pruss_xchg->cmd[2].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[2].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + } + break; + + case 5: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_RECEIVE_RESET; + endat_pruss_xchg->cmd[0].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + /*build separate command for all three channel in loadshare mode*/ + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_RECEIVE_RESET; + endat_pruss_xchg->cmd[1].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_RECEIVE_RESET; + endat_pruss_xchg->cmd[2].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + } + break; + + case 6: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEND_TEST_VALUES; + endat_pruss_xchg->cmd[0].word1 = ENDAT_RX_46BITS | (ENDAT_TX_6BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + /*build separate command for all three channel in loadshare mode*/ + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEND_TEST_VALUES; + endat_pruss_xchg->cmd[1].word1 = ENDAT_RX_46BITS | (ENDAT_TX_6BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEND_TEST_VALUES; + endat_pruss_xchg->cmd[2].word1 = ENDAT_RX_46BITS | (ENDAT_TX_6BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + } + break; + + case 7: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_RECEIVE_TEST_COMMAND; + endat_pruss_xchg->cmd[0].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[0].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + /*build separate command for all three channel in loadshare mode*/ + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_RECEIVE_TEST_COMMAND; + endat_pruss_xchg->cmd[1].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[1].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_RECEIVE_TEST_COMMAND; + endat_pruss_xchg->cmd[2].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[2].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + (ENDAT_CMDTYP_NO_SUPPLEMENT << 16); + } + break; + + case 8: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEND_POSVAL_WITH_DATA; + /* + * Though this is not 2.1 command, fw expects it to be ENDAT_CMDTYP_2_1. Ideally macro should + * have been named ENDAT_CMDTYPE_HAVE_2_2_SUPPLEMENT instead of ENDAT_CMDTYP_2_[12] for readability + */ + endat_pruss_xchg->cmd[0].word1 = (priv->pos_rx_bits_22_RTUPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_NO_SUPPLEMENT | ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) + << 16); + + /*build separate command for all three channel in loadshare mode*/ + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEND_POSVAL_WITH_DATA; + /* + * Though this is not 2.1 command, fw expects it to be ENDAT_CMDTYP_2_1. Ideally macro should + * have been named ENDAT_CMDTYPE_HAVE_2_2_SUPPLEMENT instead of ENDAT_CMDTYP_2_[12] for readability + */ + endat_pruss_xchg->cmd[1].word1 = (priv->pos_rx_bits_22_PRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_NO_SUPPLEMENT | ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) + << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEND_POSVAL_WITH_DATA; + /* + * Though this is not 2.1 command, fw expects it to be ENDAT_CMDTYP_2_1. Ideally macro should + * have been named ENDAT_CMDTYPE_HAVE_2_2_SUPPLEMENT instead of ENDAT_CMDTYP_2_[12] for readability + */ + endat_pruss_xchg->cmd[2].word1 = (priv->pos_rx_bits_22_TXPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_NO_SUPPLEMENT | ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) + << 16); + + + } + + + + if(priv->flags.info1) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + } + + } + + if(priv->flags.info2) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + } + } + + break; + + case 9: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_MEMSEL; + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_MEMSEL; + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_MEMSEL; + } + if(cmd_supplement->has_block_address) + { + endat_pruss_xchg->cmd[0].word1 = (priv->pos_rx_bits_22_RTUPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | + (ENDAT_TX_6BITS << 8) | ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << + 16) | (1 << 24); + endat_pruss_xchg->cmd[0].word2 = cmd_supplement->address | + (cmd_supplement->block << 24); + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 = (priv->pos_rx_bits_22_PRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | + (ENDAT_TX_6BITS << 8) | ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << + 16) | (1 << 24); + endat_pruss_xchg->cmd[1].word2 = cmd_supplement->address | + (cmd_supplement->block << 24); + + endat_pruss_xchg->cmd[2].word1 = (priv->pos_rx_bits_22_TXPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | + (ENDAT_TX_6BITS << 8) | ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << + 16) | (1 << 24); + endat_pruss_xchg->cmd[2].word2 = cmd_supplement->address | + (cmd_supplement->block << 24); + + } + } + + else + { + endat_pruss_xchg->cmd[0].word1 = (priv->pos_rx_bits_22_RTUPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | + (ENDAT_TX_6BITS << 8) | ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << + 16); + endat_pruss_xchg->cmd[0].word2 = cmd_supplement->address; + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 = (priv->pos_rx_bits_22_PRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | + (ENDAT_TX_6BITS << 8) | ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << + 16); + endat_pruss_xchg->cmd[1].word2 = cmd_supplement->address; + + endat_pruss_xchg->cmd[2].word1 = (priv->pos_rx_bits_22_TXPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | + (ENDAT_TX_6BITS << 8) | ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << + 16); + endat_pruss_xchg->cmd[2].word2 = cmd_supplement->address; + + } + + + } + + if(priv->flags.info1) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + } + } + + if(priv->flags.info2) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + + if(priv->load_share) + { + + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + } + } + + break; + + case 10: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_PARAM; + endat_pruss_xchg->cmd[0].word1 = (priv->pos_rx_bits_22_RTUPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + endat_pruss_xchg->cmd[0].word2 = cmd_supplement->address; + /* data MSByte should be @((char *)word2 + 1) and LSByte @((char *)word2 + 2) */ + endat_pruss_xchg->cmd[0].word2 |= ((cmd_supplement->data & 0xFF) << 16) | + (cmd_supplement->data & 0xFF00); + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_PARAM; + endat_pruss_xchg->cmd[1].word1 = (priv->pos_rx_bits_22_PRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + endat_pruss_xchg->cmd[1].word2 = cmd_supplement->address; + /* data MSByte should be @((char *)word2 + 1) and LSByte @((char *)word2 + 2) */ + endat_pruss_xchg->cmd[1].word2 |= ((cmd_supplement->data & 0xFF) << 16) | + (cmd_supplement->data & 0xFF00); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_PARAM; + endat_pruss_xchg->cmd[2].word1 = (priv->pos_rx_bits_22_TXPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + endat_pruss_xchg->cmd[2].word2 = cmd_supplement->address; + /* data MSByte should be @((char *)word2 + 1) and LSByte @((char *)word2 + 2) */ + endat_pruss_xchg->cmd[2].word2 |= ((cmd_supplement->data & 0xFF) << 16) | + (cmd_supplement->data & 0xFF00); + + } + + + if(priv->flags.info1) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + } + + } + + if(priv->flags.info2) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + } + } + + break; + + case 11: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEND_POSVAL_SEND_PARAM; + endat_pruss_xchg->cmd[0].word1 = (priv->pos_rx_bits_22_RTUPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + endat_pruss_xchg->cmd[0].word2 = cmd_supplement->address; + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEND_POSVAL_SEND_PARAM; + endat_pruss_xchg->cmd[1].word1 = (priv->pos_rx_bits_22_PRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + endat_pruss_xchg->cmd[1].word2 = cmd_supplement->address; + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEND_POSVAL_SEND_PARAM; + endat_pruss_xchg->cmd[2].word1 = (priv->pos_rx_bits_22_TXPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + endat_pruss_xchg->cmd[2].word2 = cmd_supplement->address; + + } + if(priv->flags.info1) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + } + } + + if(priv->flags.info2) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + } + } + + break; + + case 12: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_ERR_RST; + endat_pruss_xchg->cmd[0].word1 = (priv->pos_rx_bits_22_RTUPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_ERR_RST; + endat_pruss_xchg->cmd[1].word1 = (priv->pos_rx_bits_22_PRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_ERR_RST; + endat_pruss_xchg->cmd[2].word1 = (priv->pos_rx_bits_22_TXPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + } + + if(priv->flags.info1) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + } + } + + if(priv->flags.info2) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + } + } + + break; + + case 13: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_TESTCMD; + endat_pruss_xchg->cmd[0].word1 = (priv->pos_rx_bits_22_RTUPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + endat_pruss_xchg->cmd[0].word2 = cmd_supplement->address; + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_TESTCMD; + endat_pruss_xchg->cmd[1].word1 = (priv->pos_rx_bits_22_PRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + endat_pruss_xchg->cmd[1].word2 = cmd_supplement->address; + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_SEND_POSVAL_RECEIVE_TESTCMD; + endat_pruss_xchg->cmd[2].word1 = (priv->pos_rx_bits_22_TXPRU + info * + ENDAT_ADDITIONAL_INFO_RX_BITS) | (ENDAT_TX_6BITS << 8) | + ((ENDAT_CMDTYP_POSITION | ENDAT_CMDTYP_ENDAT22) << 16); + endat_pruss_xchg->cmd[2].word2 = cmd_supplement->address; + } + + if(priv->flags.info1) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO1) << 16; + } + } + + if(priv->flags.info2) + { + endat_pruss_xchg->cmd[0].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + + endat_pruss_xchg->cmd[2].word1 |= (ENDAT_CMDTYP_HAS_ADDINFO2) << 16; + } + } + + break; + + case 14: + endat_pruss_xchg->cmd[0].word0 = ENDAT_CMD_RECEIVE_COMMUNICATION_CMD; + endat_pruss_xchg->cmd[0].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[0].word0 |= ((cmd_supplement->data & 0x8000) >> 7) + | (((cmd_supplement->data << 1) & 0xFF00) << 8) | + (((cmd_supplement->data << 9) & 0xFE00) << 16); + endat_pruss_xchg->cmd[0].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + ((ENDAT_CMDTYP_NO_SUPPLEMENT | ENDAT_CMDTYP_ENDAT22) << 16); + + if(priv->load_share) + { + endat_pruss_xchg->cmd[1].word0 = ENDAT_CMD_RECEIVE_COMMUNICATION_CMD; + endat_pruss_xchg->cmd[1].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[1].word0 |= ((cmd_supplement->data & 0x8000) >> 7) + | (((cmd_supplement->data << 1) & 0xFF00) << 8) | + (((cmd_supplement->data << 9) & 0xFE00) << 16); + endat_pruss_xchg->cmd[1].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + ((ENDAT_CMDTYP_NO_SUPPLEMENT | ENDAT_CMDTYP_ENDAT22) << 16); + + endat_pruss_xchg->cmd[2].word0 = ENDAT_CMD_RECEIVE_COMMUNICATION_CMD; + endat_pruss_xchg->cmd[2].word0 |= ((cmd_supplement->address & 0x80) >> 7) + | (((cmd_supplement->address << 1) & 0xFE) << 8); + endat_pruss_xchg->cmd[2].word0 |= ((cmd_supplement->data & 0x8000) >> 7) + | (((cmd_supplement->data << 1) & 0xFF00) << 8) | + (((cmd_supplement->data << 9) & 0xFE00) << 16); + endat_pruss_xchg->cmd[2].word1 = ENDAT_RX_29BITS | (ENDAT_TX_30BITS << 8) | + ((ENDAT_CMDTYP_NO_SUPPLEMENT | ENDAT_CMDTYP_ENDAT22) << 16); + } + break; + + default: + cmd = -EINVAL; + break; + } + + return cmd; +} + +void endat_command_send(struct endat_priv *priv) +{ + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + /*for load share mode set mask for all connected channels*/ + if(priv->load_share) + { + pruss_xchg->config[0].trigger = pruss_xchg->config[0].channel==1?0x1:0; + pruss_xchg->config[1].trigger = pruss_xchg->config[1].channel==2?0x1:0; + pruss_xchg->config[2].trigger = pruss_xchg->config[2].channel==4?0x1:0; + + } + else + { + pruss_xchg->config[0].trigger = 0x1; + } + +} + +void endat_command_wait(struct endat_priv *priv) +{ + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + if(priv->load_share) + { /*waiting till host trigger bits has not clear for all enabled channels*/ + while((pruss_xchg->config[0].trigger&0x1) || (pruss_xchg->config[1].trigger &0x1) || (pruss_xchg->config[2].trigger&0x1)) + ; + } + else + { + while(pruss_xchg->config[0].trigger & 0x1) + ; + } +} +void endat_recovery_time_conversion(struct endat_priv *priv) +{ + /* RT: convert cycle to ns */ + priv->pruss_xchg->endat_ch0_rt = priv->pruss_xchg->endat_ch0_rt * ((float)(1000000000)/priv->pruss_xchg->icssg_clk); + priv->pruss_xchg->endat_ch1_rt = priv->pruss_xchg->endat_ch1_rt * ((float)(1000000000)/priv->pruss_xchg->icssg_clk); + priv->pruss_xchg->endat_ch2_rt = priv->pruss_xchg->endat_ch2_rt * ((float)(1000000000)/priv->pruss_xchg->icssg_clk); + +} + +int32_t endat_command_process(struct endat_priv *priv, int32_t cmd, + struct cmd_supplement *cmd_supplement) +{ + cmd = endat_command_build(priv, cmd, cmd_supplement); + + if(cmd < 0) + { + return cmd; + } + + endat_command_send(priv); + endat_command_wait(priv); + /* RT configuration(convert cycle to ns time ) for command 2.2*/ + if( cmd > 7 && cmd < 15 ) + { + endat_recovery_time_conversion(priv); + } + return cmd; +} + +int32_t endat_get_2_2_angle(struct endat_priv *priv) +{ + int32_t pos; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + int32_t ch = priv->channel; + + + if(!(pruss_xchg->ch[ch].crc.status & ENDAT_CRC_DATA)) + { + return -1; + } + + pos = pruss_xchg->ch[ch].pos_word0; + +#ifdef __TI_ARM__ + pos = __rbit(pos); +#else + asm("rbit %0,%1" : "=r"(pos) : "r"(pos)); +#endif + + /* verify F1 = 0 & F2 = 1 */ + if((pos & 0x3) != 0x2) + { + return -1; + } + + /* discard F1, F2 */ + pos >>= 2; + + /* mask non-angular bits */ + pos &= (1 << priv->single_turn_res) - 1; + return pos; +} + +static int32_t endat_get_pos_res(struct endat_priv *priv) +{ + int32_t cmd; + struct cmd_supplement cmd_supplement; + uint32_t word; + int32_t ch = priv->channel; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + /* select memory area encoder manufacturer page 0 */ + cmd = 2, cmd_supplement.address = MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE0; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw, absence of delay here resulted in wrong values for pos_res */ + ClockP_usleep(1000 * 12); + + /* send parameter for word13 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_13; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + word = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) & (( + 1 << ENDAT_NUM_BITS_PARAMETER) - 1); + return word &= (1 << ENDAT_NUM_BITS_VALID_PAGE0_WORD13) - 1; +} + +static int32_t endat_get_multi_turn_res(struct endat_priv *priv) +{ + int32_t cmd; + struct cmd_supplement cmd_supplement; + uint32_t word; + int32_t ch = priv->channel; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + /* select memory area encoder manufacturer page 0 */ + cmd = 2, cmd_supplement.address = MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE1; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 12); + + /* send parameter for word1 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_1; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + word = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) & (( + 1 << ENDAT_NUM_BITS_PARAMETER) - 1); + return word &= (1 << ENDAT_NUM_BITS_VALID_PAGE1_WORD1) - 1; +} + +static int32_t endat_get_id(struct endat_priv *priv) +{ + int32_t cmd; + struct cmd_supplement cmd_supplement; + uint32_t word0, word1, word2; + int32_t ch = priv->channel; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + /* select memory area encoder manufacturer page 1 */ + cmd = 2, cmd_supplement.address = MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE1; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 12); + + /* send parameter for word8 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_8; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + word0 = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) + & ((1 << ENDAT_NUM_BITS_PARAMETER) - 1); + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + /* send parameter for word9 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_9; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + word1 = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) + & ((1 << ENDAT_NUM_BITS_PARAMETER) - 1); + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + /* send parameter for word10 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_10; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + word2 = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) + & ((1 << ENDAT_NUM_BITS_PARAMETER) - 1); + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + priv->id.binary = word1 | word2 << 16; + /* swap the two ascii's so that printing as string will give what is required */ + priv->id.ascii = ((word0 & 0xFF) << 8) | ((word0 & 0xFF00) >> 8); + + return 0; +} + +static int32_t endat_get_sn(struct endat_priv *priv) +{ + int32_t cmd; + struct cmd_supplement cmd_supplement; + uint32_t word0, word1, word2; + int32_t ch = priv->channel; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + /* select memory area encoder manufacturer page 1 */ + cmd = 2, cmd_supplement.address = MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE1; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 12); + + /* send parameter for word11 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_11; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + word0 = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) + & ((1 << ENDAT_NUM_BITS_PARAMETER) - 1); + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + /* send parameter for word12 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_12; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + word1 = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) + & ((1 << ENDAT_NUM_BITS_PARAMETER) - 1); + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + /* send parameter for word13 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_13; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + word2 = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) + & ((1 << ENDAT_NUM_BITS_PARAMETER) - 1); + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + priv->sn.ascii_lsb = word0 & 0xFF; + priv->sn.binary = ((word0 & 0xFF00) >> 8) | (word1 << 8) | (( + word2 & 0xFF) << 24); + priv->sn.ascii_msb = (word2 & 0xFF00) >> 8; + + return 0; +} + +static int32_t endat_get_command_set(struct endat_priv *priv) +{ + int32_t cmd; + struct cmd_supplement cmd_supplement; + uint32_t word; + int32_t ch = priv->channel; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + /* select memory area encoder manufacturer page 2 */ + cmd = 2, cmd_supplement.address = MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE2; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 12); + + /* send parameter for word5 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_5; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + word = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) & (( + 1 << ENDAT_NUM_BITS_PARAMETER) - 1); + priv->cmd_set_2_2 = (word & 0x1) && !(word & 0x2); + priv->has_safety = (word & 0x4) && !(word & 0x8); + + return 0; +} + +static int32_t endat_get_type(struct endat_priv *priv) +{ + int32_t cmd; + struct cmd_supplement cmd_supplement; + uint32_t word; + int32_t ch = priv->channel; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + /* select memory area encoder manufacturer page 0 */ + cmd = 2, cmd_supplement.address = MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE0; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw, absence of delay here resulted in wrong values for pos_res */ + ClockP_usleep(1000 * 12); + + /* send parameter for word13 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_14; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + + word = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) & (( + 1 << ENDAT_NUM_BITS_PARAMETER) - 1); + priv->type = (word & (1 << 15)) ? rotary : linear; + + return 0; +} + +static int32_t endat_get_step(struct endat_priv *priv) +{ + int32_t cmd; + struct cmd_supplement cmd_supplement; + uint32_t word; + int32_t ch = priv->channel; + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + /* select memory area encoder manufacturer page 0 */ + cmd = 2, cmd_supplement.address = MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE1; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 12); + + /* send parameter for word4 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_4; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + word = (pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) & (( + 1 << ENDAT_NUM_BITS_PARAMETER) - 1); + + /* send parameter for word5 */ + cmd = 4, cmd_supplement.address = APP_ENDAT_WORD_5; + + if(endat_command_process(priv, cmd, &cmd_supplement) < 0) + { + return -EINVAL; + } + + /* delay copied from fw */ + ClockP_usleep(1000 * 2); + word |= ((pruss_xchg->ch[ch].pos_word0 >> (ENDAT_NUM_BITS_POSITION_CRC)) + & ((1 << ENDAT_NUM_BITS_PARAMETER) - 1)) << 16; + + return word; +} + +int32_t endat_get_encoder_info(struct endat_priv *priv) +{ + int32_t ret; + + priv->pos_res = endat_get_pos_res(priv); + + if(priv->pos_res < 0) + { + return priv->pos_res; + } + + priv->multi_turn_res = endat_get_multi_turn_res(priv); + + if(priv->multi_turn_res < 0) + { + return priv->multi_turn_res; + } + + else if(!priv->multi_turn_res) + { + priv->single_turn_res = priv->pos_res; + } + + else + { + priv->multi_turn_res = log2(priv->multi_turn_res); + priv->single_turn_res = priv->pos_res - priv->multi_turn_res; + } + + priv->step = endat_get_step(priv); + + if(priv->step < 0) + { + return priv->step; + } + /*calaculate rx frame size for all three channels and store in different variables*/ + if(!priv->load_share) + { + priv->pos_rx_bits_21_RTUPRU = priv->pos_res + ENDAT_NUM_BITS_POSITION_CRC + + ENDAT_NUM_BITS_F1; + priv->pos_rx_bits_22_RTUPRU = priv->pos_rx_bits_21_RTUPRU + ENDAT_NUM_BITS_F2; + + } + else if(priv->channel==0) /*ch0*/ + { + priv->pos_rx_bits_21_RTUPRU = priv->pos_res + ENDAT_NUM_BITS_POSITION_CRC + + ENDAT_NUM_BITS_F1; + priv->pos_rx_bits_22_RTUPRU = priv->pos_rx_bits_21_RTUPRU + ENDAT_NUM_BITS_F2; + } + else if(priv->channel==1) /*ch1*/ + { + priv->pos_rx_bits_21_PRU = priv->pos_res + ENDAT_NUM_BITS_POSITION_CRC + + ENDAT_NUM_BITS_F1; + priv->pos_rx_bits_22_PRU = priv->pos_rx_bits_21_PRU + ENDAT_NUM_BITS_F2;} + else + { + priv->pos_rx_bits_21_TXPRU = priv->pos_res + ENDAT_NUM_BITS_POSITION_CRC + + ENDAT_NUM_BITS_F1; + priv->pos_rx_bits_22_TXPRU = priv->pos_rx_bits_21_TXPRU + ENDAT_NUM_BITS_F2; + } /*ch2*/ + + ret = endat_get_id(priv); + + if(ret) + { + return ret; + } + + ret = endat_get_sn(priv); + + if(ret) + { + return ret; + } + + ret = endat_get_type(priv); + + if(ret) + { + return ret; + } + + ret = endat_get_command_set(priv); + + if(ret) + { + return ret; + } + + return 0; +} + +uint32_t endat_get_prop_delay(struct endat_priv *priv) +{ + return priv->pruss_xchg->ch[priv->channel].prop_delay; +} + +void endat_addinfo_track(struct endat_priv *priv, int32_t cmd, + struct cmd_supplement *cmd_supplement) +{ + int32_t c7_c4, c3_c0; + + /* reset stops additional info's */ + if(cmd == 5) + { + priv->flags.info1 = FALSE, priv->flags.info2 = FALSE; + } + + if(cmd != 9) + { + return; + } + + c7_c4 = (cmd_supplement->address & ENDAT_MRS_MASK_SELECT_ADDITIONAL_INFO) >> + ENDAT_MRS_SHIFT_C7_C4; + c3_c0 = cmd_supplement->address & ENDAT_MRS_MASK_STOP_ADDITIONAL_INFO; + + if(c7_c4 == ENDAT_MRS_VAL_C7_C4_SELECT_ADDITIONAL_INFO1) + { + if(c3_c0 == ENDAT_MRS_VAL_STOP_ADDITIONAL_INFO) + { + priv->flags.info1 = FALSE; + } + + else + { + priv->flags.info1 = TRUE; + } + } + + c7_c4 = (cmd_supplement->address & ENDAT_MRS_MASK_SELECT_ADDITIONAL_INFO) >> + ENDAT_MRS_SHIFT_C7_C4; + c3_c0 = cmd_supplement->address & ENDAT_MRS_MASK_STOP_ADDITIONAL_INFO; + + if(c7_c4 == ENDAT_MRS_VAL_C7_C4_SELECT_ADDITIONAL_INFO2) + { + if(c3_c0 == ENDAT_MRS_VAL_STOP_ADDITIONAL_INFO) + { + priv->flags.info2 = FALSE; + } + + else + { + priv->flags.info2 = TRUE; + } + } +} + +static void endat_config_global_rx_arm_cnt(struct endat_priv *priv, + uint16_t val) +{ + void *pruss_cfg = priv->pruss_cfg; + if(priv->pruicss_slicex) + { + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH0CFG1REGISTER + 2, val); + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH1CFG1REGISTER + 2, val); + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH2CFG1REGISTER + 2, val); + } + else + { + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH0CFG1REGISTER + 2, val); + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH1CFG1REGISTER + 2, val); + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH2CFG1REGISTER + 2, val); + } +} + +void endat_config_rx_arm_cnt(struct endat_priv *priv, uint16_t val) +{ + void *pruss_cfg = priv->pruss_cfg; + int32_t ch = priv->channel; + if(priv->pruicss_slicex) + { + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH0CFG1REGISTER + ch * 8 + 2, val); + } + else + { + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH0CFG1REGISTER + ch * 8 + 2, val); + } +} + +void endat_config_wire_delay(struct endat_priv *priv, uint16_t val) +{ + void *pruss_cfg = priv->pruss_cfg; + int32_t ch = priv->channel; + uint16_t regval; + if(priv->pruicss_slicex) + { + regval = HW_RD_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH0CFG0REGISTER + ch * + 8); + } + else + { + regval = HW_RD_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH0CFG0REGISTER + ch * + 8); + } + + /* clear wire delay bits, keep other bits as is */ + regval &= 0xF800; + /* restrict wire delay to wire delay bits only */ + val &= 0x7FF; + regval |= val; + if(priv->pruicss_slicex) + { + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH0CFG0REGISTER + ch * 8, regval); + } + else + { + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH0CFG0REGISTER + ch * 8, regval); + } +} + +void endat_config_clock(struct endat_priv *priv, + struct endat_clk_cfg *clk_cfg) +{ + void *pruss_cfg = priv->pruss_cfg; + /* Set PRU1_ED_RX_SB_POL polarity bit, required for ICSSG (don't care for ICSSM) */ + if(priv->pruicss_slicex) + { + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, clk_cfg->rx_div << 16 | 0x8 | + clk_cfg->rx_div_attr); + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER + 2, clk_cfg->tx_div); + } + else + { + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0RXCFGREGISTER, clk_cfg->rx_div << 16 | 0x8 | + clk_cfg->rx_div_attr); + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER + 2, clk_cfg->tx_div); + } + + + +} + +void endat_config_tst_delay(struct endat_priv *priv, uint16_t delay) +{ + void *pruss_cfg = priv->pruss_cfg; + int32_t ch = priv->channel; + if(priv->pruicss_slicex==1) + { + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH0CFG1REGISTER + ch * 8, delay); + } + else + { + HW_WR_REG16((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH0CFG1REGISTER + ch * 8, delay); + } + +} + +void endat_config_rx_clock_disable(struct endat_priv *priv, + uint16_t val) +{ + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + int32_t ch = priv->channel; + + pruss_xchg->ch[ch].rx_clk_less = val; +} + +static void endat_set_continuous_mode(struct endat_priv *priv) +{ + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + pruss_xchg->config[0].trigger |= (0x1 << 7 | 0x1); +} + +static void endat_clear_continuous_mode(struct endat_priv *priv) +{ + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + pruss_xchg->config[0].trigger &= ~(0x1 << 7); +} + +int32_t endat_start_continuous_mode(struct endat_priv *priv) +{ + int32_t cmd; + + cmd = endat_command_build(priv, 1, NULL); + + if(cmd < 0) + { + return cmd; + } + + endat_set_continuous_mode(priv); + + return cmd; +} + +void endat_stop_continuous_mode(struct endat_priv *priv) +{ + endat_clear_continuous_mode(priv); + endat_command_wait(priv); +} + +void endat_config_host_trigger(struct endat_priv *priv) +{ + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + /*for loadshare mode trigger set based on connected channels*/ + if(priv->load_share) + { + pruss_xchg->config[0].opmode=(pruss_xchg->config[0].channel&(1<<0))?0x1:0; + pruss_xchg->config[1].opmode=(pruss_xchg->config[1].channel&(1<<1))?0x1:0; + pruss_xchg->config[2].opmode=(pruss_xchg->config[2].channel&(1<<2))?0x1:0; + } + else + { + pruss_xchg->config[0].opmode = 0x1; + } +} + +void endat_config_periodic_trigger(struct endat_priv *priv) +{ + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + pruss_xchg->config[0].opmode = 0; +} + +void endat_config_channel(struct endat_priv *priv, int32_t ch) +{ + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + pruss_xchg->config[0].channel = 1 << ch; + priv->channel = ch; +} + +void endat_config_multi_channel_mask(struct endat_priv *priv, + uint8_t mask, + uint8_t loadshare) +{ + priv->load_share = loadshare; + + if(loadshare) + { + priv->pruss_xchg->config[0].channel = mask&(1<<0); + priv->pruss_xchg->config[1].channel = mask&(1<<1); + priv->pruss_xchg->config[2].channel = mask&(1<<2); + endat_config_primary_core_mask(priv, mask);/*select primary core for global configuration*/ + endat_config_syn_bits(priv, mask); /* configure syn bits for synchronization before any global config*/ + endat_enable_load_share_mode(priv); /*ENABLE SHARE MODE*/ + } + else + { + priv->pruss_xchg->config[0].channel = mask; + } +} + +void endat_config_syn_bits(struct endat_priv *priv, uint8_t mask) +{ + priv->pruss_xchg->endat_ch0_syn_bit=mask&(1<<0)?0x1:0; + priv->pruss_xchg->endat_ch1_syn_bit=mask&(1<<1)?0x2:0; + priv->pruss_xchg->endat_ch2_syn_bit=mask&(1<<2)?0x4:0; +} +void endat_enable_load_share_mode(struct endat_priv *priv) +{ + void *pruss_cfg = priv->pruss_cfg; + //HW_WR_REG32(0x30026104) |= 0x0800; + uint32_t rgval; + if(priv->pruicss_slicex) + { + rgval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER); + rgval |= CSL_ICSSCFG_EDPRU1TXCFGREGISTER_PRU1_ENDAT_SHARE_EN_MASK; + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, rgval); + } + else + { + rgval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER); + rgval |= CSL_ICSSCFG_EDPRU0TXCFGREGISTER_PRU0_ENDAT_SHARE_EN_MASK; + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER, rgval); + } + +} +void endat_config_primary_core_mask(struct endat_priv *priv, uint8_t mask) +{ + switch (mask) + { + + case 1: /*only channel0 connected*/ + priv->pruss_xchg->endat_primary_core_mask=0x1; + break; + case 2: /*channel1 connected*/ + priv->pruss_xchg->endat_primary_core_mask=0x2; + break; + case 3: /*channel0 and channel1 connected*/ + priv->pruss_xchg->endat_primary_core_mask=0x1; + break; + case 4: /*channel2 connected*/ + priv->pruss_xchg->endat_primary_core_mask=0x4; + break; + case 5: /*channel0 and channel2 connnected*/ + priv->pruss_xchg->endat_primary_core_mask=0x4; + break; + case 6: /*channel1 and channel2 connected*/ + priv->pruss_xchg->endat_primary_core_mask=0X4; + break; + case 7: /*all three channel connected*/ + priv->pruss_xchg->endat_primary_core_mask=0x4; + break; + + } + +} +uint8_t endat_multi_channel_detected(struct endat_priv *priv) +{ if(priv->load_share) + return (priv->pruss_xchg->config[0].channel|priv->pruss_xchg->config[1].channel|priv->pruss_xchg->config[2].channel); + else + return priv->pruss_xchg->config[0].channel; + +} + +void endat_multi_channel_set_cur(struct endat_priv *priv, int32_t ch) +{ + priv->channel = ch; +} + +int32_t endat_wait_initialization(struct endat_priv *priv, uint32_t timeout, uint8_t mask) +{ + int32_t i; + + struct endat_pruss_xchg *pruss_xchg = priv->pruss_xchg; + + for(i = 0; i < timeout; i++) + { + + + if(priv->load_share) /* for loadshare mode*/ + { + switch (mask) { + + case 1: /*channel 0 connected*/ + if((pruss_xchg->config[0].status & 1)) + return 0; + + break; + case 2: /*channel 1 connected*/ + if((pruss_xchg->config[1].status & 1)) + return 0; + break; + case 3: /*channel 0 and 1 connected*/ + if((pruss_xchg->config[0].status & 1)&&(pruss_xchg->config[1].status & 1)) + return 0; + break; + case 4: /*channel 2 connected*/ + if((pruss_xchg->config[2].status & 1)) + return 0; + break; + case 5: /*channel 0 and 2 connnected*/ + if((pruss_xchg->config[0].status & 1)&&(pruss_xchg->config[2].status & 1)) + return 0; + break; + case 6: /*channel 1 and 2 connected*/ + if((pruss_xchg->config[1].status & 1)&&(pruss_xchg->config[2].status & 1)) + return 0; + break; + case 7: /*all three channel connected*/ + if((pruss_xchg->config[0].status & 1)&&(pruss_xchg->config[1].status & 1)&&( pruss_xchg->config[2].status & 1)) + return 0; + break; + } + ClockP_usleep(1000 * 1); + + } + else if(pruss_xchg->config[0].status & 1) + { + break; + } + else + { + ClockP_usleep(1000 * 1); + } + } + + if(i == timeout) + { + return -1; + } + + return 0; +} + +static inline void endat_config_clr_cfg0(struct endat_priv *priv) +{ + void *pruss_cfg = priv->pruss_cfg; + if(priv->pruicss_slicex) + { + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH0CFG0REGISTER, 0); + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH1CFG0REGISTER, 0); + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1CH2CFG0REGISTER, 0); + } + else + { + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH0CFG0REGISTER, 0); + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH1CFG0REGISTER, 0); + HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0CH2CFG0REGISTER, 0); + } +} + +static inline void endat_config_endat_mode(struct endat_priv *priv) +{ + void *pruss_cfg = priv->pruss_cfg; + if(priv->pruicss_slicex) + { + HW_WR_REG8((uint8_t *)pruss_cfg + CSL_ICSSCFG_GPCFG1 + 3, 4); + } + else + { + HW_WR_REG8((uint8_t *)pruss_cfg + CSL_ICSSCFG_GPCFG0 + 3, 4); + } +} + +static void endat_hw_init(struct endat_priv *priv) +{ + struct endat_clk_cfg clk_cfg; + + /* set initial clock to 200KHz */ + /* 192MHz / 200KHz - 1 */ + clk_cfg.tx_div = 959; + /* 192MHz / 200KHz / 8 - 1 */ + clk_cfg.rx_div = 119; + /* 2T */ + clk_cfg.rx_en_cnt = 10000; + /* sample size 8 */ + clk_cfg.rx_div_attr = 7; + + endat_config_endat_mode(priv); + endat_config_clock(priv, &clk_cfg); + endat_config_global_rx_arm_cnt(priv, clk_cfg.rx_en_cnt); + endat_config_clr_cfg0(priv); +} + +struct endat_priv *endat_init(struct endat_pruss_xchg *pruss_xchg, + void *pruss_cfg, int32_t slice) +{ + + endat_priv.pruss_xchg = pruss_xchg; + endat_priv.pruss_cfg = pruss_cfg; + endat_priv.pruicss_slicex = slice; + endat_hw_init(&endat_priv); + return &endat_priv; +} + +uint32_t endat_get_recovery_time(struct endat_priv *priv) +{ + if(priv->channel == 0) + { + return priv->pruss_xchg->endat_ch0_rt; + } + else if (priv->channel == 1) + { + return priv->pruss_xchg->endat_ch1_rt; + } + else + { + return priv->pruss_xchg->endat_ch2_rt; + } +} diff --git a/source/motor_control/position_sense/endat/firmware/Readme.txt b/source/motor_control/position_sense/endat/firmware/Readme.txt new file mode 100644 index 0000000..539cc74 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/Readme.txt @@ -0,0 +1,6 @@ +Steps for generating ENDAT binary header files is given below. +1. In the make file, porovide correct paths for CCS(CCS_PATH) and code generation tool(CG_TOOL_ROOT). +2. Provide the required mode as shown below. If user does not provide input, default mode taken is SINGLE. + $(MCU_PLUS_SDK_PATH)\source\motor_control\position_sense\endat\firmware>gmake all CHANNELS=SINGLE + $(MCU_PLUS_SDK_PATH)\source\motor_control\position_sense\endat\firmware>gmake all CHANNELS=MULTI +3. Above step will generate either endat_master_bin.h or endat_master_multi_bin.h. \ No newline at end of file diff --git a/source/motor_control/position_sense/endat/firmware/endat_diagnostic.cmd b/source/motor_control/position_sense/endat/firmware/endat_diagnostic.cmd new file mode 100644 index 0000000..cce8931 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_diagnostic.cmd @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +MEMORY +{ + PAGE 0: + PRUIMEM: o = 0x00000000 l = 0x00001800 /* 6kB PRU Instruction RAM */ + PAGE 1: + PRUDMEM: o = 0x00000000 l = 0x00002000 /* 8kB PRU Data RAM */ +} + +SECTIONS +{ + .text > PRUIMEM, PAGE 0 +} diff --git a/source/motor_control/position_sense/endat/firmware/endat_icss_reg_defs.h b/source/motor_control/position_sense/endat/firmware/endat_icss_reg_defs.h new file mode 100644 index 0000000..93e3687 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_icss_reg_defs.h @@ -0,0 +1,87 @@ + +; +; Copyright (C) 2021-23 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + + .include "../../../../pru_io/firmware/common/icss_regs.inc" + .include "../../../../pru_io/firmware/common/icss_cfg_regs.inc" + + .asg R30.t24, ENDAT_CH0_RX_EN + .asg R31.t27, ENDAT_CH0_RX_CLR_OVF + .asg R31.t24, ENDAT_CH0_RX_CLR_VALID + .asg R31.t27, ENDAT_CH0_RX_OVF + .asg R31.t24, ENDAT_CH0_RX_VALID + + .asg R30.t25, ENDAT_CH1_RX_EN + .asg R31.t28, ENDAT_CH1_RX_CLR_OVF + .asg R31.t25, ENDAT_CH1_RX_CLR_VALID + .asg R31.t28, ENDAT_CH1_RX_OVF + .asg R31.t25, ENDAT_CH1_RX_VALID + + .asg R30.t26, ENDAT_CH2_RX_EN + .asg R31.t29, ENDAT_CH2_RX_CLR_OVF + .asg R31.t26, ENDAT_CH2_RX_CLR_VALID + .asg R31.t29, ENDAT_CH2_RX_OVF + .asg R31.t26, ENDAT_CH2_RX_VALID + + +; Channel select bits R30[17:16] +ENDAT_TX_CH0_SEL .set 0 +ENDAT_TX_CH1_SEL .set 1 +ENDAT_TX_CH2_SEL .set 2 + +; CLK MODE bits R30[20:19] +ENDAT_TX_CLK_MODE_FREERUN_STOPLOW .set (0 << 3) +ENDAT_TX_CLK_MODE_FREERUN_STOPHIGH .set (1 << 3) +ENDAT_TX_CLK_MODE_FREERUN .set (2 << 3) +ENDAT_TX_CLK_MODE_STOPHIGH_AFTER_TX .set (3 << 3) + + .asg R31.t18, ENDAT_TX_CHANNEL_GO + .asg R31.t19, ENDAT_TX_GLOBAL_REINIT + .asg R31.t20, ENDAT_TX_GLOBAL_GO + + .asg R31.t5, ENDAT_CH0_TX_GLOBAL_REINIT_ACTIVE + .asg R31.t5, ENDAT_CH0_TX_BUSY + .asg R31.t0, ENDAT_CH0_TX_OVERUN + .asg R31.t1, ENDAT_CH0_TX_UNDERRUN + + .asg R31.t13, ENDAT_CH1_TX_GLOBAL_REINIT_ACTIVE + .asg R31.t13, ENDAT_CH1_TX_BUSY + .asg R31.t8, ENDAT_CH1_TX_OVERUN + .asg R31.t9, ENDAT_CH1_TX_UNDERRUN + + .asg R31.t21, ENDAT_CH2_TX_GLOBAL_REINIT_ACTIVE + .asg R31.t21, ENDAT_CH2_TX_BUSY + .asg R31.t16, ENDAT_CH2_TX_OVERUN + .asg R31.t17, ENDAT_CH2_TX_UNDERRUN + + +; ENDAT diff --git a/source/motor_control/position_sense/endat/firmware/endat_interface.h b/source/motor_control/position_sense/endat/firmware/endat_interface.h new file mode 100644 index 0000000..75abe30 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_interface.h @@ -0,0 +1,166 @@ + +; +; Copyright (C) 2021-23 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;offsets for ch0 (without loadshare mode use these ch0 offset for all three channels) +ENDAT_CH0_OPMODE_CONFIG_OFFSET .set 0x0 ; 0: PRU trigger 1: Host trigger +ENDAT_CH0_CHANNEL_CONFIG_OFFSET .set 0x1 ; Select single channel (1, 2, 3 or Multi (0))- Not implemented yet +ENDAT_CH0_INTFC_CMD_TRIGGER_OFFSET .set 0x2 ; Command trigger indication to firmware +ENDAT_CH0_INTFC_CMD_STATUS_OFFSET .set 0x3 ; Status word for channel busy indication etc - Not used now + +;offsets for ch1 with loadshare mode, without loadshare mode no use for this offset configuration +ENDAT_CH1_OPMODE_CONFIG_OFFSET .set 0x4 ; 0: PRU trigger 1: Host trigger +ENDAT_CH1_CHANNEL_CONFIG_OFFSET .set 0x5 ; Select single channel 1 +ENDAT_CH1_INTFC_CMD_TRIGGER_OFFSET .set 0x6 ; Command trigger indication to firmware +ENDAT_CH1_INTFC_CMD_STATUS_OFFSET .set 0x7 ; Status word for channel busy indication etc - Not used now + +;offsets for ch2 with loadshare mode, +ENDAT_CH2_OPMODE_CONFIG_OFFSET .set 0x8 ; 0: PRU trigger 1: Host trigger +ENDAT_CH2_CHANNEL_CONFIG_OFFSET .set 0x9 ; Select single channel 2 +ENDAT_CH2_INTFC_CMD_TRIGGER_OFFSET .set 0xA ; Command trigger indication to firmware +ENDAT_CH2_INTFC_CMD_STATUS_OFFSET .set 0xB ; Status word for channel busy indication etc - Not used now + +;Command offset for ch0 and (command offset for all three channels in without load share mode) +ENDAT_CH0_CMD_WORD_0_OFFSET .set 0xC ; Command parameters for firmware +ENDAT_CH0_CMD_WORD_0_CMDNADDR_OFFSET .set 0xC ; 1-bit dummy + 6-bits command mode + 9 bits (address + 1-bit param) +ENDAT_CH0_CMD_WORD_0_PARAM_OFFSET .set 0xE ; 15-bit params + + +ENDAT_CH0_CMD_WORD_1_OFFSET .set 0x10 ; Command parameters for firmware +ENDAT_CH0_CMD_WORD_1_RXBITS_OFFSET .set 0x10 ; Number of bits to receive in command response for ch1 +ENDAT_CH0_CMD_WORD_1_TXBITS_OFFSET .set 0x11 ; Number of bits to transmit to encoder +ENDAT_CH0_CMD_WORD_1_CMDTYP_OFFSET .set 0x12 ; 0: EnDat2.2 otherwise: EnDat2.1 or ENDAT_CMD_SEND_POSVAL_WITH_DATA +ENDAT_CH0_CMD_WORD_1_BLKLEN_OFFSET .set 0x13 ; Block address length in bytes, 0 if not present + +ENDAT_CH0_CMD_WORD_2_OFFSET .set 0x14 ; Command parameters for firmware - 2.2 command supplement +ENDAT_CH0_CMD_WORD_2_ADDR_OFFSET .set 0x14 ; 8-bit address +ENDAT_CH0_CMD_WORD_2_PARAM_OFFSET .set 0x15 ; 16-bit data +ENDAT_CH0_CMD_WORD_2_BLKADDR_OFFSET .set 0x17 ; 8-bit optional block address + +;Command offset for ch1, use only with loadshare +ENDAT_CH1_CMD_WORD_0_OFFSET .set 0x18 ; Command parameters for firmware +ENDAT_CH1_CMD_WORD_0_CMDNADDR_OFFSET .set 0x18 ; 1-bit dummy + 6-bits command mode + 9 bits (address + 1-bit param) +ENDAT_CH1_CMD_WORD_0_PARAM_OFFSET .set 0x1A ; 15-bit params + + +ENDAT_CH1_CMD_WORD_1_OFFSET .set 0x1C ; Command parameters for firmware +ENDAT_CH1_CMD_WORD_1_RXBITS_OFFSET .set 0x1C ; Number of bits to receive in command response for ch1 +ENDAT_CH1_CMD_WORD_1_TXBITS_OFFSET .set 0x1D ; Number of bits to transmit to encoder +ENDAT_CH1_CMD_WORD_1_CMDTYP_OFFSET .set 0x1E ; 0: EnDat2.2 otherwise: EnDat2.1 or ENDAT_CMD_SEND_POSVAL_WITH_DATA +ENDAT_CH1_CMD_WORD_1_BLKLEN_OFFSET .set 0x1F ; Block address length in bytes, 0 if not present + +ENDAT_CH1_CMD_WORD_2_OFFSET .set 0x20 ; Command parameters for firmware - 2.2 command supplement +ENDAT_CH1_CMD_WORD_2_ADDR_OFFSET .set 0x20 ; 8-bit address +ENDAT_CH1_CMD_WORD_2_PARAM_OFFSET .set 0x21 ; 16-bit data +ENDAT_CH1_CMD_WORD_2_BLKADDR_OFFSET .set 0x23 ; 8-bit optional block address + +;Command offset for ch2, use only with loadshare +ENDAT_CH2_CMD_WORD_0_OFFSET .set 0x24 ; Command parameters for firmware +ENDAT_CH2_CMD_WORD_0_CMDNADDR_OFFSET .set 0x24 ; 1-bit dummy + 6-bits command mode + 9 bits (address + 1-bit param) +ENDAT_CH2_CMD_WORD_0_PARAM_OFFSET .set 0x26 ; 15-bit params + + +ENDAT_CH2_CMD_WORD_1_OFFSET .set 0x28 ; Command parameters for firmware +ENDAT_CH2_CMD_WORD_1_RXBITS_OFFSET .set 0x28 ; Number of bits to receive in command response for ch1 +ENDAT_CH2_CMD_WORD_1_TXBITS_OFFSET .set 0x29 ; Number of bits to transmit to encoder +ENDAT_CH2_CMD_WORD_1_CMDTYP_OFFSET .set 0x2A ; 0: EnDat2.2 otherwise: EnDat2.1 or ENDAT_CMD_SEND_POSVAL_WITH_DATA +ENDAT_CH2_CMD_WORD_1_BLKLEN_OFFSET .set 0x2B ; Block address length in bytes, 0 if not present + +ENDAT_CH2_CMD_WORD_2_OFFSET .set 0x2C ; Command parameters for firmware - 2.2 command supplement +ENDAT_CH2_CMD_WORD_2_ADDR_OFFSET .set 0x2C ; 8-bit address +ENDAT_CH2_CMD_WORD_2_PARAM_OFFSET .set 0x2D ; 16-bit data +ENDAT_CH2_CMD_WORD_2_BLKADDR_OFFSET .set 0x2F ; 8-bit optional block address + + +; NOTE: For ENDAT_CHx_POSITION_DATA_LSW_OFFSET: Bit0 is Error flag (EnDat2.1) and Bit0,Bit1 are Error flags (EnDat2.2) +; CH0 registers +ENDAT_CH0_POSITION_DATA_WORD0_OFFSET .set 0x30 +ENDAT_CH0_POSITION_DATA_WORD1_OFFSET .set 0x34 +ENDAT_CH0_POSITION_DATA_WORD2_OFFSET .set 0x38 +ENDAT_CH0_POSITION_DATA_WORD3_OFFSET .set 0x3C +ENDAT_CH0_CRC_ERR_COUNTER_OFFSET .set 0X40 ; CRC error count +ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET .set 0X44 +ENDAT_CH0_ENDAT22_STAT_OFFSET .set 0x45 +ENDAT_CH0_CLOCK_LESS_FOR_TD .set 0x46 +ENDAT_CH0_MEAS_PROPDELAY_OFFSET .set 0x48 + +; CH1 registers +ENDAT_CH1_POSITION_DATA_WORD0_OFFSET .set 0x50 +ENDAT_CH1_POSITION_DATA_WORD1_OFFSET .set 0x54 +ENDAT_CH1_POSITION_DATA_WORD2_OFFSET .set 0x58 +ENDAT_CH1_POSITION_DATA_WORD3_OFFSET .set 0X5C +ENDAT_CH1_CRC_ERR_COUNTER_OFFSET .set 0x60 ; CRC error count +ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET .set 0x64 +ENDAT_CH1_ENDAT22_STAT_OFFSET .set 0x65 +ENDAT_CH1_CLOCK_LESS_FOR_TD .set 0x66 +ENDAT_CH1_MEAS_PROPDELAY_OFFSET .set 0x68 + +; CH2 registers +ENDAT_CH2_POSITION_DATA_WORD0_OFFSET .set 0x70 +ENDAT_CH2_POSITION_DATA_WORD1_OFFSET .set 0x74 +ENDAT_CH2_POSITION_DATA_WORD2_OFFSET .set 0x78 +ENDAT_CH2_POSITION_DATA_WORD3_OFFSET .set 0x7C +ENDAT_CH2_CRC_ERR_COUNTER_OFFSET .set 0x80 ; CRC error count +ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET .set 0x84 +ENDAT_CH2_ENDAT22_STAT_OFFSET .set 0x85 +ENDAT_CH2_CLOCK_LESS_FOR_TD .set 0x86 +ENDAT_CH2_MEAS_PROPDELAY_OFFSET .set 0x88 + +; clock configuration +ENDAT_CONFIG_CLOCK_RX_OFFSET .set 0x90 ; clock to be configure for rx = tx * oversample rate +ENDAT_CONFIG_CLOCK_TX_OFFSET .set 0x92 ; clock to be configure for tx +ENDAT_CONFIG_CLOCK_RX_EN_CNT_OFFSET .set 0x94 ; rx arm delay + +; Delay Configuration +ENDAT_CONFIG_DELAY_125NS_OFFSET .set 0x98 +ENDAT_CONFIG_DELAY_5US_OFFSET .set 0x9C +ENDAT_CONFIG_DELAY_51US_OFFSET .set 0xA0 +ENDAT_CONFIG_DELAY_1MS_OFFSET .set 0xA4 +ENDAT_CONFIG_DELAY_2MS_OFFSET .set 0xA8 ; delay for 2ms counter +ENDAT_CONFIG_DELAY_12MS_OFFSET .set 0xAC ; delay for 12ms counter +ENDAT_CONFIG_DELAY_50MS_OFFSET .set 0xB0 ; delay for 20ms counter +ENDAT_CONFIG_DELAY_380MS_OFFSET .set 0xB4 +ENDAT_CONFIG_DELAY_900MS_OFFSET .set 0XB8 + +; mask for core set +MASK_FOR_PRIMARY_CORE .set 0xBC +;rx complete status +ENDAT_CH0_CONFIG_SYN_BIT .set 0xBD ;0th bit for ch0 +ENDAT_CH1_CONFIG_SYN_BIT .set 0xBE ;0th bit for ch0 +ENDAT_CH2_CONFIG_SYN_BIT .set 0xBF ;0th bit for ch0 +; Recovery Time +ENDAT_CH0_RT_OFFSET .set 0xC0 ; +ENDAT_CH1_RT_OFFSET .set 0xC4 ; +ENDAT_CH2_RT_OFFSET .set 0xC8 ; + +;icssgclock +PRUICSSG_CLOCK .set 0xCD; + diff --git a/source/motor_control/position_sense/endat/firmware/endat_main.asm b/source/motor_control/position_sense/endat/firmware/endat_main.asm new file mode 100644 index 0000000..c599783 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_main.asm @@ -0,0 +1,2809 @@ + +; +; Copyright (C) 2021-23 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + +CALL .macro function + JAL R29.w0, function + .endm +RET .macro + JMP R29.w0 + .endm + +CALL2 .macro function + JAL R29.w2, function + .endm +RET2 .macro + JMP R29.w2 + .endm + + +; macro to wait for all three chanels to reach at same point +; USE: R14.b0-> store syn_bit, R14.b2-> channel bit, R14.b1-> R14.b0&R14.b2 +M_WAIT_FOR_ENABLED_CHANNELS .macro +LOOP_WAIT_FOR_ENABLED_CHANNELS?: + LDI R14.b1,0 + LBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + LBCO &R14.b2, PRUx_DMEM, ENDAT_CH0_CHANNEL_CONFIG_OFFSET, 1 + AND R14.b0,R14.b0,R14.b2 + OR R14.b1, R14.b1, R14.b0 + LBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + LBCO &R14.b2, PRUx_DMEM, ENDAT_CH1_CHANNEL_CONFIG_OFFSET, 1 + AND R14.b0,R14.b0,R14.b2 + OR R14.b1, R14.b1,R14.b0 + LBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + LBCO &R14.b2, PRUx_DMEM, ENDAT_CH2_CHANNEL_CONFIG_OFFSET, 1 + AND R14.b0,R14.b0,R14.b2 + OR R14.b1, R14.b1,R14.b0 + + QBNE LOOP_WAIT_FOR_ENABLED_CHANNELS?, R14.b1, 0 + .endm + +; macro for enable PRU cycle counter +; USE: R14 register +M_ENABLE_PRU_CYCLE_COUNTER .macro + .if $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LBCO &R14, c28, 0, 4 + SET R14, R14, 3 + SBCO &R14, c28, 0, 4 + .else + LBCO &R14, c11, 0, 4 + SET R14, R14, 3 + SBCO &R14, c11, 0, 4 + .endif + .endm +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;/ +; Assembler Directives Section +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;/ + .sect ".text" + .retain ; Required for building .out with assembly file + .retainrefs ; Required for building .out with assembly file + .global ENDAT_INIT + + + .include "endat_icss_reg_defs.h" + .include "endat_params.h" + .include "endat_interface.h" + .include "firmware_version.h" +; ENABLE_MULTI_CHANNEL .set 1; Enable this for EnDat send/receive functions to work across channels + + + ; register usage + ; R0, R1, R2 - cmd i/f (R0 also used as status & scratch in b/n where it is safe) + ; R3 - used in single channel, can be used in multi (also used in prop delay, free after it) + ; R4 - scratch + ; R5 - holds selected channel + ; R8, R9 - used by prop delay, but can used after it + ; R6, R7, R8, R9, R10, R11, R12, R15-R18, R19-R22, R23-R26 used for multi ch Rx + ; R13 - scratch + ; R14, R27, R28 still free in multi ch + + .asg R4, SCRATCH + .asg R13, SCRATCH1 + .asg R5.b0, ENDAT_ENABLE_CHx + .asg R5.b1, ENDAT_ENABLE_CHx_IN_USE + .asg R1.b2, ENDAT_CMDTYP_NO_SUPPLEMENT_REG + ;.asg c24, PRUx_DMEM + ;.asg c25, PRU0_DMEM + +ENABLE_PROPDELAY_MESUREMENT .set 1 + +TRIGGER_ENDAT_COMPLETE_EVENT .set 19 +TRIGGER_ENDAT_COMPLETE_IRQ .set (0x20 | (TRIGGER_ENDAT_COMPLETE_EVENT - 16)) + + +ENDAT_INIT: + JMP ENDAT_MAIN + .word ICSS_FIRMWARE_RELEASE_1, ICSS_FIRMWARE_RELEASE_2 +ENDAT_MAIN: + .if $isdefed("PRU0") + .asg PRU0_DMEM, PRUx_DMEM + .asg ICSS_CFG_PRU0_ENDAT_CH0_CFG1, ICSS_CFG_PRUx_ENDAT_CH0_CFG1 + .asg ICSS_CFG_PRU0_ENDAT_CH1_CFG1, ICSS_CFG_PRUx_ENDAT_CH1_CFG1 + .asg ICSS_CFG_PRU0_ENDAT_CH2_CFG1, ICSS_CFG_PRUx_ENDAT_CH2_CFG1 + .asg ICSS_CFG_PRU0_ENDAT_CH0_CFG0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0 + .asg ICSS_CFG_PRU0_ENDAT_CH1_CFG0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0 + .asg ICSS_CFG_PRU0_ENDAT_CH2_CFG0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0 + .asg ICSS_CFG_PRU0_ENDAT_TXCFG, ICSS_CFG_PRUx_ENDAT_TXCFG + .asg ICSS_CFG_PRU0_ENDAT_RXCFG, ICSS_CFG_PRUx_ENDAT_RXCFG + .endif + + .if $isdefed("PRU1") + .asg PRU1_DMEM, PRUx_DMEM + .asg ICSS_CFG_PRU1_ENDAT_CH0_CFG1, ICSS_CFG_PRUx_ENDAT_CH0_CFG1 + .asg ICSS_CFG_PRU1_ENDAT_CH1_CFG1, ICSS_CFG_PRUx_ENDAT_CH1_CFG1 + .asg ICSS_CFG_PRU1_ENDAT_CH2_CFG1, ICSS_CFG_PRUx_ENDAT_CH2_CFG1 + .asg ICSS_CFG_PRU1_ENDAT_CH0_CFG0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0 + .asg ICSS_CFG_PRU1_ENDAT_CH1_CFG0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0 + .asg ICSS_CFG_PRU1_ENDAT_CH2_CFG0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0 + .asg ICSS_CFG_PRU1_ENDAT_TXCFG, ICSS_CFG_PRUx_ENDAT_TXCFG + .asg ICSS_CFG_PRU1_ENDAT_RXCFG, ICSS_CFG_PRUx_ENDAT_RXCFG + .endif + + ; enable PRU cycle counter + M_ENABLE_PRU_CYCLE_COUNTER + + + .if $isdefed("ENDAT_FW_HW_INIT") + ; Initalize ENDAT mode + ; ICSS_CFG.GPCFG0[27:26] = 1 + LDI R0.b0, 4 + SBCO &R0.b0, ICSS_CFG, ICSS_CFG_GPCFG1+3, 1 + + LDI R0.w0, 119 ; RX_CLK: 200*8 KHz + LDI R0.w2, 959 ; TX_CLK: 200 KHz + LDI R1.w0, 10000 ; Enable receiver after 2 clocks => 2us + ; Initialize ENDAT clocks + CALL FN_SET_TX_CLK + + ; Initialize PRU0_ENDAT_CH0_CFG0/1 + ZERO &R0, 4 + + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0 + SBCO &R0, ICSS_CFG, SCRATCH1.w0, 4 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0 + SBCO &R0, ICSS_CFG, SCRATCH1.w0, 4 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0 + SBCO &R0, ICSS_CFG, SCRATCH1.w0, 4 + .endif + + ; clear all registers + ZERO &R0, 120 + + ; record channel enabled by host, save it after zeroing registers (done above) + .if $isdefed("ENABLE_MULTI_CHANNEL") + LDI ENDAT_ENABLE_CHx, 0x7 + LBCO &ENDAT_ENABLE_CHx_IN_USE, PRUx_DMEM, ENDAT_CH0_CHANNEL_CONFIG_OFFSET, 1 + .else + LBCO &ENDAT_ENABLE_CHx, PRUx_DMEM, ENDAT_CH0_CHANNEL_CONFIG_OFFSET, 1 + ; if no channel selected, default to ch0 + ; TODO: till multichannel is supported, if more than 1 channel selected, default to ch0 + AND ENDAT_ENABLE_CHx, ENDAT_ENABLE_CHx, 0x7 + QBEQ ENDAT_DEFAULT_CH, ENDAT_ENABLE_CHx, 0x7 + QBEQ ENDAT_DEFAULT_CH, ENDAT_ENABLE_CHx, 0 + JMP ENDAT_SKIP_DEFAULT_CH +ENDAT_DEFAULT_CH: + LDI ENDAT_ENABLE_CHx, 0x1 +ENDAT_SKIP_DEFAULT_CH: + .endif + + + + CALL FN_ENDAT_POWER_ON_INIT + + + ; Configure the TX clock mode for channel 0 to FREERUN mode (already done - confirm) + ; Program command to TX_DATA for channel 0 (R30[7:0]) and Set go bit + ; Will be send MSB first - X M2 M1 M0 (M2) (M1) (M0) x + + ; NOTE: Use tx_frame_size for if there is a need to transmit N-bits towars the end + ; NOTE: rx_en_counter/manual rx_en is required after transmit to enable receiver + ; NOTE: At Low clock encoder can be parked upto 50ms (LC exception: 30us) + ; NOTE: At High clock encoder will reset it self after 10us (elapse of recovery time) + + LDI R0.w0, ENDAT_CMD_RECEIVE_RESET + LDI R0.w2, 0 + LDI R1.b0, ENDAT_RX_29BITS ; 1 (sb) + 29 (8+16+5) bits before setting clock to high + LDI R1.b1, ENDAT_TX_30BITS ; 6(Mode bits)+16(dummy)+8(dummy) + LDI R1.b2, ENDAT_CMDTYP_2_1 + CALL FN_SEND_RECEIVE_ENDAT + + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_50MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ; Wait 50ms + + ; Read out and buffer alarms and warnings + ; Clear the alarms + LDI R0.w0, (ENDAT_CMD_SEL_MEM_AREA | ((MRS_CODE_OPERATING_STATUS&0x80) >> 7) | (((MRS_CODE_OPERATING_STATUS << 1)&0xFF)<<8)) + LDI R0.w2, 0 + LDI R1.b0, ENDAT_RX_29BITS ; 1 (sb) + 29 (8+16+5) bits before setting clock to high + LDI R1.b1, ENDAT_TX_30BITS ; 6(Mode bits)+16(dummy)+8(dummy) + LDI R1.b2, ENDAT_CMDTYP_2_1 + CALL FN_SEND_RECEIVE_ENDAT + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_12MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ; Wait 12ms + + ; Clear error messages + ; Select MRS:10111001(C7..C0) and read Word0 (address:0x00) + LDI R0.w0, (ENDAT_CMD_RECEIVE_PARAMETERS | ((WORD_0&0x80) >> 7) | (((WORD_0 << 1)&0xFF)<<8)) + LDI R0.w2, 0 + LDI R1.b0, ENDAT_RX_29BITS ; 1 (sb) + 29 (8+16+5) bits before setting clock to high + LDI R1.b1, ENDAT_TX_30BITS ; 6(Mode bits)+16(dummy)+8(dummy) + LDI R1.b2, ENDAT_CMDTYP_2_1 + CALL FN_SEND_RECEIVE_ENDAT + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_12MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ; Wait 12ms + + ; Clear the warnings + ; Select MRS:10111001(C7..C0) and read Word1 (address:0x01) + LDI R0.w0, (ENDAT_CMD_RECEIVE_PARAMETERS | ((WORD_1&0x80) >> 7) | (((WORD_1 << 1)&0xFF)<<8)) + LDI R0.w2, 0 + LDI R1.b0, ENDAT_RX_29BITS ; 1 (sb) + 29 (8+16+5) bits before setting clock to high + LDI R1.b1, ENDAT_TX_30BITS ; 6(Mode bits)+16(dummy)+8(dummy) + LDI R1.b2, ENDAT_CMDTYP_2_1 + CALL FN_SEND_RECEIVE_ENDAT + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_12MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ; Wait 12ms + + ; Read out number of clock pulses for transfer of the position value + ; Parameters of encoder manufacturer Word 13 + ; Select MRS:10100001(C7..C0) and read Word13 (address:0x0D) + LDI R0.w0, (ENDAT_CMD_SEL_MEM_AREA | ((MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE0&0x80) >> 7) | (((MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE0 << 1)&0xFF)<<8)) + LDI R0.w2, 0 + LDI R1.b0, ENDAT_RX_29BITS ; 1 (sb) + 29 (8+16+5) bits before setting clock to high + LDI R1.b1, ENDAT_TX_30BITS ; 6(Mode bits)+16(dummy)+8(dummy) + LDI R1.b2, ENDAT_CMDTYP_2_1 + CALL FN_SEND_RECEIVE_ENDAT + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_12MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ; Wait 12ms + + ; Read out number of clock pulses for transfer of the position value + ; Parameters of encoder manufacturer Word 13 + ; Select MRS:10100001(C7..C0) to get Word13 (address:0x0D) + LDI R0.w0, (ENDAT_CMD_SEND_PARAMETERS | ((WORD_13&0x80) >> 7) | (((WORD_13 << 1)&0xFF)<<8)) + LDI R0.w2, 0 + LDI R1.b0, ENDAT_RX_29BITS ; 1 (sb) + 29 (8+16+5) bits before setting clock to high + LDI R1.b1, ENDAT_TX_30BITS ; 6(Mode bits)+16(dummy)+8(dummy) + LDI R1.b2, ENDAT_CMDTYP_2_1 + CALL FN_SEND_RECEIVE_ENDAT +; Need to save the response and extract the clock pulses info + + .if $isdefed("ENABLE_MULTI_CHANNEL") + LSL R15, R15, 3 + LSL R19, R19, 3 + LSL R23, R23, 3 + + QBBC ENDAT_SKIP2_CH0, ENDAT_ENABLE_CHx, 0 + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP2_CH0: + QBBC ENDAT_SKIP2_CH1, ENDAT_ENABLE_CHx, 1 + SBCO &R19.b1, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP2_CH1: + QBBC ENDAT_SKIP2_CH2, ENDAT_ENABLE_CHx, 2 + SBCO &R23.b1, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP2_CH2: + + .else ; ENABLE_MULTI_CHANNEL + + LSL R15, R15, 3 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;save response for ch0 in PRU + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;save response for ch1 in RTU + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;save response for CH2 in TXPRU + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 + .else + QBBC ENDAT_SKIP2_CH0, ENDAT_ENABLE_CHx, 0 + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP2_CH0: + QBBC ENDAT_SKIP2_CH1, ENDAT_ENABLE_CHx, 1 + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP2_CH1: + QBBC ENDAT_SKIP2_CH2, ENDAT_ENABLE_CHx, 2 + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP2_CH2: + + .endif + .endif ; ENABLE_MULTI_CHANNEL + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_2MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ; Wait 2ms + + ; Check whether encoder supports EnDat2.2 + ; Parameters of encoder manufacturer Word 37 + ; Select MRS:10100101(C7..C0) and read Word37 (address:0x05) + + LDI R0.w0, (ENDAT_CMD_SEL_MEM_AREA | ((MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE2&0x80) >> 7) | (((MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE2 << 1)&0xFF)<<8)) + LDI R0.w2, 0 + LDI R1.b0, ENDAT_RX_29BITS ; 1 (sb) + 29 (8+16+5) bits before setting clock to high + LDI R1.b1, ENDAT_TX_30BITS ; 6(Mode bits)+16(dummy)+8(dummy) + LDI R1.b2, ENDAT_CMDTYP_2_1 + CALL FN_SEND_RECEIVE_ENDAT + + + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_12MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ; Wait 12ms + + + ; Read out EnDat command set + ; Parameters of encoder manufacturer Word 37 + ; Select MRS:10100101(C7..C0) to get Word 37 (address:0x05) + LDI R0.w0, (ENDAT_CMD_SEND_PARAMETERS | ((WORD_5&0x80) >> 7) | (((WORD_5 << 1)&0xFF)<<8)) + LDI R0.w2, 0 + LDI R1.b0, ENDAT_RX_29BITS ; 1 (sb) + 29 (8+16+5) bits before setting clock to high + LDI R1.b1, ENDAT_TX_30BITS ; 6(Mode bits)+16(dummy)+8(dummy) + LDI R1.b2, ENDAT_CMDTYP_2_1 + CALL FN_SEND_RECEIVE_ENDAT +; Need to save the response and extract the clock pulses info + + .if $isdefed("ENABLE_MULTI_CHANNEL") + LSL R15, R15, 3 + LSL R19, R19, 3 + LSL R23, R23, 3 + + + QBBC ENDAT_SKIP4_CH0, ENDAT_ENABLE_CHx, 0 + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH0_ENDAT22_STAT_OFFSET, 1 +ENDAT_SKIP4_CH0: + QBBC ENDAT_SKIP4_CH1, ENDAT_ENABLE_CHx, 1 + SBCO &R19.b1, PRUx_DMEM, ENDAT_CH1_ENDAT22_STAT_OFFSET, 1 +ENDAT_SKIP4_CH1: + QBBC ENDAT_SKIP4_CH2, ENDAT_ENABLE_CHx, 2 + SBCO &R23.b1, PRUx_DMEM, ENDAT_CH2_ENDAT22_STAT_OFFSET, 1 +ENDAT_SKIP4_CH2: + + .else ; ENABLE_MULTI_CHANNEL + LSL R15, R15, 3 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;save response for ch0 in PRU + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH0_ENDAT22_STAT_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;save response for ch1 in RTU + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH1_ENDAT22_STAT_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;save response for CH2 in TXPRU + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH2_ENDAT22_STAT_OFFSET, 1 + .else + QBBC ENDAT_SKIP4_CH0, ENDAT_ENABLE_CHx, 0 + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH0_ENDAT22_STAT_OFFSET, 1 +ENDAT_SKIP4_CH0: + QBBC ENDAT_SKIP4_CH1, ENDAT_ENABLE_CHx, 1 + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH1_ENDAT22_STAT_OFFSET, 1 +ENDAT_SKIP4_CH1: + QBBC ENDAT_SKIP4_CH2, ENDAT_ENABLE_CHx, 2 + SBCO &R15.b1, PRUx_DMEM, ENDAT_CH2_ENDAT22_STAT_OFFSET, 1 +ENDAT_SKIP4_CH2: + .endif + .endif ; ENABLE_MULTI_CHANNEL + + ;set syn_bits of all channels for clock configuration + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0x1 ; set syn_bit bit for ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0x2 ;set syn_bit bit for ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0x4 ; set syn_bit bit for ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + .endif + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_12MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ; Wait 12ms + + ; Perform propagation delay compensation + ; Create a function to support per channel delay computation + .if $isdefed("ENABLE_PROPDELAY_MESUREMENT") + + ; tx 200KHz, rx 8*12MHz + LDI R0.w0, 1 ; RX_CLK: 8*12MHz + LDI R0.w2, 959 ; TX_CLK: 200 KHz + LDI R1.w0, 10000 ; Enable receiver after 2 clocks + + + ;wait to reach at same point for all cores before clk configuration + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0 ;clear syn_bit bit for ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_CLOCK_CONFIG1, R14.b2, 0 ; check if RTU is primary core + CALL FN_SET_TX_CLK + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0 ; clear syn_bit bit for ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_CLOCK_CONFIG1, R14.b2, 1 ; check if PRU is primary core + CALL FN_SET_TX_CLK + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0 ;clear syn_bit bit for ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_CLOCK_CONFIG1, R14.b2, 2; check if TXPRU is primary core + CALL FN_SET_TX_CLK + .else + CALL FN_SET_TX_CLK ;When load share mode is not used, that is single channel or multi channel using single PRU + .endif + +SKIP_CLOCK_CONFIG1: + +;set syn_bits of all channels for delay calculation + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0x1 ;set syn_bit bit for ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0x2 ; set syn_bit bit for ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0x4 ; set syn_bit bit for ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + .endif + + .if $isdefed("ENABLE_MULTI_CHANNEL") + + ; start loop with ch0 per channel variables + LDI R3.w0, 0 | 8 << 8 + LDI R3.w2, 24 | 5 << 8 + LDI R8.b0, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET + + LOOP PROP_DELAY_MULTI_END, 3 + + ; # read position bits (offset ch[0,1,2]: [0x44, 0x64, 0x84]) + LBCO &R2.b1, PRUx_DMEM, R8.b0, 1 + + ; bypass prop delay estimation if encoder not detected for the ch, else would wait indefinitely in prop delay fn + QBEQ ENDAT_SKIP_PROP_DELAY_CALC, R2.b1, 0 + QBEQ ENDAT_SKIP_PROP_DELAY_CALC, R2.b1, 0xFF + + CALL FN_PROP_DELAY_CALC + +ENDAT_SKIP_PROP_DELAY_CALC: + ; write prop delay (offset ch[0,1,2]: [0x28, 0x48, 0x68]) + ADD R8.b0, R8.b0, 0x4 + SBCO &R9, PRUx_DMEM, R8.b0, 4 + + ; update per ch variables for next channel + ; 0x4 + 0x1C = 0x20, corresponds to i/f buffer of one channel + ADD R8.b0, R8.b0, 0x1C + ADD R3.b0, R3.b0, 1 ; ENDAT_TX_CHx_SEL + ADD R3.b1, R3.b1, 1 ; ENDAT_CHx_CLK + ADD R3.b2, R3.b2, 1 ; ENDAT_CHx_SB + ADD R3.b3, R3.b3, 8 ; ENDAT_CHx_TX_REINIT + +PROP_DELAY_MULTI_END: + + .else + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;ch0: R3.b0 - ENDAT_TX_CHx_SEL, R2.b1 - clock plus for position, R3.b2 - ENDAT_CHx_SB, R3.b3 - ENDAT_CHx_TX_REINIT + LDI R3.w0, 0 | 8 << 8 + LDI R3.w2, 24 | 5 << 8 + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 + CALL FN_PROP_DELAY_CALC + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;ch1 : R3.b0 - ENDAT_TX_CHx_SEL, R2.b1 - clock plus for position, R3.b2 - ENDAT_CHx_SB, R3.b3 - ENDAT_CHx_TX_REINIT + LDI R3.w0, 1 | 9 << 8 + LDI R3.w2, 25 | 13 << 8 + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 + CALL FN_PROP_DELAY_CALC + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;ch2: R3.b0 - ENDAT_TX_CHx_SEL, R2.b1 - clock plus for position, R3.b2 - ENDAT_CHx_SB, R3.b3 - ENDAT_CHx_TX_REINIT + LDI R3.w0, 2 | 10 << 8 + LDI R3.w2, 26 | 21 << 8 + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 + CALL FN_PROP_DELAY_CALC + .else + QBBC ENDAT_SKIP5A_CH0, ENDAT_ENABLE_CHx, 0 + LDI R3.w0, 0 | 8 << 8 + LDI R3.w2, 24 | 5 << 8 + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP5A_CH0: + QBBC ENDAT_SKIP5A_CH1, ENDAT_ENABLE_CHx, 1 + LDI R3.w0, 1 | 9 << 8 + LDI R3.w2, 25 | 13 << 8 + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP5A_CH1: + QBBC ENDAT_SKIP5A_CH2, ENDAT_ENABLE_CHx, 2 + LDI R3.w0, 2 | 10 << 8 + LDI R3.w2, 26 | 21 << 8 + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP5A_CH2: + CALL FN_PROP_DELAY_CALC + .endif + + + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;store prop_delay value in DMEM for ch0 + SBCO &R9, PRUx_DMEM, ENDAT_CH0_MEAS_PROPDELAY_OFFSET, 4 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;store prop_delay value in DMEM for ch1 + SBCO &R9, PRUx_DMEM, ENDAT_CH1_MEAS_PROPDELAY_OFFSET, 4 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;store prop_delay value in DMEM for ch2 + SBCO &R9, PRUx_DMEM, ENDAT_CH2_MEAS_PROPDELAY_OFFSET, 4 + .else + QBBC ENDAT_SKIP7_CH0, ENDAT_ENABLE_CHx, 0 + SBCO &R9, PRUx_DMEM, ENDAT_CH0_MEAS_PROPDELAY_OFFSET, 4 +ENDAT_SKIP7_CH0: + QBBC ENDAT_SKIP7_CH1, ENDAT_ENABLE_CHx, 1 + SBCO &R9, PRUx_DMEM, ENDAT_CH1_MEAS_PROPDELAY_OFFSET, 4 +ENDAT_SKIP7_CH1: + QBBC ENDAT_SKIP7_CH2, ENDAT_ENABLE_CHx, 2 + SBCO &R9, PRUx_DMEM, ENDAT_CH2_MEAS_PROPDELAY_OFFSET, 4 +ENDAT_SKIP7_CH2: + .endif + .endif ; ENABLE_MULTI_CHANNEL + .endif ; ENABLE_PROPDELAY_MESUREMENT + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_CLOCK_RX_OFFSET, 6 + QBNE ENDAT_SKIP_DEFAULT_CLOCK, R0, 0 + LDI R0.w0, 2 ; RX_CLK: 8*8MHz + LDI R0.w2, 23 ; TX_CLK: 8 MHz + LDI R1.w0, 250 ; Enable receiver after 2 clocks => 2us +ENDAT_SKIP_DEFAULT_CLOCK: + +;wait to reach at same point for all cores before clk configuration + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0 ;clear syn_bit bit for ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_CLOCK_CONFIG2, R14.b2, 0; check RTU is primary core + CALL FN_SET_TX_CLK + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0 ;clear syn_bit bit for ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_CLOCK_CONFIG2, R14.b2, 1; check PRU is primary core + CALL FN_SET_TX_CLK + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0 ;clear syn_bit bit for ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_CLOCK_CONFIG2, R14.b2, 2; check TXPRU is primary core + CALL FN_SET_TX_CLK + .else + CALL FN_SET_TX_CLK ;When load share mode is not used, that is single channel or multi channel using single PRU + .endif + +SKIP_CLOCK_CONFIG2: + + ; status indication that host is ready (bit0 in ) - currently based on non-zero clock pulse value + ; TODO: The way status is indicated to host should be made a robust rather than the one used here + .if $isdefed("ENABLE_MULTI_CHANNEL") + LDI R0.b0, 0 + LBCO &R0.b1, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 + QBEQ ENDAT_SKIP8A_CH0, R0.b1, 0 + QBEQ ENDAT_SKIP8A_CH0, R0.b1, 0xFF + OR R0.b0, R0.b0, 0x1 +ENDAT_SKIP8A_CH0: + + LBCO &R0.b1, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 + QBEQ ENDAT_SKIP8A_CH1, R0.b1, 0 + QBEQ ENDAT_SKIP8A_CH1, R0.b1, 0xFF + OR R0.b0, R0.b0, 0x2 +ENDAT_SKIP8A_CH1: + + LBCO &R0.b1, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 + QBEQ ENDAT_SKIP8A_CH2, R0.b1, 0 + QBEQ ENDAT_SKIP8A_CH2, R0.b1, 0xFF + OR R0.b0, R0.b0, 0x4 +ENDAT_SKIP8A_CH2: + + ; check whether user specified channels has been detected + LBCO &R0.b2, PRUx_DMEM, ENDAT_CH0_CHANNEL_CONFIG_OFFSET, 1 + ; store detected channels, this has to be done after reading user specified as done above + SBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_CHANNEL_CONFIG_OFFSET, 1 + AND R0.b0, R0.b0, R0.b2 + QBEQ ENDAT_SKIP8A_END, R0.b2, R0.b0 + LDI R0.b0, 0 +ENDAT_SKIP8A_END: + MOV ENDAT_ENABLE_CHx_IN_USE, R0.b0 + + .else + LDI R0.b1, 0 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;store clock plus value in register from DMEM for ch0 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;store clock plus value in register from DMEM for ch1 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;store clock plus value in register from DMEM for ch2 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 + .else + QBBC ENDAT_SKIP8_CH0, ENDAT_ENABLE_CHx, 0 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP8_CH0: + QBBC ENDAT_SKIP8_CH1, ENDAT_ENABLE_CHx, 1 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP8_CH1: + QBBC ENDAT_SKIP8_CH2, ENDAT_ENABLE_CHx, 2 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP8_CH2: + .endif + .endif ;ENABLE_MULTI_CHANNEL + + QBEQ ENDAT_SKIP_INIT_SUCCESS, R0.b0, 0 ; if eq 0, r0.b0 can be reused as status + LDI R0.b0, 1 + +ENDAT_SKIP_INIT_SUCCESS: + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;update success status for ch0 + SBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_INTFC_CMD_STATUS_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;update success status for ch1 + SBCO &R0.b0, PRUx_DMEM, ENDAT_CH1_INTFC_CMD_STATUS_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;update success status for ch2 + SBCO &R0.b0, PRUx_DMEM, ENDAT_CH2_INTFC_CMD_STATUS_OFFSET, 1 + .else + SBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_INTFC_CMD_STATUS_OFFSET, 1 ; update success status when load share mode is not used + .endif + ; status update ends here + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ; Check RTU host trigger for ch0 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_OPMODE_CONFIG_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;Check PRU host trigger for ch1 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH1_OPMODE_CONFIG_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;Check TXPRU host trigger for ch2 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH2_OPMODE_CONFIG_OFFSET, 1 + .else ;check PRU host trigger for all three channels + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_OPMODE_CONFIG_OFFSET, 1 + .endif + QBNE HANDLE_HOST_TRIGGER_MODE, R0.b0, 0 + +HANDLE_PERIODIC_TRIGGER_MODE: + ; Get pending events from IEP + LBCO &R0, ICSS_IEP, ICSS_IEP_CMP_STATUS_REG, 4 + ; wait till IEP CMP2 event + QBBC HANDLE_PERIODIC_TRIGGER_MODE, R0, 2 + ; Clear IEP CMP2 event + SET R0, R0, 2 + SBCO &R0, ICSS_IEP, ICSS_IEP_CMP_STATUS_REG, 4 + + ; Let the fall thr' to trigger mode happen properly and trigger bit + ; will be cleared after command processing + LDI R0.b0, 1 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;set command trigger for ch0 + SBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_INTFC_CMD_TRIGGER_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;set command trigger for ch1 + SBCO &R0.b0, PRUx_DMEM, ENDAT_CH1_INTFC_CMD_TRIGGER_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;set command trigger for ch2 + SBCO &R0.b0, PRUx_DMEM, ENDAT_CH2_INTFC_CMD_TRIGGER_OFFSET, 1 + .else ;SET command TRIGGER FOR ALL CHANNELS IN WITHOUT LOAD SHARE MODE + SBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_INTFC_CMD_TRIGGER_OFFSET, 1 + .endif + +HANDLE_HOST_TRIGGER_MODE: + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;wait until command trigger is not set for ch0 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_INTFC_CMD_TRIGGER_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;wait command host trigger is not set for ch1 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH1_INTFC_CMD_TRIGGER_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;wait until command trigger is not set for ch2 + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH2_INTFC_CMD_TRIGGER_OFFSET, 1 + .else + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_INTFC_CMD_TRIGGER_OFFSET, 1 ; without load share mode(one command trigger for all three channels) + .endif + + QBBC HANDLE_HOST_TRIGGER_MODE, R0.b0, 0 + + QBBC ENDAT_SKIP_CONTINUOUS_MODE, R0.b0, 7 + .if !$isdefed("ENABLE_MULTI_CHANNEL") & !$isdefed("ENABLE_MULTI_MAKE_RTU") & !$isdefed("ENABLE_MULTI_MAKE_PRU") & !$isdefed("ENABLE_MULTI_MAKE_TXPRU") + CALL FN_CONTINUOUS_MODE + .endif + + JMP ENDAT_HOST_CMD_END + +ENDAT_SKIP_CONTINUOUS_MODE: + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;command parameters for ch0 + LBCO &R0, PRUx_DMEM, ENDAT_CH0_CMD_WORD_0_OFFSET, 8 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;command parameters for ch1 + LBCO &R0, PRUx_DMEM, ENDAT_CH1_CMD_WORD_0_OFFSET, 8 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;command parameters for ch2 + LBCO &R0, PRUx_DMEM, ENDAT_CH2_CMD_WORD_0_OFFSET, 8 + .else ;command parameters for all enabled channels, when single pru used or load share mode is nor used + LBCO &R0, PRUx_DMEM, ENDAT_CH0_CMD_WORD_0_OFFSET, 8 + .endif + + CALL FN_SEND_RECEIVE_ENDAT + QBBS ENDAT_HOST_CMD_DONE, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 0 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ; command supplement parameters for ch0 + LBCO &R1, PRUx_DMEM, ENDAT_CH0_CMD_WORD_2_OFFSET, 4 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;command supplement parameters for ch1 + LBCO &R1, PRUx_DMEM, ENDAT_CH1_CMD_WORD_2_OFFSET, 4 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU");command supplement parameters for ch2 + LBCO &R1, PRUx_DMEM, ENDAT_CH2_CMD_WORD_2_OFFSET, 4 + .else ; command supplement parameters for all channels (without load share mode) + LBCO &R1, PRUx_DMEM, ENDAT_CH0_CMD_WORD_2_OFFSET, 4 + .endif + + CALL FN_SEND_ENDAT22_COMMAND_SUPPLEMENT +ENDAT_HOST_CMD_DONE: + ; result in R15-R18, R0.b0 holds CRC status, R2.b0 indicates addinfo presence + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;ch0: store encoder response and crc in DMEM + ; R0.b0 has CRC status + MOV SCRATCH.b0, R0.b0 + LBCO &SCRATCH.b1, PRUx_DMEM, ENDAT_CH0_CRC_ERR_COUNTER_OFFSET + 1, 3 + QBBS ENDAT_SKIP14A_RTU_CH0, SCRATCH.b0, 0 ; pos/data CRC check + ADD SCRATCH.b1, SCRATCH.b1, 1 + ZERO &R15, 8 +ENDAT_SKIP14A_RTU_CH0: + QBEQ ENDAT_SKIP14D_RTU_CH0, R2.b0, 0 ; R2.b0 indicates whether addinfo1/2 present + QBBS ENDAT_SKIP14B_RTU_CH0, SCRATCH.b0, 1 ; addinfo1/2 CRC check + ADD SCRATCH.b2, SCRATCH.b2, 1 +ENDAT_SKIP14D_RTU_CH0: + ZERO &R17, 4 +ENDAT_SKIP14B_RTU_CH0: + QBNE ENDAT_SKIP14E_RTU_CH0, R2.b0, (0x3 << 3) ; R2.b0 indicates whether both addinfo are present + QBBS ENDAT_SKIP14C_RTU_CH0, SCRATCH.b0, 2 ; addinfo1 CRC check + ADD SCRATCH.b3, SCRATCH.b3, 1 +ENDAT_SKIP14E_RTU_CH0: + ZERO &R18, 4 +ENDAT_SKIP14C_RTU_CH0: + + SBCO &R15, PRUx_DMEM, ENDAT_CH0_POSITION_DATA_WORD0_OFFSET, 16 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH0_CRC_ERR_COUNTER_OFFSET, 4 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;ch1 store encoder response and crc in DMEM + MOV SCRATCH.b0, R0.b0 + LBCO &SCRATCH.b1, PRUx_DMEM, ENDAT_CH1_CRC_ERR_COUNTER_OFFSET + 1, 3 + QBBS ENDAT_SKIP14A_PRU_CH1, SCRATCH.b0, 0 ; pos/data CRC check + ADD SCRATCH.b1, SCRATCH.b1, 1 + ZERO &R15, 8 +ENDAT_SKIP14A_PRU_CH1: + QBEQ ENDAT_SKIP14D_PRU_CH1, R2.b0, 0 ; R2.b0 indicates whether addinfo1/2 present + QBBS ENDAT_SKIP14B_PRU_CH1, SCRATCH.b0, 1 ; addinfo1/2 CRC check + ADD SCRATCH.b2, SCRATCH.b2, 1 +ENDAT_SKIP14D_PRU_CH1: + ZERO &R17, 4 +ENDAT_SKIP14B_PRU_CH1: + QBNE ENDAT_SKIP14E_PRU_CH1, R2.b0, (0x3 << 3) ; R2.b0 indicates whether both addinfo are present + QBBS ENDAT_SKIP14C_PRU_CH1, SCRATCH.b0, 2 ; addinfo1 CRC check + ADD SCRATCH.b3, SCRATCH.b3, 1 +ENDAT_SKIP14E_PRU_CH1: + ZERO &R18, 4 +ENDAT_SKIP14C_PRU_CH1: + + SBCO &R15, PRUx_DMEM, ENDAT_CH1_POSITION_DATA_WORD0_OFFSET, 16 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH1_CRC_ERR_COUNTER_OFFSET, 4 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU");ch2 store encoder response and crc in DMEM + MOV SCRATCH.b0, R0.b0 + LBCO &SCRATCH.b1, PRUx_DMEM, ENDAT_CH2_CRC_ERR_COUNTER_OFFSET + 1, 3 + QBBS ENDAT_SKIP14A_TXPRU_CH2, SCRATCH.b0, 0 ; pos/data CRC check + ADD SCRATCH.b1, SCRATCH.b1, 1 + ZERO &R15, 8 +ENDAT_SKIP14A_TXPRU_CH2: + QBEQ ENDAT_SKIP14D_TXPRU_CH2, R2.b0, 0 ; R2.b0 indicates whether addinfo1/2 present + QBBS ENDAT_SKIP14B_TXPRU_CH2, SCRATCH.b0, 1 ; addinfo1/2 CRC check + ADD SCRATCH.b2, SCRATCH.b2, 1 +ENDAT_SKIP14D_TXPRU_CH2: + ZERO &R17, 4 +ENDAT_SKIP14B_TXPRU_CH2: + QBNE ENDAT_SKIP14E_TXPRU_CH2, R2.b0, (0x3 << 3) ; R2.b0 indicates whether both addinfo are present + QBBS ENDAT_SKIP14C_TXPRU_CH2, SCRATCH.b0, 2 ; addinfo1 CRC check + ADD SCRATCH.b3, SCRATCH.b3, 1 +ENDAT_SKIP14E_TXPRU_CH2: + ZERO &R18, 4 +ENDAT_SKIP14C_TXPRU_CH2: + + SBCO &R15, PRUx_DMEM, ENDAT_CH2_POSITION_DATA_WORD0_OFFSET, 16 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH2_CRC_ERR_COUNTER_OFFSET, 4 + + + .else ;store store encoder response and crc when load share mode is not enabled + QBBC ENDAT_SKIP14_CH0, ENDAT_ENABLE_CHx, 0 + ; R0.b0 has CRC status + MOV SCRATCH.b0, R0.b0 + LBCO &SCRATCH.b1, PRUx_DMEM, ENDAT_CH0_CRC_ERR_COUNTER_OFFSET + 1, 3 + QBBS ENDAT_SKIP14A_CH0, SCRATCH.b0, 0 ; pos/data CRC check + ADD SCRATCH.b1, SCRATCH.b1, 1 + ZERO &R15, 8 +ENDAT_SKIP14A_CH0: + QBEQ ENDAT_SKIP14D_CH0, R2.b0, 0 ; R2.b0 indicates whether addinfo1/2 present + QBBS ENDAT_SKIP14B_CH0, SCRATCH.b0, 1 ; addinfo1/2 CRC check + ADD SCRATCH.b2, SCRATCH.b2, 1 +ENDAT_SKIP14D_CH0: + ZERO &R17, 4 +ENDAT_SKIP14B_CH0: + QBNE ENDAT_SKIP14E_CH0, R2.b0, (0x3 << 3) ; R2.b0 indicates whether both addinfo are present + QBBS ENDAT_SKIP14C_CH0, SCRATCH.b0, 2 ; addinfo1 CRC check + ADD SCRATCH.b3, SCRATCH.b3, 1 +ENDAT_SKIP14E_CH0: + ZERO &R18, 4 +ENDAT_SKIP14C_CH0: + + SBCO &R15, PRUx_DMEM, ENDAT_CH0_POSITION_DATA_WORD0_OFFSET, 16 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH0_CRC_ERR_COUNTER_OFFSET, 4 +ENDAT_SKIP14_CH0: + + QBBC ENDAT_SKIP14_CH1, ENDAT_ENABLE_CHx, 1 + ; R0.b0 has CRC status + .if $isdefed("ENABLE_MULTI_CHANNEL") + MOV SCRATCH.b0, R0.b1 + .else + MOV SCRATCH.b0, R0.b0 + .endif + LBCO &SCRATCH.b1, PRUx_DMEM, ENDAT_CH1_CRC_ERR_COUNTER_OFFSET + 1, 3 + QBBS ENDAT_SKIP14A_CH1, SCRATCH.b0, 0 ; pos/data CRC check + ADD SCRATCH.b1, SCRATCH.b1, 1 + .if $isdefed("ENABLE_MULTI_CHANNEL") + ZERO &R19, 8 + .else + ZERO &R15, 8 + .endif +ENDAT_SKIP14A_CH1: + QBEQ ENDAT_SKIP14D_CH1, R2.b0, 0 ; R2.b0 indicates whether addinfo1/2 present + QBBS ENDAT_SKIP14B_CH1, SCRATCH.b0, 1 ; addinfo1/2 CRC check + ADD SCRATCH.b2, SCRATCH.b2, 1 +ENDAT_SKIP14D_CH1: + .if $isdefed("ENABLE_MULTI_CHANNEL") + ZERO &R21, 4 + .else + ZERO &R17, 4 + .endif +ENDAT_SKIP14B_CH1: + QBNE ENDAT_SKIP14E_CH1, R2.b0, (0x3 << 3) ; R2.b0 indicates whether both addinfo are present + QBBS ENDAT_SKIP14C_CH1, SCRATCH.b0, 2 ; addinfo1 CRC check + ADD SCRATCH.b3, SCRATCH.b3, 1 +ENDAT_SKIP14E_CH1: + .if $isdefed("ENABLE_MULTI_CHANNEL") + ZERO &R22, 4 + .else + ZERO &R18, 4 + .endif +ENDAT_SKIP14C_CH1: + .if $isdefed("ENABLE_MULTI_CHANNEL") + SBCO &R19, PRUx_DMEM, ENDAT_CH1_POSITION_DATA_WORD0_OFFSET, 16 + .else + SBCO &R15, PRUx_DMEM, ENDAT_CH1_POSITION_DATA_WORD0_OFFSET, 16 + .endif + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH1_CRC_ERR_COUNTER_OFFSET, 4 +ENDAT_SKIP14_CH1: + + QBBC ENDAT_SKIP14_CH2, ENDAT_ENABLE_CHx, 2 + ; R0.b0 has CRC status + .if $isdefed("ENABLE_MULTI_CHANNEL") + MOV SCRATCH.b0, R0.b2 + .else + MOV SCRATCH.b0, R0.b0 + .endif + LBCO &SCRATCH.b1, PRUx_DMEM, ENDAT_CH2_CRC_ERR_COUNTER_OFFSET + 1, 3 + QBBS ENDAT_SKIP14A_CH2, SCRATCH.b0, 0 ; pos/data CRC check + ADD SCRATCH.b1, SCRATCH.b1, 1 + .if $isdefed("ENABLE_MULTI_CHANNEL") + ZERO &R23, 8 + .else + ZERO &R15, 8 + .endif +ENDAT_SKIP14A_CH2: + QBEQ ENDAT_SKIP14D_CH2, R2.b0, 0 ; R2.b0 indicates whether addinfo1/2 present + QBBS ENDAT_SKIP14B_CH2, SCRATCH.b0, 1 ; addinfo1/2 CRC check + ADD SCRATCH.b2, SCRATCH.b2, 1 +ENDAT_SKIP14D_CH2: + .if $isdefed("ENABLE_MULTI_CHANNEL") + ZERO &R25, 4 + .else + ZERO &R17, 4 + .endif +ENDAT_SKIP14B_CH2: + QBNE ENDAT_SKIP14E_CH2, R2.b0, (0x3 << 3) ; R2.b0 indicates whether both addinfo are present + QBBS ENDAT_SKIP14C_CH2, SCRATCH.b0, 2 ; addinfo1 CRC check + ADD SCRATCH.b3, SCRATCH.b3, 1 +ENDAT_SKIP14E_CH2: + .if $isdefed("ENABLE_MULTI_CHANNEL") + ZERO &R26, 4 + .else + ZERO &R18, 4 + .endif +ENDAT_SKIP14C_CH2: + .if $isdefed("ENABLE_MULTI_CHANNEL") + SBCO &R23, PRUx_DMEM, ENDAT_CH2_POSITION_DATA_WORD0_OFFSET, 16 + .else + SBCO &R15, PRUx_DMEM, ENDAT_CH2_POSITION_DATA_WORD0_OFFSET, 16 + .endif + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH2_CRC_ERR_COUNTER_OFFSET, 4 +ENDAT_SKIP14_CH2: + .endif + +ENDAT_HOST_CMD_END: + + LDI R3.w0, 0 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;clear command trigger for ch0 + SBCO &R3.b0, PRUx_DMEM, ENDAT_CH0_INTFC_CMD_TRIGGER_OFFSET, 1 + LBCO &SCRATCH.b0, PRUx_DMEM, ENDAT_CH0_OPMODE_CONFIG_OFFSET, 1 ; Check RTU host trigger for ch0 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;clear command trigger for ch1 + SBCO &R3.b0, PRUx_DMEM, ENDAT_CH1_INTFC_CMD_TRIGGER_OFFSET, 1 + LBCO &SCRATCH.b0, PRUx_DMEM, ENDAT_CH1_OPMODE_CONFIG_OFFSET, 1 ;Check PRU host trigger for ch1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;clear command trigger for ch2 + SBCO &R3.b0, PRUx_DMEM, ENDAT_CH2_INTFC_CMD_TRIGGER_OFFSET, 1 + LBCO &SCRATCH.b0, PRUx_DMEM, ENDAT_CH2_OPMODE_CONFIG_OFFSET, 1 ;Check TXPRU host trigger for ch2 + .else ; when load share mode is not used + SBCO &R3.b0, PRUx_DMEM, ENDAT_CH0_INTFC_CMD_TRIGGER_OFFSET, 1 + LBCO &SCRATCH.b0, PRUx_DMEM, ENDAT_CH0_OPMODE_CONFIG_OFFSET, 1 ;check PRU host trigger for all three channels + .endif + + QBEQ HANDLE_PERIODIC_TRIGGER_MODE, SCRATCH.b0, 0 + JMP HANDLE_HOST_TRIGGER_MODE + + + .if $isdefed("ENABLE_MULTI_CHANNEL") +M_CALC_RECOV_TIME_MULTI_CH .macro + ;enable PRU cycle counter + M_ENABLE_PRU_CYCLE_COUNTER + ZERO &R14, 4 + ; waiting for raising edge of clock for all connected channels +ENDAT_TD_LAST_RISING_CLOCK_MULTI_CH?: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_TXCFG ;read clcok_status + LBCO &R27.w0, ICSS_CFG, SCRATCH1.w0, 2 + AND R27.b2, R27.b1, ENDAT_ENABLE_CHx_IN_USE ; doing AND of 8th(ch0), 9th(ch1) and 10th(ch2) bits with channel mask + QBNE ENDAT_TD_LAST_RISING_CLOCK_MULTI_CH?, R27.b2, ENDAT_ENABLE_CHx_IN_USE ; check clock_status bits for all connected channels +;set PRU counter to zero + SBCO &R14, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 +;waiting for RX complete + LDI R28.w0, 0 +W_RX_MULTI?: + QBBC ENDAT_SKIP_MULTI_WRX_CH0?, ENDAT_ENABLE_CHx_IN_USE, 0 + QBBS ENDAT_SKIP_MULTI_WRX_CH0?, R28.b1, 0 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0 + LBCO &R27, ICSS_CFG, SCRATCH1.w0, 4 + QBBS ENDAT_SKIP_MULTI_WRX_CH0?, R27, 28 + LBCO &R27, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + SBCO &R27, PRUx_DMEM, ENDAT_CH0_RT_OFFSET, 4 + SET R28.b1, R28.b1, 0 +ENDAT_SKIP_MULTI_WRX_CH0?: + +;ch1 waiting for RX complete + QBBC ENDAT_SKIP_MULTI_WRX_CH1?, ENDAT_ENABLE_CHx_IN_USE, 1 + QBBS ENDAT_SKIP_MULTI_WRX_CH1?, R28.b1, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0 + LBCO &R27, ICSS_CFG, SCRATCH1.w0, 4 + QBBS ENDAT_SKIP_MULTI_WRX_CH1?, R27, 28 + LBCO &R27, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + SBCO &R27, PRUx_DMEM, ENDAT_CH1_RT_OFFSET, 4 + SET R28.b1, R28.b1, 1 +ENDAT_SKIP_MULTI_WRX_CH1?: +;ch2 waiting for RX complete + QBBC ENDAT_SKIP_MULTI_WRX_CH2?, ENDAT_ENABLE_CHx_IN_USE, 2 + QBBS ENDAT_SKIP_MULTI_WRX_CH2?, R28.b1, 2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0 + LBCO &R27, ICSS_CFG, SCRATCH1.w0, 4 + QBBS ENDAT_SKIP_MULTI_WRX_CH2?, R27, 28 + LBCO &R27, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + SBCO &R27, PRUx_DMEM, ENDAT_CH2_RT_OFFSET, 4 + SET R28.b1, R28.b1, 2 +ENDAT_SKIP_MULTI_WRX_CH2?: + AND R28.b0, R28.b1, ENDAT_ENABLE_CHx_IN_USE + QBNE W_RX_MULTI?, R28.b0, ENDAT_ENABLE_CHx_IN_USE + .endm + + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; receive & down sample (invoked for non-CRC bits) +; Returns: received data in Rx, Ry, Rz - caller has to zero or provide value to continue +; cnt - number of rx bits, should be <= 32 +; ff[0-4] - flip flops, ex - temporary variable +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC .macro Rx, Ry, Rz, cnt, ff0, ff1, ff2, ff3, ff4, ex + LOOP RX_RECEIVE_DOWNSAMPLE_CRC_LOOP?, cnt ; Run loop for receive bits + LSL Rx, Rx, 1 + LSL Ry, Ry, 1 + LSL Rz, Rz, 1 +WB13?: + AND SCRATCH.b0, R31.b3, ENDAT_ENABLE_CHx_IN_USE + QBNE WB13?, SCRATCH.b0, ENDAT_ENABLE_CHx_IN_USE ; wait for valid + + QBBS ENDAT_SKIP33_CH0?, R31, 4 ; Check the Mid bit of received oversampled data + MOV ex.b0, ff4.b0 ; if code[i] = 0, ex = ff4 (ex = ff4 ^ 0) + JMP ENDAT_SKIP33A_CH0? +ENDAT_SKIP33_CH0?: + NOT ex.b0, ff4.b0 ; if code[i] = 1, ex = !ff4 (ex = ff4 ^ 1) + OR Rx, Rx, 1 +ENDAT_SKIP33A_CH0?: + + QBBS ENDAT_SKIP33_CH1?, R31, 4 + 8 ; Check the Mid bit of received oversampled data + MOV ex.b1, ff4.b1 ; if code[i] = 0, ex = ff4 (ex = ff4 ^ 0) + JMP ENDAT_SKIP33A_CH1? +ENDAT_SKIP33_CH1?: + NOT ex.b1, ff4.b1 ; if code[i] = 1, ex = !ff4 (ex = ff4 ^ 1) + OR Ry, Ry, 1 +ENDAT_SKIP33A_CH1?: + + QBBS ENDAT_SKIP33_CH2?, R31, 4 + 16 ; Check the Mid bit of received oversampled data + MOV ex.b2, ff4.b2 ; if code[i] = 0, ex = ff4 (ex = ff4 ^ 0) + JMP ENDAT_SKIP33A_CH2? +ENDAT_SKIP33_CH2?: + NOT ex.b2, ff4.b2 ; if code[i] = 1, ex = !ff4 (ex = ff4 ^ 1) + OR Rz, Rz, 1 +ENDAT_SKIP33A_CH2?: + + MOV R31.b3, SCRATCH.b0 ; clear valid bit + + MOV ff4, ff3 + XOR ff3, ff2, ex + MOV ff2, ff1 + XOR ff1, ff0, ex + MOV ff0, ex +RX_RECEIVE_DOWNSAMPLE_CRC_LOOP?: + .endm + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; receive & down sample (invoked for CRC bits) +; Returns: received CRC bits pushed onto Rx, Ry, Rz - caller has to provide value to continue, Ra - received CRC +; cnt - number of rx bits, should be <= 32 +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +M_OTF_RECEIVE_AND_DOWNSAMPLE .macro Rx, Ry, Rz, Ra, cnt + LOOP RX_RECEIVE_DOWNSAMPLE_LOOP?, cnt ; Run loop for receive bits + LSL Rx, Rx, 1 + LSL Ry, Ry, 1 + LSL Rz, Rz, 1 + LSL Ra, Ra, 1 ; this will do for all 3 channels +WB14?: + AND SCRATCH.b0, R31.b3, ENDAT_ENABLE_CHx_IN_USE + QBNE WB14?, SCRATCH.b0, ENDAT_ENABLE_CHx_IN_USE ; wait for valid + + QBBS ENDAT_SKIP34_CH0?, R31, 4 ; Check the Mid bit of received oversampled data + JMP ENDAT_SKIP34A_CH0? +ENDAT_SKIP34_CH0?: + OR Rx, Rx, 1 + OR Ra.b0, Ra.b0, 1 +ENDAT_SKIP34A_CH0?: + + QBBS ENDAT_SKIP34_CH1?, R31, 4 + 8 ; Check the Mid bit of received oversampled data + JMP ENDAT_SKIP34A_CH1? +ENDAT_SKIP34_CH1?: + OR Ry, Ry, 1 + OR Ra.b1, Ra.b1, 1 +ENDAT_SKIP34A_CH1?: + + QBBS ENDAT_SKIP34_CH2?, R31, 4 + 16 ; Check the Mid bit of received oversampled data + JMP ENDAT_SKIP34A_CH2? +ENDAT_SKIP34_CH2?: + OR Rz, Rz, 1 + OR Ra.b2, Ra.b2, 1 +ENDAT_SKIP34A_CH2?: + + MOV R31.b3, SCRATCH.b0 ; clear valid bit +RX_RECEIVE_DOWNSAMPLE_LOOP?: + .endm + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; Format received CRC - transalate byte to bit & reverse +; requires: ff[0-4] in R6, R7, R8, R9, R10 +; returns: formattted CRC in R12 +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +FN_FORMAT_CRC: + ZERO &R12, 4 + + LOOP ENDAT_CRC_CH0_END?, 3 + + LSL R6, R6, 8 + LSL R7, R7, 8 + LSL R8, R8, 8 + LSL R9, R9, 8 + LSL R10, R10, 8 + + ; ch2 would be initially in b0, at the end of the loop it would have reached b2, finally ch[0-2] would end up @b[0-2] as reqd. + ; no-op in first interation + LSL R12, R12, 8 + + QBBS ENDAT_CRC_CH0_BIT1?, R6.b3, 0 + SET R12.b0, R12.b0, 0 +ENDAT_CRC_CH0_BIT1?: + QBBS ENDAT_CRC_CH0_BIT2?, R7.b3, 0 + SET R12.b0, R12.b0, 1 +ENDAT_CRC_CH0_BIT2?: + QBBS ENDAT_CRC_CH0_BIT3?, R8.b3, 0 + SET R12.b0, R12.b0, 2 +ENDAT_CRC_CH0_BIT3?: + QBBS ENDAT_CRC_CH0_BIT4?, R9.b3, 0 + SET R12.b0, R12.b0, 3 +ENDAT_CRC_CH0_BIT4?: + QBBS ENDAT_CRC_CH0_END?, R10.b3, 0 + SET R12.b0, R12.b0, 4 +ENDAT_CRC_CH0_END?: + + RET2 + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; receive, down sample, calculate CRC +; Returns: received data (Ra, Rb, Rc, Rd, Re, Rf), CRC status (Ts-th bit of R0.b[0-2]) - set for success, clear for failure +; Requires: rx_size (R2.w1) +; Uses: R6.b[0-2] (ff0), R7.b[0-2] (ff1), R8.b[0-2] (ff2), R9.b[0-2] (ff3), R10.b[0-2] (ff4), R11.b[0-2](ex,crc_recvd), R12.b[0-2](crc_calc), R2.b3(cnt) +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +M_OTF_RECEIVE .macro Ra, Rb, Rc, Rd, Re, Rf, Rt, Ts + + ; initialize CRC flip-flops, i.e. ff[0-4] = 1 + LDI32 R6, 0x010101 + MOV R7, R6 + MOV R8, R6 + MOV R9, R6 + MOV R10, R6 + + ; wait for valid bit +WB11?: + AND SCRATCH.b0, R31.b3, ENDAT_ENABLE_CHx_IN_USE + QBNE WB11?, SCRATCH.b0, ENDAT_ENABLE_CHx_IN_USE; wait for valid + ; Note: 2 cycles are reqd before again checking for valid bit, and that is achieved below + MOV R31.b3, SCRATCH.b0 ; clear valid bit + + ; receive data + SUB R2.b3, R2.w1, 5 ; minus CRC bits + QBGE ENDAT_RX_LE_32_BITS?, R2.b3, 32 + LDI R2.b3, 32 + M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC Ra, Rc, Re, R2.b3, R6, R7, R8, R9, R10, R11 + SUB R2.b3, R2.w1, (32 + 5) ; note taking care of CRC bits + M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC Rb, Rd, Rf, R2.b3, R6, R7, R8, R9, R10, R11 + ZERO &R11, 4 ; clear crc_recvd + LDI R2.b3, 5 + M_OTF_RECEIVE_AND_DOWNSAMPLE Rb, Rd, Rf, R11, R2.b3 + JMP ENDAT_RX_CRC? +ENDAT_RX_LE_32_BITS?: + M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC Ra, Rc, Re, R2.b3, R6, R7, R8, R9, R10, R11 + ZERO &R11, 4 ; clear crc_recvd + RSB R2.b3, R2.b3, 32 + MIN R2.b3, R2.b3, 5 + M_OTF_RECEIVE_AND_DOWNSAMPLE Ra, Rc, Re, R11, R2.b3 + QBEQ ENDAT_RX_CRC?, R2.b3, 5 + RSB R2.b3, R2.b3, 5 + M_OTF_RECEIVE_AND_DOWNSAMPLE Rb, Rd, Rf, R11, R2.b3 +ENDAT_RX_CRC?: + QBEQ ENDAT_MULTI_SKIP_CALCU_RT?, Rt, 0 + QBBC ENDAT_MULTI_SKIP_CALCU_RT?, Rt, Ts + M_CALC_RECOV_TIME_MULTI_CH +ENDAT_MULTI_SKIP_CALCU_RT?: + ; FN_FORMAT_CRC returns formatted CRC in R12, requires R6-R10 (ff0-4) + CALL2 FN_FORMAT_CRC + + ; crc: calculated - R12, received - R11 + QBEQ ENDAT_CRC_CH0_SUCCESS?, R12.b0, R11.b0 + CLR R0.b0, R0.b0, Ts + JMP ENDAT_CRC_CH0_FAILURE? +ENDAT_CRC_CH0_SUCCESS?: + SET R0.b0, R0.b0, Ts +ENDAT_CRC_CH0_FAILURE?: + + QBEQ ENDAT_CRC_CH1_SUCCESS?, R12.b1, R11.b1 + CLR R0.b1, R0.b1, Ts + JMP ENDAT_CRC_CH1_FAILURE? +ENDAT_CRC_CH1_SUCCESS?: + SET R0.b1, R0.b1, Ts +ENDAT_CRC_CH1_FAILURE?: + + QBEQ ENDAT_CRC_CH2_SUCCESS?, R12.b2, R11.b2 + CLR R0.b2, R0.b2, Ts + JMP ENDAT_CRC_CH2_FAILURE? +ENDAT_CRC_CH2_SUCCESS?: + SET R0.b2, R0.b2, Ts +ENDAT_CRC_CH2_FAILURE?: + .endm + .else ; ENABLE_MULTI_CHANNEL + + + +; macro for ch0 +M_CALC_RECOV_TIME_CH0 .macro + ;enable PRU cycle counter + M_ENABLE_PRU_CYCLE_COUNTER + ZERO &R14, 4 +ENDAT_TD_LAST_RISING_CLOCK_CH0?: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_TXCFG + LBCO &R27.w0, ICSS_CFG, SCRATCH1.w0, 2 + QBBC ENDAT_TD_LAST_RISING_CLOCK_CH0?, R27.w0, 8 + ;set pru counter to zero + SBCO &R14, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + ; wait for rx complete +WRXCH0?: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0 + LBCO &R27, ICSS_CFG, SCRATCH1.w0, 4 + QBBS WRXCH0?, R27, 28 + + ; read pru counter at time when rx start + + LBCO &R27, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + ; store in DMEM + SBCO &R27, PRUx_DMEM, ENDAT_CH0_RT_OFFSET, 4 + + .endm +;macro for channel 1 +M_CALC_RECOV_TIME_CH1 .macro + ; enable PRU cycle counter + M_ENABLE_PRU_CYCLE_COUNTER + ZERO &R14, 4 +ENDAT_TD_LAST_RISING_CLOCK_CH1?: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_TXCFG + LBCO &R27.w0, ICSS_CFG, SCRATCH1.w0, 2 + QBBC ENDAT_TD_LAST_RISING_CLOCK_CH1?, R27.w0, 9 + + ;set pru counter to zero + SBCO &R14, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + + ; wait for rx complete +WRXCH1?: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0 + LBCO &R27, ICSS_CFG, SCRATCH1.w0, 4 + QBBS WRXCH1?, R27, 28 + + ; read pru counter at time when rx start + LBCO &R27, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + + ; store in DMEM + SBCO &R27, PRUx_DMEM, ENDAT_CH1_RT_OFFSET, 4 + + .endm +;macro for ch2 +M_CALC_RECOV_TIME_CH2 .macro + ;enable PRU counter + M_ENABLE_PRU_CYCLE_COUNTER + ZERO &R14, 4 +ENDAT_TD_LAST_RISING_CLOCK_CH2?: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_TXCFG + LBCO &R27.w0, ICSS_CFG, SCRATCH1.w0, 2 + QBBC ENDAT_TD_LAST_RISING_CLOCK_CH2?, R27.w0, 10 + + ;set pru counter to zero + .if $isdefed("ENABLE_MULTI_MAKE_TXPRU") + SBCO &R14, c28, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .else + SBCO &R14, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .endif + + + ; wait for rx complete +WRXCH2?: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0 + LBCO &R27, ICSS_CFG, SCRATCH1.w0, 4 + QBBS WRXCH2?, R27, 28 + + + ; read pru counter at time when rx start + .if $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LBCO &R27, c28, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .else + LBCO &R27, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .endif + + ; store in DMEM + SBCO &R27, PRUx_DMEM, ENDAT_CH2_RT_OFFSET, 4 + .endm + + ;macro for RT +M_RECOVERY_TIME_CALCU .macro + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + M_CALC_RECOV_TIME_CH0 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + M_CALC_RECOV_TIME_CH1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + M_CALC_RECOV_TIME_CH2 + .else + QBBC ENDAT_SKIP_RT_CH0?, ENDAT_ENABLE_CHx, 0 + M_CALC_RECOV_TIME_CH0 +ENDAT_SKIP_RT_CH0?: + QBBC ENDAT_SKIP_RT_CH1?, ENDAT_ENABLE_CHx, 1 + M_CALC_RECOV_TIME_CH1 +ENDAT_SKIP_RT_CH1?: + QBBC ENDAT_SKIP_RT_CH2?, ENDAT_ENABLE_CHx, 2 + M_CALC_RECOV_TIME_CH2 +ENDAT_SKIP_RT_CH2?: + .endif + .endm +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; receive & down sample (invoked for non-CRC bits) +; Returns: received data in Rx - caller has to zero or provide value to continue +; valid_bit - valid bit for selected channel, bit_idx - midbit of rx fifo of selected channel, cnt - number of rx bits, should be <= 32 +; ff[0-4] - flip flops, ex - temporary variable +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC .macro Rx, cnt, valid_bit, bit_idx, ff0, ff1, ff2, ff3, ff4, ex + LOOP RX_RECEIVE_DOWNSAMPLE_CRC_LOOP?, cnt ; Run loop for receive bits + LSL Rx, Rx, 1 +WB13?: + QBBC WB13?, R31, valid_bit ; wait for valid + QBBS ENDAT_SKIP33_CHx?, R31, bit_idx ; Check the Mid bit of received oversampled data + MOV ex, ff4 ; if code[i] = 0, ex = ff4 (ex = ff4 ^ 0) + JMP ENDAT_SKIP33A_CHx? +ENDAT_SKIP33_CHx?: + NOT ex, ff4 ; if code[i] = 1, ex = !ff4 (ex = ff4 ^ 1) + OR Rx, Rx, 1 +ENDAT_SKIP33A_CHx?: + SET R31, R31, valid_bit ; clear valid bit + MOV ff4, ff3 + XOR ff3, ff2, ex + MOV ff2, ff1 + XOR ff1, ff0, ex + MOV ff0, ex +RX_RECEIVE_DOWNSAMPLE_CRC_LOOP?: + .endm + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; receive & down sample (invoked for CRC bits) +; Returns: received CRC bits pushed onto Rx - caller has to provide value to continue, Ry - received CRC +; valid_bit - valid bit for selected channel, bit_idx - midbit of rx fifo of selected channel, cnt - number of rx bits, should be <= 32 +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +M_OTF_RECEIVE_AND_DOWNSAMPLE .macro Rx, Ry, cnt, valid_bit, bit_idx + LOOP RX_RECEIVE_DOWNSAMPLE_LOOP?, cnt ; Run loop for receive bits + LSL Rx, Rx, 1 + LSL Ry, Ry, 1 +WB14?: + QBBC WB14?, R31, valid_bit ; wait for valid + QBBS ENDAT_SKIP34_CHx?, R31, bit_idx ; Check the Mid bit of received oversampled data + JMP ENDAT_SKIP34A_CHx? +ENDAT_SKIP34_CHx?: + OR Rx, Rx, 1 + OR Ry, Ry, 1 +ENDAT_SKIP34A_CHx?: + SET R31, R31, valid_bit ; clear valid bit +RX_RECEIVE_DOWNSAMPLE_LOOP?: + .endm + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; calculate CRC, result in crc +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +M_CALC_CRC .macro crc, ff0, ff1, ff2, ff3, ff4 + LDI crc, 0 + QBBS ENDAT_CRC_BIT1?, ff0, 0 + SET crc, crc, 0 +ENDAT_CRC_BIT1?: + QBBS ENDAT_CRC_BIT2?, ff1, 0 + SET crc, crc, 1 +ENDAT_CRC_BIT2?: + QBBS ENDAT_CRC_BIT3?, ff2, 0 + SET crc, crc, 2 +ENDAT_CRC_BIT3?: + QBBS ENDAT_CRC_BIT4?, ff3, 0 + SET crc, crc, 3 +ENDAT_CRC_BIT4?: + QBBS ENDAT_CRC_END?, ff4, 0 + SET crc, crc, 4 +ENDAT_CRC_END?: + .endm + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; receive, down sample, calculate CRC +; Returns: received data (Ra,Rb), CRC status (Ts-th bit of R0.b0) - set for success, clear for failure +; Requires: rx_size (R2.w1), valid_bit (R3.b0), bit_idx (R3.b1) +; Uses: R12.b0 (ff0), R12.b1 (ff1), R12.b2 (ff2), R12.b3 (ff3), R3.b2 (ff4), R3.b3(ex,crc_recvd), R2.b3 (crc_calc,cnt) +; REVISIT: More optimization may be required or can be done at least in M_INIT_CRC_FLIP_FLOPS - defer those till a requirement comes +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +M_OTF_RECEIVE .macro Ra, Rb, Rt, Ts + + ; initialize CRC flip-flops, i.e. ff[0-4] = 1 + LDI32 R12, 0x01010101 + LDI R3.b2, 0x01 + + ; wait for valid bit +WB11?: + QBBC WB11?, R31, R3.b0 ; wait for valid + ; Note: 2 cycles are reqd before again checking for valid bit, and that is achieved below + SET R31, R31, R3.b0 ; clear valid bit + + ; receive data + SUB R2.b3, R2.w1, 5 ; minus CRC bits + QBGE ENDAT_RX_LE_32_BITS?, R2.b3, 32 + LDI R2.b3, 32 + M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC Ra, R2.b3, R3.b0, R3.b1, R12.b0, R12.b1, R12.b2, R12.b3, R3.b2, R3.b3 + SUB R2.b3, R2.w1, (32 + 5) ; note taking care of CRC bits + M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC Rb, R2.b3, R3.b0, R3.b1, R12.b0, R12.b1, R12.b2, R12.b3, R3.b2, R3.b3 + LDI R3.b3, 0 ; clear crc_recvd + LDI R2.b3, 5 + M_OTF_RECEIVE_AND_DOWNSAMPLE Rb, R3.b3, R2.b3, R3.b0, R3.b1 + JMP ENDAT_RX_CRC? +ENDAT_RX_LE_32_BITS?: + M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC Ra, R2.b3, R3.b0, R3.b1, R12.b0, R12.b1, R12.b2, R12.b3, R3.b2, R3.b3 + LDI R3.b3, 0 ; clear crc_recvd + RSB R2.b3, R2.b3, 32 + MIN R2.b3, R2.b3, 5 + M_OTF_RECEIVE_AND_DOWNSAMPLE Ra, R3.b3, R2.b3, R3.b0, R3.b1 + QBEQ ENDAT_RX_CRC?, R2.b3, 5 + RSB R2.b3, R2.b3, 5 + M_OTF_RECEIVE_AND_DOWNSAMPLE Rb, R3.b3, R2.b3, R3.b0, R3.b1 +ENDAT_RX_CRC?: + QBEQ ENDAT_SKIP_CALCU_RT?, Rt, 0 + QBBC ENDAT_SKIP_CALCU_RT?, Rt, Ts + M_RECOVERY_TIME_CALCU +ENDAT_SKIP_CALCU_RT?: + M_CALC_CRC R2.b3, R12.b0, R12.b1, R12.b2, R12.b3, R3.b2 + + QBEQ ENDAT_CRC_SUCCESS?, R2.b3, R3.b3 ; crc: calculated - R2.b3, received - R3.b3 + CLR R0.b0, R0.b0, Ts + JMP ENDAT_RECEIVE_DOWN_SAMPLE_END? +ENDAT_CRC_SUCCESS?: + SET R0.b0, R0.b0, Ts +ENDAT_RECEIVE_DOWN_SAMPLE_END?: + .endm + + .endif ; ENABLE_MULTI_CHANNEL + + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; continuous mode handling +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; + .if !$isdefed("ENABLE_MULTI_CHANNEL") +FN_CONTINUOUS_MODE: + + LBCO &R0, PRUx_DMEM, ENDAT_CH0_CMD_WORD_0_OFFSET, 8 + + QBBC ENDAT_SKIP31_CH0, ENDAT_ENABLE_CHx, 0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN | ENDAT_TX_CH0_SEL) +ENDAT_SKIP31_CH0: + QBBC ENDAT_SKIP31_CH1, ENDAT_ENABLE_CHx, 1 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN | ENDAT_TX_CH1_SEL) +ENDAT_SKIP31_CH1: + QBBC ENDAT_SKIP31_CH2, ENDAT_ENABLE_CHx, 2 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN | ENDAT_TX_CH2_SEL) +ENDAT_SKIP31_CH2: + + MOV R30.b0, R0.b0 ; load cmd to tx fifo + + MOV R2.w1, R1.b0 + LSL R1.b0, R1.b1, 3 + CALL2 FN_SEND + +LOOP_CONTINUOUS_MODE: + + LDI32 R15, 0 + LDI32 R16, 0 + + ; store valid bit & rx fifo bit to be checked based on selected channel + QBBC ENDAT_SKIP34_PRE_CH0, ENDAT_ENABLE_CHx, 0 + LDI R3.b0, 24 + LDI R3.b1, 4 +ENDAT_SKIP34_PRE_CH0: + QBBC ENDAT_SKIP34_PRE_CH1, ENDAT_ENABLE_CHx, 1 + LDI R3.b0, 25 + LDI R3.b1, 4 + 8 +ENDAT_SKIP34_PRE_CH1: + QBBC ENDAT_SKIP34_PRE_CH2, ENDAT_ENABLE_CHx, 2 + LDI R3.b0, 26 + LDI R3.b1, 4 + 16 +ENDAT_SKIP34_PRE_CH2: + ; set bit for calculation of RT + LDI R27.b0, 0x1 + QBBC ENDAT_SKIP_RT_FOR_CD2_1, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 2 + QBBS ENDAT_RT_FOR_CD2_2, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 0 +ENDAT_SKIP_RT_FOR_CD2_1: + ; unset bit for calculation of RT + LDI R27.b0, 0 +ENDAT_RT_FOR_CD2_2: + + .if $isdefed("ENABLE_MULTI_CHANNEL") + M_OTF_RECEIVE R15, R16, R19, R20, R23, R24, R27.b0, 0 + .else + M_OTF_RECEIVE R15, R16, R27.b0, 0 + .endif + + QBBC ENDAT_SKIP35_CH0, ENDAT_ENABLE_CHx, 0 + CLR R30.b3, R30.b3.t0 ; disable rx +ENDAT_SKIP35_CH0: + QBBC ENDAT_SKIP35_CH1, ENDAT_ENABLE_CHx, 1 + CLR R30.b3, R30.b3.t1 ; disable rx +ENDAT_SKIP35_CH1: + QBBC ENDAT_SKIP35_CH2, ENDAT_ENABLE_CHx, 2 + CLR R30.b3, R30.b3.t2 ; disable rx +ENDAT_SKIP35_CH2: + + ; Update CRC status. Update i/f buffer iff CRC success, if failure increment error count + QBBC ENDAT_SKIP36_CH0, ENDAT_ENABLE_CHx, 0 + LBCO &SCRATCH, PRUx_DMEM, ENDAT_CH0_CRC_ERR_COUNTER_OFFSET, 4 + QBBC ENDAT_SKIP36A_CH0, R0, 0 ; (R0.t0 = 0) => crc failure + SET SCRATCH.b0, SCRATCH.b0, 0 + SBCO &R15, PRUx_DMEM, ENDAT_CH0_POSITION_DATA_WORD0_OFFSET, 8 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH0_CRC_ERR_COUNTER_OFFSET, 4 + JMP ENDAT_SKIP36_CH0 +ENDAT_SKIP36A_CH0: + CLR SCRATCH.b0, SCRATCH.b0, 0 + ADD SCRATCH.b1, SCRATCH.b1, 1 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH0_CRC_ERR_COUNTER_OFFSET, 4 +ENDAT_SKIP36_CH0: + QBBC ENDAT_SKIP36_CH1, ENDAT_ENABLE_CHx, 1 + LBCO &SCRATCH, PRUx_DMEM, ENDAT_CH1_CRC_ERR_COUNTER_OFFSET, 4 + QBBC ENDAT_SKIP36A_CH1, R0, 0 ; (R0.t0 = 0) => crc failure + SET SCRATCH.b0, SCRATCH.b0, 0 + SBCO &R15, PRUx_DMEM, ENDAT_CH1_POSITION_DATA_WORD0_OFFSET, 8 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH1_CRC_ERR_COUNTER_OFFSET, 4 + JMP ENDAT_SKIP36_CH1 +ENDAT_SKIP36A_CH1: + CLR SCRATCH.b0, SCRATCH.b0, 0 + ADD SCRATCH.b1, SCRATCH.b1, 1 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH1_CRC_ERR_COUNTER_OFFSET, 4 +ENDAT_SKIP36_CH1: + QBBC ENDAT_SKIP36_CH2, ENDAT_ENABLE_CHx, 2 + LBCO &SCRATCH, PRUx_DMEM, ENDAT_CH2_CRC_ERR_COUNTER_OFFSET, 4 + QBBC ENDAT_SKIP36A_CH2, R0, 0 ; (R0.t0 = 0) => crc failure + SET SCRATCH.b0, SCRATCH.b0, 0 + SBCO &R15, PRUx_DMEM, ENDAT_CH2_POSITION_DATA_WORD0_OFFSET, 8 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH2_CRC_ERR_COUNTER_OFFSET, 4 + JMP ENDAT_SKIP36_CH2 +ENDAT_SKIP36A_CH2: + CLR SCRATCH.b0, SCRATCH.b0, 0 + ADD SCRATCH.b1, SCRATCH.b1, 1 + SBCO &SCRATCH, PRUx_DMEM, ENDAT_CH2_CRC_ERR_COUNTER_OFFSET, 4 +ENDAT_SKIP36_CH2: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG1+2 + LBCO &R0.w0, ICSS_CFG, SCRATCH1.w0, 2 + LSR R0.w0, R0.w0, 2 + LOOP RX_EN_LOOP, R0.w0 + MOV R0, R0 +RX_EN_LOOP: + + QBBC ENDAT_SKIP37_CH0, ENDAT_ENABLE_CHx, 0 + SET R30.b3, R30.b3.t0 ; enable rx +ENDAT_SKIP37_CH0: + QBBC ENDAT_SKIP37_CH1, ENDAT_ENABLE_CHx, 1 + SET R30.b3, R30.b3.t1 ; enable rx +ENDAT_SKIP37_CH1: + QBBC ENDAT_SKIP37_CH2, ENDAT_ENABLE_CHx, 2 + SET R30.b3, R30.b3.t2 ; enable rx +ENDAT_SKIP37_CH2: + LBCO &R0.b0, PRUx_DMEM, ENDAT_CH0_INTFC_CMD_TRIGGER_OFFSET, 1 + QBBS LOOP_CONTINUOUS_MODE, R0.b0, 7 + + SET R31, ENDAT_TX_GLOBAL_REINIT + QBBC ENDAT_SKIP32_CH0, ENDAT_ENABLE_CHx, 0 + CLR R30.b3, R30.b3.t0 ; disable rx +WB8: + QBBS WB8, R31, 5 +ENDAT_SKIP32_CH0: + QBBC ENDAT_SKIP32_CH1, ENDAT_ENABLE_CHx, 1 + CLR R30.b3, R30.b3.t1 ; disable rx +WB9: + QBBS WB9, R31, 13 +ENDAT_SKIP32_CH1: + QBBC ENDAT_SKIP32_CH2, ENDAT_ENABLE_CHx, 2 + CLR R30.b3, R30.b3.t2 ; disable rx +WB10: + QBBS WB10, R31, 21 +ENDAT_SKIP32_CH2: + + RET + + .endif ; ENABLE_MULTI_CHANNEL + + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; R1.b0: Number of transmit bits * 8 +; R2.w1: Number of receive bits +; Program rx_frame_size and tx_frame_size for clock/FIFO control +; Start tranmit on channel 0/1/2 +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +FN_SEND: + ; From spec: Time out for polling Start bit (50 ms), Min Time between back to back command is 1 ms + ; Program tx_frame_size ICSS_CFG_PRUx_ENDAT_CH0_CFG0[15:11] to 30 bits + ; Program rx_frame_size in ICSS_CFG_PRUx_ENDAT_CH0_CFG0[27:16] + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;load rx and tx size in channel 0 for RTU PRU + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1 + LBCO &R2.b0, ICSS_CFG, SCRATCH1.w0, 1 + ;LBCO &R2.b0, ICSS_CFG, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1, 1 + AND R2.b0, R2.b0, 0x7 + OR R2.b0, R2.b0, R1.b0 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1 + SBCO &R2, ICSS_CFG, SCRATCH1.w0, 1 + LBCO &SCRATCH.w2, PRUx_DMEM, ENDAT_CH0_CLOCK_LESS_FOR_TD, 2 + SUB SCRATCH.w0, R2.w1, SCRATCH.w2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+2 + SBCO &SCRATCH.w0, ICSS_CFG, SCRATCH1.w0, 2 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;load rx and tx size in channel 1 for PRU + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+1 + LBCO &R2.b0, ICSS_CFG, SCRATCH1.w0, 1 + AND R2.b0, R2.b0, 0x7 + OR R2.b0, R2.b0, R1.b0 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+1 + SBCO &R2, ICSS_CFG, SCRATCH1.w0, 1 + LBCO &SCRATCH.w2, PRUx_DMEM, ENDAT_CH1_CLOCK_LESS_FOR_TD, 2 + SUB SCRATCH.w0, R2.w1, SCRATCH.w2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+2 + SBCO &SCRATCH.w0, ICSS_CFG, SCRATCH1.w0, 2 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;load rx and tx size in channel 2 for TXPRU + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+1 + LBCO &R2.b0, ICSS_CFG, SCRATCH1.w0, 1 + AND R2.b0, R2.b0, 0x7 + OR R2.b0, R2.b0, R1.b0 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+1 + SBCO &R2, ICSS_CFG, SCRATCH1.w0, 1 + LBCO &SCRATCH.w2, PRUx_DMEM, ENDAT_CH2_CLOCK_LESS_FOR_TD, 2 + SUB SCRATCH.w0, R2.w1, SCRATCH.w2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+2 + SBCO &SCRATCH.w0, ICSS_CFG, SCRATCH1.w0, 2 + .else ;load rx and tx size when load share mode is not enabled + QBBC ENDAT_SKIP15_CH0, ENDAT_ENABLE_CHx, 0 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1 + LBCO &R2.b0, ICSS_CFG, SCRATCH1.w0, 1 + ;LBCO &R2.b0, ICSS_CFG, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1, 1 + AND R2.b0, R2.b0, 0x7 + OR R2.b0, R2.b0, R1.b0 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1 + SBCO &R2, ICSS_CFG, SCRATCH1.w0, 1 + LBCO &SCRATCH.w2, PRUx_DMEM, ENDAT_CH0_CLOCK_LESS_FOR_TD, 2 + SUB SCRATCH.w0, R2.w1, SCRATCH.w2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+2 + SBCO &SCRATCH.w0, ICSS_CFG, SCRATCH1.w0, 2 +ENDAT_SKIP15_CH0: + QBBC ENDAT_SKIP15_CH1, ENDAT_ENABLE_CHx, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+1 + LBCO &R2.b0, ICSS_CFG, SCRATCH1.w0, 1 + AND R2.b0, R2.b0, 0x7 + OR R2.b0, R2.b0, R1.b0 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+1 + SBCO &R2, ICSS_CFG, SCRATCH1.w0, 1 + LBCO &SCRATCH.w2, PRUx_DMEM, ENDAT_CH1_CLOCK_LESS_FOR_TD, 2 + SUB SCRATCH.w0, R2.w1, SCRATCH.w2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+2 + SBCO &SCRATCH.w0, ICSS_CFG, SCRATCH1.w0, 2 +ENDAT_SKIP15_CH1: + QBBC ENDAT_SKIP15_CH2, ENDAT_ENABLE_CHx, 2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+1 + LBCO &R2.b0, ICSS_CFG, SCRATCH1.w0, 1 + AND R2.b0, R2.b0, 0x7 + OR R2.b0, R2.b0, R1.b0 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+1 + SBCO &R2, ICSS_CFG, SCRATCH1.w0, 1 + LBCO &SCRATCH.w2, PRUx_DMEM, ENDAT_CH2_CLOCK_LESS_FOR_TD, 2 + SUB SCRATCH.w0, R2.w1, SCRATCH.w2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+2 + SBCO &SCRATCH.w0, ICSS_CFG, SCRATCH1.w0, 2 +ENDAT_SKIP15_CH2: + .endif + ; CLR R30, ENDAT_CH0_RX_EN ; Received required number of bits - disable RX +FN_SEND_WAIT_TILL_TX_CH0_BUSY: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_TXCFG + LBCO &R2.b3, ICSS_CFG, SCRATCH1.w0, 1 + ; Determines when you can assert tx go to issue a new TX frame + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;waiting to complete tx fifo for ch0 in RTU + QBBS FN_SEND_WAIT_TILL_TX_CH0_BUSY, R2.b3, 5 ; Ch0 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;waiting to complete tx fifo for ch1 in PRU + QBBS FN_SEND_WAIT_TILL_TX_CH0_BUSY, R2.b3, 6 ; Ch1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;waiting to complete tx fifo for ch2 in TXPRU + QBBS FN_SEND_WAIT_TILL_TX_CH0_BUSY, R2.b3, 7 ; Ch2 + .elseif $isdefed("ENABLE_MULTI_CHANNEL") + AND R2.b3, R2.b3, 0xE0 ; TODO : Assumption is that all 3 channels are enabled + QBNE FN_SEND_WAIT_TILL_TX_CH0_BUSY, R2.b3, 0 + .else + QBBC ENDAT_SKIP17_CH0, ENDAT_ENABLE_CHx, 0 + QBBS FN_SEND_WAIT_TILL_TX_CH0_BUSY, R2.b3, 5 ; Ch0 +ENDAT_SKIP17_CH0: + QBBC ENDAT_SKIP17_CH1, ENDAT_ENABLE_CHx, 1 + QBBS FN_SEND_WAIT_TILL_TX_CH0_BUSY, R2.b3, 6 ; Ch1 +ENDAT_SKIP17_CH1: + QBBC ENDAT_SKIP17_CH2, ENDAT_ENABLE_CHx, 2 + QBBS FN_SEND_WAIT_TILL_TX_CH0_BUSY, R2.b3, 7 ; Ch2 +ENDAT_SKIP17_CH2: + .endif + + .if $isdefed("ENABLE_MULTI_CHANNEL") + SET R31, ENDAT_TX_GLOBAL_GO + .else + SET R31, ENDAT_TX_CHANNEL_GO + .endif + RET2 + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; Send EnDat2.2 command supplement to encoder after receiving additional info1/2 +; Block till last bit is sent +; Inputs: +; R0.b3: Number of bytes to send in command suplement block address. Its normally one byte +; post 8-bit address, 16-bit dummy parameter... +; R1.b3: Block address +; Uses: R2, SCRATCH +; TODO: Check for multi channel and channel3 support +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +FN_SEND_2_2: + ; Program tx_frame_size ICSS_CFG_PRUx_ENDAT_CH0_CFG0[15:11] to 0 + ; Program rx_frame_size in ICSS_CFG_PRUx_ENDAT_CH0_CFG0[27:16] to 0 + ZERO &SCRATCH, 4 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1 + LBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 1 + AND SCRATCH.b0, SCRATCH.b0, 0x7 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1 + SBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 3 ; Ch0 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+1 + LBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 1 + AND SCRATCH.b0, SCRATCH.b0, 0x7 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+1 + SBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 3 ; Ch1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+1 + LBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 1 + AND SCRATCH.b0, SCRATCH.b0, 0x7 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+1 + SBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 3 + .else + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1 + LBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 1 + AND SCRATCH.b0, SCRATCH.b0, 0x7 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+1 + SBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 3 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+1 + LBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 1 + AND SCRATCH.b0, SCRATCH.b0, 0x7 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+1 + SBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 3 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+1 + LBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 1 + AND SCRATCH.b0, SCRATCH.b0, 0x7 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+1 + SBCO &SCRATCH, ICSS_CFG, SCRATCH1.w0, 3 + .endif +FN_SEND_2_2_WAIT_TILL_TX_CH0_BUSY: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_TXCFG + LBCO &R2.b3, ICSS_CFG, SCRATCH1.w0, 1 + ; Determines when you can assert tx go to issue a new TX frame + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;waiting to complete tx fifo for ch0 in RTU + QBBS FN_SEND_2_2_WAIT_TILL_TX_CH0_BUSY, R2.b3, 5 ; Ch0 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;waiting to complete tx fifo for ch1 in PRU + QBBS FN_SEND_2_2_WAIT_TILL_TX_CH0_BUSY, R2.b3, 6 ; Ch1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;waiting to complete tx fifo for ch2 in TXPRU + QBBS FN_SEND_2_2_WAIT_TILL_TX_CH0_BUSY, R2.b3, 7 ; Ch2 + .elseif $isdefed("ENABLE_MULTI_CHANNEL") + AND R2.b3, R2.b3, 0xE0 + QBNE FN_SEND_2_2_WAIT_TILL_TX_CH0_BUSY, R2.b3, 0 + .else + QBBC ENDAT_SKIP18_CH0, ENDAT_ENABLE_CHx, 0 + QBBS FN_SEND_2_2_WAIT_TILL_TX_CH0_BUSY, R2.b3, 5 ; Ch0 +ENDAT_SKIP18_CH0: + QBBC ENDAT_SKIP18_CH1, ENDAT_ENABLE_CHx, 1 + QBBS FN_SEND_2_2_WAIT_TILL_TX_CH0_BUSY, R2.b3, 6 ; Ch1 +ENDAT_SKIP18_CH1: + QBBC ENDAT_SKIP18_CH2, ENDAT_ENABLE_CHx, 2 + QBBS FN_SEND_2_2_WAIT_TILL_TX_CH0_BUSY, R2.b3, 7 ; Ch2 +ENDAT_SKIP18_CH2: + .endif + + .if $isdefed("ENABLE_MULTI_CHANNEL") + SET R31, ENDAT_TX_GLOBAL_GO + .else + SET R31, ENDAT_TX_CHANNEL_GO + .endif + + ; Check whether last bit is sent out + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") +;waiting for Tx fifo complete +WB_RTU_17: + AND R28.b0, R31.b0, 0x1C + QBNE WB_RTU_17, R28.b0, 0 +;waiting for Rx start first time +W_RX_RTU_CH0: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0 + LBCO &R28, ICSS_CFG, SCRATCH1.w0, 4 + QBBS W_RX_RTU_CH0, R28, 28 + ;RT claculation + M_CALC_RECOV_TIME_CH0 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") +;waiting for Tx fifo complete +WB_PRU_17: + AND R28.b0, R31.b1, 0x1C + QBNE WB_PRU_17, R28.b0, 0 +;waiting for Rx start first time +W_RX_PRU_CH1: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0 + LBCO &R28, ICSS_CFG, SCRATCH1.w0, 4 + QBBS W_RX_PRU_CH1, R28, 28 + ;RT Calculation + M_CALC_RECOV_TIME_CH1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") +;waiting for Tx fifo complete +WB_TXPRU_17: + AND R28.b0, R31.b2, 0x1C + QBNE WB_TXPRU_17, R28.b0, 0 +;waiting for Rx start first time +W_RX_TXPRU_CH2: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0 + LBCO &R28, ICSS_CFG, SCRATCH1.w0, 4 + QBBS W_RX_TXPRU_CH2, R28, 28 + ;RT Calculation + M_CALC_RECOV_TIME_CH2 + .elseif $isdefed("ENABLE_MULTI_CHANNEL") + ;waiting for Tx fifo complete + ZERO &R28, 4 +WB_TX_FIFO_COM_MULTI_CH: + QBBC ENDAT_SKIP100_MULTI_CH0, ENDAT_ENABLE_CHx_IN_USE, 0 + AND R28.b0, R31.b0, 0x1C +ENDAT_SKIP100_MULTI_CH0: + QBBC ENDAT_SKIP100_MULTI_CH1, ENDAT_ENABLE_CHx_IN_USE, 1 + AND R28.b1, R31.b1, 0x1C +ENDAT_SKIP100_MULTI_CH1: + QBBC ENDAT_SKIP100_MULTI_CH2, ENDAT_ENABLE_CHx_IN_USE, 2 + AND R28.b2, R31.b2, 0x1C +ENDAT_SKIP100_MULTI_CH2: + QBNE WB_TX_FIFO_COM_MULTI_CH, R28, 0 + + ; waiting for TX complete for all three channels + ZERO &R28, 4 +WB_TX_COM_MULTI_CH: + QBBC ENDAT_SKIP101_MULTI_CH0, ENDAT_ENABLE_CHx_IN_USE, 0 + AND R28.b0, R31.b0, 0x20 +ENDAT_SKIP101_MULTI_CH0: + QBBC ENDAT_SKIP101_MULTI_CH1, ENDAT_ENABLE_CHx_IN_USE, 1 + AND R28.b1, R31.b1, 0x20 +ENDAT_SKIP101_MULTI_CH1: + QBBC ENDAT_SKIP101_MULTI_CH2, ENDAT_ENABLE_CHx_IN_USE, 2 + AND R28.b2, R31.b2, 0x20 +ENDAT_SKIP101_MULTI_CH2: + QBNE WB_TX_COM_MULTI_CH, R28, 0 + M_CALC_RECOV_TIME_MULTI_CH + .else + QBBC ENDAT_SKIP19_CH0, ENDAT_ENABLE_CHx, 0 +;waiting for Tx fifo complete +WB_TX_FIFO_COM_CH0: + AND R28.b0, R31.b0, 0x1C + QBNE WB_TX_FIFO_COM_CH0, R28.b0, 0 +;waiting for Rx start first time +W_RX_LOW_CH0: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0 + LBCO &R28, ICSS_CFG, SCRATCH1.w0, 4 + QBBS W_RX_LOW_CH0, R28, 28 + M_CALC_RECOV_TIME_CH0 + +ENDAT_SKIP19_CH0: + QBBC ENDAT_SKIP19_CH1, ENDAT_ENABLE_CHx, 1 +;waiting for Tx fifo complete +WB_TX_FIFO_COM_CH1: + AND R28.b0, R31.b1, 0x1C + QBNE WB_TX_FIFO_COM_CH1, R28.b0, 0 +;waiting for Rx start first time +W_RX_LOW_CH1: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0 + LBCO &R28, ICSS_CFG, SCRATCH1.w0, 4 + QBBS W_RX_LOW_CH1, R28, 28 + M_CALC_RECOV_TIME_CH1 + +ENDAT_SKIP19_CH1: + QBBC ENDAT_SKIP19_CH2, ENDAT_ENABLE_CHx, 2 +;waiting for Tx fifo complete +WB_TX_FIFO_COM_CH2: + AND R28.b0, R31.b2, 0x1C + QBNE WB_TX_FIFO_COM_CH2, R28.b0, 0 +;waiting for Rx start first time +W_RX_LOW_CH2: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0 + LBCO &R28, ICSS_CFG, SCRATCH1.w0, 4 + QBBS W_RX_LOW_CH2, R28, 28 + M_CALC_RECOV_TIME_CH2 +ENDAT_SKIP19_CH2: + .endif + RET2 + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; Function to send EnDat2.2 command supplement +; R1.b0: address/MRS code/port address +; R1.w1:16-bit parameter data +; R1.b3: Block address - used by FN_SEND_2_2 +; R0.b3: Length of block address in bytes - used by FN_SEND_2_2. Force this to 1 from firmware now +; Section 2.4.2 EnDat spec: Encoder to send position value and selection of memory area +; or block address.Command supplement in this case 8-bit MRS code, 16-bit parameter(zero), +; 8-bit block address +; Uses: R30 +; Invokes: FN_SEND_2_2 - TODO: check whether both can be merged +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +FN_SEND_ENDAT22_COMMAND_SUPPLEMENT: + ; Send zero pad bits+start_bit+MRS_code+16bit Data (Low/zero)+8bit(block address) + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;set clock high after txfor ch0 in RTU + LDI R30.w2, (ENDAT_TX_CLK_MODE_STOPHIGH_AFTER_TX | ENDAT_TX_CH0_SEL) + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;set clock high after tx for ch1 in PRU + LDI R30.w2, (ENDAT_TX_CLK_MODE_STOPHIGH_AFTER_TX | ENDAT_TX_CH1_SEL) + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;set clock high after tx for ch1 in TXPRU + LDI R30.w2, (ENDAT_TX_CLK_MODE_STOPHIGH_AFTER_TX | ENDAT_TX_CH2_SEL) + .elseif $isdefed("ENABLE_MULTI_CHANNEL") + LDI R30.w2, (ENDAT_TX_CLK_MODE_STOPHIGH_AFTER_TX | ENDAT_TX_CH0_SEL) + LOOP FN_SEND_ENDAT22_MULTI_CHANNEL, 3 ; TODO: assumption all 3 channels are enabled in multi channel mode + .else + QBBC ENDAT_SKIP24_CH0, ENDAT_ENABLE_CHx, 0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_STOPHIGH_AFTER_TX | ENDAT_TX_CH0_SEL) +ENDAT_SKIP24_CH0: + QBBC ENDAT_SKIP24_CH1, ENDAT_ENABLE_CHx, 1 + LDI R30.w2, (ENDAT_TX_CLK_MODE_STOPHIGH_AFTER_TX | ENDAT_TX_CH1_SEL) +ENDAT_SKIP24_CH1: + QBBC ENDAT_SKIP24_CH2, ENDAT_ENABLE_CHx, 2 + LDI R30.w2, (ENDAT_TX_CLK_MODE_STOPHIGH_AFTER_TX | ENDAT_TX_CH2_SEL) +ENDAT_SKIP24_CH2: + .endif + + + LDI R30.b0, 1 ; Simplicity 7 clocks till start bit - can optimize later + MOV R30.b0, R1.b0 + MOV R30.b0, R1.b1 ; Data15..8 Low + MOV R30.b0, R1.b2 ; Data7..0 Low + .if $isdefed("ENABLE_MULTI_CHANNEL") + ADD R30.b2, R30.b2, 1 +FN_SEND_ENDAT22_MULTI_CHANNEL: + .endif;ENABLE_MULTI_CHANNEL + + ; FIFO is full at this point, now monitor the FIFO level and send the remaining bytes + CALL2 FN_SEND_2_2 + RET + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; Function to send and receive EnDat2.1/2.2 command/response +; Inputs: +; R0.w0: Command mode(6)+9 bits +; R0.w2: Remaining 16 bits +; R1.b0: Reecive bits +; R1.b1: Transmit bits +; R1.b2: 0: EnDat2.2 otherwise: EnDat2.1 or ENDAT_CMD_SEND_POSVAL_WITH_DATA +; R1.b3: For EnDat2.2, Block address length in bytes for command supplement +; Uses: R2, R30 +; Invokes: FN_SEND, FN_RECEIVE +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +FN_SEND_RECEIVE_ENDAT: + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;set clock low or high for ch0 in RTU + QBBC FN_SEND_RECEIVE_RTU_ENDAT22, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPHIGH | ENDAT_TX_CH0_SEL) + JMP FN_SEND_START +FN_SEND_RECEIVE_RTU_ENDAT22: + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPLOW | ENDAT_TX_CH0_SEL) + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;set clock low or high for ch1 in PRU + QBBC FN_SEND_RECEIVE_PRU_ENDAT22, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPHIGH | ENDAT_TX_CH1_SEL) + JMP FN_SEND_START +FN_SEND_RECEIVE_PRU_ENDAT22: + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPLOW | ENDAT_TX_CH1_SEL) + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;set clock low or high for ch1 in TXPRU + QBBC FN_SEND_RECEIVE_TXPRU_ENDAT22, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPHIGH | ENDAT_TX_CH2_SEL) + JMP FN_SEND_START +FN_SEND_RECEIVE_TXPRU_ENDAT22: + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPLOW | ENDAT_TX_CH2_SEL) + .else ;clock set When load share mode is not used, that is single channel or multi channel using single PRU + QBBC FN_SEND_RECEIVE_ENDAT22, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 0 + QBBC ENDAT_SKIP25_CH0, ENDAT_ENABLE_CHx, 0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPHIGH | ENDAT_TX_CH0_SEL) +ENDAT_SKIP25_CH0: + QBBC ENDAT_SKIP25_CH1, ENDAT_ENABLE_CHx, 1 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPHIGH | ENDAT_TX_CH1_SEL) +ENDAT_SKIP25_CH1: + QBBC ENDAT_SKIP25_CH2, ENDAT_ENABLE_CHx, 2 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPHIGH | ENDAT_TX_CH2_SEL) +ENDAT_SKIP25_CH2: + JMP FN_SEND_START +FN_SEND_RECEIVE_ENDAT22: + QBBC ENDAT_SKIP26_CH0, ENDAT_ENABLE_CHx, 0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPLOW | ENDAT_TX_CH0_SEL) +ENDAT_SKIP26_CH0: + QBBC ENDAT_SKIP26_CH1, ENDAT_ENABLE_CHx, 1 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPLOW | ENDAT_TX_CH1_SEL) +ENDAT_SKIP26_CH1: + QBBC ENDAT_SKIP26_CH2, ENDAT_ENABLE_CHx, 2 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN_STOPLOW | ENDAT_TX_CH2_SEL) +ENDAT_SKIP26_CH2: + .endif + +FN_SEND_START: + .if $isdefed("ENABLE_MULTI_CHANNEL") + LOOP FN_SEND_RECEIVE_ENDAT_MULTI_CHANNEL, 3 + .endif + MOV R30.b0, R0.b0 + QBGE FN_SEND_TX_DONE, R1.b1, 8 + MOV R30.b0, R0.b1 + MOV R30.b0, R0.b2 + MOV R30.b0, R0.b3 +FN_SEND_TX_DONE: + .if $isdefed("ENABLE_MULTI_CHANNEL") + ; since ENABLE_RUNTIME_CH is kept enabled with all 3 channels selected for multi channel, last channel would have been selected by now + SUB R30.b2, R30.b2, 1 +FN_SEND_RECEIVE_ENDAT_MULTI_CHANNEL: + .endif + MOV R2.w1, R1.b0 + LSL R1.b0, R1.b1, 3 + CALL2 FN_SEND + + + ;set syn_bit of all connected channels for TX_GLOBAL_INIT + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0x1 ; set syn_bit of ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0x2 ;set syn_bit of ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0x4 ;set syn_bit of ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + .endif + + ZERO &R15, 4 + ZERO &R16, 4 + .if $isdefed("ENABLE_MULTI_CHANNEL") + ZERO &R19, 4 + ZERO &R20, 4 + ZERO &R23, 4 + ZERO &R24, 4 + .endif + + + ; store valid bit & rx fifo bit to be checked based on selected channel + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;store valid bit & rx fifo bit to be checked for ch0 in PRU + LDI R3.b0, 24 + LDI R3.b1, 4 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;store valid bit & rx fifo bit to be checked for ch1 in RTU + LDI R3.b0, 25 + LDI R3.b1, 4 + 8 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;store valid bit & rx fifo bit to be checked for CH2 in TXPRU + LDI R3.b0, 26 + LDI R3.b1, 4 + 16 + .else ;without loadshare mode + QBBC ENDAT_SKIP41_CH0, ENDAT_ENABLE_CHx, 0 + LDI R3.b0, 24 + LDI R3.b1, 4 +ENDAT_SKIP41_CH0: + QBBC ENDAT_SKIP41_CH1, ENDAT_ENABLE_CHx, 1 + LDI R3.b0, 25 + LDI R3.b1, 4 + 8 +ENDAT_SKIP41_CH1: + QBBC ENDAT_SKIP41_CH2, ENDAT_ENABLE_CHx, 2 + LDI R3.b0, 26 + LDI R3.b1, 4 + 16 +ENDAT_SKIP41_CH2: + .endif + LDI R27.b0, 0x1 + AND R2.b0, R1.b2, (0x3 << 3) + + QBEQ ENDAT_START_OTF, R2.b0, 0 + SUB R2.w1, R2.w1, 30 + ;RT after additional info 1 + LDI R27.b0, 0x2 + QBNE ENDAT_START_OTF, R2.b0, (0x3 << 3) + SUB R2.w1, R2.w1, 30 + ;RT after additional info 2 + LDI R27.b0, 0x4 +ENDAT_START_OTF: + ;If it is 2.1 command then skip RT calculation + QBBC ENDAT_SKIP_RT_FOR_CMD2_1, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 2 + QBBS ENDAT_RT_FOR_NSP_CMD2_2, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 0 + ;Skip RT calculation for supplement command +ENDAT_SKIP_RT_FOR_CMD2_1: + LDI R27.b0, 0 +ENDAT_RT_FOR_NSP_CMD2_2: + LDI R0.b0, 0 + .if $isdefed("ENABLE_MULTI_CHANNEL") + LDI R0.b1, 0 + LDI R0.b2, 0 + .endif + .if $isdefed("ENABLE_MULTI_CHANNEL") + M_OTF_RECEIVE R15, R16, R19, R20, R23, R24, R27.b0, 0 + .else + M_OTF_RECEIVE R15, R16, R27.b0, 0 + .endif + + QBEQ ENDAT_END_OF_RX, R2.b0, 0 + LDI R2.w1, 29 + + .if $isdefed("ENABLE_MULTI_CHANNEL") + M_OTF_RECEIVE R17, SCRATCH, R21, SCRATCH, R25, SCRATCH, R27.b0, 1 + .else + M_OTF_RECEIVE R17, SCRATCH, R27.b0, 1 + + .endif + QBNE ENDAT_END_OF_RX, R2.b0, (0x3 << 3) + + .if $isdefed("ENABLE_MULTI_CHANNEL") + M_OTF_RECEIVE R18, SCRATCH, R22, SCRATCH, R26, SCRATCH, R27.b0, 2 + .else + M_OTF_RECEIVE R18, SCRATCH, R27.b0, 2 + .endif + +ENDAT_END_OF_RX: + QBBC SKIP_FOR_ENDAT_2_2, ENDAT_CMDTYP_NO_SUPPLEMENT_REG, 0 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0 , 0 ;clear Syn_bit of ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT1, R14.b2, 0 ; check RTU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0 ;clear syn_bit of ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT1, R14.b2, 1 ; check PRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0 ;clear syn_bit of ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT1, R14.b2, 2; check TXPRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + + .else ; for without load share mode + SET R31, ENDAT_TX_GLOBAL_REINIT + .endif + +SKIP_GLOBAL_TX_REINIT1: + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ; ch0 wait to complete TX_GLOBAL_INIT action +WBRTU28: + QBBS WBRTU28, R31, 5 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;ch1 wait to complete TX_GLOBAL_INIT action +WBPRU29: + QBBS WBPRU29, R31, 13 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU");ch2 ; wait to complete TX_GLOBAL_INIT action +WBTXPRU30: + QBBS WBTXPRU30, R31, 21 + .else + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP23_CH0, ENDAT_ENABLE_CHx_IN_USE, 0 + .else + QBBC ENDAT_SKIP23_CH0, ENDAT_ENABLE_CHx, 0 + .endif +WB28: + QBBS WB28, R31, 5 +ENDAT_SKIP23_CH0: + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP23_CH1, ENDAT_ENABLE_CHx_IN_USE, 1 + .else + QBBC ENDAT_SKIP23_CH1, ENDAT_ENABLE_CHx, 1 + .endif +WB29: + QBBS WB29, R31, 13 +ENDAT_SKIP23_CH1: + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP23_CH2, ENDAT_ENABLE_CHx_IN_USE, 2 + .else + QBBC ENDAT_SKIP23_CH2, ENDAT_ENABLE_CHx, 2 + .endif +WB30: + QBBS WB30, R31, 21 + +ENDAT_SKIP23_CH2: + .endif + +SKIP_FOR_ENDAT_2_2: + + RET + + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; Args: +; FN_DELAY_CYCLES: R0 - number of cycles to delay +; Uses: R1 +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +FN_DELAY_CYCLES: + ; clear the PRU cycle counter by writing 0x0 to it + ZERO &R2, 4 + .if $isdefed("ENABLE_MULTI_MAKE_TXPRU") ; c11 is not correct for TXPRU + SBCO &R2, c28, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .else + SBCO &R2, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .endif + +DELAY_LOOP: + .if $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LBCO &R2, c28, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .else + LBCO &R2, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .endif + QBLT DELAY_LOOP, R0, R2 + + RET2 + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; EnDat power on init procedure +; Start Power on procedure to determine EnDAT/SSI interface - ENDAT 2.2 spec(D297403) - Appendix A5 +; Uses R0, R1 +; USE R14 : in synchronization part +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +FN_ENDAT_POWER_ON_INIT: + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0 ; clear syn_bit of ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all three channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT2, R14.b2, 0 ; check RTUPRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0 ; clear syn_bit of ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all three channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT2, R14.b2, 1 ;check PRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0 ; clear syn_bit of ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all three channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT2, R14.b2, 2 ; check TXPRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .else ;without load share + SET R31, ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low + .endif + +SKIP_GLOBAL_TX_REINIT2: + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0x1 ; set syn_bit ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0x2 ; set syn_bit of ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0x4 ; set syn_bit of ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + .endif + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;waiting to complete tx_globle action for ch0 in RTU +WBRTU33: + QBBS WBRTU33, R31, 5 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;waiting to complete tx_globle action for ch1 in PRU +WBPRU34: + QBBS WBPRU34, R31, 13 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;;waiting to complete tx_globle action for ch2 in TXXPRU +WBTXPRU35: + QBBS WBTXPRU35, R31, 21 + .else + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP27_CH0, ENDAT_ENABLE_CHx_IN_USE, 0 + .else + QBBC ENDAT_SKIP27_CH0, ENDAT_ENABLE_CHx, 0 + .endif +WB33: + QBBS WB33, R31, 5 +ENDAT_SKIP27_CH0: + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP27_CH1, ENDAT_ENABLE_CHx_IN_USE, 1 + .else + QBBC ENDAT_SKIP27_CH1, ENDAT_ENABLE_CHx, 1 + .endif +WB34: + QBBS WB34, R31, 13 +ENDAT_SKIP27_CH1: + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP27_CH2, ENDAT_ENABLE_CHx_IN_USE, 2 + .else + QBBC ENDAT_SKIP27_CH2, ENDAT_ENABLE_CHx, 2 + .endif +WB35: + QBBS WB35, R31, 21 +ENDAT_SKIP27_CH2: + .endif + + ; Use ICSS_CFG_PRUx_ENDAT_CH0_CFG0 to program CLK overide and do power on init sequence + ; t1:TX_CLK HIGH or LOW for at least 800ms + ; t2: 80ms < TX_CLK HIGH < 120ms + ; TX_CLK LOW > 125ns + ; t3: 380ms < TX_CLK HIGH < 420 ms + ; Poll for encoder data after above sequence + + ; Keep TX_CLK HIGH for 900ms + + LDI R0.b0, 0x60 ; Set endat_clk_out_override_en and pru_ endat_clk + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .else + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .endif + + + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_900MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ;900ms wait + + ; Keep TX_CLK LOW for > 125ns + LDI R0.b0, 0x20 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .else + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .endif + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_125NS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES ;wait 125ns + + LDI R0.b0, 0x60 ; Set endat_clk_out_override_en and pru_ endat_clk + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .else + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .endif + + ;wait 380ms + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_380MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES + + LDI R0.b0, 0 ; Disable clock override + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .else + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG0+3 + SBCO &R0.b0, ICSS_CFG, SCRATCH1.w0, 1 + .endif + + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0 ; clear syn_bit of ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit bit not clear for all channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT3, R14.b2, 0 ; check if RTUPRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0 ; clear syn_bit of ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT3, R14.b2, 1 ; check if PRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0 ;clear syn_bit for ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT3, R14.b2, 2 ; check if TXPRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .else + SET R31, ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low + .endif + +SKIP_GLOBAL_TX_REINIT3: + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0x1 ;set syn_bit for ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0x2 ; set syn_bit for ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0x4 ; set syn_bit for ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + .endif + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;waiting to complete tx_globle for ch0 in RTU +WBRTU39: + QBBS WBRTU39, R31, 5 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;waiting to complete tx_globle for ch1 in PRU +WBPRU40: + QBBS WBPRU40, R31, 13 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;;waiting to complete tx-globle for ch2 in TXXPRU +WBTXPRU41: + QBBS WBTXPRU41, R31, 21 + .else + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP28_CH0, ENDAT_ENABLE_CHx_IN_USE, 0 + .else + QBBC ENDAT_SKIP28_CH0, ENDAT_ENABLE_CHx, 0 + .endif +WB39: + QBBS WB39, R31, 5 +ENDAT_SKIP28_CH0: + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP28_CH1, ENDAT_ENABLE_CHx_IN_USE, 1 + .else + QBBC ENDAT_SKIP28_CH1, ENDAT_ENABLE_CHx, 1 + .endif +WB41: + QBBS WB41, R31, 13 +ENDAT_SKIP28_CH1: + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP28_CH2, ENDAT_ENABLE_CHx_IN_USE, 2 + .else + QBBC ENDAT_SKIP28_CH2, ENDAT_ENABLE_CHx, 2 + .endif +WB42: + QBBS WB42, R31, 21 +ENDAT_SKIP28_CH2: + .endif + + ; Start free running clock and poll for RX_VALID + ; Set continuous clock for channel0 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ; Start free running clock and poll for RX_VALID for ch0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN | ENDAT_TX_CH0_SEL) + ; Send dummy 8-bits + LDI R30.b0, 0 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;Start free running clock and poll for RX_VALID for ch1 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN | ENDAT_TX_CH1_SEL) + ; Send dummy 8-bits + LDI R30.b0, 0 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;Start free running clock and poll for RX_VALID for ch2 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN | ENDAT_TX_CH2_SEL) + ; Send dummy 8-bits + LDI R30.b0, 0 + .else + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN | ENDAT_TX_CH0_SEL) + ; Send dummy 8-bits + LDI R30.b0, 0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN | ENDAT_TX_CH1_SEL) + ; Send dummy 8-bits + LDI R30.b0, 0 + LDI R30.w2, (ENDAT_TX_CLK_MODE_FREERUN | ENDAT_TX_CH2_SEL) + ; Send dummy 8-bits + LDI R30.b0, 0 + .endif + +WAIT_TILL_TX_CH0_1_2_BUSY: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_TXCFG + LBCO &R2.b3, ICSS_CFG, SCRATCH1.w0, 1 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;waiting to complete tx fifo for ch0 in RTU + QBBS WAIT_TILL_TX_CH0_1_2_BUSY, R2.b3, 5 ; Ch0 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;waiting to complete tx fifo for ch1 in PRU + QBBS WAIT_TILL_TX_CH0_1_2_BUSY, R2.b3, 6 ; Ch1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;waiting to complete tx fifo for ch2 in TXPRU + QBBS WAIT_TILL_TX_CH0_1_2_BUSY, R2.b3, 7 ; Ch2 + .else + AND R2.b3, R2.b3, 0xE0 + QBNE WAIT_TILL_TX_CH0_1_2_BUSY, R2.b3, 0 + .endif + + .if $isdefed("ENABLE_MULTI_CHANNEL") + SET R31, ENDAT_TX_GLOBAL_GO + .else + SET R31, ENDAT_TX_CHANNEL_GO ; NOTE: Need to send at least 1-bit to use h/w clock modes + .endif + ; Poll for RX_VALID to complete Power On Sequence +; WB46: + ; QBBC WB46, R31, 24 + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;ch0 + SET R31, ENDAT_CH0_RX_CLR_VALID + QBBC SKIP_OVFG_RTU_CLR0, R31, 27 + SET R31, ENDAT_CH0_RX_CLR_OVF +SKIP_OVFG_RTU_CLR0: + CLR R30, ENDAT_CH0_RX_EN + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;ch1 + SET R31, ENDAT_CH1_RX_CLR_VALID + QBBC SKIP_OVFG_PRU_CLR1, R31, 28 + SET R31, ENDAT_CH1_RX_CLR_OVF + +SKIP_OVFG_PRU_CLR1: + CLR R30, ENDAT_CH1_RX_EN + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;ch2 + SET R31, ENDAT_CH2_RX_CLR_VALID + QBBC SKIP_OVFG_TXPRU_CLR2, R31, 29 + SET R31, ENDAT_CH2_RX_CLR_OVF +SKIP_OVFG_TXPRU_CLR2: + CLR R30, ENDAT_CH2_RX_EN + .else ;without loadshare mode + QBBC ENDAT_SKIP46_CH0, ENDAT_ENABLE_CHx, 0 + SET R31, ENDAT_CH0_RX_CLR_VALID + QBBC SKIP_OVFG_CLR0, R31, 27 + SET R31, ENDAT_CH0_RX_CLR_OVF +SKIP_OVFG_CLR0: + CLR R30, ENDAT_CH0_RX_EN +ENDAT_SKIP46_CH0: + + QBBC ENDAT_SKIP46_CH1, ENDAT_ENABLE_CHx, 1 + SET R31, ENDAT_CH1_RX_CLR_VALID + QBBC SKIP_OVFG_CLR1, R31, 28 + SET R31, ENDAT_CH1_RX_CLR_OVF +SKIP_OVFG_CLR1: + CLR R30, ENDAT_CH1_RX_EN +ENDAT_SKIP46_CH1: + + QBBC ENDAT_SKIP46_CH2, ENDAT_ENABLE_CHx, 2 + SET R31, ENDAT_CH2_RX_CLR_VALID + QBBC SKIP_OVFG_CLR2, R31, 29 + SET R31, ENDAT_CH2_RX_CLR_OVF +SKIP_OVFG_CLR2: + CLR R30, ENDAT_CH2_RX_EN +ENDAT_SKIP46_CH2: + .endif + + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0 ;clear syn_bit for ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT4, R14.b2, 0 ; check if RTU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0 ;clear syn_bit for ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT4, R14.b2, 1 ; check if PRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0 ;clear syn_bit for ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT4, R14.b2, 2 ; check if TXPRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .else ; without load share + SET R31, ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low + .endif +SKIP_GLOBAL_TX_REINIT4: + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0x1 ;set syn_bit for ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0x2 ;set syn_bit for ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0x4 ;set syn_bit for ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + .endif + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") ;waiting to complete tx in RTU +WB47RTU_A: + QBBS WB47RTU_A, R31, 5 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ;waiting to complete tx in PRU +WB47PRU_B: + QBBS WB47PRU_B, R31, 13 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ;waiting to complete tx in TXXPRU +WB47TXPRU_C: + QBBS WB47TXPRU_C, R31, 21 + .else + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP47_CH0, ENDAT_ENABLE_CHx_IN_USE, 0 + .else + QBBC ENDAT_SKIP47_CH0, ENDAT_ENABLE_CHx, 0 + .endif +WB47_A: + QBBS WB47_A, R31, 5 +ENDAT_SKIP47_CH0: + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP47_CH1, ENDAT_ENABLE_CHx_IN_USE, 1 + .else + QBBC ENDAT_SKIP47_CH1, ENDAT_ENABLE_CHx, 1 + .endif +WB47_B: + QBBS WB47_B, R31, 13 +ENDAT_SKIP47_CH1: + .if $isdefed("ENABLE_MULTI_CHANNEL") + QBBC ENDAT_SKIP47_CH2, ENDAT_ENABLE_CHx_IN_USE, 2 + .else + QBBC ENDAT_SKIP47_CH2, ENDAT_ENABLE_CHx, 2 + .endif +WB47_C: + QBBS WB47_C, R31, 21 +ENDAT_SKIP47_CH2: + .endif + + RET + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; Initialize ECAP coninuous free running timer mode +; Uses: R1 +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +FN_ECAP_INIT: + ; Disable all interrupts on ECAP interface + LDI R1.w0, 0 + SBCO &R1.w0, ICSS_ECAP, ICSS_eCAP_ECEINT, 2 + ; Clear spurious eCAP interrupt flags + LDI R1.w0, 0xFFFF + SBCO &R1.w0, ICSS_ECAP, ICSS_eCAP_ECCLR, 2 + ; Bypass prescaler and disable REGISTER load on capture event + LDI R1.w0, 0x8100 + SBCO &R1.w0, ICSS_ECAP, ICSS_eCAP_ECCTL1, 2 + ; Select Capture Mode, Continuous Mode and free run TS Counter + LDI R1.w0, 0x0086 ; bit 4 start / stop counter + SBCO &R1.w0, ICSS_ECAP, ICSS_eCAP_ECCTL2, 2 + ; Enable Counter overflow as Interrupt sources + LDI R1.w0, 0x0020 + SBCO &R1.w0, ICSS_ECAP, ICSS_eCAP_ECEINT, 2 + RET + +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; Send EnDat master clock +; Args:R0.w0, R0.w2, R1.w0 +; R0.w0: DIV for RX_CLK +; R0.w2: DIV for TX_CLK +; R1.w0: RX_EN timer +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; + +FN_SET_TX_CLK: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_RXCFG+2 + SBCO &R0.w0, ICSS_CFG, SCRATCH1.w0, 2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_TXCFG+2 + SBCO &R0.w2, ICSS_CFG, SCRATCH1.w0, 2 + ; Program rx_en_counter in ICSS_CFG_PRUx_ENDAT_CH0_CFG1[31:16] + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH0_CFG1+2 + SBCO &R1.w0, ICSS_CFG, SCRATCH1.w0, 2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH1_CFG1+2 + SBCO &R1.w0, ICSS_CFG, SCRATCH1.w0, 2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_CH2_CFG1+2 + SBCO &R1.w0, ICSS_CFG, SCRATCH1.w0, 2 + RET + + .if $isdefed("ENABLE_PROPDELAY_MESUREMENT") +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +; Estimate prop delay +; args: +; R2.b1 - clock plus for position +; R3.b0 - ENDAT_TX_CHx_SEL +; R3.b1 - ENDAT_CHx_CLK +; R3.b2 - ENDAT_CHx_SB +; R3.b3 - ENDAT_CHx_TX_REINIT +; uses: R0, R1, R2, R8, R9 +; return: R9 - prop delay +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +FN_PROP_DELAY_CALC: + ZERO &R8.w2, 6 +PROPAGATION_DELAY_CALC_LOOP: + OR R30.w2, R3.b0, ENDAT_TX_CLK_MODE_FREERUN_STOPHIGH + + ; setup registers for transfer + LDI R30.b0, ENDAT_CMD_SEND_POSITION_VALUES + + ; calc rx frame size + + ; Note: position bits are read before invoking this fn in R2.b1, thus it + ; is supposed be an arguement, but for undiscovered yet reason, R2.b1 is + ; required to be read again here (except for ROQ437) irrespective of + ; whether it is updated before fn invocation. It gets stuck at waiting + ; for rising clock edge below. + ; This fixes it by reading # position bits in prop delay fn again, thus + ; causing prop delay to again being channel gnostic to some extent. + .if $isdefed("ENABLE_MULTI_CHANNEL") + LBCO &R2.b1, PRUx_DMEM, R8.b0, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_RTU") ;load clock plus for position bit for ch0 in PRU + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") ; load clock plus for position bit for ch1 in RTU + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") ; load clock plus for position bit for CH2 in TXPRU + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 + .else + QBBC ENDAT_SKIP39_CH0, ENDAT_ENABLE_CHx, 0 + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP39_CH0: + QBBC ENDAT_SKIP39_CH1, ENDAT_ENABLE_CHx, 1 + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP39_CH1: + QBBC ENDAT_SKIP39_CH2, ENDAT_ENABLE_CHx, 2 + LBCO &R2.b1, PRUx_DMEM, ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET, 1 +ENDAT_SKIP39_CH2: + .endif + LDI R2.b2, 0 + ; rx bits = position + CRC + F1 + ADD R2.w1, R2.w1, 6 ; CRC + F1 + + ; rx frame size = rx bits * rx clk / (rx oversample * tx clk) = rx bits * (12000 * 8) / (8 * 200) = rx bits * 60 + LSL R0.w0, R2.w1, 6 + LSL R2.w1, R2.w1, 2 + SUB R2.w1, R0.w0, R2.w1 + + LDI R1.b0, (7 << 3) ; 6(Mode bits)+1 pad + LDI R1.b2, ENDAT_CMDTYP_2_1 + CALL2 FN_SEND + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_51US_OFFSET, 4;51 us (10.2T @200KHz, 0.2T to avoid boundary ambiguities) + CALL2 FN_DELAY_CYCLES + + + ; wait for rising clock edge +ENDAT_TD_RISING_CLOCK: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ENDAT_TXCFG + LBCO &R0.w0, ICSS_CFG, SCRATCH1.w0, 2 + QBBC ENDAT_TD_RISING_CLOCK, R0.w0, R3.b1 + ;set pru counter to zero + ZERO &R0, 4 + .if $isdefed("ENABLE_MULTI_MAKE_TXPRU") + SBCO &R0, c28, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .else + SBCO &R0, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .endif + ; wait for start bit +WB1: + QBBC WB1, R31, R3.b2 + + + ; read pru counter at time when rx start + .if $isdefed("ENABLE_MULTI_MAKE_TXPRU") + + LBCO &R0, c28, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .else + LBCO &R0, c11, PRUx_CNTL_CYCLE_COUNT_OFFSET, 4 + .endif + ; rx_en = 0 + LDI R30.b3, 0 + + ;add counter value to register + ADD R9, R9, R0 + + ; wait for tx clk to get stopped naturally so that slave will not go to bad state (max ~ 54 * 5us < 1 ms) + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_1MS_OFFSET, 4; 1ms cycle counter + CALL2 FN_DELAY_CYCLES + + ; bring to sane state for next transfer + + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0 ;clear syn_bit for ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT5, R14.b2, 0 ; check RTU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0 ; clear syn_bit for ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT5, R14.b2, 1 ; check PRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0 ;clear syn_bit for ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + M_WAIT_FOR_ENABLED_CHANNELS ; wait till syn_bit not clear for all channels + LBCO &R14.b2, PRUx_DMEM, MASK_FOR_PRIMARY_CORE, 1 + QBBC SKIP_GLOBAL_TX_REINIT5, R14.b2, 2 ; check TXPRU is primary core + SET R31, ENDAT_TX_GLOBAL_REINIT + .else + SET R31, ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low + .endif + +SKIP_GLOBAL_TX_REINIT5: + +WB4: + QBBS WB4, R31, R3.b3 + + + LBCO &R0, PRUx_DMEM, ENDAT_CONFIG_DELAY_2MS_OFFSET, 4 + CALL2 FN_DELAY_CYCLES + .if $isdefed("ENABLE_MULTI_MAKE_RTU") + LDI R14.b0, 0x1 ; //set syn_bit of ch0 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH0_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_PRU") + LDI R14.b0, 0x2 ; //set syn_bit of ch1 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH1_CONFIG_SYN_BIT, 1 + .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU") + LDI R14.b0, 0x4 ; //set syn_bit of ch2 + SBCO &R14.b0, PRUx_DMEM, ENDAT_CH2_CONFIG_SYN_BIT, 1 + .endif + + ADD R8.w2, R8.w2, 1 + QBGT PROPAGATION_DELAY_CALC_LOOP, R8.w2, 8 + LSR R9, R9, 3 ; Average the 8 samples + + + LBCO &R27, PRUx_DMEM, ENDAT_CONFIG_DELAY_5US_OFFSET, 4 + +ENDAT_PROP_DELAY_MODULUS: + QBGT ENDAT_SKIP_PROP_DELAY_MODULUS, R9, R27 + SUB R9, R9, R27 + JMP ENDAT_PROP_DELAY_MODULUS +ENDAT_SKIP_PROP_DELAY_MODULUS: + + RET + .endif diff --git a/source/motor_control/position_sense/endat/firmware/endat_master_bin.h b/source/motor_control/position_sense/endat/firmware/endat_master_bin.h new file mode 100644 index 0000000..309a46e --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_master_bin.h @@ -0,0 +1,1273 @@ +/* + * endat_master_bin.h + * + * + * Copyright (c) 2015 - 2016, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int EnDatFirmware[]= { +0x21000300, +0x00000207, +0x00020001, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2effbb80, +0x91011805, +0x11070505, +0x51070503, +0x51000502, +0x21000d00, +0x24000105, +0x23042e9d, +0x24005480, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23023d9d, +0x91b03880, +0x230429dd, +0x24721d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23023d9d, +0x91ac3880, +0x230429dd, +0x24003880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23023d9d, +0x91ac3880, +0x230429dd, +0x24023880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23023d9d, +0x91ac3880, +0x230429dd, +0x24421d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23023d9d, +0x91ac3880, +0x230429dd, +0x241a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23023d9d, +0x0903efef, +0xc9000502, +0x8144182f, +0xc9010502, +0x8164182f, +0xc9020502, +0x8184182f, +0x91a83880, +0x230429dd, +0x244a1d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23023d9d, +0x91ac3880, +0x230429dd, +0x240a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23023d9d, +0x0903efef, +0xc9000502, +0x8145182f, +0xc9010502, +0x8165182f, +0xc9020502, +0x8185182f, +0x91ac3880, +0x230429dd, +0x24000180, +0x2403bfc0, +0x24271081, +0x23048b9d, +0xc9000504, +0x24080083, +0x240518c3, +0x91441822, +0xc9010504, +0x24090183, +0x240d19c3, +0x91641822, +0xc9020504, +0x240a0283, +0x24151ac3, +0x91841822, +0x2304969d, +0xc9000502, +0x81483889, +0xc9010502, +0x81683889, +0xc9020502, +0x81883889, +0x91905880, +0x6900e004, +0x24000280, +0x240017c0, +0x2400fa81, +0x23048b9d, +0x24000020, +0xc9000502, +0x91441800, +0xc9010502, +0x91641800, +0xc9020502, +0x91841800, +0x51000002, +0x24000100, +0x81031800, +0x91001800, +0x69000007, +0x91743a80, +0xcf02e0ff, +0x1f02e0e0, +0x81743a80, +0x24000100, +0x81021800, +0x91021800, +0xcf0000ff, +0xc9070003, +0x2300ca9d, +0x2100c500, +0x910c7880, +0x23023d9d, +0xd1004103, +0x91143881, +0x2302319d, +0xc9000510, +0x10000004, +0x91413824, +0xd1000403, +0x01012424, +0x2eff838f, +0x51000203, +0xd1010403, +0x01014444, +0x2eff8191, +0x69180203, +0xd1020403, +0x01016464, +0x2eff8192, +0x8130f88f, +0x81403884, +0xc9010510, +0x10000004, +0x91613824, +0xd1000403, +0x01012424, +0x2eff838f, +0x51000203, +0xd1010403, +0x01014444, +0x2eff8191, +0x69180203, +0xd1020403, +0x01016464, +0x2eff8192, +0x8150f88f, +0x81603884, +0xc9020510, +0x10000004, +0x91813824, +0xd1000403, +0x01012424, +0x2eff838f, +0x51000203, +0xd1010403, +0x01014444, +0x2eff8191, +0x69180203, +0xd1020403, +0x01016464, +0x2eff8192, +0x8170f88f, +0x81803884, +0x24000083, +0x81021803, +0x91001804, +0x570004bd, +0x21008b00, +0x910c7880, +0xc9000502, +0x240010de, +0xc9010502, +0x240011de, +0xc9020502, +0x240012de, +0x1000001e, +0x100101a2, +0x09032101, +0x2301b3dd, +0x240000cf, +0x2400008f, +0x240000d0, +0x24000090, +0xc9000503, +0x24001803, +0x24000423, +0xc9010503, +0x24001903, +0x24000c23, +0xc9020503, +0x24001a03, +0x24001423, +0x2400011b, +0xc9024102, +0xd1004102, +0x2400001b, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2100f600, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901f0f0, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21010500, +0x16004363, +0x1301f0f0, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21011500, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x21013c00, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21011f00, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901efef, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21013000, +0x1301efef, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21013b00, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x51001b2c, +0xc9001b2b, +0xc900050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0xc901050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0xc902050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c2b8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c8389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d000000, +0x21017700, +0x1f000000, +0xc9000502, +0x1d007e7e, +0xc9010502, +0x1d017e7e, +0xc9020502, +0x1d027e7e, +0xc900050a, +0x91403884, +0xc900e005, +0x1f000404, +0x8130788f, +0x81403884, +0x21018700, +0x1d000404, +0x01012424, +0x81403884, +0xc901050a, +0x91603884, +0xc900e005, +0x1f000404, +0x8150788f, +0x81603884, +0x21019100, +0x1d000404, +0x01012424, +0x81603884, +0xc902050a, +0x91803884, +0xc900e005, +0x1f000404, +0x8170788f, +0x81803884, +0x21019b00, +0x1d000404, +0x01012424, +0x81803884, +0x24010e8d, +0x908d0480, +0x0b028080, +0x30800002, +0x10e0e0e0, +0xc9000502, +0x1f007e7e, +0xc9010502, +0x1f017e7e, +0xc9020502, +0x1f027e7e, +0x91021800, +0xd707002e, +0x1f13ffff, +0xc9000503, +0x1d007e7e, +0xd105ff00, +0xc9010503, +0x1d017e7e, +0xd10dff00, +0xc9020503, +0x1d027e7e, +0xd115ff00, +0x209d0000, +0xc900050b, +0x2401098d, +0x908d0402, +0x11070202, +0x12010202, +0x2401098d, +0x808d0402, +0x914618c4, +0x04c4a284, +0x24010a8d, +0x808d0484, +0xc901050b, +0x2401118d, +0x908d0402, +0x11070202, +0x12010202, +0x2401118d, +0x808d0402, +0x916618c4, +0x04c4a284, +0x2401128d, +0x808d0484, +0xc902050b, +0x2401198d, +0x908d0402, +0x11070202, +0x12010202, +0x2401198d, +0x808d0402, +0x918618c4, +0x04c4a284, +0x24011a8d, +0x808d0484, +0x2401048d, +0x908d0462, +0xc9000502, +0xd70562fd, +0xc9010502, +0xd70662fb, +0xc9020502, +0xd70762f9, +0x1f12ffff, +0x20dd0000, +0x2eff8184, +0x2401098d, +0x908d0404, +0x11070404, +0x2401098d, +0x808d2404, +0x2401118d, +0x908d0404, +0x11070404, +0x2401118d, +0x808d2404, +0x2401198d, +0x908d0404, +0x11070404, +0x2401198d, +0x808d2404, +0x2401048d, +0x908d0462, +0xc9000502, +0xd70562fd, +0xc9010502, +0xd70662fb, +0xc9020502, +0xd70762f9, +0x1f12ffff, +0xc9000513, +0x111c1f1c, +0x6f001cff, +0x2401088d, +0x908d249c, +0xd71cfcfe, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0xc9010513, +0x111c3f1c, +0x6f001cff, +0x2401108d, +0x908d249c, +0xd71cfcfe, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0xc9020513, +0x111c5f1c, +0x6f001cff, +0x2401188d, +0x908d249c, +0xd71cfcfe, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c2b8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c8389b, +0x20dd0000, +0xc9000502, +0x240018de, +0xc9010502, +0x240019de, +0xc9020502, +0x24001ade, +0x2400011e, +0x1001011e, +0x1021211e, +0x1041411e, +0x2301dedd, +0x209d0000, +0xc9004108, +0xc9000502, +0x240008de, +0xc9010502, +0x240009de, +0xc9020502, +0x24000ade, +0x21024b00, +0xc9000502, +0x240000de, +0xc9010502, +0x240001de, +0xc9020502, +0x240002de, +0x1000001e, +0x71082104, +0x1020201e, +0x1040401e, +0x1060601e, +0x100101a2, +0x09032101, +0x2301b3dd, +0x2eff818f, +0x2eff8190, +0xc9000503, +0x24001803, +0x24000423, +0xc9010503, +0x24001903, +0x24000c23, +0xc9020503, +0x24001a03, +0x24001423, +0x2400011b, +0x11184102, +0x51000206, +0x051ea2a2, +0x2400021b, +0x69180203, +0x051ea2a2, +0x2400041b, +0xc9024102, +0xd1004102, +0x2400001b, +0x24000000, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21027a00, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901f0f0, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21028900, +0x16004363, +0x1301f0f0, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21029900, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x2102c000, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102a300, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901efef, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2102b400, +0x1301efef, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2102bf00, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x51001b2c, +0xc9001b2b, +0xc900050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0xc901050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0xc902050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c2b8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c8389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d000000, +0x2102fb00, +0x1f000000, +0x53000225, +0x24001da2, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901f1f1, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21030d00, +0x16004363, +0x1301f1f1, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901e4e4, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21031c00, +0x16004363, +0x1301e4e4, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21032c00, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x21035300, +0x3062000e, +0x0901f1f1, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21033600, +0x16004363, +0x1301f1f1, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901f1f1, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21034700, +0x1301f1f1, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21035200, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x51001b2c, +0xc9011b2b, +0xc900050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0xc901050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0xc902050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c2b8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c8389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d010000, +0x21038e00, +0x1f010000, +0x69180292, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901f2f2, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21039f00, +0x16004363, +0x1301f2f2, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901e4e4, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2103ae00, +0x16004363, +0x1301e4e4, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2103be00, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x2103e500, +0x3062000e, +0x0901f2f2, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2103c800, +0x16004363, +0x1301f2f2, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901f2f2, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2103d900, +0x1301f2f2, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2103e400, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x51001b2c, +0xc9021b2b, +0xc900050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0xc901050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0xc902050e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c2b8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c8389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d020000, +0x21042000, +0x1f020000, +0xc9004108, +0x1f13ffff, +0xc9000502, +0xd105ff00, +0xc9010502, +0xd10dff00, +0xc9020502, +0xd115ff00, +0x209d0000, +0x2eff8182, +0x810c2b82, +0x910c2b82, +0x4ee2e0ff, +0x20dd0000, +0x1f13ffff, +0xc9000502, +0xd105ff00, +0xc9010502, +0xd10dff00, +0xc9020502, +0xd115ff00, +0x24006000, +0x24010b8d, +0x808d0400, +0x2401138d, +0x808d0400, +0x24011b8d, +0x808d0400, +0x91b83880, +0x230429dd, +0x24002000, +0x24010b8d, +0x808d0400, +0x2401138d, +0x808d0400, +0x24011b8d, +0x808d0400, +0x91983880, +0x230429dd, +0x24006000, +0x24010b8d, +0x808d0400, +0x2401138d, +0x808d0400, +0x24011b8d, +0x808d0400, +0x91b43880, +0x230429dd, +0x24000000, +0x24010b8d, +0x808d0400, +0x2401138d, +0x808d0400, +0x24011b8d, +0x808d0400, +0x1f13ffff, +0xc9000502, +0xd105ff00, +0xc9010502, +0xd10dff00, +0xc9020502, +0xd115ff00, +0x240010de, +0x2400001e, +0x240011de, +0x2400001e, +0x240012de, +0x2400001e, +0x2401048d, +0x908d0462, +0x11e06262, +0x6f0062fd, +0x1f12ffff, +0xc9000505, +0x1f18ffff, +0xc91bff02, +0x1f1bffff, +0x1d18fefe, +0xc9010505, +0x1f19ffff, +0xc91cff02, +0x1f1cffff, +0x1d19fefe, +0xc9020505, +0x1f1affff, +0xc91dff02, +0x1f1dffff, +0x1d1afefe, +0x1f13ffff, +0xc9000502, +0xd105ff00, +0xc9010502, +0xd10dff00, +0xc9020502, +0xd115ff00, +0x209d0000, +0x24000081, +0x812c0381, +0x24ffff81, +0x81300381, +0x24810081, +0x81280381, +0x24008681, +0x812a0381, +0x24002081, +0x812c0381, +0x209d0000, +0x2401028d, +0x808d0480, +0x2401068d, +0x808d04c0, +0x24010e8d, +0x808d0481, +0x2401168d, +0x808d0481, +0x24011e8d, +0x808d0481, +0x209d0000, +0x2eff82c8, +0x130803de, +0x24000e1e, +0xc9000502, +0x91441822, +0xc9010502, +0x91641822, +0xc9020502, +0x91841822, +0x24000042, +0x0106a2a2, +0x0906a280, +0x0902a2a2, +0x04a280a2, +0x24003801, +0x24000141, +0x2301b3dd, +0x91a03880, +0x230429dd, +0x2401048d, +0x908d0480, +0xce2380fe, +0x2eff8180, +0x810c2b80, +0xc843ff00, +0x910c2b80, +0x2400007e, +0x00e0e9e9, +0x91a43880, +0x230429dd, +0x1f13ffff, +0xd063ff00, +0x91a83880, +0x230429dd, +0x0101c8c8, +0x6708c8de, +0x0b03e9e9, +0x919c389b, +0x60fbe903, +0x04fbe9e9, +0x2104bc00, +0x209d0000 }; diff --git a/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd b/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd new file mode 100644 index 0000000..6685c86 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd @@ -0,0 +1,3 @@ +-b +-map=endat_master_hex.map +SECTIONS {.text} diff --git a/source/motor_control/position_sense/endat/firmware/endat_master_multi_PRU_bin.h b/source/motor_control/position_sense/endat/firmware/endat_master_multi_PRU_bin.h new file mode 100644 index 0000000..36c28b6 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_master_multi_PRU_bin.h @@ -0,0 +1,1073 @@ +/* + * endat_master_multi_PRU_bin.h + * + * + * Copyright (c) 2015 - 2016, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int EnDatFirmwareMultiMakePRU[]= { +0x21000300, +0x00000207, +0x00020001, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2effbb80, +0x91011805, +0x11070505, +0x51070503, +0x51000502, +0x21000d00, +0x24000105, +0x23034a9d, +0x24005480, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91b03880, +0x230345dd, +0x24721d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x24003880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x24023880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x24421d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x241a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x0903efef, +0x8164182f, +0x91a83880, +0x230345dd, +0x244a1d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x240a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x0903efef, +0x8165182f, +0x2400020e, +0x81be180e, +0x91ac3880, +0x230345dd, +0x24000180, +0x2403bfc0, +0x24271081, +0x2400000e, +0x81be180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9014e02, +0x2303b49d, +0x2400020e, +0x81be180e, +0x24090183, +0x240d19c3, +0x91641822, +0x2303bf9d, +0x81683889, +0x91905880, +0x6900e004, +0x24000280, +0x240017c0, +0x2400fa81, +0x2400000e, +0x81be180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9014e02, +0x2303b49d, +0x24000020, +0x91641800, +0x51000002, +0x24000100, +0x81071800, +0x91041800, +0x69000007, +0x91743a80, +0xcf02e0ff, +0x1f02e0e0, +0x81743a80, +0x24000100, +0x81061800, +0x91061800, +0xcf0000ff, +0xc9070002, +0x2100ae00, +0x91187880, +0x2301b29d, +0xd1004103, +0x91203881, +0x2301ab9d, +0x10000004, +0x91613824, +0xd1000403, +0x01012424, +0x2eff838f, +0x51000203, +0xd1010403, +0x01014444, +0x2eff8191, +0x69180203, +0xd1020403, +0x01016464, +0x2eff8192, +0x8150f88f, +0x81603884, +0x24000083, +0x81061803, +0x91041804, +0x570004df, +0x21009600, +0x910c7880, +0xc9000502, +0x240010de, +0xc9010502, +0x240011de, +0xc9020502, +0x240012de, +0x1000001e, +0x100101a2, +0x09032101, +0x23017fdd, +0x240000cf, +0x2400008f, +0x240000d0, +0x24000090, +0xc9000503, +0x24001803, +0x24000423, +0xc9010503, +0x24001903, +0x24000c23, +0xc9020503, +0x24001a03, +0x24001423, +0x2400011b, +0xc9024102, +0xd1004102, +0x2400001b, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2100df00, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901f0f0, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2100ee00, +0x16004363, +0x1301f0f0, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2100fe00, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x21012500, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21010800, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901efef, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21011900, +0x1301efef, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21012400, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9001b0e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d000000, +0x21014300, +0x1f000000, +0xc9000502, +0x1d007e7e, +0xc9010502, +0x1d017e7e, +0xc9020502, +0x1d027e7e, +0xc900050a, +0x91403884, +0xc900e005, +0x1f000404, +0x8130788f, +0x81403884, +0x21015300, +0x1d000404, +0x01012424, +0x81403884, +0xc901050a, +0x91603884, +0xc900e005, +0x1f000404, +0x8150788f, +0x81603884, +0x21015d00, +0x1d000404, +0x01012424, +0x81603884, +0xc902050a, +0x91803884, +0xc900e005, +0x1f000404, +0x8170788f, +0x81803884, +0x21016700, +0x1d000404, +0x01012424, +0x81803884, +0x24010e8d, +0x908d0480, +0x0b028080, +0x30800002, +0x10e0e0e0, +0xc9000502, +0x1f007e7e, +0xc9010502, +0x1f017e7e, +0xc9020502, +0x1f027e7e, +0x91021800, +0xd707004b, +0x1f13ffff, +0xc9000503, +0x1d007e7e, +0xd105ff00, +0xc9010503, +0x1d017e7e, +0xd10dff00, +0xc9020503, +0x1d027e7e, +0xd115ff00, +0x209d0000, +0x2401118d, +0x908d0402, +0x11070202, +0x12010202, +0x2401118d, +0x808d0402, +0x916618c4, +0x04c4a284, +0x2401128d, +0x808d0484, +0x2401048d, +0x908d0462, +0xd70662fe, +0x1f12ffff, +0x20dd0000, +0x2eff8184, +0x2401118d, +0x908d0404, +0x11070404, +0x2401118d, +0x808d2404, +0x2401048d, +0x908d0462, +0xd70662fe, +0x1f12ffff, +0x111c3f1c, +0x6f001cff, +0x2401108d, +0x908d249c, +0xd71cfcfe, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0x20dd0000, +0x240019de, +0x2400011e, +0x1001011e, +0x1021211e, +0x1041411e, +0x23018edd, +0x209d0000, +0xc9004103, +0x240009de, +0x2101b600, +0x240001de, +0x1000001e, +0x71082104, +0x1020201e, +0x1040401e, +0x1060601e, +0x100101a2, +0x09032101, +0x23017fdd, +0x2400020e, +0x81be180e, +0x2eff818f, +0x2eff8190, +0x24001903, +0x24000c23, +0x2400011b, +0x11184102, +0x51000206, +0x051ea2a2, +0x2400021b, +0x69180203, +0x051ea2a2, +0x2400041b, +0xc9024102, +0xd1004102, +0x2400001b, +0x24000000, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2101e000, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901f0f0, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2101ef00, +0x16004363, +0x1301f0f0, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2101ff00, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x21022600, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21020900, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901efef, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21021a00, +0x1301efef, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21022500, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9001b0e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d000000, +0x21024400, +0x1f000000, +0x510002eb, +0x24001da2, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901f1f1, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21025600, +0x16004363, +0x1301f1f1, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901e4e4, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21026500, +0x16004363, +0x1301e4e4, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21027500, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x21029c00, +0x3062000e, +0x0901f1f1, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21027f00, +0x16004363, +0x1301f1f1, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901f1f1, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21029000, +0x1301f1f1, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21029b00, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9011b0e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d010000, +0x2102ba00, +0x1f010000, +0x69180275, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901f2f2, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102cb00, +0x16004363, +0x1301f2f2, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901e4e4, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102da00, +0x16004363, +0x1301e4e4, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2102ea00, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x21031100, +0x3062000e, +0x0901f2f2, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102f400, +0x16004363, +0x1301f2f2, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901f2f2, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21030500, +0x1301f2f2, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21031000, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9021b0e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf099bfe, +0x810c2b8e, +0x2401108d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c4389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d020000, +0x21032f00, +0x1f020000, +0xc9004115, +0x2400000e, +0x81be180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9014e02, +0x1f13ffff, +0xd10dff00, +0x209d0000, +0x2eff8182, +0x810c2b82, +0x910c2b82, +0x4ee2e0ff, +0x20dd0000, +0x2400000e, +0x81be180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9014e02, +0x1f13ffff, +0x2400020e, +0x81be180e, +0xd10dff00, +0x24006000, +0x2401138d, +0x808d0400, +0x91b83880, +0x230345dd, +0x24002000, +0x2401138d, +0x808d0400, +0x91983880, +0x230345dd, +0x24006000, +0x2401138d, +0x808d0400, +0x91b43880, +0x230345dd, +0x24000000, +0x2401138d, +0x808d0400, +0x2400000e, +0x81be180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9014e02, +0x1f13ffff, +0x2400020e, +0x81be180e, +0xd10dff00, +0x240011de, +0x2400001e, +0x2401048d, +0x908d0462, +0xd70662fe, +0x1f12ffff, +0x1f19ffff, +0xc91cff02, +0x1f1cffff, +0x1d19fefe, +0x2400000e, +0x81be180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9014e02, +0x1f13ffff, +0x2400020e, +0x81be180e, +0xd10dff00, +0x209d0000, +0x24000081, +0x812c0381, +0x24ffff81, +0x81300381, +0x24810081, +0x81280381, +0x24008681, +0x812a0381, +0x24002081, +0x812c0381, +0x209d0000, +0x2401028d, +0x808d0480, +0x2401068d, +0x808d04c0, +0x24010e8d, +0x808d0481, +0x2401168d, +0x808d0481, +0x24011e8d, +0x808d0481, +0x209d0000, +0x2eff82c8, +0x130803de, +0x24000e1e, +0x91641822, +0x24000042, +0x0106a2a2, +0x0906a280, +0x0902a2a2, +0x04a280a2, +0x24003801, +0x24000141, +0x23017fdd, +0x91a03880, +0x230345dd, +0x2401048d, +0x908d0480, +0xce2380fe, +0x2eff8180, +0x810c2b80, +0xc843ff00, +0x910c2b80, +0x2400007e, +0x00e0e9e9, +0x91a43880, +0x230345dd, +0x2400000e, +0x81be180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9014e02, +0x1f13ffff, +0xd063ff00, +0x91a83880, +0x230345dd, +0x2400020e, +0x81be180e, +0x0101c8c8, +0x6708c8cf, +0x0b03e9e9, +0x919c389b, +0x60fbe903, +0x04fbe9e9, +0x2103f400, +0x209d0000 }; diff --git a/source/motor_control/position_sense/endat/firmware/endat_master_multi_RTU_bin.h b/source/motor_control/position_sense/endat/firmware/endat_master_multi_RTU_bin.h new file mode 100644 index 0000000..fb2868c --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_master_multi_RTU_bin.h @@ -0,0 +1,1073 @@ +/* + * endat_master_multi_RTU_bin.h + * + * + * Copyright (c) 2015 - 2016, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int EnDatFirmwareMultiMakeRTU[]= { +0x21000300, +0x00000207, +0x00020001, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2effbb80, +0x91011805, +0x11070505, +0x51070503, +0x51000502, +0x21000d00, +0x24000105, +0x23034a9d, +0x24005480, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91b03880, +0x230345dd, +0x24721d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x24003880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x24023880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x24421d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x241a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x0903efef, +0x8144182f, +0x91a83880, +0x230345dd, +0x244a1d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x240a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x0903efef, +0x8145182f, +0x2400010e, +0x81bd180e, +0x91ac3880, +0x230345dd, +0x24000180, +0x2403bfc0, +0x24271081, +0x2400000e, +0x81bd180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9004e02, +0x2303b49d, +0x2400010e, +0x81bd180e, +0x24080083, +0x240518c3, +0x91441822, +0x2303bf9d, +0x81483889, +0x91905880, +0x6900e004, +0x24000280, +0x240017c0, +0x2400fa81, +0x2400000e, +0x81bd180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9004e02, +0x2303b49d, +0x24000020, +0x91441800, +0x51000002, +0x24000100, +0x81031800, +0x91001800, +0x69000007, +0x91743a80, +0xcf02e0ff, +0x1f02e0e0, +0x81743a80, +0x24000100, +0x81021800, +0x91021800, +0xcf0000ff, +0xc9070002, +0x2100ae00, +0x910c7880, +0x2301b29d, +0xd1004103, +0x91143881, +0x2301ab9d, +0x10000004, +0x91413824, +0xd1000403, +0x01012424, +0x2eff838f, +0x51000203, +0xd1010403, +0x01014444, +0x2eff8191, +0x69180203, +0xd1020403, +0x01016464, +0x2eff8192, +0x8130f88f, +0x81403884, +0x24000083, +0x81021803, +0x91001804, +0x570004df, +0x21009600, +0x910c7880, +0xc9000502, +0x240010de, +0xc9010502, +0x240011de, +0xc9020502, +0x240012de, +0x1000001e, +0x100101a2, +0x09032101, +0x23017fdd, +0x240000cf, +0x2400008f, +0x240000d0, +0x24000090, +0xc9000503, +0x24001803, +0x24000423, +0xc9010503, +0x24001903, +0x24000c23, +0xc9020503, +0x24001a03, +0x24001423, +0x2400011b, +0xc9024102, +0xd1004102, +0x2400001b, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2100df00, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901f0f0, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2100ee00, +0x16004363, +0x1301f0f0, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2100fe00, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x21012500, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21010800, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901efef, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21011900, +0x1301efef, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21012400, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9001b0e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d000000, +0x21014300, +0x1f000000, +0xc9000502, +0x1d007e7e, +0xc9010502, +0x1d017e7e, +0xc9020502, +0x1d027e7e, +0xc900050a, +0x91403884, +0xc900e005, +0x1f000404, +0x8130788f, +0x81403884, +0x21015300, +0x1d000404, +0x01012424, +0x81403884, +0xc901050a, +0x91603884, +0xc900e005, +0x1f000404, +0x8150788f, +0x81603884, +0x21015d00, +0x1d000404, +0x01012424, +0x81603884, +0xc902050a, +0x91803884, +0xc900e005, +0x1f000404, +0x8170788f, +0x81803884, +0x21016700, +0x1d000404, +0x01012424, +0x81803884, +0x24010e8d, +0x908d0480, +0x0b028080, +0x30800002, +0x10e0e0e0, +0xc9000502, +0x1f007e7e, +0xc9010502, +0x1f017e7e, +0xc9020502, +0x1f027e7e, +0x91021800, +0xd707004b, +0x1f13ffff, +0xc9000503, +0x1d007e7e, +0xd105ff00, +0xc9010503, +0x1d017e7e, +0xd10dff00, +0xc9020503, +0x1d027e7e, +0xd115ff00, +0x209d0000, +0x2401098d, +0x908d0402, +0x11070202, +0x12010202, +0x2401098d, +0x808d0402, +0x914618c4, +0x04c4a284, +0x24010a8d, +0x808d0484, +0x2401048d, +0x908d0462, +0xd70562fe, +0x1f12ffff, +0x20dd0000, +0x2eff8184, +0x2401098d, +0x908d0404, +0x11070404, +0x2401098d, +0x808d2404, +0x2401048d, +0x908d0462, +0xd70562fe, +0x1f12ffff, +0x111c1f1c, +0x6f001cff, +0x2401088d, +0x908d249c, +0xd71cfcfe, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0x20dd0000, +0x240018de, +0x2400011e, +0x1001011e, +0x1021211e, +0x1041411e, +0x23018edd, +0x209d0000, +0xc9004103, +0x240008de, +0x2101b600, +0x240000de, +0x1000001e, +0x71082104, +0x1020201e, +0x1040401e, +0x1060601e, +0x100101a2, +0x09032101, +0x23017fdd, +0x2400010e, +0x81bd180e, +0x2eff818f, +0x2eff8190, +0x24001803, +0x24000423, +0x2400011b, +0x11184102, +0x51000206, +0x051ea2a2, +0x2400021b, +0x69180203, +0x051ea2a2, +0x2400041b, +0xc9024102, +0xd1004102, +0x2400001b, +0x24000000, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2101e000, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901f0f0, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2101ef00, +0x16004363, +0x1301f0f0, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2101ff00, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x21022600, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21020900, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901efef, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21021a00, +0x1301efef, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21022500, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9001b0e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d000000, +0x21024400, +0x1f000000, +0x510002eb, +0x24001da2, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901f1f1, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21025600, +0x16004363, +0x1301f1f1, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901e4e4, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21026500, +0x16004363, +0x1301e4e4, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21027500, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x21029c00, +0x3062000e, +0x0901f1f1, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21027f00, +0x16004363, +0x1301f1f1, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901f1f1, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21029000, +0x1301f1f1, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21029b00, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9011b0e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d010000, +0x2102ba00, +0x1f010000, +0x69180275, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901f2f2, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102cb00, +0x16004363, +0x1301f2f2, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901e4e4, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102da00, +0x16004363, +0x1301e4e4, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2102ea00, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x21031100, +0x3062000e, +0x0901f2f2, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102f400, +0x16004363, +0x1301f2f2, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901f2f2, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21030500, +0x1301f2f2, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21031000, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9021b0e, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf089bfe, +0x810c2b8e, +0x2401088d, +0x908d249b, +0xd71cfbfe, +0x910c2b9b, +0x81c0389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d020000, +0x21032f00, +0x1f020000, +0xc9004115, +0x2400000e, +0x81bd180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9004e02, +0x1f13ffff, +0xd105ff00, +0x209d0000, +0x2eff8182, +0x810c2b82, +0x910c2b82, +0x4ee2e0ff, +0x20dd0000, +0x2400000e, +0x81bd180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9004e02, +0x1f13ffff, +0x2400010e, +0x81bd180e, +0xd105ff00, +0x24006000, +0x24010b8d, +0x808d0400, +0x91b83880, +0x230345dd, +0x24002000, +0x24010b8d, +0x808d0400, +0x91983880, +0x230345dd, +0x24006000, +0x24010b8d, +0x808d0400, +0x91b43880, +0x230345dd, +0x24000000, +0x24010b8d, +0x808d0400, +0x2400000e, +0x81bd180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9004e02, +0x1f13ffff, +0x2400010e, +0x81bd180e, +0xd105ff00, +0x240010de, +0x2400001e, +0x2401048d, +0x908d0462, +0xd70562fe, +0x1f12ffff, +0x1f18ffff, +0xc91bff02, +0x1f1bffff, +0x1d18fefe, +0x2400000e, +0x81bd180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9004e02, +0x1f13ffff, +0x2400010e, +0x81bd180e, +0xd105ff00, +0x209d0000, +0x24000081, +0x812c0381, +0x24ffff81, +0x81300381, +0x24810081, +0x81280381, +0x24008681, +0x812a0381, +0x24002081, +0x812c0381, +0x209d0000, +0x2401028d, +0x808d0480, +0x2401068d, +0x808d04c0, +0x24010e8d, +0x808d0481, +0x2401168d, +0x808d0481, +0x24011e8d, +0x808d0481, +0x209d0000, +0x2eff82c8, +0x130803de, +0x24000e1e, +0x91441822, +0x24000042, +0x0106a2a2, +0x0906a280, +0x0902a2a2, +0x04a280a2, +0x24003801, +0x24000141, +0x23017fdd, +0x91a03880, +0x230345dd, +0x2401048d, +0x908d0480, +0xce2380fe, +0x2eff8180, +0x810c2b80, +0xc843ff00, +0x910c2b80, +0x2400007e, +0x00e0e9e9, +0x91a43880, +0x230345dd, +0x2400000e, +0x81bd180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9004e02, +0x1f13ffff, +0xd063ff00, +0x91a83880, +0x230345dd, +0x2400010e, +0x81bd180e, +0x0101c8c8, +0x6708c8cf, +0x0b03e9e9, +0x919c389b, +0x60fbe903, +0x04fbe9e9, +0x2103f400, +0x209d0000 }; diff --git a/source/motor_control/position_sense/endat/firmware/endat_master_multi_TXPRU_bin.h b/source/motor_control/position_sense/endat/firmware/endat_master_multi_TXPRU_bin.h new file mode 100644 index 0000000..cd9e8ad --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_master_multi_TXPRU_bin.h @@ -0,0 +1,1073 @@ +/* + * endat_master_multi_TXPRU_bin.h + * + * + * Copyright (c) 2015 - 2016, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int EnDatFirmwareMultiMakeTXPRU[]= { +0x21000300, +0x00000207, +0x00020001, +0x91003c8e, +0x1f03eeee, +0x81003c8e, +0x2effbb80, +0x91011805, +0x11070505, +0x51070503, +0x51000502, +0x21000d00, +0x24000105, +0x23034a9d, +0x24005480, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91b03880, +0x230345dd, +0x24721d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x24003880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x24023880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x24421d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x241a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x0903efef, +0x8184182f, +0x91a83880, +0x230345dd, +0x244a1d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x91ac3880, +0x230345dd, +0x240a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x2301b29d, +0x0903efef, +0x8185182f, +0x2400040e, +0x81bf180e, +0x91ac3880, +0x230345dd, +0x24000180, +0x2403bfc0, +0x24271081, +0x2400000e, +0x81bf180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9024e02, +0x2303b49d, +0x2400040e, +0x81bf180e, +0x240a0283, +0x24151ac3, +0x91841822, +0x2303bf9d, +0x81883889, +0x91905880, +0x6900e004, +0x24000280, +0x240017c0, +0x2400fa81, +0x2400000e, +0x81bf180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9024e02, +0x2303b49d, +0x24000020, +0x91841800, +0x51000002, +0x24000100, +0x810b1800, +0x91081800, +0x69000007, +0x91743a80, +0xcf02e0ff, +0x1f02e0e0, +0x81743a80, +0x24000100, +0x810a1800, +0x910a1800, +0xcf0000ff, +0xc9070002, +0x2100ae00, +0x91247880, +0x2301b29d, +0xd1004103, +0x912c3881, +0x2301ab9d, +0x10000004, +0x91813824, +0xd1000403, +0x01012424, +0x2eff838f, +0x51000203, +0xd1010403, +0x01014444, +0x2eff8191, +0x69180203, +0xd1020403, +0x01016464, +0x2eff8192, +0x8170f88f, +0x81803884, +0x24000083, +0x810a1803, +0x91081804, +0x570004df, +0x21009600, +0x910c7880, +0xc9000502, +0x240010de, +0xc9010502, +0x240011de, +0xc9020502, +0x240012de, +0x1000001e, +0x100101a2, +0x09032101, +0x23017fdd, +0x240000cf, +0x2400008f, +0x240000d0, +0x24000090, +0xc9000503, +0x24001803, +0x24000423, +0xc9010503, +0x24001903, +0x24000c23, +0xc9020503, +0x24001a03, +0x24001423, +0x2400011b, +0xc9024102, +0xd1004102, +0x2400001b, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2100df00, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901f0f0, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2100ee00, +0x16004363, +0x1301f0f0, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2100fe00, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x21012500, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21010800, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901efef, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21011900, +0x1301efef, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21012400, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9001b0e, +0x91003c8e, +0x1f03eeee, +0x81003c8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c3c8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c3c9b, +0x81c8389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d000000, +0x21014300, +0x1f000000, +0xc9000502, +0x1d007e7e, +0xc9010502, +0x1d017e7e, +0xc9020502, +0x1d027e7e, +0xc900050a, +0x91403884, +0xc900e005, +0x1f000404, +0x8130788f, +0x81403884, +0x21015300, +0x1d000404, +0x01012424, +0x81403884, +0xc901050a, +0x91603884, +0xc900e005, +0x1f000404, +0x8150788f, +0x81603884, +0x21015d00, +0x1d000404, +0x01012424, +0x81603884, +0xc902050a, +0x91803884, +0xc900e005, +0x1f000404, +0x8170788f, +0x81803884, +0x21016700, +0x1d000404, +0x01012424, +0x81803884, +0x24010e8d, +0x908d0480, +0x0b028080, +0x30800002, +0x10e0e0e0, +0xc9000502, +0x1f007e7e, +0xc9010502, +0x1f017e7e, +0xc9020502, +0x1f027e7e, +0x91021800, +0xd707004b, +0x1f13ffff, +0xc9000503, +0x1d007e7e, +0xd105ff00, +0xc9010503, +0x1d017e7e, +0xd10dff00, +0xc9020503, +0x1d027e7e, +0xd115ff00, +0x209d0000, +0x2401198d, +0x908d0402, +0x11070202, +0x12010202, +0x2401198d, +0x808d0402, +0x918618c4, +0x04c4a284, +0x24011a8d, +0x808d0484, +0x2401048d, +0x908d0462, +0xd70762fe, +0x1f12ffff, +0x20dd0000, +0x2eff8184, +0x2401198d, +0x908d0404, +0x11070404, +0x2401198d, +0x808d2404, +0x2401048d, +0x908d0462, +0xd70762fe, +0x1f12ffff, +0x111c5f1c, +0x6f001cff, +0x2401188d, +0x908d249c, +0xd71cfcfe, +0x91003c8e, +0x1f03eeee, +0x81003c8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c3c8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c3c9b, +0x81c8389b, +0x20dd0000, +0x24001ade, +0x2400011e, +0x1001011e, +0x1021211e, +0x1041411e, +0x23018edd, +0x209d0000, +0xc9004103, +0x24000ade, +0x2101b600, +0x240002de, +0x1000001e, +0x71082104, +0x1020201e, +0x1040401e, +0x1060601e, +0x100101a2, +0x09032101, +0x23017fdd, +0x2400040e, +0x81bf180e, +0x2eff818f, +0x2eff8190, +0x24001a03, +0x24001423, +0x2400011b, +0x11184102, +0x51000206, +0x051ea2a2, +0x2400021b, +0x69180203, +0x051ea2a2, +0x2400041b, +0xc9024102, +0xd1004102, +0x2400001b, +0x24000000, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2101e000, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901f0f0, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2101ef00, +0x16004363, +0x1301f0f0, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2101ff00, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x21022600, +0x3062000e, +0x0901efef, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21020900, +0x16004363, +0x1301efef, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901efef, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21021a00, +0x1301efef, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901f0f0, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21022500, +0x1301f0f0, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9001b0e, +0x91003c8e, +0x1f03eeee, +0x81003c8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c3c8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c3c9b, +0x81c8389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d000000, +0x21024400, +0x1f000000, +0x510002eb, +0x24001da2, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901f1f1, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21025600, +0x16004363, +0x1301f1f1, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901e4e4, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21026500, +0x16004363, +0x1301e4e4, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21027500, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x21029c00, +0x3062000e, +0x0901f1f1, +0xc803ff00, +0xd023ff03, +0x10434363, +0x21027f00, +0x16004363, +0x1301f1f1, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901f1f1, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21029000, +0x1301f1f1, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21029b00, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9011b0e, +0x91003c8e, +0x1f03eeee, +0x81003c8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c3c8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c3c9b, +0x81c8389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d010000, +0x2102ba00, +0x1f010000, +0x69180275, +0x240101cc, +0x2401018c, +0x24000143, +0xc803ff00, +0x1e03ffff, +0x0505a262, +0x7120622b, +0x24002062, +0x3062000e, +0x0901f2f2, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102cb00, +0x16004363, +0x1301f2f2, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x0525a262, +0x3062000e, +0x0901e4e4, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102da00, +0x16004363, +0x1301e4e4, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x24000562, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x2102ea00, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x21031100, +0x3062000e, +0x0901f2f2, +0xc803ff00, +0xd023ff03, +0x10434363, +0x2102f400, +0x16004363, +0x1301f2f2, +0x1e03ffff, +0x106c6c43, +0x14634c6c, +0x102c2c4c, +0x14630c2c, +0x1063630c, +0x24000063, +0x0d206262, +0x19056262, +0x30620009, +0x0901f2f2, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21030500, +0x1301f2f2, +0x13016363, +0x1e03ffff, +0x5105620b, +0x0d056262, +0x30620009, +0x0901e4e4, +0x09016363, +0xc803ff00, +0xd023ff02, +0x21031000, +0x1301e4e4, +0x13016363, +0x1e03ffff, +0x51001b0f, +0xc9021b0e, +0x91003c8e, +0x1f03eeee, +0x81003c8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0xcf0a9bfe, +0x810c3c8e, +0x2401188d, +0x908d249b, +0xd71cfbfe, +0x910c3c9b, +0x81c8389b, +0x24000062, +0xd1000c02, +0x1f006262, +0xd1002c02, +0x1f016262, +0xd1004c02, +0x1f026262, +0xd1006c02, +0x1f036262, +0xd1004302, +0x1f046262, +0x50636203, +0x1d020000, +0x21032f00, +0x1f020000, +0xc9004115, +0x2400000e, +0x81bf180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9024e02, +0x1f13ffff, +0xd115ff00, +0x209d0000, +0x2eff8182, +0x810c3c82, +0x910c3c82, +0x4ee2e0ff, +0x20dd0000, +0x2400000e, +0x81bf180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9024e02, +0x1f13ffff, +0x2400040e, +0x81bf180e, +0xd115ff00, +0x24006000, +0x24011b8d, +0x808d0400, +0x91b83880, +0x230345dd, +0x24002000, +0x24011b8d, +0x808d0400, +0x91983880, +0x230345dd, +0x24006000, +0x24011b8d, +0x808d0400, +0x91b43880, +0x230345dd, +0x24000000, +0x24011b8d, +0x808d0400, +0x2400000e, +0x81bf180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9024e02, +0x1f13ffff, +0x2400040e, +0x81bf180e, +0xd115ff00, +0x240012de, +0x2400001e, +0x2401048d, +0x908d0462, +0xd70762fe, +0x1f12ffff, +0x1f1affff, +0xc91dff02, +0x1f1dffff, +0x1d1afefe, +0x2400000e, +0x81bf180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9024e02, +0x1f13ffff, +0x2400040e, +0x81bf180e, +0xd115ff00, +0x209d0000, +0x24000081, +0x812c0381, +0x24ffff81, +0x81300381, +0x24810081, +0x81280381, +0x24008681, +0x812a0381, +0x24002081, +0x812c0381, +0x209d0000, +0x2401028d, +0x808d0480, +0x2401068d, +0x808d04c0, +0x24010e8d, +0x808d0481, +0x2401168d, +0x808d0481, +0x24011e8d, +0x808d0481, +0x209d0000, +0x2eff82c8, +0x130803de, +0x24000e1e, +0x91841822, +0x24000042, +0x0106a2a2, +0x0906a280, +0x0902a2a2, +0x04a280a2, +0x24003801, +0x24000141, +0x23017fdd, +0x91a03880, +0x230345dd, +0x2401048d, +0x908d0480, +0xce2380fe, +0x2eff8180, +0x810c3c80, +0xc843ff00, +0x910c3c80, +0x2400007e, +0x00e0e9e9, +0x91a43880, +0x230345dd, +0x2400000e, +0x81bf180e, +0x2400002e, +0x91bd180e, +0x9101184e, +0x104e0e0e, +0x120e2e2e, +0x91be180e, +0x9105184e, +0x104e0e0e, +0x120e2e2e, +0x91bf180e, +0x9109184e, +0x104e0e0e, +0x120e2e2e, +0x6f002ef3, +0x91bc184e, +0xc9024e02, +0x1f13ffff, +0xd063ff00, +0x91a83880, +0x230345dd, +0x2400040e, +0x81bf180e, +0x0101c8c8, +0x6708c8cf, +0x0b03e9e9, +0x919c389b, +0x60fbe903, +0x04fbe9e9, +0x2103f400, +0x209d0000 }; diff --git a/source/motor_control/position_sense/endat/firmware/endat_master_multi_bin.h b/source/motor_control/position_sense/endat/firmware/endat_master_multi_bin.h new file mode 100644 index 0000000..3174b62 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_master_multi_bin.h @@ -0,0 +1,1257 @@ +/* + * endat_master_multi_bin.h + * + * + * Copyright (c) 2015 - 2016, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int EnDatFirmwareMulti[]= { +0x21000300, +0x00000207, +0x00020001, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2effbb80, +0x24000705, +0x91011825, +0x2304239d, +0x24005480, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23015e9d, +0x91b03880, +0x23041edd, +0x24721d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23015e9d, +0x91ac3880, +0x23041edd, +0x24003880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23015e9d, +0x91ac3880, +0x23041edd, +0x24023880, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23015e9d, +0x91ac3880, +0x23041edd, +0x24421d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23015e9d, +0x91ac3880, +0x23041edd, +0x241a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23015e9d, +0x0903efef, +0x0903f3f3, +0x0903f7f7, +0xc9000502, +0x8144182f, +0xc9010502, +0x81641833, +0xc9020502, +0x81841837, +0x91a83880, +0x23041edd, +0x244a1d80, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23015e9d, +0x91ac3880, +0x23041edd, +0x240a4680, +0x240000c0, +0x24001d01, +0x24001f21, +0x24000141, +0x23015e9d, +0x0903efef, +0x0903f3f3, +0x0903f7f7, +0xc9000502, +0x8145182f, +0xc9010502, +0x81651833, +0xc9020502, +0x81851837, +0x91ac3880, +0x23041edd, +0x24000180, +0x2403bfc0, +0x24271081, +0x2304809d, +0x24080083, +0x240518c3, +0x24004408, +0x3102000c, +0x90081822, +0x51002203, +0x51ff2202, +0x23048b9d, +0x01040808, +0x80083889, +0x011c0808, +0x01010303, +0x01012323, +0x01014343, +0x01086363, +0x91905880, +0x6900e004, +0x24000280, +0x240017c0, +0x2400fa81, +0x2304809d, +0x24000000, +0x91441820, +0x51002003, +0x51ff2002, +0x13010000, +0x91641820, +0x51002003, +0x51ff2002, +0x13020000, +0x91841820, +0x51002003, +0x51ff2002, +0x13040000, +0x91011840, +0x81011800, +0x10400000, +0x50004002, +0x24000000, +0x10000025, +0x51000002, +0x24000100, +0x81031800, +0x91001800, +0x69000007, +0x91743a80, +0xcf02e0ff, +0x1f02e0e0, +0x81743a80, +0x24000100, +0x81021800, +0x91021800, +0xcf0000ff, +0xc9070002, +0x2100cc00, +0x910c7880, +0x23015e9d, +0xd1004103, +0x91143881, +0x2301559d, +0xc9000510, +0x10000004, +0x91413824, +0xd1000403, +0x01012424, +0x2eff838f, +0x51000203, +0xd1010403, +0x01014444, +0x2eff8191, +0x69180203, +0xd1020403, +0x01016464, +0x2eff8192, +0x8130f88f, +0x81403884, +0xc9010510, +0x10202004, +0x91613824, +0xd1000403, +0x01012424, +0x2eff8393, +0x51000203, +0xd1010403, +0x01014444, +0x2eff8195, +0x69180203, +0xd1020403, +0x01016464, +0x2eff8196, +0x8150f893, +0x81603884, +0xc9020510, +0x10404004, +0x91813824, +0xd1000403, +0x01012424, +0x2eff8397, +0x51000203, +0xd1010403, +0x01014444, +0x2eff8199, +0x69180203, +0xd1020403, +0x01016464, +0x2eff819a, +0x8170f897, +0x81803884, +0x24000083, +0x81021803, +0x91001804, +0x570004be, +0x21009300, +0x2eff818c, +0x31020011, +0x0908e6e6, +0x0908e7e7, +0x0908e8e8, +0x0908e9e9, +0x0908eaea, +0x0908ecec, +0xd1006602, +0x1f000c0c, +0xd1006702, +0x1f010c0c, +0xd1006802, +0x1f020c0c, +0xd1006902, +0x1f030c0c, +0xd1006a02, +0x1f040c0c, +0x20dd0000, +0xc900050b, +0x2401098d, +0x908d0402, +0x11070202, +0x12010202, +0x2401098d, +0x808d0402, +0x914618c4, +0x04c4a284, +0x24010a8d, +0x808d0484, +0xc901050b, +0x2401118d, +0x908d0402, +0x11070202, +0x12010202, +0x2401118d, +0x808d0402, +0x916618c4, +0x04c4a284, +0x2401128d, +0x808d0484, +0xc902050b, +0x2401198d, +0x908d0402, +0x11070202, +0x12010202, +0x2401198d, +0x808d0402, +0x918618c4, +0x04c4a284, +0x24011a8d, +0x808d0484, +0x2401048d, +0x908d0462, +0x11e06262, +0x6f0062fd, +0x1f14ffff, +0x20dd0000, +0x2eff8184, +0x2401098d, +0x908d0404, +0x11070404, +0x2401098d, +0x808d2404, +0x2401118d, +0x908d0404, +0x11070404, +0x2401118d, +0x808d2404, +0x2401198d, +0x908d0404, +0x11070404, +0x2401198d, +0x808d2404, +0x2401048d, +0x908d0462, +0x11e06262, +0x6f0062fd, +0x1f14ffff, +0x2eff819c, +0xc9002502, +0x111c1f1c, +0xc9012502, +0x111c3f3c, +0xc9022502, +0x111c5f5c, +0x6f00fcfa, +0x2eff819c, +0xc9002502, +0x11201f1c, +0xc9012502, +0x11203f3c, +0xc9022502, +0x11205f5c, +0x6f00fcfa, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0x10253b5b, +0x6e255bfd, +0x810c2b8e, +0x2400009c, +0xc9002508, +0xd1003c07, +0x2401088d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c0389b, +0x1f003c3c, +0xc9012508, +0xd1013c07, +0x2401108d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c4389b, +0x1f013c3c, +0xc9022508, +0xd1023c07, +0x2401188d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c8389b, +0x1f023c3c, +0x10253c1c, +0x6e251ce7, +0x20dd0000, +0x240018de, +0x31020006, +0x2400011e, +0x1001011e, +0x1021211e, +0x1041411e, +0x01015e5e, +0x23010bdd, +0x209d0000, +0xc9004108, +0xc9000502, +0x240008de, +0xc9010502, +0x240009de, +0xc9020502, +0x24000ade, +0x21016c00, +0xc9000502, +0x240000de, +0xc9010502, +0x240001de, +0xc9020502, +0x240002de, +0x31020007, +0x1000001e, +0x71082104, +0x1020201e, +0x1040401e, +0x1060601e, +0x05015e5e, +0x100101a2, +0x09032101, +0x2300e4dd, +0x2eff818f, +0x2eff8190, +0x2eff8193, +0x2eff8194, +0x2eff8197, +0x2eff8198, +0xc9000503, +0x24001803, +0x24000423, +0xc9010503, +0x24001903, +0x24000c23, +0xc9020503, +0x24001a03, +0x24001423, +0x2400011b, +0x11184102, +0x51000206, +0x051ea2a2, +0x2400021b, +0x69180203, +0x051ea2a2, +0x2400041b, +0xc9024102, +0xd1004102, +0x2400001b, +0x24000000, +0x24000020, +0x24000040, +0x240001c6, +0x24010186, +0x10e6e6e7, +0x10e6e6e8, +0x10e6e6e9, +0x10e6e6ea, +0x10257f04, +0x6e2504ff, +0x1004047f, +0x0505a262, +0x71206250, +0x24002062, +0x3062001b, +0x0901efef, +0x0901f3f3, +0x0901f7f7, +0x10257f04, +0x6e2504ff, +0xd104ff03, +0x100a0a0b, +0x2101aa00, +0x16000a0b, +0x1301efef, +0xd10cff03, +0x102a2a2b, +0x2101af00, +0x16002a2b, +0x1301f3f3, +0xd114ff03, +0x104a4a4b, +0x2101b400, +0x16004a4b, +0x1301f7f7, +0x1004047f, +0x10e9e9ea, +0x14ebe8e9, +0x10e7e7e8, +0x14ebe6e7, +0x10ebebe6, +0x0525a262, +0x3062001b, +0x0901f0f0, +0x0901f4f4, +0x0901f8f8, +0x10257f04, +0x6e2504ff, +0xd104ff03, +0x100a0a0b, +0x2101c600, +0x16000a0b, +0x1301f0f0, +0xd10cff03, +0x102a2a2b, +0x2101cb00, +0x16002a2b, +0x1301f4f4, +0xd114ff03, +0x104a4a4b, +0x2101d000, +0x16004a4b, +0x1301f8f8, +0x1004047f, +0x10e9e9ea, +0x14ebe8e9, +0x10e7e7e8, +0x14ebe6e7, +0x10ebebe6, +0x2eff818b, +0x24000562, +0x30620014, +0x0901f0f0, +0x0901f4f4, +0x0901f8f8, +0x0901ebeb, +0x10257f04, +0x6e2504ff, +0xd104ff02, +0x2101e300, +0x1301f0f0, +0x13010b0b, +0xd10cff02, +0x2101e700, +0x1301f4f4, +0x13012b2b, +0xd114ff02, +0x2101eb00, +0x1301f8f8, +0x13014b4b, +0x1004047f, +0x21023500, +0x3062001b, +0x0901efef, +0x0901f3f3, +0x0901f7f7, +0x10257f04, +0x6e2504ff, +0xd104ff03, +0x100a0a0b, +0x2101f800, +0x16000a0b, +0x1301efef, +0xd10cff03, +0x102a2a2b, +0x2101fd00, +0x16002a2b, +0x1301f3f3, +0xd114ff03, +0x104a4a4b, +0x21020200, +0x16004a4b, +0x1301f7f7, +0x1004047f, +0x10e9e9ea, +0x14ebe8e9, +0x10e7e7e8, +0x14ebe6e7, +0x10ebebe6, +0x2eff818b, +0x0d206262, +0x19056262, +0x30620014, +0x0901efef, +0x0901f3f3, +0x0901f7f7, +0x0901ebeb, +0x10257f04, +0x6e2504ff, +0xd104ff02, +0x21021600, +0x1301efef, +0x13010b0b, +0xd10cff02, +0x21021a00, +0x1301f3f3, +0x13012b2b, +0xd114ff02, +0x21021e00, +0x1301f7f7, +0x13014b4b, +0x1004047f, +0x51056216, +0x0d056262, +0x30620014, +0x0901f0f0, +0x0901f4f4, +0x0901f8f8, +0x0901ebeb, +0x10257f04, +0x6e2504ff, +0xd104ff02, +0x21022c00, +0x1301f0f0, +0x13010b0b, +0xd10cff02, +0x21023000, +0x1301f4f4, +0x13012b2b, +0xd114ff02, +0x21023400, +0x1301f8f8, +0x13014b4b, +0x1004047f, +0x51001b26, +0xc9001b25, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0x10253b5b, +0x6e255bfd, +0x810c2b8e, +0x2400009c, +0xc9002508, +0xd1003c07, +0x2401088d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c0389b, +0x1f003c3c, +0xc9012508, +0xd1013c07, +0x2401108d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c4389b, +0x1f013c3c, +0xc9022508, +0xd1023c07, +0x2401188d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c8389b, +0x1f023c3c, +0x10253c1c, +0x6e251ce7, +0x2300d1dd, +0x500b0c03, +0x1d000000, +0x21026000, +0x1f000000, +0x502b2c03, +0x1d002020, +0x21026400, +0x1f002020, +0x504b4c03, +0x1d004040, +0x21026800, +0x1f004040, +0x530002ad, +0x24001da2, +0x240001c6, +0x24010186, +0x10e6e6e7, +0x10e6e6e8, +0x10e6e6e9, +0x10e6e6ea, +0x10257f04, +0x6e2504ff, +0x1004047f, +0x0505a262, +0x71206250, +0x24002062, +0x3062001b, +0x0901f1f1, +0x0901f5f5, +0x0901f9f9, +0x10257f04, +0x6e2504ff, +0xd104ff03, +0x100a0a0b, +0x21028100, +0x16000a0b, +0x1301f1f1, +0xd10cff03, +0x102a2a2b, +0x21028600, +0x16002a2b, +0x1301f5f5, +0xd114ff03, +0x104a4a4b, +0x21028b00, +0x16004a4b, +0x1301f9f9, +0x1004047f, +0x10e9e9ea, +0x14ebe8e9, +0x10e7e7e8, +0x14ebe6e7, +0x10ebebe6, +0x0525a262, +0x3062001b, +0x0901e4e4, +0x0901e4e4, +0x0901e4e4, +0x10257f04, +0x6e2504ff, +0xd104ff03, +0x100a0a0b, +0x21029d00, +0x16000a0b, +0x1301e4e4, +0xd10cff03, +0x102a2a2b, +0x2102a200, +0x16002a2b, +0x1301e4e4, +0xd114ff03, +0x104a4a4b, +0x2102a700, +0x16004a4b, +0x1301e4e4, +0x1004047f, +0x10e9e9ea, +0x14ebe8e9, +0x10e7e7e8, +0x14ebe6e7, +0x10ebebe6, +0x2eff818b, +0x24000562, +0x30620014, +0x0901e4e4, +0x0901e4e4, +0x0901e4e4, +0x0901ebeb, +0x10257f04, +0x6e2504ff, +0xd104ff02, +0x2102ba00, +0x1301e4e4, +0x13010b0b, +0xd10cff02, +0x2102be00, +0x1301e4e4, +0x13012b2b, +0xd114ff02, +0x2102c200, +0x1301e4e4, +0x13014b4b, +0x1004047f, +0x21030c00, +0x3062001b, +0x0901f1f1, +0x0901f5f5, +0x0901f9f9, +0x10257f04, +0x6e2504ff, +0xd104ff03, +0x100a0a0b, +0x2102cf00, +0x16000a0b, +0x1301f1f1, +0xd10cff03, +0x102a2a2b, +0x2102d400, +0x16002a2b, +0x1301f5f5, +0xd114ff03, +0x104a4a4b, +0x2102d900, +0x16004a4b, +0x1301f9f9, +0x1004047f, +0x10e9e9ea, +0x14ebe8e9, +0x10e7e7e8, +0x14ebe6e7, +0x10ebebe6, +0x2eff818b, +0x0d206262, +0x19056262, +0x30620014, +0x0901f1f1, +0x0901f5f5, +0x0901f9f9, +0x0901ebeb, +0x10257f04, +0x6e2504ff, +0xd104ff02, +0x2102ed00, +0x1301f1f1, +0x13010b0b, +0xd10cff02, +0x2102f100, +0x1301f5f5, +0x13012b2b, +0xd114ff02, +0x2102f500, +0x1301f9f9, +0x13014b4b, +0x1004047f, +0x51056216, +0x0d056262, +0x30620014, +0x0901e4e4, +0x0901e4e4, +0x0901e4e4, +0x0901ebeb, +0x10257f04, +0x6e2504ff, +0xd104ff02, +0x21030300, +0x1301e4e4, +0x13010b0b, +0xd10cff02, +0x21030700, +0x1301e4e4, +0x13012b2b, +0xd114ff02, +0x21030b00, +0x1301e4e4, +0x13014b4b, +0x1004047f, +0x51001b26, +0xc9011b25, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0x10253b5b, +0x6e255bfd, +0x810c2b8e, +0x2400009c, +0xc9002508, +0xd1003c07, +0x2401088d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c0389b, +0x1f003c3c, +0xc9012508, +0xd1013c07, +0x2401108d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c4389b, +0x1f013c3c, +0xc9022508, +0xd1023c07, +0x2401188d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c8389b, +0x1f023c3c, +0x10253c1c, +0x6e251ce7, +0x2300d1dd, +0x500b0c03, +0x1d010000, +0x21033700, +0x1f010000, +0x502b2c03, +0x1d012020, +0x21033b00, +0x1f012020, +0x504b4c03, +0x1d014040, +0x21033f00, +0x1f014040, +0x691802d6, +0x240001c6, +0x24010186, +0x10e6e6e7, +0x10e6e6e8, +0x10e6e6e9, +0x10e6e6ea, +0x10257f04, +0x6e2504ff, +0x1004047f, +0x0505a262, +0x71206250, +0x24002062, +0x3062001b, +0x0901f2f2, +0x0901f6f6, +0x0901fafa, +0x10257f04, +0x6e2504ff, +0xd104ff03, +0x100a0a0b, +0x21035700, +0x16000a0b, +0x1301f2f2, +0xd10cff03, +0x102a2a2b, +0x21035c00, +0x16002a2b, +0x1301f6f6, +0xd114ff03, +0x104a4a4b, +0x21036100, +0x16004a4b, +0x1301fafa, +0x1004047f, +0x10e9e9ea, +0x14ebe8e9, +0x10e7e7e8, +0x14ebe6e7, +0x10ebebe6, +0x0525a262, +0x3062001b, +0x0901e4e4, +0x0901e4e4, +0x0901e4e4, +0x10257f04, +0x6e2504ff, +0xd104ff03, +0x100a0a0b, +0x21037300, +0x16000a0b, +0x1301e4e4, +0xd10cff03, +0x102a2a2b, +0x21037800, +0x16002a2b, +0x1301e4e4, +0xd114ff03, +0x104a4a4b, +0x21037d00, +0x16004a4b, +0x1301e4e4, +0x1004047f, +0x10e9e9ea, +0x14ebe8e9, +0x10e7e7e8, +0x14ebe6e7, +0x10ebebe6, +0x2eff818b, +0x24000562, +0x30620014, +0x0901e4e4, +0x0901e4e4, +0x0901e4e4, +0x0901ebeb, +0x10257f04, +0x6e2504ff, +0xd104ff02, +0x21039000, +0x1301e4e4, +0x13010b0b, +0xd10cff02, +0x21039400, +0x1301e4e4, +0x13012b2b, +0xd114ff02, +0x21039800, +0x1301e4e4, +0x13014b4b, +0x1004047f, +0x2103e200, +0x3062001b, +0x0901f2f2, +0x0901f6f6, +0x0901fafa, +0x10257f04, +0x6e2504ff, +0xd104ff03, +0x100a0a0b, +0x2103a500, +0x16000a0b, +0x1301f2f2, +0xd10cff03, +0x102a2a2b, +0x2103aa00, +0x16002a2b, +0x1301f6f6, +0xd114ff03, +0x104a4a4b, +0x2103af00, +0x16004a4b, +0x1301fafa, +0x1004047f, +0x10e9e9ea, +0x14ebe8e9, +0x10e7e7e8, +0x14ebe6e7, +0x10ebebe6, +0x2eff818b, +0x0d206262, +0x19056262, +0x30620014, +0x0901f2f2, +0x0901f6f6, +0x0901fafa, +0x0901ebeb, +0x10257f04, +0x6e2504ff, +0xd104ff02, +0x2103c300, +0x1301f2f2, +0x13010b0b, +0xd10cff02, +0x2103c700, +0x1301f6f6, +0x13012b2b, +0xd114ff02, +0x2103cb00, +0x1301fafa, +0x13014b4b, +0x1004047f, +0x51056216, +0x0d056262, +0x30620014, +0x0901e4e4, +0x0901e4e4, +0x0901e4e4, +0x0901ebeb, +0x10257f04, +0x6e2504ff, +0xd104ff02, +0x2103d900, +0x1301e4e4, +0x13010b0b, +0xd10cff02, +0x2103dd00, +0x1301e4e4, +0x13012b2b, +0xd114ff02, +0x2103e100, +0x1301e4e4, +0x13014b4b, +0x1004047f, +0x51001b26, +0xc9021b25, +0x91002b8e, +0x1f03eeee, +0x81002b8e, +0x2eff818e, +0x2401048d, +0x908d049b, +0x10253b5b, +0x6e255bfd, +0x810c2b8e, +0x2400009c, +0xc9002508, +0xd1003c07, +0x2401088d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c0389b, +0x1f003c3c, +0xc9012508, +0xd1013c07, +0x2401108d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c4389b, +0x1f013c3c, +0xc9022508, +0xd1023c07, +0x2401188d, +0x908d249b, +0xd11cfb04, +0x910c2b9b, +0x81c8389b, +0x1f023c3c, +0x10253c1c, +0x6e251ce7, +0x2300d1dd, +0x500b0c03, +0x1d020000, +0x21040d00, +0x1f020000, +0x502b2c03, +0x1d022020, +0x21041100, +0x1f022020, +0x504b4c03, +0x1d024040, +0x21041500, +0x1f024040, +0xc9004108, +0x1f13ffff, +0xc9002502, +0xd105ff00, +0xc9012502, +0xd10dff00, +0xc9022502, +0xd115ff00, +0x209d0000, +0x2eff8182, +0x810c2b82, +0x910c2b82, +0x4ee2e0ff, +0x20dd0000, +0x1f13ffff, +0xc9002502, +0xd105ff00, +0xc9012502, +0xd10dff00, +0xc9022502, +0xd115ff00, +0x24006000, +0x24010b8d, +0x808d0400, +0x2401138d, +0x808d0400, +0x24011b8d, +0x808d0400, +0x91b83880, +0x23041edd, +0x24002000, +0x24010b8d, +0x808d0400, +0x2401138d, +0x808d0400, +0x24011b8d, +0x808d0400, +0x91983880, +0x23041edd, +0x24006000, +0x24010b8d, +0x808d0400, +0x2401138d, +0x808d0400, +0x24011b8d, +0x808d0400, +0x91b43880, +0x23041edd, +0x24000000, +0x24010b8d, +0x808d0400, +0x2401138d, +0x808d0400, +0x24011b8d, +0x808d0400, +0x1f13ffff, +0xc9002502, +0xd105ff00, +0xc9012502, +0xd10dff00, +0xc9022502, +0xd115ff00, +0x240010de, +0x2400001e, +0x240011de, +0x2400001e, +0x240012de, +0x2400001e, +0x2401048d, +0x908d0462, +0x11e06262, +0x6f0062fd, +0x1f14ffff, +0xc9000505, +0x1f18ffff, +0xc91bff02, +0x1f1bffff, +0x1d18fefe, +0xc9010505, +0x1f19ffff, +0xc91cff02, +0x1f1cffff, +0x1d19fefe, +0xc9020505, +0x1f1affff, +0xc91dff02, +0x1f1dffff, +0x1d1afefe, +0x1f13ffff, +0xc9002502, +0xd105ff00, +0xc9012502, +0xd10dff00, +0xc9022502, +0xd115ff00, +0x209d0000, +0x24000081, +0x812c0381, +0x24ffff81, +0x81300381, +0x24810081, +0x81280381, +0x24008681, +0x812a0381, +0x24002081, +0x812c0381, +0x209d0000, +0x2401028d, +0x808d0480, +0x2401068d, +0x808d04c0, +0x24010e8d, +0x808d0481, +0x2401168d, +0x808d0481, +0x24011e8d, +0x808d0481, +0x209d0000, +0x2eff82c8, +0x130803de, +0x24000e1e, +0x90081822, +0x24000042, +0x0106a2a2, +0x0906a280, +0x0902a2a2, +0x04a280a2, +0x24003801, +0x24000141, +0x2300e4dd, +0x91a03880, +0x23041edd, +0x2401048d, +0x908d0480, +0xce2380fe, +0x2eff8180, +0x810c2b80, +0xc843ff00, +0x910c2b80, +0x2400007e, +0x00e0e9e9, +0x91a43880, +0x23041edd, +0x1f13ffff, +0xd063ff00, +0x91a83880, +0x23041edd, +0x0101c8c8, +0x6708c8e3, +0x0b03e9e9, +0x919c389b, +0x60fbe903, +0x04fbe9e9, +0x2104ac00, +0x209d0000 }; diff --git a/source/motor_control/position_sense/endat/firmware/endat_params.h b/source/motor_control/position_sense/endat/firmware/endat_params.h new file mode 100644 index 0000000..8349ffe --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/endat_params.h @@ -0,0 +1,153 @@ + +; +; Copyright (C) 2021-23 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + +; EnDat command definitions +; EnDat 2.1 commands +ENDAT_CMD_SEND_POSITION_VALUES .set (0x1C >> 1) +ENDAT_CMD_SEL_MEM_AREA .set (0x38 >> 1) +ENDAT_CMD_RECEIVE_PARAMETERS .set (0x70 >> 1) +ENDAT_CMD_SEND_PARAMETERS .set (0x8C >> 1) +ENDAT_CMD_RECEIVE_RESET .set (0xA8 >> 1) +ENDAT_CMD_SEND_TEST_VALUES .set (0x54 >> 1) +ENDAT_CMD_RECEIVE_TEST_COMMAND .set (0xC4 >> 1) +; EnDat 2.2 commands +ENDAT_CMD_SEND_POSVAL_WITH_DATA .set (0xE0 >> 1) +ENDAT_CMD_SEND_POSVAL_RECEIVE_MEMSEL .set (0x24 >> 1) +ENDAT_CMD_SEND_POSVAL_RECEIVE_PARAM .set (0x6C >> 1) +ENDAT_CMD_SEND_POSVAL_SEND_PARAM .set (0x90 >> 1) +ENDAT_CMD_SEND_POSVAL_RECEIVE_TESTCMD .set (0xD8 >> 1) +ENDAT_CMD_SEND_POSVAL_RECEIVE_ERR_RST .set (0xB4 >> 1) +ENDAT_CMD_RECEIVE_COMMUNICATION_CMD .set (0x48 >> 1) + + +MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE0 .set 0xA1 ; 12 words +MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE1 .set 0xA3 ; 16 words +MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE2 .set 0xA5 ; 16 words +MRS_CODE_PARAM_OPERATING_PARAMS .set 0xA7 ; 16 words +MRS_CODE_PARAM_OEM_PAGE0 .set 0xA9 ; 64 words +MRS_CODE_PARAM_OEM_PAGE1 .set 0xAB ; 128 words +MRS_CODE_PARAM_OEM_PAGE2 .set 0xAD ; 128 words + +MRS_CODE_OPERATING_STATUS .set 0xB9 ; 4 words +MRS_CODE_PARAM_ENCODER_MFG_ENDAT2_2 .set 0xBD ; 64 words +MRS_CODE_OEM_MEM_AREA_2_2 .set 0xBF ; 4 blocks with 256 words each + +MRS_CODE_ADDITIONAL_INFO1_WITHOUT_DATA .set 0x40 +MRS_CODE_ADDITIONAL_INFO1_DIAGNOSTIC .set 0x41 +MRS_CODE_ADDITIONAL_INFO1_POSVAL2_WORD1_LSB .set 0x42 +MRS_CODE_ADDITIONAL_INFO1_POSVAL2_WORD2 .set 0x43 +MRS_CODE_ADDITIONAL_INFO1_POSVAL2_WORD3_MSB .set 0x44 +MRS_CODE_ADDITIONAL_INFO1_ACK_MEM_LSB .set 0x45 +MRS_CODE_ADDITIONAL_INFO1_ACK_MEM_MSB .set 0x46 +MRS_CODE_ADDITIONAL_INFO1_ACK_MRS_CODE .set 0x47 +MRS_CODE_ADDITIONAL_INFO1_ACK_TEST_CMD .set 0x48 +MRS_CODE_ADDITIONAL_INFO1_TESTVAL_WORD1_LSB .set 0x49 +MRS_CODE_ADDITIONAL_INFO1_TESTVAL_WORD2 .set 0x4A +MRS_CODE_ADDITIONAL_INFO1_TESTVAL_WORD3_MSB .set 0x4B +MRS_CODE_ADDITIONAL_INFO1_TEMPERATURE1 .set 0x4C +MRS_CODE_ADDITIONAL_INFO1_TEMPERATURE2 .set 0x4D +MRS_CODE_ADDITIONAL_INFO1_ADTL_SENSORS .set 0x4E +MRS_CODE_ADDITIONAL_INFO1_STOP_DATA .set 0x4F + +MRS_CODE_ADDITIONAL_INFO2_WITHOUT_DATA .set 0x50 +MRS_CODE_ADDITIONAL_INFO2_COMMUNICATION .set 0x51 +MRS_CODE_ADDITIONAL_INFO2_ACCELERATION .set 0x52 +MRS_CODE_ADDITIONAL_INFO2_COMM_N_ACCLN .set 0x53 +MRS_CODE_ADDITIONAL_INFO2_LIMIT_POS_SIGNAL .set 0x54 +MRS_CODE_ADDITIONAL_INFO2_LPS_N_ACCLN .set 0x55 +MRS_CODE_ADDITIONAL_INFO2_ASYNCPOSVAL2_WORD1_LSB .set 0x56 +MRS_CODE_ADDITIONAL_INFO2_ASYNCPOSVAL2_WORD2 .set 0x57 +MRS_CODE_ADDITIONAL_INFO2_ASYNCPOSVAL2_WORD3_MSB .set 0x58 +MRS_CODE_ADDITIONAL_INFO2_OPSTATUS_ERRSOURCE .set 0x59 +MRS_CODE_ADDITIONAL_INFO2_STOP_DATA .set 0x5F + + + +ENDAT_TX_30BITS .set 30+1 ; Adjust 1-bit as we transmit early +ENDAT_TX_6BITS .set 6+1 ; Adjust 1-bit as we transmit early +ENDAT_RX_29BITS .set 29 +ENDAT_CMDTYP_2_1 .set 1 +ENDAT_CMDTYP_2_2 .set 0 +; ROQ_1035 .set + .if $isdefed("ROQ_1035") +ENDAT21_RX_POS_BITS .set 42 ; For EnDat 2.1: 1+1+35+5 - 35-bit position value +ENDAT22_RX_POS_BITS .set 43 ; For EnDat 2.2: 1+2+35+5 - 35-bit position value + .else +ENDAT21_RX_POS_BITS .set 44 ; For EnDat 2.1: 1+1+37+5 - 37-bit position value +ENDAT22_RX_POS_BITS .set 45 ; For EnDat 2.2: 1+2+37+5 - 37-bit position value + .endif +ENDAT_RX_46BITS .set 46 ; For EnDat 2.1: encoder to send test values + +WORD_0 .set 0 +WORD_1 .set 1 +WORD_2 .set 2 +WORD_3 .set 3 +WORD_4 .set 4 +WORD_5 .set 5 +WORD_6 .set 6 +WORD_7 .set 7 +WORD_8 .set 8 +WORD_9 .set 9 +WORD_10 .set 10 +WORD_11 .set 11 +WORD_12 .set 12 +WORD_13 .set 13 +WORD_14 .set 14 +WORD_15 .set 15 +WORD_16 .set 16 +WORD_17 .set 17 +WORD_18 .set 18 +WORD_19 .set 19 + +ENDAT_TEST_PORT_D_V .set 0 +ENDAT_TEST_PORT_D_B .set 1 +ENDAT_TEST_PORT_D_C .set 2 +ENDAT_TEST_PORT_D_D .set 13 +ENDAT_TEST_PORT_D_E .set 14 + + +; Time units below in nano sec + +ENDAT_RECOVERY_Tst .set 2000 ; 2-10us with wire delay compensation - 200m x 10 ns/m => Max 2us +ENDAT_RECOVERY_Tm .set 10000 ; 10-30us for EnDat2.1 Endat2.2 : 1.25us -3.75us for clock >= 1MHz +ENDAT_RECOVERY_Tr .set 500 ; Data shall be low during this period + +ENDAT_CONFIG_CH0 .set 0x1 +ENDAT_CONFIG_CH1 .set (0x1 << 1) +ENDAT_CONFIG_CH2 .set (0x1 << 2) + +ENDAT_CMDTYP_NO_SUPPLEMENT .set 0x1 +ENDAT_CMDTYP_POSITION .set (0x1 << 1) +ENDAT_CMDTYP_ENDAT22 .set (0x1 << 2) +ENDAT_CMDTYP_HAS_ADDINFO1 .set (0x1 << 3) +ENDAT_CMDTYP_HAS_ADDINFO2 .set (0x1 << 4) diff --git a/source/motor_control/position_sense/endat/firmware/firmware_version.h b/source/motor_control/position_sense/endat/firmware/firmware_version.h new file mode 100644 index 0000000..ecfa417 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/firmware_version.h @@ -0,0 +1,67 @@ + +; +; Copyright (C) 2021-23 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + + .if !$isdefed("__firmware_version_h") +__firmware_version_h .set 1 + +; ICSS_FIRMWARE_RELEASE_1: +; bit 31..16 reserved +; bit15..8 device number +FIRMWARE_DEVICE_AM335x .set 0 ; AM335x +FIRMWARE_DEVICE_AM437x .set 1 ; AM437x +FIRMWARE_DEVICE_AM64x .set 2 ; AM64x +; bit7..0 protocol type +FIRMWARE_PROTOCOL_TYPE_PROFIBUS_SLAVE .set 0x00 +FIRMWARE_PROTOCOL_TYPE_ETHERCAT_SLAVE .set 0x01 +FIRMWARE_PROTOCOL_TYPE_PROFINET_DEVICE .set 0x02 +FIRMWARE_PROTOCOL_TYPE_SERCOS_SLAVE .set 0x03 +FIRMWARE_PROTOCOL_TYPE_OPENMAC_SLAVE .set 0x04 +FIRMWARE_PROTOCOL_TYPE_ETHERNET .set 0x05 +FIRMWARE_PROTOCOL_TYPE_ENETIP_SLAVE .set 0x06 +FIRMWARE_PROTOCOL_TYPE_ENDAT_MASTER .set 0x07 + +; ICSS_FIRMWARE_RELEASE_2: +; bit31 release or internal version +FIRMWARE_VERSION_RELEASE .set 0 +FIRMWARE_VERSION_INTERNAL .set 1 +; bit30..24 version number +FIRMWARE_VERSION_REVISION .set 0x00 +; bit23..16 major number +FIRMWARE_VERSION_MAJOR .set 0x02 +; bit15..0 minor number +FIRMWARE_VERSION_MINOR .set 0x0001 + +ICSS_FIRMWARE_RELEASE_1 .set ((FIRMWARE_DEVICE_AM64x << 8) | (FIRMWARE_PROTOCOL_TYPE_ENDAT_MASTER << 0)) +ICSS_FIRMWARE_RELEASE_2 .set ((FIRMWARE_VERSION_RELEASE << 31) | (FIRMWARE_VERSION_REVISION << 24) | (FIRMWARE_VERSION_MAJOR << 16) | (FIRMWARE_VERSION_MINOR << 0)) + + .endif diff --git a/source/motor_control/position_sense/endat/firmware/makefile b/source/motor_control/position_sense/endat/firmware/makefile new file mode 100644 index 0000000..c150a92 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/makefile @@ -0,0 +1,131 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe +MCU_PLUS_SDK_PATH?=$(abspath ../../../../..) +CCS_PATH?=C:/ti/ccs1200/ccs/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 + +#Set the default mode +CHANNELS ?= SINGLE + +ifeq ($(CHANNELS),MULTI) +MULTI_CHANNEL=ENABLE_MULTI_CHANNEL +endif + +ifeq ($(CHANNELS),SINGLE) +MULTI_CHANNEL=0 +endif + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"endat_main.obj" \ +"endat_diagnostic.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +endat_diagnostic.cmd + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/endat_main.asm + +OBJS += \ +./endat_main.obj + +ASM_DEPS += \ +./endat_main.d + +OBJS__QUOTED += \ +"endat_main.obj" + +ASM_DEPS__QUOTED += \ +"endat_main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/endat_main.asm" + +# Each subdirectory must supply rules for building sources it contributes +endat_main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/endat_main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" --include_path="$(CCS_PATH)" --include_path="$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware" --include_path="$(CG_TOOL_ROOT)/include" --define=PRU1 --define=$(MULTI_CHANNEL) --define=icssg1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(/// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware", + ], +}; + +const defines_rtu = { + common: [ + "ENABLE_MULTI_MAKE_RTU", + + ], + +}; +const defines_pru = { + common: [ + + "ENABLE_MULTI_MAKE_PRU", + + ], + +}; +const defines_txpru = { + common: [ + "ENABLE_MULTI_MAKE_TXPRU", + ], + +}; + + + +const readmeDoxygenPageTag = "ENDAT_DESIGN"; + +const cflags = { + common: [ + "-v4" + ], +}; + +const lflags = { + common: [ + "--entry_point=ENDAT_INIT", + "--disable_auto_rts", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, + { device: device, cpu: "icssg0-rtupru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, + { device: device, cpu: "icssg0-txpru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +let postBuildStepsPru1 = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 endat_master_multi_PRU_bin.h EnDatFirmwareMultiMakePRU 4; move endat_master_multi_PRU_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_multi_PRU_bin.h;", + +]; +let postBuildStepsRtupru1 = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt.b00 endat_master_multi_RTU_bin.h EnDatFirmwareMultiMakeRTU 4; move endat_master_multi_RTU_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_multi_RTU_bin.h;", + +]; +let postBuildStepsTxpru1 = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt.b00 endat_master_multi_TXPRU_bin.h EnDatFirmwareMultiMakeTXPRU 4; move endat_master_multi_TXPRU_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_multi_TXPRU_bin.h;", + +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "endat_peripheral_interface_multi_ch_load_share"; + property.isInternal = false; + property.description = "Endat Multi channel Interface for Different Make Encoders" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + if(buildOption.cpu.match("icssg0-pru1")) + { + build_property.defines = defines_pru; + property.postBuildSteps = postBuildStepsPru1; + } + if(buildOption.cpu.match("icssg0-rtupru1")) + { + build_property.defines = defines_rtu; + property.postBuildSteps = postBuildStepsRtupru1; + } + if(buildOption.cpu.match("icssg0-txpru1")) + { + build_property.defines = defines_txpru; + property.postBuildSteps = postBuildStepsTxpru1; + } + + build_property.cflags = cflags; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/.project/project_am64x.js b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/.project/project_am64x.js new file mode 100644 index 0000000..b9fd2ba --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/.project/project_am64x.js @@ -0,0 +1,138 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "endat_main.asm", + "endat_diagnostic.cmd", + "endat_master_hexpru.cmd" + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware", + ], +}; + +const defines_rtu = { + common: [ + "ENABLE_MULTI_MAKE_RTU", + + ], + +}; +const defines_pru = { + common: [ + + "ENABLE_MULTI_MAKE_PRU", + + ], + +}; +const defines_txpru = { + common: [ + "ENABLE_MULTI_MAKE_TXPRU", + ], + +}; + + + +const readmeDoxygenPageTag = "ENDAT_DESIGN"; + +const cflags = { + common: [ + "-v4" + ], +}; + +const lflags = { + common: [ + "--entry_point=ENDAT_INIT", + "--disable_auto_rts", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, + { device: device, cpu: "icssg0-rtupru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, + { device: device, cpu: "icssg0-txpru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +let postBuildStepsPru1 = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 endat_master_multi_PRU_bin.h EnDatFirmwareMultiMakePRU 4; move endat_master_multi_PRU_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_multi_PRU_bin.h ;" + +]; +let postBuildStepsRtupru1 = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-rtupru1_fw_ti-pru-cgt.b00 endat_master_multi_RTU_bin.h EnDatFirmwareMultiMakeRTU 4; move endat_master_multi_RTU_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_multi_RTU_bin.h;" + +]; +let postBuildStepsTxpru1 = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_multi_ch_load_share_am64x-evm_icssg0-txpru1_fw_ti-pru-cgt.b00 endat_master_multi_TXPRU_bin.h EnDatFirmwareMultiMakeTXPRU 4; move endat_master_multi_TXPRU_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_multi_TXPRU_bin.h;" + +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "endat_peripheral_interface_multi_ch_load_share"; + property.isInternal = false; + property.description = "Endat Multi channel Interface for Different Make Encoders" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + if(buildOption.cpu.match("icssg0-pru1")) + { + build_property.postBuildSteps = postBuildStepsPru1; + build_property.defines = defines_pru; + } + if(buildOption.cpu.match("icssg0-rtupru1")) + { + build_property.postBuildSteps = postBuildStepsRtupru1; + build_property.defines = defines_rtu; + } + if(buildOption.cpu.match("icssg0-txpru1")) + { + build_property.postBuildSteps = postBuildStepsTxpru1; + build_property.defines = defines_txpru; + } + + build_property.cflags = cflags; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..2556259 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..6b594dd --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --define=ENABLE_MULTI_MAKE_PRU --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..f74622a --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --define=ENABLE_MULTI_MAKE_RTU --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..a31cbb9 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DTX_PRU1 -DSLICE1 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --define=ENABLE_MULTI_MAKE_TXPRU --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..4e502d9 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM64X --define=ENABLE_MULTI_MAKE_PRU --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..35e1610 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-rtupru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM64X --define=ENABLE_MULTI_MAKE_RTU --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..92f09c6 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-txpru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_load_share/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DTX_PRU1 -DSLICE1 -DPRU1 -DSLICE1 -v4 --define=SOC_AM64X --define=ENABLE_MULTI_MAKE_TXPRU --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(/// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware", + ], +}; + +const defines = { + common: [ + "ENABLE_MULTI_CHANNEL", + ], +}; + + + +const readmeDoxygenPageTag = "ENDAT_DESIGN"; + +const cflags = { + common: [ + "-v4" + ], +}; + +const lflags = { + common: [ + "--entry_point=ENDAT_INIT", + "--disable_auto_rts", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 endat_master_multi_bin.h EnDatFirmwareMulti 4; move endat_master_multi_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_multi_bin.h;", + +]; +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "endat_peripheral_interface_multi_ch"; + property.isInternal = false; + property.description = "Endat Multi Channel Interface for Same make encoders" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + property.postBuildSteps = postBuildSteps; + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.cflags = cflags; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/.project/project_am64x.js b/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/.project/project_am64x.js new file mode 100644 index 0000000..dfe197a --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/.project/project_am64x.js @@ -0,0 +1,101 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "endat_main.asm", + "endat_diagnostic.cmd", + "endat_master_hexpru.cmd" + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware", + ], +}; + +const defines = { + common: [ + "ENABLE_MULTI_CHANNEL", + ], +}; + + + +const readmeDoxygenPageTag = "ENDAT_DESIGN"; + +const cflags = { + common: [ + "-v4" + ], +}; + +const lflags = { + common: [ + "--entry_point=ENDAT_INIT", + "--disable_auto_rts", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_multi_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 endat_master_multi_bin.h EnDatFirmwareMulti 4; move endat_master_multi_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_multi_bin.h;", + + +]; +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "endat_peripheral_interface_multi_ch"; + property.isInternal = false; + property.description = "Endat Multi Channel Interface for Same make encoders" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + property.postBuildSteps = postBuildSteps; + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.cflags = cflags; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..328883b --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,76 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..4812391 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --define=ENABLE_MULTI_CHANNEL --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..d543cec --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/multi_channel_single_pru/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM64X --define=ENABLE_MULTI_CHANNEL --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(/// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware", + ], +}; + +const defines = { + common: [ + + ], +}; +/*const lnkfiles = { + common: [ + "linker.cmd", + ] +};*/ + + +const readmeDoxygenPageTag = "ENDAT_DESIGN"; + +const cflags = { + common: [ + "-v4" + ], +}; + +const lflags = { + common: [ + "--entry_point=ENDAT_INIT", + "--disable_auto_rts", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 endat_master_bin.h EnDatFirmware 4; move endat_master_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_bin.h;" + +]; +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "endat_peripheral_interface_single_ch"; + property.isInternal = false; + property.description = "Endat Peripheral Interface" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + property.postBuildSteps = postBuildSteps; + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.cflags = cflags; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/endat/firmware/single_channel/.project/project_am64x.js b/source/motor_control/position_sense/endat/firmware/single_channel/.project/project_am64x.js new file mode 100644 index 0000000..8c0f2ba --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/single_channel/.project/project_am64x.js @@ -0,0 +1,99 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "endat_main.asm", + "endat_diagnostic.cmd", + "endat_master_hexpru.cmd" + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware", + ], +}; + +const defines = { + common: [ + + ], +}; + + + +const readmeDoxygenPageTag = "ENDAT_DESIGN"; + +const cflags = { + common: [ + "-v4" + ], +}; + +const lflags = { + common: [ + "--entry_point=ENDAT_INIT", + "--disable_auto_rts", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_hexpru.cmd endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe endat_peripheral_interface_single_ch_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 endat_master_bin.h EnDatFirmware 4; move endat_master_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware/endat_master_bin.h;", + +]; +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "endat_peripheral_interface_single_ch"; + property.isInternal = false; + property.description = "Endat Peripheral Interface" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + property.postBuildSteps = postBuildSteps; + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.cflags = cflags; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..bfb367b --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,75 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..7cb0e33 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..78ffc20 --- /dev/null +++ b/source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/endat/firmware/single_channel/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM64X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(); + * [AM437x: endat_init(0x54440000);] + * + * B. Configure to host trigger mode + * + * endat_config_host_trigger(priv); + * + * C. Select channel + * + * endat_config_channel(priv, <#channel>); + * + * D. Load & run the firmware + * + * E. Wait for firmware to initialize, clock frequency would be set to 8MHz by the end of the following command + * + * endat_wait_initialization(priv, ); + * + * F. Set 200KHz frequency to read encoder information so as to not to be affected by propagation delay + * + * endat_config_clock(priv, clk_cfg); + * + * G. Get encoder information + * + * endat_get_encoder_info(priv); + * + * H. Set operating frequency, say 8MHz + * + * endat_config_clock(priv, &clk_cfg); + * + * I. Get the propagation delay estimated by the firmware + * + * prop_delay = endat_get_prop_delay(priv); + * + * J. Handle propagation delay + * + * endat_config_rx_arm_cnt(priv, ); + * endat_config_rx_clock_disable(priv, ); + * + * K. Configure tST + * + * endat_config_tst_delay(priv, 1MHz, use 2000, else 0)>); + * + * L. Process the EnDat command, transmit, this returns upon receive & command is complete, + * + * endat_command_process(priv, cmd, cmd_supplement); + * + * M. Process the received data + * + * endat_recvd_process(priv, cmd, &endat_format_data); + * + * N. Do CRC verification + * + * endat_recvd_validate(priv, cmd, &endat_format_data); + * + * O. Update additional information state tracking, if needed + * + * endat_addinfo_track(priv, cmd, &cmd_supplement); + * + * Result would be in union endat_format_data + * + * + * Example API usage [simplified] (periodic trigger mode, single channel): + * ----------------------------------------------------------------------- + * + * Note: IEP CMP2 is the trigger event in periodic trigger mode and has to be setup beforehand. + * + * A. Get encoder info, follow steps A, B, C, D, E, G of host trigger mode, firmware defaults to 8MHz frequency + * + * B. Switch to periodic trigger mode, this will take effect after the next command completes + * + * endat_config_periodic_trigger(priv); + * + * C. Setup & send the 2.2 position periodic command, needs to be done only once + * + * endat_command_process(priv, 8, NULL); + * + * D. After giving enough time to complete the command after periodic event, to read angle for rotary encoder quickly + * + * endat_get_2_2_angle(priv); + * + * + * Example API usage (periodic trigger mode, single channel): + * --------------------------------------------------------- + * + * Note: IEP CMP2 is the trigger event in periodic trigger mode and has to be setup beforehand. + * + * A. Get encoder info & set desired timings for required frequency taking care of propagation delay, steps A-K of host trigger mode + * + * B. Switch to periodic trigger mode, this will take effect after the next command completes + * + * endat_config_periodic_trigger(priv); + * + * C. Setup the command to be periodically sent + * + * endat_command_build(priv, cmd, cmd_supplement); + * + * D. Send the command + * + * endat_command_send(priv); + * + * E. Wait for the command to finish + * + * endat_command_wait(priv); + * + * F. Process the received data + * + * endat_recvd_process(priv, cmd, &endat_format_data); + * + * G. Do CRC verification + * + * endat_recvd_validate(priv, cmd, &endat_format_data); + * + * H. Update additional information state tracking, if needed + * + * endat_addinfo_track(priv, cmd, &cmd_supplement); + * + * Result would be in union endat_format_data + * + * Repeat E-H to get periodic update after the next periodic event
+ * happens, this can be done in say ISR (which could be linked to the
+ * periodic event). For a new command to be executed periodically,
+ * endat_command_build() can invoked after step H, this will take effect
+ * from the next periodic event. + * + * EnDat commands: + * --------------- + * + * Command description of command numbers passed to endat_command_process() + * and endat_command_build() as follows, + * + * 1: Encoder send position values
+ * 2: Selection of memory area
+ * 3: Encoder receive parameter
+ * 4: Encoder send parameter
+ * 5: Encoder receive reset
+ * 6: Encoder send test values
+ * 7: Encoder receive test command
+ * 8: Encoder to send position + AI(s)
+ * 9: Encoder to send position + AI(s) and receive selection of memory area
+ * 10: Encoder to send position + AI(s) and receive parameter
+ * 11: Encoder to send position + AI(s) and send parameter
+ * 12: Encoder to send position + AI(s) and receive error reset
+ * 13: Encoder to send position + AI(s) and receive test command
+ * 14: Encoder receive communication command
+ * + */ + +#ifndef ENDAT_API_H_ +#define ENDAT_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + /** + * \defgroup MOTOR_CONTROL_API APIs for Motor Control Encoders + * + * This module contains APIs for device drivers for various motor control encoders supported in this SDK. + */ + +/** + * \defgroup ENDAT_API_MODULE APIs for ENDAT Encoder + * \ingroup MOTOR_CONTROL_API + * + * Here is the list of APIs used for EnDAT encoder communication protocol + * + * @{ + */ + +/** + * \brief process raw recieved data and format based on the command + * + * \param[in] priv cookie returned by endat_init + * \param[in] cmd EnDat command number + * \param[out] u pointer to union for storing formatted data based on cmd + * + * \retval 0 for success, -EINVAL for failure + * + */ +int32_t endat_recvd_process(struct endat_priv *priv, int32_t cmd, + union endat_format_data *u); + +/** + * \brief CRC result indicated in return value as follows,
+ * 0th bit high position/address/params/test CRC success
+ * 0th bit low position/address/params/test CRC failure
+ * 1st bit high if addinfo 1 present, addinfo 1 CRC success
+ * 1st bit low if addinfo 1 present, addinfo 1 CRC failure
+ * 2nd bit high if addinfo 2 present, addinfo 2 CRC success
+ * 2nd bit low if addinfo 2 present, addinfo 2 CRC failure + * + * \param[in] priv cookie returned by endat_init + * \param[in] cmd EnDat command number + * \param[in] u pointer to union having formatted data based on cmd + * + * \retval status position/address/params/test CRC status + * + */ +uint32_t endat_recvd_validate(struct endat_priv *priv, int32_t cmd, + union endat_format_data *u); + +/** + * \brief send the EnDat command and wait till firmware acknowledges + * + * \param[in] priv cookie returned by endat_init + * \param[in] cmd EnDat command number + * \param[in] cmd_supplement Supplement information needed to setup EnDat cmd + * + * \retval 0 for success, -EINVAL for failure + * + */ +int32_t endat_command_process(struct endat_priv *priv, int32_t cmd, + struct cmd_supplement *cmd_supplement); + +/** + * \brief setup the EnDat command in the PRU interface buffer + * + * \param[in] priv cookie returned by endat_init + * \param[in] cmd EnDat command number + * \param[in] cmd_supplement Supplement information needed to setup EnDat cmd + * + * \retval 0 for success, -EINVAL for failure + * + */ +int32_t endat_command_build(struct endat_priv *priv, int32_t cmd, + struct cmd_supplement *cmd_supplement); + +/** + * \brief trigger sending the EnDat command in PRU + * + * \param[in] priv cookie returned by endat_init + * + * + */ +void endat_command_send(struct endat_priv *priv); + +/** + * \brief wait till PRU finishes EnDat transaction + * + * \param[in] priv cookie returned by endat_init + * + * + */ +void endat_command_wait(struct endat_priv *priv); + + +/** + * \brief read RT from DMEM + * + * \param[in] priv cookie returned by endat_init + * + * \retval Value of Recovery Time in nanoseconds + * + */ +uint32_t endat_get_recovery_time(struct endat_priv *priv); + +/** + * \brief update priv with position resolution, id, serial number, encoder + * type and supported command set + * + * \param[in] priv cookie returned by endat_init + * + * \retval 0 for success, -EINVAL for failure + * + */ +int32_t endat_get_encoder_info(struct endat_priv *priv); + +/** + * \brief get propagation delay automatically estimated by the firmware + * + * \param[in] priv cookie returned by endat_init + * + * \retval delay estimated propogation delay + * + */ +uint32_t endat_get_prop_delay(struct endat_priv *priv); + +/** + * \brief track presence of additional information in priv + * + * \param[in] priv cookie returned by endat_init + * \param[in] cmd EnDat command number + * \param[in] cmd_supplement Supplement information needed to setup EnDat cmd + * + * + */ +void endat_addinfo_track(struct endat_priv *priv, int32_t cmd, + struct cmd_supplement *cmd_supplement); + +/** + * \brief configure EnDat clock + * + * \param[in] priv cookie returned by endat_init + * \param[in] clk_cfg pointer to structure containing clock configuration data + * + * + */ +void endat_config_clock(struct endat_priv *priv, + struct endat_clk_cfg *clk_cfg); + +/** + * \brief configure tST delay + * + * \param[in] priv cookie returned by endat_init + * \param[in] delay tST delay value + * + * + */ +void endat_config_tst_delay(struct endat_priv *priv, uint16_t delay); + +/** + * \brief configure rx arm counter + * + * \param[in] priv cookie returned by endat_init + * \param[in] val rx arm counter value in ns + * + * + */ +void endat_config_rx_arm_cnt(struct endat_priv *priv, uint16_t val); + +/** + * \brief configure wire delay for the selected channel + * + * \param[in] priv cookie returned by endat_init + * \param[in] val wire delay in ns + * + * + */ +void endat_config_wire_delay(struct endat_priv *priv, uint16_t val); + +/** + * \brief configure clocks to be disabled at the end of rx to account for tD + * + * \param[in] priv cookie returned by endat_init + * \param[in] val number of clocks to be disabled + * + * + */ +void endat_config_rx_clock_disable(struct endat_priv *priv, + uint16_t val); + +/** + * \brief start continuous mode + * + * \param[in] priv cookie returned by endat_init + * + * \retval 0 success, -EINVAL for failure + * + */ +int32_t endat_start_continuous_mode(struct endat_priv *priv); + +/** + * \brief stop continuous mode + * + * \param[in] priv cookie returned by endat_init + * + * + */ +void endat_stop_continuous_mode(struct endat_priv *priv); + +/** + * \brief configure EnDat master for host trigger mode + * + * \param[in] priv cookie returned by endat_init + * + * + */ +void endat_config_host_trigger(struct endat_priv *priv); + +/** + * \brief configure EnDat master in periodic trigger mode + * + * \param[in] priv cookie returned by endat_init + * + * + */ +void endat_config_periodic_trigger(struct endat_priv *priv); +/* brief set syn_bits of all connected channels for synchronization before global_TX_init + * + * \param[in] priv cookie returned by endat_init + * \param[in] mask channels mask + * + */ +void endat_config_syn_bits(struct endat_priv *priv, uint8_t mask); +/** + * \brief set a core as primay core for global configuration, clk configuration and TX_GLOBAL_INIT + * + * \param[in] priv cookie returned by endat_init + * \param[in] mask channels mask + * + * + */ +void endat_config_primary_core_mask(struct endat_priv *priv, uint8_t mask); +/** + * \brief enable load share mode if encoders has diffent make + * + * \param[in] priv cookie returned by endat_init + * + */ +void endat_enable_load_share_mode(struct endat_priv *priv); +/** + * \brief select channel to be used by EnDat master + * + * \param[in] priv cookie returned by endat_init + * \param[in] ch channel to be selected + * + * + */ +void endat_config_channel(struct endat_priv *priv, int32_t ch); +/** + * \brief select mask of channels to be used in multi channel configuration by EnDat master + * + * \param[in] priv cookie returned by endat_init + * \param[in] mask channel mask + * \param[in] loadshare value for loadshare mode enable. + * + */ +void endat_config_multi_channel_mask(struct endat_priv *priv, + uint8_t mask, + uint8_t loadshare); +/** + * \brief select channels detected in multi channel configuration by EnDat master.
+ * required to be invoked only if firmware indicates initialization failure
+ * to know the channels that has been detected. Initialization success implies
+ * that all channels indicated has been detected. + * + * \param[in] priv cookie returned by endat_init + * + * \retval mask mask of the detected channels + * + */ +uint8_t endat_multi_channel_detected(struct endat_priv *priv); + +/** + * \brief In multi channel configuration, select channel before receive processing in
+ * multi channel configuration. After receive is complete, select each channel
+ * and invoke rx API's to parse data recieved in each channel. + * + * \param[in] priv cookie returned by endat_init + * \param[in] ch channel number to be selected + * + * + */ +void endat_multi_channel_set_cur(struct endat_priv *priv, int32_t ch); +/** + * \brief wait for EnDat master firmware to initialize + * + * \param[in] priv cookie returned by endat_init + * \param[in] timeout timeout to wait for initialization + * \param[in] mask channel mask + * \retval 0 for success, -EINVAL for failure + * + */ +int32_t endat_wait_initialization(struct endat_priv *priv, uint32_t timeout, uint8_t mask); + +/** + * \brief Initialize EnDat firmware interface address and get the pointer + * to struct endat_priv instance + * + * \param[in] pruss_xchg EnDat firmware interface address + * \param[in] pruss_cfg ICSS PRU config base address + * \param[in] slice ICSS PRU SLICE + * + * \retval priv pointer to struct endat_priv instance + * + */ +struct endat_priv *endat_init(struct endat_pruss_xchg *pruss_xchg, + void *pruss_cfg, int32_t slice); + +/** + * \brief Read EnDat 2.2 angular position in steps for rotary encoders
+ * (prior to invoking this, 2.2 position command has to be completed)
+ * This checks the CRC status (updated on-the-fly by firmware),
+ * checks the group alarm errors (F1/F2 bits) and the angle value
+ * recieved in reverse are reversed in a highly optimized way using
+ * inline assembly.
+ * Assumptions (that holds good for quite a few encoders):
+ * 1. Total resolution >= 25
+ * 2. Single turn resolution <= 30 + * + * \param[in] priv cookie returned by endat_init + * + * \retval angle for angular position in steps on success, -1 for failure + * + */ +int32_t endat_get_2_2_angle(struct endat_priv *priv); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/motor_control/position_sense/endat/include/endat_drv.h b/source/motor_control/position_sense/endat/include/endat_drv.h new file mode 100644 index 0000000..6d91e8f --- /dev/null +++ b/source/motor_control/position_sense/endat/include/endat_drv.h @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2021-23 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef ENDAT_DRV_H_ +#define ENDAT_DRV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#define ENDAT_MODE_SINGLE_CHANNEL_SINGLE_PRU (0U) +#define ENDAT_MODE_MULTI_CHANNEL_SINGLE_PRU (1U) +#define ENDAT_MODE_MULTI_CHANNEL_MULTI_PRU (2U) + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) + + +/*12 words */ +#define MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE0 0xA1 +/*16 words */ +#define MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE1 0xA3 +/*16 words*/ +#define MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE2 0xA5 + +/* Adjust 1-bit as we transmit early */ +#define ENDAT_TX_30BITS (30 + 1) +/*Adjust 1-bit as we transmit early */ +#define ENDAT_TX_6BITS (6 + 1) +#define ENDAT_RX_29BITS 29 +/* For EnDat 2.1: encoder to send test values */ +#define ENDAT_RX_46BITS 46 + +#define APP_ENDAT_WORD_0 0 +#define APP_ENDAT_WORD_1 1 +#define APP_ENDAT_WORD_2 2 +#define APP_ENDAT_WORD_3 3 +#define APP_ENDAT_WORD_4 4 +#define APP_ENDAT_WORD_5 5 +#define APP_ENDAT_WORD_6 6 +#define APP_ENDAT_WORD_7 7 +#define APP_ENDAT_WORD_8 8 +#define APP_ENDAT_WORD_9 9 +#define APP_ENDAT_WORD_10 10 +#define APP_ENDAT_WORD_11 11 +#define APP_ENDAT_WORD_12 12 +#define APP_ENDAT_WORD_13 13 +#define APP_ENDAT_WORD_14 14 +#define APP_ENDAT_WORD_15 15 +#define APP_ENDAT_WORD_16 16 +#define APP_ENDAT_WORD_17 17 +#define APP_ENDAT_WORD_18 18 +#define APP_ENDAT_WORD_19 19 + +#define ENDAT_NUM_BITS_POSITION_CRC 5 +#define ENDAT_NUM_BITS_F1 1 +#define ENDAT_NUM_BITS_F2 1 +#define ENDAT_NUM_BITS_PARAMETER 16 +#define ENDAT_NUM_BITS_ADDRESS 8 + +#define EINVAL 1 + +struct endat_clk_cfg +{ + uint16_t rx_div; + uint16_t tx_div; + uint16_t rx_en_cnt; + uint16_t rx_div_attr; +}; + +struct flags +{ + uint32_t info1 : 1; + uint32_t info2 : 1; +}; + +struct id +{ + uint32_t ascii; + uint32_t binary; +}; + +struct sn +{ + uint32_t ascii_msb; + uint32_t binary; + uint32_t ascii_lsb; +}; + +enum { linear, rotary }; + +struct endat_priv +{ int32_t pruicss_slicex; + int32_t load_share; + int32_t pos_res; + int32_t single_turn_res; + int32_t multi_turn_res; + int32_t step; + uint32_t pos_rx_bits_21_RTUPRU; + uint32_t pos_rx_bits_21_PRU; + uint32_t pos_rx_bits_21_TXPRU; + uint32_t pos_rx_bits_22_RTUPRU; + uint32_t pos_rx_bits_22_PRU; + uint32_t pos_rx_bits_22_TXPRU; + struct flags flags; + struct id id; + struct sn sn; + uint32_t cmd_set_2_2; + int32_t type; + int32_t raw_data; + int32_t channel; + uint16_t rx_en_cnt; + struct endat_pruss_xchg *pruss_xchg; + int32_t has_safety; + void *pruss_cfg; +}; + +struct cmd_supplement +{ + /* + * uint8_t is ideal for address, but as scanf(%x) is done, + * there could be side effects as other fields may get corrupted, + * though it is not much of an issue as address is ensured to be + * less than 0xff. But to be on safer side keep it unsigned, + * same applies to block also + */ + uint32_t address; + uint32_t data; + uint32_t block; + uint8_t has_block_address; + uint32_t frequency; +}; + +struct endat_data +{ + /* position */ + uint64_t recvd1; + /* addinfo 1/2 */ + uint32_t recvd2; + /* addinfo 1 */ + uint32_t recvd3; +}; + +struct endat_position +{ + uint64_t position; + uint64_t revolution; + uint8_t f1; + uint8_t f2; + uint8_t crc; +}; + +struct endat_addinfo +{ + uint32_t addinfo; + uint8_t crc; +}; + +struct endat_position_addinfo +{ + struct endat_position position; + struct endat_addinfo addinfo1, addinfo2; +}; + +struct endat_addr_params +{ + uint8_t address; + uint16_t params; + uint8_t crc; +}; + +struct endat_test_values +{ + uint64_t value; + uint8_t f1; + uint8_t crc; +}; + +union endat_format_data +{ + struct endat_position_addinfo position_addinfo; + struct endat_addr_params addr_params; + struct endat_test_values test; +}; + +#define VALID_2_1_CMD(x) (((x) == 1) || ((x) == 2) || ((x) == 3) || ((x) == 4) || ((x) == 5) || ((x) == 6) || ((x) == 7) ) +#define VALID_2_2_CMD(x) (((x) == 8) || ((x) == 9) || ((x) == 10) || ((x) == 11) || ((x) == 12) || ((x) == 13) || ((x) == 14)) + +#define ENDAT_NUM_ADDITIONAL_INFO_DUMMY_BIT 1 +#define ENDAT_NUM_BYTES_ADDITIONAL_INFO 3 + +#define ENDAT_STATUS_WARN_SHIFT 7 +#define ENDAT_STATUS_RM_SHIFT 6 +#define ENDAT_STATUS_BUSY_SHIFT 5 +#define ENDAT_STATUS_WARN_MASK (1 << ENDAT_STATUS_WARN_SHIFT) +#define ENDAT_STATUS_RM_MASK (1 << ENDAT_STATUS_RM_SHIFT) +#define ENDAT_STATUS_BUSY_MASK (1 << ENDAT_STATUS_BUSY_SHIFT) +#define ENDAT_INFORMATION_MASK 0x1f + +#define ENDAT_21_F1_SHIFT 31 +#define ENDAT_21_F1_MASK (1 << ENDAT_21_F1_SHIFT) +#define ENDAT_22_F1_SHIFT ENDAT_21_F1_SHIFT +#define ENDAT_22_F1_MASK (1 << ENDAT_22_F1_SHIFT) +#define ENDAT_F2_SHIFT 30 +#define ENDAT_F2_MASK (1 << ENDAT_F2_SHIFT) + +#define ENDAT_ADDITIONAL_INFO_RX_BITS 30 + +#define ENDAT_SECTION2_MEMORY 0xBF + +#define ENDAT_NUM_BITS_VALID_PAGE0_WORD13 6 + +#define ENDAT_NUM_BITS_VALID_PAGE1_WORD1 16 + +#define ENDAT_MRS_SHIFT_C7_C4 (4) +#define ENDAT_MRS_VAL_C7_C4_SELECT_ADDITIONAL_INFO1 (0x4) +#define ENDAT_MRS_VAL_C7_C4_SELECT_ADDITIONAL_INFO2 (0x5) +#define ENDAT_MRS_MASK_SELECT_ADDITIONAL_INFO (0xF << ENDAT_MRS_SHIFT_C7_C4) +#define ENDAT_MRS_VAL_STOP_ADDITIONAL_INFO (0xF) +#define ENDAT_MRS_MASK_STOP_ADDITIONAL_INFO (ENDAT_MRS_VAL_STOP_ADDITIONAL_INFO) + +#define ENDAT_GET_POS_MULTI_TURN(pos, priv) (((pos) & (((unsigned long long) 1 << (priv)->pos_res) - 1)) >> (priv)->single_turn_res) +#define ENDAT_GET_POS_SINGLE_TURN(pos, priv) ((pos) & (((unsigned long long) 1 << (priv)->single_turn_res) - 1)) + +#include "endat_api.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/motor_control/position_sense/endat/include/endat_interface.h b/source/motor_control/position_sense/endat/include/endat_interface.h new file mode 100644 index 0000000..225281b --- /dev/null +++ b/source/motor_control/position_sense/endat/include/endat_interface.h @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2021-23 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ENDAT_INTERFACE_H_ +#define ENDAT_INTERFACE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ========================================================================== */ +/* Macros */ +/* ========================================================================== */ + +/** \brief 2.1 send position value */ +#define ENDAT_CMD_SEND_POSITION_VALUES (0x1C >> 1) +/** \brief 2.1 select memory area */ +#define ENDAT_CMD_SEL_MEM_AREA (0x38 >> 1) +/** \brief 2.1 receive paramter */ +#define ENDAT_CMD_RECEIVE_PARAMETERS (0x70 >> 1) +/** \brief 2.1 send paramter */ +#define ENDAT_CMD_SEND_PARAMETERS (0x8C >> 1) +/** \brief 2.1 receive reset */ +#define ENDAT_CMD_RECEIVE_RESET (0xA8 >> 1) +/** \brief 2.1 send test values */ +#define ENDAT_CMD_SEND_TEST_VALUES (0x54 >> 1) +/** \brief 2.1 receive test command */ +#define ENDAT_CMD_RECEIVE_TEST_COMMAND (0xC4 >> 1) + +/** \brief 2.2 send position value with addinfo(s) */ +#define ENDAT_CMD_SEND_POSVAL_WITH_DATA (0xE0 >> 1) +/** \brief 2.2 send position value with addinfo(s) & select memory area */ +#define ENDAT_CMD_SEND_POSVAL_RECEIVE_MEMSEL (0x24 >> 1) +/** \brief 2.2 send position value with addinfo(s) & receive parameter */ +#define ENDAT_CMD_SEND_POSVAL_RECEIVE_PARAM (0x6C >> 1) +/** \brief 2.2 send position value with addinfo(s) & send parameter */ +#define ENDAT_CMD_SEND_POSVAL_SEND_PARAM (0x90 >> 1) +/** \brief 2.2 send position value with addinfo(s) & receive test command */ +#define ENDAT_CMD_SEND_POSVAL_RECEIVE_TESTCMD (0xD8 >> 1) +/** \brief 2.2 send position value with addinfo(s) & receive error reset */ +#define ENDAT_CMD_SEND_POSVAL_RECEIVE_ERR_RST (0xB4 >> 1) +/** \brief 2.2 receive communication command */ +#define ENDAT_CMD_RECEIVE_COMMUNICATION_CMD (0x48 >> 1) + +/** \brief command has no command supplement */ +#define ENDAT_CMDTYP_NO_SUPPLEMENT 0x1 +/** \brief position command */ +#define ENDAT_CMDTYP_POSITION (0x1 << 1) +/** \brief command belongs to EnDat 2.2 command set */ +#define ENDAT_CMDTYP_ENDAT22 (0x1 << 2) +/** \brief 2.2 position command with additional info 1 */ +#define ENDAT_CMDTYP_HAS_ADDINFO1 (0x1 << 3) +/** \brief 2.2 position command with additional info 2 */ +#define ENDAT_CMDTYP_HAS_ADDINFO2 (0x1 << 4) + +/** \brief position/data CRC status mask */ +#define ENDAT_CRC_DATA (0x1 << 0) +/** \brief additional info 1/2 CRC status mask (if either one present)
+ if both present, indicates additional info 2 CRC status mask */ +#define ENDAT_CRC_ADDINFOX (0x1 << 1) +/** \brief additional info 1 CRC status mask (if both present) */ +#define ENDAT_CRC_ADDINFO1 (0x1 << 2) + +/* ========================================================================== */ +/* Structures */ +/* ========================================================================== */ + +/** + * \brief Structure defining per channel CRC information + * + * \details Firmware per channel CRC information interface + */ +struct crc +{ + volatile uint8_t status; + /**< CRC status, + bit0: 1 - position/data success, 0 - position/data failure
+ bit1: 1 - additional info1 success, 0 - additioanl info1 failure
+ bit2: 1 - additional info2 success, 0 - additioanl info2 failure */ + volatile uint8_t err_cnt_data; + /**< CRC position/data error count (will wraparound after 255) */ + volatile uint8_t err_cnt_addinfox; + /**< CRC additional info1/2 error count (will wraparound after 255) */ + volatile uint8_t err_cnt_addinfo1; + /**< CRC additional info1 error count (will wraparound after 255)
+ applicable only when both additional info's are present */ +}; + +/** + * \brief Structure defining EnDat per channel interface + * + * \details Firmware per channel interface + */ +struct endat_pruss_ch_info +{ + volatile uint32_t pos_word0; + /**< Initial (<=32) position bits received including error bits */ + volatile uint32_t pos_word1; + /**< position bits received after the initial 32 bits (if applicable) */ + volatile uint32_t pos_word2; + /**< additional info 1/2 (will be additional info 2 if both present) */ + volatile uint32_t pos_word3; + /**< additional info 1 (if both additional 1 & 2 present) */ + struct crc crc; + /**< crc information */ + volatile uint8_t num_clk_pulse; + /**< position bits excluding SB, error, CRC (updated upon initialization) */ + volatile uint8_t endat22_stat; + /**< encoder command set type, 1 - 2.2 supported, 0 - 2.2 not supported */ + volatile uint16_t rx_clk_less; + /**< receive clocks to be reduced to handle propagation delay (to be
+ updated by host, if applicable) */ + volatile uint32_t prop_delay; + /**< automatically estimated propagation delay */ + volatile uint32_t resvd_int0; + /**< reserved */ +}; + +/** + * \brief Structure defining EnDat command interface + * + * \details Firmware command interface + */ +struct endat_pruss_cmd +{ + volatile uint32_t word0; + /**< command,
+ [Byte 0] bit 7: 0(dummy), bit 6-1: command, bit 0: address bit 7
+ [Byte 1] bit 7-1: address bit 6-0, bit 0: parameter bit 15
+ [Byte 2] bit 7-0: parameter bit 14-7
+ [Byte 2] bit 7-1: parameter bit 6-0, bit 0: 0(dummy) */ + volatile uint32_t word1; + /**< command parameters,
+ [Byte 0] receive bits, includes SB & dummy (for additional info) for PRU
+ [Byte 1] transmit bit
+ [Byte 2] attributes,
+ bit0: 1 - no command supplement, 0 - command supplement present
+ bit1: 1 - position command, 0 - not position command
+ bit2: 1 - EnDat 2.2 command, 0 - EnDat 2.1 command
+ bit3: 1 - additional info1 present, 0 - no additional info1
+ bit4: 1 - additional info2 present, 0 - no additional info2
+ [Byte 3] 1 - block address selected, 0 - block address not selected */ + volatile uint32_t word2; + /**< command supplement,
+ [Byte 0] address
+ [Byte 1] parameter MSByte
+ [Byte 2] parameter LSByte
+ [Byte 3] block address */ + +}; + +/** + * \brief Structure defining EnDat configuration interface + * + * \details Firmware configuration interface + */ +struct endat_pruss_config +{ + volatile uint8_t opmode; + /**< operation mode selection: 0 - periodic trigger, 1 - host trigger */ + volatile uint8_t channel; + /**< channel mask (1 << channel), 0 < channel < 3. This has to be
+ selected before running firmware. Once initialization is complete,
+ it will reflect the detected channels in the selected mask.
+ Multichannel can have upto 3 selected, while single channel only one */ + volatile uint8_t trigger; + /**< command trigger. Set LSB to send cmd, will be cleared upon cmd
+ completion. Set/clear MSB to start/stop continuous clock mode.
+ To start continuous mode LSB also has to be set. Note that cmd
+ has to be setup before trigger */ + volatile uint8_t status; + /**< initialization status: 1 - upon successful. Wait around 5 seconds
+ after firmware has started running to confirm status */ +}; + +/** + * \brief Structure defining EnDat interface + * + * \details Firmware config, command and channel interface + * + */ +struct endat_pruss_xchg +{ + struct endat_pruss_config config[3]; + /**< config interface */ + struct endat_pruss_cmd cmd[3]; + /**< command interface */ + struct endat_pruss_ch_info ch[3]; + /**< per channel interface */ + uint16_t endat_rx_clk_config; + uint16_t endat_tx_clk_config; + uint32_t endat_rx_clk_cnten; + uint32_t endat_delay_125ns; + uint32_t endat_delay_5us; + uint32_t endat_delay_51us; + uint32_t endat_delay_1ms; + uint32_t endat_delay_2ms; + uint32_t endat_delay_12ms; + uint32_t endat_delay_50ms; + uint32_t endat_delay_380ms; + uint32_t endat_delay_900ms; + volatile uint8_t endat_primary_core_mask; + volatile uint8_t endat_ch0_syn_bit; + volatile uint8_t endat_ch1_syn_bit; + volatile uint8_t endat_ch2_syn_bit; + uint32_t endat_ch0_rt; + uint32_t endat_ch1_rt; + uint32_t endat_ch2_rt; + uint64_t icssg_clk; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/motor_control/position_sense/endat/makefile.am243x.r5f.ti-arm-clang b/source/motor_control/position_sense/endat/makefile.am243x.r5f.ti-arm-clang new file mode 100644 index 0000000..81e35b6 --- /dev/null +++ b/source/motor_control/position_sense/endat/makefile.am243x.r5f.ti-arm-clang @@ -0,0 +1,119 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang +AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar + +PROFILE?=release +ConfigName:=$(PROFILE) + +LIBNAME:=motorcontrol_endat.am243x.r5f.ti-arm-clang.$(PROFILE).lib + +FILES_common := \ + endat_drv.c \ + +FILES_PATH_common = \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/driver \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/include \ + +DEFINES_common := \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +ARFLAGS_common := \ + rc \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ifeq ($(CPLUSPLUS_BUILD), yes) +CFLAGS += $(CFLAGS_cpp_common) +endif +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE)) + +LIBDIR := lib +OBJDIR := obj/am243x/ti-arm-clang/$(PROFILE)/r5f/motorcontrol_endat/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $< + +all: $(LIBDIR)/$(LIBNAME) + +$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR) + @echo . + @echo Archiving: $(LIBNAME) to $@ ... + $(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS)) + @echo Archiving: $(LIBNAME) Done !!! + @echo . + +clean: + @echo Cleaning: $(LIBNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(LIBDIR)/$(LIBNAME) + +scrub: + @echo Scrubing: $(LIBNAME) ... + -$(RMDIR) obj/ + -$(RMDIR) lib/ + +$(OBJS): | $(OBJDIR) + +$(LIBDIR) $(OBJDIR): + $(MKDIR) $@ + +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/source/motor_control/position_sense/endat/makefile.am64x.r5f.ti-arm-clang b/source/motor_control/position_sense/endat/makefile.am64x.r5f.ti-arm-clang new file mode 100644 index 0000000..1380eac --- /dev/null +++ b/source/motor_control/position_sense/endat/makefile.am64x.r5f.ti-arm-clang @@ -0,0 +1,119 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang +AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar + +PROFILE?=release +ConfigName:=$(PROFILE) + +LIBNAME:=motorcontrol_endat.am64x.r5f.ti-arm-clang.$(PROFILE).lib + +FILES_common := \ + endat_drv.c \ + +FILES_PATH_common = \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/driver \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/endat/include \ + +DEFINES_common := \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +ARFLAGS_common := \ + rc \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ifeq ($(CPLUSPLUS_BUILD), yes) +CFLAGS += $(CFLAGS_cpp_common) +endif +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE)) + +LIBDIR := lib +OBJDIR := obj/am64x/ti-arm-clang/$(PROFILE)/r5f/motorcontrol_endat/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $< + +all: $(LIBDIR)/$(LIBNAME) + +$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR) + @echo . + @echo Archiving: $(LIBNAME) to $@ ... + $(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS)) + @echo Archiving: $(LIBNAME) Done !!! + @echo . + +clean: + @echo Cleaning: $(LIBNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(LIBDIR)/$(LIBNAME) + +scrub: + @echo Scrubing: $(LIBNAME) ... + -$(RMDIR) obj/ + -$(RMDIR) lib/ + +$(OBJS): | $(OBJDIR) + +$(LIBDIR) $(OBJDIR): + $(MKDIR) $@ + +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/source/motor_control/position_sense/hdsl/.project/project.js b/source/motor_control/position_sense/hdsl/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/.project/project_am243x.js b/source/motor_control/position_sense/hdsl/.project/project_am243x.js new file mode 100644 index 0000000..f4485e4 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/.project/project_am243x.js @@ -0,0 +1,55 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "hdsl_drv.c", + "hdsl_lut.c", + ], +}; + +const filedirs = { + common: [ + "driver", + //"${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/driver", + ], +}; + +const includes = { + common: [ + "include", + //"${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/include", + ], +}; + +const buildOptionCombos = [ + { device: device, cpu: "r5f", cgt: "ti-arm-clang"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "library"; + property.name = "motorcontrol_hdsl"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/.project/project_am64x.js b/source/motor_control/position_sense/hdsl/.project/project_am64x.js new file mode 100644 index 0000000..a4760c9 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/.project/project_am64x.js @@ -0,0 +1,56 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "hdsl_drv.c", + "hdsl_lut.c", + ], +}; + +const filedirs = { + common: [ + "driver", + // "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/driver", + ], +}; + +const includes = { + common: [ + "include", + // "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/include", + ], +}; + +const buildOptionCombos = [ + { device: device, cpu: "r5f", cgt: "ti-arm-clang"}, + // { device: device, cpu: "r5f", cgt: "gcc-armv7"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "library"; + property.name = "motorcontrol_hdsl"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/driver/hdsl_drv.c b/source/motor_control/position_sense/hdsl/driver/hdsl_drv.c new file mode 100644 index 0000000..b6901d1 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/driver/hdsl_drv.c @@ -0,0 +1,423 @@ +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* Should move the below to sysconfig generated code */ + HDSL_Config hdslConfig0; + HDSL_Config hdslConfig1; + HDSL_Config hdslConfig2; + +void hdsl_enable_load_share_mode(void *gPru_cfg ,uint32_t PRU_SLICE) +{ + //HW_WR_REG32(0x30026104) |= 0x0800; + uint32_t rgval; + if(PRU_SLICE==1) + { + rgval = HW_RD_REG32((uint8_t *)gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER); + rgval |= CSL_ICSSCFG_EDPRU1TXCFGREGISTER_PRU1_ENDAT_SHARE_EN_MASK; + HW_WR_REG32((uint8_t *)gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, rgval); + } + else + { + rgval = HW_RD_REG32((uint8_t *)gPru_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER); + rgval |= CSL_ICSSCFG_EDPRU0TXCFGREGISTER_PRU0_ENDAT_SHARE_EN_MASK; + HW_WR_REG32((uint8_t *)gPru_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER, rgval); + } + +} +HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore,uint8_t PRU_mode) +{ + /* + HDSL memory map: + RTU_PRU core: 0x0000 - 0x06FF + PRU core: 0x0700 - 0x0DFF + TX_PRU core: 0x0E00 - 0x1500 + */ + uint32_t DMEM_BASE_OFFSET_RTU_PRU1=0; + uint32_t DMEM_BASE_OFFSET_PRU1=0x700; + uint32_t DMEM_BASE_OFFSET_TX_PRU1=0xE00; + HDSL_Handle hdslHandle; + if (PRU_mode==0) + { + hdslHandle = &hdslConfig0; + hdslHandle->baseMemAddr = (uint32_t *)(((PRUICSS_HwAttrs *)(icssgHandle->hwAttrs))->pru1DramBase); + } + else + { + if(icssCore == PRUICSS_RTU_PRU1) + { + hdslHandle = &hdslConfig0; + hdslHandle->baseMemAddr = (uint32_t *)((((PRUICSS_HwAttrs *)(icssgHandle->hwAttrs))->pru1DramBase)+DMEM_BASE_OFFSET_RTU_PRU1); + } + else if(icssCore == PRUICSS_PRU1) + { + hdslHandle = &hdslConfig1; + hdslHandle->baseMemAddr = (uint32_t *)((((PRUICSS_HwAttrs *)(icssgHandle->hwAttrs))->pru1DramBase) + DMEM_BASE_OFFSET_PRU1); + } + else if(icssCore == PRUICSS_TX_PRU1) + { + hdslHandle = &hdslConfig2; + hdslHandle->baseMemAddr = (uint32_t *)((((PRUICSS_HwAttrs *)(icssgHandle->hwAttrs))->pru1DramBase) + DMEM_BASE_OFFSET_TX_PRU1); + } + else + { + hdslHandle = NULL; + } + } + + if (hdslHandle != NULL) + { + hdslHandle->icssgHandle = icssgHandle; + hdslHandle->icssCore = icssCore; + hdslHandle->hdslInterface = (HDSL_Interface *) hdslHandle->baseMemAddr; + hdslHandle->multi_turn = 0; + } + + return hdslHandle; +} + +void HDSL_iep_init(HDSL_Handle hdslHandle) +{ + HW_WR_REG32((uint32_t)(((PRUICSS_HwAttrs *)(hdslHandle->icssgHandle->hwAttrs))->iep0RegBase) + CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG, + (CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG_CNT_ENABLE_MASK | (1 << CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG_DEFAULT_INC_SHIFT))); + /* Use OCP as IEP CLK src */ + HW_WR_REG32((uint32_t)(((PRUICSS_HwAttrs *)(hdslHandle->icssgHandle->hwAttrs))->cfgRegBase) + CSL_ICSSCFG_IEPCLK, CSL_ICSSCFG_IEPCLK_OCP_EN_MASK); +} + +int HDSL_enable_sync_signal(uint8_t ES, uint32_t period) +{ + /*program here*/ + uint32_t start_time = 10000; + + uint32_t inEvent; + uint32_t outEvent_latch; + uint32_t outEvent_gpio; + uint32_t iep_base = CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE; + + /*Enable IEP. Enable the Counter and set the DEFAULT_INC and CMP_INC to 1.*/ + HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG) = 0x111; + + /*Enable SYNC0 and program pulse width*/ + /*Enable SYNC and SYNC0*/ + HWREG(iep_base + CSL_ICSS_G_PR1_IEP1_SLV_SYNC_CTRL_REG) |= 0x03; + /*Enable cyclic mod*/ + HWREG(iep_base + CSL_ICSS_G_PR1_IEP1_SLV_SYNC_CTRL_REG) |= 0x20; + /*32504 4500 = num_of_cycles, 50Khz signals, 20us time period//(pulse_width / 4) - 1; */ + HWREG(iep_base + CSL_ICSS_G_PR1_IEP1_SLV_SYNC_PWIDTH_REG) = (period)/2; + /* (period / 4) - 1; */ + HWREG(iep_base + CSL_ICSS_G_PR1_IEP1_SLV_SYNC0_PERIOD_REG) =(period); + + /*Program CMP1*/ + HWREG(iep_base + CSL_ICSS_G_PR1_IEP1_SLV_CMP_CFG_REG) |= 0x00000004; + /*; Ensure this start time is in future*/ + HWREG(iep_base + CSL_ICSS_G_PR1_IEP1_SLV_CMP1_REG0) = start_time; + + /*TSR configuration:*/ + inEvent = SYNCEVENT_INTRTR_IN_27; + outEvent_latch = SYNCEVT_RTR_SYNC10_EVT; + outEvent_gpio = SYNCEVT_RTR_SYNC30_EVT; + + HWREG(CSL_TIMESYNC_EVENT_INTROUTER0_CFG_BASE + outEvent_latch) = inEvent | 0x10000; + HWREG(CSL_TIMESYNC_EVENT_INTROUTER0_CFG_BASE + outEvent_gpio) = inEvent | 0x10000; + HWREG(CSL_TIMESYNC_EVENT_INTROUTER0_CFG_BASE + SYNCEVT_RTR_SYNC28_EVT) = inEvent | 0x10000; + + return 1; +} + +uint64_t HDSL_get_pos(HDSL_Handle hdslHandle, int position_id) +{ + uint64_t val; + HDSL_Interface *hdslInterfaceStruct = hdslHandle->hdslInterface; + switch(position_id){ + case 0: + /* Fast Position */ + val = hdslInterfaceStruct->POS0 | (hdslInterfaceStruct->POS1 << 8) | + (hdslInterfaceStruct->POS2 << 16) | (hdslInterfaceStruct->POS3 << 24); + val |= (uint64_t)hdslInterfaceStruct->POS4 << 32; + return val; + + break; + + case 1: + /* Safe Position 1 */ + val = hdslInterfaceStruct->VPOS0 | (hdslInterfaceStruct->VPOS1 << 8) | + (hdslInterfaceStruct->VPOS2 << 16) | (hdslInterfaceStruct->VPOS3 << 24); + val |= (uint64_t)hdslInterfaceStruct->VPOS4 << 32; + return val; + + break; + + case 2: + /* Safe Position 2 */ + val = hdslInterfaceStruct->VPOS20 | (hdslInterfaceStruct->VPOS21 << 8) | + (hdslInterfaceStruct->VPOS22 << 16) | (hdslInterfaceStruct->VPOS23 << 24); + val |= (uint64_t)hdslInterfaceStruct->VPOS24 << 32; + + return val; + break; + + default: + return -1; + } +} + +uint8_t HDSL_get_qm(HDSL_Handle hdslHandle) +{ + uint8_t ureg = hdslHandle->hdslInterface->MASTER_QM & 0xF; + return ureg; +} + + +uint16_t HDSL_get_events(HDSL_Handle hdslHandle) +{ + uint16_t ureg = hdslHandle->hdslInterface->EVENT_L | (hdslHandle->hdslInterface->EVENT_H << 8); + return ureg; +} + +uint8_t HDSL_get_safe_events(HDSL_Handle hdslHandle) +{ + return hdslHandle->hdslInterface->EVENT_S; +} + +uint16_t HDSL_get_online_status_d(HDSL_Handle hdslHandle) +{ + uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_D; + return ureg; +} + +uint16_t HDSL_get_online_status_1(HDSL_Handle hdslHandle) +{ + uint16_t ureg =hdslHandle->hdslInterface->ONLINE_STATUS_1; + return ureg; +} + +uint16_t HDSL_get_online_status_2(HDSL_Handle hdslHandle) +{ + uint16_t ureg = hdslHandle->hdslInterface->ONLINE_STATUS_2; + return ureg; +} +uint8_t HDSL_get_sum(HDSL_Handle hdslHandle) +{ + uint8_t ureg = hdslHandle->hdslInterface->SAFE_SUM; + return ureg; +} + + +uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle) +{ + return (uint8_t) (hdslHandle->hdslInterface->ACC_ERR_CNT & 0x1F); +} + +uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle) +{ + uint8_t ureg = (hdslHandle->hdslInterface->DELAY & 0xF0) >> 4; + return ureg; +} + +int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t data, uint64_t timeout) +{ + uint64_t end; + end = ClockP_getTimeUsec() + timeout; + + while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + { + if(ClockP_getTimeUsec() > end) + { + return SystemP_TIMEOUT; + } + } + hdslHandle->hdslInterface->S_PC_DATA = data; + hdslHandle->hdslInterface->SLAVE_REG_CTRL = addr; + while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 0) + { + if(ClockP_getTimeUsec() > end) + { + return SystemP_TIMEOUT; + } + } + while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + { + if(ClockP_getTimeUsec() > end) + { + return SystemP_TIMEOUT; + } + } + return SystemP_SUCCESS; +} + +int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *data, uint64_t timeout) +{ + + uint64_t end; + end = ClockP_getTimeUsec() + timeout; + + while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + { + if(ClockP_getTimeUsec() > end) + { + return SystemP_TIMEOUT; + } + } + hdslHandle->hdslInterface->S_PC_DATA = 0; + hdslHandle->hdslInterface->SLAVE_REG_CTRL = (addr | (1<<7)); + while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 0) + { + if(ClockP_getTimeUsec() > end) + { + return SystemP_TIMEOUT; + } + } + while((hdslHandle->hdslInterface->EVENT_S & 0x1) != 1) + { + if(ClockP_getTimeUsec() > end) + { + return SystemP_TIMEOUT; + } + } + *data = hdslHandle->hdslInterface->S_PC_DATA; + return SystemP_SUCCESS; +} + +uint8_t HDSL_read_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off) +{ + switch(buff_off) + { + case 0: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER0); + break; + case 1: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER1); + break; + case 2: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER2); + break; + case 3: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER3); + break; + case 4: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER4); + break; + case 5: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER5); + break; + case 6: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER6); + break; + case 7: + return (uint8_t) (hdslHandle->hdslInterface->PC_BUFFER7); + break; + default: + return 0; + break; + } +} + +void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t pc_buf0, uint8_t pc_buf1, uint8_t pc_buf2, uint8_t pc_buf3, uint8_t pc_buf4, uint8_t pc_buf5, uint8_t pc_buf6, uint8_t pc_buf7) +{ + hdslHandle->hdslInterface->PC_BUFFER0 = pc_buf0; + hdslHandle->hdslInterface->PC_BUFFER1 = pc_buf1; + hdslHandle->hdslInterface->PC_BUFFER2 = pc_buf2; + hdslHandle->hdslInterface->PC_BUFFER3 = pc_buf3; + hdslHandle->hdslInterface->PC_BUFFER4 = pc_buf4; + hdslHandle->hdslInterface->PC_BUFFER5 = pc_buf5; + hdslHandle->hdslInterface->PC_BUFFER6 = pc_buf6; + hdslHandle->hdslInterface->PC_BUFFER7 = pc_buf7; +} + +uint8_t HDSL_get_sync_ctrl(HDSL_Handle hdslHandle) +{ + return (uint8_t) (hdslHandle->hdslInterface->SYNC_CTRL); +} + +void HDSL_set_sync_ctrl(HDSL_Handle hdslHandle, uint8_t val) +{ + hdslHandle->hdslInterface->SYNC_CTRL = val; +} + +uint8_t HDSL_get_master_qm(HDSL_Handle hdslHandle) +{ + return (uint8_t) hdslHandle->hdslInterface->MASTER_QM; +} + +uint8_t HDSL_get_edges(HDSL_Handle hdslHandle) +{ + return (uint8_t) hdslHandle->hdslInterface->EDGES; +} + +void HDSL_set_pc_addr(HDSL_Handle hdslHandle, uint8_t pc_addrh, uint8_t pc_addrl, uint8_t pc_offh, uint8_t pc_offl) +{ + hdslHandle->hdslInterface->PC_ADD_L = pc_addrl; + hdslHandle->hdslInterface->PC_ADD_H = pc_addrh; + + hdslHandle->hdslInterface->PC_OFF_L = pc_offl; + hdslHandle->hdslInterface->PC_OFF_H = pc_offh; +} + +void HDSL_set_pc_ctrl(HDSL_Handle hdslHandle, uint8_t value) +{ + hdslHandle->hdslInterface->PC_CTRL = value; +} + +uint8_t HDSL_get_delay(HDSL_Handle hdslHandle) +{ + return (uint8_t) hdslHandle->hdslInterface->DELAY; +} + +uint8_t HDSL_get_enc_id(HDSL_Handle hdslHandle, int byte) +{ + switch(byte) + { + case 0: + return (uint8_t) hdslHandle->hdslInterface->ENC_ID0; + case 1: + return (uint8_t) hdslHandle->hdslInterface->ENC_ID1; + case 2: + return (uint8_t) hdslHandle->hdslInterface->ENC_ID2; + default: + return -1; + } +} + +void* HDSL_get_src_loc(HDSL_Handle hdslHandle) +{ + /* returns HDSL interface struct memory location */ + return (void *)hdslHandle->hdslInterface; +} + +uint32_t HDSL_get_length(HDSL_Handle hdslHandle) +{ + return sizeof(*(hdslHandle->hdslInterface)); +} + diff --git a/source/motor_control/position_sense/hdsl/driver/hdsl_lut.c b/source/motor_control/position_sense/hdsl/driver/hdsl_lut.c new file mode 100644 index 0000000..6208ffc --- /dev/null +++ b/source/motor_control/position_sense/hdsl/driver/hdsl_lut.c @@ -0,0 +1,1304 @@ +/* + * Copyright (C) 2021-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#define ENC_5B6B_OFFS 0x100 +#define ENC_3B4B_OFFS 0x160 +#define DEC_5B6B_OFFS 0x120 +#define DEC_3B4B_OFFS 0x168 +#define BITCNT_OFFS 0x178 +#define LUT_CRC5_OFFS 0x478 +#define LUT_CRC16_OFFS 0x278 +#define LUT_BITTOBYTE_OFFS 0x5A4 +#define LUT_RSSI_OFFS 0x5E4 +#define LUT_EE_OFFS (0x5E4 + 256) + +static void hdsl_enc_dec_lut(HDSL_Handle hdslHandle) +{ +#define INVAL 0xFF + + void *enc_5b6b = (void *)((uint32_t)(hdslHandle->baseMemAddr) + ENC_5B6B_OFFS); + void *enc_3b4b = (void *)((uint32_t)(hdslHandle->baseMemAddr) + ENC_3B4B_OFFS); + void *dec_5b6b = (void *)((uint32_t)(hdslHandle->baseMemAddr) + DEC_5B6B_OFFS); + void *dec_3b4b = (void *)((uint32_t)(hdslHandle->baseMemAddr) + DEC_3B4B_OFFS); + + // Encoding LUTs (input MSB first, output LSB first) + // LUT 5b/6b encoding + HW_WR_REG8((uint32_t)enc_5b6b + 0x00, 0x18); + HW_WR_REG8((uint32_t)enc_5b6b + 0x01, 0x22); + HW_WR_REG8((uint32_t)enc_5b6b + 0x02, 0x12); + HW_WR_REG8((uint32_t)enc_5b6b + 0x03, 0x31); + HW_WR_REG8((uint32_t)enc_5b6b + 0x04, 0x0a); + HW_WR_REG8((uint32_t)enc_5b6b + 0x05, 0x29); + HW_WR_REG8((uint32_t)enc_5b6b + 0x06, 0x19); + HW_WR_REG8((uint32_t)enc_5b6b + 0x07, 0x07); + HW_WR_REG8((uint32_t)enc_5b6b + 0x08, 0x06); + HW_WR_REG8((uint32_t)enc_5b6b + 0x09, 0x25); + HW_WR_REG8((uint32_t)enc_5b6b + 0x0a, 0x15); + HW_WR_REG8((uint32_t)enc_5b6b + 0x0b, 0x34); + HW_WR_REG8((uint32_t)enc_5b6b + 0x0c, 0x0d); + HW_WR_REG8((uint32_t)enc_5b6b + 0x0d, 0x2c); + HW_WR_REG8((uint32_t)enc_5b6b + 0x0e, 0x1c); + HW_WR_REG8((uint32_t)enc_5b6b + 0x0f, 0x28); + HW_WR_REG8((uint32_t)enc_5b6b + 0x10, 0x24); + HW_WR_REG8((uint32_t)enc_5b6b + 0x11, 0x23); + HW_WR_REG8((uint32_t)enc_5b6b + 0x12, 0x13); + HW_WR_REG8((uint32_t)enc_5b6b + 0x13, 0x32); + HW_WR_REG8((uint32_t)enc_5b6b + 0x14, 0x0b); + HW_WR_REG8((uint32_t)enc_5b6b + 0x15, 0x2a); + HW_WR_REG8((uint32_t)enc_5b6b + 0x16, 0x1a); + HW_WR_REG8((uint32_t)enc_5b6b + 0x17, 0x05); + HW_WR_REG8((uint32_t)enc_5b6b + 0x18, 0x0c); + HW_WR_REG8((uint32_t)enc_5b6b + 0x19, 0x26); + HW_WR_REG8((uint32_t)enc_5b6b + 0x1a, 0x16); + HW_WR_REG8((uint32_t)enc_5b6b + 0x1b, 0x09); + HW_WR_REG8((uint32_t)enc_5b6b + 0x1c, 0x30); + HW_WR_REG8((uint32_t)enc_5b6b + 0x1d, 0x11); + HW_WR_REG8((uint32_t)enc_5b6b + 0x1e, 0x21); + HW_WR_REG8((uint32_t)enc_5b6b + 0x1f, 0x14); + + // LUT 3b/4b encoding + HW_WR_REG8((uint32_t)enc_3b4b + 0x00, 0x04); + HW_WR_REG8((uint32_t)enc_3b4b + 0x01, 0x09); + HW_WR_REG8((uint32_t)enc_3b4b + 0x02, 0x05); + HW_WR_REG8((uint32_t)enc_3b4b + 0x03, 0x03); + HW_WR_REG8((uint32_t)enc_3b4b + 0x04, 0x02); + HW_WR_REG8((uint32_t)enc_3b4b + 0x05, 0x0a); + HW_WR_REG8((uint32_t)enc_3b4b + 0x06, 0x06); + HW_WR_REG8((uint32_t)enc_3b4b + 0x07, 0x01); + + // input is with LSB first, output is MSB first + HW_WR_REG8((uint32_t)dec_5b6b + 0x00, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x01, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x02, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x03, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x04, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x05, 0x17); + HW_WR_REG8((uint32_t)dec_5b6b + 0x06, 0x08); + HW_WR_REG8((uint32_t)dec_5b6b + 0x07, 0x07); + HW_WR_REG8((uint32_t)dec_5b6b + 0x08, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x09, 0x1b); + HW_WR_REG8((uint32_t)dec_5b6b + 0x0a, 0x04); + HW_WR_REG8((uint32_t)dec_5b6b + 0x0b, 0x14); + HW_WR_REG8((uint32_t)dec_5b6b + 0x0c, 0x18); + HW_WR_REG8((uint32_t)dec_5b6b + 0x0d, 0x0c); + HW_WR_REG8((uint32_t)dec_5b6b + 0x0e, 0x1c); + HW_WR_REG8((uint32_t)dec_5b6b + 0x0f, 0x1c); + HW_WR_REG8((uint32_t)dec_5b6b + 0x10, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x11, 0x1d); + HW_WR_REG8((uint32_t)dec_5b6b + 0x12, 0x02); + HW_WR_REG8((uint32_t)dec_5b6b + 0x13, 0x12); + HW_WR_REG8((uint32_t)dec_5b6b + 0x14, 0x1f); + HW_WR_REG8((uint32_t)dec_5b6b + 0x15, 0x0a); + HW_WR_REG8((uint32_t)dec_5b6b + 0x16, 0x1a); + HW_WR_REG8((uint32_t)dec_5b6b + 0x17, 0x0f); + HW_WR_REG8((uint32_t)dec_5b6b + 0x18, 0x00); + HW_WR_REG8((uint32_t)dec_5b6b + 0x19, 0x06); + HW_WR_REG8((uint32_t)dec_5b6b + 0x1a, 0x16); + HW_WR_REG8((uint32_t)dec_5b6b + 0x1b, 0x10); + HW_WR_REG8((uint32_t)dec_5b6b + 0x1c, 0x0e); + HW_WR_REG8((uint32_t)dec_5b6b + 0x1d, 0x01); + HW_WR_REG8((uint32_t)dec_5b6b + 0x1e, 0x1e); + HW_WR_REG8((uint32_t)dec_5b6b + 0x1f, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x20, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x21, 0x1e); + HW_WR_REG8((uint32_t)dec_5b6b + 0x22, 0x01); + HW_WR_REG8((uint32_t)dec_5b6b + 0x23, 0x11); + HW_WR_REG8((uint32_t)dec_5b6b + 0x24, 0x10); + HW_WR_REG8((uint32_t)dec_5b6b + 0x25, 0x09); + HW_WR_REG8((uint32_t)dec_5b6b + 0x26, 0x19); + HW_WR_REG8((uint32_t)dec_5b6b + 0x27, 0x00); + HW_WR_REG8((uint32_t)dec_5b6b + 0x28, 0x0f); + HW_WR_REG8((uint32_t)dec_5b6b + 0x29, 0x05); + HW_WR_REG8((uint32_t)dec_5b6b + 0x2a, 0x15); + HW_WR_REG8((uint32_t)dec_5b6b + 0x2b, 0x1f); + HW_WR_REG8((uint32_t)dec_5b6b + 0x2c, 0x0d); + HW_WR_REG8((uint32_t)dec_5b6b + 0x2d, 0x02); + HW_WR_REG8((uint32_t)dec_5b6b + 0x2e, 0x1d); + HW_WR_REG8((uint32_t)dec_5b6b + 0x2f, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x30, 0x1c); + HW_WR_REG8((uint32_t)dec_5b6b + 0x31, 0x03); + HW_WR_REG8((uint32_t)dec_5b6b + 0x32, 0x13); + HW_WR_REG8((uint32_t)dec_5b6b + 0x33, 0x18); + HW_WR_REG8((uint32_t)dec_5b6b + 0x34, 0x0b); + HW_WR_REG8((uint32_t)dec_5b6b + 0x35, 0x04); + HW_WR_REG8((uint32_t)dec_5b6b + 0x36, 0x1b); + HW_WR_REG8((uint32_t)dec_5b6b + 0x37, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x38, 0x07); + HW_WR_REG8((uint32_t)dec_5b6b + 0x39, 0x08); + HW_WR_REG8((uint32_t)dec_5b6b + 0x3a, 0x17); + HW_WR_REG8((uint32_t)dec_5b6b + 0x3b, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x3c, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x3d, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x3e, INVAL); + HW_WR_REG8((uint32_t)dec_5b6b + 0x3f, INVAL); + + // LUT 3b/4b decoding + // input is with LSB first, output is MSB first + HW_WR_REG8((uint32_t)dec_3b4b + 0x00, INVAL); + HW_WR_REG8((uint32_t)dec_3b4b + 0x01, (0x7 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x02, (0x4 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x03, (0x3 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x04, (0x0 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x05, (0x2 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x06, (0x6 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x07, (0x7 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x08, (0x7 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x09, (0x1 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x0a, (0x5 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x0b, (0x0 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x0c, (0x3 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x0d, (0x4 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x0e, (0x7 << 5)); + HW_WR_REG8((uint32_t)dec_3b4b + 0x0f, INVAL); + +} + +static void hdsl_generate_bit_cnt_lut(HDSL_Handle hdslHandle) +{ + void *bitcnt = (void *)((uint32_t)(hdslHandle->baseMemAddr) + BITCNT_OFFS); + + HW_WR_REG8((uint32_t)bitcnt + 0x0, 0); + HW_WR_REG8((uint32_t)bitcnt + 0x1, 1); + HW_WR_REG8((uint32_t)bitcnt + 0x2, 1); + HW_WR_REG8((uint32_t)bitcnt + 0x3, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x4, 1); + HW_WR_REG8((uint32_t)bitcnt + 0x5, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x6, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x7, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x8, 1); + HW_WR_REG8((uint32_t)bitcnt + 0x9, 2); + HW_WR_REG8((uint32_t)bitcnt + 0xa, 2); + HW_WR_REG8((uint32_t)bitcnt + 0xb, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xc, 2); + HW_WR_REG8((uint32_t)bitcnt + 0xd, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xe, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xf, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x10, 1); + HW_WR_REG8((uint32_t)bitcnt + 0x11, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x12, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x13, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x14, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x15, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x16, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x17, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x18, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x19, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x1a, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x1b, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x1c, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x1d, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x1e, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x1f, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x20, 1); + HW_WR_REG8((uint32_t)bitcnt + 0x21, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x22, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x23, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x24, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x25, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x26, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x27, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x28, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x29, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x2a, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x2b, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x2c, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x2d, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x2e, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x2f, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x30, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x31, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x32, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x33, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x34, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x35, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x36, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x37, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x38, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x39, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x3a, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x3b, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x3c, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x3d, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x3e, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x3f, 6); + HW_WR_REG8((uint32_t)bitcnt + 0x40, 1); + HW_WR_REG8((uint32_t)bitcnt + 0x41, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x42, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x43, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x44, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x45, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x46, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x47, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x48, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x49, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x4a, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x4b, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x4c, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x4d, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x4e, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x4f, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x50, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x51, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x52, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x53, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x54, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x55, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x56, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x57, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x58, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x59, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x5a, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x5b, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x5c, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x5d, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x5e, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x5f, 6); + HW_WR_REG8((uint32_t)bitcnt + 0x60, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x61, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x62, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x63, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x64, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x65, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x66, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x67, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x68, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x69, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x6a, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x6b, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x6c, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x6d, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x6e, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x6f, 6); + HW_WR_REG8((uint32_t)bitcnt + 0x70, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x71, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x72, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x73, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x74, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x75, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x76, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x77, 6); + HW_WR_REG8((uint32_t)bitcnt + 0x78, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x79, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x7a, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x7b, 6); + HW_WR_REG8((uint32_t)bitcnt + 0x7c, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x7d, 6); + HW_WR_REG8((uint32_t)bitcnt + 0x7e, 6); + HW_WR_REG8((uint32_t)bitcnt + 0x7f, 7); + HW_WR_REG8((uint32_t)bitcnt + 0x80, 1); + HW_WR_REG8((uint32_t)bitcnt + 0x81, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x82, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x83, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x84, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x85, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x86, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x87, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x88, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x89, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x8a, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x8b, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x8c, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x8d, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x8e, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x8f, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x90, 2); + HW_WR_REG8((uint32_t)bitcnt + 0x91, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x92, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x93, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x94, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x95, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x96, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x97, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x98, 3); + HW_WR_REG8((uint32_t)bitcnt + 0x99, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x9a, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x9b, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x9c, 4); + HW_WR_REG8((uint32_t)bitcnt + 0x9d, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x9e, 5); + HW_WR_REG8((uint32_t)bitcnt + 0x9f, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xa0, 2); + HW_WR_REG8((uint32_t)bitcnt + 0xa1, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xa2, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xa3, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xa4, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xa5, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xa6, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xa7, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xa8, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xa9, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xaa, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xab, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xac, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xad, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xae, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xaf, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xb0, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xb1, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xb2, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xb3, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xb4, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xb5, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xb6, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xb7, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xb8, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xb9, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xba, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xbb, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xbc, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xbd, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xbe, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xbf, 7); + HW_WR_REG8((uint32_t)bitcnt + 0xc0, 2); + HW_WR_REG8((uint32_t)bitcnt + 0xc1, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xc2, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xc3, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xc4, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xc5, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xc6, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xc7, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xc8, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xc9, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xca, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xcb, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xcc, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xcd, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xce, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xcf, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xd0, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xd1, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xd2, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xd3, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xd4, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xd5, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xd6, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xd7, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xd8, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xd9, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xda, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xdb, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xdc, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xdd, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xde, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xdf, 7); + HW_WR_REG8((uint32_t)bitcnt + 0xe0, 3); + HW_WR_REG8((uint32_t)bitcnt + 0xe1, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xe2, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xe3, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xe4, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xe5, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xe6, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xe7, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xe8, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xe9, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xea, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xeb, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xec, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xed, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xee, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xef, 7); + HW_WR_REG8((uint32_t)bitcnt + 0xf0, 4); + HW_WR_REG8((uint32_t)bitcnt + 0xf1, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xf2, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xf3, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xf4, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xf5, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xf6, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xf7, 7); + HW_WR_REG8((uint32_t)bitcnt + 0xf8, 5); + HW_WR_REG8((uint32_t)bitcnt + 0xf9, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xfa, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xfb, 7); + HW_WR_REG8((uint32_t)bitcnt + 0xfc, 6); + HW_WR_REG8((uint32_t)bitcnt + 0xfd, 7); + HW_WR_REG8((uint32_t)bitcnt + 0xfe, 7); + HW_WR_REG8((uint32_t)bitcnt + 0xff, 8); + +} + +static void hdsl_generate_crc5_lut(HDSL_Handle hdslHandle) +{ + void *lut_crc5 = (void *)((uint32_t)(hdslHandle->baseMemAddr) + LUT_CRC5_OFFS); + + HW_WR_REG8((uint32_t)lut_crc5 + 0x0, 0x0); + HW_WR_REG8((uint32_t)lut_crc5 + 0x1, 0x5); + HW_WR_REG8((uint32_t)lut_crc5 + 0x2, 0xa); + HW_WR_REG8((uint32_t)lut_crc5 + 0x3, 0xf); + HW_WR_REG8((uint32_t)lut_crc5 + 0x4, 0x14); + HW_WR_REG8((uint32_t)lut_crc5 + 0x5, 0x11); + HW_WR_REG8((uint32_t)lut_crc5 + 0x6, 0x1e); + HW_WR_REG8((uint32_t)lut_crc5 + 0x7, 0x1b); + HW_WR_REG8((uint32_t)lut_crc5 + 0x8, 0xd); + HW_WR_REG8((uint32_t)lut_crc5 + 0x9, 0x8); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa, 0x7); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb, 0x2); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc, 0x19); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd, 0x1c); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe, 0x13); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf, 0x16); + HW_WR_REG8((uint32_t)lut_crc5 + 0x10, 0x1a); + HW_WR_REG8((uint32_t)lut_crc5 + 0x11, 0x1f); + HW_WR_REG8((uint32_t)lut_crc5 + 0x12, 0x10); + HW_WR_REG8((uint32_t)lut_crc5 + 0x13, 0x15); + HW_WR_REG8((uint32_t)lut_crc5 + 0x14, 0xe); + HW_WR_REG8((uint32_t)lut_crc5 + 0x15, 0xb); + HW_WR_REG8((uint32_t)lut_crc5 + 0x16, 0x4); + HW_WR_REG8((uint32_t)lut_crc5 + 0x17, 0x1); + HW_WR_REG8((uint32_t)lut_crc5 + 0x18, 0x17); + HW_WR_REG8((uint32_t)lut_crc5 + 0x19, 0x12); + HW_WR_REG8((uint32_t)lut_crc5 + 0x1a, 0x1d); + HW_WR_REG8((uint32_t)lut_crc5 + 0x1b, 0x18); + HW_WR_REG8((uint32_t)lut_crc5 + 0x1c, 0x3); + HW_WR_REG8((uint32_t)lut_crc5 + 0x1d, 0x6); + HW_WR_REG8((uint32_t)lut_crc5 + 0x1e, 0x9); + HW_WR_REG8((uint32_t)lut_crc5 + 0x1f, 0xc); + HW_WR_REG8((uint32_t)lut_crc5 + 0x20, 0x11); + HW_WR_REG8((uint32_t)lut_crc5 + 0x21, 0x14); + HW_WR_REG8((uint32_t)lut_crc5 + 0x22, 0x1b); + HW_WR_REG8((uint32_t)lut_crc5 + 0x23, 0x1e); + HW_WR_REG8((uint32_t)lut_crc5 + 0x24, 0x5); + HW_WR_REG8((uint32_t)lut_crc5 + 0x25, 0x0); + HW_WR_REG8((uint32_t)lut_crc5 + 0x26, 0xf); + HW_WR_REG8((uint32_t)lut_crc5 + 0x27, 0xa); + HW_WR_REG8((uint32_t)lut_crc5 + 0x28, 0x1c); + HW_WR_REG8((uint32_t)lut_crc5 + 0x29, 0x19); + HW_WR_REG8((uint32_t)lut_crc5 + 0x2a, 0x16); + HW_WR_REG8((uint32_t)lut_crc5 + 0x2b, 0x13); + HW_WR_REG8((uint32_t)lut_crc5 + 0x2c, 0x8); + HW_WR_REG8((uint32_t)lut_crc5 + 0x2d, 0xd); + HW_WR_REG8((uint32_t)lut_crc5 + 0x2e, 0x2); + HW_WR_REG8((uint32_t)lut_crc5 + 0x2f, 0x7); + HW_WR_REG8((uint32_t)lut_crc5 + 0x30, 0xb); + HW_WR_REG8((uint32_t)lut_crc5 + 0x31, 0xe); + HW_WR_REG8((uint32_t)lut_crc5 + 0x32, 0x1); + HW_WR_REG8((uint32_t)lut_crc5 + 0x33, 0x4); + HW_WR_REG8((uint32_t)lut_crc5 + 0x34, 0x1f); + HW_WR_REG8((uint32_t)lut_crc5 + 0x35, 0x1a); + HW_WR_REG8((uint32_t)lut_crc5 + 0x36, 0x15); + HW_WR_REG8((uint32_t)lut_crc5 + 0x37, 0x10); + HW_WR_REG8((uint32_t)lut_crc5 + 0x38, 0x6); + HW_WR_REG8((uint32_t)lut_crc5 + 0x39, 0x3); + HW_WR_REG8((uint32_t)lut_crc5 + 0x3a, 0xc); + HW_WR_REG8((uint32_t)lut_crc5 + 0x3b, 0x9); + HW_WR_REG8((uint32_t)lut_crc5 + 0x3c, 0x12); + HW_WR_REG8((uint32_t)lut_crc5 + 0x3d, 0x17); + HW_WR_REG8((uint32_t)lut_crc5 + 0x3e, 0x18); + HW_WR_REG8((uint32_t)lut_crc5 + 0x3f, 0x1d); + HW_WR_REG8((uint32_t)lut_crc5 + 0x40, 0x7); + HW_WR_REG8((uint32_t)lut_crc5 + 0x41, 0x2); + HW_WR_REG8((uint32_t)lut_crc5 + 0x42, 0xd); + HW_WR_REG8((uint32_t)lut_crc5 + 0x43, 0x8); + HW_WR_REG8((uint32_t)lut_crc5 + 0x44, 0x13); + HW_WR_REG8((uint32_t)lut_crc5 + 0x45, 0x16); + HW_WR_REG8((uint32_t)lut_crc5 + 0x46, 0x19); + HW_WR_REG8((uint32_t)lut_crc5 + 0x47, 0x1c); + HW_WR_REG8((uint32_t)lut_crc5 + 0x48, 0xa); + HW_WR_REG8((uint32_t)lut_crc5 + 0x49, 0xf); + HW_WR_REG8((uint32_t)lut_crc5 + 0x4a, 0x0); + HW_WR_REG8((uint32_t)lut_crc5 + 0x4b, 0x5); + HW_WR_REG8((uint32_t)lut_crc5 + 0x4c, 0x1e); + HW_WR_REG8((uint32_t)lut_crc5 + 0x4d, 0x1b); + HW_WR_REG8((uint32_t)lut_crc5 + 0x4e, 0x14); + HW_WR_REG8((uint32_t)lut_crc5 + 0x4f, 0x11); + HW_WR_REG8((uint32_t)lut_crc5 + 0x50, 0x1d); + HW_WR_REG8((uint32_t)lut_crc5 + 0x51, 0x18); + HW_WR_REG8((uint32_t)lut_crc5 + 0x52, 0x17); + HW_WR_REG8((uint32_t)lut_crc5 + 0x53, 0x12); + HW_WR_REG8((uint32_t)lut_crc5 + 0x54, 0x9); + HW_WR_REG8((uint32_t)lut_crc5 + 0x55, 0xc); + HW_WR_REG8((uint32_t)lut_crc5 + 0x56, 0x3); + HW_WR_REG8((uint32_t)lut_crc5 + 0x57, 0x6); + HW_WR_REG8((uint32_t)lut_crc5 + 0x58, 0x10); + HW_WR_REG8((uint32_t)lut_crc5 + 0x59, 0x15); + HW_WR_REG8((uint32_t)lut_crc5 + 0x5a, 0x1a); + HW_WR_REG8((uint32_t)lut_crc5 + 0x5b, 0x1f); + HW_WR_REG8((uint32_t)lut_crc5 + 0x5c, 0x4); + HW_WR_REG8((uint32_t)lut_crc5 + 0x5d, 0x1); + HW_WR_REG8((uint32_t)lut_crc5 + 0x5e, 0xe); + HW_WR_REG8((uint32_t)lut_crc5 + 0x5f, 0xb); + HW_WR_REG8((uint32_t)lut_crc5 + 0x60, 0x16); + HW_WR_REG8((uint32_t)lut_crc5 + 0x61, 0x13); + HW_WR_REG8((uint32_t)lut_crc5 + 0x62, 0x1c); + HW_WR_REG8((uint32_t)lut_crc5 + 0x63, 0x19); + HW_WR_REG8((uint32_t)lut_crc5 + 0x64, 0x2); + HW_WR_REG8((uint32_t)lut_crc5 + 0x65, 0x7); + HW_WR_REG8((uint32_t)lut_crc5 + 0x66, 0x8); + HW_WR_REG8((uint32_t)lut_crc5 + 0x67, 0xd); + HW_WR_REG8((uint32_t)lut_crc5 + 0x68, 0x1b); + HW_WR_REG8((uint32_t)lut_crc5 + 0x69, 0x1e); + HW_WR_REG8((uint32_t)lut_crc5 + 0x6a, 0x11); + HW_WR_REG8((uint32_t)lut_crc5 + 0x6b, 0x14); + HW_WR_REG8((uint32_t)lut_crc5 + 0x6c, 0xf); + HW_WR_REG8((uint32_t)lut_crc5 + 0x6d, 0xa); + HW_WR_REG8((uint32_t)lut_crc5 + 0x6e, 0x5); + HW_WR_REG8((uint32_t)lut_crc5 + 0x6f, 0x0); + HW_WR_REG8((uint32_t)lut_crc5 + 0x70, 0xc); + HW_WR_REG8((uint32_t)lut_crc5 + 0x71, 0x9); + HW_WR_REG8((uint32_t)lut_crc5 + 0x72, 0x6); + HW_WR_REG8((uint32_t)lut_crc5 + 0x73, 0x3); + HW_WR_REG8((uint32_t)lut_crc5 + 0x74, 0x18); + HW_WR_REG8((uint32_t)lut_crc5 + 0x75, 0x1d); + HW_WR_REG8((uint32_t)lut_crc5 + 0x76, 0x12); + HW_WR_REG8((uint32_t)lut_crc5 + 0x77, 0x17); + HW_WR_REG8((uint32_t)lut_crc5 + 0x78, 0x1); + HW_WR_REG8((uint32_t)lut_crc5 + 0x79, 0x4); + HW_WR_REG8((uint32_t)lut_crc5 + 0x7a, 0xb); + HW_WR_REG8((uint32_t)lut_crc5 + 0x7b, 0xe); + HW_WR_REG8((uint32_t)lut_crc5 + 0x7c, 0x15); + HW_WR_REG8((uint32_t)lut_crc5 + 0x7d, 0x10); + HW_WR_REG8((uint32_t)lut_crc5 + 0x7e, 0x1f); + HW_WR_REG8((uint32_t)lut_crc5 + 0x7f, 0x1a); + HW_WR_REG8((uint32_t)lut_crc5 + 0x80, 0xe); + HW_WR_REG8((uint32_t)lut_crc5 + 0x81, 0xb); + HW_WR_REG8((uint32_t)lut_crc5 + 0x82, 0x4); + HW_WR_REG8((uint32_t)lut_crc5 + 0x83, 0x1); + HW_WR_REG8((uint32_t)lut_crc5 + 0x84, 0x1a); + HW_WR_REG8((uint32_t)lut_crc5 + 0x85, 0x1f); + HW_WR_REG8((uint32_t)lut_crc5 + 0x86, 0x10); + HW_WR_REG8((uint32_t)lut_crc5 + 0x87, 0x15); + HW_WR_REG8((uint32_t)lut_crc5 + 0x88, 0x3); + HW_WR_REG8((uint32_t)lut_crc5 + 0x89, 0x6); + HW_WR_REG8((uint32_t)lut_crc5 + 0x8a, 0x9); + HW_WR_REG8((uint32_t)lut_crc5 + 0x8b, 0xc); + HW_WR_REG8((uint32_t)lut_crc5 + 0x8c, 0x17); + HW_WR_REG8((uint32_t)lut_crc5 + 0x8d, 0x12); + HW_WR_REG8((uint32_t)lut_crc5 + 0x8e, 0x1d); + HW_WR_REG8((uint32_t)lut_crc5 + 0x8f, 0x18); + HW_WR_REG8((uint32_t)lut_crc5 + 0x90, 0x14); + HW_WR_REG8((uint32_t)lut_crc5 + 0x91, 0x11); + HW_WR_REG8((uint32_t)lut_crc5 + 0x92, 0x1e); + HW_WR_REG8((uint32_t)lut_crc5 + 0x93, 0x1b); + HW_WR_REG8((uint32_t)lut_crc5 + 0x94, 0x0); + HW_WR_REG8((uint32_t)lut_crc5 + 0x95, 0x5); + HW_WR_REG8((uint32_t)lut_crc5 + 0x96, 0xa); + HW_WR_REG8((uint32_t)lut_crc5 + 0x97, 0xf); + HW_WR_REG8((uint32_t)lut_crc5 + 0x98, 0x19); + HW_WR_REG8((uint32_t)lut_crc5 + 0x99, 0x1c); + HW_WR_REG8((uint32_t)lut_crc5 + 0x9a, 0x13); + HW_WR_REG8((uint32_t)lut_crc5 + 0x9b, 0x16); + HW_WR_REG8((uint32_t)lut_crc5 + 0x9c, 0xd); + HW_WR_REG8((uint32_t)lut_crc5 + 0x9d, 0x8); + HW_WR_REG8((uint32_t)lut_crc5 + 0x9e, 0x7); + HW_WR_REG8((uint32_t)lut_crc5 + 0x9f, 0x2); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa0, 0x1f); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa1, 0x1a); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa2, 0x15); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa3, 0x10); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa4, 0xb); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa5, 0xe); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa6, 0x1); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa7, 0x4); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa8, 0x12); + HW_WR_REG8((uint32_t)lut_crc5 + 0xa9, 0x17); + HW_WR_REG8((uint32_t)lut_crc5 + 0xaa, 0x18); + HW_WR_REG8((uint32_t)lut_crc5 + 0xab, 0x1d); + HW_WR_REG8((uint32_t)lut_crc5 + 0xac, 0x6); + HW_WR_REG8((uint32_t)lut_crc5 + 0xad, 0x3); + HW_WR_REG8((uint32_t)lut_crc5 + 0xae, 0xc); + HW_WR_REG8((uint32_t)lut_crc5 + 0xaf, 0x9); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb0, 0x5); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb1, 0x0); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb2, 0xf); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb3, 0xa); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb4, 0x11); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb5, 0x14); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb6, 0x1b); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb7, 0x1e); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb8, 0x8); + HW_WR_REG8((uint32_t)lut_crc5 + 0xb9, 0xd); + HW_WR_REG8((uint32_t)lut_crc5 + 0xba, 0x2); + HW_WR_REG8((uint32_t)lut_crc5 + 0xbb, 0x7); + HW_WR_REG8((uint32_t)lut_crc5 + 0xbc, 0x1c); + HW_WR_REG8((uint32_t)lut_crc5 + 0xbd, 0x19); + HW_WR_REG8((uint32_t)lut_crc5 + 0xbe, 0x16); + HW_WR_REG8((uint32_t)lut_crc5 + 0xbf, 0x13); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc0, 0x9); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc1, 0xc); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc2, 0x3); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc3, 0x6); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc4, 0x1d); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc5, 0x18); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc6, 0x17); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc7, 0x12); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc8, 0x4); + HW_WR_REG8((uint32_t)lut_crc5 + 0xc9, 0x1); + HW_WR_REG8((uint32_t)lut_crc5 + 0xca, 0xe); + HW_WR_REG8((uint32_t)lut_crc5 + 0xcb, 0xb); + HW_WR_REG8((uint32_t)lut_crc5 + 0xcc, 0x10); + HW_WR_REG8((uint32_t)lut_crc5 + 0xcd, 0x15); + HW_WR_REG8((uint32_t)lut_crc5 + 0xce, 0x1a); + HW_WR_REG8((uint32_t)lut_crc5 + 0xcf, 0x1f); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd0, 0x13); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd1, 0x16); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd2, 0x19); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd3, 0x1c); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd4, 0x7); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd5, 0x2); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd6, 0xd); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd7, 0x8); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd8, 0x1e); + HW_WR_REG8((uint32_t)lut_crc5 + 0xd9, 0x1b); + HW_WR_REG8((uint32_t)lut_crc5 + 0xda, 0x14); + HW_WR_REG8((uint32_t)lut_crc5 + 0xdb, 0x11); + HW_WR_REG8((uint32_t)lut_crc5 + 0xdc, 0xa); + HW_WR_REG8((uint32_t)lut_crc5 + 0xdd, 0xf); + HW_WR_REG8((uint32_t)lut_crc5 + 0xde, 0x0); + HW_WR_REG8((uint32_t)lut_crc5 + 0xdf, 0x5); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe0, 0x18); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe1, 0x1d); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe2, 0x12); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe3, 0x17); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe4, 0xc); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe5, 0x9); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe6, 0x6); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe7, 0x3); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe8, 0x15); + HW_WR_REG8((uint32_t)lut_crc5 + 0xe9, 0x10); + HW_WR_REG8((uint32_t)lut_crc5 + 0xea, 0x1f); + HW_WR_REG8((uint32_t)lut_crc5 + 0xeb, 0x1a); + HW_WR_REG8((uint32_t)lut_crc5 + 0xec, 0x1); + HW_WR_REG8((uint32_t)lut_crc5 + 0xed, 0x4); + HW_WR_REG8((uint32_t)lut_crc5 + 0xee, 0xb); + HW_WR_REG8((uint32_t)lut_crc5 + 0xef, 0xe); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf0, 0x2); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf1, 0x7); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf2, 0x8); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf3, 0xd); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf4, 0x16); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf5, 0x13); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf6, 0x1c); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf7, 0x19); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf8, 0xf); + HW_WR_REG8((uint32_t)lut_crc5 + 0xf9, 0xa); + HW_WR_REG8((uint32_t)lut_crc5 + 0xfa, 0x5); + HW_WR_REG8((uint32_t)lut_crc5 + 0xfb, 0x0); + HW_WR_REG8((uint32_t)lut_crc5 + 0xfc, 0x1b); + HW_WR_REG8((uint32_t)lut_crc5 + 0xfd, 0x1e); + HW_WR_REG8((uint32_t)lut_crc5 + 0xfe, 0x11); + HW_WR_REG8((uint32_t)lut_crc5 + 0xff, 0x14); + +} + +static void hdsl_generate_crc16_lut(HDSL_Handle hdslHandle) +{ + void *lut_crc16 = (void *)((uint32_t)(hdslHandle->baseMemAddr) + LUT_CRC16_OFFS); + + HW_WR_REG16((uint32_t)lut_crc16 + 0x0, 0x0); + HW_WR_REG16((uint32_t)lut_crc16 + 0x2, 0x90d9); + HW_WR_REG16((uint32_t)lut_crc16 + 0x4, 0xb16b); + HW_WR_REG16((uint32_t)lut_crc16 + 0x6, 0x21b2); + HW_WR_REG16((uint32_t)lut_crc16 + 0x8, 0xf20f); + HW_WR_REG16((uint32_t)lut_crc16 + 0xa, 0x62d6); + HW_WR_REG16((uint32_t)lut_crc16 + 0xc, 0x4364); + HW_WR_REG16((uint32_t)lut_crc16 + 0xe, 0xd3bd); + HW_WR_REG16((uint32_t)lut_crc16 + 0x10, 0x74c7); + HW_WR_REG16((uint32_t)lut_crc16 + 0x12, 0xe41e); + HW_WR_REG16((uint32_t)lut_crc16 + 0x14, 0xc5ac); + HW_WR_REG16((uint32_t)lut_crc16 + 0x16, 0x5575); + HW_WR_REG16((uint32_t)lut_crc16 + 0x18, 0x86c8); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1a, 0x1611); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1c, 0x37a3); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1e, 0xa77a); + HW_WR_REG16((uint32_t)lut_crc16 + 0x20, 0xe98e); + HW_WR_REG16((uint32_t)lut_crc16 + 0x22, 0x7957); + HW_WR_REG16((uint32_t)lut_crc16 + 0x24, 0x58e5); + HW_WR_REG16((uint32_t)lut_crc16 + 0x26, 0xc83c); + HW_WR_REG16((uint32_t)lut_crc16 + 0x28, 0x1b81); + HW_WR_REG16((uint32_t)lut_crc16 + 0x2a, 0x8b58); + HW_WR_REG16((uint32_t)lut_crc16 + 0x2c, 0xaaea); + HW_WR_REG16((uint32_t)lut_crc16 + 0x2e, 0x3a33); + HW_WR_REG16((uint32_t)lut_crc16 + 0x30, 0x9d49); + HW_WR_REG16((uint32_t)lut_crc16 + 0x32, 0xd90); + HW_WR_REG16((uint32_t)lut_crc16 + 0x34, 0x2c22); + HW_WR_REG16((uint32_t)lut_crc16 + 0x36, 0xbcfb); + HW_WR_REG16((uint32_t)lut_crc16 + 0x38, 0x6f46); + HW_WR_REG16((uint32_t)lut_crc16 + 0x3a, 0xff9f); + HW_WR_REG16((uint32_t)lut_crc16 + 0x3c, 0xde2d); + HW_WR_REG16((uint32_t)lut_crc16 + 0x3e, 0x4ef4); + HW_WR_REG16((uint32_t)lut_crc16 + 0x40, 0x43c5); + HW_WR_REG16((uint32_t)lut_crc16 + 0x42, 0xd31c); + HW_WR_REG16((uint32_t)lut_crc16 + 0x44, 0xf2ae); + HW_WR_REG16((uint32_t)lut_crc16 + 0x46, 0x6277); + HW_WR_REG16((uint32_t)lut_crc16 + 0x48, 0xb1ca); + HW_WR_REG16((uint32_t)lut_crc16 + 0x4a, 0x2113); + HW_WR_REG16((uint32_t)lut_crc16 + 0x4c, 0xa1); + HW_WR_REG16((uint32_t)lut_crc16 + 0x4e, 0x9078); + HW_WR_REG16((uint32_t)lut_crc16 + 0x50, 0x3702); + HW_WR_REG16((uint32_t)lut_crc16 + 0x52, 0xa7db); + HW_WR_REG16((uint32_t)lut_crc16 + 0x54, 0x8669); + HW_WR_REG16((uint32_t)lut_crc16 + 0x56, 0x16b0); + HW_WR_REG16((uint32_t)lut_crc16 + 0x58, 0xc50d); + HW_WR_REG16((uint32_t)lut_crc16 + 0x5a, 0x55d4); + HW_WR_REG16((uint32_t)lut_crc16 + 0x5c, 0x7466); + HW_WR_REG16((uint32_t)lut_crc16 + 0x5e, 0xe4bf); + HW_WR_REG16((uint32_t)lut_crc16 + 0x60, 0xaa4b); + HW_WR_REG16((uint32_t)lut_crc16 + 0x62, 0x3a92); + HW_WR_REG16((uint32_t)lut_crc16 + 0x64, 0x1b20); + HW_WR_REG16((uint32_t)lut_crc16 + 0x66, 0x8bf9); + HW_WR_REG16((uint32_t)lut_crc16 + 0x68, 0x5844); + HW_WR_REG16((uint32_t)lut_crc16 + 0x6a, 0xc89d); + HW_WR_REG16((uint32_t)lut_crc16 + 0x6c, 0xe92f); + HW_WR_REG16((uint32_t)lut_crc16 + 0x6e, 0x79f6); + HW_WR_REG16((uint32_t)lut_crc16 + 0x70, 0xde8c); + HW_WR_REG16((uint32_t)lut_crc16 + 0x72, 0x4e55); + HW_WR_REG16((uint32_t)lut_crc16 + 0x74, 0x6fe7); + HW_WR_REG16((uint32_t)lut_crc16 + 0x76, 0xff3e); + HW_WR_REG16((uint32_t)lut_crc16 + 0x78, 0x2c83); + HW_WR_REG16((uint32_t)lut_crc16 + 0x7a, 0xbc5a); + HW_WR_REG16((uint32_t)lut_crc16 + 0x7c, 0x9de8); + HW_WR_REG16((uint32_t)lut_crc16 + 0x7e, 0xd31); + HW_WR_REG16((uint32_t)lut_crc16 + 0x80, 0x878a); + HW_WR_REG16((uint32_t)lut_crc16 + 0x82, 0x1753); + HW_WR_REG16((uint32_t)lut_crc16 + 0x84, 0x36e1); + HW_WR_REG16((uint32_t)lut_crc16 + 0x86, 0xa638); + HW_WR_REG16((uint32_t)lut_crc16 + 0x88, 0x7585); + HW_WR_REG16((uint32_t)lut_crc16 + 0x8a, 0xe55c); + HW_WR_REG16((uint32_t)lut_crc16 + 0x8c, 0xc4ee); + HW_WR_REG16((uint32_t)lut_crc16 + 0x8e, 0x5437); + HW_WR_REG16((uint32_t)lut_crc16 + 0x90, 0xf34d); + HW_WR_REG16((uint32_t)lut_crc16 + 0x92, 0x6394); + HW_WR_REG16((uint32_t)lut_crc16 + 0x94, 0x4226); + HW_WR_REG16((uint32_t)lut_crc16 + 0x96, 0xd2ff); + HW_WR_REG16((uint32_t)lut_crc16 + 0x98, 0x142); + HW_WR_REG16((uint32_t)lut_crc16 + 0x9a, 0x919b); + HW_WR_REG16((uint32_t)lut_crc16 + 0x9c, 0xb029); + HW_WR_REG16((uint32_t)lut_crc16 + 0x9e, 0x20f0); + HW_WR_REG16((uint32_t)lut_crc16 + 0xa0, 0x6e04); + HW_WR_REG16((uint32_t)lut_crc16 + 0xa2, 0xfedd); + HW_WR_REG16((uint32_t)lut_crc16 + 0xa4, 0xdf6f); + HW_WR_REG16((uint32_t)lut_crc16 + 0xa6, 0x4fb6); + HW_WR_REG16((uint32_t)lut_crc16 + 0xa8, 0x9c0b); + HW_WR_REG16((uint32_t)lut_crc16 + 0xaa, 0xcd2); + HW_WR_REG16((uint32_t)lut_crc16 + 0xac, 0x2d60); + HW_WR_REG16((uint32_t)lut_crc16 + 0xae, 0xbdb9); + HW_WR_REG16((uint32_t)lut_crc16 + 0xb0, 0x1ac3); + HW_WR_REG16((uint32_t)lut_crc16 + 0xb2, 0x8a1a); + HW_WR_REG16((uint32_t)lut_crc16 + 0xb4, 0xaba8); + HW_WR_REG16((uint32_t)lut_crc16 + 0xb6, 0x3b71); + HW_WR_REG16((uint32_t)lut_crc16 + 0xb8, 0xe8cc); + HW_WR_REG16((uint32_t)lut_crc16 + 0xba, 0x7815); + HW_WR_REG16((uint32_t)lut_crc16 + 0xbc, 0x59a7); + HW_WR_REG16((uint32_t)lut_crc16 + 0xbe, 0xc97e); + HW_WR_REG16((uint32_t)lut_crc16 + 0xc0, 0xc44f); + HW_WR_REG16((uint32_t)lut_crc16 + 0xc2, 0x5496); + HW_WR_REG16((uint32_t)lut_crc16 + 0xc4, 0x7524); + HW_WR_REG16((uint32_t)lut_crc16 + 0xc6, 0xe5fd); + HW_WR_REG16((uint32_t)lut_crc16 + 0xc8, 0x3640); + HW_WR_REG16((uint32_t)lut_crc16 + 0xca, 0xa699); + HW_WR_REG16((uint32_t)lut_crc16 + 0xcc, 0x872b); + HW_WR_REG16((uint32_t)lut_crc16 + 0xce, 0x17f2); + HW_WR_REG16((uint32_t)lut_crc16 + 0xd0, 0xb088); + HW_WR_REG16((uint32_t)lut_crc16 + 0xd2, 0x2051); + HW_WR_REG16((uint32_t)lut_crc16 + 0xd4, 0x1e3); + HW_WR_REG16((uint32_t)lut_crc16 + 0xd6, 0x913a); + HW_WR_REG16((uint32_t)lut_crc16 + 0xd8, 0x4287); + HW_WR_REG16((uint32_t)lut_crc16 + 0xda, 0xd25e); + HW_WR_REG16((uint32_t)lut_crc16 + 0xdc, 0xf3ec); + HW_WR_REG16((uint32_t)lut_crc16 + 0xde, 0x6335); + HW_WR_REG16((uint32_t)lut_crc16 + 0xe0, 0x2dc1); + HW_WR_REG16((uint32_t)lut_crc16 + 0xe2, 0xbd18); + HW_WR_REG16((uint32_t)lut_crc16 + 0xe4, 0x9caa); + HW_WR_REG16((uint32_t)lut_crc16 + 0xe6, 0xc73); + HW_WR_REG16((uint32_t)lut_crc16 + 0xe8, 0xdfce); + HW_WR_REG16((uint32_t)lut_crc16 + 0xea, 0x4f17); + HW_WR_REG16((uint32_t)lut_crc16 + 0xec, 0x6ea5); + HW_WR_REG16((uint32_t)lut_crc16 + 0xee, 0xfe7c); + HW_WR_REG16((uint32_t)lut_crc16 + 0xf0, 0x5906); + HW_WR_REG16((uint32_t)lut_crc16 + 0xf2, 0xc9df); + HW_WR_REG16((uint32_t)lut_crc16 + 0xf4, 0xe86d); + HW_WR_REG16((uint32_t)lut_crc16 + 0xf6, 0x78b4); + HW_WR_REG16((uint32_t)lut_crc16 + 0xf8, 0xab09); + HW_WR_REG16((uint32_t)lut_crc16 + 0xfa, 0x3bd0); + HW_WR_REG16((uint32_t)lut_crc16 + 0xfc, 0x1a62); + HW_WR_REG16((uint32_t)lut_crc16 + 0xfe, 0x8abb); + HW_WR_REG16((uint32_t)lut_crc16 + 0x100, 0x9fcd); + HW_WR_REG16((uint32_t)lut_crc16 + 0x102, 0xf14); + HW_WR_REG16((uint32_t)lut_crc16 + 0x104, 0x2ea6); + HW_WR_REG16((uint32_t)lut_crc16 + 0x106, 0xbe7f); + HW_WR_REG16((uint32_t)lut_crc16 + 0x108, 0x6dc2); + HW_WR_REG16((uint32_t)lut_crc16 + 0x10a, 0xfd1b); + HW_WR_REG16((uint32_t)lut_crc16 + 0x10c, 0xdca9); + HW_WR_REG16((uint32_t)lut_crc16 + 0x10e, 0x4c70); + HW_WR_REG16((uint32_t)lut_crc16 + 0x110, 0xeb0a); + HW_WR_REG16((uint32_t)lut_crc16 + 0x112, 0x7bd3); + HW_WR_REG16((uint32_t)lut_crc16 + 0x114, 0x5a61); + HW_WR_REG16((uint32_t)lut_crc16 + 0x116, 0xcab8); + HW_WR_REG16((uint32_t)lut_crc16 + 0x118, 0x1905); + HW_WR_REG16((uint32_t)lut_crc16 + 0x11a, 0x89dc); + HW_WR_REG16((uint32_t)lut_crc16 + 0x11c, 0xa86e); + HW_WR_REG16((uint32_t)lut_crc16 + 0x11e, 0x38b7); + HW_WR_REG16((uint32_t)lut_crc16 + 0x120, 0x7643); + HW_WR_REG16((uint32_t)lut_crc16 + 0x122, 0xe69a); + HW_WR_REG16((uint32_t)lut_crc16 + 0x124, 0xc728); + HW_WR_REG16((uint32_t)lut_crc16 + 0x126, 0x57f1); + HW_WR_REG16((uint32_t)lut_crc16 + 0x128, 0x844c); + HW_WR_REG16((uint32_t)lut_crc16 + 0x12a, 0x1495); + HW_WR_REG16((uint32_t)lut_crc16 + 0x12c, 0x3527); + HW_WR_REG16((uint32_t)lut_crc16 + 0x12e, 0xa5fe); + HW_WR_REG16((uint32_t)lut_crc16 + 0x130, 0x284); + HW_WR_REG16((uint32_t)lut_crc16 + 0x132, 0x925d); + HW_WR_REG16((uint32_t)lut_crc16 + 0x134, 0xb3ef); + HW_WR_REG16((uint32_t)lut_crc16 + 0x136, 0x2336); + HW_WR_REG16((uint32_t)lut_crc16 + 0x138, 0xf08b); + HW_WR_REG16((uint32_t)lut_crc16 + 0x13a, 0x6052); + HW_WR_REG16((uint32_t)lut_crc16 + 0x13c, 0x41e0); + HW_WR_REG16((uint32_t)lut_crc16 + 0x13e, 0xd139); + HW_WR_REG16((uint32_t)lut_crc16 + 0x140, 0xdc08); + HW_WR_REG16((uint32_t)lut_crc16 + 0x142, 0x4cd1); + HW_WR_REG16((uint32_t)lut_crc16 + 0x144, 0x6d63); + HW_WR_REG16((uint32_t)lut_crc16 + 0x146, 0xfdba); + HW_WR_REG16((uint32_t)lut_crc16 + 0x148, 0x2e07); + HW_WR_REG16((uint32_t)lut_crc16 + 0x14a, 0xbede); + HW_WR_REG16((uint32_t)lut_crc16 + 0x14c, 0x9f6c); + HW_WR_REG16((uint32_t)lut_crc16 + 0x14e, 0xfb5); + HW_WR_REG16((uint32_t)lut_crc16 + 0x150, 0xa8cf); + HW_WR_REG16((uint32_t)lut_crc16 + 0x152, 0x3816); + HW_WR_REG16((uint32_t)lut_crc16 + 0x154, 0x19a4); + HW_WR_REG16((uint32_t)lut_crc16 + 0x156, 0x897d); + HW_WR_REG16((uint32_t)lut_crc16 + 0x158, 0x5ac0); + HW_WR_REG16((uint32_t)lut_crc16 + 0x15a, 0xca19); + HW_WR_REG16((uint32_t)lut_crc16 + 0x15c, 0xebab); + HW_WR_REG16((uint32_t)lut_crc16 + 0x15e, 0x7b72); + HW_WR_REG16((uint32_t)lut_crc16 + 0x160, 0x3586); + HW_WR_REG16((uint32_t)lut_crc16 + 0x162, 0xa55f); + HW_WR_REG16((uint32_t)lut_crc16 + 0x164, 0x84ed); + HW_WR_REG16((uint32_t)lut_crc16 + 0x166, 0x1434); + HW_WR_REG16((uint32_t)lut_crc16 + 0x168, 0xc789); + HW_WR_REG16((uint32_t)lut_crc16 + 0x16a, 0x5750); + HW_WR_REG16((uint32_t)lut_crc16 + 0x16c, 0x76e2); + HW_WR_REG16((uint32_t)lut_crc16 + 0x16e, 0xe63b); + HW_WR_REG16((uint32_t)lut_crc16 + 0x170, 0x4141); + HW_WR_REG16((uint32_t)lut_crc16 + 0x172, 0xd198); + HW_WR_REG16((uint32_t)lut_crc16 + 0x174, 0xf02a); + HW_WR_REG16((uint32_t)lut_crc16 + 0x176, 0x60f3); + HW_WR_REG16((uint32_t)lut_crc16 + 0x178, 0xb34e); + HW_WR_REG16((uint32_t)lut_crc16 + 0x17a, 0x2397); + HW_WR_REG16((uint32_t)lut_crc16 + 0x17c, 0x225); + HW_WR_REG16((uint32_t)lut_crc16 + 0x17e, 0x92fc); + HW_WR_REG16((uint32_t)lut_crc16 + 0x180, 0x1847); + HW_WR_REG16((uint32_t)lut_crc16 + 0x182, 0x889e); + HW_WR_REG16((uint32_t)lut_crc16 + 0x184, 0xa92c); + HW_WR_REG16((uint32_t)lut_crc16 + 0x186, 0x39f5); + HW_WR_REG16((uint32_t)lut_crc16 + 0x188, 0xea48); + HW_WR_REG16((uint32_t)lut_crc16 + 0x18a, 0x7a91); + HW_WR_REG16((uint32_t)lut_crc16 + 0x18c, 0x5b23); + HW_WR_REG16((uint32_t)lut_crc16 + 0x18e, 0xcbfa); + HW_WR_REG16((uint32_t)lut_crc16 + 0x190, 0x6c80); + HW_WR_REG16((uint32_t)lut_crc16 + 0x192, 0xfc59); + HW_WR_REG16((uint32_t)lut_crc16 + 0x194, 0xddeb); + HW_WR_REG16((uint32_t)lut_crc16 + 0x196, 0x4d32); + HW_WR_REG16((uint32_t)lut_crc16 + 0x198, 0x9e8f); + HW_WR_REG16((uint32_t)lut_crc16 + 0x19a, 0xe56); + HW_WR_REG16((uint32_t)lut_crc16 + 0x19c, 0x2fe4); + HW_WR_REG16((uint32_t)lut_crc16 + 0x19e, 0xbf3d); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1a0, 0xf1c9); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1a2, 0x6110); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1a4, 0x40a2); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1a6, 0xd07b); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1a8, 0x3c6); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1aa, 0x931f); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1ac, 0xb2ad); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1ae, 0x2274); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1b0, 0x850e); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1b2, 0x15d7); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1b4, 0x3465); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1b6, 0xa4bc); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1b8, 0x7701); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1ba, 0xe7d8); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1bc, 0xc66a); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1be, 0x56b3); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1c0, 0x5b82); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1c2, 0xcb5b); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1c4, 0xeae9); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1c6, 0x7a30); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1c8, 0xa98d); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1ca, 0x3954); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1cc, 0x18e6); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1ce, 0x883f); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1d0, 0x2f45); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1d2, 0xbf9c); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1d4, 0x9e2e); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1d6, 0xef7); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1d8, 0xdd4a); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1da, 0x4d93); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1dc, 0x6c21); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1de, 0xfcf8); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1e0, 0xb20c); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1e2, 0x22d5); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1e4, 0x367); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1e6, 0x93be); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1e8, 0x4003); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1ea, 0xd0da); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1ec, 0xf168); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1ee, 0x61b1); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1f0, 0xc6cb); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1f2, 0x5612); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1f4, 0x77a0); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1f6, 0xe779); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1f8, 0x34c4); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1fa, 0xa41d); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1fc, 0x85af); + HW_WR_REG16((uint32_t)lut_crc16 + 0x1fe, 0x1576); + +} + +static void hdsl_generate_bit_to_byte_lut(HDSL_Handle hdslHandle) +{ + void *lut_bittobyte = (void *)((uint32_t)(hdslHandle->baseMemAddr) + LUT_BITTOBYTE_OFFS); + + HW_WR_REG32((uint32_t)lut_bittobyte + 0x0, 0x0); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x4, 0x1); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x8, 0x100); + HW_WR_REG32((uint32_t)lut_bittobyte + 0xc, 0x101); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x10, 0x10000); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x14, 0x10001); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x18, 0x10100); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x1c, 0x10101); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x20, 0x1000000); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x24, 0x1000001); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x28, 0x1000100); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x2c, 0x1000101); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x30, 0x1010000); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x34, 0x1010001); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x38, 0x1010100); + HW_WR_REG32((uint32_t)lut_bittobyte + 0x3c, 0x1010101); + +} + +static void hdsl_generate_rssi_lut(HDSL_Handle hdslHandle) +{ + void *lut_rssi = (void *)((uint32_t)(hdslHandle->baseMemAddr) + LUT_RSSI_OFFS); + + HW_WR_REG8((uint32_t)lut_rssi + 0x0, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x1, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x2, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x3, 0xa); + HW_WR_REG8((uint32_t)lut_rssi + 0x4, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x5, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x6, 0xa); + HW_WR_REG8((uint32_t)lut_rssi + 0x7, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x8, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x9, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xa, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0xb, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xc, 0xa); + HW_WR_REG8((uint32_t)lut_rssi + 0xd, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xe, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0xf, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x10, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x11, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x12, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x13, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x14, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x15, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x16, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x17, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x18, 0xa); + HW_WR_REG8((uint32_t)lut_rssi + 0x19, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x1a, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x1b, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x1c, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x1d, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x1e, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x1f, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x20, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x21, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x22, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x23, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x24, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x25, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x26, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x27, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x28, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x29, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x2a, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x2b, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x2c, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x2d, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x2e, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x2f, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x30, 0xa); + HW_WR_REG8((uint32_t)lut_rssi + 0x31, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x32, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x33, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x34, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x35, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x36, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x37, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x38, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x39, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x3a, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x3b, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x3c, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x3d, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x3e, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x3f, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x40, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x41, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x42, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x43, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x44, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x45, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x46, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x47, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x48, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x49, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x4a, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x4b, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x4c, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x4d, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x4e, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x4f, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x50, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x51, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x52, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x53, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x54, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x55, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x56, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x57, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x58, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x59, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x5a, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x5b, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x5c, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x5d, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x5e, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x5f, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x60, 0xa); + HW_WR_REG8((uint32_t)lut_rssi + 0x61, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x62, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x63, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x64, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x65, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x66, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x67, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x68, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x69, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x6a, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x6b, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x6c, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x6d, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x6e, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x6f, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x70, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x71, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x72, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x73, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x74, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x75, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x76, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x77, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x78, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x79, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x7a, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x7b, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x7c, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x7d, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x7e, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x7f, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x80, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0x81, 0xa); + HW_WR_REG8((uint32_t)lut_rssi + 0x82, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x83, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0x84, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x85, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x86, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x87, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x88, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x89, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x8a, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x8b, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x8c, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x8d, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x8e, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x8f, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x90, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0x91, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x92, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x93, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x94, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x95, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x96, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x97, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x98, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0x99, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x9a, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x9b, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x9c, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x9d, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x9e, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0x9f, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xa0, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0xa1, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xa2, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xa3, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xa4, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xa5, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xa6, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xa7, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xa8, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xa9, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xaa, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xab, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xac, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xad, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xae, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xaf, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xb0, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xb1, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xb2, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xb3, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xb4, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xb5, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xb6, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xb7, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xb8, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xb9, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xba, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xbb, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xbc, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xbd, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xbe, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xbf, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xc0, 0xa); + HW_WR_REG8((uint32_t)lut_rssi + 0xc1, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0xc2, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xc3, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xc4, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xc5, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xc6, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xc7, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xc8, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xc9, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xca, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xcb, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xcc, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xcd, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xce, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xcf, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xd0, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xd1, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xd2, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xd3, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xd4, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xd5, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xd6, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xd7, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xd8, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xd9, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xda, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xdb, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xdc, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xdd, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xde, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xdf, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xe0, 0x8); + HW_WR_REG8((uint32_t)lut_rssi + 0xe1, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xe2, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xe3, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xe4, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xe5, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xe6, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xe7, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xe8, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xe9, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xea, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xeb, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xec, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xed, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xee, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xef, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xf0, 0x6); + HW_WR_REG8((uint32_t)lut_rssi + 0xf1, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xf2, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xf3, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xf4, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xf5, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xf6, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xf7, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xf8, 0x4); + HW_WR_REG8((uint32_t)lut_rssi + 0xf9, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xfa, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xfb, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xfc, 0x2); + HW_WR_REG8((uint32_t)lut_rssi + 0xfd, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xfe, 0xc); + HW_WR_REG8((uint32_t)lut_rssi + 0xff, 0xc); +} + +static void hdsl_generate_extra_edge_lut(HDSL_Handle hdslHandle) +{ + void *lut_ee = (void *)((uint32_t)(hdslHandle->baseMemAddr) + LUT_EE_OFFS); + + HW_WR_REG8((uint32_t)lut_ee + 0, 0x00); + HW_WR_REG8((uint32_t)lut_ee + 1, 0x80); + HW_WR_REG8((uint32_t)lut_ee + 2, 0xc0); + HW_WR_REG8((uint32_t)lut_ee + 3, 0xe0); + HW_WR_REG8((uint32_t)lut_ee + 4, 0xf0); + HW_WR_REG8((uint32_t)lut_ee + 5, 0xf8); + HW_WR_REG8((uint32_t)lut_ee + 6, 0xfc); + HW_WR_REG8((uint32_t)lut_ee + 7, 0xfe); + HW_WR_REG8((uint32_t)lut_ee + 8, 0xff); +} + +static void hdsl_configure_register_if(HDSL_Handle hdslHandle) +{ + hdslHandle->hdslInterface->PC_ADD_H = 0x80; + hdslHandle->hdslInterface->PC_OFF_H = 0x80; + hdslHandle->hdslInterface->MAXDEV_H = 0x0; + hdslHandle->hdslInterface->MAXDEV_L = 0x0; + hdslHandle->hdslInterface->MAXDEV_H_THRES = 0xFF; + hdslHandle->hdslInterface->MAXDEV_L_THRES = 0xFF; + hdslHandle->hdslInterface->VERSION = 0x41; + hdslHandle->hdslInterface->ACC_ERR_CNT_THRES = 0x1F; + + HW_WR_REG32(((uint32_t)(hdslHandle->baseMemAddr) + 0xac), 0x4cc8115d); + HW_WR_REG32(((uint32_t)(hdslHandle->baseMemAddr) + 0xac)+4, 0xfb334990); + HW_WR_REG32(((uint32_t)(hdslHandle->baseMemAddr) + 0xac)+8, 0xfffff800); +} + +void HDSL_generate_memory_image(HDSL_Handle hdslHandle) +{ + hdsl_enc_dec_lut(hdslHandle); + hdsl_generate_bit_cnt_lut(hdslHandle); + hdsl_generate_crc5_lut(hdslHandle); + hdsl_generate_crc16_lut(hdslHandle); + hdsl_generate_bit_to_byte_lut(hdslHandle); + hdsl_generate_rssi_lut(hdslHandle); + hdsl_generate_extra_edge_lut(hdslHandle); + hdsl_configure_register_if(hdslHandle); +} diff --git a/source/motor_control/position_sense/hdsl/firmware/datalink.asm b/source/motor_control/position_sense/hdsl/firmware/datalink.asm new file mode 100644 index 0000000..4339d52 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/datalink.asm @@ -0,0 +1,1692 @@ + +; +; Copyright (C) 2021-2023 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + .include "memory.inc" + .include "defines.inc" + .include "macros.inc" + ;.sect ".text" + .ref transport_init + .ref transport_on_h_frame + .ref transport_on_v_frame + .ref transport_on_v_frame_2 + .ref transport_layer_processing_1 + .ref transport_layer_processing_2 + .ref calc_acc_crc + .ref calc_speed + .ref calc_fastpos + .ref transport_layer + .ref transport_layer_send_msg + .ref transport_layer_recv_msg + .ref load_code + .ref datalink_reset + .ref send_01 + .ref int_div + + .ref transport_on_v_frame_2 + .ref transport_layer_processing_1 + .ref transport_layer_processing_2 + + ;.ref transport_layer_assemble_msg + ;.global transport_layer_assemble_msg_done + .global transport_layer_send_msg_done + .global transport_layer_recv_msg_done + .global transport_layer_done + .global datalink_abort + .global datalink_abort2 + .global qm_add + .global datalink_transport_on_v_frame_done + .global datalink_transport_on_v_frame_done_2 + .global transport_layer_processing_1_done + .global transport_layer_processing_2_done + .if !$defined("HDSL_MULTICHANNEL") + .global update_events + .endif + .global datalink_init + .global qm_add + .global calc_rssi + .global send_stuffing + .global send_header + .global send_trailer + .global wait_delay + .global datalink_loadfw + .global recv_dec + .global main + .global datalink_wait_vsynch + +;Initialize connection and state machine here +datalink_init: +;-------------------------------------------------------------------------------------------------- + .sect ".text" + jmp main +;-------------------------------------------------------------------------------------------------- +;State LOADFW +;this state does not exist in the Hiperface DSL specification and is only used to gain time for loading PRU Code to intruction memory! +datalink_loadfw: + ldi LOOP_CNT.b1, NUM_LOADFW + zero &FAST_POSH, 4 + +datalink_loadfw_loop: + ldi REG_FNC.w0, (0x0000 | M_PAR_IDREQ) + CALL send_header + ;CALL recv_dec + WAIT_TX_DONE +;slave transmits answer here (61 bits) + READ_IEPCNT SPEED +;we switch to tx again + TX_EN +;wait 12bits - delay +;TODO: rm delay! + qbeq datalink_loadfw_no_wait, SLAVE_DELAY, 12 +;wait 61+1sw+12delay bits - slave delay +; ldi REG_TMP1, (74*CYCLES_BIT-26+4-3) + .if $defined("FREERUN_300_MHZ") + ldi REG_TMP1, (74*CYCLES_BIT+5-2) + .else + ldi REG_TMP1, (74*CYCLES_BIT+5) + .endif + READ_IEPCNT REG_TMP0 + sub REG_TMP0, REG_TMP0, SPEED + sub REG_TMP0, REG_TMP1, REG_TMP0 + WAIT REG_TMP0 +datalink_loadfw_no_wait: +;send TRAILER + CALL1 send_trailer + CALL1 send_stuffing + sub LOOP_CNT.b1, LOOP_CNT.b1, 1 + qbne datalink_loadfw_loop, LOOP_CNT.b1, 0 + zero &SPEED, (4*8) + +;-------------------------------------------------------------------------------------------------- +;State WAIT VSYNC +;Send M_PAR_IDLE and wait for VSYNC=1 + ldi LOOP_CNT.b1, 7 +datalink_wait_vsynch: + zero &SPEED, (4*8) + ldi LOOP_CNT.b1, 7 +;send m_par_reset 8b/10b: 5b/6b and 3b/4b, first=1,vsync=0,reserved=0 + ldi REG_FNC.w0, (0x0400 | M_PAR_INIT) + CALL send_header + CALL recv_dec +;check for timeout + sub LOOP_CNT.b1, LOOP_CNT.b1, 1 + qbeq datalink_abort_jmp, LOOP_CNT.b1, 0 + CALL1 send_stuffing + +;check for error in parameter channel (byte 1) + qbbs datalink_wait_vsynch, BYTE_ERROR, BYTE_CH_PARAMETER +;try again if vsync is not set + qbbc datalink_wait_vsynch, H_FRAME.s_par, 7 + ;qba datalink_wait_vsynch +;received vsync - now set msync for synchronization + set H_FRAME.flags, H_FRAME.flags, FLAG_MSYNC +;message can be sent now +; Set EVENT_S_FRES in EVENT_S register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 + set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_FRES +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + qbbc update_events_no_int0, REG_TMP0.b1, EVENT_S_FRES +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ4 +update_events_no_int0: +; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_1_FRES-8) + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 +; Set EVENT_FREL in EVENT_L register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + set REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int1, REG_TMP0.w2, EVENT_FREL +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int1: +; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 +;-------------------------------------------------------------------------------------------------- +;State RX0-RX7 + ldi LOOP_CNT.w2, 8 + ldi SEND_PARA, M_PAR_IDLE + ldi CRC, 0 +datalink_rx0_7: + ldi REG_FNC.b1, 0x4 +;check if we set MSYNC + qbbc datalink_rx0_7_no_msync, H_FRAME.flags, FLAG_MSYNC + set REG_FNC.b1, REG_FNC.b1, 1 +datalink_rx0_7_no_msync: +;flip MSYNC in rx7 + qbne datalink_rx0_7_not_rx7, LOOP_CNT.b2, 1 + ldi REG_TMP0, (1< flip + xor CRC_VERT_H, CRC_VERT_H, 0xff +recv_dec_vertical_not_rx7: + ldi REG_TMP0, (LUT_CRC16+PDMEM00) + lsl REG_TMP1.w0, CRC_VERT_H, 1 + lbbo ®_TMP0.w0, REG_TMP0, REG_TMP1.w0, 2 + xor REG_TMP0.b1, REG_TMP0.b1, CRC_VERT_L + mov CRC_VERT, REG_TMP0.w0 +;receive parameter channel + ldi REG_FNC.b1, 1 + ldi LOOP_CNT.b0, 6 + CALL1 recv_dec_10b + mov H_FRAME.s_par, REG_FNC.b0 +;put data to CHANNEL - parameter channel, only lower 5 bits contain data information + lsl CHANNEL.ch_parah, CHANNEL.ch_parah, 5 + lsr REG_TMP0, CHANNEL.ch_paral, 27 + or CHANNEL.ch_parah, CHANNEL.ch_parah, REG_TMP0 + lsl CHANNEL.ch_paral, CHANNEL.ch_paral, 5 + and REG_TMP0, H_FRAME.s_par, 0x1f + or CHANNEL.ch_paral, CHANNEL.ch_paral, REG_TMP0 +;receive pipe channel + ldi REG_FNC.b1, 2 + ldi LOOP_CNT.b0, 6 + CALL1 recv_dec_10b + mov H_FRAME.pipe, REG_FNC.b0 +;receive acceleration channel + ldi REG_FNC.b1, 3 + ldi LOOP_CNT.b0, 6 + CALL1 recv_dec_10b + mov H_FRAME.acc, REG_FNC.b0 + ldi REG_FNC.b1, 4 + ldi LOOP_CNT.b0, 6 + CALL1 recv_dec_10b + lsl H_FRAME.acc, H_FRAME.acc, 8 + or H_FRAME.acc, H_FRAME.acc, REG_FNC.b0 +;one switch bit - always opposite of last bit + ldi REG_TMP0.w2, 0 +datalink_receive_signal_swb_0: + qbbc datalink_receive_signal_swb_0, r31, RX_VALID_FLAG ;changed here from 24 to 26 + POP_FIFO REG_TMP0.b0 + CLEAR_VAL + qbbc datalink_receive_signal_swb_received_0_0, REG_TMP0.w0, SAMPLE_EDGE + set REG_TMP0.w2, REG_TMP0.w2, 0 +datalink_receive_signal_swb_received_0_0: +;check for error in vertical channel + qbbc datalink_receive_signal_no_error_0, BYTE_ERROR, BYTE_CH_VERTICAL + qbbs datalink_receive_signal_no_error_0, BYTE_ERROR, 7 + set BYTE_ERROR, BYTE_ERROR, 7 + qbbs datalink_receive_signal_no_error_0, H_FRAME.flags, FLAG_ERR_VERT + set H_FRAME.flags, H_FRAME.flags, FLAG_ERR_VERT + QM_SUB 6 + qba recv_dec_vertical_no_special_character +datalink_receive_signal_no_error_0: +;vertical channel is only allowed to have K29.7 as special character + qbbc recv_dec_vertical_no_special_character, SPECIAL_CHARACTER, BYTE_CH_VERTICAL + qbeq recv_dec_vertical_no_special_character, H_FRAME.vert, K29_7 + QM_SUB 2 +recv_dec_vertical_no_special_character: +;check for error in parameter channel + qbbc datalink_receive_signal_no_error_1, BYTE_ERROR, BYTE_CH_PARAMETER + QM_SUB 1 + qba recv_dec_para_no_special_character +datalink_receive_signal_no_error_1: +;check for special character: parameter channel is not allowed to have that + qbbc recv_dec_para_no_special_character, SPECIAL_CHARACTER, BYTE_CH_PARAMETER + QM_SUB 2 +recv_dec_para_no_special_character: +;check for error in pipe channel + qbbc datalink_receive_signal_no_error_2, BYTE_ERROR, BYTE_CH_PIPE + QM_SUB 1 +datalink_receive_signal_no_error_2: +;check for error in acceleration channel + and REG_TMP0, BYTE_ERROR, (0x03<<3) + qbeq datalink_receive_signal_no_error_3_4, REG_TMP0, 0 + set H_FRAME.flags, H_FRAME.flags, FLAG_ERR_ACC + QM_SUB 2 + qba recv_dec_acc_no_special_character +datalink_receive_signal_no_error_3_4: +;vertical channel is only allowed to have K29.7 as special character + qbbc recv_dec_acc_check_special_character, SPECIAL_CHARACTER, BYTE_CH_ACC_H + qbne recv_dec_acc_special_character, H_FRAME_acc1, K29_7 +recv_dec_acc_check_special_character: + qbbc recv_dec_acc_no_special_character, SPECIAL_CHARACTER, BYTE_CH_ACC_L + qbeq recv_dec_acc_no_special_character, H_FRAME_acc0, K29_7 +recv_dec_acc_special_character: + QM_SUB 2 +recv_dec_acc_no_special_character: +;receive secondary channel + ldi REG_FNC.b1, 5 + ldi LOOP_CNT.b0, 6 + CALL1 srecv_dec_10b +;switch to TX + TX_EN +;wait 61+1sw+12delay bits - slave delay + ldi REG_TMP1, (74*CYCLES_BIT+9) ; -9 for 100m + READ_CYCLCNT REG_TMP0 + qble datalink_receive_signal_no_delay_wait_0, REG_TMP0, REG_TMP1 + sub REG_TMP0, REG_TMP1, REG_TMP0 + WAIT REG_TMP0 + +datalink_receive_signal_no_delay_wait_0: +;send TRAILER + CALL1 send_trailer +;put data to CHANNEL - secondary channel + mov H_FRAME.secondary, REG_FNC.b0 + lsl CHANNEL.ch_sech, CHANNEL.ch_sech, 8 + lsr REG_TMP0, CHANNEL.ch_secl, 24 + or CHANNEL.ch_sech, CHANNEL.ch_sech, REG_TMP0 + lsl CHANNEL.ch_secl, CHANNEL.ch_secl, 8 + or CHANNEL.ch_secl, CHANNEL.ch_secl, H_FRAME.secondary +;check for error in secondary channel + qbbc datalink_receive_signal_no_error_5, BYTE_ERROR, BYTE_CH_SECONDARY + qbbs datalink_receive_signal_no_error_5, H_FRAME.flags, FLAG_ERR_SEC + set H_FRAME.flags, H_FRAME.flags, FLAG_ERR_SEC + QM_SUB 8 +;calc running crc for secondary channel + xor CRC_SEC_H, CRC_SEC_H, H_FRAME.secondary + qbne recv_dec_secondary_not_rx7, LOOP_CNT.b2, 1 +;last byte of secondary channel: crc -> flip + xor CRC_SEC_H, CRC_SEC_H, 0xff +recv_dec_secondary_not_rx7: + ldi REG_TMP0, (LUT_CRC16+PDMEM00) + lsl REG_TMP1.w0, CRC_SEC_H, 1 + lbbo ®_TMP0.w0, REG_TMP0, REG_TMP1.w0, 2 + xor REG_TMP0.b1, REG_TMP0.b1, CRC_SEC_L + mov CRC_SEC, REG_TMP0.w0 +datalink_receive_signal_no_error_5: + RET +;-------------------------------------------------------------------------------------------------- +;Function: send_header (RET_ADDR) +;This function sends the header (data before slave answer) +;input: +; REG_FNC.w0: parameter channel input +;output: +;modifies: +; REG_TMP0, REG_FNC +;-------------------------------------------------------------------------------------------------- +send_header: +;push SYNC and first 2 bits of SAMPLE + + .if $defined("HDSL_MULTICHANNEL") + ;PUSH 8 bytes for 1 byte data (0x2f) in FIFO + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + +;check if we have an EXTRA period +;if we have a EXTRA period: do TX FIFO synchronization here to gain processing time + qbeq send_header_no_extra_wait, EXTRA_SIZE, 0 +; PUSH 8 bytes for 1 byte data (0xff) in FIFO + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + .else + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x2f + ;check if we have an EXTRA period +;if we have a EXTRA period: do TX FIFO synchronization here to gain processing time + qbeq send_header_no_extra_wait, EXTRA_SIZE, 0 + PUSH_FIFO_CONST 0xff + .endif ;HDSL_MULTICHANNEL + RESET_CYCLCNT + +send_header_modified: +send_header_no_extra_wait: + + .if $defined("HDSL_MULTICHANNEL") + qbne dont_push_for_non7_hframe,LOOP_CNT.b2,7 + PUSH_FIFO_CONST 0xff +dont_push_for_non7_hframe: + .endif +;calculate EQUALIZATION + add DISPARITY, DISPARITY, EXTRA_SIZE + qbbs send_header_disp_neg, DISPARITY, 7 +send_header_disp_pos: + qblt send_header_disp_pos0, DISPARITY, 1 + ldi REG_TMP11.b0, 0x60 ; 0x6a + qba send_header_end_disp +send_header_disp_pos0: + qblt send_header_disp_pos1, DISPARITY, 3 + ldi REG_TMP11.b0, 0x62 + sub DISPARITY, DISPARITY, 2 + qba send_header_end_disp +send_header_disp_pos1: + ldi REG_TMP11.b0, 0x60 + sub DISPARITY, DISPARITY, 4 + qba send_header_end_disp +send_header_disp_neg: + not REG_TMP11.b0, DISPARITY + add REG_TMP11.b0, REG_TMP11.b0, 1 + qblt send_header_disp_neg0, REG_TMP11.b0, 1 + ldi REG_TMP11.b0, 0x60; 0x6a + qba send_header_end_disp +send_header_disp_neg0: + qblt send_header_disp_neg1, REG_TMP11.b0, 3 + ldi REG_TMP11.b0, 0x6d + add DISPARITY, DISPARITY, 2 + qba send_header_end_disp +send_header_disp_neg1: + ldi REG_TMP11.b0, 0x6f + add DISPARITY, DISPARITY, 4 +send_header_end_disp: +;reset eCAP1 INT + ldi REG_TMP1.w0, (ECAP+ECAP_ECCLR) + ldi REG_TMP1.w2, 0xffff + sbco ®_TMP1.w2, PWMSS1_CONST, REG_TMP1.w0, 2 + ;sbco ®_TMP1.w2, PWMSS2_CONST, REG_TMP1.w0, 2 +;HINT: we have some processing time here (140 cycles) +;go to V-Frame callback on transport layer + qbbc datalink_transport_no_v_frame_2, H_FRAME.flags, FLAG_NORMAL_FLOW +; Check if it V-Frame is complete (and currently the header for first H-Frame is +; being sent) -> state rx0 since we wait for processing v-frame in beginning of +; next frame and not at end of frame in rx7. If yes, start the V-frame +; processing. It will be completed in next H-Frame (State rx1). Therefore the +; V-frame processing is split into two parts : transport_on_v_frame and +; transport_on_v_frame_2. + qbne datalink_transport_no_v_frame, LOOP_CNT.b2, 8 + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0xff + .endif + jmp transport_on_v_frame +datalink_transport_on_v_frame_done: + +datalink_transport_no_v_frame: +; Check if the first H-Frame is complete (and currently the header for second H-Frame +; is being sent). If yes, perform the remaining part of V-frame processing + qbne datalink_transport_no_v_frame_2, LOOP_CNT.b2, 7 + .if $defined("HDSL_MULTICHANNEL") + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + .endif + jmp transport_on_v_frame_2 + +datalink_transport_on_v_frame_done_2: +datalink_transport_no_v_frame_2: + +;check if we have an EXTRA period + qbeq send_header_no_extra, EXTRA_SIZE, 0 + +;********************************************************************************; + ;extra value decide starts + qbeq num_pulses_is_one3, NUM_PULSES, 1 + mov EXTRA_SIZE_SELF, EXTRA_SIZE + ldi EXTRA_EDGE_SELF, 0 + qba extra_value_decided +num_pulses_is_one3: + mov EXTRA_SIZE_SELF, EXTRA_SIZE_COMP + mov EXTRA_EDGE_SELF, EXTRA_EDGE_COMP +extra_value_decided: + ;extra value decide ends + ;remainder increament logic starts + lbco ®_TMP0.b0, MASTER_REGS_CONST, SYNC_EXTRA_REMAINDER, 1 ;reload ES + qbgt remainder_increament_done1, REG_TMP0.b0, NUM_PULSES + add EXTRA_SIZE_SELF, EXTRA_SIZE_SELF, 1 +remainder_increament_done1: + ;remainder increament logic ends + qbne extra_edge_calculation_for_self_done1, EXTRA_EDGE_SELF, 0 + sub EXTRA_SIZE_SELF, EXTRA_SIZE_SELF, 1 + ldi EXTRA_EDGE_SELF, 0xFF +extra_edge_calculation_for_self_done1: + qba send_header_extra_not_too_large + +send_header_extra_not_too_large: +;limit STUFFING + qbge send_header_no_cap_stuffing, NUM_STUFFING, MAX_STUFFING + ldi NUM_STUFFING, MAX_STUFFING +send_header_no_cap_stuffing: + ;qba send_header_encode + .if $defined(EXT_SYNC_ENABLE_DEBUG) + lbco ®_TMP0, c25, 0, 4 + add REG_TMP0,REG_TMP0,4 + READ_CYCLCNT REG_TMP1 + ;lbco ®_TMP1, c1, 0x10, 4 + sbco ®_TMP1, c25, REG_TMP0, 4 + sbco ®_TMP0, c25, 0, 4 + .endif + +;read cyclecount + READ_CYCLCNT REG_TMP1 + .if $defined(EXT_SYNC_ENABLE) + qbeq modified_header_wait, MODIFIED_HEADER_STARTED, 1 + ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9-4-10) + qba modified_header_wait_done +modified_header_wait: + ldi REG_TMP0, (11*(CLKDIV_NORMAL+1)) +modified_header_wait_done: + .else + ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9-4-4) + .endif + sub REG_TMP0, REG_TMP0, REG_TMP1 + WAIT REG_TMP0 +;reset ECAP INT +send_header_extra_no_wait: + .if !$defined("HDSL_MULTICHANNEL") + TX_CLK_DIV CLKDIV_FAST, REG_TMP0 + .endif + sub REG_TMP1.b0, EXTRA_SIZE_SELF, 1 +send_header_extra_loop: + .if !$defined("HDSL_MULTICHANNEL") + WAIT_TX_FIFO_FREE + .endif + PUSH_FIFO_CONST 0xff + sub REG_TMP1.b0, REG_TMP1.b0, 1 + qbne send_header_extra_loop, REG_TMP1.b0, 0 + ldi REG_TMP0, (11*(CLKDIV_FAST+1)-0) +;send last extra with fine granularity + .if !$defined("HDSL_MULTICHANNEL") + WAIT_TX_FIFO_FREE + .endif + PUSH_FIFO EXTRA_EDGE_SELF + +send_header_extra_no_edge: +;reset clock to normal frequency + .if $defined("HDSL_MULTICHANNEL") + mov FIFO_L,REG_TMP11.b0 + PUSH_FIFO_8x FIFO_L + .else + WAIT_TX_FIFO_FREE + PUSH_FIFO REG_TMP11.b0 +;skip synch pulse measurement if we generate pulse ourself + WAIT REG_TMP0 +send_header_no_wait_after_synch: + TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 + .endif ;HDSL_MULTICHANNEL + + + .if $defined(EXT_SYNC_ENABLE) +;**********************************************************************************************; +;pseudo code: +;we just pushed the extra edge so now is the time to take the time capture. +;from the experiments 12 cycle latency for read so adjust for that. +;also one more thing to consider is that EXTRA_EDGE is not always 0xFF. +;It can take values, FF, FC,F8, F0, E0, C0, 80 etc. so we need to adjust for +;that also to get the exact timing of extra edge fall. +; +;iep_time = read_iep(); +;iep_time = iep_time + 12 ; //latency adjustment_done +;if(EXTRA_EDGE == 0xFF) +;{ +; ;do nothing +;} +;if(EXTRA_EDGE == 0xFE) +;{ +; ;each bit in extra edge is 3 pru cycle, simnce here +; ;extra edge came one bit early, so on from other possibilities. +; iep_time = iep_time - 3; +;} +;if(EXTRA_EDGE == 0xFC) +;{ +; iep_time = iep_time - 6; +;} +;if(EXTRA_EDGE == 0xF8) +;{ +; iep_time = iep_time - 9; +;} +;if(EXTRA_EDGE == 0xF0) +;{ +; iep_time = iep_time - 12; +;} +;if(EXTRA_EDGE == 0xE0) +;{ +; iep_time = iep_time - 15; +;} +;if(EXTRA_EDGE == 0xC0) +;{ +; iep_time = iep_time - 18; +;} +;if(EXTRA_EDGE == 0x80) +;{ +; iep_time = iep_time - 21; +;} +;extra_edge_fall_time = iep_time; + + + qbne num_pulses_is_not_one1, NUM_PULSES, 1 ;not the last frame of period + + lbco ®_TMP0, c1, 0x10, 4 + add REG_TMP0, REG_TMP0, 12 ;read offset + + qbeq adjustment_done, EXTRA_EDGE_SELF, 0xFF +is_val_FE: + qbne is_val_FC, EXTRA_EDGE_SELF, 0xFE + sub REG_TMP0, REG_TMP0, 3 + qba adjustment_done +is_val_FC: + qbne is_val_F8, EXTRA_EDGE_SELF, 0xFC + sub REG_TMP0, REG_TMP0, 6 + qba adjustment_done +is_val_F8: + qbne is_val_F0, EXTRA_EDGE_SELF, 0xF8 + sub REG_TMP0, REG_TMP0, 9 + qba adjustment_done +is_val_F0: + qbne is_val_E0, EXTRA_EDGE_SELF, 0xF0 + sub REG_TMP0, REG_TMP0, 12 + qba adjustment_done +is_val_E0: + qbne is_val_C0, EXTRA_EDGE_SELF, 0xE0 + sub REG_TMP0, REG_TMP0, 15 + qba adjustment_done +is_val_C0: + qbne is_val_80, EXTRA_EDGE_SELF, 0xC0 + sub REG_TMP0, REG_TMP0, 18 + qba adjustment_done +is_val_80: + qbne adjustment_done,EXTRA_EDGE_SELF, 0x80 + sub REG_TMP0, REG_TMP0, 21 + qba adjustment_done +adjustment_done: + sbco ®_TMP0, MASTER_REGS_CONST, EXTRA_EDGE_TIMESTAMP, 4 +num_pulses_is_not_one1: + qba send_header_extra_drive_cycle_check_end +;**********************************************************************************************; + .endif + +send_header_extra_drive_cycle_check_end: + qba send_header_encode +send_header_no_extra: +;push last bit of SAMPLE, 3 bits of CYCLE RESET and 4 bits EQUALIZATION + .if $defined("HDSL_MULTICHANNEL") + mov FIFO_L,REG_TMP11.b0 + PUSH_FIFO_2B_8x + PUSH_FIFO_2B_8x + .else + PUSH_FIFO REG_TMP11.b0 + .endif ;HDSL_MULTICHANNEL +send_header_encode: +;encode data + ldi REG_TMP11, (PDMEM00+LUT_5b6b_ENC) + lbbo ®_FNC.b3, REG_TMP11, REG_FNC.b0, 1 + LOOKUP_BITCNT REG_TMP0, REG_FNC.b3 + ldi REG_TMP11, (PDMEM00+LUT_3b4b_ENC) + lbbo ®_FNC.b2, REG_TMP11, REG_FNC.b1, 1 + LOOKUP_BITCNT REG_TMP1, REG_FNC.b2 +;check if subblock polarity is 0 + qbeq send_header_encode_first_subblock_end, REG_TMP0.b0, 3 +;calculate outcoming disparity (due to LUT structure, we lookup always neg. encodings->#0>=#1) +;calculate how many 0s are there more than 1s + lsl REG_TMP0.b0, REG_TMP0.b0, 1 + rsb REG_TMP0.b0, REG_TMP0.b0, 6 +;check line disparity for first block + qbbc send_header_encode_first_subblock_pos, DISPARITY, 7 + xor REG_FNC.b3, REG_FNC.b3, 0x3f + add DISPARITY, DISPARITY, REG_TMP0.b0 + qba send_header_encode_first_subblock_end +send_header_encode_first_subblock_pos: + sub DISPARITY, DISPARITY, REG_TMP0.b0 +send_header_encode_first_subblock_end: +;check line disparity for second block + qbbc send_header_encode_sec_subblock_pos, DISPARITY, 7 +;do not flip if subblock polarity is 0 + qbeq send_header_encode_sec_subblock_pos, REG_TMP1.b0, 2 + xor REG_FNC.b2, REG_FNC.b2, 0x0f + qba send_header_encode_sec_subblock_end +send_header_encode_sec_subblock_pos: +send_header_encode_sec_subblock_end: +;put together + lsl REG_FNC.b3, REG_FNC.b3, 2 + lsr REG_TMP0.b0, REG_FNC.b2, 2 + or REG_FNC.b3, REG_FNC.b3, REG_TMP0.b0 + lsl REG_FNC.b2, REG_FNC.b2, 6 + qbbc transport_layer_send_msg_done1, H_FRAME.flags, FLAG_NORMAL_FLOW + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_1_8x + PUSH_FIFO_2_8x + .endif + jmp transport_layer_send_msg +transport_layer_send_msg_done1: + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_2B_8x + PUSH_FIFO_2B_8x + .endif +transport_layer_send_msg_done: +;encoding end + .if $defined("HDSL_MULTICHANNEL") + mov FIFO_L,REG_FNC.b3 + PUSH_FIFO_8x FIFO_L + .else + WAIT_TX_FIFO_FREE + PUSH_FIFO REG_FNC.b3 + .endif ;HDSL_MULTICHANNEL + ;check if we receive or send 01 pattern + qbeq send_header_send_01_pattern, REG_FNC.b0, M_PAR_RESET + qbeq send_header_send_01_pattern, REG_FNC.b0, M_PAR_SYNC + qba send_header_dont_send_01 +send_header_send_01_pattern: +;send 01 pattern + CALL1 send_01 + qba send_header_end +send_header_dont_send_01: +;send last 2 parameter bits + WAIT_TX_FIFO_FREE +;overclock + qbbs send_header_dont_send_01_send_1, REG_FNC.b2, 7 + PUSH_FIFO_CONST 0x00 + qba send_header_dont_send_01_send_next +send_header_dont_send_01_send_1: + PUSH_FIFO_CONST 0xff +send_header_dont_send_01_send_next: + RESET_CYCLCNT + + .if $defined(EXT_SYNC_ENABLE_DEBUG) + lbco ®_TMP0, c25, 0, 4 + add REG_TMP0,REG_TMP0,4 + qble log_done1, REG_TMP0,255 + sbco ®_FNC, c25, REG_TMP0, 4 + sbco ®_TMP0, c25, 0, 4 +log_done1: + .endif + +;HINT: we have some processing time here (~74 cycles) ;6-19:sorry, not anymore, used for ext. sync suppport + +;***********************************************************************************************************; +;pseudocode: +;This code takes care of two things +;1)overhead adjustment per frame +;2)compensation for any diff between the sync pulse captured from latch and extra +;edge fall time computed by PRU + +;/*push in fifo M_PAR data to get time for processing. +;store the default values of extra and stuffing calculated in the beginning, to this we will +;make adjustments as per need*/ +;EXTRA_EDGE_COMP = EXTRA_EDGE +;EXTRA_SIZE_COMP = EXTRA_SIZE +;NUM_STUFFING_COMP = NUM_STUFFING + +;/*note all the time here is in terms of PRU cycle(4.44ns) unless specified*/ +;sync_pulse_rise_time = read_latch1_iep1_capture_register(); +;extra_edge_fall_time = read(); //it was read and stored in memory earliar +;diff_for_compensation = (sync_pulse_rise_time - extra_edge_fall_time)/3; // we have also converted cycles to bit here, by dividing by 3, note these overclocked bits we are talking about +;overhead_adjustment = 8 - TIME_REST_COMP; //coming from last cycle, overhead of child is (8 - parents TIME_REST) +;total_adjustment = (diff_for_compensation + overhead_adjustment); // we take care of sign etc. +;EXTRA_EDGE_COMP = EXTRA_EDGE_COMP (-/+) total_adjustment; //extra size may vary here, if extra_edge is not able to compensate fully +;if(EXTRA_SIZE_COMP < 4) +;{ +; EXTRA_SIZE_COMP = EXTRA_SIZE_COMP + 1; +; NUM_STUFFING_COMP = NUM_STUFFING_COMP - 1; +;} +;if(EXTRA_SIZE_COMP > 9) +;{ +; EXTRA_SIZE_COMP = EXTRA_SIZE_COMP - 1; +; NUM_STUFFING_COMP = NUM_STUFFING_COMP + 1; +;} +;in next cycle these _COMP values will be pushed to fifo and new values will be calculated and so on. +;one point to note here is if you need to adjust num of stuffing you need to do it from one cycle before. +;since stuffng for current cycle is not pushed yet, we can do that. +;that's one strategic importance of keeping this code here. + +comp_logic_starts: + .if $defined(EXT_SYNC_ENABLE) + ;compensation logic for diff between sync signal and extra edge starts; + + qbne num_pulses_is_not_one2, NUM_PULSES, 1 ;not the last frame of period + .if $defined(EXT_SYNC_ENABLE_DEBUG) + lbco ®_TMP0, c25, 0, 4 + add REG_TMP0,REG_TMP0,4 + READ_CYCLCNT REG_TMP1 + sbco ®_TMP1, c25, REG_TMP0, 4 + sbco ®_TMP0, c25, 0, 4 + .endif + mov EXTRA_EDGE_COMP, EXTRA_EDGE + mov EXTRA_SIZE_COMP, EXTRA_SIZE + mov NUM_STUFFING_COMP, NUM_STUFFING + + lbco ®_TMP0, MASTER_REGS_CONST, EXTRA_EDGE_TIMESTAMP, 4 + lbco ®_TMP1, IEP1_BASE_CONST, 0x50, 4 + qbge extra_edge_ahead, REG_TMP1 ,REG_TMP0 + mov REG_TMP2, REG_TMP0 + sub REG_TMP0, REG_TMP1, REG_TMP0 + + .if $defined(EXT_SYNC_ENABLE_DEBUG) + lbco ®_TMP1, c25, 0, 4 + add REG_TMP1,REG_TMP1,4 + qble log_1_done, REG_TMP1, 255 + sbco ®_TMP0, c25, REG_TMP1, 4 + sbco ®_TMP1, c25, 0, 4 +log_1_done: + .endif + ldi REG_TMP2, MAX_ALLOWED_CYCLE_DIFF + qble cycle_diff_more_than_max_allowed, REG_TMP0 ,REG_TMP2 + qbge no_capping1, REG_TMP0 ,CAPPING_CYCLE_DIFF + ldi REG_TMP0 , CAPPING_CYCLE_DIFF + ;qbge compensation_not_needed_this_cycle, REG_TMP0 ,2 + +no_capping1: + mov REG_TMP1, REG_FNC ;taking backup + mov REG_FNC.w0, REG_TMP0 + ldi REG_FNC.w2, 3 + CALL1 int_div + mov REG_TMP0.b0, REG_FNC.b2 + qbeq no_reminder1, REG_FNC.w0, 0 + add REG_TMP0.b0, REG_TMP0.b0,1 +no_reminder1: + mov REG_FNC, REG_TMP1 ;reloading orig value + qba self_overhead_more1 +extra_edge_ahead: + mov REG_TMP2, REG_TMP0 + sub REG_TMP0, REG_TMP0, REG_TMP1 + .if $defined(EXT_SYNC_ENABLE_DEBUG) + lbco ®_TMP1, c25, 0, 4 + add REG_TMP1,REG_TMP1,4 + sbco ®_TMP0, c25, REG_TMP1, 4 + sbco ®_TMP1, c25, 0, 4 + .endif + ldi REG_TMP2, MAX_ALLOWED_CYCLE_DIFF + qble cycle_diff_more_than_max_allowed, REG_TMP0 ,REG_TMP2 + qbge no_capping2, REG_TMP0 ,CAPPING_CYCLE_DIFF + ldi REG_TMP0 , CAPPING_CYCLE_DIFF +no_capping2: + mov REG_TMP1, REG_FNC ;taking backup + mov REG_FNC.w0, REG_TMP0 + ldi REG_FNC.w2, 3 + CALL1 int_div + mov REG_TMP0.b0, REG_FNC.b2 + qbeq no_reminder2, REG_FNC.w0, 0 + add REG_TMP0.b0, REG_TMP0.b0, 1 +no_reminder2: + mov REG_FNC, REG_TMP1 ;reloading orig value + qba child_overhead_more1 +cycle_diff_more_than_max_allowed: + ;halt ;enable to debug jitter out of bound issues + ldi REG_TMP0.b0, 0 ;this is the case of iep wraparound between two readings. happens once in 3-4 hours, let's not waste cycles here + ;by taking care of wraparound calculation, let's just ignore this reading. + +child_overhead_more1: + ldi REG_TMP1.b0, 8 + sub REG_TMP1.b0, REG_TMP1.b0, TIME_REST_COMP + qbne time_rest_comp_not_8_1, REG_TMP1.b0, 8 + ldi REG_TMP1.b0, 0 +time_rest_comp_not_8_1: + mov TIME_REST_COMP, TIME_REST + + add TIME_REST_COMP, TIME_REST_COMP, 16 + sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 2 + sub TIME_REST_COMP, TIME_REST_COMP, REG_TMP0.b0 + sub TIME_REST_COMP, TIME_REST_COMP, REG_TMP1.b0 + qba check_time_rest_size_violation1 +self_overhead_more1: + ldi REG_TMP1.b0, 8 + sub REG_TMP1.b0, REG_TMP1.b0, TIME_REST_COMP + qbne time_rest_comp_not_8_2, REG_TMP1.b0, 8 + ldi REG_TMP1.b0, 0 +time_rest_comp_not_8_2: + mov TIME_REST_COMP, TIME_REST + + add TIME_REST_COMP, TIME_REST_COMP, 8 + sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 1 + add TIME_REST_COMP, TIME_REST_COMP, REG_TMP0.b0 + + sub TIME_REST_COMP, TIME_REST_COMP, REG_TMP1.b0 + +check_time_rest_size_violation1: + qbge comp_done1, TIME_REST_COMP, 7 + add EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 1 + sub TIME_REST_COMP, TIME_REST_COMP, 8 + qbge comp_done1, TIME_REST_COMP, 7 + add EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 1 + sub TIME_REST_COMP, TIME_REST_COMP, 8 +comp_done1: + mov REG_TMP0.b1, TIME_REST_COMP + ldi EXTRA_EDGE_COMP, 0 + qbeq extra_edge_bit_setting_loop_end1, REG_TMP0.b1, 0 + ldi REG_TMP0.b2, 7 +extra_edge_bit_setting1: + set EXTRA_EDGE_COMP, EXTRA_EDGE_COMP, REG_TMP0.b2 + sub REG_TMP0.b1, REG_TMP0.b1, 1 + sub REG_TMP0.b2, REG_TMP0.b2, 1 + qblt extra_edge_bit_setting1, REG_TMP0.b1, 0 +extra_edge_bit_setting_loop_end1: + mov REG_TMP0.b0, EXTRA_SIZE_COMP + qbeq check_if_extra_remainder, EXTRA_EDGE_COMP, 0 + add REG_TMP0.b0, REG_TMP0.b0, 1 +check_if_extra_remainder: + lbco ®_TMP0.b1, MASTER_REGS_CONST, SYNC_EXTRA_REMAINDER, 1 ;reload ES + qbeq send_header_extra_too_small1, REG_TMP0.b1, 0 + add REG_TMP0.b0, REG_TMP0.b0, 1 ;there is an extra remainder +send_header_extra_too_small1: + qble send_header_extra_not_too_small1, REG_TMP0.b0, 4 ;too small extra window + add EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 6 + sub NUM_STUFFING_COMP, NUM_STUFFING_COMP, 1 +send_header_extra_not_too_small1: + qbge extra_size_validation_done1, REG_TMP0.b0, 9 ;too large extra window + sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 6 + add NUM_STUFFING_COMP, NUM_STUFFING_COMP, 1 +extra_size_validation_done1: +num_pulses_is_not_one2: + ;compensation logic for diff between sync signal and extra edge ends; + .endif +;***********************************************************************************************************; +comp_logic_ends: + + qbeq send_header_end, REG_FNC.b0, M_PAR_RESET + qbeq send_header_end, REG_FNC.b0, M_PAR_SYNC + + .if !$defined("HDSL_MULTICHANNEL") + qbbc transport_layer_recv_msg_done, H_FRAME.flags, FLAG_NORMAL_FLOW +;HINT: we have processing time here (~168 cycles) + jmp transport_layer_recv_msg +transport_layer_recv_msg_done: + READ_CYCLCNT REG_TMP1 + ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9) + sub REG_TMP0, REG_TMP0, REG_TMP1 + WAIT REG_TMP0 + TX_CLK_DIV CLKDIV_FAST, r0 + .endif ;HDSL_MULTICHANNEL + + qbbs send_header_dont_send_01_send_11, REG_FNC.b2, 6 + PUSH_FIFO_CONST 0x00 + ldi LAST_BIT_SENT, 0 + .if $defined(EXT_SYNC_ENABLE) + ldi REG_TMP2.b0, 0x1F + ;ldi REG_SCRATCH, P0EDRXCFG + sbco ®_TMP2.b0, ICSS_CFGx, EDRXCFG, 1 + .endif + qba send_header_dont_send_01_send_next1 +send_header_dont_send_01_send_11: + PUSH_FIFO_CONST 0xff + ldi LAST_BIT_SENT, 1 + .if $defined(EXT_SYNC_ENABLE) + ldi REG_TMP2.b0, 0x17 + ;ldi REG_SCRATCH, P0EDRXCFG + sbco ®_TMP2.b0, ICSS_CFGx, EDRXCFG, 1 + .endif +send_header_dont_send_01_send_next1: + .if $defined("HDSL_MULTICHANNEL") + qbbc transport_layer_recv_msg_done, H_FRAME.flags, FLAG_NORMAL_FLOW +;HINT: we have processing time here (~168 cycles) + jmp transport_layer_recv_msg +transport_layer_recv_msg_done: + READ_CYCLCNT REG_TMP1 + ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9) + sub REG_TMP0, REG_TMP0, REG_TMP1 + ;WAIT REG_TMP0 + NOP_2 + NOP_2 + NOP_2 + TX_CLK_DIV_WAIT CLKDIV_FAST, r0 +;leave overclocked to be able to reduce transmission delay + .endif ;single channel +send_header_sync_wait: +send_header_end: + RET +;-------------------------------------------------------------------------------------------------- +;Function: send_stuffing (RET_ADDR) +;This function sends the trailer (data after slave answer: STUFFING) +;input: +;output: +;modifies: +; REG_TMP0, REG_FNC +;-------------------------------------------------------------------------------------------------- +send_stuffing: + .if $defined(EXT_SYNC_ENABLE) + mov REG_TMP11, RET_ADDR1 + ;do calc + ;stuffing value decide starts + qbeq num_pulses_is_one, NUM_PULSES, 1 + mov REG_FNC.b3, NUM_STUFFING + qba stuffing_value_decided +num_pulses_is_one: + mov REG_FNC.b3, NUM_STUFFING_COMP +stuffing_value_decided: + ;stuffing value decide ends + ;remainder increament logic starts + lbco ®_TMP0.b0, MASTER_REGS_CONST, SYNC_STUFFING_REMAINDER, 1 ;reload ES + qbgt remainder_increament_done, REG_TMP0.b0, NUM_PULSES + add REG_FNC.b3, REG_FNC.b3, 1 +remainder_increament_done: + ;remainder increament logic ends + ;ES reload starts + sub NUM_PULSES, NUM_PULSES, 1 + qbne num_pulses_non_zero, NUM_PULSES, 0 + lbco &NUM_PULSES, MASTER_REGS_CONST, SYNC_CTRL, 1 ;reload ES +num_pulses_non_zero: + ;ES reload ends + qbeq send_stuffing_no_stuffing, REG_FNC.b3, 0 +;check if we have stuffing + READ_CYCLCNT REG_TMP0 + qbeq learn_state_started, LEARN_STATE_STARTED, 1 + rsb REG_TMP2, REG_TMP0, (5*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4) + qba calculation_for_wait_done +learn_state_started: + ;lbco ®_TMP1, c1, 0x10, 4 + rsb REG_TMP2, REG_TMP0, (4*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4) +calculation_for_wait_done: + nop + .else + mov REG_TMP11, RET_ADDR1 + qbeq send_stuffing_no_stuffing, NUM_STUFFING, 0 +;check if we have stuffing + ;halt + READ_CYCLCNT REG_TMP0 + rsb REG_TMP2, REG_TMP0, (5*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4) + mov REG_FNC.b3, NUM_STUFFING + .endif;EXT_SYNC_ENABLE + PUSH_FIFO_CONST 0x0b + WAIT REG_TMP2 +;send first 4 zeroes with double frequency +;synchronize with clock +send_stuffing_sync_clk: + ;ldi REG_SCRATCH, P0EDTXCFG + lbco ®_TMP1, ICSS_CFGx, EDTXCFG, 4 + .if $defined(CHANNEL_2) + qbbc send_stuffing_sync_clk, REG_TMP1, 10 + .endif + .if $defined(CHANNEL_1) + qbbc send_stuffing_sync_clk, REG_TMP1, 9 + .endif + .if $defined(CHANNEL_0) + qbbc send_stuffing_sync_clk, REG_TMP1, 8 + .endif +send_stuffing_first: + .if $defined("HDSL_MULTICHANNEL") + TX_CLK_DIV_WAIT CLKDIV_DOUBLE, REG_TMP1 + .else + TX_CLK_DIV CLKDIV_DOUBLE, REG_TMP1 + .endif ;HDSL_MULTICHANNEL +;wait 4 cycles + ldi REG_FNC.w0, CLKDIV_NORMAL + ldi REG_FNC.b2, 4 + CALL1 switch_clk + sub REG_FNC.b3, REG_FNC.b3, 1 + qbeq send_stuffing_no_stuffing, REG_FNC.b3, 0 + +send_stuffing_loop: + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x0b +;wait 4 cycles + ldi REG_FNC.w0, CLKDIV_DOUBLE + ldi REG_FNC.b2, 4 + CALL1 switch_clk +;wait 4 cycles + ldi REG_FNC.w0, CLKDIV_NORMAL + ldi REG_FNC.b2, 3 + CALL1 switch_clk + sub REG_FNC.b3, REG_FNC.b3, 1 + qbne send_stuffing_loop, REG_FNC.b3, 0 +send_stuffing_no_stuffing: + mov RET_ADDR1, REG_TMP11 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: send_trailer (RET_ADDR) +;This function sends the trailer (data after slave answer: TRAILER) +;gain: 5*24-6=114 cycles +;input: +;output: +;modifies: +; REG_TMP0, REG_FNC +;-------------------------------------------------------------------------------------------------- +send_trailer: +;already overclocked +;reduce trailer length by a few ns to compensate for a slightly transmission start delay < 30ns +;so: first reduce from higher clockrate to lower clock rate for 1 cycle, then set to normal clockrate again +;send TRAILER + ;PUSH 8 bytes for 1 byte data (0x03) in FIFO + .if $defined("HDSL_MULTICHANNEL") + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + PUSH_FIFO_CONST 0x00 + TX_CHANNEL + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + .else + PUSH_FIFO_CONST 0x03 + TX_CHANNEL + .endif ;HDSL_MULTICHANNEL + ;determine DELAY Master Register (also used as 2 dummy cycles) + lsl REG_TMP1.b0, RSSI, 4 + or REG_TMP1.b0, REG_TMP1.b0, SLAVE_DELAY + +; additional delay here shortens the the first trailer byte + NOP_2 + NOP_2 + NOP_2 + .if !$defined("HDSL_MULTICHANNEL") + .if $defined("FREERUN_300_MHZ") + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + .endif + .endif + .if !$defined("HDSL_MULTICHANNEL") + TX_CLK_DIV CLKDIV_SLOW, REG_TMP0 + .endif +;reset DISPARITY + ldi DISPARITY, 0 + ;store RSSI/DELAY (also used as 2 dummy cycles) + sbco ®_TMP1.b0, MASTER_REGS_CONST, DELAY, 1 +;update qm when rssi < 2 + qble send_trailer_dont_update_qm, RSSI, 2 +;save return addr + mov REG_TMP11.w0, RET_ADDR1 + qm_sub 4 +;restore return addr + mov RET_ADDR1, REG_TMP11.w0 +send_trailer_dont_update_qm: + .if !$defined("HDSL_MULTICHANNEL") + TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 + .endif +;syn with clock before resetting counter + .if !$defined("HDSL_MULTICHANNEL") + WAIT_CLK_LOW REG_TMP0 + .endif + RESET_CYCLCNT + RET1 +;-------------------------------------------------------------------------------------------------- +datalink_abort: + qbbs datalink_abort_no_wait, r30, RX_ENABLE ;changed here from 24 to 26 + WAIT_TX_DONE +datalink_abort_no_wait: + lbco ®_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1 + add REG_TMP0.b0, REG_TMP0.b0, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1 +; Set EVENT_PRST in EVENT register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + set REG_TMP0.w0, REG_TMP0.w0, EVENT_PRST +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int2, REG_TMP0.w2, EVENT_PRST +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int2: +; Set EVENT_S_PRST in EVENT_S register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 + set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + qbbc update_events_no_int18, REG_TMP0.b1, EVENT_S_PRST +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ4 +update_events_no_int18: + +; Set PRST bits in ONLINE_STATUS registers + lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST + set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST + set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST + sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + jmp datalink_reset +;-------------------------------------------------------------------------------------------------- +;Function: switch_clk (RET_ADDR1) +; +;input: +; REG_FNC.w0: new clk_div +; REG_FNC.b2: #of cycles to wait before switching +;output: +;modifies: +; REG_TMP0, REG_FNC +;-------------------------------------------------------------------------------------------------- +switch_clk: + WAIT_CLK_LOW REG_TMP0 + WAIT_CLK_HIGH REG_TMP0 + sub REG_FNC.b2, REG_FNC.b2, 1 + qbne switch_clk, REG_FNC.b2, 1 + WAIT_CLK_LOW REG_TMP0 + ;ldi REG_SCRATCH, P0EDTXCFG+2 + sbco ®_FNC.w0, ICSS_CFGx, EDTXCFG+2, 2 + WAIT_CLK_HIGH REG_TMP0 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: qm_add (RET_ADDR1) +;Adds value to Quality Monitor and resets connection if necessary +; 15+9=24 cycles +;input: +; REG_FNC.b0: value +;modifies: +; REG_TMP0, REG_FNC +;-------------------------------------------------------------------------------------------------- +qm_add: + .if 1 + and QM, QM, 0x7f +;check if negative (bit 7 indicates there is a link -> check bit 6) + qbbc qm_add_no_reset, QM, 6 + ; set EDIO28 + ;ldi32 REG_TMP1, 0x02e300 + ;sbbo ®_TMP1.b0, REG_TMP1, 0x13, 1 + halt + ldi QM, 0 +;update MASTER_QM + sbco &QM, MASTER_REGS_CONST, MASTER_QM, 1 + qba datalink_abort +qm_add_no_reset: +;max value is 15 + qbge qm_add_no_capping, QM, QM_MAX + ldi QM, QM_MAX +qm_add_no_capping: +;check if we need to set event flag + qble qm_add_below_not_14, QM, 14 +; Defer the events register update to later +; Set EVENT_UPDATE_PENDING_QMLW to indicate a low QM value + lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + set REG_TMP0.b0, REG_TMP0.w0, EVENT_UPDATE_PENDING_QMLW + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 +qm_add_below_not_14: + or QM, QM, (1<<7) +;update MASTER_QM + sbco &QM, MASTER_REGS_CONST, MASTER_QM, 1 +qm_add_end: + .endif + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: wait_delay (RET_ADDR1) +;functions waits to compensate slave delay if necessary +;input: +;modifies: +;-------------------------------------------------------------------------------------------------- +wait_delay: + WAIT_TX_DONE + .if $defined("FREERUN_300_MHZ") + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + NOP_2 + .endif + .if $defined("HDSL_MULTICHANNEL") + NOP_2 + NOP_2 + NOP_2 + NOP_2 + .endif ;HDSL_MULTICHANNEL + +; same code as in learn +; with 4 or 3 bit encoder does not respond after time, starts working with 2 set it to 1 +wait_on_rx_transtion_in_wait_delay: + RX_EN + ;measure passed time during receive and wait appropriately at the end -> reset cyclecount + RESET_CYCLCNT + +;reset RSSI + ldi RSSI, 12 +; wait for slave delay in bits + qbeq wait_delay_no_wait, SLAVE_DELAY, 0 + mov REG_TMP1.b0, SLAVE_DELAY +wait_delay_recv_wire: + qbbc wait_delay_recv_wire, r31, RX_VALID_FLAG + POP_FIFO REG_TMP0.b0 + CLEAR_VAL + sub REG_TMP1.b0,REG_TMP1.b0,1 + qbne wait_delay_recv_wire, REG_TMP1.b0, 0 + +wait_delay_no_wait: + RET1 + +;-------------------------------------------------------------------------------------------------- +;Function: calc_rssi (RET_ADDR1) +;Calculates RSSI based on current EDGES +;input: CUR_EDGES +;output: RSSI +;-------------------------------------------------------------------------------------------------- +calc_rssi: + ldi REG_TMP0, (PDMEM00 + 0x5e4);LUT_RSSI) + lbbo ®_TMP0, REG_TMP0, CUR_EDGES, 1 +;store new rssi only if value is smaller + qblt calc_rssi_discard, REG_TMP0.b0, RSSI + mov RSSI, REG_TMP0.b0 +calc_rssi_discard: + RET1 +;-------------------------------------------------------------------------------------------------- diff --git a/source/motor_control/position_sense/hdsl/firmware/datalink_init.asm b/source/motor_control/position_sense/hdsl/firmware/datalink_init.asm new file mode 100644 index 0000000..57c2bf2 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/datalink_init.asm @@ -0,0 +1,891 @@ + +; +; Copyright (C) 2021-2023 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + + .include "memory.inc" + .include "defines.inc" + .include "macros.inc" + .ref transport_init + .ref qm_add + .ref calc_rssi + .ref send_stuffing + .ref send_header + .ref send_trailer + .ref wait_delay + .ref datalink_loadfw + .ref recv_dec + .ref datalink_wait_vsynch + .global datalink_reset + .global datalink_init_start + .global send_01 + .global int_div + + .sect ".text" + +relocatable0: + +datalink_init_start: +;State RESET + zero &r0, 124 +;send 2 times +datalink_reset: + +;setup ICSS encoder peripheral for Hiperface DSL + ldi DISPARITY, 0x00 + TX_EN + SET_TX_CH0 + REINIT_TX + TX_FRAME_SIZE 0, REG_TMP0 + .if $defined("HDSL_MULTICHANNEL") + TX_CLK_DIV CLKDIV_FAST, REG_TMP0 + .else + TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 + .endif + zero &H_FRAME, (4*2) +;init transport layer here + CALL transport_init +;QualityMonitor is initialized with 8 + ldi QM, 8 +;free running mode frame size is 108 + ldi EXTRA_SIZE, 0 + ldi NUM_STUFFING, 0 +;reset PRST bit in SYS_CTRL + lbco ®_TMP0, MASTER_REGS_CONST, SYS_CTRL, 1 + clr REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST + sbco ®_TMP0, MASTER_REGS_CONST, SYS_CTRL, 1 +;reset SAFE_CTRL register + zero ®_TMP0.b0, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_CTRL, 1 +; Write the fixed bits and reset PRST bits in ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2 +; In ONLINE_STATUS_D high, bit 2 is FIX0, bit 4 is FIX1 and bit 5 is FIX0 +; In ONLINE_STATUS_D low, bit 0 is FIX0 and bit 3 is FIX0 + lbco ®_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_D, 2 + ; clearing bits with fix0 and PRST bit + and REG_TMP0.w0, REG_TMP0.w0, ((~((1< vert == acc.b0 && par == acc.b1 && pipe.nibble0 == pipe.nibble1 +;second half of palindrome is actually our ENC_ID! + qbne datalink_abort2, H_FRAME.vert, H_FRAME_acc0 + qbne datalink_abort2, H_FRAME.s_par, H_FRAME_acc1 + and REG_TMP0.b0, H_FRAME.pipe, 0xf + lsr REG_TMP0.b1, H_FRAME.pipe, 4 + qbne datalink_abort2, REG_TMP0.b0, REG_TMP0.b1; +;now store the encoder ID + mov REG_TMP0.w0, H_FRAME.acc + mov REG_TMP0.b2, H_FRAME.pipe +;now in memory for master registers +;big endian format + mov REG_TMP1.b0, REG_TMP0.b2 + mov REG_TMP1.b1, REG_TMP0.b1 + mov REG_TMP1.b2, REG_TMP0.b0 + sbco ®_TMP1, MASTER_REGS_CONST, ENC_ID2, 3 +;Safe QM + set LINK bit, which means we have established a link +;just add 0 to QM to update + QM_ADD 0 +;Synchronization with Drive Cycle is enabled here! + set H_FRAME.flags, H_FRAME.flags, FLAG_DRIVE_SYNC +;-------------------------------------------------------------------------------------------------- +;State ID COMPUTE +datalink_id_compute: +;decode the ENC_ID here +;num of acc bits is always +8 + and NUM_ACC_BITS, REG_TMP0, 0x0f + add NUM_ACC_BITS, NUM_ACC_BITS, 8 +;num pos bits is +num acc bits + lsr NUM_ST_BITS, REG_TMP0, 4 + and NUM_ST_BITS, NUM_ST_BITS, 0x3f + add NUM_ST_BITS, NUM_ST_BITS, NUM_ACC_BITS + sub NUM_ST_BITS, NUM_ST_BITS, NUM_MT_BITS +;finding the mask for position + add REG_TMP0.b0, NUM_ST_BITS, NUM_MT_BITS + rsb REG_TMP0.b0, REG_TMP0.b0, 40 + ldi32 REG_TMP1, 0xffffffff + lsr REG_TMP1, REG_TMP1, REG_TMP0.b0 + sbco ®_TMP1, MASTER_REGS_CONST, MASK_POS, 4 + ;qba datalink_id_req + CALL1 send_stuffing + jmp datalink_wait_vsynch +;-------------------------------------------------------------------------------------------------- + +;-------------------------------------------------------------------------------------------------- +;Function: +;This functions receives data without deocoding. +;output: +; r20-r19: data +;-------------------------------------------------------------------------------------------------- +receive: + ldi LOOP_CNT.b0, 32 + CALL1 wait_delay + ldi REG_TMP0.w0, 0 + ldi REG_TMP11, (PDMEM00+0x5a4);LUT_B2B) + zero &r18, (4*5) +datalink_receive_signal_0_31_1: + qbbc datalink_receive_signal_0_31_1, r31, RX_VALID_FLAG + POP_FIFO REG_TMP0.b0 + CLEAR_VAL + sub LOOP_CNT.b0, LOOP_CNT.b0, 1 + qbbc datalink_receive_signal_0_31_received_0_1, REG_TMP0.w0, SAMPLE_EDGE + set r20, r20, LOOP_CNT.b0 +datalink_receive_signal_0_31_received_0_1: + mov REG_TMP0.b1, REG_TMP0.b0 +;get edges + lsr REG_TMP1.b0, REG_TMP0.w0, 1 + xor CUR_EDGES, REG_TMP1.b0, REG_TMP0.b0 + CALL1 calc_rssi + qbne datalink_receive_signal_0_31_1, LOOP_CNT.b0, 0 +;receive next bits + ldi LOOP_CNT.b0, 29 +datalink_receive_signal_32_60_1: + qbbc datalink_receive_signal_32_60_1, r31, RX_VALID_FLAG ;changed here from 24 to 26 + POP_FIFO REG_TMP0.b0 + CLEAR_VAL + sub LOOP_CNT.b0, LOOP_CNT.b0, 1 + qbbc datalink_receive_signal_32_60_received_0_1, REG_TMP0.w0, SAMPLE_EDGE + set r19, r19, LOOP_CNT.b0 +datalink_receive_signal_32_60_received_0_1: + mov REG_TMP0.b1, REG_TMP0.b0 +;get edges + lsr REG_TMP1.b0, REG_TMP0.w0, 1 + xor CUR_EDGES, REG_TMP1.b0, REG_TMP0.b0 + CALL1 calc_rssi + qbne datalink_receive_signal_32_60_1, LOOP_CNT.b0, 1 +datalink_receive_signal_last_1: + qbbc datalink_receive_signal_last_1, r31, RX_VALID_FLAG ;changed here from 24 to 26 + POP_FIFO REG_TMP0.b0 + qbbc datalink_receive_signal_last_received_0_1, REG_TMP0.w0, SAMPLE_EDGE + set r19, r19, 0 +datalink_receive_signal_last_received_0_1: + lsl r19, r19, 3 + CLEAR_VAL +; same delay code as in learn + ldi REG_TMP1, (74*CYCLES_BIT+7) ; -9 for 100 m + READ_CYCLCNT REG_TMP0 + qble receive_skip_wait, REG_TMP0, REG_TMP1 + sub REG_TMP0, REG_TMP1, REG_TMP0 + add r0,r0,1 + WAIT REG_TMP0 +receive_skip_wait: + TX_EN +; datalink_receive_signal_no_delay_wait_1: + CALL1 send_trailer + CALL1 send_stuffing + RET +;-------------------------------------------------------------------------------------------------- +;Function: sync_pulse (RET_ADDR1) +;functions bussy waits for sync pulse +;input: +;modifies: +;-------------------------------------------------------------------------------------------------- +;stores sync pulse period in R20 in unit of cycles +sync_pulse: + lbco ®_TMP1, c1, IEP_CAPR6_RISE, 4 +wait_next_pulse: + lbco &R20, c1, IEP_CAPR6_RISE, 4 + QBEQ wait_next_pulse, R20, REG_TMP1 + SUB R20, R20, REG_TMP1 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: int_div (RET_ADDR1) +;integer divides +;input: +; REG_FNC.w0: Number +; REG_FNC.w2: Divisor +;output: +; REG_FNC.w2: Result +; REG_FNC.w0: Rest +;modifies: +;-------------------------------------------------------------------------------------------------- +int_div: + ldi REG_TMP0, 0 +int_div_loop: + qbgt int_div_end, REG_FNC.w0, REG_FNC.w2 + sub REG_FNC.w0, REG_FNC.w0, REG_FNC.w2 + add REG_TMP0, REG_TMP0, 1 + qba int_div_loop +int_div_end: + mov REG_FNC.w2, REG_TMP0 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: check_test_pattern (RET_ADDR1) +;This function checks if the test pattern was received +;input: +; r18-r20: data +;output: +; REG_FNC.b0: 1 if true +;modifies: +; REG_TMP0, REG_FNC +;-------------------------------------------------------------------------------------------------- +check_test_pattern: +;load test pattern and mask from memory + lbco ®_TMP0, MASTER_REGS_CONST, TEST_PATTERN0, 12 +;rm switch bit + and REG_TMP11, r19, REG_TMP2 + ldi REG_TMP2, 0xff8 + and REG_TMP2, r19, REG_TMP2 + lsl REG_TMP2, REG_TMP2, 1 + or REG_TMP11, REG_TMP2, REG_TMP11 +;if found go to next step + qbne check_test_pattern_false, r20, REG_TMP0 + qbne check_test_pattern_false, REG_TMP11, REG_TMP1 +check_test_pattern_true: + ldi REG_FNC.b0, 1 + RET1 +check_test_pattern_false: + ldi REG_FNC.b0, 0 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: send_01 (RET_ADDR1) +;This function sends 01 pattern in RESET and SYNC state +;input: +; REG_FNC.b2: last two bits of parameter channel +;output: +;modifies: +;-------------------------------------------------------------------------------------------------- +send_01: +;send 01 pattern +;2 para bits, 1 switch bit, 5 slave bit + or REG_FNC.b2, REG_FNC.b2, 0x15;0bPPS10101 + .if $defined("HDSL_MULTICHANNEL") + mov FIFO_L,REG_FNC.b2 + PUSH_FIFO_8x FIFO_L + .else + PUSH_FIFO REG_FNC.b2 + .endif +;56+12 line delay slave bits + ldi REG_TMP0.b0, 8 +send_header_send_01_pattern_loop: + ;;PUSH 8 bytes for 1 byte data (0x55) in FIFO + WAIT_TX_FIFO_FREE + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0xff + .else + PUSH_FIFO_CONST 0x55 + .endif + sub REG_TMP0.b0, REG_TMP0.b0, 1 + qbne send_header_send_01_pattern_loop, REG_TMP0.b0, 0 +;send last 0101 (4 bits) + WAIT_TX_FIFO_FREE +;overclock(8x) + PUSH_FIFO_CONST 0x00 + ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9) + .if !$defined("HDSL_MULTICHANNEL") + WAIT REG_TMP0 + TX_CLK_DIV CLKDIV_FAST, REG_TMP0 + .endif + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0xff +;push TRAILER + ;PUSH 8 bytes for 1 byte data (0x03) in FIFO + WAIT_TX_FIFO_FREE + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + .else + PUSH_FIFO_CONST 0x03 + .endif + .if $defined("FREERUN_300_MHZ") + ldi REG_TMP0, (6*(CLKDIV_FAST+1)-8+2) + .else + ldi REG_TMP0, (6*(CLKDIV_FAST+1)-8) + .endif + .if !$defined("HDSL_MULTICHANNEL") + WAIT REG_TMP0 + TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 + ;wait to have same timing as send_trailer + ldi REG_TMP0, 30;6 + WAIT REG_TMP0 + .endif + + +;reset cyclecount + RESET_CYCLCNT + RET1 diff --git a/source/motor_control/position_sense/hdsl/firmware/defines.inc b/source/motor_control/position_sense/hdsl/firmware/defines.inc new file mode 100644 index 0000000..d8c5781 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/defines.inc @@ -0,0 +1,312 @@ + +; Copyright (C) 2021-2023 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + +;number of cycles for 1 bit + .if $defined("FREERUN_300_MHZ") +;number of cycles for 1 bit +CYCLES_BIT .set 32 +;clock divider +CLKDIV_225MHZ .set 0 +CLKDIV_FAST .set 3 +CLKDIV_FASTER .set 22 +CLKDIV_DOUBLE .set 15 +CLKDIV_NORMAL .set 31 +CLKDIV_HALF .set 63 +CLKDIV_SLOWER .set 82 +CLKDIV_SLOW .set 63 + + .else +;number of cycles for 1 bit +CYCLES_BIT .set 24 + +;clock divider +CLKDIV_225MHZ .set 0 +CLKDIV_FAST .set 2 +CLKDIV_FASTER .set 16 +CLKDIV_DOUBLE .set 11 +CLKDIV_NORMAL .set 23 +CLKDIV_HALF .set 47 +CLKDIV_SLOWER .set 61;60 +CLKDIV_SLOW .set 47;50;47 + + .endif + +;6 bits sync + 2 bits sample +SYNC .set 0x2f +;1 bit sample + 3 bit cycle_reset +CYCLE_RESET .set 0x06 +; cycle_reset + equalization in first state +FIRST_CYCLE_EQ .set ((0x06<<4) | 0x0a) +;8 bits trailer +TRAILER .set 0x03 +;line delay is 12 bits +LINE_DELAY .set 12 + +;m_par symbols +M_PAR_IDLE .set 0x10 +M_PAR_SYNC .set 0x19 +M_PAR_START .set 0x1a +M_PAR_LEARN .set 0x1b +M_PAR_CHECK .set 0x1c +M_PAR_IDREQ .set 0x1d +M_PAR_INIT .set 0x1e +M_PAR_RESET .set 0x1f +M_PAR_0x1 .set 0x01 +M_PAR_0x2 .set 0x02 +M_PAR_0x3 .set 0x03 +M_PAR_0x4 .set 0x04 +M_PAR_0x5 .set 0x05 +M_PAR_0x6 .set 0x06 +M_PAR_0x7 .set 0x07 +M_PAR_0x8 .set 0x08 +M_PAR_0x9 .set 0x09 +M_PAR_0xa .set 0x0a +M_PAR_0xb .set 0x0b +M_PAR_0xc .set 0x0c +M_PAR_0xd .set 0x0d +M_PAR_0xe .set 0x0e +M_PAR_0xf .set 0x0f + +;s_par symbols +S_PAR_IDLE .set 0x10 +S_PAR_SNAK .set 0x15 +S_PAR_LNAK .set 0x1a +S_PAR_INIT .set 0x1f + +;datalink parameters +LINK_TIMEOUT .set ((DELAY_BITS-3)*CYCLES_BIT) +DELAY_BITS .set 12 + +;FLAGS +FLAG_NORMAL_FLOW .set 1 +FLAG_MSYNC .set 2 +FLAG_ERR_ACC .set 3 +FLAG_ERR_VERT .set 4 +FLAG_ERR_SEC .set 5 +UPDATE_FPOS_WITH_SPOS .set 6 +MPAR_BUSY .set 7 +FLAG_DRIVE_SYNC .set 8 +FLAG_PARA_BUSY .set 9 +FLAG_WAIT_IDLE .set 10 + +FLAG_ERRORS .set ((~((1<_int_req +PRU0_ARM_IRQ .set (0x20 | PRU_ARM_EVENT0) + +PRU_ARM_EVENT1 .set (19 - 16) ;SYS_EVENT_19 is pr1_pru_mst_intr<3>_int_req +PRU0_ARM_IRQ1 .set (0x20 | PRU_ARM_EVENT1) + +PRU_ARM_EVENT2 .set (20 - 16) ;SYS_EVENT_20 is pr1_pru_mst_intr<4>_int_req +PRU0_ARM_IRQ2 .set (0x20 | PRU_ARM_EVENT2) + +PRU_ARM_EVENT3 .set (21 - 16) ;SYS_EVENT_21 is pr1_pru_mst_intr<5>_int_req +PRU0_ARM_IRQ3 .set (0x20 | PRU_ARM_EVENT3) + +; This interrupt is used for EVENT_S interrupt +PRU_ARM_EVENT4 .set (22 - 16) ;SYS_EVENT_22 is pr1_pru_mst_intr<6>_int_req +PRU0_ARM_IRQ4 .set (0x20 | PRU_ARM_EVENT4) + +;constants for event_h/l (event_h is saved in low part of register when read from memory!) +;event_h +EVENT_INT .set 7 +EVENT_SUM .set 6 +; EVENT_SCE is moved to EVENT_S_SCE +EVENT_POS .set 3 +; EVENT_VPOS is moved to EVENT_S_VPOS +EVENT_DTE .set 1 +EVENT_PRST .set 0 + +;event_l +EVENT_MIN .set (5+8) +EVENT_ANS .set (4+8) +EVENT_QMLW .set (2+8) +EVENT_FREL .set (1+8) +; EVENT_FRES is moved to EVENT_S_FRES + +;constants for event_s +EVENT_S_SINT .set 7 +EVENT_S_SSUM .set 6 +EVENT_S_SCE .set 5 +EVENT_S_VPOS .set 4 +EVENT_S_QMLW .set 3 +EVENT_S_PRST .set 2 +EVENT_S_MIN .set 1 +EVENT_S_FRES .set 0 + +; ONLINE_STATUS_D constants +; ONLINE_STATUS_D high byte +ONLINE_STATUS_D_INT .set 7 +ONLINE_STATUS_D_SUM .set 6 +ONLINE_STATUS_D_HIGH_BIT5_FIX0 .set 5 +ONLINE_STATUS_D_HIGH_BIT4_FIX1 .set 4 +ONLINE_STATUS_D_POS .set 3 +ONLINE_STATUS_D_HIGH_BIT2_FIX0 .set 2 +ONLINE_STATUS_D_DTE .set 1 +ONLINE_STATUS_D_PRST .set 0 +; ONLINE_STATUS_D low byte +ONLINE_STATUS_D_POSTX_HIGH .set (7+8) +ONLINE_STATUS_D_POSTX_LOW .set (6+8) +ONLINE_STATUS_D_MIN .set (5+8) +ONLINE_STATUS_D_ANS .set (4+8) +ONLINE_STATUS_D_LOW_BIT3_FIX0 .set (3+8) +ONLINE_STATUS_D_QMLW .set (2+8) +ONLINE_STATUS_D_FREL .set (1+8) +ONLINE_STATUS_D_LOW_BIT0_FIX0 .set (0+8) + +; ONLINE_STATUS_1 constants +; ONLINE_STATUS_1 high byte +ONLINE_STATUS_1_SINT .set 7 +ONLINE_STATUS_1_SSUM .set 6 +ONLINE_STATUS_1_SCE .set 5 +ONLINE_STATUS_1_HIGH_BIT4_FIX1 .set 4 +ONLINE_STATUS_1_HIGH_BIT3_FIX0 .set 3 +ONLINE_STATUS_1_VPOS .set 2 +ONLINE_STATUS_1_HIGH_BIT1_FIX0 .set 1 +ONLINE_STATUS_1_PRST .set 0 +; ONLINE_STATUS_1 low byte +ONLINE_STATUS_1_POSTX_HIGH .set (7+8) +ONLINE_STATUS_1_POSTX_LOW .set (6+8) +ONLINE_STATUS_1_MIN .set (5+8) +ONLINE_STATUS_1_LOW_BIT4_FIX0 .set (4+8) +ONLINE_STATUS_1_LOW_BIT3_FIX0 .set (3+8) +ONLINE_STATUS_1_QMLW .set (2+8) +ONLINE_STATUS_1_LOW_BIT1_FIX0 .set (1+8) +ONLINE_STATUS_1_FRES .set (0+8) + +; ONLINE_STATUS_2 constants + +; ONLINE_STATUS_2 high byte +ONLINE_STATUS_2_HIGH_BIT7_FIX0 .set 7 +ONLINE_STATUS_2_SUM2 .set 6 +ONLINE_STATUS_2_SCE2 .set 5 +ONLINE_STATUS_2_HIGH_BIT4_FIX1 .set 4 +ONLINE_STATUS_2_HIGH_BIT3_FIX0 .set 3 +ONLINE_STATUS_2_VPOS2 .set 2 +ONLINE_STATUS_2_HIGH_BIT1_FIX0 .set 1 +ONLINE_STATUS_2_PRST .set 0 + +; ONLINE_STATUS_2 low byte +ONLINE_STATUS_2_POSTX_HIGH .set (7+8) +ONLINE_STATUS_2_POSTX_LOW .set (6+8) +ONLINE_STATUS_2_LOW_BIT5_FIX0 .set (5+8) +ONLINE_STATUS_2_LOW_BIT4_FIX0 .set (4+8) +ONLINE_STATUS_2_LOW_BIT3_FIX0 .set (3+8) +ONLINE_STATUS_2_QMLW .set (2+8) +ONLINE_STATUS_2_LOW_BIT1_FIX0 .set (1+8) +ONLINE_STATUS_2_LOW_BIT0_FIX0 .set (0+8) + +; STATUS2 constants +STATUS2_TOG2 .set 7 +STATUS2_TEST2 .set 6 +STATUS2_ERR2 .set 5 + +;SYS_CTRL constants +SYS_CTRL_PRST .set 7 +SYS_CTRL_MRST .set 6 +SYS_CTRL_FRST .set 5 +SYS_CTRL_LOOP .set 4 +SYS_CTRL_PRDY .set 3 +SYS_CTRL_SPPE .set 2 +SYS_CTRL_SPOL .set 1 +SYS_CTRL_OEN .set 0 + +;SAFE_CTRL constants +SAFE_CTRL_PRST .set 7 +SAFE_CTRL_MRST .set 6 + +;STUFFING is at max. 26*6 bits +MAX_STUFFING .set 26 + +;Num. of LOADFW states (CODE_SIZE/NUM_LOADFW = size of code per load) +NUM_LOADFW .set 1 + +;MAX cycle differene allowed between the SYNC pulse and extra edge +MAX_ALLOWED_CYCLE_DIFF .set 10000 + +;MAX cycle differene allowed between the SYNC pulse and extra edge +CAPPING_CYCLE_DIFF .set 18 diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js new file mode 100644 index 0000000..7522b8b --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; \ No newline at end of file diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am243x.js b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am243x.js new file mode 100644 index 0000000..b90e01b --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am243x.js @@ -0,0 +1,98 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "main.asm", + "datalink.asm", + "datalink_init.asm", + "transport.asm", + "utils.asm", + "hdsl_master_icssg_hexpru.cmd", + "hdsl_master_icssg.cmd", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_0", + "ICSS_G_V_1_0", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_freerun_225_mhz"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 225 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am64x.js b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am64x.js new file mode 100644 index 0000000..a82d79a --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am64x.js @@ -0,0 +1,98 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "main.asm", + "datalink.asm", + "datalink_init.asm", + "transport.asm", + "utils.asm", + "hdsl_master_icssg_hexpru.cmd", + "hdsl_master_icssg.cmd", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_0", + "ICSS_G_V_1_0", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_freerun_225_mhz"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 225 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..f155222 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,86 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..86b336f --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..c6637d0 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_225_mhz/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(/// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_0", + "ICSS_G_V_1_0", + "FREERUN_300_MHZ", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_300_mhz_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_300_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_freerun_300_mhz"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/.project/project_am64x.js b/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/.project/project_am64x.js new file mode 100644 index 0000000..6351a66 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/.project/project_am64x.js @@ -0,0 +1,99 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "main.asm", + "datalink.asm", + "datalink_init.asm", + "transport.asm", + "utils.asm", + "hdsl_master_icssg_hexpru.cmd", + "hdsl_master_icssg.cmd", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_0", + "ICSS_G_V_1_0", + "FREERUN_300_MHZ", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_300_mhz_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_300_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_freerun_300_mhz"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..5ca1237 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,87 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..407456d --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..ea4aebc --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/freerun_300_mhz/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( PRUIMEM, PAGE 0 + .text:main > 0x0 +} diff --git a/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h new file mode 100644 index 0000000..4938d9b --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -0,0 +1,1707 @@ +/* + * hdsl_master_icssg_300_mhz_bin.h + * + * + * Copyright (c) 2015 - 2016, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int Hiperface_DSL2_0[]= { +0x21066e00, +0x24000125, +0x2eff818f, +0x24001d8d, +0x23016a9d, +0xd105ff00, +0x91143a8e, +0x1d007e7e, +0x510c4608, +0x240943e1, +0x91143a80, +0x04eee0e0, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x230216d1, +0x2301f7d1, +0x05012525, +0x6f0025f0, +0x2eff8f8e, +0x24000725, +0x2eff8f8e, +0x24000725, +0x24041e8d, +0x23016a9d, +0x2300ef9d, +0x05012525, +0x5100254c, +0x2301f7d1, +0xd70170f8, +0xcf0723f7, +0x1f02c4c4, +0x913d1880, +0x1f000000, +0x813d1800, +0xc9002002, +0x2400269f, +0x91531800, +0x1f000000, +0x81531800, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x240008c5, +0x24001031, +0x240000f8, +0x2400042d, +0xc902c402, +0x1f012d2d, +0x69014503, +0x240004e0, +0x14e0c4c4, +0x11807070, +0x1031310d, +0x51015904, +0x23016a9d, +0x24000159, +0x79000003, +0x2301709d, +0x10e0e0e0, +0x2300ef9d, +0xd101700f, +0xc9072306, +0x5101450a, +0x2400040d, +0x040d6666, +0x230253d1, +0x79000009, +0x69014508, +0x2400060d, +0x040d6666, +0x230253d1, +0x79000004, +0x2400010d, +0x000d6666, +0x230253d1, +0x1d03c4c4, +0x2301f7d1, +0x51000c09, +0xd104ff00, +0xd703ffff, +0x24002f1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x810c3c80, +0x79000004, +0xd104ff00, +0xd703ffff, +0x24002f1e, +0x23046a9d, +0x05014545, +0x4f0045d2, +0x24000070, +0x01016565, +0x24000845, +0x1f01c4c4, +0x7f0000cd, +0x21023200, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230277d1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230277d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230277d1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230277d1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230277d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230277d1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x24000605, +0x2eff8283, +0x230262d1, +0x240000c0, +0x2400002d, +0x230069d1, +0x100d0d03, +0x0908f3f3, +0x0b18f2e0, +0x12e0f3f3, +0x0908f2f2, +0x1203f2f2, +0x14033838, +0x69014502, +0x15ff3838, +0x240278e0, +0x09013881, +0xf0810080, +0x14182020, +0x10808098, +0x2400012d, +0x24000605, +0x230069d1, +0x100d0d23, +0x0905f7f7, +0x0b1bf6e0, +0x12e0f7f7, +0x0905f6f6, +0x111f23e0, +0x12e0f6f6, +0x2400022d, +0x24000605, +0x230069d1, +0x100d0d43, +0x2400032d, +0x24000605, +0x230069d1, +0x100d0d84, +0x2400042d, +0x24000605, +0x230069d1, +0x09088484, +0x120d8484, +0x240000c0, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00c0c0, +0xc9007009, +0xd1077008, +0x1f077070, +0xd104c406, +0x1f04c4c4, +0x2400060d, +0x040d6666, +0x230253d1, +0x79000006, +0xc9005005, +0x51fd0304, +0x2400020d, +0x040d6666, +0x230253d1, +0xc9017005, +0x2400010d, +0x040d6666, +0x230253d1, +0x79000005, +0xc9015004, +0x2400020d, +0x040d6666, +0x230253d1, +0xc9027004, +0x2400010d, +0x040d6666, +0x230253d1, +0x111870e0, +0x5100e006, +0x1f03c4c4, +0x2400020d, +0x040d6666, +0x230253d1, +0x79000008, +0xc9035002, +0x69fd2403, +0xc9045005, +0x51fd0404, +0x2400020d, +0x040d6666, +0x230253d1, +0x2400052d, +0x24000605, +0x2300acd1, +0x1d007e7e, +0x240949e1, +0x910c3c80, +0x58e1e005, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x230216d1, +0x100d0d63, +0x0908f5f5, +0x0b18f4e0, +0x12e0f5f5, +0x0908f4f4, +0x1263f4f4, +0xc905700e, +0xd105c40d, +0x1f05c4c4, +0x2400080d, +0x040d6666, +0x230253d1, +0x14637878, +0x69014502, +0x15ff7878, +0x240278e0, +0x09017881, +0xf0810080, +0x14582020, +0x108080d8, +0x209d0000, +0xd104ff00, +0xd703ffff, +0x24002f1e, +0x51000c03, +0x2400ff1e, +0x810c3c80, +0x000c1111, +0xd107110b, +0x49011103, +0x2400600b, +0x79000013, +0x49031104, +0x2400620b, +0x05021111, +0x7900000f, +0x2400600b, +0x05041111, +0x7900000c, +0x1600110b, +0x01010b0b, +0x49010b03, +0x2400600b, +0x79000007, +0x49030b04, +0x24006d0b, +0x01021111, +0x79000003, +0x24006f0b, +0x01041111, +0x24013081, +0x24ffffc1, +0x808113c1, +0xc901c405, +0x69084502, +0x21028400, +0x69074502, +0x2102df00, +0x51000c2b, +0x51015b04, +0x100c0c02, +0x24000022, +0x79000003, +0x102a2a02, +0x100a0a22, +0x91e01800, +0x605b0002, +0x01010202, +0x69002203, +0x05010202, +0x2400ff22, +0x79000001, +0x711a2c02, +0x24001a2c, +0x910c3c81, +0x24010fe0, +0x04e1e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240003c0, +0x810605c0, +0x05010201, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x05010101, +0x6f0001fc, +0x24002ce0, +0xd104ff00, +0xd703ffff, +0x1022221e, +0xd104ff00, +0xd703ffff, +0x100b0b1e, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x24001fc0, +0x810605c0, +0x79000002, +0x100b0b1e, +0x240100eb, +0xf00d0b6d, +0x240178e0, +0xf06d0000, +0x240160eb, +0xf02d0b4d, +0x240178e1, +0xf04d0101, +0x51030008, +0x09010000, +0x0d060000, +0xc9071104, +0x153f6d6d, +0x00001111, +0x79000002, +0x04001111, +0xc9071104, +0x51020103, +0x150f4d4d, +0x79000001, +0x09026d6d, +0x0b024d00, +0x12006d6d, +0x09064d4d, +0xc901c402, +0x2103db00, +0xd104ff00, +0xd703ffff, +0x106d6d1e, +0x511f0d03, +0x51190d02, +0x79000003, +0x230635d1, +0x7900001a, +0xd104ff00, +0xd703ffff, +0xd1074d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x810c3c80, +0x511f0d12, +0x51190d11, +0xc901c402, +0x21032000, +0x910c3c81, +0x240117e0, +0x04e1e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240003c0, +0x810605c0, +0xd1064d04, +0x2400001e, +0x24000026, +0x79000003, +0x2400ff1e, +0x24000126, +0x209d0000, +0x10d1d1eb, +0x51002c1c, +0x910c3c80, +0x0da4e0e2, +0x102c2c6d, +0x24000b1e, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x91042581, +0xcf08e1ff, +0x24000fc1, +0x810605c1, +0x24001f8d, +0x2400044d, +0x230247d1, +0x05016d6d, +0x51006d0c, +0xd104ff00, +0xd703ffff, +0x24000b1e, +0x24000f8d, +0x2400044d, +0x230247d1, +0x24001f8d, +0x2400034d, +0x230247d1, +0x05016d6d, +0x6f006df6, +0x10ebebd1, +0x20d10000, +0x2400031e, +0x1f12ffff, +0x09041001, +0x12460101, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x24003fc0, +0x810605c0, +0x24000011, +0x810a1801, +0x59021006, +0x10d1d18b, +0x2400040d, +0x040d6666, +0x230253d1, +0x108b8bd1, +0x24001fc0, +0x810605c0, +0x91042580, +0xd708e0ff, +0x810c3c80, +0x20d10000, +0xd118fe02, +0xd105ff00, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x91505880, +0x1f008080, +0x1f00c0c0, +0x1f008181, +0x81505880, +0x2104eb00, +0x91042580, +0xd708e0ff, +0x91042580, +0xcf08e0ff, +0x05014d4d, +0x6f014dfb, +0x91042580, +0xd708e0ff, +0x8106058d, +0x91042580, +0xcf08e0ff, +0x20d10000, +0x117f6666, +0xc9066605, +0x2a000000, +0x24000066, +0x81031866, +0x7f0000da, +0x710f6602, +0x24000f66, +0x590e6604, +0x91aa1800, +0x1f008000, +0x81aa1800, +0x13806666, +0x81031866, +0x20d10000, +0xd105ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x1f007e7e, +0x810c3c80, +0x24000c10, +0x51004607, +0x10464601, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010101, +0x6f0001fc, +0x20d10000, +0x2405e4e0, +0xf0300000, +0x48100002, +0x10000010, +0x20d10000, +0x2eff838e, +0x24003f00, +0x81401800, +0x8138180e, +0x8110788e, +0x8198388e, +0x2eff8587, +0x209d0000, +0x108d8dab, +0x2eff8000, +0x815a1800, +0x10323201, +0x10121221, +0x81601881, +0xd104c40e, +0x91521801, +0x110b0101, +0x5100980c, +0x913d1880, +0x1f050000, +0x813d1800, +0xc9052002, +0x2400269f, +0x1f050101, +0x81521801, +0x2400060d, +0x040d6666, +0x230253d1, +0x7900003f, +0x2400010d, +0x000d6666, +0x230253d1, +0x69fd7309, +0x913d1880, +0x1f040000, +0x813d1800, +0xc9042002, +0x2400269f, +0x1f020101, +0x81521801, +0x79000033, +0x81521801, +0x0908f3e2, +0x10727202, +0x91a45800, +0x0480d281, +0x06c093c1, +0x10e1e1e2, +0xc91fe203, +0x1600e2e2, +0x0101e2e2, +0x913a18c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e204, +0x10222200, +0x10020220, +0x813a1880, +0x914218c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e207, +0x1f010101, +0x91043880, +0x1f018080, +0x81041880, +0xc901c002, +0x2400229f, +0x1d010101, +0x81501801, +0x6900e105, +0x686e5304, +0x813a188d, +0x24000019, +0x79000002, +0x2304d1d1, +0x10535300, +0x10333320, +0x10131340, +0x10727260, +0x10525201, +0x815b5800, +0x24000100, +0x815a1800, +0x815618c4, +0x815818d8, +0x81637894, +0x240000e0, +0x81983880, +0x81a4586e, +0x81701873, +0x10abab8d, +0x240000f8, +0x11cf4444, +0x21018d00, +0x108d8dab, +0x91637881, +0x91541800, +0x915618c0, +0xd105c008, +0x915818c0, +0x5100c007, +0x1f058000, +0x81541800, +0x2400060d, +0x040d6666, +0x230253d1, +0x79000017, +0x1d058000, +0x81541800, +0x2400010d, +0x000d6666, +0x230253d1, +0x91541800, +0x69fd6204, +0x1f028000, +0x81541800, +0x79000002, +0x1d028000, +0x15e06262, +0x2ed00381, +0xd1060204, +0xd1050203, +0x1d060000, +0x79000002, +0x1f060000, +0x81541800, +0x81463882, +0x814a3881, +0x2400249f, +0x915a1800, +0x69010004, +0x915b7800, +0x81197800, +0x2400239f, +0x24000300, +0x814e1800, +0x91701800, +0x81361800, +0x91081821, +0x10210001, +0x91503802, +0x1d060202, +0x1d060242, +0x5100010d, +0x91043880, +0x1f068080, +0x81041880, +0xc8c0c002, +0x2400229f, +0x913d1880, +0x1f060000, +0x813d1880, +0xc9062002, +0x2400269f, +0x1f060202, +0x1f060242, +0x81503802, +0x10abab8d, +0x21018f00, +0x91001800, +0xc9070002, +0x21023200, +0x91351800, +0xc9070002, +0x21023200, +0x51005c2c, +0x110ff602, +0x49085c02, +0x150f0202, +0x240278e0, +0x0b043c01, +0x14020101, +0x09010181, +0xf0810081, +0x09049c9c, +0x14819c9c, +0x71105c0a, +0xd1025c04, +0x09040200, +0x807c1800, +0x79000005, +0x907c1800, +0x12020000, +0x807c1800, +0x01017c7c, +0x79000013, +0x69045c12, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x51009c09, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x91511800, +0x1d050000, +0x81511800, +0x05045c5c, +0x79000089, +0x0b03f700, +0x111f0000, +0x5110005d, +0xd10ac485, +0xd104005c, +0x1f0ac4c4, +0x111f006b, +0x09046b6b, +0x0902f700, +0x0b1ef620, +0x12200000, +0x110f0000, +0x12006b6b, +0x10f6f6e2, +0x24002c01, +0x31020007, +0x110f0220, +0x0b01e240, +0x11f04040, +0x12402000, +0x2d000001, +0x0b0ae2e2, +0xd1076b1e, +0x24003001, +0xd1066b0e, +0x2400010d, +0x230660d1, +0x68ab8d45, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900003b, +0x2400020d, +0x230660d1, +0x688b8d38, +0x8137184b, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900002d, +0x0b026b00, +0x11030000, +0x2400005c, +0x51000003, +0x2400085c, +0x08005c5c, +0x10ebebe0, +0x2ed00180, +0xc9056b05, +0x81281880, +0x8120188b, +0x2400207c, +0x79000010, +0x81281880, +0x51005c04, +0x2400227c, +0x812018c0, +0x7900000b, +0x15ff0b0b, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x1d09c4c4, +0x2400040d, +0x24003001, +0x230660d1, +0x15ff8d9c, +0x69005c34, +0x51009c33, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x7900002a, +0x1d0ac4c4, +0x111f2300, +0x51150023, +0x691a000a, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x79000011, +0x691f0010, +0x91043880, +0x1f0d8080, +0x81041880, +0xc90dc002, +0x2400229f, +0x913d1880, +0x1f010000, +0x813d1800, +0xc9012002, +0x2400269f, +0x91513800, +0x1f050000, +0x1f054040, +0x81513800, +0x79000005, +0x91513800, +0x1d050000, +0x1d054040, +0x81513800, +0x69001b08, +0xd1073b07, +0x05013b3b, +0x69003b05, +0x2400403b, +0x2400181b, +0xc9027a02, +0x01081b1b, +0x2101e800, +0x24001031, +0x91001800, +0xc9060007, +0x1d060000, +0x81001800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x7900005d, +0x91351800, +0xc9060007, +0x1d060000, +0x81351800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x79000055, +0xc909c41c, +0x05041b1b, +0x490c1b06, +0x0a1b9a31, +0x110f3131, +0x69001b02, +0x1d09c4c4, +0x7900004d, +0xc9077a08, +0x905a1831, +0xc9021b03, +0x0b043131, +0x79000003, +0x110f3131, +0x01015a5a, +0x79000003, +0x0a1bfa31, +0x110f3131, +0x240278e2, +0x0b043a00, +0x14310000, +0x09010080, +0xf0800280, +0x09049a9a, +0x14809a9a, +0x69101b02, +0x15ff1a1a, +0x79000039, +0x91401800, +0x513f0016, +0x913d1840, +0x1d004040, +0x813d1840, +0x91531840, +0x1d004040, +0x81531840, +0x24003f20, +0x81401820, +0x113f007a, +0x2400009a, +0xc9070005, +0x13407a7a, +0x107a7a5a, +0x2400181b, +0x79000004, +0x91371820, +0x1020205a, +0x2400201b, +0x2400403b, +0x1f09c4c4, +0x79000022, +0x912c1800, +0xc9000020, +0x1d000000, +0x812c1800, +0x1f09c4c4, +0x91041880, +0x1d098080, +0x81041880, +0x91511800, +0x1d010000, +0x81511800, +0x91283881, +0x1001017a, +0x2400101b, +0xc9050102, +0x01101b1b, +0x0b031b00, +0x8fc4d801, +0xd1067a0c, +0x0b020101, +0x11030101, +0x51000109, +0x24000821, +0x08012101, +0x00011b1b, +0x10000040, +0x0b030100, +0x9f20d801, +0x01c44040, +0x8e40d801, +0x01101b1b, +0x2400c45a, +0x2400009a, +0x91aa1800, +0xc900000d, +0x91043880, +0x1f0a8080, +0x81041880, +0xc90ac002, +0x2400229f, +0x913d1880, +0x1f030000, +0x813d1800, +0xc9032002, +0x2400269f, +0x1d008080, +0x81aa1800, +0x91031800, +0x590e0007, +0x91505880, +0x1f0a8080, +0x1f0ac0c0, +0x1f0a8181, +0x81505880, +0x79000006, +0x91505880, +0x1d0a8080, +0x1d0ac0c0, +0x1d0a8181, +0x81505880, +0x91501801, +0x91aa1800, +0xc901000a, +0x1d018080, +0x81aa1800, +0x91043880, +0x1f038080, +0x81041880, +0xc903c002, +0x2400229f, +0x1f030101, +0x79000002, +0x1d030101, +0x81501801, +0x2101d500, +0x24000000, +0x814e1800, +0xd103c40a, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x69000d03, +0x24fdfd80, +0x68808427, +0x91381800, +0x01010000, +0x81381800, +0x91411820, +0x60200002, +0x21023200, +0x109d9d8b, +0x0901c880, +0x090288c0, +0x0903c781, +0x090487c1, +0x00c08080, +0x0081c181, +0x00818080, +0x00898080, +0x0b058080, +0xc90a8002, +0x13f82020, +0x0080c98d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x2304b8d1, +0x209d0000, +0x108b8b9d, +0x91aa1800, +0x1f018000, +0x81aa1800, +0x79000010, +0x8138180d, +0x0b05848d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x2304b8d1, +0x91983880, +0x008e8080, +0x024ec0c0, +0x81983880, +0x10efefe0, +0x10eeeee1, +0x2ed00380, +0x81107880, +0x24000200, +0x814e1800, +0x2400209f, +0x2400259f, +0x209d0000, +0x24000001, +0xc917ee02, +0x2400ff01, +0x10eeeee0, +0x10010160, +0x00006e6e, +0x0b08e0e0, +0x10010160, +0x02e0efef, +0x91e43881, +0x10e1efef, +0x20d10000, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x20d10000, +0x01011919, +0x91983880, +0x0000526e, +0x0220720f, +0x02c093af, +0x0300536f, +0x6902190b, +0xc90fc907, +0x1600c980, +0x01018080, +0x0b038080, +0x16008080, +0x01018080, +0x79000002, +0x0b038080, +0x00808e8e, +0x03006e6e, +0x20d10000, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x20d10000, +0x2effbd80, +0x24000011, +0x1d007e7e, +0x11fc5e5e, +0x1f13ffff, +0x1d007e7e, +0x1f13ffff, +0x31310002, +0x0100e0e0, +0x1d035e5e, +0x240000e0, +0x81080580, +0x24001fc0, +0x810605c0, +0x2eff8383, +0x23027c9d, +0x24000866, +0x2400000c, +0x2400002c, +0x91001800, +0x1d070000, +0x81001800, +0x2eff8000, +0x81351800, +0x91501880, +0x11da8080, +0x13108080, +0x81501880, +0x91521880, +0x11f48080, +0x13108080, +0x81521880, +0x91541880, +0x11748080, +0x13108080, +0x81541880, +0x240128e1, +0x90e13382, +0x1d00e2e2, +0xc901e002, +0x1f01e2e2, +0x80e13382, +0x9101185b, +0x51005b0e, +0x7900000d, +0x23061dd1, +0x91dc388c, +0x240000e2, +0x91e21882, +0x104c4c0a, +0x100c0c2a, +0x106c6c4a, +0x102c2c6a, +0x23061dd1, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x2400001e, +0x2400001e, +0x1f12ffff, +0x240000ca, +0x24001f8d, +0x23016a9d, +0x2301f7d1, +0x0101caca, +0x6f02cafc, +0x240000ca, +0x2400198d, +0x23016a9d, +0x2301f7d1, +0x0101caca, +0x6f10cafc, +0x2400017b, +0x24000925, +0x24001a8d, +0x23016a9d, +0xd105ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31000002, +0x0100e0e0, +0x1f007e7e, +0x810c3c80, +0x24004805, +0x2eff8592, +0x24005401, +0x2400000b, +0x24000021, +0x24000845, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x69000b0e, +0x51ff000d, +0x240178e2, +0xf0000202, +0x0104e206, +0x61080602, +0x05080606, +0x0d070606, +0x69400504, +0x69064503, +0x71030602, +0x24000006, +0x1e06f6f6, +0x2400010b, +0x05014545, +0xc8068002, +0x1e452121, +0x10000020, +0x69080503, +0x6f0145ea, +0x79000005, +0x6f0045e8, +0x2d802101, +0x05080505, +0x6f0005e3, +0x240947e3, +0xc918ff00, +0x101f1f00, +0x05014545, +0xc8060002, +0x1e452121, +0x10000020, +0x2d802101, +0x910c3c99, +0x58e3f933, +0x04f9e3eb, +0x100b0b19, +0x0b01ebeb, +0x0501ebeb, +0x4f00ebff, +0x1d007e7e, +0x2400031e, +0x1f12ffff, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x24003fc2, +0x810605c2, +0x24000011, +0x31010001, +0x24001fc2, +0x810605c2, +0x91042582, +0xd708e2ff, +0x810c3c80, +0xd104ff00, +0xd703ffff, +0x24002c1e, +0xd104ff00, +0xd703ffff, +0x2400b21e, +0x2400cb1e, +0x24000065, +0x69012501, +0x01016565, +0x0901f4f4, +0x0b077300, +0x1200f4f4, +0x0901f3f3, +0x0b077200, +0x12001313, +0x0901f2f2, +0x230629d1, +0x510e6506, +0x6f010df6, +0x10656546, +0x05012525, +0x4f002595, +0x7900001c, +0x2a000000, +0xd118fe0c, +0xd105ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2a000000, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x7f000030, +0x24000925, +0xd104ff00, +0xd703ffff, +0x24001b8d, +0x23016a9d, +0x2305ef9d, +0x230629d1, +0x6f010dea, +0x05012525, +0x4f0025f8, +0x24001025, +0x24001c8d, +0x23016a9d, +0x2305ef9d, +0x230629d1, +0x6f010dd6, +0x05012525, +0x4f0025fa, +0x810a1846, +0x24001d8d, +0x23016a9d, +0x2300ef9d, +0x6e0403cf, +0x6e2423ce, +0x110f4300, +0x0b044320, +0x6e2000cb, +0x10848480, +0x10434340, +0x10404001, +0x10202021, +0x10000041, +0x810d3801, +0x2400000d, +0x000d6666, +0x230253d1, +0x1f08c4c4, +0x110fe05d, +0x01085d5d, +0x0b04e07d, +0x113f7d7d, +0x005d7d7d, +0x050c7d7d, +0x010c7d00, +0x0d280000, +0x24ffffc1, +0x24ffff81, +0x0a00e1e1, +0x81e43881, +0x2301f7d1, +0x21001600, +0x24002005, +0x230262d1, +0x24000080, +0x2405a4eb, +0x2eff8992, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f4f4, +0x10000020, +0x0b018001, +0x14000130, +0x230277d1, +0x6f0005f6, +0x24001d05, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f3f3, +0x10000020, +0x0b018001, +0x14000130, +0x230277d1, +0x6f0105f6, +0xc918ff00, +0x101f1f00, +0xc8068002, +0x1f00f3f3, +0x0903f3f3, +0x1f18ffff, +0x240947e1, +0x910c3c80, +0x58e1e006, +0x04e0e1e0, +0x0101e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x1d007e7e, +0x230216d1, +0x2301f7d1, +0x209d0000, +0x91502181, +0x91502194, +0x56e1f4ff, +0x04e1f4f4, +0x20d10000, +0x240000e0, +0x60cd8d04, +0x04cd8d8d, +0x0101e0e0, +0x7f0000fd, +0x10e0e0cd, +0x20d10000, +0x91acb880, +0x10e2f3eb, +0x240ff8e2, +0x10e2f3e2, +0x0901e2e2, +0x12ebe2eb, +0x68e0f404, +0x68e1eb03, +0x2400010d, +0x20d10000, +0x2400000d, +0x20d10000, +0x13154d4d, +0x104d4d1e, +0x24000800, +0xd104ff00, +0xd703ffff, +0x2400551e, +0x05010000, +0x6f0000fc, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x240117e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240003c0, +0x810605c0, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400031e, +0x240012e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x24001fc0, +0x810605c0, +0x24001ee0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x810c3c80, +0x20d10000, +0x91043880, +0x1e0d8080, +0x81041880, +0xc80dc002, +0x2400229f, +0x20d10000, +0x240278e2, +0x100d0d40, +0x2400008d, +0x24000080, +0x2c600100, +0x14002d00, +0x09018080, +0xf0800280, +0x09088d8d, +0x148d808d, +0x05014040, +0x4f0040f8, +0x15ff0d0d, +0x20d10000, +0x91003c82, +0x1308e2e2, +0x81003c82, +0x2104ea00 }; diff --git a/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_ch0_bin.h b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_ch0_bin.h new file mode 100644 index 0000000..53c1e44 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_ch0_bin.h @@ -0,0 +1,2035 @@ +/* + * hdsl_master_icssg_300_mhz_ch0_bin.h + * + * + * Copyright (c) 2021 - 2023, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int Hiperface_DSL2_0_RTU[]= { +0x2107ac00, +0x24000125, +0x2eff818f, +0x24001d8d, +0x23019c9d, +0xd105ff00, +0x91143a8e, +0x1d007e7e, +0x510c4608, +0x240943e1, +0x91143a80, +0x04eee0e0, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x2302ced1, +0x2302aed1, +0x05012525, +0x6f0025f0, +0x2eff8f8e, +0x24000725, +0x2eff8f8e, +0x24000725, +0x24041e8d, +0x23019c9d, +0x2301219d, +0x05012525, +0x5100257e, +0x2302aed1, +0xd70170f8, +0xcf0723f7, +0x1f02c4c4, +0x913d1880, +0x1f000000, +0xc9002002, +0x2400269f, +0x813d1800, +0x91531800, +0x1f000000, +0x81531800, +0x91043880, +0x1f098080, +0xc909c002, +0x2400229f, +0x81041880, +0x91511800, +0x1f010000, +0x81511800, +0x240008c5, +0x24001031, +0x240000f8, +0x2400042d, +0xc902c402, +0x1f012d2d, +0x69014503, +0x240004e0, +0x14e0c4c4, +0x11807070, +0x1031310d, +0x51015904, +0x23019c9d, +0x24000159, +0x79000003, +0x2301c49d, +0x10e0e0e0, +0x2301219d, +0xd101700f, +0xc9072306, +0x5101450a, +0x2400040d, +0x040d6666, +0x230313d1, +0x79000009, +0x69014508, +0x2400060d, +0x040d6666, +0x230313d1, +0x79000004, +0x2400010d, +0x000d6666, +0x230313d1, +0x1d03c4c4, +0x2302aed1, +0x51000c23, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x810c3c80, +0x79000005, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0x2305329d, +0x05014545, +0x51074517, +0x49004502, +0x21008f00, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x7f0000a6, +0x24000070, +0x24000845, +0x1f01c4c4, +0x2400ff1e, +0x7f0000a1, +0xcf01c4ec, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0x7f00009b, +0x2102f200, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x23033bd1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x23033bd1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x24000605, +0x2eff8283, +0x230322d1, +0x240000c0, +0x2400002d, +0x23009bd1, +0x100d0d03, +0x0908f3f3, +0x0b18f2e0, +0x12e0f3f3, +0x0908f2f2, +0x1203f2f2, +0x14033838, +0x69014502, +0x15ff3838, +0x240278e0, +0x09013881, +0xf0810080, +0x14182020, +0x10808098, +0x2400012d, +0x24000605, +0x23009bd1, +0x100d0d23, +0x0905f7f7, +0x0b1bf6e0, +0x12e0f7f7, +0x0905f6f6, +0x111f23e0, +0x12e0f6f6, +0x2400022d, +0x24000605, +0x23009bd1, +0x100d0d43, +0x2400032d, +0x24000605, +0x23009bd1, +0x100d0d84, +0x2400042d, +0x24000605, +0x23009bd1, +0x09088484, +0x120d8484, +0x240000c0, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00c0c0, +0xc9007009, +0xd1077008, +0x1f077070, +0xd104c406, +0x1f04c4c4, +0x2400060d, +0x040d6666, +0x230313d1, +0x79000006, +0xc9005005, +0x51fd0304, +0x2400020d, +0x040d6666, +0x230313d1, +0xc9017005, +0x2400010d, +0x040d6666, +0x230313d1, +0x79000005, +0xc9015004, +0x2400020d, +0x040d6666, +0x230313d1, +0xc9027004, +0x2400010d, +0x040d6666, +0x230313d1, +0x111870e0, +0x5100e006, +0x1f03c4c4, +0x2400020d, +0x040d6666, +0x230313d1, +0x79000008, +0xc9035002, +0x69fd2403, +0xc9045005, +0x51fd0404, +0x2400020d, +0x040d6666, +0x230313d1, +0x2400052d, +0x24000605, +0x2300ded1, +0x1d007e7e, +0x240949e1, +0x910c3c80, +0x58e1e005, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x2302ced1, +0x100d0d63, +0x0908f5f5, +0x0b18f4e0, +0x12e0f5f5, +0x0908f4f4, +0x1263f4f4, +0xc905700e, +0xd105c40d, +0x1f05c4c4, +0x2400080d, +0x040d6666, +0x230313d1, +0x14637878, +0x69014502, +0x15ff7878, +0x240278e0, +0x09017881, +0xf0810080, +0x14582020, +0x108080d8, +0x209d0000, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x51000c12, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x810c3c80, +0x69074502, +0x2400ff1e, +0x000c1111, +0xd107110b, +0x49011103, +0x2400600b, +0x79000013, +0x49031104, +0x2400620b, +0x05021111, +0x7900000f, +0x2400600b, +0x05041111, +0x7900000c, +0x1600110b, +0x01010b0b, +0x49010b03, +0x2400600b, +0x79000007, +0x49030b04, +0x24006d0b, +0x01021111, +0x79000003, +0x24006f0b, +0x01041111, +0x24013081, +0x24ffffc1, +0x808113c1, +0xc901c40c, +0x69084504, +0x2400001e, +0x2400ff1e, +0x21034800, +0x69074507, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x2103a700, +0x51000c27, +0x51015b04, +0x100c0c02, +0x24000022, +0x79000003, +0x102a2a02, +0x100a0a22, +0x91e01800, +0x605b0002, +0x01010202, +0x69002203, +0x05010202, +0x2400ff22, +0x79000001, +0x711a2c02, +0x24001a2c, +0x910c3c81, +0x05010201, +0x2400ff1e, +0x05010101, +0x6f0001fe, +0x1022221e, +0x100b0b79, +0x3103000f, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x7900001e, +0x100b0b79, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x240100eb, +0xf00d0b6d, +0x240178e0, +0xf06d0000, +0x240160eb, +0xf02d0b4d, +0x240178e1, +0xf04d0101, +0x51030008, +0x09010000, +0x0d060000, +0xc9071104, +0x153f6d6d, +0x00001111, +0x79000002, +0x04001111, +0xc9071104, +0x51020103, +0x150f4d4d, +0x79000001, +0x09026d6d, +0x0b024d00, +0x12006d6d, +0x09064d4d, +0xc901c41a, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x2104a300, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x106d6d79, +0x3103000f, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x511f0d03, +0x51190d02, +0x79000003, +0x230758d1, +0x7900001b, +0xd104ff00, +0xd703ffff, +0xd1074d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x810c3c80, +0x511f0d13, +0x51190d12, +0xd1064d04, +0x2400001e, +0x24000026, +0x79000003, +0x2400ff1e, +0x24000126, +0xc901c402, +0x2103e800, +0x910c3c81, +0x240117e0, +0x04e1e0e0, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x209d0000, +0x10d1d1eb, +0x51002c1d, +0x910c3c80, +0x0da4e0e2, +0x102c2c6d, +0x24000b1e, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x91042581, +0xcf08e1ff, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x24001f8d, +0x2400044d, +0x230307d1, +0x05016d6d, +0x51006d0c, +0xd104ff00, +0xd703ffff, +0x24000b1e, +0x24000f8d, +0x2400044d, +0x230307d1, +0x24001f8d, +0x2400034d, +0x230307d1, +0x05016d6d, +0x6f006df6, +0x10ebebd1, +0x20d10000, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x09041001, +0x12460101, +0x31010001, +0x31010001, +0x31010001, +0x24000011, +0x810a1801, +0x59021006, +0x10d1d18b, +0x2400040d, +0x040d6666, +0x230313d1, +0x108b8bd1, +0x810c3c80, +0x20d10000, +0xd118fe02, +0xd105ff00, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0xc900c002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f020000, +0xc9022002, +0x2400269f, +0x813d1800, +0x91505880, +0x1f008080, +0x1f00c0c0, +0x1f008181, +0x81505880, +0x2105b300, +0x91042580, +0xd708e0ff, +0x91042580, +0xcf08e0ff, +0x05014d4d, +0x6f014dfb, +0x91042580, +0xd708e0ff, +0x8106058d, +0x91042580, +0xcf08e0ff, +0x20d10000, +0x117f6666, +0xc9066605, +0x2a000000, +0x24000066, +0x81031866, +0x7f0000da, +0x710f6602, +0x24000f66, +0x590e6604, +0x91aa1800, +0x1f008000, +0x81aa1800, +0x13806666, +0x81031866, +0x20d10000, +0xd105ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x1f007e7e, +0x810c3c80, +0x24000c10, +0x51004607, +0x10464601, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010101, +0x6f0001fc, +0x20d10000, +0x2405e4e0, +0xf0300000, +0x48100002, +0x10000010, +0x20d10000, +0x2eff838e, +0x24003f00, +0x81401800, +0x8138180e, +0x8110788e, +0x8198388e, +0x2eff8587, +0x209d0000, +0x108d8dab, +0x2eff8000, +0x815a1800, +0x10323201, +0x10121221, +0x81601881, +0xd104c40f, +0x91521801, +0x1d050101, +0x1d020101, +0x5100980c, +0x913d1880, +0x1f050000, +0xc9052002, +0x2400269f, +0x813d1800, +0x1f050101, +0x81521801, +0x2400060d, +0x040d6666, +0x230313d1, +0x79000041, +0x2400010d, +0x000d6666, +0x230313d1, +0x69fd7309, +0x913d1880, +0x1f040000, +0xc9042002, +0x2400269f, +0x813d1800, +0x1f020101, +0x81521801, +0x79000035, +0x81521801, +0x0908f3e2, +0x10727202, +0x91a45800, +0x0480d281, +0x06c093c1, +0x10e1e1e2, +0xc91fe203, +0x1600e2e2, +0x0101e2e2, +0x913a18c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e204, +0x10222200, +0x10020220, +0x813a1880, +0x2400ff1e, +0x2400ff1e, +0x914218c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e207, +0x1f010101, +0x91043880, +0x1f018080, +0xc901c002, +0x2400229f, +0x81041880, +0x1d010101, +0x81501801, +0x6900e105, +0x686e5304, +0x813a188d, +0x24000019, +0x79000002, +0x230599d1, +0x10535300, +0x10333320, +0x10131340, +0x10727260, +0x10525201, +0x815b5800, +0x24000100, +0x815a1800, +0x815618c4, +0x815818d8, +0x81637894, +0x2400ff1e, +0x240000e0, +0x81983880, +0x81a4586e, +0x81701873, +0x10abab8d, +0x240000f8, +0x11cf4444, +0x2101e500, +0x108d8dab, +0x91637881, +0x91541800, +0x915618c0, +0xd105c008, +0x915818c0, +0x5100c007, +0x1f058000, +0x81541800, +0x2400060d, +0x040d6666, +0x230313d1, +0x79000017, +0x1d058000, +0x81541800, +0x2400010d, +0x000d6666, +0x230313d1, +0x91541800, +0x69fd6204, +0x1f028000, +0x81541800, +0x79000002, +0x1d028000, +0x15e06262, +0x2ed00381, +0xd1060204, +0xd1050203, +0x1d060000, +0x79000002, +0x1f060000, +0x81541800, +0x81463882, +0x814a3881, +0x2400249f, +0x915a1800, +0x69010004, +0x915b7800, +0x81197800, +0x2400239f, +0x24000300, +0x814e1800, +0x91701800, +0x81361800, +0x91081821, +0x10210001, +0x91503802, +0x1d060202, +0x1d060242, +0x5100010d, +0x91043880, +0x1f068080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f060000, +0xc9062002, +0x2400269f, +0x813d1880, +0x1f060202, +0x1f060242, +0x81503802, +0x10abab8d, +0x2101ec00, +0x91001800, +0xc9070002, +0x2102f200, +0x91351800, +0xc9070002, +0x2102f200, +0x51005c2c, +0x110ff602, +0x49085c02, +0x150f0202, +0x240278e0, +0x0b043c01, +0x14020101, +0x09010181, +0xf0810081, +0x09049c9c, +0x14819c9c, +0x71105c0a, +0xd1025c04, +0x09040200, +0x807c1800, +0x79000005, +0x907c1800, +0x12020000, +0x807c1800, +0x01017c7c, +0x79000013, +0x69045c12, +0x91043880, +0x1f098080, +0xc909c002, +0x2400229f, +0x81041880, +0x91511800, +0x1f010000, +0x81511800, +0x51009c09, +0x91043880, +0x1f0c8080, +0xc90cc002, +0x2400229f, +0x81041880, +0x91511800, +0x1f050000, +0x81511800, +0x91511800, +0x1d050000, +0x81511800, +0x05045c5c, +0x79000089, +0x0b03f700, +0x111f0000, +0x5110005d, +0xd10ac485, +0xd104005c, +0x1f0ac4c4, +0x111f006b, +0x09046b6b, +0x0902f700, +0x0b1ef620, +0x12200000, +0x110f0000, +0x12006b6b, +0x10f6f6e2, +0x24002c01, +0x31020007, +0x110f0220, +0x0b01e240, +0x11f04040, +0x12402000, +0x2d000001, +0x0b0ae2e2, +0xd1076b1e, +0x24003001, +0xd1066b0e, +0x2400010d, +0x23079ed1, +0x68ab8d45, +0x13803b3b, +0x913d1880, +0x1f008080, +0xc9002002, +0x2400229f, +0x813d1800, +0x91531800, +0x1f000000, +0x81531800, +0x7900003b, +0x2400020d, +0x23079ed1, +0x688b8d38, +0x8137184b, +0x13803b3b, +0x913d1880, +0x1f008080, +0xc9002002, +0x2400229f, +0x813d1800, +0x91531800, +0x1f000000, +0x81531800, +0x7900002d, +0x0b026b00, +0x11030000, +0x2400005c, +0x51000003, +0x2400085c, +0x08005c5c, +0x10ebebe0, +0x2ed00180, +0xc9056b05, +0x81281880, +0x8120188b, +0x2400207c, +0x79000010, +0x81281880, +0x51005c04, +0x2400227c, +0x812018c0, +0x7900000b, +0x15ff0b0b, +0x91043880, +0x1f098080, +0xc909c002, +0x2400229f, +0x81041880, +0x91511800, +0x1f010000, +0x81511800, +0x1d09c4c4, +0x2400040d, +0x24003001, +0x23079ed1, +0x15ff8d9c, +0x69005c34, +0x51009c33, +0x91043880, +0x1f0c8080, +0xc90cc002, +0x2400229f, +0x81041880, +0x91511800, +0x1f050000, +0x81511800, +0x7900002a, +0x1d0ac4c4, +0x111f2300, +0x51150023, +0x691a000a, +0x91043880, +0x1f0c8080, +0xc90cc002, +0x2400229f, +0x81041880, +0x91511800, +0x1f050000, +0x81511800, +0x79000011, +0x691f0010, +0x91043880, +0x1f0d8080, +0xc90dc002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f010000, +0xc9012002, +0x2400269f, +0x813d1800, +0x91513800, +0x1f050000, +0x1f054040, +0x81513800, +0x79000005, +0x91513800, +0x1d050000, +0x1d054040, +0x81513800, +0x69001b08, +0xd1073b07, +0x05013b3b, +0x69003b05, +0x2400403b, +0x2400181b, +0xc9027a02, +0x01081b1b, +0x2102a400, +0x24001031, +0x91001800, +0xc9060007, +0x1d060000, +0x81001800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x7900005d, +0x91351800, +0xc9060007, +0x1d060000, +0x81351800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x79000055, +0xc909c41c, +0x05041b1b, +0x490c1b06, +0x0a1b9a31, +0x110f3131, +0x69001b02, +0x1d09c4c4, +0x7900004d, +0xc9077a08, +0x905a1831, +0xc9021b03, +0x0b043131, +0x79000003, +0x110f3131, +0x01015a5a, +0x79000003, +0x0a1bfa31, +0x110f3131, +0x240278e2, +0x0b043a00, +0x14310000, +0x09010080, +0xf0800280, +0x09049a9a, +0x14809a9a, +0x69101b02, +0x15ff1a1a, +0x79000039, +0x91401800, +0x513f0016, +0x913d1840, +0x1d004040, +0x813d1840, +0x91531840, +0x1d004040, +0x81531840, +0x24003f20, +0x81401820, +0x113f007a, +0x2400009a, +0xc9070005, +0x13407a7a, +0x107a7a5a, +0x2400181b, +0x79000004, +0x91371820, +0x1020205a, +0x2400201b, +0x2400403b, +0x1f09c4c4, +0x79000022, +0x912c1800, +0xc9000020, +0x1d000000, +0x812c1800, +0x1f09c4c4, +0x91041880, +0x1d098080, +0x81041880, +0x91511800, +0x1d010000, +0x81511800, +0x91283881, +0x1001017a, +0x2400101b, +0xc9050102, +0x01101b1b, +0x0b031b00, +0x8fc4d801, +0xd1067a0c, +0x0b020101, +0x11030101, +0x51000109, +0x24000821, +0x08012101, +0x00011b1b, +0x10000040, +0x0b030100, +0x9f20d801, +0x01c44040, +0x8e40d801, +0x01101b1b, +0x2400c45a, +0x2400009a, +0x91aa1800, +0xc900000d, +0x91043880, +0x1f0a8080, +0xc90ac002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f030000, +0xc9032002, +0x2400269f, +0x813d1800, +0x1d008080, +0x81aa1800, +0x91031800, +0x590e0007, +0x91505880, +0x1f0a8080, +0x1f0ac0c0, +0x1f0a8181, +0x81505880, +0x79000006, +0x91505880, +0x1d0a8080, +0x1d0ac0c0, +0x1d0a8181, +0x81505880, +0x91501801, +0x91aa1800, +0xc901000a, +0x1d018080, +0x81aa1800, +0x91043880, +0x1f038080, +0xc903c002, +0x2400229f, +0x81041880, +0x1f030101, +0x79000002, +0x1d030101, +0x81501801, +0x21027e00, +0x24000000, +0x814e1800, +0xd103c40a, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x69000d03, +0x24fdfd80, +0x68808427, +0x91381800, +0x01010000, +0x81381800, +0x91411820, +0x60200002, +0x2102f200, +0x109d9d8b, +0x0901c880, +0x090288c0, +0x0903c781, +0x090487c1, +0x00c08080, +0x0081c181, +0x00818080, +0x00898080, +0x0b058080, +0xc90a8002, +0x13f82020, +0x0080c98d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x230580d1, +0x209d0000, +0x108b8b9d, +0x91aa1800, +0x1f018000, +0x81aa1800, +0x79000010, +0x8138180d, +0x0b05848d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x230580d1, +0x91983880, +0x008e8080, +0x024ec0c0, +0x81983880, +0x10efefe0, +0x10eeeee1, +0x2ed00380, +0x81107880, +0x24000200, +0x814e1800, +0x2400209f, +0x2400259f, +0x209d0000, +0x24000001, +0xc917ee02, +0x2400ff01, +0x10eeeee0, +0x10010160, +0x00006e6e, +0x0b08e0e0, +0x10010160, +0x02e0efef, +0x91e43881, +0x10e1efef, +0x20d10000, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x20d10000, +0x01011919, +0x91983880, +0x0000526e, +0x0220720f, +0x02c093af, +0x0300536f, +0x6902190b, +0xc90fc907, +0x1600c980, +0x01018080, +0x0b038080, +0x16008080, +0x01018080, +0x79000002, +0x0b038080, +0x00808e8e, +0x03006e6e, +0x20d10000, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x20d10000, +0x2effbd80, +0x2400ecc0, +0x81ea18c0, +0x240002d8, +0x24e31098, +0xf100180a, +0x15400a0a, +0x24000011, +0x1d007e7e, +0x11fc5e5e, +0x1f13ffff, +0x1d007e7e, +0x1f13ffff, +0x31310002, +0x0100e0e0, +0x1d035e5e, +0x240000e0, +0x81080580, +0x240003c0, +0x810605c0, +0x2eff8383, +0x2303409d, +0x24000866, +0x2400000c, +0x2400002c, +0x91001800, +0x1d070000, +0x81001800, +0x2eff8000, +0x81351800, +0x91501880, +0x11da8080, +0x13108080, +0x81501880, +0x91521880, +0x11f48080, +0x13108080, +0x81521880, +0x91541880, +0x11748080, +0x13108080, +0x81541880, +0x240128e1, +0x90e13382, +0x1d00e2e2, +0xc901e002, +0x1f01e2e2, +0x80e13382, +0x9101185b, +0x51005b0e, +0x7900000d, +0x230740d1, +0x91dc388c, +0x240000e2, +0x91e21882, +0x104c4c0a, +0x100c0c2a, +0x106c6c4a, +0x102c2c6a, +0x230740d1, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x2400001e, +0x2400001e, +0x2400001e, +0x2400001e, +0x1f12ffff, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0x240000ca, +0x24001f8d, +0x23019c9d, +0x2302aed1, +0x0101caca, +0x6f02cafc, +0x240000ca, +0x2400198d, +0x23019c9d, +0x2302aed1, +0x0101caca, +0x6f10cafc, +0x2400017b, +0x24000925, +0x24001a8d, +0x23019c9d, +0xd105ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31000002, +0x0100e0e0, +0x1f007e7e, +0x810c3c80, +0x24004805, +0x2eff8592, +0x24005401, +0x2400000b, +0x24000021, +0x24000845, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x69000b0e, +0x51ff000d, +0x240178e2, +0xf0000202, +0x0104e206, +0x61080602, +0x05080606, +0x0d070606, +0x69400504, +0x69064503, +0x71030602, +0x24000006, +0x1e06f6f6, +0x2400010b, +0x05014545, +0xc8068002, +0x1e452121, +0x10000020, +0x69080503, +0x6f0145ea, +0x79000005, +0x6f0045e8, +0x2d802101, +0x05080505, +0x6f0005e3, +0x240947e3, +0xc918ff00, +0x101f1f00, +0x05014545, +0xc8060002, +0x1e452121, +0x10000020, +0x2d802101, +0x910c3c99, +0x58e3f96e, +0x04f9e3eb, +0x100b0b19, +0x0b01ebeb, +0x0501ebeb, +0x4f00ebff, +0x1d007e7e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x24000011, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x91042582, +0xd708e2ff, +0x810c3c80, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0x2400ff1e, +0x24000065, +0x69012501, +0x01016565, +0x0901f4f4, +0x0b077300, +0x1200f4f4, +0x0901f3f3, +0x0b077200, +0x12001313, +0x0901f2f2, +0x23074cd1, +0x510e6506, +0x6f010df6, +0x10656546, +0x05012525, +0x4f002558, +0x7900001c, +0x2a000000, +0xd118fe0c, +0xd105ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2a000000, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0xc900c002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f020000, +0xc9022002, +0x2400269f, +0x813d1800, +0x7d0000d3, +0x24000925, +0x24001b8d, +0x23019c9d, +0x2307129d, +0x23074cd1, +0x6f010dec, +0x05012525, +0x4f0025fa, +0x24001025, +0x24001c8d, +0x23019c9d, +0x2307129d, +0x23074cd1, +0x6f010dd8, +0x05012525, +0x4f0025fa, +0x810a1846, +0x24001d8d, +0x23019c9d, +0x2301219d, +0x6e0403d1, +0x6e2423d0, +0x110f4300, +0x0b044320, +0x6e2000cd, +0x10848480, +0x10434340, +0x10404001, +0x10202021, +0x10000041, +0x810d3801, +0x2400000d, +0x000d6666, +0x230313d1, +0x1f08c4c4, +0x110fe05d, +0x01085d5d, +0x0b04e07d, +0x113f7d7d, +0x005d7d7d, +0x050c7d7d, +0x010c7d00, +0x0d280000, +0x24ffffc1, +0x24ffff81, +0x0a00e1e1, +0x81e43881, +0x2302aed1, +0x21001600, +0x24002005, +0x230322d1, +0x24000080, +0x2405a4eb, +0x2eff8992, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f4f4, +0x10000020, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f6, +0x24001d05, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f3f3, +0x10000020, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0105f6, +0xc918ff00, +0x101f1f00, +0xc8068002, +0x1f00f3f3, +0x0903f3f3, +0x1f18ffff, +0x240947e1, +0x910c3c80, +0x58e1e006, +0x04e0e1e0, +0x0101e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x1d007e7e, +0x2302ced1, +0x2302aed1, +0x209d0000, +0x91502181, +0x91502194, +0x56e1f4ff, +0x04e1f4f4, +0x20d10000, +0x240000e0, +0x60cd8d04, +0x04cd8d8d, +0x0101e0e0, +0x7f0000fd, +0x10e0e0cd, +0x20d10000, +0x91acb880, +0x10e2f3eb, +0x240ff8e2, +0x10e2f3e2, +0x0901e2e2, +0x12ebe2eb, +0x68e0f404, +0x68e1eb03, +0x2400010d, +0x20d10000, +0x2400000d, +0x20d10000, +0x13154d4d, +0x104d4d79, +0x3103000f, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x24000800, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0x05010000, +0x6f0000ef, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x240117e0, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x240012e0, +0x810c3c80, +0x20d10000, +0x91043880, +0x1e0d8080, +0xc80dc002, +0x2400229f, +0x81041880, +0x20d10000, +0x240278e2, +0x100d0d40, +0x2400008d, +0x24000080, +0x2c600100, +0x14002d00, +0x09018080, +0xf0800280, +0x09088d8d, +0x148d808d, +0x05014040, +0x4f0040f8, +0x15ff0d0d, +0x20d10000, +0x91003c82, +0x1308e2e2, +0x81003c82, +0x2105b200, +0x244030c2, +0x24000082, +0x240000c1, +0x24210081, +0x240c00eb, +0x0504ebeb, +0xf0eb2180, +0xe0eb2280, +0x6f00ebfd, +0x21000000 }; diff --git a/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_ch1_bin.h b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_ch1_bin.h new file mode 100644 index 0000000..9804db4 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_ch1_bin.h @@ -0,0 +1,2034 @@ +/* + * hdsl_master_icssg_300_mhz_ch1_bin.h + * + * + * Copyright (c) 2021 - 2023, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int Hiperface_DSL2_0_PRU[]= { +0x2107ab00, +0x24000125, +0x2eff818f, +0x24001d8d, +0x23019c9d, +0xd10dff00, +0x91143a8e, +0x1d017e7e, +0x510c4608, +0x240943e1, +0x91143a80, +0x04eee0e0, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x2302ced1, +0x2302aed1, +0x05012525, +0x6f0025f0, +0x2eff8f8e, +0x24000725, +0x2eff8f8e, +0x24000725, +0x24041e8d, +0x23019c9d, +0x2301219d, +0x05012525, +0x5100257e, +0x2302aed1, +0xd70170f8, +0xcf0723f7, +0x1f02c4c4, +0x913d1880, +0x1f000000, +0xc9002002, +0x2400269f, +0x813d1800, +0x91531800, +0x1f000000, +0x81531800, +0x91043880, +0x1f098080, +0xc909c002, +0x2400229f, +0x81041880, +0x91511800, +0x1f010000, +0x81511800, +0x240008c5, +0x24001031, +0x240000f8, +0x2400042d, +0xc902c402, +0x1f012d2d, +0x69014503, +0x240004e0, +0x14e0c4c4, +0x11807070, +0x1031310d, +0x51015904, +0x23019c9d, +0x24000159, +0x79000003, +0x2301c49d, +0x10e0e0e0, +0x2301219d, +0xd101700f, +0xc9072306, +0x5101450a, +0x2400040d, +0x040d6666, +0x230313d1, +0x79000009, +0x69014508, +0x2400060d, +0x040d6666, +0x230313d1, +0x79000004, +0x2400010d, +0x000d6666, +0x230313d1, +0x1d03c4c4, +0x2302aed1, +0x51000c23, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x810c3c80, +0x79000005, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0x2305329d, +0x05014545, +0x51074517, +0x49004502, +0x21008f00, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x7f0000a6, +0x24000070, +0x24000845, +0x1f01c4c4, +0x2400ff1e, +0x7f0000a1, +0xcf01c4ec, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0x7f00009b, +0x2102f200, +0x10d1d182, +0x240000cd, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f7, +0x240820eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x23033bd1, +0x110fcdc0, +0x240868eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x10d1d182, +0x240000cd, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f7, +0x240820eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x23033bd1, +0x110fcdc0, +0x240868eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x24000605, +0x2eff8283, +0x230322d1, +0x240000c0, +0x2400002d, +0x23009bd1, +0x100d0d03, +0x0908f3f3, +0x0b18f2e0, +0x12e0f3f3, +0x0908f2f2, +0x1203f2f2, +0x14033838, +0x69014502, +0x15ff3838, +0x240978e0, +0x09013881, +0xf0810080, +0x14182020, +0x10808098, +0x2400012d, +0x24000605, +0x23009bd1, +0x100d0d23, +0x0905f7f7, +0x0b1bf6e0, +0x12e0f7f7, +0x0905f6f6, +0x111f23e0, +0x12e0f6f6, +0x2400022d, +0x24000605, +0x23009bd1, +0x100d0d43, +0x2400032d, +0x24000605, +0x23009bd1, +0x100d0d84, +0x2400042d, +0x24000605, +0x23009bd1, +0x09088484, +0x120d8484, +0x240000c0, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0xc8068002, +0x1f00c0c0, +0xc9007009, +0xd1077008, +0x1f077070, +0xd104c406, +0x1f04c4c4, +0x2400060d, +0x040d6666, +0x230313d1, +0x79000006, +0xc9005005, +0x51fd0304, +0x2400020d, +0x040d6666, +0x230313d1, +0xc9017005, +0x2400010d, +0x040d6666, +0x230313d1, +0x79000005, +0xc9015004, +0x2400020d, +0x040d6666, +0x230313d1, +0xc9027004, +0x2400010d, +0x040d6666, +0x230313d1, +0x111870e0, +0x5100e006, +0x1f03c4c4, +0x2400020d, +0x040d6666, +0x230313d1, +0x79000008, +0xc9035002, +0x69fd2403, +0xc9045005, +0x51fd0404, +0x2400020d, +0x040d6666, +0x230313d1, +0x2400052d, +0x24000605, +0x2300ded1, +0x1d017e7e, +0x240949e1, +0x910c3c80, +0x58e1e005, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x2302ced1, +0x100d0d63, +0x0908f5f5, +0x0b18f4e0, +0x12e0f5f5, +0x0908f4f4, +0x1263f4f4, +0xc905700e, +0xd105c40d, +0x1f05c4c4, +0x2400080d, +0x040d6666, +0x230313d1, +0x14637878, +0x69014502, +0x15ff7878, +0x240978e0, +0x09017881, +0xf0810080, +0x14582020, +0x108080d8, +0x209d0000, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x51000c12, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x810c3c80, +0x69074502, +0x2400ff1e, +0x000c1111, +0xd107110b, +0x49011103, +0x2400600b, +0x79000013, +0x49031104, +0x2400620b, +0x05021111, +0x7900000f, +0x2400600b, +0x05041111, +0x7900000c, +0x1600110b, +0x01010b0b, +0x49010b03, +0x2400600b, +0x79000007, +0x49030b04, +0x24006d0b, +0x01021111, +0x79000003, +0x24006f0b, +0x01041111, +0x24013081, +0x24ffffc1, +0x808113c1, +0xc901c40c, +0x69084504, +0x2400001e, +0x2400ff1e, +0x21034800, +0x69074507, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x2103a700, +0x51000c27, +0x51015b04, +0x100c0c02, +0x24000022, +0x79000003, +0x102a2a02, +0x100a0a22, +0x91e01800, +0x605b0002, +0x01010202, +0x69002203, +0x05010202, +0x2400ff22, +0x79000001, +0x711a2c02, +0x24001a2c, +0x910c3c81, +0x05010201, +0x2400ff1e, +0x05010101, +0x6f0001fe, +0x1022221e, +0x100b0b79, +0x3103000f, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x7900001e, +0x100b0b79, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x240800eb, +0xf00d0b6d, +0x240878e0, +0xf06d0000, +0x240860eb, +0xf02d0b4d, +0x240878e1, +0xf04d0101, +0x51030008, +0x09010000, +0x0d060000, +0xc9071104, +0x153f6d6d, +0x00001111, +0x79000002, +0x04001111, +0xc9071104, +0x51020103, +0x150f4d4d, +0x79000001, +0x09026d6d, +0x0b024d00, +0x12006d6d, +0x09064d4d, +0xc901c41a, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x2104a300, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x106d6d79, +0x3103000f, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x511f0d03, +0x51190d02, +0x79000003, +0x230757d1, +0x7900001b, +0xd10cff00, +0xd70bffff, +0xd1074d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x810c3c80, +0x511f0d13, +0x51190d12, +0xd1064d04, +0x2400001e, +0x24000026, +0x79000003, +0x2400ff1e, +0x24000126, +0xc901c402, +0x2103e800, +0x910c3c81, +0x240117e0, +0x04e1e0e0, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x209d0000, +0x10d1d1eb, +0x51002c1d, +0x910c3c80, +0x0da4e0e2, +0x102c2c6d, +0x24000b1e, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x91042581, +0xcf09e1ff, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x24001f8d, +0x2400044d, +0x230307d1, +0x05016d6d, +0x51006d0c, +0xd10cff00, +0xd70bffff, +0x24000b1e, +0x24000f8d, +0x2400044d, +0x230307d1, +0x24001f8d, +0x2400034d, +0x230307d1, +0x05016d6d, +0x6f006df6, +0x10ebebd1, +0x20d10000, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x09041001, +0x12460101, +0x31010001, +0x31010001, +0x31010001, +0x24000011, +0x810a1801, +0x59021006, +0x10d1d18b, +0x2400040d, +0x040d6666, +0x230313d1, +0x108b8bd1, +0x810c3c80, +0x20d10000, +0xd119fe02, +0xd10dff00, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0xc900c002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f020000, +0xc9022002, +0x2400269f, +0x813d1800, +0x91505880, +0x1f008080, +0x1f00c0c0, +0x1f008181, +0x81505880, +0x2105b300, +0x91042580, +0xd709e0ff, +0x91042580, +0xcf09e0ff, +0x05014d4d, +0x6f014dfb, +0x91042580, +0xd709e0ff, +0x8106058d, +0x91042580, +0xcf09e0ff, +0x20d10000, +0x117f6666, +0xc9066605, +0x2a000000, +0x24000066, +0x81031866, +0x7f0000da, +0x710f6602, +0x24000f66, +0x590e6604, +0x91aa1800, +0x1f008000, +0x81aa1800, +0x13806666, +0x81031866, +0x20d10000, +0xd10dff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x1f017e7e, +0x810c3c80, +0x24000c10, +0x51004607, +0x10464601, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010101, +0x6f0001fc, +0x20d10000, +0x240ce4e0, +0xf0300000, +0x48100002, +0x10000010, +0x20d10000, +0x2eff838e, +0x24003f00, +0x81401800, +0x8138180e, +0x8110788e, +0x8198388e, +0x2eff8587, +0x209d0000, +0x108d8dab, +0x2eff8000, +0x815a1800, +0x10323201, +0x10121221, +0x81601881, +0xd104c40f, +0x91521801, +0x1d050101, +0x1d020101, +0x5100980c, +0x913d1880, +0x1f050000, +0xc9052002, +0x2400269f, +0x813d1800, +0x1f050101, +0x81521801, +0x2400060d, +0x040d6666, +0x230313d1, +0x79000041, +0x2400010d, +0x000d6666, +0x230313d1, +0x69fd7309, +0x913d1880, +0x1f040000, +0xc9042002, +0x2400269f, +0x813d1800, +0x1f020101, +0x81521801, +0x79000035, +0x81521801, +0x0908f3e2, +0x10727202, +0x91a45800, +0x0480d281, +0x06c093c1, +0x10e1e1e2, +0xc91fe203, +0x1600e2e2, +0x0101e2e2, +0x913a18c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e204, +0x10222200, +0x10020220, +0x813a1880, +0x2400ff1e, +0x2400ff1e, +0x914218c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e207, +0x1f010101, +0x91043880, +0x1f018080, +0xc901c002, +0x2400229f, +0x81041880, +0x1d010101, +0x81501801, +0x6900e105, +0x686e5304, +0x813a188d, +0x24000019, +0x79000002, +0x230599d1, +0x10535300, +0x10333320, +0x10131340, +0x10727260, +0x10525201, +0x815b5800, +0x24000100, +0x815a1800, +0x815618c4, +0x815818d8, +0x81637894, +0x2400ff1e, +0x240000e0, +0x81983880, +0x81a4586e, +0x81701873, +0x10abab8d, +0x240000f8, +0x11cf4444, +0x2101e500, +0x108d8dab, +0x91637881, +0x91541800, +0x915618c0, +0xd105c008, +0x915818c0, +0x5100c007, +0x1f058000, +0x81541800, +0x2400060d, +0x040d6666, +0x230313d1, +0x79000017, +0x1d058000, +0x81541800, +0x2400010d, +0x000d6666, +0x230313d1, +0x91541800, +0x69fd6204, +0x1f028000, +0x81541800, +0x79000002, +0x1d028000, +0x15e06262, +0x2ed00381, +0xd1060204, +0xd1050203, +0x1d060000, +0x79000002, +0x1f060000, +0x81541800, +0x81463882, +0x814a3881, +0x2400249f, +0x915a1800, +0x69010004, +0x915b7800, +0x81197800, +0x2400239f, +0x24000300, +0x814e1800, +0x91701800, +0x81361800, +0x91081821, +0x10210001, +0x91503802, +0x1d060202, +0x1d060242, +0x5100010d, +0x91043880, +0x1f068080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f060000, +0xc9062002, +0x2400269f, +0x813d1880, +0x1f060202, +0x1f060242, +0x81503802, +0x10abab8d, +0x2101ec00, +0x91001800, +0xc9070002, +0x2102f200, +0x91351800, +0xc9070002, +0x2102f200, +0x51005c2c, +0x110ff602, +0x49085c02, +0x150f0202, +0x240978e0, +0x0b043c01, +0x14020101, +0x09010181, +0xf0810081, +0x09049c9c, +0x14819c9c, +0x71105c0a, +0xd1025c04, +0x09040200, +0x807c1800, +0x79000005, +0x907c1800, +0x12020000, +0x807c1800, +0x01017c7c, +0x79000013, +0x69045c12, +0x91043880, +0x1f098080, +0xc909c002, +0x2400229f, +0x81041880, +0x91511800, +0x1f010000, +0x81511800, +0x51009c09, +0x91043880, +0x1f0c8080, +0xc90cc002, +0x2400229f, +0x81041880, +0x91511800, +0x1f050000, +0x81511800, +0x91511800, +0x1d050000, +0x81511800, +0x05045c5c, +0x79000089, +0x0b03f700, +0x111f0000, +0x5110005d, +0xd10ac485, +0xd104005c, +0x1f0ac4c4, +0x111f006b, +0x09046b6b, +0x0902f700, +0x0b1ef620, +0x12200000, +0x110f0000, +0x12006b6b, +0x10f6f6e2, +0x24002c01, +0x31020007, +0x110f0220, +0x0b01e240, +0x11f04040, +0x12402000, +0x2d000001, +0x0b0ae2e2, +0xd1076b1e, +0x24003001, +0xd1066b0e, +0x2400010d, +0x23079dd1, +0x68ab8d45, +0x13803b3b, +0x913d1880, +0x1f008080, +0xc9002002, +0x2400229f, +0x813d1800, +0x91531800, +0x1f000000, +0x81531800, +0x7900003b, +0x2400020d, +0x23079dd1, +0x688b8d38, +0x8137184b, +0x13803b3b, +0x913d1880, +0x1f008080, +0xc9002002, +0x2400229f, +0x813d1800, +0x91531800, +0x1f000000, +0x81531800, +0x7900002d, +0x0b026b00, +0x11030000, +0x2400005c, +0x51000003, +0x2400085c, +0x08005c5c, +0x10ebebe0, +0x2ed00180, +0xc9056b05, +0x81281880, +0x8120188b, +0x2400207c, +0x79000010, +0x81281880, +0x51005c04, +0x2400227c, +0x812018c0, +0x7900000b, +0x15ff0b0b, +0x91043880, +0x1f098080, +0xc909c002, +0x2400229f, +0x81041880, +0x91511800, +0x1f010000, +0x81511800, +0x1d09c4c4, +0x2400040d, +0x24003001, +0x23079dd1, +0x15ff8d9c, +0x69005c34, +0x51009c33, +0x91043880, +0x1f0c8080, +0xc90cc002, +0x2400229f, +0x81041880, +0x91511800, +0x1f050000, +0x81511800, +0x7900002a, +0x1d0ac4c4, +0x111f2300, +0x51150023, +0x691a000a, +0x91043880, +0x1f0c8080, +0xc90cc002, +0x2400229f, +0x81041880, +0x91511800, +0x1f050000, +0x81511800, +0x79000011, +0x691f0010, +0x91043880, +0x1f0d8080, +0xc90dc002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f010000, +0xc9012002, +0x2400269f, +0x813d1800, +0x91513800, +0x1f050000, +0x1f054040, +0x81513800, +0x79000005, +0x91513800, +0x1d050000, +0x1d054040, +0x81513800, +0x69001b08, +0xd1073b07, +0x05013b3b, +0x69003b05, +0x2400403b, +0x2400181b, +0xc9027a02, +0x01081b1b, +0x2102a400, +0x24001031, +0x91001800, +0xc9060007, +0x1d060000, +0x81001800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x7900005d, +0x91351800, +0xc9060007, +0x1d060000, +0x81351800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x79000055, +0xc909c41c, +0x05041b1b, +0x490c1b06, +0x0a1b9a31, +0x110f3131, +0x69001b02, +0x1d09c4c4, +0x7900004d, +0xc9077a08, +0x905a1831, +0xc9021b03, +0x0b043131, +0x79000003, +0x110f3131, +0x01015a5a, +0x79000003, +0x0a1bfa31, +0x110f3131, +0x240978e2, +0x0b043a00, +0x14310000, +0x09010080, +0xf0800280, +0x09049a9a, +0x14809a9a, +0x69101b02, +0x15ff1a1a, +0x79000039, +0x91401800, +0x513f0016, +0x913d1840, +0x1d004040, +0x813d1840, +0x91531840, +0x1d004040, +0x81531840, +0x24003f20, +0x81401820, +0x113f007a, +0x2400009a, +0xc9070005, +0x13407a7a, +0x107a7a5a, +0x2400181b, +0x79000004, +0x91371820, +0x1020205a, +0x2400201b, +0x2400403b, +0x1f09c4c4, +0x79000022, +0x912c1800, +0xc9000020, +0x1d000000, +0x812c1800, +0x1f09c4c4, +0x91041880, +0x1d098080, +0x81041880, +0x91511800, +0x1d010000, +0x81511800, +0x91283881, +0x1001017a, +0x2400101b, +0xc9050102, +0x01101b1b, +0x0b031b00, +0x8fc4d801, +0xd1067a0c, +0x0b020101, +0x11030101, +0x51000109, +0x24000821, +0x08012101, +0x00011b1b, +0x10000040, +0x0b030100, +0x9f20d801, +0x01c44040, +0x8e40d801, +0x01101b1b, +0x2400c45a, +0x2400009a, +0x91aa1800, +0xc900000d, +0x91043880, +0x1f0a8080, +0xc90ac002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f030000, +0xc9032002, +0x2400269f, +0x813d1800, +0x1d008080, +0x81aa1800, +0x91031800, +0x590e0007, +0x91505880, +0x1f0a8080, +0x1f0ac0c0, +0x1f0a8181, +0x81505880, +0x79000006, +0x91505880, +0x1d0a8080, +0x1d0ac0c0, +0x1d0a8181, +0x81505880, +0x91501801, +0x91aa1800, +0xc901000a, +0x1d018080, +0x81aa1800, +0x91043880, +0x1f038080, +0xc903c002, +0x2400229f, +0x81041880, +0x1f030101, +0x79000002, +0x1d030101, +0x81501801, +0x21027e00, +0x24000000, +0x814e1800, +0xd103c40a, +0x151f8484, +0x240b78e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x69000d03, +0x24fdfd80, +0x68808427, +0x91381800, +0x01010000, +0x81381800, +0x91411820, +0x60200002, +0x2102f200, +0x109d9d8b, +0x0901c880, +0x090288c0, +0x0903c781, +0x090487c1, +0x00c08080, +0x0081c181, +0x00818080, +0x00898080, +0x0b058080, +0xc90a8002, +0x13f82020, +0x0080c98d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x230580d1, +0x209d0000, +0x108b8b9d, +0x91aa1800, +0x1f018000, +0x81aa1800, +0x79000010, +0x8138180d, +0x0b05848d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x230580d1, +0x91983880, +0x008e8080, +0x024ec0c0, +0x81983880, +0x10efefe0, +0x10eeeee1, +0x2ed00380, +0x81107880, +0x24000200, +0x814e1800, +0x2400209f, +0x2400259f, +0x209d0000, +0x24000001, +0xc917ee02, +0x2400ff01, +0x10eeeee0, +0x10010160, +0x00006e6e, +0x0b08e0e0, +0x10010160, +0x02e0efef, +0x91e43881, +0x10e1efef, +0x20d10000, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x20d10000, +0x01011919, +0x91983880, +0x0000526e, +0x0220720f, +0x02c093af, +0x0300536f, +0x6902190b, +0xc90fc907, +0x1600c980, +0x01018080, +0x0b038080, +0x16008080, +0x01018080, +0x79000002, +0x0b038080, +0x00808e8e, +0x03006e6e, +0x20d10000, +0x151f8484, +0x240b78e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x20d10000, +0x2effbd80, +0x2400ecc0, +0x81ea18c0, +0x240002d8, +0x24e31098, +0xf100180a, +0x15400a0a, +0x24000011, +0x1d017e7e, +0x11fc5e5e, +0x1f005e5e, +0x1f13ffff, +0x1d017e7e, +0x1f13ffff, +0x31310002, +0x0100e0e0, +0x1d035e5e, +0x240000e0, +0x81100580, +0x240003c0, +0x810605c0, +0x2eff8383, +0x2303409d, +0x24000866, +0x2400000c, +0x2400002c, +0x91001800, +0x1d070000, +0x81001800, +0x2eff8000, +0x81351800, +0x91501880, +0x11da8080, +0x13108080, +0x81501880, +0x91521880, +0x11f48080, +0x13108080, +0x81521880, +0x91541880, +0x11748080, +0x13108080, +0x81541880, +0x240128e1, +0x90e13382, +0x1d00e2e2, +0xc901e002, +0x1f01e2e2, +0x80e13382, +0x9101185b, +0x51005b0e, +0x7900000d, +0x23073fd1, +0x91dc388c, +0x240000e2, +0x91e21882, +0x104c4c0a, +0x100c0c2a, +0x106c6c4a, +0x102c2c6a, +0x23073fd1, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x2400001e, +0x2400001e, +0x2400001e, +0x2400001e, +0x1f12ffff, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0x240000ca, +0x24001f8d, +0x23019c9d, +0x2302aed1, +0x0101caca, +0x6f02cafc, +0x240000ca, +0x2400198d, +0x23019c9d, +0x2302aed1, +0x0101caca, +0x6f10cafc, +0x2400017b, +0x24000925, +0x24001a8d, +0x23019c9d, +0xd10dff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31000002, +0x0100e0e0, +0x1f017e7e, +0x810c3c80, +0x24004805, +0x2eff8592, +0x24005401, +0x2400000b, +0x24000021, +0x24000845, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x69000b0e, +0x51ff000d, +0x240878e2, +0xf0000202, +0x0104e206, +0x61080602, +0x05080606, +0x0d070606, +0x69400504, +0x69064503, +0x71030602, +0x24000006, +0x1e06f6f6, +0x2400010b, +0x05014545, +0xc8068002, +0x1e452121, +0x10000020, +0x69080503, +0x6f0145ea, +0x79000005, +0x6f0045e8, +0x2d802101, +0x05080505, +0x6f0005e3, +0x240947e3, +0xc919ff00, +0x103f3f00, +0x05014545, +0xc8060002, +0x1e452121, +0x10000020, +0x2d802101, +0x910c3c99, +0x58e3f96e, +0x04f9e3eb, +0x100b0b19, +0x0b01ebeb, +0x0501ebeb, +0x4f00ebff, +0x1d017e7e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x24000011, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x91042582, +0xd709e2ff, +0x810c3c80, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0x2400ff1e, +0x24000065, +0x69012501, +0x01016565, +0x0901f4f4, +0x0b077300, +0x1200f4f4, +0x0901f3f3, +0x0b077200, +0x12001313, +0x0901f2f2, +0x23074bd1, +0x510e6506, +0x6f010df6, +0x10656546, +0x05012525, +0x4f00255a, +0x7900001c, +0x2a000000, +0xd119fe0c, +0xd10dff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2a000000, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0xc900c002, +0x2400229f, +0x81041880, +0x913d1880, +0x1f020000, +0xc9022002, +0x2400269f, +0x813d1800, +0x7d0000d4, +0x24000925, +0x24001b8d, +0x23019c9d, +0x2307119d, +0x23074bd1, +0x6f010dec, +0x05012525, +0x4f0025fa, +0x24001025, +0x24001c8d, +0x23019c9d, +0x2307119d, +0x23074bd1, +0x6f010dd8, +0x05012525, +0x4f0025fa, +0x810a1846, +0x24001d8d, +0x23019c9d, +0x2301219d, +0x6e0403d1, +0x6e2423d0, +0x110f4300, +0x0b044320, +0x6e2000cd, +0x10848480, +0x10434340, +0x10404001, +0x10202021, +0x10000041, +0x810d3801, +0x2400000d, +0x000d6666, +0x230313d1, +0x1f08c4c4, +0x110fe05d, +0x01085d5d, +0x0b04e07d, +0x113f7d7d, +0x005d7d7d, +0x050c7d7d, +0x010c7d00, +0x0d280000, +0x24ffffc1, +0x24ffff81, +0x0a00e1e1, +0x81e43881, +0x2302aed1, +0x21001600, +0x24002005, +0x230322d1, +0x24000080, +0x240ca4eb, +0x2eff8992, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05f4f4, +0x10000020, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0005f6, +0x24001d05, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05f3f3, +0x10000020, +0x0b018001, +0x14000130, +0x23033bd1, +0x6f0105f6, +0xc919ff00, +0x103f3f00, +0xc8068002, +0x1f00f3f3, +0x0903f3f3, +0x1f19ffff, +0x240947e1, +0x910c3c80, +0x58e1e006, +0x04e0e1e0, +0x0101e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x1d017e7e, +0x2302ced1, +0x2302aed1, +0x209d0000, +0x91502181, +0x91502194, +0x56e1f4ff, +0x04e1f4f4, +0x20d10000, +0x240000e0, +0x60cd8d04, +0x04cd8d8d, +0x0101e0e0, +0x7f0000fd, +0x10e0e0cd, +0x20d10000, +0x91acb880, +0x10e2f3eb, +0x240ff8e2, +0x10e2f3e2, +0x0901e2e2, +0x12ebe2eb, +0x68e0f404, +0x68e1eb03, +0x2400010d, +0x20d10000, +0x2400000d, +0x20d10000, +0x13154d4d, +0x104d4d79, +0x3103000f, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x24000800, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0x05010000, +0x6f0000ef, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x240117e0, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x240012e0, +0x810c3c80, +0x20d10000, +0x91043880, +0x1e0d8080, +0xc80dc002, +0x2400229f, +0x81041880, +0x20d10000, +0x240978e2, +0x100d0d40, +0x2400008d, +0x24000080, +0x2c600100, +0x14002d00, +0x09018080, +0xf0800280, +0x09088d8d, +0x148d808d, +0x05014040, +0x4f0040f8, +0x15ff0d0d, +0x20d10000, +0x91003c82, +0x1308e2e2, +0x81003c82, +0x2105b200, +0x244030c2, +0x24000082, +0x240000c1, +0x24210081, +0x240c00eb, +0x0504ebeb, +0xf0eb2180, +0xe0eb2280, +0x6f00ebfd, +0x21000000 }; diff --git a/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_ch2_bin.h b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_ch2_bin.h new file mode 100644 index 0000000..9a8894c --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_ch2_bin.h @@ -0,0 +1,1824 @@ +/* + * hdsl_master_icssg_300_mhz_ch2_bin.h + * + * + * Copyright (c) 2021 - 2023, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int Hiperface_DSL2_0_TX[]= { +0x2106d900, +0x24000125, +0x2eff818f, +0x24001d8d, +0x2301b19d, +0xd115ff00, +0x91143a8e, +0x1d027e7e, +0x510c4608, +0x240943e1, +0x91143a80, +0x04eee0e0, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x23029cd1, +0x23027cd1, +0x05012525, +0x6f0025f0, +0x2eff8f8e, +0x24000725, +0x2eff8f8e, +0x24000725, +0x24041e8d, +0x2301b19d, +0x2301369d, +0x05012525, +0x5100257b, +0x23027cd1, +0xd70170f8, +0xcf0723f7, +0x1f02c4c4, +0x2400088d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x2400098d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x240008c5, +0x24000065, +0x24001031, +0x240000f8, +0x2400042d, +0xc902c402, +0x1f012d2d, +0x69014503, +0x240004e0, +0x14e0c4c4, +0x11807070, +0x1031310d, +0x51015904, +0x2301b19d, +0x24000159, +0x79000003, +0x2301de9d, +0x10e0e0e0, +0x2301369d, +0xd101700f, +0xc9072306, +0x5101450a, +0x2400040d, +0x040d6666, +0x2302d7d1, +0x79000009, +0x69014508, +0x2400060d, +0x040d6666, +0x2302d7d1, +0x79000004, +0x2400010d, +0x000d6666, +0x2302d7d1, +0x1d03c4c4, +0x23027cd1, +0x51000c2d, +0x24002f1b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x2400ff1b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x810c3c80, +0x79000005, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x2400001e, +0x23064e9d, +0x05014545, +0x49004502, +0x21009100, +0x2400ff1e, +0x2400001e, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x2400ff1e, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x2400ff1e, +0x7f0000a1, +0x24000070, +0x24000845, +0x1f01c4c4, +0x2400ff1e, +0x2400001e, +0x7f00009b, +0x2400ff1e, +0x1f12ffff, +0x2400ff1b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x2100ae00, +0x2102bf00, +0x10d1d182, +0x240000cd, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230303d1, +0x6f0005f7, +0x240f20eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230303d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230303d1, +0x110fcdc0, +0x240f68eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x10d1d182, +0x240000cd, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230303d1, +0x6f0005f7, +0x240f20eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230303d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230303d1, +0x110fcdc0, +0x240f68eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x24000605, +0x2eff8283, +0x2302ebd1, +0x240000c0, +0x2400002d, +0x2300b0d1, +0x100d0d03, +0x0908f3f3, +0x0b18f2e0, +0x12e0f3f3, +0x0908f2f2, +0x1203f2f2, +0x14033838, +0x69014502, +0x15ff3838, +0x241078e0, +0x09013881, +0xf0810080, +0x14182020, +0x10808098, +0x2400012d, +0x24000605, +0x2300b0d1, +0x100d0d23, +0x0905f7f7, +0x0b1bf6e0, +0x12e0f7f7, +0x0905f6f6, +0x111f23e0, +0x12e0f6f6, +0x2400022d, +0x24000605, +0x2300b0d1, +0x100d0d43, +0x2400032d, +0x24000605, +0x2300b0d1, +0x100d0d84, +0x2400042d, +0x24000605, +0x2300b0d1, +0x09088484, +0x120d8484, +0x240000c0, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0xc8068002, +0x1f00c0c0, +0xc9007009, +0xd1077008, +0x1f077070, +0xd104c406, +0x1f04c4c4, +0x2400060d, +0x040d6666, +0x2302d7d1, +0x79000006, +0xc9005005, +0x51fd0304, +0x2400020d, +0x040d6666, +0x2302d7d1, +0xc9017005, +0x2400010d, +0x040d6666, +0x2302d7d1, +0x79000005, +0xc9015004, +0x2400020d, +0x040d6666, +0x2302d7d1, +0xc9027004, +0x2400010d, +0x040d6666, +0x2302d7d1, +0x111870e0, +0x5100e006, +0x1f03c4c4, +0x2400020d, +0x040d6666, +0x2302d7d1, +0x79000008, +0xc9035002, +0x69fd2403, +0xc9045005, +0x51fd0404, +0x2400020d, +0x040d6666, +0x2302d7d1, +0x2400052d, +0x24000605, +0x2300f3d1, +0x1d027e7e, +0x240949e1, +0x910c3c80, +0x58e1e005, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x23029cd1, +0x100d0d63, +0x0908f5f5, +0x0b18f4e0, +0x12e0f5f5, +0x0908f4f4, +0x1263f4f4, +0xc905700e, +0xd105c40d, +0x1f05c4c4, +0x2400080d, +0x040d6666, +0x2302d7d1, +0x14637878, +0x69014502, +0x15ff7878, +0x241078e0, +0x09017881, +0xf0810080, +0x14582020, +0x108080d8, +0x209d0000, +0xd114ff00, +0xd713ffff, +0x2400001e, +0xd114ff00, +0xd713ffff, +0x2400001e, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0xd114ff00, +0xd713ffff, +0x2400001e, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x2400ff1e, +0x51000c17, +0x2400ff1b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x810c3c80, +0x000c1111, +0xd107110b, +0x49011103, +0x2400600b, +0x79000013, +0x49031104, +0x2400620b, +0x05021111, +0x7900000f, +0x2400600b, +0x05041111, +0x7900000c, +0x1600110b, +0x01010b0b, +0x49010b03, +0x2400600b, +0x79000007, +0x49030b04, +0x24006d0b, +0x01021111, +0x79000003, +0x24006f0b, +0x01041111, +0x24013081, +0x24ffffc1, +0x808113c1, +0xc901c405, +0x69084504, +0x2400ff1e, +0x2400ff1e, +0x21050500, +0x51000c29, +0x51015b04, +0x100c0c02, +0x24000022, +0x79000003, +0x102a2a02, +0x100a0a22, +0x91e01800, +0x605b0002, +0x01010202, +0x69002203, +0x05010202, +0x2400ff22, +0x79000001, +0x711a2c02, +0x24001a2c, +0x910c3c81, +0x05010201, +0x2400ff1e, +0x05010101, +0x6f0001fe, +0x1022221e, +0x3103000f, +0xd1070b05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09010b0b, +0xd1070b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09010b0b, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x79000010, +0x3103000f, +0xd1070b05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09010b0b, +0xd1070b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09010b0b, +0x240f00eb, +0xf00d0b6d, +0x240f78e0, +0xf06d0000, +0x240f60eb, +0xf02d0b4d, +0x240f78e1, +0xf04d0101, +0x51030008, +0x09010000, +0x0d060000, +0xc9071104, +0x153f6d6d, +0x00001111, +0x79000002, +0x04001111, +0xc9071104, +0x51020103, +0x150f4d4d, +0x79000001, +0x09026d6d, +0x0b024d00, +0x12006d6d, +0x09064d4d, +0xc901c402, +0x2105f600, +0x3103000f, +0xd1076d05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09016d6d, +0xd1076d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09016d6d, +0x511f0d03, +0x51190d02, +0x79000003, +0x2304b3d1, +0x79000019, +0xd1074d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x810c3c80, +0x511f0d13, +0x51190d12, +0xc901c402, +0x21056900, +0x910c3c81, +0x240117e0, +0x04e1e0e0, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0xd1064d04, +0x2400001e, +0x24000026, +0x79000003, +0x2400ff1e, +0x24000126, +0x209d0000, +0x10d1d1eb, +0x51002c1d, +0x910c3c80, +0x0da4e0e2, +0x102c2c6d, +0x24000b1e, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x91042581, +0xcf0ae1ff, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x24001f8d, +0x2400044d, +0x2302cbd1, +0x05016d6d, +0x51006d0c, +0xd114ff00, +0xd713ffff, +0x24000b1e, +0x24000f8d, +0x2400044d, +0x2302cbd1, +0x24001f8d, +0x2400034d, +0x2302cbd1, +0x05016d6d, +0x6f006df6, +0x10ebebd1, +0x20d10000, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x2400001e, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x2400ff1e, +0x09041001, +0x12460101, +0x24000011, +0x810a1801, +0x59021006, +0x10d1d18b, +0x2400040d, +0x040d6666, +0x2302d7d1, +0x108b8bd1, +0x91042580, +0xd70ae0ff, +0x810c3c80, +0x20d10000, +0xd11afe02, +0xd115ff00, +0x91a91800, +0x01010000, +0x81a91800, +0x2400008d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x21030a00, +0x91042580, +0xd70ae0ff, +0x91042580, +0xcf0ae0ff, +0x05014d4d, +0x6f014dfb, +0x91042580, +0xd70ae0ff, +0x8106058d, +0x91042580, +0xcf0ae0ff, +0x20d10000, +0x117f6666, +0xc9066605, +0x2a000000, +0x24000066, +0x81031866, +0x7f0000e3, +0x710f6602, +0x24000f66, +0x590e6609, +0x10d1d1e1, +0x24000a8d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x10e1e1d1, +0x13806666, +0x81031866, +0x20d10000, +0xd115ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x1f027e7e, +0x810c3c80, +0x24000c10, +0x51004607, +0x10464601, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0x05010101, +0x6f0001fc, +0x20d10000, +0x2413e4e0, +0xf0300000, +0x48100002, +0x10000010, +0x20d10000, +0x2a000000, +0x2effbd80, +0x2400ecc0, +0x81ea18c0, +0x240002d8, +0x24e31098, +0xf100180a, +0x15400a0a, +0x24000011, +0x1d027e7e, +0x11fc5e5e, +0x1f015e5e, +0x1f13ffff, +0x1d027e7e, +0x1f13ffff, +0x31310002, +0x0100e0e0, +0x1d035e5e, +0x240000e0, +0x81180580, +0x240003c0, +0x810605c0, +0x2eff8383, +0x2304fd9d, +0x24000866, +0x2400000c, +0x2400002c, +0x91001800, +0x1d070000, +0x81001800, +0x240128e1, +0x90e13382, +0x1d00e2e2, +0xc901e002, +0x1f01e2e2, +0x80e13382, +0x9101185b, +0x51005b0e, +0x7900000d, +0x23049bd1, +0x91dc388c, +0x240000e2, +0x91e21882, +0x104c4c0a, +0x100c0c2a, +0x106c6c4a, +0x102c2c6a, +0x23049bd1, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x2400001e, +0x2400001e, +0x2400001e, +0x2400001e, +0x1f12ffff, +0x2400001b, +0x3103000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0x2400001b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x2400003b, +0x24001f8d, +0x2301b19d, +0x23027cd1, +0x01013b3b, +0x6f023bfc, +0x2400003b, +0x2400198d, +0x2301b19d, +0x23027cd1, +0x01013b3b, +0x6f103bfc, +0x2400017b, +0x24000925, +0x24001a8d, +0x2301b19d, +0xd115ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31000002, +0x0100e0e0, +0x1f027e7e, +0x810c3c80, +0x24004805, +0x2eff8592, +0x24005401, +0x2400000b, +0x24000021, +0x24000845, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0x69000b0e, +0x51ff000d, +0x240f78e2, +0xf0000202, +0x0104e206, +0x61080602, +0x05080606, +0x0d070606, +0x69400504, +0x69064503, +0x71030602, +0x24000006, +0x1e06f6f6, +0x2400010b, +0x05014545, +0xc8068002, +0x1e452121, +0x10000020, +0x69080503, +0x6f0145ea, +0x79000005, +0x6f0045e8, +0x2d802101, +0x05080505, +0x6f0005e3, +0x240947e3, +0xc91aff00, +0x105f5f00, +0x05014545, +0xc8060002, +0x1e452121, +0x10000020, +0x2d802101, +0x910c3c99, +0x58e3f981, +0x04f9e3eb, +0x100b0b19, +0x0b01ebeb, +0x0501ebeb, +0x4f00ebff, +0x1d027e7e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd114ff00, +0xd713ffff, +0x2400001e, +0xd114ff00, +0xd713ffff, +0x2400001e, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x24000011, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x91042582, +0xd70ae2ff, +0x810c3c80, +0x24002c1b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x2400b21b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x2400cb1b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x24000065, +0x69012501, +0x01016565, +0x0901f4f4, +0x0b077300, +0x1200f4f4, +0x0901f3f3, +0x0b077200, +0x12001313, +0x0901f2f2, +0x2304a7d1, +0x510e6506, +0x6f010df6, +0x10656546, +0x05012525, +0x4f002547, +0x79000014, +0x2a000000, +0xd11afe0c, +0xd115ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2a000000, +0x91a91800, +0x01010000, +0x81a91800, +0x2400008d, +0x2306c5d1, +0x7d0000cf, +0x24000925, +0x24001b8d, +0x2301b19d, +0x23046d9d, +0x2304a7d1, +0x6f010df4, +0x05012525, +0x4f0025fa, +0x24001025, +0x24001c8d, +0x2301b19d, +0x23046d9d, +0x2304a7d1, +0x6f010de0, +0x05012525, +0x4f0025fa, +0x810a1846, +0x24001d8d, +0x2301b19d, +0x2301369d, +0x6e0403d9, +0x6e2423d8, +0x110f4300, +0x0b044320, +0x6e2000d5, +0x10848480, +0x10434340, +0x10404001, +0x10202021, +0x10000041, +0x810d3801, +0x2400000d, +0x000d6666, +0x2302d7d1, +0x1f08c4c4, +0x110fe05d, +0x01085d5d, +0x0b04e07d, +0x113f7d7d, +0x005d7d7d, +0x050c7d7d, +0x010c7d00, +0x0d280000, +0x24ffffc1, +0x24ffff81, +0x0a00e1e1, +0x81e43881, +0x23027cd1, +0x21001600, +0x24002005, +0x2302ebd1, +0x24000080, +0x2413a4eb, +0x2eff8992, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0x05010505, +0xc8068002, +0x1e05f4f4, +0x10000020, +0x0b018001, +0x14000130, +0x230303d1, +0x6f0005f6, +0x24001d05, +0xc91aff00, +0x105f5f00, +0x1f1affff, +0x05010505, +0xc8068002, +0x1e05f3f3, +0x10000020, +0x0b018001, +0x14000130, +0x230303d1, +0x6f0105f6, +0xc91aff00, +0x105f5f00, +0xc8068002, +0x1f00f3f3, +0x0903f3f3, +0x1f1affff, +0x240947e1, +0x910c3c80, +0x58e1e006, +0x04e0e1e0, +0x0101e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x1d027e7e, +0x23029cd1, +0x23027cd1, +0x209d0000, +0x91502181, +0x91502194, +0x56e1f4ff, +0x04e1f4f4, +0x20d10000, +0x240000e0, +0x60cd8d04, +0x04cd8d8d, +0x0101e0e0, +0x7f0000fd, +0x10e0e0cd, +0x20d10000, +0x91acb880, +0x10e2f3eb, +0x240ff8e2, +0x10e2f3e2, +0x0901e2e2, +0x12ebe2eb, +0x68e0f404, +0x68e1eb03, +0x2400010d, +0x20d10000, +0x2400000d, +0x20d10000, +0x13154d4d, +0x3103000f, +0xd1074d05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09014d4d, +0xd1074d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09014d4d, +0x24000800, +0x2400551b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x05010000, +0x6f0000ea, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x240117e0, +0x2400ff1e, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x2400ff1e, +0x2400031b, +0x3105000a, +0xd107fb05, +0xd114ff00, +0xd713ffff, +0x2400001e, +0x79000004, +0xd114ff00, +0xd713ffff, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0xd1071b03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09011b1b, +0x240012e0, +0x24001ee0, +0x810c3c80, +0x20d10000, +0x2eff838e, +0x24003f00, +0x81401800, +0x8138180e, +0x8110788e, +0x8198388e, +0x2eff8587, +0x209d0000, +0x108d8dab, +0x10323201, +0x10121221, +0x811e1881, +0xd104c40b, +0x5100980b, +0x2400050d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x2400060d, +0x040d6666, +0x2302d7d1, +0x79000040, +0x2400010d, +0x000d6666, +0x2302d7d1, +0x69fd7308, +0x2400020d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x79000035, +0x0908f3e2, +0x10727202, +0x91a45800, +0x0480d281, +0x06c093c1, +0x10e1e1e2, +0xc91fe203, +0x1600e2e2, +0x0101e2e2, +0x913a18c0, +0x10404000, +0x10606040, +0x10000060, +0x70c0e204, +0x10222200, +0x10020220, +0x813a1880, +0x914218c0, +0x10404000, +0x10606040, +0x10000060, +0x70c0e207, +0x2400010d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x6900e105, +0x686e5304, +0x813a188d, +0x24000019, +0x79000002, +0x2306acd1, +0x2400ff1e, +0x2400ff1e, +0x10535300, +0x10333320, +0x10131340, +0x10727260, +0x10525201, +0x81195800, +0x15e07575, +0x2ed00394, +0x81463895, +0x81541815, +0x2400249f, +0x2400229f, +0x814a3894, +0x241003e0, +0x814e1800, +0x2400209f, +0x240000e0, +0x81983880, +0x81a4586e, +0x81181873, +0x91081821, +0x10217301, +0x51000106, +0x91043880, +0x1f068080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x91043880, +0x81501880, +0x81521880, +0x2400239f, +0x2400229f, +0x10abab8d, +0x240000f8, +0x11cf4444, +0x2101fd00, +0x91001800, +0xc9070002, +0x2102bf00, +0xc901c489, +0x51005c25, +0x110ff602, +0x49085c02, +0x150f0202, +0x241078e0, +0x0b043c01, +0x14020101, +0x09010181, +0xf0810081, +0x09049c9c, +0x14819c9c, +0x71105c0a, +0xd1025c04, +0x09040200, +0x807c1800, +0x79000005, +0x907c1800, +0x12020000, +0x807c1800, +0x01017c7c, +0x7900000f, +0x69045c0e, +0x2400098d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x51009c07, +0x24000c0d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x05045c5c, +0x79000064, +0x0b03f700, +0x111f0000, +0x5110004f, +0xd10ac460, +0xd104004e, +0x1f0ac4c4, +0x111f006b, +0x09046b6b, +0x0902f700, +0x0b1ef620, +0x12200000, +0x110f0000, +0x12006b6b, +0x10f6f6e2, +0x24002c01, +0x31020007, +0x110f0220, +0x0b01e240, +0x11f04040, +0x12402000, +0x2d000001, +0x0b0ae2e2, +0xd1076b14, +0x24003001, +0xd1066b06, +0x2400010d, +0x2306cbd1, +0x68ab8d37, +0x13803b3b, +0x79000035, +0x2400020d, +0x2306cbd1, +0x688b8d32, +0x8137184b, +0x13803b3b, +0x2400088d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x79000029, +0x0b026b00, +0x11030000, +0x2400005c, +0x51000003, +0x2400085c, +0x08005c5c, +0x10ebebe0, +0x2ed00180, +0xc9056b05, +0x81281880, +0x8120188b, +0x2400207c, +0x7900000e, +0x81281880, +0x51005c04, +0x2400227c, +0x812018c0, +0x79000009, +0x15ff0b0b, +0x2400090d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x1d09c4c4, +0x2400040d, +0x24003001, +0x2306cbd1, +0x15ff8d9c, +0x69005c1b, +0x51009c1a, +0x24000c0d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x79000013, +0x1d0ac4c4, +0x111f2300, +0x5115000c, +0x691a0007, +0x24000c0d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x69001b08, +0xd1073b07, +0x05013b3b, +0x69003b05, +0x2400403b, +0x2400181b, +0xc9027a02, +0x01081b1b, +0x21026c00, +0x24001031, +0x91001800, +0xc9060007, +0x1d060000, +0x81001800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x7900004f, +0xc909c41c, +0x05041b1b, +0x490c1b06, +0x0a1b9a31, +0x110f3131, +0x69001b02, +0x1d09c4c4, +0x79000047, +0xc9077a08, +0x905a1831, +0xc9021b03, +0x0b043131, +0x79000003, +0x110f3131, +0x01015a5a, +0x79000003, +0x0a1bfa31, +0x110f3131, +0x241078e2, +0x0b043a00, +0x14310000, +0x09010080, +0xf0800280, +0x09049a9a, +0x14809a9a, +0x69101b02, +0x15ff1a1a, +0x79000033, +0x91401800, +0x513f0013, +0x910418c0, +0x1d08c0c0, +0x810418c0, +0x2400ff20, +0x81401820, +0x113f007a, +0x2400009a, +0xc9070005, +0x13407a7a, +0x107a7a5a, +0x2400181b, +0x79000004, +0x91371820, +0x1020205a, +0x2400201b, +0x2400403b, +0x1f09c4c4, +0x7900001f, +0x912c1800, +0xc900001d, +0x1d000000, +0x812c1800, +0x1f09c4c4, +0x91041880, +0x1d098080, +0x81041880, +0x91283881, +0x1001017a, +0x2400101b, +0xc9050102, +0x01101b1b, +0x0b031b00, +0x8fc4d801, +0xd1067a0c, +0x0b020101, +0x11030101, +0x51000109, +0x24000821, +0x08012101, +0x00011b1b, +0x10000040, +0x0b030100, +0x9f20d801, +0x01c44040, +0x8e40d801, +0x01101b1b, +0x2400c45a, +0x2400009a, +0x21024f00, +0x24000000, +0x814e1800, +0xd103c405, +0x2306bed1, +0x69000d03, +0x24fdfd80, +0x6880841f, +0x91381800, +0x01010000, +0x81381800, +0x91411820, +0x60200002, +0x2102bf00, +0x109d9d8b, +0x0901c880, +0x090288c0, +0x0903c781, +0x090487c1, +0x00c08080, +0x0081c181, +0x00818080, +0x00898080, +0x0b058080, +0xc90a8002, +0x13f82020, +0x0080c98d, +0x23069fd1, +0x230693d1, +0x209d0000, +0x108b8b9d, +0x2400038d, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x79000005, +0x8138180d, +0x0b05848d, +0x23069fd1, +0x230693d1, +0x91983880, +0x008e8080, +0x024ec0c0, +0x81983880, +0x10efefe0, +0x10eeeee1, +0x2ed00380, +0x81107880, +0x24000200, +0x814e1800, +0x2400209f, +0x2400259f, +0x209d0000, +0x0901c880, +0x090288c0, +0x0903c781, +0x090487c1, +0x00c08080, +0x0081c181, +0x00818080, +0x00898080, +0x0b058080, +0xc90a8002, +0x13f82020, +0x0080c98d, +0x23069fd1, +0x230693d1, +0x209d0000, +0x24000001, +0xc917ee02, +0x2400ff01, +0x10eeeee0, +0x10010160, +0x00006e6e, +0x0b08e0e0, +0x10010160, +0x02e0efef, +0x91e43881, +0x10e1efef, +0x20d10000, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x20d10000, +0x01011919, +0x91983880, +0x0000526e, +0x0220720f, +0x02c093af, +0x0300536f, +0x6902190b, +0xc90fc907, +0x1600c980, +0x01018080, +0x0b038080, +0x16008080, +0x01018080, +0x79000002, +0x0b038080, +0x00808e8e, +0x03006e6e, +0x20d10000, +0x151f8484, +0x241278e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x20d10000, +0x91043880, +0x1e0d8080, +0xc8c0c002, +0x2400229f, +0x81041880, +0x20d10000, +0x241078e2, +0x100d0d40, +0x2400008d, +0x24000080, +0x2c600100, +0x14002d00, +0x09018080, +0xf0800280, +0x09088d8d, +0x148d808d, +0x05014040, +0x4f0040f8, +0x15ff0d0d, +0x20d10000, +0x91003c82, +0x1308e2e2, +0x81003c82, +0x21030900, +0x244030c2, +0x24000082, +0x240000c1, +0x24210081, +0x240c00eb, +0x0504ebeb, +0xf0eb2180, +0xe0eb2280, +0x6f00ebfd, +0x21000000 }; diff --git a/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h new file mode 100644 index 0000000..b819582 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h @@ -0,0 +1,1671 @@ +/* + * hdsl_master_icssg_bin.h + * + * + * Copyright (c) 2015 - 2016, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int Hiperface_DSL2_0[]= { +0x21064a00, +0x24000125, +0x2eff818f, +0x24001d8d, +0x23016a9d, +0xd105ff00, +0x91143a8e, +0x1d007e7e, +0x510c4608, +0x2406f5e1, +0x91143a80, +0x04eee0e0, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x230216d1, +0x2301f7d1, +0x05012525, +0x6f0025f0, +0x2eff8f8e, +0x24000725, +0x2eff8f8e, +0x24000725, +0x24041e8d, +0x23016a9d, +0x2300ef9d, +0x05012525, +0x5100254c, +0x2301f7d1, +0xd70170f8, +0xcf0723f7, +0x1f02c4c4, +0x913d1880, +0x1f000000, +0x813d1800, +0xc9002002, +0x2400269f, +0x91531800, +0x1f000000, +0x81531800, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x240008c5, +0x24001031, +0x240000f8, +0x2400042d, +0xc902c402, +0x1f012d2d, +0x69014503, +0x240004e0, +0x14e0c4c4, +0x11807070, +0x1031310d, +0x51015904, +0x23016a9d, +0x24000159, +0x79000003, +0x2301709d, +0x10e0e0e0, +0x2300ef9d, +0xd101700f, +0xc9072306, +0x5101450a, +0x2400040d, +0x040d6666, +0x23024ed1, +0x79000009, +0x69014508, +0x2400060d, +0x040d6666, +0x23024ed1, +0x79000004, +0x2400010d, +0x000d6666, +0x23024ed1, +0x1d03c4c4, +0x2301f7d1, +0x51000c09, +0xd104ff00, +0xd703ffff, +0x24002f1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x810c3c80, +0x79000004, +0xd104ff00, +0xd703ffff, +0x24002f1e, +0x23045c9d, +0x05014545, +0x4f0045d2, +0x24000070, +0x01016565, +0x24000845, +0x1f01c4c4, +0x7f0000cd, +0x21022d00, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230269d1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230269d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230269d1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230269d1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230269d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230269d1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x24000605, +0x2eff8283, +0x23025dd1, +0x240000c0, +0x2400002d, +0x230069d1, +0x100d0d03, +0x0908f3f3, +0x0b18f2e0, +0x12e0f3f3, +0x0908f2f2, +0x1203f2f2, +0x14033838, +0x69014502, +0x15ff3838, +0x240278e0, +0x09013881, +0xf0810080, +0x14182020, +0x10808098, +0x2400012d, +0x24000605, +0x230069d1, +0x100d0d23, +0x0905f7f7, +0x0b1bf6e0, +0x12e0f7f7, +0x0905f6f6, +0x111f23e0, +0x12e0f6f6, +0x2400022d, +0x24000605, +0x230069d1, +0x100d0d43, +0x2400032d, +0x24000605, +0x230069d1, +0x100d0d84, +0x2400042d, +0x24000605, +0x230069d1, +0x09088484, +0x120d8484, +0x240000c0, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00c0c0, +0xc9007009, +0xd1077008, +0x1f077070, +0xd104c406, +0x1f04c4c4, +0x2400060d, +0x040d6666, +0x23024ed1, +0x79000006, +0xc9005005, +0x51fd0304, +0x2400020d, +0x040d6666, +0x23024ed1, +0xc9017005, +0x2400010d, +0x040d6666, +0x23024ed1, +0x79000005, +0xc9015004, +0x2400020d, +0x040d6666, +0x23024ed1, +0xc9027004, +0x2400010d, +0x040d6666, +0x23024ed1, +0x111870e0, +0x5100e006, +0x1f03c4c4, +0x2400020d, +0x040d6666, +0x23024ed1, +0x79000008, +0xc9035002, +0x69fd2403, +0xc9045005, +0x51fd0404, +0x2400020d, +0x040d6666, +0x23024ed1, +0x2400052d, +0x24000605, +0x2300acd1, +0x1d007e7e, +0x2406f9e1, +0x910c3c80, +0x58e1e005, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x230216d1, +0x100d0d63, +0x0908f5f5, +0x0b18f4e0, +0x12e0f5f5, +0x0908f4f4, +0x1263f4f4, +0xc905700e, +0xd105c40d, +0x1f05c4c4, +0x2400080d, +0x040d6666, +0x23024ed1, +0x14637878, +0x69014502, +0x15ff7878, +0x240278e0, +0x09017881, +0xf0810080, +0x14582020, +0x108080d8, +0x209d0000, +0xd104ff00, +0xd703ffff, +0x24002f1e, +0x51000c03, +0x2400ff1e, +0x810c3c80, +0x000c1111, +0xd107110b, +0x49011103, +0x2400600b, +0x79000013, +0x49031104, +0x2400620b, +0x05021111, +0x7900000f, +0x2400600b, +0x05041111, +0x7900000c, +0x1600110b, +0x01010b0b, +0x49010b03, +0x2400600b, +0x79000007, +0x49030b04, +0x24006d0b, +0x01021111, +0x79000003, +0x24006f0b, +0x01041111, +0x24013081, +0x24ffffc1, +0x808113c1, +0xc901c405, +0x69084502, +0x21027600, +0x69074502, +0x2102d100, +0x51000c2b, +0x51015b04, +0x100c0c02, +0x24000022, +0x79000003, +0x102a2a02, +0x100a0a22, +0x91e01800, +0x605b0002, +0x01010202, +0x69002203, +0x05010202, +0x2400ff22, +0x79000001, +0x711a2c02, +0x24001a2c, +0x910c3c81, +0x2400c7e0, +0x04e1e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240002c0, +0x810605c0, +0x05010201, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x05010101, +0x6f0001fc, +0x240021e0, +0xd104ff00, +0xd703ffff, +0x1022221e, +0xd104ff00, +0xd703ffff, +0x100b0b1e, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240017c0, +0x810605c0, +0x79000002, +0x100b0b1e, +0x240100eb, +0xf00d0b6d, +0x240178e0, +0xf06d0000, +0x240160eb, +0xf02d0b4d, +0x240178e1, +0xf04d0101, +0x51030008, +0x09010000, +0x0d060000, +0xc9071104, +0x153f6d6d, +0x00001111, +0x79000002, +0x04001111, +0xc9071104, +0x51020103, +0x150f4d4d, +0x79000001, +0x09026d6d, +0x0b024d00, +0x12006d6d, +0x09064d4d, +0xc901c402, +0x2103cd00, +0xd104ff00, +0xd703ffff, +0x106d6d1e, +0x511f0d03, +0x51190d02, +0x79000003, +0x230611d1, +0x7900001a, +0xd104ff00, +0xd703ffff, +0xd1074d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x810c3c80, +0x511f0d12, +0x51190d11, +0xc901c402, +0x21031200, +0x910c3c81, +0x2400cfe0, +0x04e1e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240002c0, +0x810605c0, +0xd1064d04, +0x2400001e, +0x24000026, +0x79000003, +0x2400ff1e, +0x24000126, +0x209d0000, +0x10d1d1eb, +0x51002c1c, +0x910c3c80, +0x0d7ce0e2, +0x102c2c6d, +0x24000b1e, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x91042581, +0xcf08e1ff, +0x24000bc1, +0x810605c1, +0x2400178d, +0x2400044d, +0x230242d1, +0x05016d6d, +0x51006d0c, +0xd104ff00, +0xd703ffff, +0x24000b1e, +0x24000b8d, +0x2400044d, +0x230242d1, +0x2400178d, +0x2400034d, +0x230242d1, +0x05016d6d, +0x6f006df6, +0x10ebebd1, +0x20d10000, +0x2400031e, +0x1f12ffff, +0x09041001, +0x12460101, +0x31010001, +0x31010001, +0x31010001, +0x24002fc0, +0x810605c0, +0x24000011, +0x810a1801, +0x59021006, +0x10d1d18b, +0x2400040d, +0x040d6666, +0x23024ed1, +0x108b8bd1, +0x240017c0, +0x810605c0, +0x91042580, +0xd708e0ff, +0x810c3c80, +0x20d10000, +0xd118fe02, +0xd105ff00, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x91505880, +0x1f008080, +0x1f00c0c0, +0x1f008181, +0x81505880, +0x2104dd00, +0x91042580, +0xd708e0ff, +0x91042580, +0xcf08e0ff, +0x05014d4d, +0x6f014dfb, +0x91042580, +0xd708e0ff, +0x8106058d, +0x91042580, +0xcf08e0ff, +0x20d10000, +0x117f6666, +0xc9066605, +0x2a000000, +0x24000066, +0x81031866, +0x7f0000da, +0x710f6602, +0x24000f66, +0x590e6604, +0x91aa1800, +0x1f008000, +0x81aa1800, +0x13806666, +0x81031866, +0x20d10000, +0xd105ff00, +0x1f007e7e, +0x810c3c80, +0x24000c10, +0x51004607, +0x10464601, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010101, +0x6f0001fc, +0x20d10000, +0x2405e4e0, +0xf0300000, +0x48100002, +0x10000010, +0x20d10000, +0x2eff838e, +0x24003f00, +0x81401800, +0x8138180e, +0x8110788e, +0x8198388e, +0x2eff8587, +0x209d0000, +0x108d8dab, +0x2eff8000, +0x815a1800, +0x10323201, +0x10121221, +0x81601881, +0xd104c40e, +0x91521801, +0x110b0101, +0x5100980c, +0x913d1880, +0x1f050000, +0x813d1800, +0xc9052002, +0x2400269f, +0x1f050101, +0x81521801, +0x2400060d, +0x040d6666, +0x23024ed1, +0x7900003f, +0x2400010d, +0x000d6666, +0x23024ed1, +0x69fd7309, +0x913d1880, +0x1f040000, +0x813d1800, +0xc9042002, +0x2400269f, +0x1f020101, +0x81521801, +0x79000033, +0x81521801, +0x0908f3e2, +0x10727202, +0x91a45800, +0x0480d281, +0x06c093c1, +0x10e1e1e2, +0xc91fe203, +0x1600e2e2, +0x0101e2e2, +0x913a18c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e204, +0x10222200, +0x10020220, +0x813a1880, +0x914218c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e207, +0x1f010101, +0x91043880, +0x1f018080, +0x81041880, +0xc901c002, +0x2400229f, +0x1d010101, +0x81501801, +0x6900e105, +0x686e5304, +0x813a188d, +0x24000019, +0x79000002, +0x2304c3d1, +0x10535300, +0x10333320, +0x10131340, +0x10727260, +0x10525201, +0x815b5800, +0x24000100, +0x815a1800, +0x815618c4, +0x815818d8, +0x81637894, +0x240000e0, +0x81983880, +0x81a4586e, +0x81701873, +0x10abab8d, +0x240000f8, +0x11cf4444, +0x21018d00, +0x108d8dab, +0x91637881, +0x91541800, +0x915618c0, +0xd105c008, +0x915818c0, +0x5100c007, +0x1f058000, +0x81541800, +0x2400060d, +0x040d6666, +0x23024ed1, +0x79000017, +0x1d058000, +0x81541800, +0x2400010d, +0x000d6666, +0x23024ed1, +0x91541800, +0x69fd6204, +0x1f028000, +0x81541800, +0x79000002, +0x1d028000, +0x15e06262, +0x2ed00381, +0xd1060204, +0xd1050203, +0x1d060000, +0x79000002, +0x1f060000, +0x81541800, +0x81463882, +0x814a3881, +0x2400249f, +0x915a1800, +0x69010004, +0x915b7800, +0x81197800, +0x2400239f, +0x24000300, +0x814e1800, +0x91701800, +0x81361800, +0x91081821, +0x10210001, +0x91503802, +0x1d060202, +0x1d060242, +0x5100010d, +0x91043880, +0x1f068080, +0x81041880, +0xc8c0c002, +0x2400229f, +0x913d1880, +0x1f060000, +0x813d1880, +0xc9062002, +0x2400269f, +0x1f060202, +0x1f060242, +0x81503802, +0x10abab8d, +0x21018f00, +0x91001800, +0xc9070002, +0x21022d00, +0x91351800, +0xc9070002, +0x21022d00, +0x51005c2c, +0x110ff602, +0x49085c02, +0x150f0202, +0x240278e0, +0x0b043c01, +0x14020101, +0x09010181, +0xf0810081, +0x09049c9c, +0x14819c9c, +0x71105c0a, +0xd1025c04, +0x09040200, +0x807c1800, +0x79000005, +0x907c1800, +0x12020000, +0x807c1800, +0x01017c7c, +0x79000013, +0x69045c12, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x51009c09, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x91511800, +0x1d050000, +0x81511800, +0x05045c5c, +0x79000089, +0x0b03f700, +0x111f0000, +0x5110005d, +0xd10ac485, +0xd104005c, +0x1f0ac4c4, +0x111f006b, +0x09046b6b, +0x0902f700, +0x0b1ef620, +0x12200000, +0x110f0000, +0x12006b6b, +0x10f6f6e2, +0x24002c01, +0x31020007, +0x110f0220, +0x0b01e240, +0x11f04040, +0x12402000, +0x2d000001, +0x0b0ae2e2, +0xd1076b1e, +0x24003001, +0xd1066b0e, +0x2400010d, +0x23063cd1, +0x68ab8d45, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900003b, +0x2400020d, +0x23063cd1, +0x688b8d38, +0x8137184b, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900002d, +0x0b026b00, +0x11030000, +0x2400005c, +0x51000003, +0x2400085c, +0x08005c5c, +0x10ebebe0, +0x2ed00180, +0xc9056b05, +0x81281880, +0x8120188b, +0x2400207c, +0x79000010, +0x81281880, +0x51005c04, +0x2400227c, +0x812018c0, +0x7900000b, +0x15ff0b0b, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x1d09c4c4, +0x2400040d, +0x24003001, +0x23063cd1, +0x15ff8d9c, +0x69005c34, +0x51009c33, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x7900002a, +0x1d0ac4c4, +0x111f2300, +0x51150023, +0x691a000a, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x79000011, +0x691f0010, +0x91043880, +0x1f0d8080, +0x81041880, +0xc90dc002, +0x2400229f, +0x913d1880, +0x1f010000, +0x813d1800, +0xc9012002, +0x2400269f, +0x91513800, +0x1f050000, +0x1f054040, +0x81513800, +0x79000005, +0x91513800, +0x1d050000, +0x1d054040, +0x81513800, +0x69001b08, +0xd1073b07, +0x05013b3b, +0x69003b05, +0x2400403b, +0x2400181b, +0xc9027a02, +0x01081b1b, +0x2101e800, +0x24001031, +0x91001800, +0xc9060007, +0x1d060000, +0x81001800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x7900005d, +0x91351800, +0xc9060007, +0x1d060000, +0x81351800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x79000055, +0xc909c41c, +0x05041b1b, +0x490c1b06, +0x0a1b9a31, +0x110f3131, +0x69001b02, +0x1d09c4c4, +0x7900004d, +0xc9077a08, +0x905a1831, +0xc9021b03, +0x0b043131, +0x79000003, +0x110f3131, +0x01015a5a, +0x79000003, +0x0a1bfa31, +0x110f3131, +0x240278e2, +0x0b043a00, +0x14310000, +0x09010080, +0xf0800280, +0x09049a9a, +0x14809a9a, +0x69101b02, +0x15ff1a1a, +0x79000039, +0x91401800, +0x513f0016, +0x913d1840, +0x1d004040, +0x813d1840, +0x91531840, +0x1d004040, +0x81531840, +0x24003f20, +0x81401820, +0x113f007a, +0x2400009a, +0xc9070005, +0x13407a7a, +0x107a7a5a, +0x2400181b, +0x79000004, +0x91371820, +0x1020205a, +0x2400201b, +0x2400403b, +0x1f09c4c4, +0x79000022, +0x912c1800, +0xc9000020, +0x1d000000, +0x812c1800, +0x1f09c4c4, +0x91041880, +0x1d098080, +0x81041880, +0x91511800, +0x1d010000, +0x81511800, +0x91283881, +0x1001017a, +0x2400101b, +0xc9050102, +0x01101b1b, +0x0b031b00, +0x8fc4d801, +0xd1067a0c, +0x0b020101, +0x11030101, +0x51000109, +0x24000821, +0x08012101, +0x00011b1b, +0x10000040, +0x0b030100, +0x9f20d801, +0x01c44040, +0x8e40d801, +0x01101b1b, +0x2400c45a, +0x2400009a, +0x91aa1800, +0xc900000d, +0x91043880, +0x1f0a8080, +0x81041880, +0xc90ac002, +0x2400229f, +0x913d1880, +0x1f030000, +0x813d1800, +0xc9032002, +0x2400269f, +0x1d008080, +0x81aa1800, +0x91031800, +0x590e0007, +0x91505880, +0x1f0a8080, +0x1f0ac0c0, +0x1f0a8181, +0x81505880, +0x79000006, +0x91505880, +0x1d0a8080, +0x1d0ac0c0, +0x1d0a8181, +0x81505880, +0x91501801, +0x91aa1800, +0xc901000a, +0x1d018080, +0x81aa1800, +0x91043880, +0x1f038080, +0x81041880, +0xc903c002, +0x2400229f, +0x1f030101, +0x79000002, +0x1d030101, +0x81501801, +0x2101d500, +0x24000000, +0x814e1800, +0xd103c40a, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x69000d03, +0x24fdfd80, +0x68808427, +0x91381800, +0x01010000, +0x81381800, +0x91411820, +0x60200002, +0x21022d00, +0x109d9d8b, +0x0901c880, +0x090288c0, +0x0903c781, +0x090487c1, +0x00c08080, +0x0081c181, +0x00818080, +0x00898080, +0x0b058080, +0xc90a8002, +0x13f82020, +0x0080c98d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x2304aad1, +0x209d0000, +0x108b8b9d, +0x91aa1800, +0x1f018000, +0x81aa1800, +0x79000010, +0x8138180d, +0x0b05848d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x2304aad1, +0x91983880, +0x008e8080, +0x024ec0c0, +0x81983880, +0x10efefe0, +0x10eeeee1, +0x2ed00380, +0x81107880, +0x24000200, +0x814e1800, +0x2400209f, +0x2400259f, +0x209d0000, +0x24000001, +0xc917ee02, +0x2400ff01, +0x10eeeee0, +0x10010160, +0x00006e6e, +0x0b08e0e0, +0x10010160, +0x02e0efef, +0x91e43881, +0x10e1efef, +0x20d10000, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x20d10000, +0x01011919, +0x91983880, +0x0000526e, +0x0220720f, +0x02c093af, +0x0300536f, +0x6902190b, +0xc90fc907, +0x1600c980, +0x01018080, +0x0b038080, +0x16008080, +0x01018080, +0x79000002, +0x0b038080, +0x00808e8e, +0x03006e6e, +0x20d10000, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x20d10000, +0x2effbd80, +0x24000011, +0x1d007e7e, +0x11fc5e5e, +0x1f13ffff, +0x1d007e7e, +0x1f13ffff, +0x31310002, +0x0100e0e0, +0x1d035e5e, +0x240000e0, +0x81080580, +0x240017c0, +0x810605c0, +0x2eff8383, +0x23026e9d, +0x24000866, +0x2400000c, +0x2400002c, +0x91001800, +0x1d070000, +0x81001800, +0x2eff8000, +0x81351800, +0x91501880, +0x11da8080, +0x13108080, +0x81501880, +0x91521880, +0x11f48080, +0x13108080, +0x81521880, +0x91541880, +0x11748080, +0x13108080, +0x81541880, +0x240128e1, +0x90e13382, +0x1d00e2e2, +0xc901e002, +0x1f01e2e2, +0x80e13382, +0x9101185b, +0x51005b0e, +0x7900000d, +0x2305f9d1, +0x91dc388c, +0x240000e2, +0x91e21882, +0x104c4c0a, +0x100c0c2a, +0x106c6c4a, +0x102c2c6a, +0x2305f9d1, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x2400001e, +0x2400001e, +0x1f12ffff, +0x240000ca, +0x24001f8d, +0x23016a9d, +0x2301f7d1, +0x0101caca, +0x6f02cafc, +0x240000ca, +0x2400198d, +0x23016a9d, +0x2301f7d1, +0x0101caca, +0x6f10cafc, +0x2400017b, +0x24000925, +0x24001a8d, +0x23016a9d, +0xd105ff00, +0x31000002, +0x0100e0e0, +0x1f007e7e, +0x810c3c80, +0x24004805, +0x2eff8592, +0x24005401, +0x2400000b, +0x24000021, +0x24000845, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x69000b0e, +0x51ff000d, +0x240178e2, +0xf0000202, +0x0104e206, +0x61080602, +0x05080606, +0x0d070606, +0x69400504, +0x69064503, +0x71030602, +0x24000006, +0x1e06f6f6, +0x2400010b, +0x05014545, +0xc8068002, +0x1e452121, +0x10000020, +0x69080503, +0x6f0145ea, +0x79000005, +0x6f0045e8, +0x2d802101, +0x05080505, +0x6f0005e3, +0x2406f9e3, +0xc918ff00, +0x101f1f00, +0x05014545, +0xc8060002, +0x1e452121, +0x10000020, +0x2d802101, +0x910c3c99, +0x58e3f92e, +0x04f9e3eb, +0x100b0b19, +0x0b01ebeb, +0x0501ebeb, +0x4f00ebff, +0x1d007e7e, +0x2400031e, +0x1f12ffff, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x24002fc2, +0x810605c2, +0x24000011, +0x31010001, +0x240017c2, +0x810605c2, +0x91042582, +0xd708e2ff, +0x810c3c80, +0xd104ff00, +0xd703ffff, +0x24002c1e, +0xd104ff00, +0xd703ffff, +0x2400b21e, +0x2400cb1e, +0x24000065, +0x69012501, +0x01016565, +0x0901f4f4, +0x0b077300, +0x1200f4f4, +0x0901f3f3, +0x0b077200, +0x12001313, +0x0901f2f2, +0x230605d1, +0x510e6506, +0x6f010df6, +0x10656546, +0x05012525, +0x4f0025a2, +0x79000013, +0x2a000000, +0xd118fe03, +0xd105ff00, +0x2a000000, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x7f000046, +0x24000925, +0xd104ff00, +0xd703ffff, +0x24001b8d, +0x23016a9d, +0x2305cb9d, +0x230605d1, +0x6f010dea, +0x05012525, +0x4f0025f8, +0x24001025, +0x24001c8d, +0x23016a9d, +0x2305cb9d, +0x230605d1, +0x6f010ddf, +0x05012525, +0x4f0025fa, +0x810a1846, +0x24001d8d, +0x23016a9d, +0x2300ef9d, +0x6e0403d8, +0x6e2423d7, +0x110f4300, +0x0b044320, +0x6e2000d4, +0x10848480, +0x10434340, +0x10404001, +0x10202021, +0x10000041, +0x810d3801, +0x2400000d, +0x000d6666, +0x23024ed1, +0x1f08c4c4, +0x110fe05d, +0x01085d5d, +0x0b04e07d, +0x113f7d7d, +0x005d7d7d, +0x050c7d7d, +0x010c7d00, +0x0d280000, +0x24ffffc1, +0x24ffff81, +0x0a00e1e1, +0x81e43881, +0x2301f7d1, +0x21001600, +0x24002005, +0x23025dd1, +0x24000080, +0x2405a4eb, +0x2eff8992, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f4f4, +0x10000020, +0x0b018001, +0x14000130, +0x230269d1, +0x6f0005f6, +0x24001d05, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f3f3, +0x10000020, +0x0b018001, +0x14000130, +0x230269d1, +0x6f0105f6, +0xc918ff00, +0x101f1f00, +0xc8068002, +0x1f00f3f3, +0x0903f3f3, +0x1f18ffff, +0x2406f7e1, +0x910c3c80, +0x58e1e006, +0x04e0e1e0, +0x0101e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x1d007e7e, +0x230216d1, +0x2301f7d1, +0x209d0000, +0x91502181, +0x91502194, +0x56e1f4ff, +0x04e1f4f4, +0x20d10000, +0x240000e0, +0x60cd8d04, +0x04cd8d8d, +0x0101e0e0, +0x7f0000fd, +0x10e0e0cd, +0x20d10000, +0x91acb880, +0x10e2f3eb, +0x240ff8e2, +0x10e2f3e2, +0x0901e2e2, +0x12ebe2eb, +0x68e0f404, +0x68e1eb03, +0x2400010d, +0x20d10000, +0x2400000d, +0x20d10000, +0x13154d4d, +0x104d4d1e, +0x24000800, +0xd104ff00, +0xd703ffff, +0x2400551e, +0x05010000, +0x6f0000fc, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400cfe0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240002c0, +0x810605c0, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400031e, +0x24000ae0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240017c0, +0x810605c0, +0x24001ee0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x810c3c80, +0x20d10000, +0x91043880, +0x1e0d8080, +0x81041880, +0xc80dc002, +0x2400229f, +0x20d10000, +0x240278e2, +0x100d0d40, +0x2400008d, +0x24000080, +0x2c600100, +0x14002d00, +0x09018080, +0xf0800280, +0x09088d8d, +0x148d808d, +0x05014040, +0x4f0040f8, +0x15ff0d0d, +0x20d10000, +0x91003c82, +0x1308e2e2, +0x81003c82, +0x2104dc00 }; diff --git a/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd new file mode 100644 index 0000000..72d4837 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd @@ -0,0 +1,3 @@ +-b +-map=Hiperface_DSL2_2.map +SECTIONS {.text} diff --git a/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h new file mode 100644 index 0000000..39e5a97 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h @@ -0,0 +1,2024 @@ +/* + * hdsl_master_icssg_multichannel_ch0_bin.h + * + * + * Copyright (c) 2015 - 2016, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int Hiperface_DSL2_0_RTU[]= { +0x2107ab00, +0x24000125, +0x2eff818f, +0x24001d8d, +0x23019c9d, +0xd105ff00, +0x91143a8e, +0x1d007e7e, +0x510c4608, +0x240943e1, +0x91143a80, +0x04eee0e0, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x2302d4d1, +0x2302b4d1, +0x05012525, +0x6f0025f0, +0x2eff8f8e, +0x24000725, +0x2eff8f8e, +0x24000725, +0x24041e8d, +0x23019c9d, +0x2301219d, +0x05012525, +0x5100257e, +0x2302b4d1, +0xd70170f8, +0xcf0723f7, +0x1f02c4c4, +0x913d1880, +0x1f000000, +0x813d1800, +0xc9002002, +0x2400269f, +0x91531800, +0x1f000000, +0x81531800, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x240008c5, +0x24001031, +0x240000f8, +0x2400042d, +0xc902c402, +0x1f012d2d, +0x69014503, +0x240004e0, +0x14e0c4c4, +0x11807070, +0x1031310d, +0x51015904, +0x23019c9d, +0x24000159, +0x79000003, +0x2301c49d, +0x10e0e0e0, +0x2301219d, +0xd101700f, +0xc9072306, +0x5101450a, +0x2400040d, +0x040d6666, +0x230319d1, +0x79000009, +0x69014508, +0x2400060d, +0x040d6666, +0x230319d1, +0x79000004, +0x2400010d, +0x000d6666, +0x230319d1, +0x1d03c4c4, +0x2302b4d1, +0x51000c23, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x810c3c80, +0x79000005, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0x2305379d, +0x05014545, +0x51074517, +0x49004502, +0x21008f00, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x7f0000a6, +0x24000070, +0x24000845, +0x1f01c4c4, +0x2400ff1e, +0x7f0000a1, +0xcf01c4ec, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0x7f00009b, +0x2102f800, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230341d1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230341d1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x24000605, +0x2eff8283, +0x230328d1, +0x240000c0, +0x2400002d, +0x23009bd1, +0x100d0d03, +0x0908f3f3, +0x0b18f2e0, +0x12e0f3f3, +0x0908f2f2, +0x1203f2f2, +0x14033838, +0x69014502, +0x15ff3838, +0x240278e0, +0x09013881, +0xf0810080, +0x14182020, +0x10808098, +0x2400012d, +0x24000605, +0x23009bd1, +0x100d0d23, +0x0905f7f7, +0x0b1bf6e0, +0x12e0f7f7, +0x0905f6f6, +0x111f23e0, +0x12e0f6f6, +0x2400022d, +0x24000605, +0x23009bd1, +0x100d0d43, +0x2400032d, +0x24000605, +0x23009bd1, +0x100d0d84, +0x2400042d, +0x24000605, +0x23009bd1, +0x09088484, +0x120d8484, +0x240000c0, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00c0c0, +0xc9007009, +0xd1077008, +0x1f077070, +0xd104c406, +0x1f04c4c4, +0x2400060d, +0x040d6666, +0x230319d1, +0x79000006, +0xc9005005, +0x51fd0304, +0x2400020d, +0x040d6666, +0x230319d1, +0xc9017005, +0x2400010d, +0x040d6666, +0x230319d1, +0x79000005, +0xc9015004, +0x2400020d, +0x040d6666, +0x230319d1, +0xc9027004, +0x2400010d, +0x040d6666, +0x230319d1, +0x111870e0, +0x5100e006, +0x1f03c4c4, +0x2400020d, +0x040d6666, +0x230319d1, +0x79000008, +0xc9035002, +0x69fd2403, +0xc9045005, +0x51fd0404, +0x2400020d, +0x040d6666, +0x230319d1, +0x2400052d, +0x24000605, +0x2300ded1, +0x1d007e7e, +0x240949e1, +0x910c3c80, +0x58e1e005, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x2302d4d1, +0x100d0d63, +0x0908f5f5, +0x0b18f4e0, +0x12e0f5f5, +0x0908f4f4, +0x1263f4f4, +0xc905700e, +0xd105c40d, +0x1f05c4c4, +0x2400080d, +0x040d6666, +0x230319d1, +0x14637878, +0x69014502, +0x15ff7878, +0x240278e0, +0x09017881, +0xf0810080, +0x14582020, +0x108080d8, +0x209d0000, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x51000c12, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x810c3c80, +0x69074502, +0x2400ff1e, +0x000c1111, +0xd107110b, +0x49011103, +0x2400600b, +0x79000013, +0x49031104, +0x2400620b, +0x05021111, +0x7900000f, +0x2400600b, +0x05041111, +0x7900000c, +0x1600110b, +0x01010b0b, +0x49010b03, +0x2400600b, +0x79000007, +0x49030b04, +0x24006d0b, +0x01021111, +0x79000003, +0x24006f0b, +0x01041111, +0x24013081, +0x24ffffc1, +0x808113c1, +0xc901c40c, +0x69084504, +0x2400001e, +0x2400ff1e, +0x21034e00, +0x69074507, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x2103ac00, +0x51000c2d, +0x51015b04, +0x100c0c02, +0x24000022, +0x79000003, +0x102a2a02, +0x100a0a22, +0x91e01800, +0x605b0002, +0x01010202, +0x69002203, +0x05010202, +0x2400ff22, +0x79000001, +0x711a2c02, +0x24001a2c, +0x910c3c81, +0x24010fe0, +0x04e1e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x05010201, +0x2400ff1e, +0x05010101, +0x6f0001fe, +0x24002ce0, +0x1022221e, +0x100b0b79, +0x3103000f, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x7900001e, +0x100b0b79, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x240100eb, +0xf00d0b6d, +0x240178e0, +0xf06d0000, +0x240160eb, +0xf02d0b4d, +0x240178e1, +0xf04d0101, +0x51030008, +0x09010000, +0x0d060000, +0xc9071104, +0x153f6d6d, +0x00001111, +0x79000002, +0x04001111, +0xc9071104, +0x51020103, +0x150f4d4d, +0x79000001, +0x09026d6d, +0x0b024d00, +0x12006d6d, +0x09064d4d, +0xc901c41a, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x2104a800, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x106d6d79, +0x3103000f, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x511f0d03, +0x51190d02, +0x79000003, +0x230757d1, +0x7900001b, +0xd104ff00, +0xd703ffff, +0xd1074d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x810c3c80, +0x511f0d13, +0x51190d12, +0xd1064d04, +0x2400001e, +0x24000026, +0x79000003, +0x2400ff1e, +0x24000126, +0xc901c402, +0x2103ed00, +0x910c3c81, +0x240117e0, +0x04e1e0e0, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x209d0000, +0x10d1d1eb, +0x51002c1d, +0x910c3c80, +0x0da4e0e2, +0x102c2c6d, +0x24000b1e, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x91042581, +0xcf08e1ff, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x24001f8d, +0x2400044d, +0x23030dd1, +0x05016d6d, +0x51006d0c, +0xd104ff00, +0xd703ffff, +0x24000b1e, +0x24000f8d, +0x2400044d, +0x23030dd1, +0x24001f8d, +0x2400034d, +0x23030dd1, +0x05016d6d, +0x6f006df6, +0x10ebebd1, +0x20d10000, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x09041001, +0x12460101, +0x31010001, +0x31010001, +0x31010001, +0x24000011, +0x810a1801, +0x59021006, +0x10d1d18b, +0x2400040d, +0x040d6666, +0x230319d1, +0x108b8bd1, +0x810c3c80, +0x20d10000, +0xd118fe02, +0xd105ff00, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x91505880, +0x1f008080, +0x1f00c0c0, +0x1f008181, +0x81505880, +0x2105b800, +0x91042580, +0xd708e0ff, +0x91042580, +0xcf08e0ff, +0x05014d4d, +0x6f014dfb, +0x91042580, +0xd708e0ff, +0x8106058d, +0x91042580, +0xcf08e0ff, +0x20d10000, +0x117f6666, +0xc9066605, +0x2a000000, +0x24000066, +0x81031866, +0x7f0000da, +0x710f6602, +0x24000f66, +0x590e6604, +0x91aa1800, +0x1f008000, +0x81aa1800, +0x13806666, +0x81031866, +0x20d10000, +0xd105ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x1f007e7e, +0x810c3c80, +0x24000c10, +0x51004607, +0x10464601, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010101, +0x6f0001fc, +0x20d10000, +0x2405e4e0, +0xf0300000, +0x48100002, +0x10000010, +0x20d10000, +0x2eff838e, +0x24003f00, +0x81401800, +0x8138180e, +0x8110788e, +0x8198388e, +0x2eff8587, +0x209d0000, +0x108d8dab, +0x2eff8000, +0x815a1800, +0x10323201, +0x10121221, +0x81601881, +0xd104c40e, +0x91521801, +0x110b0101, +0x5100980c, +0x913d1880, +0x1f050000, +0x813d1800, +0xc9052002, +0x2400269f, +0x1f050101, +0x81521801, +0x2400060d, +0x040d6666, +0x230319d1, +0x79000041, +0x2400010d, +0x000d6666, +0x230319d1, +0x69fd7309, +0x913d1880, +0x1f040000, +0x813d1800, +0xc9042002, +0x2400269f, +0x1f020101, +0x81521801, +0x79000035, +0x81521801, +0x0908f3e2, +0x10727202, +0x91a45800, +0x0480d281, +0x06c093c1, +0x10e1e1e2, +0xc91fe203, +0x1600e2e2, +0x0101e2e2, +0x913a18c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e204, +0x10222200, +0x10020220, +0x813a1880, +0x2400ff1e, +0x2400ff1e, +0x914218c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e207, +0x1f010101, +0x91043880, +0x1f018080, +0x81041880, +0xc901c002, +0x2400229f, +0x1d010101, +0x81501801, +0x6900e105, +0x686e5304, +0x813a188d, +0x24000019, +0x79000002, +0x23059ed1, +0x10535300, +0x10333320, +0x10131340, +0x10727260, +0x10525201, +0x815b5800, +0x24000100, +0x815a1800, +0x815618c4, +0x815818d8, +0x81637894, +0x2400ff1e, +0x240000e0, +0x81983880, +0x81a4586e, +0x81701873, +0x10abab8d, +0x240000f8, +0x11cf4444, +0x2101e500, +0x108d8dab, +0x91637881, +0x91541800, +0x915618c0, +0xd105c008, +0x915818c0, +0x5100c007, +0x1f058000, +0x81541800, +0x2400060d, +0x040d6666, +0x230319d1, +0x79000017, +0x1d058000, +0x81541800, +0x2400010d, +0x000d6666, +0x230319d1, +0x91541800, +0x69fd6204, +0x1f028000, +0x81541800, +0x79000002, +0x1d028000, +0x15e06262, +0x2ed00381, +0xd1060204, +0xd1050203, +0x1d060000, +0x79000002, +0x1f060000, +0x81541800, +0x81463882, +0x814a3881, +0x2400249f, +0x915a1800, +0x69010004, +0x915b7800, +0x81197800, +0x2400239f, +0x24000300, +0x814e1800, +0x91701800, +0x81361800, +0x91081821, +0x10210001, +0x91503802, +0x1d060202, +0x1d060242, +0x5100010d, +0x91043880, +0x1f068080, +0x81041880, +0xc8c0c002, +0x2400229f, +0x913d1880, +0x1f060000, +0x813d1880, +0xc9062002, +0x2400269f, +0x1f060202, +0x1f060242, +0x81503802, +0x10abab8d, +0x2101ec00, +0x91001800, +0xc9070002, +0x2102f800, +0x91351800, +0xc9070002, +0x2102f800, +0x51005c2c, +0x110ff602, +0x49085c02, +0x150f0202, +0x240278e0, +0x0b043c01, +0x14020101, +0x09010181, +0xf0810081, +0x09049c9c, +0x14819c9c, +0x71105c0a, +0xd1025c04, +0x09040200, +0x807c1800, +0x79000005, +0x907c1800, +0x12020000, +0x807c1800, +0x01017c7c, +0x79000013, +0x69045c12, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x51009c09, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x91511800, +0x1d050000, +0x81511800, +0x05045c5c, +0x79000089, +0x0b03f700, +0x111f0000, +0x5110005d, +0xd10ac485, +0xd104005c, +0x1f0ac4c4, +0x111f006b, +0x09046b6b, +0x0902f700, +0x0b1ef620, +0x12200000, +0x110f0000, +0x12006b6b, +0x10f6f6e2, +0x24002c01, +0x31020007, +0x110f0220, +0x0b01e240, +0x11f04040, +0x12402000, +0x2d000001, +0x0b0ae2e2, +0xd1076b1e, +0x24003001, +0xd1066b0e, +0x2400010d, +0x23079dd1, +0x68ab8d45, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900003b, +0x2400020d, +0x23079dd1, +0x688b8d38, +0x8137184b, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900002d, +0x0b026b00, +0x11030000, +0x2400005c, +0x51000003, +0x2400085c, +0x08005c5c, +0x10ebebe0, +0x2ed00180, +0xc9056b05, +0x81281880, +0x8120188b, +0x2400207c, +0x79000010, +0x81281880, +0x51005c04, +0x2400227c, +0x812018c0, +0x7900000b, +0x15ff0b0b, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x1d09c4c4, +0x2400040d, +0x24003001, +0x23079dd1, +0x15ff8d9c, +0x69005c34, +0x51009c33, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x7900002a, +0x1d0ac4c4, +0x111f2300, +0x51150023, +0x691a000a, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x79000011, +0x691f0010, +0x91043880, +0x1f0d8080, +0x81041880, +0xc90dc002, +0x2400229f, +0x913d1880, +0x1f010000, +0x813d1800, +0xc9012002, +0x2400269f, +0x91513800, +0x1f050000, +0x1f054040, +0x81513800, +0x79000005, +0x91513800, +0x1d050000, +0x1d054040, +0x81513800, +0x69001b08, +0xd1073b07, +0x05013b3b, +0x69003b05, +0x2400403b, +0x2400181b, +0xc9027a02, +0x01081b1b, +0x2102aa00, +0x24001031, +0x91001800, +0xc9060007, +0x1d060000, +0x81001800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x7900005d, +0x91351800, +0xc9060007, +0x1d060000, +0x81351800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x79000055, +0xc909c41c, +0x05041b1b, +0x490c1b06, +0x0a1b9a31, +0x110f3131, +0x69001b02, +0x1d09c4c4, +0x7900004d, +0xc9077a08, +0x905a1831, +0xc9021b03, +0x0b043131, +0x79000003, +0x110f3131, +0x01015a5a, +0x79000003, +0x0a1bfa31, +0x110f3131, +0x240278e2, +0x0b043a00, +0x14310000, +0x09010080, +0xf0800280, +0x09049a9a, +0x14809a9a, +0x69101b02, +0x15ff1a1a, +0x79000039, +0x91401800, +0x513f0016, +0x913d1840, +0x1d004040, +0x813d1840, +0x91531840, +0x1d004040, +0x81531840, +0x24003f20, +0x81401820, +0x113f007a, +0x2400009a, +0xc9070005, +0x13407a7a, +0x107a7a5a, +0x2400181b, +0x79000004, +0x91371820, +0x1020205a, +0x2400201b, +0x2400403b, +0x1f09c4c4, +0x79000022, +0x912c1800, +0xc9000020, +0x1d000000, +0x812c1800, +0x1f09c4c4, +0x91041880, +0x1d098080, +0x81041880, +0x91511800, +0x1d010000, +0x81511800, +0x91283881, +0x1001017a, +0x2400101b, +0xc9050102, +0x01101b1b, +0x0b031b00, +0x8fc4d801, +0xd1067a0c, +0x0b020101, +0x11030101, +0x51000109, +0x24000821, +0x08012101, +0x00011b1b, +0x10000040, +0x0b030100, +0x9f20d801, +0x01c44040, +0x8e40d801, +0x01101b1b, +0x2400c45a, +0x2400009a, +0x91aa1800, +0xc900000d, +0x91043880, +0x1f0a8080, +0x81041880, +0xc90ac002, +0x2400229f, +0x913d1880, +0x1f030000, +0x813d1800, +0xc9032002, +0x2400269f, +0x1d008080, +0x81aa1800, +0x91031800, +0x590e0007, +0x91505880, +0x1f0a8080, +0x1f0ac0c0, +0x1f0a8181, +0x81505880, +0x79000006, +0x91505880, +0x1d0a8080, +0x1d0ac0c0, +0x1d0a8181, +0x81505880, +0x91501801, +0x91aa1800, +0xc901000a, +0x1d018080, +0x81aa1800, +0x91043880, +0x1f038080, +0x81041880, +0xc903c002, +0x2400229f, +0x1f030101, +0x79000002, +0x1d030101, +0x81501801, +0x21028400, +0x24000000, +0x814e1800, +0xd103c40a, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x69000d03, +0x24fdfd80, +0x68808427, +0x91381800, +0x01010000, +0x81381800, +0x91411820, +0x60200002, +0x2102f800, +0x109d9d8b, +0x0901c880, +0x090288c0, +0x0903c781, +0x090487c1, +0x00c08080, +0x0081c181, +0x00818080, +0x00898080, +0x0b058080, +0xc90a8002, +0x13f82020, +0x0080c98d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x230585d1, +0x209d0000, +0x108b8b9d, +0x91aa1800, +0x1f018000, +0x81aa1800, +0x79000010, +0x8138180d, +0x0b05848d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x230585d1, +0x91983880, +0x008e8080, +0x024ec0c0, +0x81983880, +0x10efefe0, +0x10eeeee1, +0x2ed00380, +0x81107880, +0x24000200, +0x814e1800, +0x2400209f, +0x2400259f, +0x209d0000, +0x24000001, +0xc917ee02, +0x2400ff01, +0x10eeeee0, +0x10010160, +0x00006e6e, +0x0b08e0e0, +0x10010160, +0x02e0efef, +0x91e43881, +0x10e1efef, +0x20d10000, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x20d10000, +0x01011919, +0x91983880, +0x0000526e, +0x0220720f, +0x02c093af, +0x0300536f, +0x6902190b, +0xc90fc907, +0x1600c980, +0x01018080, +0x0b038080, +0x16008080, +0x01018080, +0x79000002, +0x0b038080, +0x00808e8e, +0x03006e6e, +0x20d10000, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x20d10000, +0x2effbd80, +0x24000011, +0x1d007e7e, +0x11fc5e5e, +0x1f13ffff, +0x1d007e7e, +0x1f13ffff, +0x31310002, +0x0100e0e0, +0x1d035e5e, +0x240000e0, +0x81080580, +0x240003c0, +0x810605c0, +0x2eff8383, +0x2303469d, +0x24000866, +0x2400000c, +0x2400002c, +0x91001800, +0x1d070000, +0x81001800, +0x2eff8000, +0x81351800, +0x91501880, +0x11da8080, +0x13108080, +0x81501880, +0x91521880, +0x11f48080, +0x13108080, +0x81521880, +0x91541880, +0x11748080, +0x13108080, +0x81541880, +0x240128e1, +0x90e13382, +0x1d00e2e2, +0xc901e002, +0x1f01e2e2, +0x80e13382, +0x9101185b, +0x51005b0e, +0x7900000d, +0x23073fd1, +0x91dc388c, +0x240000e2, +0x91e21882, +0x104c4c0a, +0x100c0c2a, +0x106c6c4a, +0x102c2c6a, +0x23073fd1, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x2400001e, +0x2400001e, +0x2400001e, +0x2400001e, +0x1f12ffff, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0x240000ca, +0x24001f8d, +0x23019c9d, +0x2302b4d1, +0x0101caca, +0x6f02cafc, +0x240000ca, +0x2400198d, +0x23019c9d, +0x2302b4d1, +0x0101caca, +0x6f10cafc, +0x2400017b, +0x24000925, +0x24001a8d, +0x23019c9d, +0xd105ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31000002, +0x0100e0e0, +0x1f007e7e, +0x810c3c80, +0x24004805, +0x2eff8592, +0x24005401, +0x2400000b, +0x24000021, +0x24000845, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x69000b0e, +0x51ff000d, +0x240178e2, +0xf0000202, +0x0104e206, +0x61080602, +0x05080606, +0x0d070606, +0x69400504, +0x69064503, +0x71030602, +0x24000006, +0x1e06f6f6, +0x2400010b, +0x05014545, +0xc8068002, +0x1e452121, +0x10000020, +0x69080503, +0x6f0145ea, +0x79000005, +0x6f0045e8, +0x2d802101, +0x05080505, +0x6f0005e3, +0x240947e3, +0xc918ff00, +0x101f1f00, +0x05014545, +0xc8060002, +0x1e452121, +0x10000020, +0x2d802101, +0x910c3c99, +0x58e3f96e, +0x04f9e3eb, +0x100b0b19, +0x0b01ebeb, +0x0501ebeb, +0x4f00ebff, +0x1d007e7e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x24000011, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x91042582, +0xd708e2ff, +0x810c3c80, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0x2400ff1e, +0x24000065, +0x69012501, +0x01016565, +0x0901f4f4, +0x0b077300, +0x1200f4f4, +0x0901f3f3, +0x0b077200, +0x12001313, +0x0901f2f2, +0x23074bd1, +0x510e6506, +0x6f010df6, +0x10656546, +0x05012525, +0x4f002558, +0x7900001c, +0x2a000000, +0xd118fe0c, +0xd105ff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2a000000, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x7d0000d9, +0x24000925, +0x24001b8d, +0x23019c9d, +0x2307119d, +0x23074bd1, +0x6f010dec, +0x05012525, +0x4f0025fa, +0x24001025, +0x24001c8d, +0x23019c9d, +0x2307119d, +0x23074bd1, +0x6f010dd8, +0x05012525, +0x4f0025fa, +0x810a1846, +0x24001d8d, +0x23019c9d, +0x2301219d, +0x6e0403d1, +0x6e2423d0, +0x110f4300, +0x0b044320, +0x6e2000cd, +0x10848480, +0x10434340, +0x10404001, +0x10202021, +0x10000041, +0x810d3801, +0x2400000d, +0x000d6666, +0x230319d1, +0x1f08c4c4, +0x110fe05d, +0x01085d5d, +0x0b04e07d, +0x113f7d7d, +0x005d7d7d, +0x050c7d7d, +0x010c7d00, +0x0d280000, +0x24ffffc1, +0x24ffff81, +0x0a00e1e1, +0x81e43881, +0x2302b4d1, +0x21001600, +0x24002005, +0x230328d1, +0x24000080, +0x2405a4eb, +0x2eff8992, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f4f4, +0x10000020, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f6, +0x24001d05, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f3f3, +0x10000020, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0105f6, +0xc918ff00, +0x101f1f00, +0xc8068002, +0x1f00f3f3, +0x0903f3f3, +0x1f18ffff, +0x240947e1, +0x910c3c80, +0x58e1e006, +0x04e0e1e0, +0x0101e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x1d007e7e, +0x2302d4d1, +0x2302b4d1, +0x209d0000, +0x91502181, +0x91502194, +0x56e1f4ff, +0x04e1f4f4, +0x20d10000, +0x240000e0, +0x60cd8d04, +0x04cd8d8d, +0x0101e0e0, +0x7f0000fd, +0x10e0e0cd, +0x20d10000, +0x91acb880, +0x10e2f3eb, +0x240ff8e2, +0x10e2f3e2, +0x0901e2e2, +0x12ebe2eb, +0x68e0f404, +0x68e1eb03, +0x2400010d, +0x20d10000, +0x2400000d, +0x20d10000, +0x13154d4d, +0x104d4d79, +0x3103000f, +0xd1077905, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x79000004, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x24000800, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0x05010000, +0x6f0000ef, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x240117e0, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400001e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x2400ff1e, +0x240012e0, +0x810c3c80, +0x20d10000, +0x91043880, +0x1e0d8080, +0x81041880, +0xc80dc002, +0x2400229f, +0x20d10000, +0x240278e2, +0x100d0d40, +0x2400008d, +0x24000080, +0x2c600100, +0x14002d00, +0x09018080, +0xf0800280, +0x09088d8d, +0x148d808d, +0x05014040, +0x4f0040f8, +0x15ff0d0d, +0x20d10000, +0x91003c82, +0x1308e2e2, +0x81003c82, +0x2105b700 }; diff --git a/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h new file mode 100644 index 0000000..56cbb62 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h @@ -0,0 +1,2023 @@ +/* + * hdsl_master_icssg_multichannel_ch1_bin.h + * + * + * Copyright (c) 2015 - 2016, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int Hiperface_DSL2_0_PRU[]= { +0x2107aa00, +0x24000125, +0x2eff818f, +0x24001d8d, +0x23019c9d, +0xd10dff00, +0x91143a8e, +0x1d017e7e, +0x510c4608, +0x240943e1, +0x91143a80, +0x04eee0e0, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x2302d4d1, +0x2302b4d1, +0x05012525, +0x6f0025f0, +0x2eff8f8e, +0x24000725, +0x2eff8f8e, +0x24000725, +0x24041e8d, +0x23019c9d, +0x2301219d, +0x05012525, +0x5100257e, +0x2302b4d1, +0xd70170f8, +0xcf0723f7, +0x1f02c4c4, +0x913d1880, +0x1f000000, +0x813d1800, +0xc9002002, +0x2400269f, +0x91531800, +0x1f000000, +0x81531800, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x240008c5, +0x24001031, +0x240000f8, +0x2400042d, +0xc902c402, +0x1f012d2d, +0x69014503, +0x240004e0, +0x14e0c4c4, +0x11807070, +0x1031310d, +0x51015904, +0x23019c9d, +0x24000159, +0x79000003, +0x2301c49d, +0x10e0e0e0, +0x2301219d, +0xd101700f, +0xc9072306, +0x5101450a, +0x2400040d, +0x040d6666, +0x230319d1, +0x79000009, +0x69014508, +0x2400060d, +0x040d6666, +0x230319d1, +0x79000004, +0x2400010d, +0x000d6666, +0x230319d1, +0x1d03c4c4, +0x2302b4d1, +0x51000c23, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x810c3c80, +0x79000005, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0x2305379d, +0x05014545, +0x51074517, +0x49004502, +0x21008f00, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x7f0000a6, +0x24000070, +0x24000845, +0x1f01c4c4, +0x2400ff1e, +0x7f0000a1, +0xcf01c4ec, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0x7f00009b, +0x2102f800, +0x10d1d182, +0x240000cd, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f7, +0x240820eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230341d1, +0x110fcdc0, +0x240868eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x10d1d182, +0x240000cd, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f7, +0x240820eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x230341d1, +0x110fcdc0, +0x240868eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x24000605, +0x2eff8283, +0x230328d1, +0x240000c0, +0x2400002d, +0x23009bd1, +0x100d0d03, +0x0908f3f3, +0x0b18f2e0, +0x12e0f3f3, +0x0908f2f2, +0x1203f2f2, +0x14033838, +0x69014502, +0x15ff3838, +0x240978e0, +0x09013881, +0xf0810080, +0x14182020, +0x10808098, +0x2400012d, +0x24000605, +0x23009bd1, +0x100d0d23, +0x0905f7f7, +0x0b1bf6e0, +0x12e0f7f7, +0x0905f6f6, +0x111f23e0, +0x12e0f6f6, +0x2400022d, +0x24000605, +0x23009bd1, +0x100d0d43, +0x2400032d, +0x24000605, +0x23009bd1, +0x100d0d84, +0x2400042d, +0x24000605, +0x23009bd1, +0x09088484, +0x120d8484, +0x240000c0, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0xc8068002, +0x1f00c0c0, +0xc9007009, +0xd1077008, +0x1f077070, +0xd104c406, +0x1f04c4c4, +0x2400060d, +0x040d6666, +0x230319d1, +0x79000006, +0xc9005005, +0x51fd0304, +0x2400020d, +0x040d6666, +0x230319d1, +0xc9017005, +0x2400010d, +0x040d6666, +0x230319d1, +0x79000005, +0xc9015004, +0x2400020d, +0x040d6666, +0x230319d1, +0xc9027004, +0x2400010d, +0x040d6666, +0x230319d1, +0x111870e0, +0x5100e006, +0x1f03c4c4, +0x2400020d, +0x040d6666, +0x230319d1, +0x79000008, +0xc9035002, +0x69fd2403, +0xc9045005, +0x51fd0404, +0x2400020d, +0x040d6666, +0x230319d1, +0x2400052d, +0x24000605, +0x2300ded1, +0x1d017e7e, +0x240949e1, +0x910c3c80, +0x58e1e005, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x2302d4d1, +0x100d0d63, +0x0908f5f5, +0x0b18f4e0, +0x12e0f5f5, +0x0908f4f4, +0x1263f4f4, +0xc905700e, +0xd105c40d, +0x1f05c4c4, +0x2400080d, +0x040d6666, +0x230319d1, +0x14637878, +0x69014502, +0x15ff7878, +0x240978e0, +0x09017881, +0xf0810080, +0x14582020, +0x108080d8, +0x209d0000, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x51000c12, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x810c3c80, +0x69074502, +0x2400ff1e, +0x000c1111, +0xd107110b, +0x49011103, +0x2400600b, +0x79000013, +0x49031104, +0x2400620b, +0x05021111, +0x7900000f, +0x2400600b, +0x05041111, +0x7900000c, +0x1600110b, +0x01010b0b, +0x49010b03, +0x2400600b, +0x79000007, +0x49030b04, +0x24006d0b, +0x01021111, +0x79000003, +0x24006f0b, +0x01041111, +0x24013081, +0x24ffffc1, +0x808113c1, +0xc901c40c, +0x69084504, +0x2400001e, +0x2400ff1e, +0x21034e00, +0x69074507, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x2400ff1e, +0x2103ac00, +0x51000c2d, +0x51015b04, +0x100c0c02, +0x24000022, +0x79000003, +0x102a2a02, +0x100a0a22, +0x91e01800, +0x605b0002, +0x01010202, +0x69002203, +0x05010202, +0x2400ff22, +0x79000001, +0x711a2c02, +0x24001a2c, +0x910c3c81, +0x24010fe0, +0x04e1e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x05010201, +0x2400ff1e, +0x05010101, +0x6f0001fe, +0x24002ce0, +0x1022221e, +0x100b0b79, +0x3103000f, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x7900001e, +0x100b0b79, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x240800eb, +0xf00d0b6d, +0x240878e0, +0xf06d0000, +0x240860eb, +0xf02d0b4d, +0x240878e1, +0xf04d0101, +0x51030008, +0x09010000, +0x0d060000, +0xc9071104, +0x153f6d6d, +0x00001111, +0x79000002, +0x04001111, +0xc9071104, +0x51020103, +0x150f4d4d, +0x79000001, +0x09026d6d, +0x0b024d00, +0x12006d6d, +0x09064d4d, +0xc901c41a, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x2104a800, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x106d6d79, +0x3103000f, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x511f0d03, +0x51190d02, +0x79000003, +0x230756d1, +0x7900001b, +0xd10cff00, +0xd70bffff, +0xd1074d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x810c3c80, +0x511f0d13, +0x51190d12, +0xd1064d04, +0x2400001e, +0x24000026, +0x79000003, +0x2400ff1e, +0x24000126, +0xc901c402, +0x2103ed00, +0x910c3c81, +0x240117e0, +0x04e1e0e0, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x209d0000, +0x10d1d1eb, +0x51002c1d, +0x910c3c80, +0x0da4e0e2, +0x102c2c6d, +0x24000b1e, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x91042581, +0xcf09e1ff, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x24001f8d, +0x2400044d, +0x23030dd1, +0x05016d6d, +0x51006d0c, +0xd10cff00, +0xd70bffff, +0x24000b1e, +0x24000f8d, +0x2400044d, +0x23030dd1, +0x24001f8d, +0x2400034d, +0x23030dd1, +0x05016d6d, +0x6f006df6, +0x10ebebd1, +0x20d10000, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x09041001, +0x12460101, +0x31010001, +0x31010001, +0x31010001, +0x24000011, +0x810a1801, +0x59021006, +0x10d1d18b, +0x2400040d, +0x040d6666, +0x230319d1, +0x108b8bd1, +0x810c3c80, +0x20d10000, +0xd119fe02, +0xd10dff00, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x91505880, +0x1f008080, +0x1f00c0c0, +0x1f008181, +0x81505880, +0x2105b800, +0x91042580, +0xd709e0ff, +0x91042580, +0xcf09e0ff, +0x05014d4d, +0x6f014dfb, +0x91042580, +0xd709e0ff, +0x8106058d, +0x91042580, +0xcf09e0ff, +0x20d10000, +0x117f6666, +0xc9066605, +0x2a000000, +0x24000066, +0x81031866, +0x7f0000da, +0x710f6602, +0x24000f66, +0x590e6604, +0x91aa1800, +0x1f008000, +0x81aa1800, +0x13806666, +0x81031866, +0x20d10000, +0xd10dff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x1f017e7e, +0x810c3c80, +0x24000c10, +0x51004607, +0x10464601, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010101, +0x6f0001fc, +0x20d10000, +0x240ce4e0, +0xf0300000, +0x48100002, +0x10000010, +0x20d10000, +0x2eff838e, +0x24003f00, +0x81401800, +0x8138180e, +0x8110788e, +0x8198388e, +0x2eff8587, +0x209d0000, +0x108d8dab, +0x2eff8000, +0x815a1800, +0x10323201, +0x10121221, +0x81601881, +0xd104c40e, +0x91521801, +0x110b0101, +0x5100980c, +0x913d1880, +0x1f050000, +0x813d1800, +0xc9052002, +0x2400269f, +0x1f050101, +0x81521801, +0x2400060d, +0x040d6666, +0x230319d1, +0x79000041, +0x2400010d, +0x000d6666, +0x230319d1, +0x69fd7309, +0x913d1880, +0x1f040000, +0x813d1800, +0xc9042002, +0x2400269f, +0x1f020101, +0x81521801, +0x79000035, +0x81521801, +0x0908f3e2, +0x10727202, +0x91a45800, +0x0480d281, +0x06c093c1, +0x10e1e1e2, +0xc91fe203, +0x1600e2e2, +0x0101e2e2, +0x913a18c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e204, +0x10222200, +0x10020220, +0x813a1880, +0x2400ff1e, +0x2400ff1e, +0x914218c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e207, +0x1f010101, +0x91043880, +0x1f018080, +0x81041880, +0xc901c002, +0x2400229f, +0x1d010101, +0x81501801, +0x6900e105, +0x686e5304, +0x813a188d, +0x24000019, +0x79000002, +0x23059ed1, +0x10535300, +0x10333320, +0x10131340, +0x10727260, +0x10525201, +0x815b5800, +0x24000100, +0x815a1800, +0x815618c4, +0x815818d8, +0x81637894, +0x2400ff1e, +0x240000e0, +0x81983880, +0x81a4586e, +0x81701873, +0x10abab8d, +0x240000f8, +0x11cf4444, +0x2101e500, +0x108d8dab, +0x91637881, +0x91541800, +0x915618c0, +0xd105c008, +0x915818c0, +0x5100c007, +0x1f058000, +0x81541800, +0x2400060d, +0x040d6666, +0x230319d1, +0x79000017, +0x1d058000, +0x81541800, +0x2400010d, +0x000d6666, +0x230319d1, +0x91541800, +0x69fd6204, +0x1f028000, +0x81541800, +0x79000002, +0x1d028000, +0x15e06262, +0x2ed00381, +0xd1060204, +0xd1050203, +0x1d060000, +0x79000002, +0x1f060000, +0x81541800, +0x81463882, +0x814a3881, +0x2400249f, +0x915a1800, +0x69010004, +0x915b7800, +0x81197800, +0x2400239f, +0x24000300, +0x814e1800, +0x91701800, +0x81361800, +0x91081821, +0x10210001, +0x91503802, +0x1d060202, +0x1d060242, +0x5100010d, +0x91043880, +0x1f068080, +0x81041880, +0xc8c0c002, +0x2400229f, +0x913d1880, +0x1f060000, +0x813d1880, +0xc9062002, +0x2400269f, +0x1f060202, +0x1f060242, +0x81503802, +0x10abab8d, +0x2101ec00, +0x91001800, +0xc9070002, +0x2102f800, +0x91351800, +0xc9070002, +0x2102f800, +0x51005c2c, +0x110ff602, +0x49085c02, +0x150f0202, +0x240978e0, +0x0b043c01, +0x14020101, +0x09010181, +0xf0810081, +0x09049c9c, +0x14819c9c, +0x71105c0a, +0xd1025c04, +0x09040200, +0x807c1800, +0x79000005, +0x907c1800, +0x12020000, +0x807c1800, +0x01017c7c, +0x79000013, +0x69045c12, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x51009c09, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x91511800, +0x1d050000, +0x81511800, +0x05045c5c, +0x79000089, +0x0b03f700, +0x111f0000, +0x5110005d, +0xd10ac485, +0xd104005c, +0x1f0ac4c4, +0x111f006b, +0x09046b6b, +0x0902f700, +0x0b1ef620, +0x12200000, +0x110f0000, +0x12006b6b, +0x10f6f6e2, +0x24002c01, +0x31020007, +0x110f0220, +0x0b01e240, +0x11f04040, +0x12402000, +0x2d000001, +0x0b0ae2e2, +0xd1076b1e, +0x24003001, +0xd1066b0e, +0x2400010d, +0x23079cd1, +0x68ab8d45, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900003b, +0x2400020d, +0x23079cd1, +0x688b8d38, +0x8137184b, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900002d, +0x0b026b00, +0x11030000, +0x2400005c, +0x51000003, +0x2400085c, +0x08005c5c, +0x10ebebe0, +0x2ed00180, +0xc9056b05, +0x81281880, +0x8120188b, +0x2400207c, +0x79000010, +0x81281880, +0x51005c04, +0x2400227c, +0x812018c0, +0x7900000b, +0x15ff0b0b, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x1d09c4c4, +0x2400040d, +0x24003001, +0x23079cd1, +0x15ff8d9c, +0x69005c34, +0x51009c33, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x7900002a, +0x1d0ac4c4, +0x111f2300, +0x51150023, +0x691a000a, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x79000011, +0x691f0010, +0x91043880, +0x1f0d8080, +0x81041880, +0xc90dc002, +0x2400229f, +0x913d1880, +0x1f010000, +0x813d1800, +0xc9012002, +0x2400269f, +0x91513800, +0x1f050000, +0x1f054040, +0x81513800, +0x79000005, +0x91513800, +0x1d050000, +0x1d054040, +0x81513800, +0x69001b08, +0xd1073b07, +0x05013b3b, +0x69003b05, +0x2400403b, +0x2400181b, +0xc9027a02, +0x01081b1b, +0x2102aa00, +0x24001031, +0x91001800, +0xc9060007, +0x1d060000, +0x81001800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x7900005d, +0x91351800, +0xc9060007, +0x1d060000, +0x81351800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x79000055, +0xc909c41c, +0x05041b1b, +0x490c1b06, +0x0a1b9a31, +0x110f3131, +0x69001b02, +0x1d09c4c4, +0x7900004d, +0xc9077a08, +0x905a1831, +0xc9021b03, +0x0b043131, +0x79000003, +0x110f3131, +0x01015a5a, +0x79000003, +0x0a1bfa31, +0x110f3131, +0x240978e2, +0x0b043a00, +0x14310000, +0x09010080, +0xf0800280, +0x09049a9a, +0x14809a9a, +0x69101b02, +0x15ff1a1a, +0x79000039, +0x91401800, +0x513f0016, +0x913d1840, +0x1d004040, +0x813d1840, +0x91531840, +0x1d004040, +0x81531840, +0x24003f20, +0x81401820, +0x113f007a, +0x2400009a, +0xc9070005, +0x13407a7a, +0x107a7a5a, +0x2400181b, +0x79000004, +0x91371820, +0x1020205a, +0x2400201b, +0x2400403b, +0x1f09c4c4, +0x79000022, +0x912c1800, +0xc9000020, +0x1d000000, +0x812c1800, +0x1f09c4c4, +0x91041880, +0x1d098080, +0x81041880, +0x91511800, +0x1d010000, +0x81511800, +0x91283881, +0x1001017a, +0x2400101b, +0xc9050102, +0x01101b1b, +0x0b031b00, +0x8fc4d801, +0xd1067a0c, +0x0b020101, +0x11030101, +0x51000109, +0x24000821, +0x08012101, +0x00011b1b, +0x10000040, +0x0b030100, +0x9f20d801, +0x01c44040, +0x8e40d801, +0x01101b1b, +0x2400c45a, +0x2400009a, +0x91aa1800, +0xc900000d, +0x91043880, +0x1f0a8080, +0x81041880, +0xc90ac002, +0x2400229f, +0x913d1880, +0x1f030000, +0x813d1800, +0xc9032002, +0x2400269f, +0x1d008080, +0x81aa1800, +0x91031800, +0x590e0007, +0x91505880, +0x1f0a8080, +0x1f0ac0c0, +0x1f0a8181, +0x81505880, +0x79000006, +0x91505880, +0x1d0a8080, +0x1d0ac0c0, +0x1d0a8181, +0x81505880, +0x91501801, +0x91aa1800, +0xc901000a, +0x1d018080, +0x81aa1800, +0x91043880, +0x1f038080, +0x81041880, +0xc903c002, +0x2400229f, +0x1f030101, +0x79000002, +0x1d030101, +0x81501801, +0x21028400, +0x24000000, +0x814e1800, +0xd103c40a, +0x151f8484, +0x240b78e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x69000d03, +0x24fdfd80, +0x68808427, +0x91381800, +0x01010000, +0x81381800, +0x91411820, +0x60200002, +0x2102f800, +0x109d9d8b, +0x0901c880, +0x090288c0, +0x0903c781, +0x090487c1, +0x00c08080, +0x0081c181, +0x00818080, +0x00898080, +0x0b058080, +0xc90a8002, +0x13f82020, +0x0080c98d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x230585d1, +0x209d0000, +0x108b8b9d, +0x91aa1800, +0x1f018000, +0x81aa1800, +0x79000010, +0x8138180d, +0x0b05848d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x230585d1, +0x91983880, +0x008e8080, +0x024ec0c0, +0x81983880, +0x10efefe0, +0x10eeeee1, +0x2ed00380, +0x81107880, +0x24000200, +0x814e1800, +0x2400209f, +0x2400259f, +0x209d0000, +0x24000001, +0xc917ee02, +0x2400ff01, +0x10eeeee0, +0x10010160, +0x00006e6e, +0x0b08e0e0, +0x10010160, +0x02e0efef, +0x91e43881, +0x10e1efef, +0x20d10000, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x20d10000, +0x01011919, +0x91983880, +0x0000526e, +0x0220720f, +0x02c093af, +0x0300536f, +0x6902190b, +0xc90fc907, +0x1600c980, +0x01018080, +0x0b038080, +0x16008080, +0x01018080, +0x79000002, +0x0b038080, +0x00808e8e, +0x03006e6e, +0x20d10000, +0x151f8484, +0x240b78e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x20d10000, +0x2effbd80, +0x24000011, +0x1d017e7e, +0x11fc5e5e, +0x1f005e5e, +0x1f13ffff, +0x1d017e7e, +0x1f13ffff, +0x31310002, +0x0100e0e0, +0x1d035e5e, +0x240000e0, +0x81100580, +0x240003c0, +0x810605c0, +0x2eff8383, +0x2303469d, +0x24000866, +0x2400000c, +0x2400002c, +0x91001800, +0x1d070000, +0x81001800, +0x2eff8000, +0x81351800, +0x91501880, +0x11da8080, +0x13108080, +0x81501880, +0x91521880, +0x11f48080, +0x13108080, +0x81521880, +0x91541880, +0x11748080, +0x13108080, +0x81541880, +0x240128e1, +0x90e13382, +0x1d00e2e2, +0xc901e002, +0x1f01e2e2, +0x80e13382, +0x9101185b, +0x51005b0e, +0x7900000d, +0x23073ed1, +0x91dc388c, +0x240000e2, +0x91e21882, +0x104c4c0a, +0x100c0c2a, +0x106c6c4a, +0x102c2c6a, +0x23073ed1, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x2400001e, +0x2400001e, +0x2400001e, +0x2400001e, +0x1f12ffff, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0x240000ca, +0x24001f8d, +0x23019c9d, +0x2302b4d1, +0x0101caca, +0x6f02cafc, +0x240000ca, +0x2400198d, +0x23019c9d, +0x2302b4d1, +0x0101caca, +0x6f10cafc, +0x2400017b, +0x24000925, +0x24001a8d, +0x23019c9d, +0xd10dff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31000002, +0x0100e0e0, +0x1f017e7e, +0x810c3c80, +0x24004805, +0x2eff8592, +0x24005401, +0x2400000b, +0x24000021, +0x24000845, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x69000b0e, +0x51ff000d, +0x240878e2, +0xf0000202, +0x0104e206, +0x61080602, +0x05080606, +0x0d070606, +0x69400504, +0x69064503, +0x71030602, +0x24000006, +0x1e06f6f6, +0x2400010b, +0x05014545, +0xc8068002, +0x1e452121, +0x10000020, +0x69080503, +0x6f0145ea, +0x79000005, +0x6f0045e8, +0x2d802101, +0x05080505, +0x6f0005e3, +0x240947e3, +0xc919ff00, +0x103f3f00, +0x05014545, +0xc8060002, +0x1e452121, +0x10000020, +0x2d802101, +0x910c3c99, +0x58e3f96e, +0x04f9e3eb, +0x100b0b19, +0x0b01ebeb, +0x0501ebeb, +0x4f00ebff, +0x1d017e7e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x10e0e0e0, +0x2400001e, +0x1f12ffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x24000011, +0x31010001, +0x10e0e0e0, +0x10e0e0e0, +0x10e0e0e0, +0x91042582, +0xd709e2ff, +0x810c3c80, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0x2400ff1e, +0x24000065, +0x69012501, +0x01016565, +0x0901f4f4, +0x0b077300, +0x1200f4f4, +0x0901f3f3, +0x0b077200, +0x12001313, +0x0901f2f2, +0x23074ad1, +0x510e6506, +0x6f010df6, +0x10656546, +0x05012525, +0x4f00255a, +0x7900001c, +0x2a000000, +0xd119fe0c, +0xd10dff00, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x2a000000, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x7d0000da, +0x24000925, +0x24001b8d, +0x23019c9d, +0x2307109d, +0x23074ad1, +0x6f010dec, +0x05012525, +0x4f0025fa, +0x24001025, +0x24001c8d, +0x23019c9d, +0x2307109d, +0x23074ad1, +0x6f010dd8, +0x05012525, +0x4f0025fa, +0x810a1846, +0x24001d8d, +0x23019c9d, +0x2301219d, +0x6e0403d1, +0x6e2423d0, +0x110f4300, +0x0b044320, +0x6e2000cd, +0x10848480, +0x10434340, +0x10404001, +0x10202021, +0x10000041, +0x810d3801, +0x2400000d, +0x000d6666, +0x230319d1, +0x1f08c4c4, +0x110fe05d, +0x01085d5d, +0x0b04e07d, +0x113f7d7d, +0x005d7d7d, +0x050c7d7d, +0x010c7d00, +0x0d280000, +0x24ffffc1, +0x24ffff81, +0x0a00e1e1, +0x81e43881, +0x2302b4d1, +0x21001600, +0x24002005, +0x230328d1, +0x24000080, +0x240ca4eb, +0x2eff8992, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05f4f4, +0x10000020, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0005f6, +0x24001d05, +0xc919ff00, +0x103f3f00, +0x1f19ffff, +0x05010505, +0xc8068002, +0x1e05f3f3, +0x10000020, +0x0b018001, +0x14000130, +0x230341d1, +0x6f0105f6, +0xc919ff00, +0x103f3f00, +0xc8068002, +0x1f00f3f3, +0x0903f3f3, +0x1f19ffff, +0x240947e1, +0x910c3c80, +0x58e1e006, +0x04e0e1e0, +0x0101e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x1d017e7e, +0x2302d4d1, +0x2302b4d1, +0x209d0000, +0x91502181, +0x91502194, +0x56e1f4ff, +0x04e1f4f4, +0x20d10000, +0x240000e0, +0x60cd8d04, +0x04cd8d8d, +0x0101e0e0, +0x7f0000fd, +0x10e0e0cd, +0x20d10000, +0x91acb880, +0x10e2f3eb, +0x240ff8e2, +0x10e2f3e2, +0x0901e2e2, +0x12ebe2eb, +0x68e0f404, +0x68e1eb03, +0x2400010d, +0x20d10000, +0x2400000d, +0x20d10000, +0x13154d4d, +0x104d4d79, +0x3103000f, +0xd1077905, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x79000004, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x09017979, +0xd1077903, +0x2400001e, +0x79000002, +0x2400ff1e, +0x09017979, +0x24000800, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0x05010000, +0x6f0000ef, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x240117e0, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400ff1e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400001e, +0x2400001e, +0xd10cff00, +0xd70bffff, +0x2400ff1e, +0x2400ff1e, +0x240012e0, +0x810c3c80, +0x20d10000, +0x91043880, +0x1e0d8080, +0x81041880, +0xc80dc002, +0x2400229f, +0x20d10000, +0x240978e2, +0x100d0d40, +0x2400008d, +0x24000080, +0x2c600100, +0x14002d00, +0x09018080, +0xf0800280, +0x09088d8d, +0x148d808d, +0x05014040, +0x4f0040f8, +0x15ff0d0d, +0x20d10000, +0x91003c82, +0x1308e2e2, +0x81003c82, +0x2105b700 }; diff --git a/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_sync_bin.h b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_sync_bin.h new file mode 100644 index 0000000..345094c --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_sync_bin.h @@ -0,0 +1,1794 @@ +/* + * hdsl_master_icssg_sync_bin.h + * + * + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int Hiperface_DSL_SYNC2_0[]= { +0x2106c500, +0x24000125, +0x2eff818f, +0x24001d8d, +0x23016a9d, +0xd105ff00, +0x91143a8e, +0x1d007e7e, +0x510c4608, +0x2406f5e1, +0x91143a80, +0x04eee0e0, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x230298d1, +0x23026cd1, +0x05012525, +0x6f0025f0, +0x2eff8f8e, +0x24000725, +0x2eff8f8e, +0x24000725, +0x24041e8d, +0x23016a9d, +0x2300ef9d, +0x05012525, +0x5100254c, +0x23026cd1, +0xd70170f8, +0xcf0723f7, +0x1f02c4c4, +0x913d1880, +0x1f000000, +0x813d1800, +0xc9002002, +0x2400269f, +0x91531800, +0x1f000000, +0x81531800, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x240008c5, +0x24001031, +0x240000f8, +0x2400042d, +0xc902c402, +0x1f012d2d, +0x69014503, +0x240004e0, +0x14e0c4c4, +0x11807070, +0x1031310d, +0x51015904, +0x23016a9d, +0x24000159, +0x79000003, +0x2301709d, +0x10e0e0e0, +0x2300ef9d, +0xd101700f, +0xc9072306, +0x5101450a, +0x2400040d, +0x040d6666, +0x2302d0d1, +0x79000009, +0x69014508, +0x2400060d, +0x040d6666, +0x2302d0d1, +0x79000004, +0x2400010d, +0x000d6666, +0x2302d0d1, +0x1d03c4c4, +0x23026cd1, +0x51000c09, +0xd104ff00, +0xd703ffff, +0x24002f1e, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x810c3c80, +0x79000004, +0xd104ff00, +0xd703ffff, +0x24002f1e, +0x2304de9d, +0x05014545, +0x4f0045d2, +0x24000070, +0x01016565, +0x24000845, +0x1f01c4c4, +0x7f0000cd, +0x2102af00, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x2302ebd1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x2302ebd1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x2302ebd1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x10d1d182, +0x240000cd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x2302ebd1, +0x6f0005f7, +0x240120eb, +0xf0cd0b0d, +0x113ccd20, +0x513c2003, +0x51002002, +0x79000002, +0x1e2d7070, +0x0903cdcd, +0x24000305, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05cdcd, +0x0b018001, +0x14000130, +0x2302ebd1, +0x6f0005f7, +0x24000001, +0x1c2d5050, +0x1178cd00, +0x51780003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x111fcd00, +0x511f0003, +0x51000002, +0x79000002, +0x1e2d7070, +0x0901cdcd, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00cdcd, +0x0b018021, +0x14002130, +0x2302ebd1, +0x110fcdc0, +0x240168eb, +0xf0c00b00, +0x12000d0d, +0x1137cd00, +0x15200000, +0x51370003, +0x51000002, +0x79000003, +0x2400e001, +0x1e2d5050, +0x14010d0d, +0x108282d1, +0x20d10000, +0x24000605, +0x2eff8283, +0x2302dfd1, +0x240000c0, +0x2400002d, +0x230069d1, +0x100d0d03, +0x0908f3f3, +0x0b18f2e0, +0x12e0f3f3, +0x0908f2f2, +0x1203f2f2, +0x14033838, +0x69014502, +0x15ff3838, +0x240278e0, +0x09013881, +0xf0810080, +0x14182020, +0x10808098, +0x2400012d, +0x24000605, +0x230069d1, +0x100d0d23, +0x0905f7f7, +0x0b1bf6e0, +0x12e0f7f7, +0x0905f6f6, +0x111f23e0, +0x12e0f6f6, +0x2400022d, +0x24000605, +0x230069d1, +0x100d0d43, +0x2400032d, +0x24000605, +0x230069d1, +0x100d0d84, +0x2400042d, +0x24000605, +0x230069d1, +0x09088484, +0x120d8484, +0x240000c0, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0xc8068002, +0x1f00c0c0, +0xc9007009, +0xd1077008, +0x1f077070, +0xd104c406, +0x1f04c4c4, +0x2400060d, +0x040d6666, +0x2302d0d1, +0x79000006, +0xc9005005, +0x51fd0304, +0x2400020d, +0x040d6666, +0x2302d0d1, +0xc9017005, +0x2400010d, +0x040d6666, +0x2302d0d1, +0x79000005, +0xc9015004, +0x2400020d, +0x040d6666, +0x2302d0d1, +0xc9027004, +0x2400010d, +0x040d6666, +0x2302d0d1, +0x111870e0, +0x5100e006, +0x1f03c4c4, +0x2400020d, +0x040d6666, +0x2302d0d1, +0x79000008, +0xc9035002, +0x69fd2403, +0xc9045005, +0x51fd0404, +0x2400020d, +0x040d6666, +0x2302d0d1, +0x2400052d, +0x24000605, +0x2300acd1, +0x1d007e7e, +0x2406f9e1, +0x910c3c80, +0x58e1e005, +0x04e0e1e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x230298d1, +0x100d0d63, +0x0908f5f5, +0x0b18f4e0, +0x12e0f5f5, +0x0908f4f4, +0x1263f4f4, +0xc905700e, +0xd105c40d, +0x1f05c4c4, +0x2400080d, +0x040d6666, +0x2302d0d1, +0x14637878, +0x69014502, +0x15ff7878, +0x240278e0, +0x09017881, +0xf0810080, +0x14582020, +0x108080d8, +0x209d0000, +0xd104ff00, +0xd703ffff, +0x24002f1e, +0x51000c03, +0x2400ff1e, +0x810c3c80, +0x000c1111, +0xd107110b, +0x49011103, +0x2400600b, +0x79000013, +0x49031104, +0x2400620b, +0x05021111, +0x7900000f, +0x2400600b, +0x05041111, +0x7900000c, +0x1600110b, +0x01010b0b, +0x49010b03, +0x2400600b, +0x79000007, +0x49030b04, +0x24006d0b, +0x01021111, +0x79000003, +0x24006f0b, +0x01041111, +0x24013081, +0x24ffffc1, +0x808113c1, +0xc901c405, +0x69084502, +0x2102f800, +0x69074502, +0x21035300, +0x51000c49, +0x51015b04, +0x100c0c02, +0x24000022, +0x79000003, +0x102a2a02, +0x100a0a22, +0x91e01800, +0x605b0002, +0x01010202, +0x69002203, +0x05010202, +0x2400ff22, +0x79000001, +0x711a2c02, +0x24001a2c, +0x910c3c81, +0x51015903, +0x2400c1e0, +0x79000002, +0x240108e0, +0x04e1e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240002c0, +0x810605c0, +0x05010201, +0xd104ff00, +0xd703ffff, +0x2400ff1e, +0x05010101, +0x6f0001fc, +0x240021e0, +0xd104ff00, +0xd703ffff, +0x1022221e, +0xd104ff00, +0xd703ffff, +0x100b0b1e, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240017c0, +0x810605c0, +0x69015b1a, +0x91102180, +0x010ce0e0, +0x51ff2216, +0x69fe2203, +0x0503e0e0, +0x79000013, +0x69fc2203, +0x0506e0e0, +0x79000010, +0x69f82203, +0x0509e0e0, +0x7900000d, +0x69f02203, +0x050ce0e0, +0x7900000a, +0x69e02203, +0x050fe0e0, +0x79000007, +0x69c02203, +0x0512e0e0, +0x79000004, +0x69802203, +0x0515e0e0, +0x79000001, +0x81d83880, +0x79000001, +0x79000002, +0x100b0b1e, +0x240100eb, +0xf00d0b6d, +0x240178e0, +0xf06d0000, +0x240160eb, +0xf02d0b4d, +0x240178e1, +0xf04d0101, +0x51030008, +0x09010000, +0x0d060000, +0xc9071104, +0x153f6d6d, +0x00001111, +0x79000002, +0x04001111, +0xc9071104, +0x51020103, +0x150f4d4d, +0x79000001, +0x09026d6d, +0x0b024d00, +0x12006d6d, +0x09064d4d, +0xc901c402, +0x21044f00, +0xd104ff00, +0xd703ffff, +0x106d6d1e, +0x511f0d03, +0x51190d02, +0x79000003, +0x23068cd1, +0x79000071, +0xd104ff00, +0xd703ffff, +0xd1074d03, +0x2400001e, +0x79000002, +0x2400ff1e, +0x810c3c80, +0x69015b53, +0x104c4c0a, +0x100c0c2a, +0x102c2c6a, +0x91d83880, +0x91502181, +0x70e0e110, +0x10e0e0e2, +0x04e0e1e0, +0x242710e2, +0x58e2e01b, +0x7112e002, +0x240012e0, +0x10edede1, +0x10e0e08d, +0x240003cd, +0x230679d1, +0x104d4d00, +0x51008d02, +0x01010000, +0x10e1e1ed, +0x7900001b, +0x10e0e0e2, +0x04e1e0e0, +0x242710e2, +0x58e2e00c, +0x7112e002, +0x240012e0, +0x10edede1, +0x10e0e08d, +0x240003cd, +0x230679d1, +0x104d4d00, +0x51008d02, +0x01010000, +0x10e1e1ed, +0x79000002, +0x24000000, +0x24000801, +0x044a0101, +0x69080102, +0x24000001, +0x106c6c4a, +0x01104a4a, +0x05022a2a, +0x04004a4a, +0x04014a4a, +0x7900000a, +0x24000801, +0x044a0101, +0x69080102, +0x24000001, +0x106c6c4a, +0x01084a4a, +0x05012a2a, +0x00004a4a, +0x04014a4a, +0x71074a06, +0x01012a2a, +0x05084a4a, +0x71074a03, +0x01012a2a, +0x05084a4a, +0x104a4a20, +0x2400000a, +0x51002006, +0x24000740, +0x1e400a0a, +0x05012020, +0x05014040, +0x4f0020fd, +0x102a2a00, +0x51000a02, +0x01010000, +0x91e01820, +0x51002002, +0x01010000, +0x59040003, +0x01062a2a, +0x05016a6a, +0x71090003, +0x05062a2a, +0x01016a6a, +0x511f0d16, +0x51190d15, +0xc901c402, +0x21039400, +0x910c3c81, +0x2400cfe0, +0x04e1e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240002c0, +0x810605c0, +0xd1064d06, +0x2400001e, +0x24000026, +0x24001f02, +0x81000502, +0x79000005, +0x2400ff1e, +0x24000126, +0x24001702, +0x81000502, +0x209d0000, +0x10d1d1eb, +0x51015b03, +0x102c2c6d, +0x79000002, +0x106a6a6d, +0x91e11800, +0x605b0002, +0x01016d6d, +0x05015b5b, +0x69005b02, +0x9101185b, +0x51006d1f, +0x910c3c80, +0x51017b03, +0x0d7ce0e2, +0x79000002, +0x0d64e0e2, +0x10e0e0e0, +0x24000b1e, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x91042581, +0xcf08e1ff, +0x24000bc1, +0x810605c1, +0x2400178d, +0x2400044d, +0x2302c4d1, +0x05016d6d, +0x51006d0c, +0xd104ff00, +0xd703ffff, +0x24000b1e, +0x24000b8d, +0x2400044d, +0x2302c4d1, +0x2400178d, +0x2400034d, +0x2302c4d1, +0x05016d6d, +0x6f006df6, +0x10ebebd1, +0x20d10000, +0x2400031e, +0x1f12ffff, +0x09041001, +0x12460101, +0x31010001, +0x31010001, +0x31010001, +0x24002fc0, +0x810605c0, +0x24000011, +0x810a1801, +0x59021006, +0x10d1d18b, +0x2400040d, +0x040d6666, +0x2302d0d1, +0x108b8bd1, +0x240017c0, +0x810605c0, +0x91042580, +0xd708e0ff, +0x810c3c80, +0x20d10000, +0xd118fe02, +0xd105ff00, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x91505880, +0x1f008080, +0x1f00c0c0, +0x1f008181, +0x81505880, +0x21055f00, +0x91042580, +0xd708e0ff, +0x91042580, +0xcf08e0ff, +0x05014d4d, +0x6f014dfb, +0x91042580, +0xd708e0ff, +0x8106058d, +0x91042580, +0xcf08e0ff, +0x20d10000, +0x117f6666, +0xc9066605, +0x2a000000, +0x24000066, +0x81031866, +0x7f0000da, +0x710f6602, +0x24000f66, +0x590e6604, +0x91aa1800, +0x1f008000, +0x81aa1800, +0x13806666, +0x81031866, +0x20d10000, +0xd105ff00, +0x1f007e7e, +0x810c3c80, +0x24000c10, +0x51004607, +0x10464601, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010101, +0x6f0001fc, +0x20d10000, +0x2405e4e0, +0xf0300000, +0x48100002, +0x10000010, +0x20d10000, +0x2eff838e, +0x24003f00, +0x81401800, +0x8138180e, +0x8110788e, +0x8198388e, +0x2eff8587, +0x209d0000, +0x108d8dab, +0x2eff8000, +0x815a1800, +0x10323201, +0x10121221, +0x81601881, +0xd104c40e, +0x91521801, +0x110b0101, +0x5100980c, +0x913d1880, +0x1f050000, +0x813d1800, +0xc9052002, +0x2400269f, +0x1f050101, +0x81521801, +0x2400060d, +0x040d6666, +0x2302d0d1, +0x7900003f, +0x2400010d, +0x000d6666, +0x2302d0d1, +0x69fd7309, +0x913d1880, +0x1f040000, +0x813d1800, +0xc9042002, +0x2400269f, +0x1f020101, +0x81521801, +0x79000033, +0x81521801, +0x0908f3e2, +0x10727202, +0x91a45800, +0x0480d281, +0x06c093c1, +0x10e1e1e2, +0xc91fe203, +0x1600e2e2, +0x0101e2e2, +0x913a18c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e204, +0x10222200, +0x10020220, +0x813a1880, +0x914218c0, +0x10404000, +0x10606040, +0x10000060, +0x91501801, +0x70c0e207, +0x1f010101, +0x91043880, +0x1f018080, +0x81041880, +0xc901c002, +0x2400229f, +0x1d010101, +0x81501801, +0x6900e105, +0x686e5304, +0x813a188d, +0x24000019, +0x79000002, +0x230545d1, +0x10535300, +0x10333320, +0x10131340, +0x10727260, +0x10525201, +0x815b5800, +0x24000100, +0x815a1800, +0x815618c4, +0x815818d8, +0x81637894, +0x240000e0, +0x81983880, +0x81a4586e, +0x81701873, +0x10abab8d, +0x240000f8, +0x11cf4444, +0x21018d00, +0x108d8dab, +0x91637881, +0x91541800, +0x915618c0, +0xd105c008, +0x915818c0, +0x5100c007, +0x1f058000, +0x81541800, +0x2400060d, +0x040d6666, +0x2302d0d1, +0x79000017, +0x1d058000, +0x81541800, +0x2400010d, +0x000d6666, +0x2302d0d1, +0x91541800, +0x69fd6204, +0x1f028000, +0x81541800, +0x79000002, +0x1d028000, +0x15e06262, +0x2ed00381, +0xd1060204, +0xd1050203, +0x1d060000, +0x79000002, +0x1f060000, +0x81541800, +0x81463882, +0x814a3881, +0x2400249f, +0x915a1800, +0x69010004, +0x915b7800, +0x81197800, +0x2400239f, +0x24000300, +0x814e1800, +0x91701800, +0x81361800, +0x91081821, +0x10210001, +0x91503802, +0x1d060202, +0x1d060242, +0x5100010d, +0x91043880, +0x1f068080, +0x81041880, +0xc8c0c002, +0x2400229f, +0x913d1880, +0x1f060000, +0x813d1880, +0xc9062002, +0x2400269f, +0x1f060202, +0x1f060242, +0x81503802, +0x10abab8d, +0x21018f00, +0x91001800, +0xc9070002, +0x2102af00, +0x91351800, +0xc9070002, +0x2102af00, +0x51005c2c, +0x110ff602, +0x49085c02, +0x150f0202, +0x240278e0, +0x0b043c01, +0x14020101, +0x09010181, +0xf0810081, +0x09049c9c, +0x14819c9c, +0x71105c0a, +0xd1025c04, +0x09040200, +0x807c1800, +0x79000005, +0x907c1800, +0x12020000, +0x807c1800, +0x01017c7c, +0x79000013, +0x69045c12, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x51009c09, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x91511800, +0x1d050000, +0x81511800, +0x05045c5c, +0x79000089, +0x0b03f700, +0x111f0000, +0x5110005d, +0xd10ac485, +0xd104005c, +0x1f0ac4c4, +0x111f006b, +0x09046b6b, +0x0902f700, +0x0b1ef620, +0x12200000, +0x110f0000, +0x12006b6b, +0x10f6f6e2, +0x24002c01, +0x31020007, +0x110f0220, +0x0b01e240, +0x11f04040, +0x12402000, +0x2d000001, +0x0b0ae2e2, +0xd1076b1e, +0x24003001, +0xd1066b0e, +0x2400010d, +0x2306b7d1, +0x68ab8d45, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900003b, +0x2400020d, +0x2306b7d1, +0x688b8d38, +0x8137184b, +0x13803b3b, +0x913d1880, +0x1f008080, +0x813d1800, +0xc9002002, +0x2400229f, +0x91531800, +0x1f000000, +0x81531800, +0x7900002d, +0x0b026b00, +0x11030000, +0x2400005c, +0x51000003, +0x2400085c, +0x08005c5c, +0x10ebebe0, +0x2ed00180, +0xc9056b05, +0x81281880, +0x8120188b, +0x2400207c, +0x79000010, +0x81281880, +0x51005c04, +0x2400227c, +0x812018c0, +0x7900000b, +0x15ff0b0b, +0x91043880, +0x1f098080, +0x81041880, +0xc909c002, +0x2400229f, +0x91511800, +0x1f010000, +0x81511800, +0x1d09c4c4, +0x2400040d, +0x24003001, +0x2306b7d1, +0x15ff8d9c, +0x69005c34, +0x51009c33, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x7900002a, +0x1d0ac4c4, +0x111f2300, +0x51150023, +0x691a000a, +0x91043880, +0x1f0c8080, +0x81041880, +0xc90cc002, +0x2400229f, +0x91511800, +0x1f050000, +0x81511800, +0x79000011, +0x691f0010, +0x91043880, +0x1f0d8080, +0x81041880, +0xc90dc002, +0x2400229f, +0x913d1880, +0x1f010000, +0x813d1800, +0xc9012002, +0x2400269f, +0x91513800, +0x1f050000, +0x1f054040, +0x81513800, +0x79000005, +0x91513800, +0x1d050000, +0x1d054040, +0x81513800, +0x69001b08, +0xd1073b07, +0x05013b3b, +0x69003b05, +0x2400403b, +0x2400181b, +0xc9027a02, +0x01081b1b, +0x21025900, +0x24001031, +0x91001800, +0xc9060007, +0x1d060000, +0x81001800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x7900005d, +0x91351800, +0xc9060007, +0x1d060000, +0x81351800, +0x24001e31, +0x2eff829a, +0x1d09c4c4, +0x79000055, +0xc909c41c, +0x05041b1b, +0x490c1b06, +0x0a1b9a31, +0x110f3131, +0x69001b02, +0x1d09c4c4, +0x7900004d, +0xc9077a08, +0x905a1831, +0xc9021b03, +0x0b043131, +0x79000003, +0x110f3131, +0x01015a5a, +0x79000003, +0x0a1bfa31, +0x110f3131, +0x240278e2, +0x0b043a00, +0x14310000, +0x09010080, +0xf0800280, +0x09049a9a, +0x14809a9a, +0x69101b02, +0x15ff1a1a, +0x79000039, +0x91401800, +0x513f0016, +0x913d1840, +0x1d004040, +0x813d1840, +0x91531840, +0x1d004040, +0x81531840, +0x24003f20, +0x81401820, +0x113f007a, +0x2400009a, +0xc9070005, +0x13407a7a, +0x107a7a5a, +0x2400181b, +0x79000004, +0x91371820, +0x1020205a, +0x2400201b, +0x2400403b, +0x1f09c4c4, +0x79000022, +0x912c1800, +0xc9000020, +0x1d000000, +0x812c1800, +0x1f09c4c4, +0x91041880, +0x1d098080, +0x81041880, +0x91511800, +0x1d010000, +0x81511800, +0x91283881, +0x1001017a, +0x2400101b, +0xc9050102, +0x01101b1b, +0x0b031b00, +0x8fc4d801, +0xd1067a0c, +0x0b020101, +0x11030101, +0x51000109, +0x24000821, +0x08012101, +0x00011b1b, +0x10000040, +0x0b030100, +0x9f20d801, +0x01c44040, +0x8e40d801, +0x01101b1b, +0x2400c45a, +0x2400009a, +0x91aa1800, +0xc900000d, +0x91043880, +0x1f0a8080, +0x81041880, +0xc90ac002, +0x2400229f, +0x913d1880, +0x1f030000, +0x813d1800, +0xc9032002, +0x2400269f, +0x1d008080, +0x81aa1800, +0x91031800, +0x590e0007, +0x91505880, +0x1f0a8080, +0x1f0ac0c0, +0x1f0a8181, +0x81505880, +0x79000006, +0x91505880, +0x1d0a8080, +0x1d0ac0c0, +0x1d0a8181, +0x81505880, +0x91501801, +0x91aa1800, +0xc901000a, +0x1d018080, +0x81aa1800, +0x91043880, +0x1f038080, +0x81041880, +0xc903c002, +0x2400229f, +0x1f030101, +0x79000002, +0x1d030101, +0x81501801, +0x2101f300, +0x24000000, +0x814e1800, +0xd103c40a, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x69000d03, +0x24fdfd80, +0x68808427, +0x91381800, +0x01010000, +0x81381800, +0x91411820, +0x60200002, +0x2102af00, +0x109d9d8b, +0x0901c880, +0x090288c0, +0x0903c781, +0x090487c1, +0x00c08080, +0x0081c181, +0x00818080, +0x00898080, +0x0b058080, +0xc90a8002, +0x13f82020, +0x0080c98d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x23052cd1, +0x209d0000, +0x108b8b9d, +0x91aa1800, +0x1f018000, +0x81aa1800, +0x79000010, +0x8138180d, +0x0b05848d, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x23052cd1, +0x91983880, +0x008e8080, +0x024ec0c0, +0x81983880, +0x10efefe0, +0x10eeeee1, +0x2ed00380, +0x81107880, +0x24000200, +0x814e1800, +0x2400209f, +0x2400259f, +0x209d0000, +0x24000001, +0xc917ee02, +0x2400ff01, +0x10eeeee0, +0x10010160, +0x00006e6e, +0x0b08e0e0, +0x10010160, +0x02e0efef, +0x91e43881, +0x10e1efef, +0x20d10000, +0x14e0e0e0, +0xc90a8d02, +0x24fff8a0, +0x128d8080, +0x00808e8e, +0x02404e4e, +0x10c8c889, +0x108888c8, +0x10c7c788, +0x108787c7, +0x04c98087, +0x108080c9, +0x20d10000, +0x01011919, +0x91983880, +0x0000526e, +0x0220720f, +0x02c093af, +0x0300536f, +0x6902190b, +0xc90fc907, +0x1600c980, +0x01018080, +0x0b038080, +0x16008080, +0x01018080, +0x79000002, +0x0b038080, +0x00808e8e, +0x03006e6e, +0x20d10000, +0x151f8484, +0x240478e2, +0xf0240220, +0x09032020, +0x14042020, +0xf020020d, +0x20d10000, +0x2effbd80, +0x24000011, +0x1d007e7e, +0x11fc5e5e, +0x1f13ffff, +0x1d007e7e, +0x1f13ffff, +0x31310002, +0x0100e0e0, +0x1d035e5e, +0x240000e0, +0x81080580, +0x240017c0, +0x810605c0, +0x2eff8383, +0x2302f09d, +0x24000866, +0x2400000c, +0x2400002c, +0x91001800, +0x1d070000, +0x81001800, +0x2eff8000, +0x81351800, +0x91501880, +0x11da8080, +0x13108080, +0x81501880, +0x91521880, +0x11f48080, +0x13108080, +0x81521880, +0x91541880, +0x11748080, +0x13108080, +0x81541880, +0x240128e1, +0x90e13382, +0x1d00e2e2, +0xc901e002, +0x1f01e2e2, +0x80e13382, +0x9101185b, +0x51005b0d, +0x230674d1, +0x91dc388c, +0x240000e2, +0x91e21882, +0x104c4c0a, +0x100c0c2a, +0x106c6c4a, +0x102c2c6a, +0x230674d1, +0x0b01e2e2, +0x0501e2e2, +0x4f00e2ff, +0x2400001e, +0x2400001e, +0x1f12ffff, +0x240000ca, +0x24001f8d, +0x23016a9d, +0x23026cd1, +0x0101caca, +0x6f02cafc, +0x240000ca, +0x2400198d, +0x23016a9d, +0x23026cd1, +0x0101caca, +0x6f10cafc, +0x2400017b, +0x24000925, +0x24001a8d, +0x23016a9d, +0xd105ff00, +0x31000002, +0x0100e0e0, +0x1f007e7e, +0x810c3c80, +0x24004805, +0x2eff8592, +0x24005401, +0x2400000b, +0x24000021, +0x24000845, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x69000b0e, +0x51ff000d, +0x240178e2, +0xf0000202, +0x0104e206, +0x61080602, +0x05080606, +0x0d070606, +0x69400504, +0x69064503, +0x71030602, +0x24000006, +0x1e06f6f6, +0x2400010b, +0x05014545, +0xc8068002, +0x1e452121, +0x10000020, +0x69080503, +0x6f0145ea, +0x79000005, +0x6f0045e8, +0x2d802101, +0x05080505, +0x6f0005e3, +0x2406f9e3, +0xc918ff00, +0x101f1f00, +0x05014545, +0xc8060002, +0x1e452121, +0x10000020, +0x2d802101, +0x910c3c99, +0x58e3f928, +0x04f9e3eb, +0x100b0b19, +0x0b01ebeb, +0x0501ebeb, +0x4f00ebff, +0x1d007e7e, +0x2400031e, +0x1f12ffff, +0x31010001, +0x31010001, +0x31010001, +0x31010001, +0x24002fc2, +0x810605c2, +0x24000011, +0x31010001, +0x240017c2, +0x810605c2, +0x91042582, +0xd708e2ff, +0x810c3c80, +0x24000065, +0x69012501, +0x01016565, +0x0901f4f4, +0x0b077300, +0x1200f4f4, +0x0901f3f3, +0x0b077200, +0x12001313, +0x0901f2f2, +0x230680d1, +0x510e6507, +0x6f010df6, +0x10656546, +0x23026cd1, +0x05012525, +0x4f0025a8, +0x79000013, +0x2a000000, +0xd118fe03, +0xd105ff00, +0x2a000000, +0x91a91800, +0x01010000, +0x81a91800, +0x91043880, +0x1f008080, +0x81041880, +0xc900c002, +0x2400229f, +0x913d1880, +0x1f020000, +0x813d1800, +0xc9022002, +0x2400269f, +0x7f00004d, +0x24000925, +0xd104ff00, +0xd703ffff, +0x24001b8d, +0x23016a9d, +0x2306469d, +0x230680d1, +0x6f010dea, +0x05012525, +0x4f0025f8, +0x24001025, +0x24001c8d, +0x23016a9d, +0x2306469d, +0x230680d1, +0x6f010ddf, +0x05012525, +0x4f0025fa, +0x810a1846, +0x24001d8d, +0x23016a9d, +0x2300ef9d, +0x6e0403d8, +0x6e2423d7, +0x110f4300, +0x0b044320, +0x6e2000d4, +0x10848480, +0x10434340, +0x10404001, +0x10202021, +0x10000041, +0x810d3801, +0x2400000d, +0x000d6666, +0x2302d0d1, +0x1f08c4c4, +0x110fe05d, +0x01085d5d, +0x0b04e07d, +0x113f7d7d, +0x005d7d7d, +0x050c7d7d, +0x010c7d00, +0x0d280000, +0x24ffffc1, +0x24ffff81, +0x0a00e1e1, +0x81e43881, +0x23026cd1, +0x21001600, +0x24002005, +0x2302dfd1, +0x24000080, +0x2405a4eb, +0x2eff8992, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f4f4, +0x10000020, +0x0b018001, +0x14000130, +0x2302ebd1, +0x6f0005f6, +0x24001d05, +0xc918ff00, +0x101f1f00, +0x1f18ffff, +0x05010505, +0xc8068002, +0x1e05f3f3, +0x10000020, +0x0b018001, +0x14000130, +0x2302ebd1, +0x6f0105f6, +0xc918ff00, +0x101f1f00, +0xc8068002, +0x1f00f3f3, +0x0903f3f3, +0x1f18ffff, +0x2406f7e1, +0x910c3c80, +0x58e1e006, +0x04e0e1e0, +0x0101e0e0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x1d007e7e, +0x230298d1, +0x23026cd1, +0x209d0000, +0x91502181, +0x91502194, +0x56e1f4ff, +0x04e1f4f4, +0x20d10000, +0x240000e0, +0x60cd8d04, +0x04cd8d8d, +0x0101e0e0, +0x7f0000fd, +0x10e0e0cd, +0x20d10000, +0x91acb880, +0x10e2f3eb, +0x240ff8e2, +0x10e2f3e2, +0x0901e2e2, +0x12ebe2eb, +0x68e0f404, +0x68e1eb03, +0x2400010d, +0x20d10000, +0x2400000d, +0x20d10000, +0x13154d4d, +0x104d4d1e, +0x24000800, +0xd104ff00, +0xd703ffff, +0x2400551e, +0x05010000, +0x6f0000fc, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400cfe0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240002c0, +0x810605c0, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400001e, +0x2400ff1e, +0xd104ff00, +0xd703ffff, +0x2400031e, +0x24000ae0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x240017c0, +0x810605c0, +0x24001ee0, +0x0b01e0e0, +0x0501e0e0, +0x4f00e0ff, +0x810c3c80, +0x20d10000, +0x91043880, +0x1e0d8080, +0x81041880, +0xc80dc002, +0x2400229f, +0x20d10000, +0x240278e2, +0x100d0d40, +0x2400008d, +0x24000080, +0x2c600100, +0x14002d00, +0x09018080, +0xf0800280, +0x09088d8d, +0x148d808d, +0x05014040, +0x4f0040f8, +0x15ff0d0d, +0x20d10000, +0x91003c82, +0x1308e2e2, +0x81003c82, +0x21055e00 }; diff --git a/source/motor_control/position_sense/hdsl/firmware/macros.inc b/source/motor_control/position_sense/hdsl/firmware/macros.inc new file mode 100644 index 0000000..68a3560 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/macros.inc @@ -0,0 +1,448 @@ + +; Copyright (C) 2021-2023 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + +CALL .macro func + jal RET_ADDR0, func + .endm + +RET .macro + JMP RET_ADDR0 + .endm + +CALL1 .macro func + jal RET_ADDR1, func + .endm + +RET1 .macro + JMP RET_ADDR1 + .endm + +QM_ADD .macro val + ldi REG_FNC.b0, (val & 0xff) + add QM, QM, REG_FNC.b0 + CALL1 qm_add + .endm + +QM_SUB .macro val + ldi REG_FNC.b0, (val & 0xff) + sub QM, QM, REG_FNC.b0 + CALL1 qm_add + .endm + +FIND_EDGE .macro src, tmp + LOOKUP_BITCNT tmp, src + add SAMPLE_EDGE, tmp, 4 + WRAP_AROUND SAMPLE_EDGE, 8 + .endm + +WRAP_AROUND .macro reg, threshold + qbgt l?, reg, threshold + sub reg, reg, threshold;threshold/2 + ;ldi reg, (threshold-1) +l?: + .endm + +LOOKUP_BITCNT .macro dst, src + ldi dst, (PDMEM00+LUT_BITCNT) + lbbo &dst, dst, src, 1 + .endm + +SAMPLE .macro dst, src + ldi dst, (PDMEM00+LUT_BITCNT) + lbbo &dst, dst, src, 1 + qblt l?, dst, 4 + ldi dst, 0 + jmp end? +l?: + ldi dst, 1 +end?: + .endm + +WAIT .macro delay + lsr delay, delay, 1 +l?: sub delay,delay,1 + qblt l?,delay,0 + .endm + +WAIT_X24 .macro reg, offset + lsl reg, reg, 3 + sub reg, reg, offset +l?: + and r0, r0, r0 + sub reg, reg, 1 + qblt l?, reg, 0 + .endm + +WAIT_BITS .macro bits, reg + ldi32 reg, (CYCLES_BIT/2*bits-1) +l?: + sub reg, reg, 1 + qblt l?, reg, 0 + .endm + +TX_EN .macro + .if $defined(CHANNEL_2) + clr r30.b3, r30.b3, 2 + .endif + .if $defined(CHANNEL_1) + clr r30.b3, r30.b3, 1 + .endif + .if $defined(CHANNEL_0) + clr r30.b3, r30.b3, 0 + .endif + .endm + +;4 cycles +;tx delay is always 0 +TX_FRAME_SIZE .macro bits, tmp0 + ldi tmp0, (bits<<11) + .if $defined(CHANNEL_2) + ;ldi REG_SCRATCH, P0EDCH2CFG0 + sbco &tmp0, ICSS_CFGx, EDCH2CFG0, 2 + .endif + .if $defined(CHANNEL_1) + ;ldi REG_SCRATCH, P0EDCH1CFG0 + sbco &tmp0, ICSS_CFGx, EDCH1CFG0, 2 + .endif + .if $defined(CHANNEL_0) + ;ldi REG_SCRATCH, P0EDCH0CFG0 + sbco &tmp0, ICSS_CFGx, EDCH0CFG0, 2 + .endif + .endm + +;4 cycles +TX_CLK_DIV .macro div, tmp0 + ldi tmp0.w2, div + ;ldi REG_SCRATCH, P0EDTXCFG+2 + sbco &tmp0.w2, ICSS_CFGx, EDTXCFG+2, 2 + .endm + +TX_CLK_DIV_WAIT .macro div,tmp0 + nop + nop + nop + .endm + +WAIT_TX_DONE .macro + ;WAIT_TX_FIFO_CLEAR +l?: + qbbs l?, r31, TX_GLOBAL_REINIT_ACTIVE + .endm + +;WAIT_TX_FIFO_CLEAR .macro +;l?: +; qbbs l?, r31, TX_GLOBAL_TX_GO +; qbbs l?, r31, TX_GLOBAL_REINIT +; qbbs l?, r31, TX_CHANNEL_GO +; .endm + +WAIT_TX_FIFO_FREE .macro +l?: + .if $defined(CHANNEL_2) + qbbs l?, r31, TX_GLOBAL_TX_GO + qbbs l?, r31, TX_GLOBAL_REINIT + .endif + .if $defined(CHANNEL_1) + qbbs l?, r31, 12 + qbbs l?, r31, 11 + .endif + .if $defined(CHANNEL_0) + qbbs l?, r31, 4 ;fill level 4 + qbbs l?, r31, 3 ;fill level 2 + .endif + .endm + +SET_TX_CH0 .macro + and r30.b2, r30.b2, 0xfc ;clear the channel select bits + .if !$defined(CHANNEL_0) + set r30.b2, r30.b2, CHANNEL_NUM + .endif + .endm + +CLKMODE .macro + clr r30.b2, r30.b2, 3 + ;set r30.b2, r30.b2, 4 + ;ldi r30.b2, 0x00 + ;ldi r30.b2, 0x08 + ;ldi r30.b2, 0x10 + ;ldi r30.b2, 0x18 + .endm + +REINIT_TX .macro + set r31, r31, TX_GLOBAL_REINIT + TX_EN + set r31, r31, TX_GLOBAL_REINIT +l?: + ;qbbs l?, r31, 21 + loop loop1?, 50 + add R0, R0, 0 +loop1?: + + CLKMODE + .endm + +REINIT_TX_CNT .macro reg + ldi reg, 6 + set r31, r31, TX_GLOBAL_REINIT + TX_EN + set r31, r31, TX_GLOBAL_REINIT +l?: + add reg, reg, 2 + qbbs l?, r31, TX_GLOBAL_REINIT_ACTIVE + CLKMODE + .endm + +TX_CHANNEL .macro + set r31, r31, TX_CHANNEL_GO + .endm + +PUSH_FIFO_CONST .macro dat + ldi r30.b0, dat + .endm + +PUSH_FIFO .macro dat + mov r30.b0, dat + .endm + .if $defined(HDSL_MULTICHANNEL) +PUSH_FIFO_8x .macro dat + ;sbco &dat,MASTER_REGS_CONST,0x90,1 + ; mov dat,dat + loop L1?, 4 + qbbs L2_0?, dat, 7 ; check bit 0 + WAIT_TX_FIFO_FREE + ldi r30.b0, 0x0 ; Push oversampled 0s on the wire + qba L3_0? +L2_0?: + WAIT_TX_FIFO_FREE + ldi r30.b0, 0xff ; Push oversampled 1s on the wire +L3_0?: + lsl dat,dat, 1 ; Drop least significant bit + + qbbs L2_1?, dat, 7 ; check bit 0 + ldi r30.b0, 0x0 ; Push oversampled 0s on the wire + qba L3_1? +L2_1?: + ldi r30.b0, 0xff ; Push oversampled 1s on the wire +L3_1?: + lsl dat,dat, 1 ; Drop least significant bit + + +L1?: + .endm + + +PUSH_FIFO_2B_8x .macro + ;mov FIFO_L,dat + qbbs L2_0?, FIFO_L, 7 ; check bit 0 + WAIT_TX_FIFO_FREE + ldi r30.b0, 0x0 ; Push oversampled 0s on the wire + qba L3_0? +L2_0?: + WAIT_TX_FIFO_FREE + ldi r30.b0, 0xff ; Push oversampled 1s on the wire +L3_0?: + lsl FIFO_L,FIFO_L, 1 ; Drop least significant bit + + qbbs L2_1?, FIFO_L, 7 ; check bit 0 + ldi r30.b0, 0x0 ; Push oversampled 0s on the wire + qba L3_1? +L2_1?: + ldi r30.b0, 0xff ; Push oversampled 1s on the wire +L3_1?: + lsl FIFO_L,FIFO_L, 1 ; Drop least significant bit + + .endm + + +PUSH_FIFO_1_8x .macro + ;mov FIFO_L,dat + qbbs L2_0?, FIFO_L, 7 ; check bit 0 + + ldi r30.b0, 0x0 ; Push oversampled 0s on the wire + qba L3_0? +L2_0?: + + ldi r30.b0, 0xff ; Push oversampled 1s on the wire +L3_0?: + lsl FIFO_L,FIFO_L, 1 ; Drop least significant bit + + qbbs L2_1?, FIFO_L, 7 ; check bit 0 + WAIT_TX_FIFO_FREE + ldi r30.b0, 0x0 ; Push oversampled 0s on the wire + qba L3_1? +L2_1?: + WAIT_TX_FIFO_FREE + ldi r30.b0, 0xff ; Push oversampled 1s on the wire + +L3_1?: + lsl FIFO_L,FIFO_L, 1 ; Drop least significant bit + + .endm + +PUSH_FIFO_2_8x .macro + ; mov FIFO_L,dat + qbbs L2_0?, FIFO_L, 7 ; check bit 0 + + ldi r30.b0, 0x0 ; Push oversampled 0s on the wire + qba L3_0? +L2_0?: + + ldi r30.b0, 0xff ; Push oversampled 1s on the wire +L3_0?: + lsl FIFO_L,FIFO_L, 1 ; Drop least significant bit + + qbbs L2_1?, FIFO_L, 7 ; check bit 0 + + ldi r30.b0, 0x0 ; Push oversampled 0s on the wire + qba L3_1? +L2_1?: + + ldi r30.b0, 0xff ; Push oversampled 1s on the wire + +L3_1?: + lsl FIFO_L,FIFO_L, 1 ; Drop least significant bit + + .endm + + .endif + +POP_FIFO .macro dst + .if $defined(CHANNEL_2) + mov dst, r31.b2 + .endif + .if $defined(CHANNEL_1) + mov dst, r31.b1 + .endif + .if $defined(CHANNEL_0) + mov dst, r31.b0 + + .if $defined(EXT_SYNC_ENABLE_DEBUG) + lbco ®_TMP2, c25, 0, 4 + add REG_TMP2,REG_TMP2,4 + sbco &dst, c25, REG_TMP2, 1 + sbco ®_TMP2, c25, 0, 4 + .endif + + .endif + .endm + +RX_EN .macro + .if $defined(CHANNEL_2) + set r30.b3, r30.b3, 2 + .endif + .if $defined(CHANNEL_1) + set r30.b3, r30.b3, 1 + .endif + .if $defined(CHANNEL_0) + set r30.b3, r30.b3, 0 + .endif + .endm + +REINIT_RX .macro + set r31, r31, TX_GLOBAL_REINIT +l?: + qbbs l?, r31, TX_GLOBAL_REINIT_ACTIVE + RX_EN + CLKMODE + .endm + +CLEAR_VAL .macro + set r31, r31, RX_VALID_FLAG + .endm + +CLEAR_OVF .macro + set r31, r31, RX_OVERFLOW_FLAG + .endm + +;CLEAR_VAL_OVF .macro + ;ldi r31.b3, 0x24 + ;.endm + + +RESET_CYCLCNT .macro + sbco &r0, PRU_CTRL_CONST, PRU_CYCLCNT, 4 + .endm + +READ_CYCLCNT .macro dst + lbco &dst, PRU_CTRL_CONST, PRU_CYCLCNT, 4 + .endm + +READ_IEPCNT .macro dst + lbco &dst, IEP_CONST, IEP_CNT, 4 + .endm + +WAIT_CLK_HIGH .macro tmp +l?: + ;ldi REG_SCRATCH, P0EDTXCFG + lbco &tmp, ICSS_CFGx, EDTXCFG, 4 + ;//here 8 for endat0, 9 for endat1 and 10 for endat2 + .if $defined(CHANNEL_2) + qbbc l?, tmp, 10 + .endif + .if $defined(CHANNEL_1) + qbbc l?, tmp, 9 + .endif + .if $defined(CHANNEL_0) + qbbc l?, tmp, 8 + .endif + .endm + +WAIT_CLK_LOW .macro tmp +l?: + ;ldi REG_SCRATCH, P0EDTXCFG + lbco &tmp, ICSS_CFGx, EDTXCFG, 4 + ;//here 8 for endat0, 9 for endat1 and 10 for endat2 + .if $defined(CHANNEL_2) + qbbs l?, tmp, 10 + .endif + .if $defined(CHANNEL_1) + qbbs l?, tmp, 9 + .endif + .if $defined(CHANNEL_0) + qbbs l?, tmp, 8 + .endif + .endm + +RESET_ECAP_INT .macro tmp0, tmp1 + ldi tmp0, (ECAP+ECAP_ECCLR) + ldi tmp1, 0xffff + sbco &tmp1, PWMSS1_CONST, tmp0, 2 + .endm + +NOP .macro + and r0, r0, r0 + .endm + +NOP_2 .macro + loop l?, 2 +l?: + .endm diff --git a/source/motor_control/position_sense/hdsl/firmware/main.asm b/source/motor_control/position_sense/hdsl/firmware/main.asm new file mode 100644 index 0000000..518bd9d --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/main.asm @@ -0,0 +1,53 @@ + +; Copyright (C) 2021-2023 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + + .include "memory.inc" + .include "defines.inc" + .include "macros.inc" + + .retain ; Required for building .out with assembly file + .retainrefs ; Required for building .out with assembly file + .ref datalink_init + .ref transport_init + .ref load_code + .ref datalink_init_start + .global main + .sect ".text" + +main: +;init code +;enable cyclecount + lbco ®_TMP2, PRU_CTRL_CONST, 0x00, 4 + or REG_TMP2, REG_TMP2, (1<<3) + sbco ®_TMP2, PRU_CTRL_CONST, 0x00, 4 + ;skip code loading since there is no edma overlay in ICSSG + jmp datalink_init_start diff --git a/source/motor_control/position_sense/hdsl/firmware/memory.inc b/source/motor_control/position_sense/hdsl/firmware/memory.inc new file mode 100644 index 0000000..230217c --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/memory.inc @@ -0,0 +1,509 @@ + +; Copyright (C) 2021-2023 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + +;-------------------------------------------------------------------------------------------------- +;Offsets +;-------------------------------------------------------------------------------------------------- +;ICSS_CFG .set C4 +;SYSCFG .set 0x04 +;GPCFG0 .set 0x08 +;GPCFG1 .set 0x0c +;PMAO .set 0x28 +P0EDRXCFG .set 0xe0 +P0EDTXCFG .set 0xe4 +P0EDCH0CFG0 .set 0xe8 +P0EDCH0CFG1 .set 0xec +P0EDCH1CFG0 .set 0xf0 +P0EDCH1CFG1 .set 0xf4 +P0EDCH2CFG0 .set 0xf8 +P0EDCH2CFG1 .set 0xfc + +P1EDRXCFG .set 0x100 +P1EDTXCFG .set 0x104 +P1EDCH0CFG0 .set 0x108 +P1EDCH0CFG1 .set 0x10C +P1EDCH1CFG0 .set 0x110 +P1EDCH1CFG1 .set 0x114 +P1EDCH2CFG0 .set 0x118 +P1EDCH2CFG1 .set 0x11C + +;-------------------------------------------------------------------------------------------------- +;ICSS0 PRU0 DMEM +;-------------------------------------------------------------------------------------------------- + .if $defined(PRU1) +ICSS_CFGx .set C5 +EDTXCFG .set (P1EDTXCFG-0x100) +EDRXCFG .set (P1EDRXCFG-0x100) +EDCH0CFG0 .set (P1EDCH0CFG0-0x100) +EDCH0CFG1 .set (P1EDCH0CFG1-0x100) +EDCH1CFG0 .set (P1EDCH1CFG0-0x100) +EDCH1CFG1 .set (P1EDCH1CFG1-0x100) +EDCH2CFG0 .set (P1EDCH2CFG0-0x100) +EDCH2CFG1 .set (P1EDCH2CFG1-0x100) + .else +ICSS_CFGx .set C4 +EDTXCFG .set P0EDTXCFG +EDRXCFG .set P0EDRXCFG +EDCH0CFG0 .set P0EDCH0CFG0 +EDCH0CFG1 .set P0EDCH0CFG1 +EDCH1CFG0 .set P0EDCH1CFG0 +EDCH1CFG1 .set P0EDCH1CFG1 +EDCH2CFG0 .set P0EDCH2CFG0 +EDCH2CFG1 .set P0EDCH2CFG1 + .endif + +; Each HDSL channel will use a portion of DMEM for HDSL shared/local data storage for that channel. +; CHANNEL_0: 0x0000 - 0x06FF +; CHANNEL_1: 0x0700 - 0x0DFF +; CHANNEL_2: 0x0E00 - 0x0~FF + + .if $defined(CHANNEL_2) ; TX_PRU +PDMEM00 .set 0x0E00 + .endif + .if $defined(CHANNEL_1) ; PRU +PDMEM00 .set 0x0700 + .endif + .if $defined(CHANNEL_0) ; RTU_PRU +PDMEM00 .set 0x0000 + .endif + +PDMEM00_CONST .set C24 +MASTER_REGS_CONST .set C24 +IEP1_BASE_CONST .set C1 +;Hiperface DSL Master Registers +MASTER_REGS .set 0x00 +MASTER_REGS_SIZE .set (DUMMY_END + 1) +;LUT for 5b/6b encoding +LUT_5b6b_ENC .set (MASTER_REGS + MASTER_REGS_SIZE) +LUT_5b6b_ENC_SIZE .set 32 +;LUT for 5b/6b decoding +LUT_5b6b_DEC .set (LUT_5b6b_ENC + LUT_5b6b_ENC_SIZE) +LUT_5b6b_DEC_SIZE .set 64 +;LUT for 3b/4b encoding +LUT_3b4b_ENC .set (LUT_5b6b_DEC + LUT_5b6b_DEC_SIZE) +LUT_3b4b_ENC_SIZE .set 8 +;LUT for 3b/4b decoding +LUT_3b4b_DEC .set (LUT_3b4b_ENC + LUT_3b4b_ENC_SIZE) +LUT_3b4b_DEC_SIZE .set 16 +LUT_BITCNT .set (LUT_3b4b_DEC + LUT_3b4b_DEC_SIZE) +LUT_BITCNT_SIZE .set 256 +LUT_CRC16 .set (LUT_BITCNT + LUT_BITCNT_SIZE) +LUT_CRC16_SIZE .set (256*2) +LUT_CRC5 .set (LUT_CRC16 + LUT_CRC16_SIZE) +LUT_CRC5_SIZE .set (1*256) +ABS_ERR_PTR .set (LUT_CRC5 + LUT_CRC5_SIZE) +ABS_ERR_PTR_SIZE .set 2 +ABS_ERR_BUF .set (ABS_ERR_PTR + ABS_ERR_PTR_SIZE) +ABS_ERR_BUF_SIZE .set (NUM_FRAMES_AVG*4) +LUT_B2B .set (ABS_ERR_BUF + 2 + ABS_ERR_BUF_SIZE) ;+2 is for 4-byte address alignment +LUT_B2B_SIZE .set (4*16) +LUT_RSSI .set (LUT_B2B + LUT_B2B_SIZE) +LUT_RSSI_SIZE .set (256) +LUT_EE .set (0x5e4 + LUT_RSSI_SIZE);(LUT_RSSI + LUT_RSSI_SIZE) +LUT_EE_SIZE .set 9 + +;-------------------------------------------------------------------------------------------------- +;Register Usage +;-------------------------------------------------------------------------------------------------- +;channel structure +channel_s .struct +ch_vertl .int +ch_verth .int +ch_secl .int +ch_sech .int +ch_paral .int +ch_parah .int + .endstruct +CHANNEL .sassign r18, channel_s + .asg r18.w0, crc_vert + .asg r18, VERT_L + .asg r19, VERT_H +; R18, R19, R20, R21, R22 and R23 are used for channel_s + +h_frame_s .struct +vert .byte +s_par .byte +pipe .byte +secondary .byte +acc .short +flags .short + .endstruct +H_FRAME .sassign r3, h_frame_s + .asg r4.b0, H_FRAME_acc0 + .asg r4.b1, H_FRAME_acc1 + .asg r4.b2, H_FRAME_flags_l + .asg r4.b3, H_FRAME_flags_h + + +short_msg_s .struct +crc .short +data .byte +addr .byte +bits_left .byte +timeout .byte + .endstruct +SHORT_MSG .sassign r26, short_msg_s + .asg r26, SHORT_MSG32 + .asg r26.b0, SHORT_MSG_CRC_L + .asg r26.b1, SHORT_MSG_CRC_H + +long_msg_recv_s .struct +crc .short +bits_left .byte +ptr .byte + .endstruct +LONG_MSG_RECV .sassign r28, long_msg_recv_s + .asg r28.b1, LONG_MSG_RECV_CRC_H + .asg r28.b0, LONG_MSG_RECV_CRC_L + + + .asg r6.b3, QM + .asg r6.b2, SLAVE_DELAY + .asg r6.b1, LAST_BIT_SENT + .asg r6.b0, SAMPLE_EDGE + .asg r5, LOOP_CNT + .asg r0, REG_TMP0 + .asg r1, REG_TMP1 + .asg r2, REG_TMP2 + .asg r20, REG_SCRATCH + .asg r11, REG_TMP11 + .asg r16.b0, RSSI + .asg r16.b1, CUR_EDGES + .asg r16.b2, SPECIAL_CHARACTER + .asg r16.b3, BYTE_ERROR + .asg r15, FAST_POSH + .asg r14.b3, FAST_POSL + .asg r14, SPEED + .asg r17.b0, DISPARITY + .asg r17.b1, SEND_PARA + .asg r29.w0, RET_ADDR0 + .asg r17.w2, RET_ADDR1 + .asg r29.b2, NUM_ACC_BITS + .asg r29.b3, NUM_ST_BITS + .asg r13, REG_FNC + .asg r7.w0, DELTA_ACC0 + .asg r7.w2, DELTA_ACC1 + .asg r8.w0, DELTA_ACC2 + .asg r8.w2, DELTA_ACC3 + .asg r9.w0, DELTA_ACC4 + .asg r9.w2, LAST_ACC + ;.asg r10, EXTRA_POS + ;.asg r10.w0, TIME_COMP + ;.asg r10.w2, LAST_TIME_COMP + .asg r10.w0, SYNC_DIFF0 + .asg r10.w2, LOOP_CNT_0 + .asg r12.b0, EXTRA_SIZE + .asg r12.b1, NUM_STUFFING + .asg r12.b2, EXTRA_EDGE + .asg r12.b3, TIME_REST + .asg r27.b2, NUM_PULSES + .asg r25.b2, TIME_EXTRA_WINDOW ;free for am65xx use case + .asg r25.b3,FIFO_L ;load fifo + .asg r25.b2, MODIFIED_HEADER_STARTED + .asg r27.b3, LEARN_STATE_STARTED + .asg r25.b0, ALIGN_PH + .asg r24, CRC + .asg r24.w0, CRC_VERT + .asg r24.b1, CRC_VERT_H + .asg r24.b0, CRC_VERT_L + .asg r24.w2, CRC_SEC + .asg r24.b3, CRC_SEC_H + .asg r24.b2, CRC_SEC_L + + .asg r2.b0, EXTRA_SIZE_SELF ;take care! these are not persistent registers, r2 is actually temp reigister. these names are + .asg r2.b1, EXTRA_EDGE_SELF ;given to temp register for ease of reading. they are used as temp. + + .asg r10.b0, EXTRA_EDGE_COMP + .asg r10.b1, EXTRA_SIZE_COMP + .asg r10.b2, TIME_REST_COMP + .asg r10.b3, NUM_STUFFING_COMP + +;-------------------------------------------------------------------------------------------------- +;DSL Master Register offsets +SYS_CTRL .set 0x00 +SYNC_CTRL .set 0x01 +MASTER_QM .set 0x03 +EVENT_H .set 0x04 +EVENT_L .set 0x05 +MASK_H .set 0x06 +MASK_L .set 0x07 +MASK_SUM .set 0x08 +EDGES .set 0x09 +DELAY .set 0x0A +VERSION .set 0x0B +ENC_ID2 .set 0x0D +ENC_ID1 .set 0x0E +ENC_ID0 .set 0x0F +POS4 .set 0x10 +POS3 .set 0x11 +POS2 .set 0x12 +POS1 .set 0x13 +POS0 .set 0x14 +VEL2 .set 0x15 +VEL1 .set 0x16 +VEL0 .set 0x17 +;SUMMARY/MIR_SUM is not supported +;SUMMARY .set 0x18 +VPOS4 .set 0x19 +VPOS3 .set 0x1A +VPOS2 .set 0x1B +VPOS1 .set 0x1C +VPOS0 .set 0x1D +VPOSCRC_H .set 0x1E +VPOSCRC_L .set 0x1F +PC_BUFFER0 .set 0x20 +PC_BUFFER1 .set 0x21 +PC_BUFFER2 .set 0x22 +PC_BUFFER3 .set 0x23 +PC_BUFFER4 .set 0x24 +PC_BUFFER5 .set 0x25 +PC_BUFFER6 .set 0x26 +PC_BUFFER7 .set 0x27 +PC_ADD_H .set 0x28 +PC_ADD_L .set 0x29 +PC_OFF_H .set 0x2A +PC_OFF_L .set 0x2B +PC_CTRL .set 0x2C +PIPE_S .set 0x2D +PIPE_D .set 0x2E +PC_DATA .set 0x2F + +SAFE_CTRL .set 0x35 +SAFE_SUM .set 0x36 +S_PC_DATA .set 0x37 + +ACC_ERR_CNT .set 0x38 +MAXACC .set 0x39 +MAXDEV_H .set 0x3A +MAXDEV_L .set 0x3B + +EVENT_S .set 0x3D +MASK_S .set 0x3E + +DUMMY .set 0x3F +;extra Master Registers as workaround for different access method depended behaviour (r/w) +SLAVE_REG_CTRL .set 0x40 +ACC_ERR_CNT_TRESH .set 0x41 +MAXDEV_TRESH_H .set 0x42 +MAXDEV_TRESH_L .set 0x43 +;extra MASTER registers (not in the specification! little endian!) +NUM_VERT_ERR0 .set 0x90 +NUM_VERT_ERR1 .set 0x91 +NUM_VERT_ERR2 .set 0x92 +NUM_VERT_ERR3 .set 0x93 +NUM_VERT_FRAMES0 .set 0x94 +NUM_VERT_FRAMES1 .set 0x95 +NUM_VERT_FRAMES2 .set 0x96 +NUM_VERT_FRAMES3 .set 0x97 +REL_POS0 .set 0x98 +REL_POS1 .set 0x99 +REL_POS2 .set 0x9a +REL_POS3 .set 0x9b +MISMATCH0 .set 0x9c +MISMATCH1 .set 0x9d +MISMATCH2 .set 0x9e +MISMATCH3 .set 0x9f +NUM_H_ERR0 .set 0xa0 +NUM_H_ERR1 .set 0xa1 +NUM_H_ERR2 .set 0xa2 +NUM_H_ERR3 .set 0xa3 +LAST_FAST_POS0 .set 0xa4 +LAST_FAST_POS1 .set 0xa5 +LAST_FAST_POS2 .set 0xa6 +LAST_FAST_POS3 .set 0xa7 +LAST_FAST_POS4 .set 0xa8 +NUM_RESETS .set 0xa9 +EVENT_UPDATE_PENDING .set 0xaa +;EVENT_UPDATE_PENDING Bit Defines +EVENT_UPDATE_PENDING_QMLW .set (0) +EVENT_UPDATE_PENDING_POS .set (1) +EVENT_UPDATE_PENDING_BIT_2 .set (2) +EVENT_UPDATE_PENDING_BIT_3 .set (3) +EVENT_UPDATE_PENDING_BIT_4 .set (4) +EVENT_UPDATE_PENDING_BIT_5 .set (5) +EVENT_UPDATE_PENDING_BIT_6 .set (6) +EVENT_UPDATE_PENDING_BIT_7 .set (7) +TEST_PATTERN0 .set 0xac +TEST_PATTERN1 .set 0xad +TEST_PATTERN2 .set 0xae +TEST_PATTERN3 .set 0xaf +TEST_PATTERN4 .set 0xb0 +TEST_PATTERN5 .set 0xb1 +TEST_PATTERN6 .set 0xb2 +TEST_PATTERN7 .set 0xb3 +TEST_PAT_MASK0 .set 0xb4 +TEST_PAT_MASK1 .set 0xb5 +TEST_PAT_MASK2 .set 0xb6 +TEST_PAT_MASK3 .set 0xb7 +SYNC_DIFF .set 0xb8 +SYNC_PULSE_PERIOD .set 0xbc +LONG_MSG_BUFFER .set 0xc4 +SYNC_PULSE_ERROR .set 0xc0 +ECAP_OFFSETS .set 0xce +EXTRA_EDGE_TIMESTAMP .set 0xd8;4bytes +SYNC_PARAM1 .set 0xdc;4bytes +SYNC_EXTRA_REMAINDER .set 0xe0;1bytes +SYNC_STUFFING_REMAINDER .set 0xe1;1bytes +WAIT_BEFORE_START .set 0xe2;2bytes ;free +MASK_POS .set 0xe4;4bytes +SYNC_JITTER .set 0xe8;2bytes +SYNC_DIFF_HIST_CNT .set 0xea;2bytes +SYNC_DIFF_HIST .set 0xec;2*8bytes +DUMMY_END .set 0xff +ADDR .set 0x15ff +;-------------------------------------------------------------------------------------------------- +;Memory offsets +;-------------------------------------------------------------------------------------------------- +PRU_CTRL_CONST .set C28 +;PRU_CTRL .set 0x00022000 +PRU_CYCLCNT .set 0x0c +PWMSS1_CONST .set C19 ;AM437x specific for sync pule synchronization +PWMSS1_ECAP .set 0x48302100 ;AM437x specific for sync pule synchronization +PWMSS2_CONST .set C20 ;AM437x specific for sync pule synchronization +ECAP .set 0x100 ;AM437x specific for sync pule synchronization +ECAP_ECCLR .set 0x30 ;AM437x specific for sync pule synchronization +ECAP_ECEINT .set 0x2c ;AM437x specific for sync pule synchronization +ECAP_CAP1 .set 0x08 ;AM437x specific for sync pule synchronization +ECAP_ECCTL1 .set 0x28 ;AM437x specific for sync pule synchronization +INTC_SICR .set 0x24 ;AM437x specific for sync pule synchronization +INTC_SECR1 .set 0x284 ;AM437x specific for sync pule synchronization +INTC_SECR0 .set 0x280 ;AM437x specific for sync pule synchronization +INTC_CONST .set C0 ;AM437x specific for sync pule synchronization +IEP_CONST .set C26 +IEP1_CONST .set 0x2F000 +IEP_CNT .set 0x14 ;todo TSmod check as 64bit now (old0x0c) +IEP_CAPR6_RISE .set 0x50 +SHARED_MEM_CONST .set 0x0b010000;0x54442000+0x10000 +;-------------------------------------------------------------------------------------------------- +;Memory offsets for dynamic loading of PRU code +;-------------------------------------------------------------------------------------------------- +CODE_BASE .set (0x40300000);(0x54400000+0x00040000+0x2100) +CODE_SIZE .set 0x600 +DYNAMIC_CODE_OFFSET .set 0x1000 ;0x2100 + +;-------------------------------------------------------------------------------------------------- +;R31 flags for RX +;-------------------------------------------------------------------------------------------------- + .if $defined(CHANNEL_2) +RX_OVERFLOW_FLAG .set 29 +RX_VALID_FLAG .set 26 + .endif + + .if $defined(CHANNEL_1) +RX_OVERFLOW_FLAG .set 28 +RX_VALID_FLAG .set 25 + .endif + + .if $defined(CHANNEL_0) +RX_OVERFLOW_FLAG .set 27 +RX_VALID_FLAG .set 24 + .endif + +;-------------------------------------------------------------------------------------------------- +;R30 flags for RX +;-------------------------------------------------------------------------------------------------- + .if $defined(CHANNEL_2) +RX_ENABLE .set 26 + .endif + + .if $defined(CHANNEL_1) +RX_ENABLE .set 25 + .endif + + .if $defined(CHANNEL_0) +RX_ENABLE .set 24 + .endif + +;-------------------------------------------------------------------------------------------------- +;R31 flags for TX +;-------------------------------------------------------------------------------------------------- + +;global flags +TX_GLOBAL_TX_GO .set 20 +TX_GLOBAL_REINIT .set 19 +TX_CHANNEL_GO .set 18 + + .if $defined(CHANNEL_2) +TX_GLOBAL_REINIT_ACTIVE .set 21 +TX_UNDERRUN .set 17 +TX_OVERRUN .set 16 + .endif + + .if $defined(CHANNEL_1) +TX_GLOBAL_REINIT_ACTIVE .set 13 +TX_UNDERRUN .set 9 +TX_OVERRUN .set 8 + .endif + + .if $defined(CHANNEL_0) +TX_GLOBAL_REINIT_ACTIVE .set 5 +TX_UNDERRUN .set 1 +TX_OVERRUN .set 0 + .endif + +;-------------------------------------------------------------------------------------------------- +;R30 flags for TX +;-------------------------------------------------------------------------------------------------- + + .if $defined(CHANNEL_2) +CHANNEL_NUM .set 1 + .endif + + .if $defined(CHANNEL_1) +CHANNEL_NUM .set 0 + .endif + +VERSION2 .set 0x44 +ENC2_ID .set 0x45 +STATUS2 .set 0x46 +VPOS24 .set 0x47 +VPOS23 .set 0x48 +VPOS22 .set 0x49 +VPOS21 .set 0x4A +VPOS20 .set 0x4B +VPOSCRC2_H .set 0x4C +VPOSCRC2_L .set 0x4D +POSTX .set 0x4E + +ONLINE_STATUS_D .set 0x50 +ONLINE_STATUS_1 .set 0x52 +ONLINE_STATUS_2 .set 0x54 + +H_FRAME_FLAGS_TEMP .set 0x56 ; 2 bytes +CRC_SEC_TEMP .set 0x58 ; 2 bytes +VPOS_VALID .set 0x5A ; 1 byte +VPOS_TEMP .set 0x5B ; 5 bytes +VPOSCRC_TEMP .set 0x60 ; 2 bytes +STATUS2_TEMP .set 0x62 ; 1 byte +VPOS2_TEMP .set 0x63 ; 5 bytes +VPOSCRC2_TEMP .set 0x68 ; 2 bytes +SAFE_SUM_TEMP .set 0x70 ; 1 byte \ No newline at end of file diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js new file mode 100644 index 0000000..7522b8b --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; \ No newline at end of file diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project_am243x.js b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project_am243x.js new file mode 100644 index 0000000..d0bb7b5 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project_am243x.js @@ -0,0 +1,100 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "main.asm", + "datalink.asm", + "datalink_init.asm", + "transport.asm", + "utils.asm", + "hdsl_master_icssg_hexpru.cmd", + "hdsl_master_icssg.cmd", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_0", + "ICSS_G_V_1_0", + "FREERUN_300_MHZ", + "HDSL_MULTICHANNEL", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch0_bin.h Hiperface_DSL2_0_RTU 4; move hdsl_master_icssg_multichannel_ch0_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_multichannel_ch0"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project_am64x.js b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project_am64x.js new file mode 100644 index 0000000..8b30e11 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/.project/project_am64x.js @@ -0,0 +1,100 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "main.asm", + "datalink.asm", + "datalink_init.asm", + "transport.asm", + "utils.asm", + "hdsl_master_icssg_hexpru.cmd", + "hdsl_master_icssg.cmd", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_0", + "ICSS_G_V_1_0", + "FREERUN_300_MHZ", + "HDSL_MULTICHANNEL", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch0_bin.h Hiperface_DSL2_0_RTU 4; move hdsl_master_icssg_multichannel_ch0_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_multichannel_ch0"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..28cd2f7 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..d14e4bf --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..b53941c --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch0/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(/// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_1", + "ICSS_G_V_1_0", + "FREERUN_300_MHZ", + "HDSL_MULTICHANNEL", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch1_bin.h Hiperface_DSL2_0_PRU 4; move hdsl_master_icssg_multichannel_ch1_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_multichannel_ch1"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/.project/project_am64x.js b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/.project/project_am64x.js new file mode 100644 index 0000000..06a1521 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/.project/project_am64x.js @@ -0,0 +1,100 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "main.asm", + "datalink.asm", + "datalink_init.asm", + "transport.asm", + "utils.asm", + "hdsl_master_icssg_hexpru.cmd", + "hdsl_master_icssg.cmd", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_1", + "ICSS_G_V_1_0", + "FREERUN_300_MHZ", + "HDSL_MULTICHANNEL", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch1_bin.h Hiperface_DSL2_0_PRU 4; move hdsl_master_icssg_multichannel_ch1_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_multichannel_ch1"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..7f4777f --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..c2f577d --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..1eece1f --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/multichannel_ch1/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(/// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_0", + "EXT_SYNC_ENABLE", + "ICSS_G_V_1_0", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_sync_bin.h Hiperface_DSL_SYNC2_0 4; move hdsl_master_icssg_sync_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_sync_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_sync_225_mhz"; + property.description = "HDSL Master Sync Mode Firmware for PRU-ICSS running at 225 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/.project/project_am64x.js b/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/.project/project_am64x.js new file mode 100644 index 0000000..1312898 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/.project/project_am64x.js @@ -0,0 +1,99 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "main.asm", + "datalink.asm", + "datalink_init.asm", + "transport.asm", + "utils.asm", + "hdsl_master_icssg_hexpru.cmd", + "hdsl_master_icssg.cmd", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_0", + "EXT_SYNC_ENABLE", + "ICSS_G_V_1_0", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_sync_bin.h Hiperface_DSL_SYNC2_0 4; move hdsl_master_icssg_sync_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware/hdsl_master_icssg_sync_bin.h ;" + +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_sync_225_mhz"; + property.description = "HDSL Master Sync Mode Firmware for PRU-ICSS running at 225 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..72a30de --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,87 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..1631492 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0 --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..f14a247 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/hdsl/firmware/sync_225_mhz/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0 --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( could be replaced with PA STATS on ICSS_G +;Not required as it's not part of SICK IP requirement. + .if 0 + lbco ®_TMP1, MASTER_REGS_CONST, NUM_VERT_FRAMES0, 4 + add REG_TMP1, REG_TMP1, 1 + sbco ®_TMP1, MASTER_REGS_CONST, NUM_VERT_FRAMES0, 4 + .endif +; clear VPOS_VALID + zero ®_TMP0.b0, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, VPOS_VALID, 1 + +;store CRC in Master Registers + mov REG_TMP1.b0, VERT_L.b1 + mov REG_TMP1.b1, VERT_L.b0 +; Store the required data for vertical channel in temporary memory. +; It will be stored to DMEM in transport_on_v_frame_2 + sbco ®_TMP1, MASTER_REGS_CONST, VPOSCRC_TEMP, 2 +;transmission error? + qbbs transport_on_v_frame_dont_update_qm, H_FRAME.flags, FLAG_ERR_VERT + lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1, 1 + and REG_TMP1.b0, REG_TMP1.b0, (~((1< add 1 to QM + QM_ADD 1 +;check for special character: K29.7 is sent in first byte of vertical channel if slave error occured + qbne transport_on_v_frame_check_pos, VERT_H.b3, K29_7 +; Set EVENT_S_VPOS in EVENT register, due to encoder internal error + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 + set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_VPOS +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + qbbc update_events_no_int5, REG_TMP0.b1, EVENT_S_VPOS +; generate interrupt_s + ldi r31.w0, PRU0_ARM_IRQ4 +update_events_no_int5: +; Set ONLINE_STATUS_1_VPOS in ONLINE_STATUS_1 register + set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_1_VPOS + sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1, 1 + qba transport_on_v_frame_exit +transport_on_v_frame_check_pos: + sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1, 1 + lsl REG_TMP2, CHANNEL.ch_verth, 8 + mov REG_TMP2.b0, VERT_L.b3 +;first V-Frame? -> update FAST POS with SAFE POS +transport_on_v_frame_not_first: +;check for LAST FAST POS and SAFE POS mismatch + lbco ®_TMP0.b0, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS + sub REG_TMP1.w0, VERT_L.w2, REG_TMP0.w0 + suc REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2 + mov REG_TMP2, REG_TMP1 +;check if diff is neg, + qbbc transport_on_v_frame_diff_pos, REG_TMP2, 31 + not REG_TMP2, REG_TMP2 + add REG_TMP2, REG_TMP2, 1 +transport_on_v_frame_diff_pos: +;load MAXDEV_H/L + lbco ®_TMP0.w2, MASTER_REGS_CONST, MAXDEV_H, 2 + mov REG_TMP0.b0, REG_TMP0.b2 + mov REG_TMP0.b2, REG_TMP0.b3 + mov REG_TMP0.b3, REG_TMP0.b0 +;check if it is larger + lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + qbge transport_on_v_frame_dont_update_maxdev, REG_TMP2, REG_TMP0.w2 + mov REG_TMP0.b0, REG_TMP2.b1 + mov REG_TMP0.b1, REG_TMP2.b0 + sbco ®_TMP0, MASTER_REGS_CONST, MAXDEV_H, 2 +transport_on_v_frame_dont_update_maxdev: +;load MAXDEV_TRESH_H/L + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + .endif + lbco ®_TMP0.w2, MASTER_REGS_CONST, MAXDEV_TRESH_H, 2 + mov REG_TMP0.b0, REG_TMP0.b2 + mov REG_TMP0.b2, REG_TMP0.b3 + mov REG_TMP0.b3, REG_TMP0.b0 +;check if it is larger + lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + qbge transport_on_v_frame_dont_update_dte, REG_TMP2, REG_TMP0.w2 +; Set EVENT_DTE in ONLINE_STATUS_D register + set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE +; Set EVENT_DTE in EVENT register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + set REG_TMP0.w0, REG_TMP0.w0, EVENT_DTE +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int6, REG_TMP0.w2, EVENT_DTE +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int6: +transport_on_v_frame_dont_update_dte: +; Clear EVENT_DTE in ONLINE_STATUS_D register + clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_DTE + sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 +;check for diff. is 0 -> estimate if not + + qbne transport_on_v_frame_estimate, REG_TMP1, 0 + qbne transport_on_v_frame_estimate, VERT_H.b2, FAST_POSL +;reset MAXDEV_H/L + sbco ®_FNC.w0, MASTER_REGS_CONST, MAXDEV_H, 2 +;reset ALIGN_PH + ldi ALIGN_PH, 0 + qba transport_on_v_frame_no_pos_mismatch +; estimate/correct +transport_on_v_frame_estimate: + CALL1 estimator_fpos +transport_on_v_frame_no_pos_mismatch: +;store SAFE POS + + mov REG_TMP0.b0, VERT_H.b2 + mov REG_TMP0.b1, VERT_H.b1 + mov REG_TMP0.b2, VERT_H.b0 + mov REG_TMP0.b3, VERT_L.b3 + mov REG_TMP1.b0, VERT_L.b2 + +; Store the required data for vertical channel in temporary memory. +; It will be stored to DMEM in transport_on_v_frame_2 + sbco ®_TMP0.b0, MASTER_REGS_CONST, VPOS_TEMP, 5 + +; set VPOS_VALID + ldi REG_TMP0.b0, 0x1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, VPOS_VALID, 1 + +; Store the required data for secondary channel in temporary memory. +; It will be processed in transport_on_v_frame_2 + +; store H_FRAME.flags + sbco &H_FRAME.flags, MASTER_REGS_CONST, H_FRAME_FLAGS_TEMP, 2 +; store CRC_SEC + sbco &CRC_SEC, MASTER_REGS_CONST, CRC_SEC_TEMP, 2 +; store the 8 bytes from secondary channel + sbco &R20, MASTER_REGS_CONST, VPOS2_TEMP, 8 + +transport_on_v_frame_exit: +;we are in RX0 +;reset rel. pos + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_CONST 0xff + .endif + ldi REG_TMP0, 0 + sbco ®_TMP0, MASTER_REGS_CONST, REL_POS0, 4 +;store last FAST_POS + sbco &FAST_POSL, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS + +; Store summary + sbco &VERT_H.b3, MASTER_REGS_CONST, SAFE_SUM_TEMP, 1 + +;restore REG_FNC.w0 content + mov REG_FNC.w0, REG_TMP11.w1 +;reset vertical/secondary channel crc + ldi CRC, 0 +;reset flags + and H_FRAME_flags_l, H_FRAME_flags_l, FLAG_ERRORS + jmp datalink_transport_on_v_frame_done + +;---------------------------------------------------- +;transport_on_v_frame_2 +; Cycle Budget : 140 cycles +; extracts safe position from secondary channel +; verifies the summary from encoder +; NOT allowed to use REG_TMP11 +;---------------------------------------------------- +transport_on_v_frame_2: + +;save REG_FNC.w0 content + mov REG_TMP11.w1, REG_FNC.w0 + +; retrieve the 8 bytes for secondary channel from VPOS2_TEMP + lbco ®_TMP1, MASTER_REGS_CONST, VPOS2_TEMP, 8 + +; error checks for secondary channel + lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 +; retrieve H_FRAME.flags from H_FRAME_FLAGS_TEMP + lbco ®_TMP0.w2, MASTER_REGS_CONST, H_FRAME_FLAGS_TEMP, 2 +;channel 2 transmission error? + qbbs transport_on_v_frame_dont_update_qm_secondary_channel, REG_TMP0.w2, FLAG_ERR_SEC +;checking for crc error in channel 2 +; retrieve CRC_SEC from CRC_SEC_TEMP + lbco ®_TMP0.w2, MASTER_REGS_CONST, CRC_SEC_TEMP, 2 + qbeq check_for_slave_error_on_secondary_channel, REG_TMP0.w2, 0 +; set SCE2 bit in ONLINE_STATUS_2 + set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + QM_SUB 6 +transport_on_v_frame_dont_update_qm_secondary_channel: + qba transport_on_v_frame_2_exit +check_for_slave_error_on_secondary_channel: +; clear SCE2 bit in ONLINE_STATUS_2 + clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 +;CRC was correct -> add 1 to QM + QM_ADD 1 +; NOTE: QM_ADD uses REG_TMP0. Loading REG_TMP0 again here. It can be optimized. + lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 +;check for special character: K29.7 is sent in first byte of secondary vertical channel if slave error occured +; assumption: r21.b3 contains the first byte of secondary vertical channel + qbne transport_on_v_frame_no_vpos2_error, REG_TMP2.b3, K29_7 + ; set VPOS2 bit in ONLINE_STATUS_2 + set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + qba transport_on_v_frame_vpos2_error_exit +transport_on_v_frame_no_vpos2_error: + clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 +transport_on_v_frame_vpos2_error_exit: + +; store the data from secondary channel +; invert the bits for STATUS2 + xor REG_TMP2.b3, REG_TMP2.b3, 0xe0 +; swap bytes in each 32 bit register REG_TMP1 and REG_TMP2 + xin 160, ®_TMP1, 8 + +; update ONLINE_STATUS_2_SUM2 in ONLINE_STATUS_2 + qbbs online_status_2_sum2_set, REG_TMP2.b0, STATUS2_TEST2 + qbbs online_status_2_sum2_set, REG_TMP2.b0, STATUS2_ERR2 + clr REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SUM2 + qba online_status_2_sum2_not_set +online_status_2_sum2_set: + set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SUM2 +online_status_2_sum2_not_set: + sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2, 1 + + +; Store STATUS2, VPOS24, VPOS23 and VPOS22 + sbco ®_TMP2.b0, MASTER_REGS_CONST, STATUS2, 4 +; Store VPOS21, VPOS20, VPOSCRC2_H and VPOSCRC2_L + sbco ®_TMP1.b0, MASTER_REGS_CONST, VPOS21, 4 +; generate interrupt PRU0_ARM_IRQ2 + ldi r31.w0, PRU0_ARM_IRQ2 + +transport_on_v_frame_2_exit: + +; Check for VPOS_VALID, If it is valid, update the position and crc to DMEM +; and raise interrupt + lbco ®_TMP0.b0, MASTER_REGS_CONST, VPOS_VALID, 1 + qbne transport_skip_vpos_update, REG_TMP0.b0, 1 + lbco ®_TMP0.b0, MASTER_REGS_CONST, VPOS_TEMP, 7 + sbco ®_TMP0.b0, MASTER_REGS_CONST, VPOS4, 7 +; generate interrupt PRU0_ARM_IRQ1 + ldi r31.w0, PRU0_ARM_IRQ1 +transport_skip_vpos_update: +; Set POSTX to 3 + ldi REG_TMP0.b0, 0x3 + sbco ®_TMP0.b0, MASTER_REGS_CONST, POSTX, 1 + +; Load summary + lbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM_TEMP, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM, 1 +;check SUMMARY and MASK_SUM + lbco ®_TMP1.b1, MASTER_REGS_CONST, MASK_SUM, 1 + and REG_TMP1.b0, REG_TMP0.b0, REG_TMP1.b1 + lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 3 + clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM + clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM + qbeq summary_no_int, REG_TMP1.b0, 0x00 +;set event and generate interrupt + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + ;set REG_TMP0.w0, REG_TMP0.w0, REG_FNC.b0 + set REG_TMP0.w0, REG_TMP0.w0, EVENT_SUM +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int7, REG_TMP0.w2, REG_TMP0.w2 +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int7: +;set event_s and generate interrupt_s + lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 + set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SSUM +;save events + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 + qbbc update_events_no_int17, REG_TMP0.b1, EVENT_S_SSUM +; generate interrupt_s + ldi r31.w0, PRU0_ARM_IRQ4 +update_events_no_int17: + set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM + set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM +summary_no_int: + sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 3 + +;restore REG_FNC.w0 content + mov REG_FNC.w0, REG_TMP11.w1 + + jmp datalink_transport_on_v_frame_done_2 +;---------------------------------------------------- +;transport_layer_recv_msg +;Handles Hiperface DSL messages receiving +;?? cycles +;input: +;output: +;modifies: +;---------------------------------------------------- +transport_layer_recv_msg: +;check if we reset protocol + lbco ®_TMP0.b0, MASTER_REGS_CONST, SYS_CTRL, 1 +;ERROR: qbbc datalink_abort2 is not working, though no compiler error + qbbc transport_layer_no_prst, REG_TMP0.b0, SYS_CTRL_PRST + + jmp datalink_abort +transport_layer_no_prst: +;check if we reset protocol by reading SAFE_CTRL register + lbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_CTRL, 1 + qbbc transport_layer_no_safe_prst, REG_TMP0.b0, SAFE_CTRL_PRST + jmp datalink_abort +transport_layer_no_safe_prst: +;are we already receiving a long message? + qbeq transport_layer_check_for_new_msg, LONG_MSG_RECV.bits_left, 0 + + and REG_TMP2.b0, CHANNEL.ch_paral, 0x0f +;last byte (crc low)? -> then flip it + qblt transport_layer_recving_long_msg_dont_flip_nibble, LONG_MSG_RECV.bits_left, 8 + xor REG_TMP2.b0, REG_TMP2.b0, 0x0f +transport_layer_recving_long_msg_dont_flip_nibble: +;calculate running crc + ldi REG_TMP0, (LUT_CRC16+PDMEM00) + lsr REG_TMP1.b0, LONG_MSG_RECV_CRC_H, 4 + xor REG_TMP1.b0, REG_TMP1.b0, REG_TMP2.b0 + lsl REG_TMP1.w0, REG_TMP1.b0, 1 + lbbo ®_TMP1.w0, REG_TMP0, REG_TMP1.w0, 2 + lsl LONG_MSG_RECV.crc, LONG_MSG_RECV.crc, 4 + xor LONG_MSG_RECV.crc, LONG_MSG_RECV.crc, REG_TMP1.w0 + +;are we receiving crc? + qbge transport_layer_recving_long_msg_crc, LONG_MSG_RECV.bits_left, 16 +;still receiving data + qbbs transport_layer_recving_long_msg_data_low_nibble, LONG_MSG_RECV.bits_left, 2 + +transport_layer_recving_long_msg_data_high_nibble: + + lsl REG_TMP0.b0, REG_TMP2.b0, 4 + sbco ®_TMP0.b0, MASTER_REGS_CONST, LONG_MSG_RECV.ptr, 1 + ;160 + + qba transport_layer_recving_long_msg_data_nibble_end +transport_layer_recving_long_msg_data_low_nibble: + + lbco ®_TMP0.b0, MASTER_REGS_CONST, LONG_MSG_RECV.ptr, 1 + or REG_TMP0.b0, REG_TMP0.b0, REG_TMP2.b0 + sbco ®_TMP0.b0, MASTER_REGS_CONST, LONG_MSG_RECV.ptr, 1 + add LONG_MSG_RECV.ptr, LONG_MSG_RECV.ptr, 1 +transport_layer_recving_long_msg_data_nibble_end: + + qba transport_layer_recving_long_msg_end +transport_layer_recving_long_msg_crc: +;we are receiving crc + + qbne transport_layer_recving_long_msg_end, LONG_MSG_RECV.bits_left, 4 +;set long msg channel to unbusy +; Set EVENT_FREL in EVENT register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + set REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int8, REG_TMP0.w2, EVENT_FREL +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int8: +; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 +;check for crc error + qbeq transport_layer_recving_long_msg_end, LONG_MSG_RECV.crc, 0 +; Set EVENT_ANS in EVENT register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + set REG_TMP0.w0, REG_TMP0.w0, EVENT_ANS +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int9, REG_TMP0.w2, EVENT_ANS +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int9: +; Set ANS in ONLINE_STATUS_D register + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + set REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 +transport_layer_recving_long_msg_end: +; Clear ANS in ONLINE_STATUS_D register + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_MIN-8) + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + sub LONG_MSG_RECV.bits_left, LONG_MSG_RECV.bits_left, 4 + qba transport_layer_recv_msg_end +transport_layer_check_for_new_msg: +;check only position ch_para[35:39], if found at this position, we can use subsequent nibbles and have full short message available + lsr REG_TMP0.b0, CHANNEL.ch_parah, 3 + and REG_TMP0.b0, REG_TMP0.b0, 0x1f + qbeq transport_layer_recv_no_msg, REG_TMP0.b0, S_PAR_IDLE + qbbs transport_layer_recv_msg_end, H_FRAME.flags, FLAG_WAIT_IDLE +;check for special character + qbbs transport_layer_recv_msg_check_for_nak, REG_TMP0.b0, 4 +;set flag to signalize that we need to wait for next S_PAR_IDLE again, so we do not parse data multiple times + set H_FRAME.flags, H_FRAME.flags, FLAG_WAIT_IDLE +;reassemble 32 bits of msg, 5bits->4bits + and REG_TMP11.b3, REG_TMP0.b0, 0x1f + lsl REG_TMP11.b3, REG_TMP11.b3, 4 + lsl REG_TMP0.b0, CHANNEL.ch_parah, 2 + lsr REG_TMP0.b1, CHANNEL.ch_paral, 30 + or REG_TMP0.b0, REG_TMP0.b0, REG_TMP0.b1 + and REG_TMP0.b0, REG_TMP0.b0, 0x0f + or REG_TMP11.b3, REG_TMP11.b3, REG_TMP0.b0 + + mov REG_TMP2, CHANNEL.ch_paral + ldi REG_TMP1.b0, ®_TMP11.b0 + loop transport_layer_reassemble_msg_loop, 3 + and REG_TMP0.b1, REG_TMP2.b0, 0x0f + lsr REG_TMP0.b2, REG_TMP2, 1 + and REG_TMP0.b2, REG_TMP0.b2, 0xf0 + or REG_TMP0.b0, REG_TMP0.b1, REG_TMP0.b2 + mvib *REG_TMP1.b0++, REG_TMP0.b0 + lsr REG_TMP2, REG_TMP2, 10 +transport_layer_reassemble_msg_loop: +;identify message type + ;jmp transport_layer_received_long_msg + qbbs transport_layer_received_long_msg, REG_TMP11.b3, 7 +transport_layer_received_short_msg: +;check crc + ldi REG_TMP1.b0, &r12.b0 +;read or write? + qbbs transport_layer_short_msg_recv_read, REG_TMP11.b3, 6 +;received write ack + ldi REG_FNC.b0, 1 + CALL1 (calc_16bit_crc);-DYNAMIC_CODE_OFFSET-CODE_TRANSPORT_LAYER*CODE_SIZE) + qbne transport_layer_recv_msg_check_for_nak, REG_FNC.w0, REG_TMP11.w1 +;we received a valid msg -> set ACK flag + or SHORT_MSG.timeout, SHORT_MSG.timeout, (1< set ACK flag + or SHORT_MSG.timeout, SHORT_MSG.timeout, (1< we send lower nibble + qbbc transport_layer_sned_long_msg_lower_nibble, SHORT_MSG.bits_left, 2 + lsr SEND_PARA, SEND_PARA, 4 + qba transport_layer_sned_long_msg_nibble_end +transport_layer_sned_long_msg_lower_nibble: + and SEND_PARA, SEND_PARA, 0x0f + add SHORT_MSG.data, SHORT_MSG.data, 1 +transport_layer_sned_long_msg_nibble_end: + qba transport_layer_send_sending_calc_crc +transport_layer_send_sending_short_msg: +;we are still sending short message + lsr SEND_PARA, SHORT_MSG32, SHORT_MSG.bits_left +;no special char -> only 4 bits + and SEND_PARA, SEND_PARA, 0x0f +transport_layer_send_sending_calc_crc: +;calculate running CRC + ldi REG_TMP2, (LUT_CRC16+PDMEM00) + lsr REG_TMP0.b0, SHORT_MSG_CRC_H, 4 + xor REG_TMP0.b0, REG_TMP0.b0, SEND_PARA + lsl REG_TMP0.w0, REG_TMP0.b0, 1 + lbbo ®_TMP0.w0, REG_TMP2, REG_TMP0.w0, 2 + lsl SHORT_MSG.crc, SHORT_MSG.crc, 4 + xor SHORT_MSG.crc, SHORT_MSG.crc, REG_TMP0.w0 +;flip lower crc byte (only once) + qbne transport_layer_send_sending_msg_crc_dont_flip, SHORT_MSG.bits_left, 16 + xor SHORT_MSG_CRC_L, SHORT_MSG_CRC_L, 0xff +transport_layer_send_sending_msg_crc_dont_flip: + qba transport_layer_send_msg_end +transport_layer_check_for_new_short_msg: +;check for SLAVE_REG_CTRL if we read/write data + + lbco ®_TMP0.b0, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1 + qbeq transport_layer_no_short_msg, REG_TMP0.b0, 0x3f +;set short msg channel to busy (reset EVENT_S_FRES) + lbco ®_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 + clr REG_TMP0.b2, REG_TMP0.b2, EVENT_S_FRES + sbco ®_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 +; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register + lbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 + clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_FRES-8) + sbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1+1), 1 +;reset + ldi REG_TMP0.b1, 0x3f + sbco ®_TMP0.b1, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1 +;only 6 bit address + and SHORT_MSG.addr, REG_TMP0.b0, 0x3f +;reset CRC + ldi SHORT_MSG.crc, 0 + +;MSB in Master Register identifies mode (r/w) + qbbc transport_layer_short_msg_write, REG_TMP0.b0, 7 +;we read slave register + or SHORT_MSG.addr, SHORT_MSG.addr, (MSG_READ<<6) +;read short messages contain less content -> move addr part to data + mov SHORT_MSG.data, SHORT_MSG.addr + ldi SHORT_MSG.bits_left, (8*3) + qba transport_layer_short_msg_dir_end +transport_layer_short_msg_write: +;we write slave register -> DIR=0 +;load data from S_PC_DATA for writing + lbco ®_TMP0.b1, MASTER_REGS_CONST, S_PC_DATA, 1 + mov SHORT_MSG.data, REG_TMP0.b1 +;we write slave register -> DIR=0 + ldi SHORT_MSG.bits_left, (8*4) +transport_layer_short_msg_dir_end: + ldi SHORT_MSG.timeout, 64 +;set para channel to busy + set H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY + qba transport_layer_send_msg_end +transport_layer_no_short_msg: +;check for new long msg + lbco ®_TMP0.b0, MASTER_REGS_CONST, PC_CTRL, 1 + qbbc transport_layer_send_msg_end, REG_TMP0.b0, 0 + clr REG_TMP0.b0, REG_TMP0.b0, 0 + sbco ®_TMP0.b0, MASTER_REGS_CONST, PC_CTRL, 1 +;set para channel to busy + set H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY +;set long msg channel to busy (reset FREL) + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 2 + clr REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL + sbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 2 +; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register + lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) + sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D+1), 1 + lbco ®_TMP1, MASTER_REGS_CONST, PC_ADD_H, 4 + mov SHORT_MSG.addr, REG_TMP1.b0 + ldi SHORT_MSG.bits_left, 16 + + +;using PC_OFF? + qbbc transport_layer_assemble_long_msg_no_pc_off, REG_TMP1.b0, LOFF + add SHORT_MSG.bits_left, SHORT_MSG.bits_left, 16 +transport_layer_assemble_long_msg_no_pc_off: +;save ADDR(+OFF) to memory buffer + + lsr REG_TMP0.b0, SHORT_MSG.bits_left, 3 + sbco ®_TMP1, MASTER_REGS_CONST, LONG_MSG_BUFFER, b0 +;skip LLEN on read operation + qbbs transport_layer_assemble_long_msg_no_llen, SHORT_MSG.addr, 6 +;get LLEN + lsr REG_TMP1.b0, REG_TMP1.b0, 2 + and REG_TMP1.b0, REG_TMP1.b0, 0x03 + qbeq transport_layer_assemble_long_msg_no_llen, REG_TMP1.b0, 0 + ldi REG_TMP1.b1, 8 + lsl REG_TMP1.b0, REG_TMP1.b1, REG_TMP1.b0;counting no. of bits length we need to send + add SHORT_MSG.bits_left, SHORT_MSG.bits_left, REG_TMP1.b0 + mov REG_TMP0.b2, REG_TMP0.b0 + lsr REG_TMP0.b0, REG_TMP1.b0, 3 + lbco ®_TMP1, MASTER_REGS_CONST, PC_BUFFER0, b0 + add REG_TMP0.b2, REG_TMP0.b2, LONG_MSG_BUFFER + ;Store the data at LONG_MSG_BUFFER+4 + sbco ®_TMP1, MASTER_REGS_CONST, REG_TMP0.b2, b0 +transport_layer_assemble_long_msg_no_llen: +;crc + add SHORT_MSG.bits_left, SHORT_MSG.bits_left, 16 +;load ptr for memory buffer + ldi SHORT_MSG.data, LONG_MSG_BUFFER + ldi SHORT_MSG.crc, 0 + + +transport_layer_send_msg_end: + +; Check for Low QM value and update event registers if required +; Check EVENT_UPDATE_PENDING_QMLW to process a low QM value event update + lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + qbbc transport_layer_no_qmlw_event, REG_TMP0.b0, EVENT_UPDATE_PENDING_QMLW +; Set EVENT_QMLW in EVENT register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + set REG_TMP0.w0, REG_TMP0.w0, EVENT_QMLW +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int3, REG_TMP0.w2, EVENT_QMLW +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int3: +; Set EVENT_S_QMLW in EVENT_S register + lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 + set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_QMLW +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + qbbc update_events_no_int16, REG_TMP0.b1, EVENT_S_QMLW +; generate interrupt_s + ldi r31.w0, PRU0_ARM_IRQ4 +update_events_no_int16: +;Clear EVENT_UPDATE_PENDING_QMLW + clr REG_TMP0.w0, REG_TMP0.w0, EVENT_UPDATE_PENDING_QMLW + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 +transport_layer_no_qmlw_event: + +; Update QMLW bits in ONLINE_STATUS registers + lbco ®_TMP0.b0, MASTER_REGS_CONST, MASTER_QM, 1 + qble transport_layer_online_status_qm_not_low, REG_TMP0.b0, 14 +; Set QMLW bits + lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW + set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW + set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW + sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + qba transport_layer_online_status_qm_update_done +transport_layer_online_status_qm_not_low: +; Clear QMLW bits + lbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 + clr REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_QMLW + clr REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_QMLW + clr REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_QMLW + sbco ®_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D, 6 +transport_layer_online_status_qm_update_done: + +; update POS bits in ONLINE_STATUS_D and EVENT + lbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 +; Check EVENT_UPDATE_PENDING_POS to process a pending POS set + lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + qbbc transport_layer_no_pos_event, REG_TMP0.b0, EVENT_UPDATE_PENDING_POS +; Clear EVENT_UPDATE_PENDING_POS + clr REG_TMP0.w0, REG_TMP0.w0, EVENT_UPDATE_PENDING_POS + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + +; Set EVENT_POS in EVENT register + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + set REG_TMP0.w0, REG_TMP0.w0, EVENT_POS +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int14, REG_TMP0.w2, EVENT_POS +; generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int14: + set REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_POS + qba transport_layer_pos_update_done +transport_layer_no_pos_event: + clr REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_D_POS +transport_layer_pos_update_done: + sbco ®_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D, 1 + jmp transport_layer_send_msg_done + +;---------------------------------------------------- +;Function: transport_on_h_frame (RET_ADDR) +;calculates the acceleration, velocity and fast position +; 38+9+52 = 99 cycles +;input: +;output: +;modifies: +;---------------------------------------------------- +;TODO: reduce processing time by 24 cycles +transport_on_h_frame: + +; Set POSTX to 0 + ldi REG_TMP0.b0, 0x0 + sbco ®_TMP0.b0, MASTER_REGS_CONST, POSTX, 1 + +;check for byte error in acceleration channel + qbbs transport_acc_err_inc, H_FRAME.flags, FLAG_ERR_ACC +;crc error verification + ;CALL1 calc_acc_crc +;5 bits CRC of acceleration channel are flipped -> flip back + xor H_FRAME.acc, H_FRAME.acc, 0x1f + ldi REG_TMP2, (LUT_CRC5+PDMEM00) + lbbo ®_TMP0.b1, REG_TMP2, H_FRAME_acc1, 1 + lsl REG_TMP0.b1, REG_TMP0.b1, 3 + xor REG_TMP0.b1, REG_TMP0.b1, H_FRAME_acc0 + lbbo ®_FNC.b0, REG_TMP2, REG_TMP0.b1, 1 + qbne transport_acc_err_inc, REG_FNC.b0, 0 +;check for special character: K29.7 is sent two times if slave error occured + ldi REG_TMP0.w0, DOUBLE_K29_7 + qbne delta_delta_position, H_FRAME.acc, REG_TMP0.w0 +transport_acc_err_inc: +;update the acc_err_cnt register + lbco ®_TMP0.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1 + add REG_TMP0.b0, REG_TMP0.b0, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1 +;reset if it is too large + lbco ®_TMP0.b1, MASTER_REGS_CONST, ACC_ERR_CNT_TRESH, 1 + qbgt transport_on_h_frame_no_reset, REG_TMP0.b0, REG_TMP0.b1 + jmp datalink_abort +transport_on_h_frame_no_reset: +;save return addr + mov REG_TMP11.w0, RET_ADDR0 + ;CALL estimator_acc; Instead of calling the API, copy the code here to save PRU cycles. +;---------------------------------------------------- +;Function: estimator_acc (RET_ADDR) +;This function estimates the FPOS and VEL +;15+15+22=52 cycles +;input: +; +;output: +; FAST_POSH, FAST_POSL, SPEED +;modifies: +; FAST_POSH, FAST_POSL, SPEED, REG_TMP1, REG_TMP0 +;---------------------------------------------------- +;Estimating the acceleration +;ith acc = (delta_a4* 1 + delta_a3 * 2 + delta_a2 * 4 + delta_a1 * 8 + delta_a0 * 16) / 32 + lsl REG_TMP0.w0, DELTA_ACC3, 1 + lsl REG_TMP0.w2, DELTA_ACC2, 2 + lsl REG_TMP1.w0, DELTA_ACC1, 3 + lsl REG_TMP1.w2, DELTA_ACC0, 4 + add REG_TMP0.w0, REG_TMP0.w0, REG_TMP0.w2 + add REG_TMP1.w0, REG_TMP1.w2, REG_TMP1.w0 + add REG_TMP0.w0, REG_TMP0.w0, REG_TMP1.w0 + add REG_TMP0.w0, REG_TMP0.w0, DELTA_ACC4 +;divide with 32 + lsr REG_TMP0.w0, REG_TMP0.w0, 5 +;sign extend delta acceleration to 16 bit -> acc size + qbbc estimator_acc_sign_extend_dacc1, REG_TMP0.w0, 10 + or REG_TMP0.b1, REG_TMP0.b1, 0xf8 +estimator_acc_sign_extend_dacc1: +; calcuate MAXACC, cap acc +;add estimated delta acc to LAST_ACC + add REG_FNC.w0, LAST_ACC, REG_TMP0.w0 +;check if estimated acc is neg. or pos. + ;CALL1 calc_speed; Instead of calling the API, copy the code here to save PRU cycles. +;sign extend acceleration to 24 bit -> speed size + xor REG_TMP0, REG_TMP0, REG_TMP0 + qbbc calc_speed_extend_acc1, REG_FNC.w0, 10 + ldi REG_TMP0.w1, 0xfff8 +calc_speed_extend_acc1: + or REG_TMP0.w0, REG_TMP0.w0, REG_FNC.w0 + add SPEED.w0, SPEED.w0, REG_TMP0.w0 + adc SPEED.b2, SPEED.b2, REG_TMP0.b2 +;updating the delta acceleration regs + mov DELTA_ACC4, DELTA_ACC3 + mov DELTA_ACC3, DELTA_ACC2 + mov DELTA_ACC2, DELTA_ACC1 + mov DELTA_ACC1, DELTA_ACC0 + sub DELTA_ACC0, REG_TMP0.w0, LAST_ACC + mov LAST_ACC, REG_TMP0.w0 + CALL1 calc_fastpos + RET +;restore return addr + mov RET_ADDR0, REG_TMP11.w0 +; Moving the event and online register update during stuffing +; Set EVENT_UPDATE_PENDING_POS to indicate a fast position data consistency error + lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + set REG_TMP0.b0, REG_TMP0.w0, EVENT_UPDATE_PENDING_POS + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1 + qba transport_on_h_frame_exit +delta_delta_position: +;reset ACC_ERR_CNT + sbco ®_FNC.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1 +;shift out crc bits + lsr REG_FNC.w0, H_FRAME.acc, 5 +; learn highest abs. acc + ;CALL1 calc_speed; Instead of calling the API, copy the code here to save PRU cycles. +;sign extend acceleration to 24 bit -> speed size + xor REG_TMP0, REG_TMP0, REG_TMP0 + qbbc calc_speed_extend_acc0, REG_FNC.w0, 10 + ldi REG_TMP0.w1, 0xfff8 +calc_speed_extend_acc0: + or REG_TMP0.w0, REG_TMP0.w0, REG_FNC.w0 + add SPEED.w0, SPEED.w0, REG_TMP0.w0 + adc SPEED.b2, SPEED.b2, REG_TMP0.b2 +;updating the delta acceleration regs + mov DELTA_ACC4, DELTA_ACC3 + mov DELTA_ACC3, DELTA_ACC2 + mov DELTA_ACC2, DELTA_ACC1 + mov DELTA_ACC1, DELTA_ACC0 + sub DELTA_ACC0, REG_TMP0.w0, LAST_ACC + mov LAST_ACC, REG_TMP0.w0 + CALL1 calc_fastpos +transport_on_h_frame_exit: +;calculate rel. pos and store + lbco ®_TMP0, MASTER_REGS_CONST, REL_POS0, 4 + add REG_TMP0.w0, REG_TMP0.w0, SPEED.w0 + adc REG_TMP0.w2, REG_TMP0.w2, SPEED.b2 + sbco ®_TMP0, MASTER_REGS_CONST, REL_POS0, 4 +;store fast pos. and velocity + mov REG_TMP0, FAST_POSH + mov REG_TMP1, SPEED + xin 160, ®_TMP0, 8 + sbco ®_TMP0, MASTER_REGS_CONST, POS4, SIZE_FAST_POS+3 +; Set POSTX to 2 + ldi REG_TMP0.b0, 0x2 + sbco ®_TMP0.b0, MASTER_REGS_CONST, POSTX, 1 +; signal event mst_intr[0] and PRU0_ARM_IRQ3 + ldi r31.w0, 32+0 + ldi r31.w0, PRU0_ARM_IRQ3 + RET + +;-------------------------------------------------------------------------------------------------- +;Function: calc_fastpos (RET_ADDR1) +;This function sign extends speed and adds it to fast position +;22 cycles +;input:SPEED, FAST_POSH, FAST_POSL +; +;output: FAST_POSH, FAST_POSL +; +;modifies:FAST_POSH, FAST_POSL +; +;-------------------------------------------------------------------------------------------------- +calc_fastpos: +;sign extend speed to NUM_POS_BITS=NUM_MT_BITS+NUM_ST_BITS and add it to FAST_POS + ldi REG_TMP1.b0, 0 + qbbc calc_fastpos_extend_vel, SPEED, 23 + ldi REG_TMP1.b0, 0xff +calc_fastpos_extend_vel: + mov REG_TMP0, SPEED + mov REG_TMP0.b3, REG_TMP1.b0 +;calculating fast position + add FAST_POSL, FAST_POSL, REG_TMP0.b0 + lsr REG_TMP0, REG_TMP0, 8 + mov REG_TMP0.b3, REG_TMP1.b0 + adc FAST_POSH, FAST_POSH, REG_TMP0 +;load mask for fast position + lbco ®_TMP1, MASTER_REGS_CONST, MASK_POS, 4 + and FAST_POSH, FAST_POSH, REG_TMP1 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: calc_speed (RET_ADDR1) +;This function sign extends acceleration and adds it to speed +;15 cycles +;input: +; SPEED +; REG_FNC.w0: acceleration +; +;output: SPEED +; +;modifies: SPEED +; +;-------------------------------------------------------------------------------------------------- +calc_speed: +;sign extend acceleration to 24 bit -> speed size + xor REG_TMP0, REG_TMP0, REG_TMP0 + qbbc calc_speed_extend_acc, REG_FNC.w0, 10 + ldi REG_TMP0.w1, 0xfff8 +calc_speed_extend_acc: + or REG_TMP0.w0, REG_TMP0.w0, REG_FNC.w0 + add SPEED.w0, SPEED.w0, REG_TMP0.w0 + adc SPEED.b2, SPEED.b2, REG_TMP0.b2 +;updating the delta acceleration regs + mov DELTA_ACC4, DELTA_ACC3 + mov DELTA_ACC3, DELTA_ACC2 + mov DELTA_ACC2, DELTA_ACC1 + mov DELTA_ACC1, DELTA_ACC0 + sub DELTA_ACC0, REG_TMP0.w0, LAST_ACC + mov LAST_ACC, REG_TMP0.w0 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: estimator_fpos (RET_ADDR1) +;This function estimates fpos when vpos and fpos mismatch +;The FAST_POS will oscillate with a small error around the SAFE_POS +; +;19 cycles +; +;input: +; REG_TMP1: vpos - last fpos +; +;output: FAST_POSH, FAST_POSL, SPEED +; +;modifies:FAST_POSH, FAST_POSL, SPEED +;NOT allowed to use REG_TMP11 +; +;-------------------------------------------------------------------------------------------------- +estimator_fpos: + add ALIGN_PH, ALIGN_PH, 1 +;pos=abspos+relpos + lbco ®_TMP0, MASTER_REGS_CONST, REL_POS0, 4 + add FAST_POSL, VERT_L.b2, REG_TMP0.b0 + adc FAST_POSH.b0, VERT_L.b3, REG_TMP0.b1 + adc FAST_POSH.w1, VERT_H.w0, REG_TMP0.w2 + adc FAST_POSH.b3, VERT_H.b2, 0 + qbne estimator_fpos_align_ph_not_2, ALIGN_PH, 2 +;vel = vel+acc/8 + qbbc estimator_fpos_acc_pos, LAST_ACC, 15 + not REG_TMP0.w0, LAST_ACC + add REG_TMP0.w0, REG_TMP0.w0, 1 + lsr REG_TMP0.w0, REG_TMP0.w0, 3 + not REG_TMP0.w0, REG_TMP0.w0 + add REG_TMP0.w0, REG_TMP0.w0, 1 + qba estimator_fpos_acc_sing_check_end +estimator_fpos_acc_pos: + lsr REG_TMP0.w0, REG_TMP0.w0, 3 +estimator_fpos_acc_sing_check_end: + add SPEED.w0, SPEED.w0, REG_TMP0.w0 + adc SPEED.b3, SPEED.b3, 0 +estimator_fpos_align_ph_not_2: + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: store_error (RET_ADDR1) +;Stores error in ring buffer +;15 cycles +;input: +; REG_FNC: error +;output: +;modifies: +;-------------------------------------------------------------------------------------------------- +store_error: +;load abs error ring buffer ptr. + ;ldi REG_TMP1, (PDMEM00+ABS_ERR_PTR) + ;xor REG_TMP0, REG_TMP0, REG_TMP0 + ;lbbo ®_TMP0, REG_TMP1, 0x00, ABS_ERR_PTR_SIZE +;store error + ;sbbo ®_FNC, REG_TMP0, 0x00, 4 +;update and store ptr + ;add REG_TMP0.w0, REG_TMP0.w0, 4 + ;ldi REG_TMP0.w2, (PDMEM00+ABS_ERR_BUF+ABS_ERR_BUF_SIZE) + ;qbgt store_error_dont_reset_abs_err_ptr, REG_TMP0.w0, REG_TMP0.w2 + ;ldi REG_TMP0.w0, (PDMEM00+ABS_ERR_BUF) +store_error_dont_reset_abs_err_ptr: + ;sbbo ®_TMP0.w0, REG_TMP1, 0x00, ABS_ERR_PTR_SIZE + ;RET1 +;-------------------------------------------------------------------------------------------------- +;Function: calc_acc_crc (RET_ADD1) +;This function checks the crc for the acceleration channel +;11 cycles +;input: +; H_frame.acc +;output: +; REG_FNC.b0: 0 indicates that crc check was successfully +;modifies: +; REG_TMP0, REG_FNC +;-------------------------------------------------------------------------------------------------- +calc_acc_crc: +;5 bits CRC of acceleration channel are flipped -> flip back + xor H_FRAME.acc, H_FRAME.acc, 0x1f + ldi REG_TMP2, (LUT_CRC5+PDMEM00) + lbbo ®_TMP0.b1, REG_TMP2, H_FRAME_acc1, 1 + lsl REG_TMP0.b1, REG_TMP0.b1, 3 + xor REG_TMP0.b1, REG_TMP0.b1, H_FRAME_acc0 + lbbo ®_FNC.b0, REG_TMP2, REG_TMP0.b1, 1 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: demp_data_symbols (RET_ADDR1) +;Demaps data symbols (5bits) and converts them to data nibbles (4bits) +;input: +; REG_FNC.b0: Number of data symbols +; r1.b1: source +; r1.b0: destination +;output: +; *r1.b0[0:REG_FNC.b0]: demapped data +;modifies: +;-------------------------------------------------------------------------------------------------- +demap_data_symbols: diff --git a/source/motor_control/position_sense/hdsl/firmware/utils.asm b/source/motor_control/position_sense/hdsl/firmware/utils.asm new file mode 100644 index 0000000..b027911 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/firmware/utils.asm @@ -0,0 +1,92 @@ + +; Copyright (C) 2021-2023 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + + .include "memory.inc" + .include "defines.inc" + .include "macros.inc" + + .sect ".text" + .global update_events + .global demp_data_symbols + .global calc_acc_crc + .global calc_16bit_crc + .global load_code + +;-------------------------------------------------------------------------------------------------- +;Function: update_events (RET_ADDR1) +;Updates event register and generates interrupts if necessary +; 9 cycles +;input: +; REG_FNC.b0: event number +;output: +;modifies: +;-------------------------------------------------------------------------------------------------- +update_events: +;read events and masks + lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 + set REG_TMP0.w0, REG_TMP0.w0, REG_FNC.b0 +;save events + sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2 + qbbc update_events_no_int, REG_TMP0.w2, REG_FNC.b0 +;generate interrupt + ldi r31.w0, PRU0_ARM_IRQ +update_events_no_int: + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: calc_16bit_crc (RET_ADD1) +;This function checks the crc for the acceleration channel (polynomial is x^5 + x^2 + 1) +;11*REG_FNC.b2+3 cycles -> 69 cycles for 6 bytes data +;input: +; REG_FNC.b0: num bytes +; r1.b0: pointer to register + 1 byte, counting down from there +;output: +; REG_FNC.w0: 16 bit CRC +;modifies: +; REG_TMP0, REG_FNC, r1 +;-------------------------------------------------------------------------------------------------- +calc_16bit_crc: + ldi REG_TMP2, (LUT_CRC16+PDMEM00) + mov REG_TMP0.b2, REG_FNC.b0 + ldi REG_FNC.w0, 0 +calc_16bit_crc_loop: + ldi REG_TMP0.w0, 0 + mvib REG_TMP0.b0, *--r1.b0 + xor REG_TMP0.b0, REG_FNC.b1, REG_TMP0.b0 + lsl REG_TMP0.w0, REG_TMP0.w0, 1 + lbbo ®_TMP0.w0, REG_TMP2, REG_TMP0.w0, 2 + lsl REG_FNC.w0, REG_FNC.w0, 8 + xor REG_FNC.w0, REG_TMP0.w0, REG_FNC.w0 + sub REG_TMP0.b2, REG_TMP0.b2, 1 + qblt calc_16bit_crc_loop, REG_TMP0.b2, 0 +;CRC_L is flipped + xor REG_FNC.b0, REG_FNC.b0, 0xff + RET1 diff --git a/source/motor_control/position_sense/hdsl/include/hdsl_drv.h b/source/motor_control/position_sense/hdsl/include/hdsl_drv.h new file mode 100644 index 0000000..1310cc0 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/include/hdsl_drv.h @@ -0,0 +1,545 @@ +/* + * Copyright (C) 2021-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef HDSL_DRV_H_ +#define HDSL_DRV_H_ + +/** + * \defgroup HDSL_API_MODULE APIs for HDSL Encoder + * \ingroup MOTOR_CONTROL_API + * + * Here is the list of APIs used for HDSL Encoder communication protocol + * + * @{ + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include +#include + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +#define MAX_WAIT 20000 + +#define HDSL_ICSSG0_INST 0U +#define HDSL_ICSSG1_INST 1U + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +/*TSR configuration:*/ + +/*inEvent value:*/ +/* ICSSG_0_EDC1_SYNC0 ICSSG0 IEP1 sync event 0 Pulse */ +#define SYNCEVENT_INTRTR_IN_27 27 + +/*outEvent values:*/ +/*SYNC0_OUT Pin Selectable timesync event 24 Edge (4+(24*4)) */ +#define SYNCEVT_RTR_SYNC28_EVT 0x64 +/* SYNC1_OUT Pin Selectable timesync event 25 Edge (4+(25*4)) */ +#define SYNCEVT_RTR_SYNC29_EVT 0x68 +/* SYNC2_OUT Pin Selectable timesync event 26 Edge (4+(26*4)) */ +#define SYNCEVT_RTR_SYNC30_EVT 0x6C +/* SYNC3_OUT Pin Selectable timesync event 27 Edge (4+(27*4)) */ +#define SYNCEVT_RTR_SYNC31_EVT 0x70 +/* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */ +#define SYNCEVT_RTR_SYNC10_EVT 0x2C + +enum { + MENU_SAFE_POSITION, + MENU_QUALITY_MONITORING, + MENU_EVENTS, + MENU_SUMMARY, + MENU_ACC_ERR_CNT, + MENU_RSSI, + MENU_PC_SHORT_MSG_WRITE, + MENU_PC_SHORT_MSG_READ, + MENU_PC_LONG_MSG_WRITE, + MENU_HDSL_REG_INTO_DDR, + MENU_HDSL_REG_INTO_DDR_GPIO, + MENU_DIRECT_READ_RID0_LENGTH8, + MENU_DIRECT_READ_RID81_LENGTH8, + MENU_DIRECT_READ_RID81_LENGTH2, + MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0, + MENU_INDIRECT_WRITE_RID0_LENGTH8, + MENU_DIRECT_READ_RID0_LENGTH8_OFFSET6, + MENU_LIMIT, + MENU_INVALID, +}; + +typedef struct HDSL_Config_s *HDSL_Handle; + +/* ========================================================================== */ +/* Structure Declarations & Definitions */ +/* ========================================================================== */ + +/** + * \anchor HDSL_Interface + * \name HDSL Master Register Interface Parameters Structure + * @{ + */ +typedef struct { + volatile uint8_t SYS_CTRL; /**< System control */ + volatile uint8_t SYNC_CTRL; /**< Synchronization control */ + volatile uint8_t resvd0; /**< Reserved 0 */ + volatile uint8_t MASTER_QM; /**< Quality monitoring */ + volatile uint8_t EVENT_H; /**< High bytes event */ + volatile uint8_t EVENT_L; /**< Low bytes event */ + volatile uint8_t MASK_H; /**< High byte event mask */ + volatile uint8_t MASK_L; /**< Low byte event mask */ + volatile uint8_t MASK_SUM; /**< Summary mask */ + volatile uint8_t EDGES; /**< Cable bit sampling time control */ + volatile uint8_t DELAY; /**< Run time delay of system cable and signal strength */ + volatile uint8_t VERSION; /**< Version */ + volatile uint8_t resvd1; /**< Reserved 1 */ + volatile uint8_t ENC_ID2; /**< Encoder ID, byte 2 */ + volatile uint8_t ENC_ID1; /**< Encoder ID, byte 1 */ + volatile uint8_t ENC_ID0; /**< Encoder ID, byte 0 */ + volatile uint8_t POS4; /**< Fast position, byte 4 */ + volatile uint8_t POS3; /**< Fast position, byte 3 */ + volatile uint8_t POS2; /**< Fast position, byte 2 */ + volatile uint8_t POS1; /**< Fast position, byte 1 */ + volatile uint8_t POS0; /**< Fast position, byte 0 */ + volatile uint8_t VEL2; /**< Speed, byte 2 */ + volatile uint8_t VEL1; /**< Speed, byte 1 */ + volatile uint8_t VEL0; /**< Speed, byte 0 */ + volatile uint8_t resvd2; /**< Reserved 2 */ + volatile uint8_t VPOS4; /**< Safe position, byte 4 */ + volatile uint8_t VPOS3; /**< Safe position, byte 3 */ + volatile uint8_t VPOS2; /**< Safe position, byte 2 */ + volatile uint8_t VPOS1; /**< Safe position, byte 1 */ + volatile uint8_t VPOS0; /**< Safe position, byte 0 */ + volatile uint8_t VPOSCRC_H; /**< CRC of Safe position, byte 1 */ + volatile uint8_t VPOSCRC_L; /**< CRC of Safe position, byte 0 */ + volatile uint8_t PC_BUFFER0; /**< Parameters channel buffer, byte 0 */ + volatile uint8_t PC_BUFFER1; /**< Parameters channel buffer, byte 1 */ + volatile uint8_t PC_BUFFER2; /**< Parameters channel buffer, byte 2 */ + volatile uint8_t PC_BUFFER3; /**< Parameters channel buffer, byte 3 */ + volatile uint8_t PC_BUFFER4; /**< Parameters channel buffer, byte 4 */ + volatile uint8_t PC_BUFFER5; /**< Parameters channel buffer, byte 5 */ + volatile uint8_t PC_BUFFER6; /**< Parameters channel buffer, byte 6 */ + volatile uint8_t PC_BUFFER7; /**< Parameters channel buffer, byte 7 */ + volatile uint8_t PC_ADD_H; /**< Long message address, byte 1 */ + volatile uint8_t PC_ADD_L; /**< Long message address, byte 0 */ + volatile uint8_t PC_OFF_H; /**< Long message address offset, byte 1 */ + volatile uint8_t PC_OFF_L; /**< Long message address offset, byte 0 */ + volatile uint8_t PC_CTRL; /**< Parameters channel control */ + volatile uint8_t PIPE_S; /**< Sensor hub channel status */ + volatile uint8_t PIPE_D; /**< Sensor hub channel data */ + volatile uint8_t PC_DATA; /**< Short message parameters channel data */ + volatile uint8_t resvd3; /**< Reserved 3 */ + volatile uint8_t resvd4; /**< Reserved 4 */ + volatile uint8_t resvd5; /**< Reserved 5 */ + volatile uint8_t resvd6; /**< Reserved 6 */ + volatile uint8_t resvd7; /**< Reserved 7 */ + volatile uint8_t resvd8; /**< Reserved 8 */ + volatile uint8_t SAFE_SUM; /**< Summarized slave status */ + volatile uint8_t S_PC_DATA; /**< Response of Short message parameters channel Read for safe1 channel */ + volatile uint8_t ACC_ERR_CNT; /**< Fast position error counter */ + volatile uint8_t MAXACC; /**< Fast position acceleration boundary */ + volatile uint8_t MAXDEV_H; /**< Fast position estimator deviation high byte */ + volatile uint8_t MAXDEV_L; /**< Fast position estimator deviation low byte */ + volatile uint8_t resvd9; /**< Reserved 9 */ + volatile uint8_t EVENT_S; /**< Safe Events */ + volatile uint8_t resvd10; /**< Reserved 10 */ + volatile uint8_t DUMMY; /**< Dummy, no data */ + volatile uint8_t SLAVE_REG_CTRL; /**< Short message control */ + volatile uint8_t ACC_ERR_CNT_THRES; /**< Fast position error counter threshold */ + volatile uint8_t MAXDEV_H_THRES; /**< Fast position estimator deviation high byte threshold */ + volatile uint8_t MAXDEV_L_THRES; /**< Fast position estimator deviation low byte threshold */ + /*Safe 2 Interface */ + volatile uint8_t version; + volatile uint8_t ENC2_ID; + volatile uint8_t STATUS2; + volatile uint8_t VPOS24; + volatile uint8_t VPOS23; + volatile uint8_t VPOS22; + volatile uint8_t VPOS21; + volatile uint8_t VPOS20; + volatile uint8_t VPOSCRC2_H; + volatile uint8_t VPOSCRC2_L; + volatile uint8_t DUMMY2; + /* Online Status*/ + volatile uint16_t ONLINE_STATUS_D; + volatile uint16_t ONLINE_STATUS_1; + volatile uint16_t ONLINE_STATUS_2; +} HDSL_Interface; +/** @} */ + +/** + * \anchor HDSL_Config + * \name HDSL Config Parameters Structure + * @{ + */ +typedef struct HDSL_Config_s { + PRUICSS_Handle icssgHandle; + /**< PRUICSS_Handle for icssg0 or icssg1 instance*/ + uint32_t icssCore; + /**< PRUICSS core identifier + * Check #PRUICSS_PRU0 and check other available macros + */ + uint32_t *baseMemAddr; // icssgHandle->hwAttrs->baseAddr + PRUICSS_DATARAM(PRUICSS_PRUx) + /**< Base Memory Address for HDSL channel configuration */ + HDSL_Interface *hdslInterface; + /**< HDSL master memory interface structure */ + uint32_t multi_turn; + /**< HDSL ----- */ + uint32_t res; + /**< HDSL ----- */ + uint64_t mask; + /**< HDSL ----- */ + + // intc_initdata // ** - needs to be common for all channels and fixed (configure for all 3 channels in starting) + +} HDSL_Config; +/** @} */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ +/** + * \brief enable load share mode for multi-channel HDSL + * + * \param[in] gPru_cfg Cfg base register address + * \param[in] PRU_SLICE PRU slice, 1 for PRU1 and 0 for PRU0 + * + */ +void hdsl_enable_load_share_mode(void *gPru_cfg ,uint32_t PRU_SLICE); +/** + * \brief Open HDSL handle for the specified core + * (interrupt mapping should already be completed) + * + * \param[in] icssgHandle #PRUICSS_Handle for the ICSS instance + * \param[in] icssCore Core to map in ICSSG instance + * \param[in] PRU_mode 0 for dissabled load share mode, 1 for enabled load share mode + * \retval HDSL_Handle + * + */ +// HDSL_ICSSG0_INST, HDSL_ICSSG1_INST +HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore,uint8_t PRU_mode); + +/** + * \brief Initialize IEP and Use OCP as IEP CLK src + * + * \param[in] hdslHandle + * + */ +void HDSL_iep_init(HDSL_Handle hdslHandle); + +/** + * \brief Enable IEP
+ * *Enable SYNC0 and program pulse width
+ * Enable cyclic mod
+ * Program CMP1
+ * TSR configuration
+ * + * \param[in] ES + * \param[in] period + * \retval 1 for successful enable sync signal + * + */ +int HDSL_enable_sync_signal(uint8_t ES, uint32_t period); + +/** + * \brief Calculate fast position,safe position1,safe position2 + * + * \param[in] hdslHandle + * \param[in] position_id + * \retval position value in integer for successful position return, -1 for error in position return + * + */ +uint64_t HDSL_get_pos(HDSL_Handle hdslHandle, int position_id); + +/** + * \brief Getting quality monitoring value + * + * \param[in] hdslHandle + * \retval 8 bit integer QM value + */ +uint8_t HDSL_get_qm(HDSL_Handle hdslHandle); + +/** +* \brief Taking values of High bytes event (EVENT_H) and Low bytes event(EVENT_L) + * + * \param[in] hdslHandle + * \retval 16 bit integer concatenated values of both EVENT_H,EVENT_L + * + */ +uint16_t HDSL_get_events(HDSL_Handle hdslHandle); + +/** +* \brief Taking values of Safe Event (EVENT_S) register + * + * \param[in] hdslHandle + + * \retval 8 bit integer values of EVENT_S + * + */ +uint8_t HDSL_get_safe_events(HDSL_Handle hdslHandle); + + +/** +* \brief Taking values of Online Status D (ONLINE_STATUS_D) register + * + * \param[in] hdslHandle + + * \retval 16 bit integer value of ONLINE_STATUS_D + * + */ +uint16_t HDSL_get_online_status_d(HDSL_Handle hdslHandle); + +/** +* \brief Taking values of Online Status D (ONLINE_STATUS_D) register + * + * \param[in] hdslHandle + + * \retval 16 bit integer value of ONLINE_STATUS_D + * + */ +uint16_t HDSL_get_online_status_1(HDSL_Handle hdslHandle); + +/** +* \brief Taking values of Online Status D (ONLINE_STATUS_D) register + * + * \param[in] hdslHandle + + * \retval 16 bit integer value of ONLINE_STATUS_D + * + */ +uint16_t HDSL_get_online_status_2(HDSL_Handle hdslHandle); + +/** +* \brief Getting Summarized slave status + * + * \param[in] hdslHandle + * \retval 8 bit integer value of summarized status + * + */ +uint8_t HDSL_get_sum(HDSL_Handle hdslHandle); + +/** + * \brief Acceleration error counter + * + * \param[in] hdslHandle + * \retval 8 bit integer value of acceleration error counter + * + */ +uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle); + +/** +* \brief Read RSSI value + * + * \param[in] hdslHandle + * \retval 8 bit RSSI integer value + * + */ +uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle); + +/** + * \brief Write Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) with gPc_data and Short message control value(SLAVE_REG_CTRL) in hdsl interface + * + * \param[in] hdslHandle + * \param[in] addr Address + * \param[in] data Data + * \param[in] timeout Timeout in microseconds + * + * \return #SystemP_SUCCESS in case of success, #SystemP_TIMEOUT in case of timeout + * + */ +int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t data, uint64_t timeout); + +/** + * \brief Read Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) and write Short message control value(SLAVE_REG_CTRL) with gPc_addr in hdsl interface + * + * \param[in] hdslHandle + * \param[in] addr Address + * \param[in] data Pointer to data buffer where read data will be stored + * \param[in] timeout Timeout in microseconds + * + * \return #SystemP_SUCCESS in case of success, #SystemP_TIMEOUT in case of timeout + * + */ +int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *data, uint64_t timeout); + +/** + * \brief Write PC_AAD_L ,PC_ADD_H ,PC_OFF_L,PC_OFF_H and PC_CTRL values in hdsl interface + * + * \param[in] hdslHandle + * \param[in] pc_addrh + * \param[in] pc_addrl + * \param[in] pc_offh + * \param[in] pc_offl + * + */ +void HDSL_set_pc_addr(HDSL_Handle hdslHandle, uint8_t pc_addrh, uint8_t pc_addrl, uint8_t pc_offh, uint8_t pc_offl); + +/** + * \brief To set the direction read/write for long message communication + * + * \param[in] hdslHandle + * \param[in] value + * + */ +void HDSL_set_pc_ctrl(HDSL_Handle hdslHandle, uint8_t value); + +/** + * \brief Write Parameters channel buffer for different bytes(bytes 0-7) + * + * \param[in] hdslHandle + * \param[in] pc_buf0 + * \param[in] pc_buf1 + * \param[in] pc_buf2 + * \param[in] pc_buf3 + * \param[in] pc_buf4 + * \param[in] pc_buf5 + * \param[in] pc_buf6 + * \param[in] pc_buf7 + * + */ +void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t pc_buf0, uint8_t pc_buf1, uint8_t pc_buf2, uint8_t pc_buf3, uint8_t pc_buf4, uint8_t pc_buf5, uint8_t pc_buf6, uint8_t pc_buf7); + +/** + * \brief Returns Parameters channel buffer for different bytes(bytes 0-7) + * + * \param[in] hdslHandle + * \param[in] buff_off + * \retval 8 bit integer value of PC_BUFFER from hdsl interface + * + */ +uint8_t HDSL_read_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off); + +/** + * \brief Returns Synchronization control value + * + * \param[in] hdslHandle + * \retval 8 bit integer value of SYNC_CTRL from hdsl interface + * + */ + +uint8_t HDSL_get_sync_ctrl(HDSL_Handle hdslHandle); + +/** + * \brief Writes Synchronization control value + * + * \param[in] hdslHandle + * \param[in] val + * + */ +void HDSL_set_sync_ctrl(HDSL_Handle hdslHandle, uint8_t val); + +/** + * \brief Returns Quality monitoring value + * + * \param[in] hdslHandle + * \retval 8 bit integer value of MASTER_QM from hdsl interface + * + */ +uint8_t HDSL_get_master_qm(HDSL_Handle hdslHandle); + +/** + * \brief Returns Cable bit sampling time control + * + * \param[in] hdslHandle + * \retval 8 bit integer value of EDGES from hdsl interface + * + */ +uint8_t HDSL_get_edges(HDSL_Handle hdslHandle); + +/** + * \brief Returns Run time delay of system cable and signal strength + * + * \param[in] hdslHandle + * \retval 8 bit integer value of DELAY from hdsl interface + * + */ +uint8_t HDSL_get_delay(HDSL_Handle hdslHandle); + +/** + * \brief Read encoder id bytes(byte no. 0-2) + * + * \param[in] hdslHandle + * \param[in] byte + * \retval 8 bit encoder bytes data from hdsl interface + * + */ +uint8_t HDSL_get_enc_id(HDSL_Handle hdslHandle, int byte); + +/** + * \brief Generates memory image + * + * \param[in] hdslHandle + * + */ +void HDSL_generate_memory_image(HDSL_Handle hdslHandle); + +/** + * \brief Get memory location for HDSL interface struct + * + * \param[in] hdslHandle + * \retval Pointer containing base memeory address + * + */ +void* HDSL_get_src_loc(HDSL_Handle hdslHandle); + +/** + * \brief Get size of memory used by HDSL interface struct + * + * \param[in] hdslHandle + * \retval Size of the struct + * + */ +uint32_t HDSL_get_length(HDSL_Handle hdslHandle); + +#ifdef __cplusplus +} +#endif + +/** @} */ +#endif diff --git a/source/motor_control/position_sense/hdsl/include/pruss_intc_mapping.h b/source/motor_control/position_sense/hdsl/include/pruss_intc_mapping.h new file mode 100644 index 0000000..dda9142 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/include/pruss_intc_mapping.h @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2021-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PRUSS_INTC_MAPPING_H_ +#define PRUSS_INTC_MAPPING_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ICSS1_PRUSS0_HOST_INTR5 56 + +/* ICSS0 event map */ +#define HIPERFACE_EVENT0 16 +#define HIPERFACE_EVENT1 18 +#define HIPERFACE_EVENT2 19 +#define HIPERFACE_EVENT3 20 +#define HIPERFACE_EVENT4 21 + +#define HDSL_APP_CHANNEL0 0 +#define HDSL_APP_CHANNEL1 1 +#define HDSL_APP_CHANNEL2 2 +#define HDSL_APP_CHANNEL3 3 +#define HDSL_APP_CHANNEL4 4 +#define HDSL_APP_CHANNEL5 5 +#define HDSL_APP_CHANNEL6 6 +#define HDSL_APP_CHANNEL7 7 +#define HDSL_APP_CHANNEL8 8 +#define HDSL_APP_CHANNEL9 9 + +#define PRU_EVTOUT0 2 +#define PRU_EVTOUT3 5 +#define PRU_EVTOUT5 7 +#define PRU_EVTOUT6 8 + +#define PRU_EVTOUT5_HOSTEN_MASK 0x003C +#define PRU_EVTOUT6_HOSTEN_MASK 0x0100 + +#define SYS_EVT_POLARITY_HIGH 1 + +#define SYS_EVT_TYPE_EDGE 1 +#define SYS_EVT_TYPE_LEVEL 0 + +/* ICSS0 / ICSS_L */ +/* Is HDSL_APP_CHANNEL0->PRU0 & HDSL_APP_CHANNEL1->PRU1 reqd ?, seems not reqd */ +#define PRU_ICSS0_INTC_INITDATA { \ + { HIPERFACE_EVENT0, HIPERFACE_EVENT2, HIPERFACE_EVENT3, HIPERFACE_EVENT4, 0xFF }, \ + { \ + {HIPERFACE_EVENT0, HDSL_APP_CHANNEL2, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_LEVEL}, \ + {HIPERFACE_EVENT2, HDSL_APP_CHANNEL3, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_LEVEL}, \ + {HIPERFACE_EVENT3, HDSL_APP_CHANNEL4, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_LEVEL}, \ + {HIPERFACE_EVENT4, HDSL_APP_CHANNEL5, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_LEVEL}, \ + {0xFF, 0xFF, 0xFF, 0xFF }, \ + }, \ + { \ + {HDSL_APP_CHANNEL2, PRU_EVTOUT0}, \ + {HDSL_APP_CHANNEL3, HDSL_APP_CHANNEL3}, \ + {HDSL_APP_CHANNEL4, HDSL_APP_CHANNEL4}, \ + {HDSL_APP_CHANNEL5, PRU_EVTOUT3},\ + {0xFF,0xFF} \ + }, \ + PRU_EVTOUT5_HOSTEN_MASK } + +/* Is HDSL_APP_CHANNEL0->PRU0 & HDSL_APP_CHANNEL1->PRU1 reqd ?, seems not reqd */ +#define PRU_ICSS1_INTC_INITDATA { \ + { ICSS1_PRUSS0_HOST_INTR5, 0xFF },\ + { \ + {ICSS1_PRUSS0_HOST_INTR5, HDSL_APP_CHANNEL8,SYS_EVT_POLARITY_HIGH ,SYS_EVT_TYPE_EDGE }, \ + {0xFF,0xFF,0xFF,0xFF} \ + }, \ + { \ + {HDSL_APP_CHANNEL8, PRU_EVTOUT6}, \ + {0xFF,0xFF} \ + }, \ + PRU_EVTOUT6_HOSTEN_MASK } + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/motor_control/position_sense/hdsl/makefile.am243x.r5f.ti-arm-clang b/source/motor_control/position_sense/hdsl/makefile.am243x.r5f.ti-arm-clang new file mode 100644 index 0000000..fd25ad9 --- /dev/null +++ b/source/motor_control/position_sense/hdsl/makefile.am243x.r5f.ti-arm-clang @@ -0,0 +1,120 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang +AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar + +PROFILE?=release +ConfigName:=$(PROFILE) + +LIBNAME:=motorcontrol_hdsl.am243x.r5f.ti-arm-clang.$(PROFILE).lib + +FILES_common := \ + hdsl_drv.c \ + hdsl_lut.c \ + +FILES_PATH_common = \ + driver \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -Iinclude \ + +DEFINES_common := \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +ARFLAGS_common := \ + rc \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ifeq ($(CPLUSPLUS_BUILD), yes) +CFLAGS += $(CFLAGS_cpp_common) +endif +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE)) + +LIBDIR := lib +OBJDIR := obj/am243x/ti-arm-clang/$(PROFILE)/r5f/motorcontrol_hdsl/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $< + +all: $(LIBDIR)/$(LIBNAME) + +$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR) + @echo . + @echo Archiving: $(LIBNAME) to $@ ... + $(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS)) + @echo Archiving: $(LIBNAME) Done !!! + @echo . + +clean: + @echo Cleaning: $(LIBNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(LIBDIR)/$(LIBNAME) + +scrub: + @echo Scrubing: $(LIBNAME) ... + -$(RMDIR) obj/ + -$(RMDIR) lib/ + +$(OBJS): | $(OBJDIR) + +$(LIBDIR) $(OBJDIR): + $(MKDIR) $@ + +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/source/motor_control/position_sense/hdsl/makefile.am64x.r5f.ti-arm-clang b/source/motor_control/position_sense/hdsl/makefile.am64x.r5f.ti-arm-clang new file mode 100644 index 0000000..51e7b6a --- /dev/null +++ b/source/motor_control/position_sense/hdsl/makefile.am64x.r5f.ti-arm-clang @@ -0,0 +1,120 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang +AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar + +PROFILE?=release +ConfigName:=$(PROFILE) + +LIBNAME:=motorcontrol_hdsl.am64x.r5f.ti-arm-clang.$(PROFILE).lib + +FILES_common := \ + hdsl_drv.c \ + hdsl_lut.c \ + +FILES_PATH_common = \ + driver \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -Iinclude \ + +DEFINES_common := \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +ARFLAGS_common := \ + rc \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ifeq ($(CPLUSPLUS_BUILD), yes) +CFLAGS += $(CFLAGS_cpp_common) +endif +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE)) + +LIBDIR := lib +OBJDIR := obj/am64x/ti-arm-clang/$(PROFILE)/r5f/motorcontrol_hdsl/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $< + +all: $(LIBDIR)/$(LIBNAME) + +$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR) + @echo . + @echo Archiving: $(LIBNAME) to $@ ... + $(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS)) + @echo Archiving: $(LIBNAME) Done !!! + @echo . + +clean: + @echo Cleaning: $(LIBNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(LIBDIR)/$(LIBNAME) + +scrub: + @echo Scrubing: $(LIBNAME) ... + -$(RMDIR) obj/ + -$(RMDIR) lib/ + +$(OBJS): | $(OBJDIR) + +$(LIBDIR) $(OBJDIR): + $(MKDIR) $@ + +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/source/motor_control/position_sense/tamagawa/.project/project.js b/source/motor_control/position_sense/tamagawa/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/tamagawa/.project/project_am243x.js b/source/motor_control/position_sense/tamagawa/.project/project_am243x.js new file mode 100644 index 0000000..ee9372e --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/.project/project_am243x.js @@ -0,0 +1,53 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "tamagawa_drv.c", + ], +}; + +const filedirs = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/driver", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/include", + ], +}; + +const buildOptionCombos = [ + { device: device, cpu: "r5f", cgt: "ti-arm-clang"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "library"; + property.name = "motorcontrol_tamagawa"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.projecspecFileAction = "link"; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/tamagawa/.project/project_am64x.js b/source/motor_control/position_sense/tamagawa/.project/project_am64x.js new file mode 100644 index 0000000..a1747af --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/.project/project_am64x.js @@ -0,0 +1,52 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "tamagawa_drv.c", + ], +}; + +const filedirs = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/driver", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/include", + ], +}; + +const buildOptionCombos = [ + { device: device, cpu: "r5f", cgt: "ti-arm-clang"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "library"; + property.name = "motorcontrol_tamagawa"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/tamagawa/driver/tamagawa_drv.c b/source/motor_control/position_sense/tamagawa/driver/tamagawa_drv.c new file mode 100644 index 0000000..fd2bb35 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/driver/tamagawa_drv.c @@ -0,0 +1,621 @@ +/* + * Copyright (C) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +static struct tamagawa_priv tamagawa_priv; + +int32_t tamagawa_parse(int32_t cmd, struct tamagawa_priv *priv) +{ + /* Parses the data in tamagawa interface received from the Encoder*/ + uint32_t word0, word1, word2; + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + + word0 = tamagawa_xchg->ch[priv->channel].pos_word0; + word1 = tamagawa_xchg->ch[priv->channel].pos_word1; + word2 = tamagawa_xchg->ch[priv->channel].pos_word2; + + switch(cmd) + { + case DATA_ID_0: + /* Data readout: data in one revolution */ + /* Data frames: cf(8 bits) + sf(8 bits) + abs(3 frames with 8 bits data each) + crc(8 bits) */ + tamagawa_xchg->tamagawa_interface.rx_frames_received.cf = (word0>>24) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.sf = (word0>>16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.abs = ((word0>>8)& 0xFF) | ((word0)& 0xFF)<<8 | (((word1>>8) & 0xFF) << 16); + tamagawa_xchg->tamagawa_interface.rx_frames_received.crc = (word1) & 0xFF; + tamagawa_xchg->ch[priv->channel].pos_word1=word1<<16; + break; + + case DATA_ID_1: + /* Data readout: multi-turn data */ + /* Data frames: cf(8 bits) + sf(8 bits) + abm(3 frames with 8 bits data each) + crc(8 bits) */ + tamagawa_xchg->tamagawa_interface.rx_frames_received.cf =(word0>>24) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.sf =(word0>>16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.abm = ((word0>>8)& 0xFF) | ((word0)& 0xFF)<<8 | (((word1>>8) & 0xFF) << 16); + tamagawa_xchg->tamagawa_interface.rx_frames_received.crc =(word1) & 0xFF; + tamagawa_xchg->ch[priv->channel].pos_word1=word1<<16; + break; + + case DATA_ID_2: + /* Data readout: encoder ID */ + /* Data frames: cf(8 bits) + sf(8 bits) + enid(8 bits)+ crc(8 bits) */ + tamagawa_xchg->tamagawa_interface.rx_frames_received.cf = (word0>>24) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.sf = (word0>>16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.enid = (word0>>8)& 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.crc = (word0)& 0xFF; + break; + + case DATA_ID_3: + /* Data readout: data in one revolution, encoder ID, multi-turn, encoder error */ + /* Data frames: cf(8 bits) + sf(8 bits) + abs(3 frames with 8 bits data each) + enid(8 bits) + abm(3 frames with 8 bits data each) + almc(8 bits) + crc(8 bits) */ + tamagawa_xchg->tamagawa_interface.rx_frames_received.cf = (word0>>24) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.sf = (word0>>16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.abs = ((word0>>8)& 0xFF) | ((word0)& 0xFF)<<8 | (((word1>>24) & 0xFF) << 16); + tamagawa_xchg->tamagawa_interface.rx_frames_received.enid =(word1 >> 16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.abm = ((word1>>8)& 0xFF) | ((word1)& 0xFF)<<8 | (((word2>>16) & 0xFF) << 16); + tamagawa_xchg->tamagawa_interface.rx_frames_received.almc =(word2 >> 8) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.crc = (word2) & 0xFF; + tamagawa_xchg->ch[priv->channel].pos_word2=word2<<8; + break; + + case DATA_ID_7: + /* Reset */ + /* Data frames: cf(8 bits) + sf(8 bits) + abs(3 frames with 8 bits data each) + crc(8 bits) */ + tamagawa_xchg->tamagawa_interface.rx_frames_received.cf = (word0>>24) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.sf = (word0>>16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.abs = ((word0>>8)& 0xFF) | ((word0)& 0xFF)<<8 | (((word1>>8) & 0xFF) << 16); + tamagawa_xchg->tamagawa_interface.rx_frames_received.crc = (word1) & 0xFF; + tamagawa_xchg->ch[priv->channel].pos_word1=word1<<16; + break; + + case DATA_ID_8: + /* Reset */ + /* Data frames: cf(8 bits) + sf(8 bits) + abs(3 frames with 8 bits data each) + crc(8 bits) */ + tamagawa_xchg->tamagawa_interface.rx_frames_received.cf = (word0>>24) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.sf = (word0>>16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.abs = ((word0>>8)& 0xFF) | ((word0)& 0xFF)<<8 | (((word1>>8) & 0xFF) << 16); + tamagawa_xchg->tamagawa_interface.rx_frames_received.crc = (word1) & 0xFF; + tamagawa_xchg->ch[priv->channel].pos_word1=word1<<16; + break; + + case DATA_ID_C: + /* Reset */ + /* Data frames: cf(8 bits) + sf(8 bits) + abs(3 frames with 8 bits data each) + crc(8 bits) */ + tamagawa_xchg->tamagawa_interface.rx_frames_received.cf = (word0>>24) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.sf = (word0>>16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.abs = ((word0>>8)& 0xFF) | ((word0)& 0xFF)<<8 | (((word1>>8) & 0xFF) << 16); + tamagawa_xchg->tamagawa_interface.rx_frames_received.crc = (word1) & 0xFF; + tamagawa_xchg->ch[priv->channel].pos_word1=word1<<16; + break; + + case DATA_ID_6: + /* EEPROM Write */ + /* Data frames: cf(1frame) + adf(8 bits) + edf(8 bits) + crc(8 bits) */ + tamagawa_xchg->tamagawa_interface.rx_frames_received.cf = (word0>>24) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.adf = (word0>>16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.edf =(word0>>8)& 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.crc = (word0)& 0xFF; + break; + + case DATA_ID_D: + /* EEPROM Read */ + /* Data frames: cf(1frame) + adf(8 bits) + edf(8 bits) + crc(8 bits) */ + tamagawa_xchg->tamagawa_interface.rx_frames_received.cf = (word0>>24) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.adf = (word0>>16) & 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.edf =(word0>>8)& 0xFF; + tamagawa_xchg->tamagawa_interface.rx_frames_received.crc = (word0)& 0xFF; + break; + + default: + return -1; + } + + return 0; +} + +static uint8_t tamagawa_crc(struct tamagawa_priv *priv, uint8_t len, uint32_t ch) +{ + /* Calculates the CRC for the currently selected channel. Uses the CRC function (X^8+1) */ + uint8_t crc = 0; + uint8_t val; + uint32_t i, j; + uint32_t word0, word1, word2; + + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + + word0 = tamagawa_xchg->tamagawa_eeprom_interface[ch].word0; + word1 = tamagawa_xchg->tamagawa_eeprom_interface[ch].word1; + word2 = tamagawa_xchg->tamagawa_eeprom_interface[ch].word2; + + /* In EEPROM Write, we have CF, ADF and EDF fields as bits 24-31, 16-23 and 8-15 respectively */ + /* In EEPROM Write, we have CF and ADF fields as bits 24-31 and 16-23 respectively */ + /* Size of the array is 12 in order to use 12 8 bit integers for different frames */ + uint8_t data[12]; + data[3]=word0 & 0xFF; + data[2]=(word0 >> 8) & 0xFF; + data[1]=(word0 >> 16) & 0xFF; + data[0]=(word0 >> 24) & 0xFF; + + data[7]=word1 & 0xFF; + data[6]=(word1 >> 8) & 0xFF; + data[5]=(word1 >> 16) & 0xFF; + data[4]=(word1 >> 24) & 0xFF; + + data[11]=word2 & 0xFF; + data[10]=(word2 >> 8) & 0xFF; + data[9]=(word2 >> 16) & 0xFF; + data[8]=(word2 >> 24) & 0xFF; + + + for(i = 0; i < len; i++) + { + for(j = 0; j < 8; j++) + { + val = (data[i] >> 7) ^ (crc >> 7); + crc <<= 1; + data[i] <<= 1; + crc |= val; + } + } + + return crc; +} + +void tamagawa_update_crc(struct tamagawa_priv *priv, int32_t cmd, uint32_t ch) +{ + /* Passes the values of CF(Control Field), ADF(address of EEPROM) and EDF(data for EEPROM) to the CRC calculator fucntion and update the CRC field */ + uint32_t word0; + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + tamagawa_eeprom_crc_reinit(priv); + word0 = tamagawa_xchg->tamagawa_eeprom_interface[ch].word0; + + if (cmd == DATA_ID_6) + { + /* Bitwise OR the 32 bit integer with the CF, ADF and EDF values left shifted 24, 16 and 8 times respectively, in order to get the correct sequence of bits for CRC calculation*/ + word0 = (word0|0x32)<<24; + word0 = word0 | (tamagawa_xchg->tamagawa_eeprom_interface[ch].adf<<16); + word0 = word0 | (tamagawa_xchg->tamagawa_eeprom_interface[ch].edf<<8); + tamagawa_xchg->tamagawa_eeprom_interface[ch].word0 = word0; + tamagawa_xchg->tamagawa_eeprom_interface[ch].crc = tamagawa_crc(priv, 3, ch); + } + else + { + /* Bitwise OR the 32 bit integer with the CF and ADF values left shifted 24 and 16 times respectively, in order to get the correct sequence of bits for CRC calculation*/ + word0 = (word0|0xEA)<<24; + word0 = word0 | (tamagawa_xchg->tamagawa_eeprom_interface[ch].adf<<16); + tamagawa_xchg->tamagawa_eeprom_interface[ch].word0 = word0; + tamagawa_xchg->tamagawa_eeprom_interface[ch].crc = tamagawa_crc(priv, 2, ch); + } + + tamagawa_eeprom_crc_reinit(priv); +} + +int32_t tamagawa_crc_verify(struct tamagawa_priv *priv) +{ + /* Verifies the CRC computed with the encoder crc */ + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + uint32_t word0; + word0 = tamagawa_xchg->ch[priv->channel].cal_crc; + + if ((word0 & 0xFF)==1) + { + return 1; + } + else + { + return -1; + } +} + +void tamagawa_set_baudrate(struct tamagawa_priv *priv, double baudrate) +{ + /* Updates the values for oversample rate and division factor for Tx and Rx based on the baud rate selected */ + if (baudrate==2.5) + { + /* For 2.5 Mbps, Rx Divide factor is 10, Tx Divide factor is 80 and Oversampling rate is 8 */ + priv->tamagawa_xchg->tamagawa_interface.rx_div_factor= 9; + priv->tamagawa_xchg->tamagawa_interface.tx_div_factor= 79; + priv->tamagawa_xchg->tamagawa_interface.oversample_rate= 7; + } + if(baudrate==5) + { + /* For 5 Mbps, Rx Divide factor is 5, Tx Divide factor is 40 and Oversampling rate is 8 */ + priv->tamagawa_xchg->tamagawa_interface.rx_div_factor= 4; + priv->tamagawa_xchg->tamagawa_interface.tx_div_factor= 39; + priv->tamagawa_xchg->tamagawa_interface.oversample_rate= 7; + } +} + +int32_t tamagawa_command_build(struct tamagawa_priv *priv, int32_t cmd, uint8_t gTamagawa_multi_ch_mask) +{ + /* Sets up the tamagawa command in the PRU interface buffer */ + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + + /*first clear command parameters to be safe */ + memset(&tamagawa_xchg->cmd, 0, sizeof(tamagawa_xchg->cmd)); + uint32_t ch; + switch(cmd) + { + case DATA_ID_0: + /* Data readout: data in one revolution */ + /* After reversing the Control Field and adding the start and stop bits, update the Tx data such that it can be loaded byte-wise */ + tamagawa_xchg->cmd.word0 = (0x20)|(0x40<<8); + /* Number of expected Rx frames is 6 */ + tamagawa_xchg->tamagawa_interface.rx_frames = 6; + /* Number of Tx frames being sent to the encoder is 1, and the number of Rx frames to be received is 6 */ + tamagawa_xchg->cmd.word1 = (1)|(6<<8); + break; + + case DATA_ID_1: + /* Data readout: multi-turn data */ + /* After reversing the Control Field and adding the start and stop bits, update the Tx data such that it can be loaded byte-wise */ + tamagawa_xchg->cmd.word0 = (0x28)|(0xC0<<8); + /* Number of expected Rx frames is 6 */ + tamagawa_xchg->tamagawa_interface.rx_frames = 6; + /* Number of Tx frames being sent to the encoder is 1, and the number of Rx frames to be received is 6 */ + tamagawa_xchg->cmd.word1 = (1)|(6<<8); + break; + + case DATA_ID_2: + /* Data readout: encoder ID */ + /* After reversing the Control Field and adding the start and stop bits, update the Tx data such that it can be loaded byte-wise */ + tamagawa_xchg->cmd.word0 = (0x24)|(0xC0<<8); + /* Number of expected Rx frames is 4 */ + tamagawa_xchg->tamagawa_interface.rx_frames = 4; + /* Number of Tx frames being sent to the encoder is 1, and the number of Rx frames to be received is 4 */ + tamagawa_xchg->cmd.word1 = (1)|(4<<8); + break; + + case DATA_ID_3: + /* Data readout: data in one revolution, encoder ID, multi-turn, encoder error */ + /* After reversing the Control Field and adding the start and stop bits, update the Tx data such that it can be loaded byte-wise */ + tamagawa_xchg->cmd.word0 = (0x2C)|(0x40<<8); + /* Number of expected Rx frames is 11 */ + tamagawa_xchg->tamagawa_interface.rx_frames = 11; + /* Number of Tx frames being sent to the encoder is 1, and the number of Rx frames to be received is 11 */ + tamagawa_xchg->cmd.word1 = (1)|(0xB<<8); + break; + + case DATA_ID_7: + /* Reset */ + /* After reversing the Control Field and adding the start and stop bits, update the Tx data such that it can be loaded byte-wise */ + tamagawa_xchg->cmd.word0 = (0x2E)|(0xC0<<8); + /* Number of expected Rx frames is 6 */ + tamagawa_xchg->tamagawa_interface.rx_frames = 6; + /* Number of Tx frames being sent to the encoder is 1, and the number of Rx frames to be received is 6 */ + tamagawa_xchg->cmd.word1 = (1)|(6<<8); + break; + + case DATA_ID_8: + /* Reset */ + /* After reversing the Control Field and adding the start and stop bits, update the Tx data such that it can be loaded byte-wise */ + tamagawa_xchg->cmd.word0 = (0x21)|(0xC0<<8); + /* Number of expected Rx frames is 6 */ + tamagawa_xchg->tamagawa_interface.rx_frames = 6; + /* Number of Tx frames being sent to the encoder is 1, and the number of Rx frames to be received is 6 */ + tamagawa_xchg->cmd.word1 = (1)|(6<<8); + break; + + case DATA_ID_C: + /* Reset */ + /* After reversing the Control Field and adding the start and stop bits, update the Tx data such that it can be loaded byte-wise */ + tamagawa_xchg->cmd.word0 = (0x23)|(0x40<<8); + /* Number of expected Rx frames is 6 */ + tamagawa_xchg->tamagawa_interface.rx_frames = 6; + /* Number of Tx frames being sent to the encoder is 1, and the number of Rx frames to be received is 6 */ + tamagawa_xchg->cmd.word1 = (1)|(6<<8); + break; + + case DATA_ID_D: + /* EEPROM Read */ + /* Loop through all the selected channels and prepare the EEPROM Read Tx data based on the CF, ADF and CRC data */ + for(ch = 0 ; ch < MAX_CHANNELS ; ch++) + { + if(gTamagawa_multi_ch_mask & 1 << ch) + { + tamagawa_prepare_eeprom_command(priv, cmd, ch); + } + } + /* Number of expected Rx frames is 4 */ + tamagawa_xchg->tamagawa_interface.rx_frames = 4; + /* Number of Tx frames being sent to the encoder is 3, and the number of Rx frames to be received is 4 */ + tamagawa_xchg->cmd.word1 = (3)|(4<<8); + break; + + case DATA_ID_6: + /* EEPROM Write */ + /* Loop through all the selected channels and prepare the EEPROM Read Tx data based on the CF, ADF, EDF and CRC data */ + for(ch = 0 ; ch < MAX_CHANNELS; ch++) + { + if(gTamagawa_multi_ch_mask & 1 << ch) + { + tamagawa_prepare_eeprom_command(priv, cmd, ch); + } + } + /* Number of expected Rx frames is 4 */ + tamagawa_xchg->tamagawa_interface.rx_frames = 4; + /* Number of Tx frames being sent to the encoder is 4, and the number of Rx frames to be received is 4 */ + tamagawa_xchg->cmd.word1 = (4)|(4<<8); + break; + + default: + cmd = -1; + break; + } + + return cmd; +} + +void tamagawa_command_send(struct tamagawa_priv *priv) +{ + /* Triggers sending the tamagawa command in PRU */ + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + /* Set the trigger value as 1 */ + tamagawa_xchg->config.trigger = 0x1; +} + +void tamagawa_command_wait(struct tamagawa_priv *priv) +{ + /* Waits till PRU finishes tamagawa transaction */ + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + /* Wait until the trigger value is 1 */ + while(tamagawa_xchg->config.trigger & 0x1) + ; +} + +int32_t tamagawa_command_process(struct tamagawa_priv *priv, int32_t cmd, uint8_t gTamagawa_multi_ch_mask) +{ + /* Sends the tamagawa command and waits till firmware acknowledges */ + + /* Use tamagawa_command_build to setup the tamagawa command in the PRU interface buffer */ + cmd = tamagawa_command_build(priv, cmd, gTamagawa_multi_ch_mask); + + if(cmd < 0) + { + return cmd; + } + + /* Trigger sending the tamagawa command in PRU */ + tamagawa_command_send(priv); + /* Wait till PRU finishes tamagawa transaction */ + tamagawa_command_wait(priv); + + /* In case of EEPROM commands, reset the command id for all the channels back to 0 */ + if (cmd == DATA_ID_6 || cmd == DATA_ID_D) + { + priv->tamagawa_xchg->tamagawa_eeprom_interface[0].cmd = 0; + priv->tamagawa_xchg->tamagawa_eeprom_interface[1].cmd = 0; + priv->tamagawa_xchg->tamagawa_eeprom_interface[2].cmd = 0; + } + + return cmd; +} + +uint32_t tamagawa_reverse_bits(int8_t data) +{ + /* Reverses the bits of the 8 bit data*/ + /* Loops through all the bits of input data. If the bit at i-th position is set for the input data, then set the bit at (N – 1 – i)-th position in reversed number. + Here, N is the number of bits in the input data.*/ + uint32_t number_of_bits = sizeof(data) * 8; + uint32_t reversed_num = 0; + uint32_t current_bit_pos; + for (current_bit_pos = 0; current_bit_pos < number_of_bits; current_bit_pos++) { + if ((data & (1 << current_bit_pos))) + reversed_num |= 1 << ((number_of_bits - 1) - current_bit_pos); + } + return reversed_num; +} + +uint64_t tamagawa_prepare_eeprom_tx_data(uint64_t eeprom_tx_data, volatile uint32_t data) +{ + /* Takes the 8 bit data of CF(Control Field), ADF(address of EEPROM), EDF(data for EEPROM) and CRC, reverses it and adds the start and the stop bits */ + + /* Call tamagawa_reverse_bits function in order to reverse the bits of the data */ + uint32_t reversed_num = tamagawa_reverse_bits(data); + /* Perform left shift of the 64 bit integer holding the EEPROM Tx data 9 times and bitwise-OR it with the reversed number to add the start bit and the reversed data*/ + eeprom_tx_data = eeprom_tx_data<<9; + eeprom_tx_data = eeprom_tx_data|reversed_num; + /* Perform left shift of the integer holding the EEPROM Tx data 1 more time and bitwise-OR it with 1 in order to add the stop bit */ + eeprom_tx_data = eeprom_tx_data<<1; + eeprom_tx_data = eeprom_tx_data|1; + return eeprom_tx_data; +} + +void tamagawa_prepare_eeprom_command(struct tamagawa_priv *priv, int32_t cmd,uint32_t ch) +{ + /* Prepares the required EEPROM command from the CF(Control Field), ADF(address of EEPROM), EDF(data for EEPROM) and CRC */ + uint64_t eeprom_tx_data = 0; + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + if (cmd== DATA_ID_6) + { + /* Command preparation for EEPROM Write */ + /* Control Field value for EEPROM Write is 0x32 */ + eeprom_tx_data = tamagawa_prepare_eeprom_tx_data(eeprom_tx_data, 0x32); + eeprom_tx_data = tamagawa_prepare_eeprom_tx_data(eeprom_tx_data, tamagawa_xchg->tamagawa_eeprom_interface[ch].adf); + eeprom_tx_data = tamagawa_prepare_eeprom_tx_data(eeprom_tx_data, tamagawa_xchg->tamagawa_eeprom_interface[ch].edf); + eeprom_tx_data = tamagawa_prepare_eeprom_tx_data(eeprom_tx_data, tamagawa_xchg->tamagawa_eeprom_interface[ch].crc); + } + else + { + /* Command preparation for EEPROM Read */ + /* Control Field value for EEPROM Read is 0xEA */ + eeprom_tx_data = tamagawa_prepare_eeprom_tx_data(eeprom_tx_data, 0xEA); + eeprom_tx_data = tamagawa_prepare_eeprom_tx_data(eeprom_tx_data, tamagawa_xchg->tamagawa_eeprom_interface[ch].adf); + eeprom_tx_data = tamagawa_prepare_eeprom_tx_data(eeprom_tx_data, tamagawa_xchg->tamagawa_eeprom_interface[ch].crc); + /* 64 bit integer is left shifted twice to load the data byte wise into the Tx FIFO correctly */ + eeprom_tx_data <<= 2; + } + /* Assign the value of the prepared Tx data for EEPROM commands to the 64 bit integer eeprom_tx_data for the currently selected channel */ + tamagawa_xchg->tamagawa_eeprom_interface[ch].eeprom_tx_data = eeprom_tx_data; +} + +void tamagawa_config_clock(struct tamagawa_priv *priv, struct tamagawa_clk_cfg *clk_cfg) +{ + /* Configures the tamagawa clock */ + void *pruss_cfg = priv->pruss_cfg; + /* Configure the PRUx Rx CFG register by writing the Rx Divide Factor and Oversampling rate */ + HW_WR_REG32((uint32_t)(pruss_cfg) + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_RXCFG, (uint32_t)(clk_cfg->rx_div << 16 | 0x8 | clk_cfg->rx_div_attr)); + /* Configure the PRUx Tx CFG register by writing the Tx Divide Factor */ + HW_WR_REG16((uint32_t)(pruss_cfg) + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_TXCFG + 2, (uint16_t)(clk_cfg->tx_div)); +} + +void tamagawa_config_host_trigger(struct tamagawa_priv *priv) +{ + /* Configures tamagawa master for host trigger mode */ + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + + tamagawa_xchg->config.opmode = 0x1; +} + +void tamagawa_config_periodic_trigger(struct tamagawa_priv *priv) +{ + /* Configures tamagawa master in periodic trigger mode */ + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + + tamagawa_xchg->config.opmode = 0; +} + +void tamagawa_config_channel(struct tamagawa_priv *priv, uint32_t ch) +{ + /* Selects the channel to be used by tamagawa master */ + struct tamagawa_xchg *tamagawa_xchg = priv->tamagawa_xchg; + + tamagawa_xchg->config.channel = 1 << ch; + priv->channel = ch; + tamagawa_xchg->tamagawa_interface.ch_mask = 1 << ch; +} + +void tamagawa_config_multi_channel_mask(struct tamagawa_priv *priv, uint8_t mask) +{ + /* Selects mask of channels to be used in multi channel configuration */ + priv->tamagawa_xchg->config.channel = mask; +} + +void tamagawa_update_data_id(struct tamagawa_priv *priv, int32_t cmd) +{ + /* Updates the data id according to the command selected */ + priv->tamagawa_xchg->tamagawa_interface.data_id= cmd; + if(cmd == DATA_ID_6 || cmd == DATA_ID_D) + { + priv->tamagawa_xchg->tamagawa_eeprom_interface[0].cmd = cmd; + priv->tamagawa_xchg->tamagawa_eeprom_interface[1].cmd = cmd; + priv->tamagawa_xchg->tamagawa_eeprom_interface[2].cmd = cmd; + } +} + +void tamagawa_update_adf(struct tamagawa_priv *priv, uint32_t val, uint32_t ch) +{ + /* Updates the ADF field for the currently selected channel for EEPROM commands */ + priv->tamagawa_xchg->tamagawa_eeprom_interface[ch].adf = val; +} + +void tamagawa_update_edf(struct tamagawa_priv *priv, uint32_t val, uint32_t ch) +{ + /* Updates the EDF field for the currently selected channel for EEPROM Write command */ + priv->tamagawa_xchg->tamagawa_eeprom_interface[ch].edf = val; +} + +void tamagawa_eeprom_crc_reinit(struct tamagawa_priv *priv) +{ + /* Resets the integers used to calculate the CRC back to 0 for all the channels */ + uint32_t ch = 0; + for(ch = 0; ch < MAX_CHANNELS; ch++) + { + priv->tamagawa_xchg->tamagawa_eeprom_interface[ch].word0 = 0; + priv->tamagawa_xchg->tamagawa_eeprom_interface[ch].word1 = 0; + priv->tamagawa_xchg->tamagawa_eeprom_interface[ch].word2 = 0; + } +} + +uint8_t tamagawa_multi_channel_detected(struct tamagawa_priv *priv) +{ + /* Detects the channels that have been selected in multi-channel configuration */ + return priv->tamagawa_xchg->config.channel; +} + +void tamagawa_multi_channel_set_cur(struct tamagawa_priv *priv, uint32_t ch) +{ + /* Set the channel that is currently being processed */ + priv->channel = ch; +} + +static inline void tamagawa_config_clr_cfg0(struct tamagawa_priv *priv) +{ + void *pruss_cfg = priv->pruss_cfg; + /* Clear the CFG0 registers for the selected PRUx slice for Channel 0 */ + HW_WR_REG32((uint32_t)(pruss_cfg) + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH0_CFG0, 0); + /* Clear the CFG0 registers for the selected PRUx slice for Channel 1 */ + HW_WR_REG32((uint32_t)(pruss_cfg) + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH1_CFG0, 0); + /* Clear the CFG0 registers for the selected PRUx slice for Channel 2 */ + HW_WR_REG32((uint32_t)(pruss_cfg) + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH2_CFG0, 0); +} + +struct tamagawa_priv *tamagawa_init(struct tamagawa_xchg *tamagawa_xchg, void *pruss_cfg, uint32_t slice_value) +{ + /* Initializes tamagawa firmware interface address and get the pointer to struct tamagawa_priv instance */ + tamagawa_priv.tamagawa_xchg = tamagawa_xchg; + tamagawa_priv.pruss_cfg = pruss_cfg; + tamagawa_priv.slice_value = slice_value; + + /* If the slice value is 0, it denotes that PRU0 is selected. Assign the register offsets for PRU0 */ + if(slice_value==0) + { + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH2_CFG0 = CSL_ICSSCFG_EDPRU0CH2CFG0REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH0_CFG0 = CSL_ICSSCFG_EDPRU0CH0CFG0REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH0_CFG1 = CSL_ICSSCFG_EDPRU0CH0CFG1REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH1_CFG1 = CSL_ICSSCFG_EDPRU0CH1CFG1REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH1_CFG0 = CSL_ICSSCFG_EDPRU0CH1CFG0REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH2_CFG1 = CSL_ICSSCFG_EDPRU0CH2CFG1REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_GPCFGx = CSL_ICSSCFG_GPCFG0; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_RXCFG = CSL_ICSSCFG_EDPRU0RXCFGREGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_TXCFG = CSL_ICSSCFG_EDPRU0TXCFGREGISTER; + } + /* If the slice value is 1, it denotes that PRU1 is selected. Assign the register offsets for PRU1 */ + else if(slice_value==1) + { + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH0_CFG0 = CSL_ICSSCFG_EDPRU1CH0CFG0REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH1_CFG0 = CSL_ICSSCFG_EDPRU1CH1CFG0REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH2_CFG0 = CSL_ICSSCFG_EDPRU1CH2CFG0REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH0_CFG1 = CSL_ICSSCFG_EDPRU1CH0CFG1REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH1_CFG1 = CSL_ICSSCFG_EDPRU1CH1CFG1REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_CH2_CFG1 = CSL_ICSSCFG_EDPRU1CH2CFG1REGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_GPCFGx = CSL_ICSSCFG_GPCFG1; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_RXCFG = CSL_ICSSCFG_EDPRU1RXCFGREGISTER; + tamagawa_priv.register_offset_val.ICSS_CFG_PRUx_ED_TXCFG = CSL_ICSSCFG_EDPRU1TXCFGREGISTER; + } + + return &tamagawa_priv; +} diff --git a/source/motor_control/position_sense/tamagawa/firmware/eeprom_read.h b/source/motor_control/position_sense/tamagawa/firmware/eeprom_read.h new file mode 100644 index 0000000..028e269 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/eeprom_read.h @@ -0,0 +1,149 @@ +; Copyright (C) 2022 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions + ; are met: + ; + ; Redistributions of source code must retain the above copyright + ; notice, this list of conditions and the following disclaimer. + ; + ; Redistributions in binary form must reproduce the above copyright + ; notice, this list of conditions and the following disclaimer in the + ; documentation and/or other materials provided with the + ; distribution. + ; + ; Neither the name of Texas Instruments Incorporated nor the names of + ; its contributors may be used to endorse or promote products derived + ; from this software without specific prior written permission. + ; + ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ; + + +;************************************************************************************ +;* File: eeprom_read.h * +;* * +;* Brief: Macro for performing EEPROM Read on Tamagawa encoder * +;************************************************************************************ + +;************************************************************************************************************************************* +; Macro: EEPROM_READ_MACRO +; +; Perform the EEPROM Read operation on the Tamagawa encoders. +; +; Registers: +; R25- Used to store the Tx data to be sent to the encoder +; R26.b0- Used to store the offset of the 64 bit integer holding Tx data +; R30.b0- Used to load Tx FIFO for a selected channel +; R30.b2- Used to store the currently selected channel +; +; +; +; PseudoCode: +; (start code) +; 1.Check if the current channel is enabled. +; 2.Load the offset of the 64 bit integer holding Tx data to R26.b0 for the currently selected channel. +; 3.Load 4 bytes of data from the offset stored in R26.b0 to R25. +; 4.Load the Tx FIFO for the currently selected channel by writing to the R30.b0 byte-wise 4 times. +; 5.Loop through the steps 1-4 thrice in case of multi-channel configuration to fill Tx FIFO for all selected channels. +; 6.Once the Tx FIFO of all the selected channels is loaded with 4 bytes, make a call to the FN_SEND function that performs Tx in single shot mode with Tx frame size = 30 bits. +; (end code) +; +; Parameters: +; ch_mask - Channel mask, used to check if the current channel is enabled +; pru_dmem - Data Memory address for PRU +; +; Worst case peak cycle usage: 110 (approx.) +; For EEPROM Read, the Control Field (CF), Address (ADF) and CRC frames should be transmitted to the encoder in about 6.0 μs and 12.0 μs for 5 Mbps and 2.5 Mbps Tamagawa Encoders respectively.. +; +;************************************************************************************************************************************** + + .if !$isdefed("__eeprom_read_h") +__eeprom_read_h .set 1 + + .include "tamagawa_interface.h" + .include "tamagawa_constants.h" + .global FN_SEND + .global CALL + .global CALL2 + +EEPROM_READ_MACRO .macro ch_mask, pru_dmem + + ;In case of EEPROM Read, there is a need to send 30 bits of data to the Encoder + ;32 bits of data is first loaded into the Tx FIFO and Tx in Single shot mode is started with Tx frame size = 30 bits + + .if $defined("ENABLE_MULTI_CHANNEL") + LOOP EEPROM_READ_MULTI_CHANNEL?, 3 ;In each iteration, channel is selected and Tx Fifo is loaded . + .endif + + ; if channel 0 is enabled, use the Tx command offset for ch 0. + QBBC TAMAGAWA_CH_SEL_SKIP_CH0?, ch_mask, 0 + ; Check if the current channel is 0 + AND R26.b0, R30.b2, CHANNEL_CHECK_MASK + ; If the current channel is not 0, skip loading the offset for Channel 0 + QBNE TAMAGAWA_CH_SEL_SKIP_CH0?, R26.b0, 0 + ; Load the offset of the address where EEPROM Tx command is stored + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_0_CH0 + JMP TAMAGAWA_LOADED_OFFSET? + +TAMAGAWA_CH_SEL_SKIP_CH0?: + ; if channel 1 is enabled, use the Tx command offset for ch 1 + QBBC TAMAGAWA_CH_SEL_SKIP_CH1?, ch_mask, 1 + ; Check if the current channel is 1 + AND R26.b0, R30.b2, CHANNEL_CHECK_MASK + ; If the current channel is not 1, skip loading the offset for Channel 1 + QBNE TAMAGAWA_CH_SEL_SKIP_CH1?, R26.b0, 1 + ; Load the offset of the address where EEPROM Tx command is stored + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_0_CH1 + JMP TAMAGAWA_LOADED_OFFSET? + +TAMAGAWA_CH_SEL_SKIP_CH1?: + ; if channel 2 is enabled, use the Tx command offset for ch 2 + QBBC TAMAGAWA_CH_SEL_SKIP_CH2?, ch_mask, 2 + ; Check if the current channel is 2 + AND R26.b0, R30.b2, CHANNEL_CHECK_MASK + ; If the current channel is not 2, skip loading the offset for Channel 2 + QBNE TAMAGAWA_CH_SEL_SKIP_CH2?, R26.b0, 2 + ; Load the offset of the address where EEPROM Tx command is stored + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_0_CH2 + JMP TAMAGAWA_LOADED_OFFSET? + +TAMAGAWA_CH_SEL_SKIP_CH2?: + +TAMAGAWA_LOADED_OFFSET?: + ;load 4 bytes of data from the TAMAGAWA_EEPROM_TX_CMD offset to R25 + LBCO &R25, pru_dmem, R26.b0, 4 + + ;load Tx Fifo + MOV R30.b0, R25.b3 + ;load Tx Fifo + MOV R30.b0, R25.b2 + ;load Tx Fifo + MOV R30.b0, R25.b1 + ;load Tx Fifo + MOV R30.b0, R25.b0 + + + .if $defined("ENABLE_MULTI_CHANNEL") + ; last channel would have been selected first + ;R30[17:16] tx_ch_sel is decremented to select next channel and load Tx Fifo. + SUB R30.b2, R30.b2, 1 +EEPROM_READ_MULTI_CHANNEL?: + .endif + + ; Sending Tx Fifo data via Data line(PERIF0_OUT,PERIF1_OUT,PERIF2_OUT) to encoders + CALL2 FN_SEND + + .endm + + .endif diff --git a/source/motor_control/position_sense/tamagawa/firmware/eeprom_write.h b/source/motor_control/position_sense/tamagawa/firmware/eeprom_write.h new file mode 100644 index 0000000..36336cd --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/eeprom_write.h @@ -0,0 +1,278 @@ +; Copyright (C) 2022 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions + ; are met: + ; + ; Redistributions of source code must retain the above copyright + ; notice, this list of conditions and the following disclaimer. + ; + ; Redistributions in binary form must reproduce the above copyright + ; notice, this list of conditions and the following disclaimer in the + ; documentation and/or other materials provided with the + ; distribution. + ; + ; Neither the name of Texas Instruments Incorporated nor the names of + ; its contributors may be used to endorse or promote products derived + ; from this software without specific prior written permission. + ; + ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ; + + +;************************************************************************************ +;* File: eeprom_write.h * +;* * +;* Brief: Macro for performing EEPROM Write on Tamagawa encoder * +;************************************************************************************ + +;************************************************************************************************************************************* +; Macro: EEPROM_WRITE_MACRO +; +; Perform the EEPROM Read operation on the Tamagawa encoders. +; +; Registers: +; R25- Used to store the Tx data to be sent to the encoder +; R26.b0- Used to store the offset of the 64 bit integer holding Tx data +; R30.b0- Used to load Tx FIFO for a selected channel +; R30.b2- Used to store the currently selected channel +; R31- Used to monitor the Tx FIFO level for different channels +; +; +; +; PseudoCode: +; (start code) +; 1.Check if the current channel is enabled. +; 2.Load the offset of 5th byte of the 64 bit integer holding Tx data to R26.b0 for the currently selected channel. +; 3.Load 1 byte of data from the offset stored in R26.b0 to R25. +; 4.Load the 5th byte of Tx data to the Tx FIFO for the currently seelcted channel by writing to R30.b0 once. +; 5.Load the offset of 0th byte of the 64 bit integer holding Tx data to R26.b0 for the currently selected channel. +; 6.Load 4 bytes of data from the offset stored in R26.b0 to R25. +; 7.Load the Tx FIFO for the currently selected channel by writing to the R30.b0 byte-wise 3 times. +; 8.Loop through the steps 1-7 thrice in case of multi-channel configuration to fill Tx FIFO for all selected channels. +; 9.Once the Tx FIFO of all the selected channels is loaded with 4 bytes, make a call to the FN_SEND function that performs Tx in Continuous mode. +; 10.Monitor the Tx FIFO level for the current channel until the FIFO level reaches 3 bytes or less. +; 11.Load the last byte of Tx data into the Tx FIFO by writing to the R30.b0 once. +; 12.Repeat the steps 10-11 for all the selected channels. +; (end code) +; +; Parameters: +; ch_mask - Channel mask, used to check if the current channel is enabled +; pru_dmem - Data Memory address for PRU +; +; Worst case peak cycle usage: 750 (aprpox.) +; For EEPROM Write, the Control Field (CF), Address (ADF), Data (EDF) and CRC frames should be transmitted to the encoder in about 8.0 μs and 16.0 μs for 5 Mbps and 2.5 Mbps Tamagawa Encoders respectively. +; +;************************************************************************************************************************************** + + .if !$isdefed("__eeprom_write_h") +__eeprom_write_h .set 1 + + .include "tamagawa_interface.h" + .include "tamagawa_constants.h" + .global FN_SEND + .global CALL + .global CALL2 + +EEPROM_WRITE_MACRO .macro ch_mask, pru_dmem + + ;In case of EEPROM Write, there is a need to send 40 bits of data to the Encoder + ;First 32 bits of data is loaded into the Tx FIFO and Tx in Continuous FIFO loading is initiated + ;Keep polling r31[20-18, 12-10, 4-2] (tx_fifo_sts) and reload the FIFO with the last 8 bits when the FIFO level reaches 3 bytes + + ;In case of EEPROM write, we need to first load the + ;value stored at the 5th byte of the 64 bit integer used to store the Tx data. + + .if $defined("ENABLE_MULTI_CHANNEL") + ;In each iteration, channel is selected and Tx Fifo is loaded . + LOOP EEPROM_WRITE_MULTI_CHANNEL?, 3 + .endif + + ; if channel 0 is enabled, use the Tx command offset for ch 0 + QBBC TAMAGAWA_WRITE_SKIP_CH0?, ch_mask, 0 + ; Check if the current channel is 0 + AND R26.b0, R30.b2, CHANNEL_CHECK_MASK + ; If the current channel is not 0, skip loading the offset for Channel 0 + QBNE TAMAGAWA_WRITE_SKIP_CH0?, R26.b0, 0 + ; Load the offset of the address where EEPROM Tx command's 5th byte is stored + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_1_CH0 + ;load the 5th byte of data from the offset stored in R26.b0 to R25 + LBCO &R25.b0, pru_dmem, R26.b0, 1 + ;load Tx Fifo + MOV R30.b0,R25.b0 + ; Load the offset of the address where EEPROM Tx command is stored + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_0_CH0 + ;load 4 bytes of data from the offset stored in R26.b0 to R25 + LBCO &R25, pru_dmem, R26.b0, 4 + ;load Tx Fifo + MOV R30.b0,R25.b3 + ;load Tx Fifo + MOV R30.b0,R25.b2 + ;load Tx Fifo + MOV R30.b0,R25.b1 + + JMP TAMAGAWA_EEPROM_LOADED_BYTE1? + +TAMAGAWA_WRITE_SKIP_CH0?: + ; if channel 1 is enabled, use the Tx command offset for ch 1 + QBBC TAMAGAWA_WRITE_SKIP_CH1?, TAMAGAWA_ENABLE_CHx, 1 + ; Check if the current channel is 1 + AND R26.b0, R30.b2, CHANNEL_CHECK_MASK + ; If the current channel is not 1, skip loading the offset for Channel 1 + QBNE TAMAGAWA_WRITE_SKIP_CH1?, R26.b0, 1 + ; Load the offset of the address where EEPROM Tx command's 5th byte is stored + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_1_CH1 + ;load the 5th byte of data from the offset stored in R26.b0 to R25 + LBCO &R25.b0, pru_dmem, R26.b0, 1 + ;load Tx Fifo + MOV R30.b0,R25.b0 + ; Load the offset of the address where EEPROM Tx command is stored + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_0_CH1 + ;load 4 bytes of data from the offset stored in R26.b0 to R25 + LBCO &R25, pru_dmem, R26.b0, 4 + ;load Tx Fifo + MOV R30.b0,R25.b3 + ;load Tx Fifo + MOV R30.b0,R25.b2 + ;load Tx Fifo + MOV R30.b0,R25.b1 + + JMP TAMAGAWA_EEPROM_LOADED_BYTE1? + +TAMAGAWA_WRITE_SKIP_CH1?: + ; if channel 2 is enabled, use the Tx command offset for ch 2 + QBBC TAMAGAWA_WRITE_SKIP_CH2?, TAMAGAWA_ENABLE_CHx, 2 + ; Check if the current channel is 2 + AND R26.b0, R30.b2, CHANNEL_CHECK_MASK + ; If the current channel is not 1, skip loading the offset for Channel 2 + QBNE TAMAGAWA_WRITE_SKIP_CH2?, R26.b0, 2 + ; Load the offset of the address where EEPROM Tx command's 5th byte is stored + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_1_CH2 + ;load the 5th byte of data from the offset stored in R26.b0 to R25 + LBCO &R25.b0, pru_dmem, R26.b0, 1 + ;load Tx Fifo + MOV R30.b0,R25.b0 + ; Load the offset of the address where EEPROM Tx command is stored + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_0_CH2 + ;load 4 bytes of data from the offset stored in R26.b0 to R25 + LBCO &R25, pru_dmem, R26.b0, 4 + ;load Tx Fifo + MOV R30.b0,R25.b3 + ;load Tx Fifo + MOV R30.b0,R25.b2 + ;load Tx Fifo + MOV R30.b0,R25.b1 + + JMP TAMAGAWA_EEPROM_LOADED_BYTE1? +TAMAGAWA_WRITE_SKIP_CH2?: + +TAMAGAWA_EEPROM_LOADED_BYTE1?: + +EEPROM_WRITE_END?: + + .if $defined("ENABLE_MULTI_CHANNEL") + ; last channel would have been selected first + ;R30[17:16] tx_ch_sel is decremented to select next channel and load Tx Fifo. + SUB R30.b2, R30.b2, 1 +EEPROM_WRITE_MULTI_CHANNEL?: + .endif + + ; Sending Tx Fifo data via Data line(PERIF0_OUT,PERIF1_OUT,PERIF2_OUT) to encoders + CALL2 FN_SEND + +;EEPROM_WRITE_CONT?: + ; Clear the R26 register in order to monitor the Tx FIFO level for different channels + ZERO &R26.b0,4 + ; Move the value of number of channels selected to R30.b2 + MOV R30.b2, R10.b0 + + .if $defined("ENABLE_MULTI_CHANNEL") + ;In each iteration, channel is selected and Tx Fifo is loaded . + LOOP TAMAGAWA_EEPROM_CONTINUE_MULTI_CH?, 3 + .endif + +WAITLABEL0?: + ; if channel 0 is not enabled, skip polling the bits 2-4 of R31. + QBBC TAMAGAWA_EEPROM_SKIP_CH0?, TAMAGAWA_ENABLE_CHx, 0 + ; Check if the current channel is 0 + AND R26.b0, R30.b2, CHANNEL_CHECK_MASK + ; If the current channel is not 0, skip polling the bits 2-4 of R31 + QBNE TAMAGAWA_EEPROM_SKIP_CH0?, R26.b0, 0 + ; Monitor the bits 2-4 of R31 to get the Tx FIFO Level + AND R26.b0,R31.b0,POLLING_MASK + ;Keep waiting till the Tx FIFO level is not at 3 bytes + QBLT WAITLABEL0?, R26.b0, THREE_BYTES_FIFO_LEVEL + + ; Load the offset of the Tx Command + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_0_CH0 + ; Load 1 byte of data from TAMAGAWA_EEPROM_TX_CMD to R25.b0 + LBCO &R25.b0, pru_dmem, R26.b0, 1 + ;load Tx Fifo + MOV R30.b0,R25.b0 + JMP TAMAGAWA_EEPROM_LOADED_BYTE4? +TAMAGAWA_EEPROM_SKIP_CH0?: + +WAITLABEL1?: + ; if channel 1 is not enabled, skip polling the bits 10-12 of R31. + QBBC TAMAGAWA_EEPROM_SKIP_CH1?, TAMAGAWA_ENABLE_CHx, 1 + ; Check if the current channel is 1 + AND R26.b0, R30.b2, CHANNEL_CHECK_MASK + ; If the current channel is not 1, skip polling the bits 10-12 of R31 + QBNE TAMAGAWA_EEPROM_SKIP_CH1?, R26.b0, 1 + ; Monitor the bits 10-12 of R31 to get the Tx FIFO Level + AND R26.b0,R31.b1,POLLING_MASK + ;Keep waiting till the Tx FIFO level is not at 3 bytes + QBLT WAITLABEL1?, R26.b0, THREE_BYTES_FIFO_LEVEL + + ; Load the offset of the Tx Command + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_0_CH1 + ; Load 1 byte of data from TAMAGAWA_EEPROM_TX_CMD to R25.b0 + LBCO &R25.b0, pru_dmem, R26.b0, 1 + ;load Tx Fifo + MOV R30.b0,R25.b0 + JMP TAMAGAWA_EEPROM_LOADED_BYTE4? +TAMAGAWA_EEPROM_SKIP_CH1?: + +WAITLABEL2?: + ; if channel 2 is not enabled, skip polling the bits 18-20 of R31. + QBBC TAMAGAWA_EEPROM_SKIP_CH2?, TAMAGAWA_ENABLE_CHx, 2 + ; Check if the current channel is 1 + AND R26.b0, R30.b2, CHANNEL_CHECK_MASK + ; If the current channel is not 1, skip polling the bits 18-20 of R31 + QBNE TAMAGAWA_EEPROM_SKIP_CH2?, R26.b0, 2 + ; Monitor the bits 18-20 of R31 to get the Tx FIFO Level + AND R26.b0,R31.b2,POLLING_MASK + ;Keep waiting till the Tx FIFO level is not at 3 bytes + QBLT WAITLABEL2?, R26.b0, THREE_BYTES_FIFO_LEVEL + + ; Load the offset of the Tx Command + LDI R26.b0, TAMAGAWA_EEPROM_TX_CMD_0_CH2 + ; Load 1 byte of data from TAMAGAWA_EEPROM_TX_CMD to R25.b0 + LBCO &R25.b0, pru_dmem, R26.b0, 1 + ;load Tx Fifo + MOV R30.b0,R25.b0 + JMP TAMAGAWA_EEPROM_LOADED_BYTE4? +TAMAGAWA_EEPROM_SKIP_CH2?: + +TAMAGAWA_EEPROM_LOADED_BYTE4?: + + .if $defined("ENABLE_MULTI_CHANNEL") + ; last channel would have been selected first + ;R30[17:16] tx_ch_sel is decremented to select next channel and load Tx Fifo. + SUB R30.b2, R30.b2, 1 +TAMAGAWA_EEPROM_CONTINUE_MULTI_CH?: + .endif + + .endm + + .endif diff --git a/source/motor_control/position_sense/tamagawa/firmware/firmware_version.h b/source/motor_control/position_sense/tamagawa/firmware/firmware_version.h new file mode 100644 index 0000000..adffff7 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/firmware_version.h @@ -0,0 +1,69 @@ + +; +; Copyright (C) 2022 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; + + .if !$isdefed("__firmware_version_h") +__firmware_version_h .set 1 + +; ICSS_FIRMWARE_RELEASE_1: +; bit 31..16 reserved +; bit15..8 device number +FIRMWARE_DEVICE_AM335x .set 0 ; AM335x +FIRMWARE_DEVICE_AM437x .set 1 ; AM437x +FIRMWARE_DEVICE_AM64x_AM243x .set 2 ; AM64x_AM243x + +; bit7..0 protocol type +FIRMWARE_PROTOCOL_TYPE_PROFIBUS_SLAVE .set 0x00 +FIRMWARE_PROTOCOL_TYPE_ETHERCAT_SLAVE .set 0x01 +FIRMWARE_PROTOCOL_TYPE_PROFINET_DEVICE .set 0x02 +FIRMWARE_PROTOCOL_TYPE_SERCOS_SLAVE .set 0x03 +FIRMWARE_PROTOCOL_TYPE_OPENMAC_SLAVE .set 0x04 +FIRMWARE_PROTOCOL_TYPE_ETHERNET .set 0x05 +FIRMWARE_PROTOCOL_TYPE_ENETIP_SLAVE .set 0x06 +FIRMWARE_PROTOCOL_TYPE_ENDAT_MASTER .set 0x07 +FIRMWARE_PROTOCOL_TYPE_TAMAGAWA .set 0x08 + +; ICSS_FIRMWARE_RELEASE_2: +; bit31 release or internal version +FIRMWARE_VERSION_RELEASE .set 0 +FIRMWARE_VERSION_INTERNAL .set 1 +; bit30..24 version number +FIRMWARE_VERSION_REVISION .set 0x00 +; bit23..16 major number +FIRMWARE_VERSION_MAJOR .set 0x01 +; bit15..0 minor number +FIRMWARE_VERSION_MINOR .set 0x0000 + +ICSS_FIRMWARE_RELEASE_1 .set ((FIRMWARE_DEVICE_AM64x_AM243x << 8) | (FIRMWARE_PROTOCOL_TYPE_TAMAGAWA << 0)) +ICSS_FIRMWARE_RELEASE_2 .set ((FIRMWARE_VERSION_RELEASE << 31) | (FIRMWARE_VERSION_REVISION << 24) | (FIRMWARE_VERSION_MAJOR << 16) | (FIRMWARE_VERSION_MINOR << 0)) + + .endif diff --git a/source/motor_control/position_sense/tamagawa/firmware/multi_ch_receive_frames.h b/source/motor_control/position_sense/tamagawa/firmware/multi_ch_receive_frames.h new file mode 100644 index 0000000..d235396 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/multi_ch_receive_frames.h @@ -0,0 +1,347 @@ +; Copyright (C) 2022 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions + ; are met: + ; + ; Redistributions of source code must retain the above copyright + ; notice, this list of conditions and the following disclaimer. + ; + ; Redistributions in binary form must reproduce the above copyright + ; notice, this list of conditions and the following disclaimer in the + ; documentation and/or other materials provided with the + ; distribution. + ; + ; Neither the name of Texas Instruments Incorporated nor the names of + ; its contributors may be used to endorse or promote products derived + ; from this software without specific prior written permission. + ; + ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ; + + +;************************************************************************************ +;* File: multi_ch_receive_frames.h * +;* * +;* Brief: Macro for receiving data frames from Tamagawa encoder * +;************************************************************************************ + +;************************************************************************************ +;* File: multi_ch_rx.h * +;* * +;* Brief: Macro for receiving one single data frame (which contains 8 bits) * +;* from Tamagawa encoder * +;************************************************************************************ + +;****************************************************************************************************************************************** +; Macro: MULTI_CH_RECEIVE_DATA_FRAME +; Receive complete data frame in Intermediate Register of particular channel +; +; +; Registers: +; R11.b0,R11.b1,R11.b2 - Intermediate Frame register for CH0/CH1/CH2 +; R12,R13,R14-Intermediate channel register for CH0/CH1/CH2 +; R16-R18: Channel register for CH0 +; R19-R21: Channel register for CH1 +; R22-R24: Channel register for CH2 +; +; PseudoCode: +; (start code) +; 1.Perform LSL by 8 on Intermediate channel register for making b0 level(R12.b0,) available for upcoming frame. +; 2.Wait till first valid bit flag raised. +; 3.Store the mid data bit from oversampled data for respective channel in intermediate frame register at MSB position +; 4.Perform LSR to shift right Intermediate frame register's bit by 1 +; 5.clear the valid flag. +; 6.Repeat instructions from 2-5 until all bits for 1 data frame received in Intermediate frame register. +; 7.Transfer intermediate frame register(R11.b0) value to Intermediate channel Register(R12) for channel at b0 level(R12.b0). +; (end code) +; +; Parameters: +; +; Ry0,Ry1,Ry2 - Intermediate Frame register for CH0/CH1/CH2 +; Rx0,Rx1,Rx2 - Intermediate channel register for CH0/CH1/CH2 +; cnt - size of data frame +; scratch - temporary variable +; scratch1 - temporary variable +; valid_mask - Mask of channels which are enabled +; +; Worst case peak cycle usage: 6070 (approx.) +; +;************************************************************************************************************************************** + + + .if !$isdefed("__multi_ch_receive_frames_h") +__multi_ch_receive_frames_h .set 1 + + .include "tamagawa_interface.h" + +MULTI_CH_RECEIVE_DATA_FRAME .macro Ry0,Ry1,Ry2,Rx0,Rx1,Rx2, cnt ,scratch,scratch1,valid_mask,temp1,temp2,temp3,temp4,temp5,temp6,val1,val2,val3,crc1,crc2,crc3,rx_frames,dmem + ;To Shift 1 byte left in Intermediate registers for loading incoming rx frame of 1 byte at Rx0.b0,Rx1.b0,Rx2.b0 positions. + ;Intermediate Register for channel 0 + LSL Rx0 ,Rx0 ,8 + ;Intermediate Register for channel 1 + LSL Rx1 ,Rx1 ,8 + ;Intermediate Register for channel 2 + LSL Rx2 ,Rx2 ,8 + + ; Run loop for receive bits for each data frame + LOOP RX_RECEIVE_DOWNSAMPLE_LOOP1?, cnt + + ;Shift 1 position right for align the bit to LSB position (As we are receiving bit sequence in LSB bit first mode for each frame). + LSR Ry0, Ry0, 1 + LSR Ry1, Ry1, 1 + LSR Ry2, Ry2, 1 + + +WB13?: + AND scratch.b0 ,R31.b3 ,valid_mask + ; wait for valid + QBNE WB13?, scratch.b0,valid_mask + + +CH0?: + ; CHANNEL 0:Check the Mid bit of received oversampled data + QBBS BIT_LOGIC_1_CH0?, R31, 4 + JMP CH1? +BIT_LOGIC_1_CH0?: + ;If Mid bit of oversampled data has logic 1 then store as logic 1. + SET Ry0, Ry0.t7 + +CH1?: + ; CHANNEL 1:Check the Mid bit of received oversampled data + QBBS BIT_LOGIC_1_CH1?, R31, 4+8 + JMP CH2? +BIT_LOGIC_1_CH1?: + ;If Mid bit of oversampled data has logic 1 then store as logic 1. + SET Ry1, Ry1.t7 + +CH2?: + ; CHANNEL 2:Check the Mid bit of received oversampled data + QBBS BIT_LOGIC_1_CH2?, R31, 4+16 + JMP BIT_CAPTURED? +BIT_LOGIC_1_CH2?: + ;If Mid bit of oversampled data has logic 1 then store as logic 1. + SET Ry2, Ry2.t7 + +BIT_CAPTURED?: + ;Clear valid bit + MOV R31.b3, scratch.b0 +RX_RECEIVE_DOWNSAMPLE_LOOP1?: +;Moving inverted data frame(which is correct info, as we receive LSB first from encoder) on particular intermediate channel rx register + ;1 byte load to CH0 intermediate Reg + MOV Rx0.b0,Ry0 + ;1 byte load to CH1 intermediate Reg + MOV Rx1.b0,Ry1 + ;1 byte load to CH2 intermediate Reg + MOV Rx2.b0,Ry2 + +CRC_CALC?: + +CHECH_LAST_RX_FRAME?: + QBEQ CRC_2?, rx_frames,1 + + LOOP CRC_1?,8 + LSR temp1,Ry0,7 + LSR temp2,crc1,7 + XOR val1,temp1,temp2 + LSL crc1,crc1,1 + LSL Ry0,Ry0,1 + OR crc1,crc1,val1 + + LSR temp3,Ry1,7 + LSR temp4,crc2,7 + XOR val2,temp3,temp4 + LSL crc2,crc2,1 + LSL Ry1,Ry1,1 + OR crc2,crc2,val2 + + LSR temp5,Ry2,7 + LSR temp6,crc3,7 + XOR val3,temp5,temp6 + LSL crc3,crc3,1 + LSL Ry2,Ry2,1 + OR crc3,crc3,val3 + + +CRC_1?: + JMP CRC_4? + +CRC_2?: + LDI temp1,0 + LDI temp2,0 + LDI temp3,0 + +CRC_RES_1?: + QBEQ CRC_SUCCESS_1?,Ry0,crc1 + +CRC_RES_2?: + QBEQ CRC_SUCCESS_2?,Ry1,crc2 + +CRC_RES_3?: + QBEQ CRC_SUCCESS_3?,Ry2,crc3 + + JMP CRC_3? + +CRC_SUCCESS_1?: + LDI temp1,1 + JMP CRC_RES_2? +CRC_SUCCESS_2?: + LDI temp2,1 + JMP CRC_RES_3? +CRC_SUCCESS_3?: + LDI temp3,1 + +CRC_3?: + + SBCO &temp1,dmem,TAMAGAWA_CH0_CRC_OFFSET,4 + SBCO &temp2,dmem,TAMAGAWA_CH1_CRC_OFFSET,4 + SBCO &temp3,dmem,TAMAGAWA_CH2_CRC_OFFSET,4 + +CRC_4?: + + + .endm + + +;************************************************************************************************************************************* +; Macro: RECEIVE_FRAMES_M +; +; Receive data from encoder and store it in respective registers assigned to channels +; +; Registers: +; R11.b0,R11.b1,R11.b2 - Intermediate Frame register for CH0/CH1/CH2 +; R12,R13,R14- Intermediate channel registers for CH0/CH1/CH2 +; R16-R18: Channel register for CH0 +; R19-R21: Channel register for CH1 +; R22-R24: Channel register for CH2 +; +; +; +; PseudoCode: +; (start code) +; 1.Read start bit and simply clear the valid flag without storing it. +; 2.Read and store next 8 bits in Intermediate register +; 3.Read stop bit and simply clear the valid flag without storing it. +; 4.When Intermediate Register gets full ,unload its data to Assigned Registers for particular channel +; 5. Continue loop between 1-4 instruction no. till last frame receive +; 6. After last frame received in intermediate register, unload its data to Assigned Registers for particular channel +; (end code) +; +; Parameters: +; df_size - Size of data frame (8 bits in tamagawa) +; bytes_filled - Current byte level received from encoder +; rx_frames - no. of rx frames left that are expected to from encoder for the current command id. +; flag - used as a trigger to unload last frame intermediate register data to channel registers +; scratch - temporary variable +; scratch1 - temporary variable +; valid_mask - Mask of channels which are enabled +; +;************************************************************************************************************************************** + + +RECEIVE_FRAMES_M .macro df_size, bytes_filled ,rx_frames, flag ,scratch, scratch1,valid_mask,dmem + +;;Now data for first frame comes up FOR TAMAGAWA COMMAND +START_BIT?: + ; Getting valid bit flag for enabled channel + AND scratch.b0 ,R31.b3 ,valid_mask + ; wait for valid + QBNE START_BIT?, scratch.b0, valid_mask + ;Set the valid bit for clearing flag so that next bit can come. + ; This bit is start bit which is not stored. + MOV R31.b3, scratch.b0 + +DATA_FRAME_M?: ;For receiving upcoming data frame + + MULTI_CH_RECEIVE_DATA_FRAME R11.b0, R11.b1, R11.b2 , R12 ,R13 , R14, df_size ,scratch,scratch1,valid_mask,R3.b0,R3.b1,R3.b2,R3.b3,R5.b0,R5.b1,R5.b2,R5.b3,R6.b1,R6.b2,R6.b3,R7.b1,rx_frames,dmem ;Receive data frame(1 byte) + ;Increment the data bytes captured already by 1 + ADD bytes_filled,bytes_filled,1 +;For handling stop bit after data frame +STOP_BIT_HANDLE_M?: + ;decrementing the expected rx frames by 1 + SUB rx_frames ,rx_frames ,1 + +VALID_BIT_M?: + ;Getting valid bit flag for enabled channel + AND scratch.b0 ,R31.b3 ,valid_mask + ; wait for valid + QBNE VALID_BIT_M?, scratch.b0, valid_mask + MOV R31.b3, scratch.b0 ;clear valid bit + +;As each channel using 3 registers for Rx data. 1 Register is used as intermediate register to load frames received. +; If intermediate register gets full, then its data will be flushed to respective registers assigned for each channel. + ;If Intermediate Reg full , Unload its data to First register of enabled channel as bytes_filled level crosses value 4 + QBEQ LOAD_FIRST_REG_M?,bytes_filled ,4 + ;If Intermediate Reg full , Unload its data to First register of enabled channel as bytes_filled level crosses value 8 + QBEQ LOAD_SECOND_REG_M?,bytes_filled ,8 + ;If Intermediate Reg full , Unload its data to First register of enabled channel as bytes_filled level crosses value 12 + QBEQ LOAD_THIRD_REG_M?,bytes_filled ,12 + +CONTINUE_RX_LOAD_M?: + ;If all frames over, last Unload of intermidiate register needs to be done. + QBEQ END_RX_M?,rx_frames ,0 + ;If frames are left to receive,Jump to receive next frame( Jump to Handle next Start bit) + JMP START_BIT? + +LOAD_FIRST_REG_M?: + ;transferring 4bytes from intermediate to respective channel registers + ;loading CH0, Reg1 + MOV R16,R12 + ;loading CH1, Reg1 + MOV R19,R13 + ;loading CH2, Reg1 + MOV R22,R14 + ;clearing all intermediate registers + ZERO &R12 ,12 + QBEQ END_RX_4_M?, flag ,0 + JMP CONTINUE_RX_LOAD_M? + +LOAD_SECOND_REG_M?: + ;transferring 4bytes from intermediate to respective channel registers + ;loading CH0,Reg2 + MOV R17,R12 + ;loading CH1, Reg2 + MOV R20,R13 + ;loading CH2, Reg2 + MOV R23,R14 + ;clearing all intermediate registers + ZERO &R12 ,12 + ;If flag is 0: Indication of last frame,Rx done. + QBEQ END_RX_4_M?,flag ,0 + JMP CONTINUE_RX_LOAD_M? + +LOAD_THIRD_REG_M?: + ;transferring 4bytes from intermediate to respective channel registers + ;loading CH0, Reg3 + MOV R18,R12 + ;loading CH1, Reg3 + MOV R21,R13 + ;loading CH2, Reg3 + MOV R24,R14 + ;clearing all intermediate registers + ZERO &R12 ,12 + QBEQ END_RX_4_M?, flag ,0 + JMP CONTINUE_RX_LOAD_M? + + +END_RX_M?: + ;As Rx ends here, last bytes present in intermediate register needs to be loaded into respective channel register + LDI flag,0 + QBGT LOAD_FIRST_REG_M?,bytes_filled,4 + QBGT LOAD_SECOND_REG_M?,bytes_filled,8 + QBGT LOAD_THIRD_REG_M?,bytes_filled,12 + +END_RX_4_M?: + .endm + + .endif diff --git a/source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project.js b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project.js new file mode 100644 index 0000000..7522b8b --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; \ No newline at end of file diff --git a/source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project_am243x.js b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project_am243x.js new file mode 100644 index 0000000..0547741 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project_am243x.js @@ -0,0 +1,94 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "tamagawa_main.asm", + "tamagawa_diagnostic.cmd", + "tamagawa_master_hexpru.cmd", + ], +}; + +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../../..", /* Example base */ + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware", + ], +}; + +const defines = { + common: [ + "ENABLE_MULTI_CHANNEL", + ], +}; + +const readmeDoxygenPageTag = "TAMAGAWA_DESIGN"; + +const cflags = { + common: [ + "-v4" + ], +}; + +const lflags = { + common: [ + "--entry_point=TAMAGAWA_INIT", + "--disable_auto_rts", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_hexpru.cmd tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 tamagawa_master_multi_channel_bin.h TamagawaFirmware 4; move tamagawa_master_multi_channel_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_multi_channel_bin.h ;" +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "tamagawa_multi_channel"; + property.isInternal = false; + property.description = "Tamagawa Peripheral Interface" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + property.postBuildSteps = postBuildSteps; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.cflags = cflags; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project_am64x.js b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project_am64x.js new file mode 100644 index 0000000..2b28b44 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/.project/project_am64x.js @@ -0,0 +1,94 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "tamagawa_main.asm", + "tamagawa_diagnostic.cmd", + "tamagawa_master_hexpru.cmd", + ], +}; + +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../../..", /* Example base */ + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware", + ], +}; + +const defines = { + common: [ + "ENABLE_MULTI_CHANNEL", + ], +}; + +const readmeDoxygenPageTag = "TAMAGAWA_DESIGN"; + +const cflags = { + common: [ + "-v4" + ], +}; + +const lflags = { + common: [ + "--entry_point=TAMAGAWA_INIT", + "--disable_auto_rts", + ], +}; + + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_hexpru.cmd tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MCU_PLUS_SDK_PATH}/tools/bin2header/bin2header.exe tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 tamagawa_master_multi_channel_bin.h TamagawaFirmware 4; move tamagawa_master_multi_channel_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_multi_channel_bin.h ;" +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "tamagawa_multi_channel"; + property.isInternal = false; + property.description = "Tamagawa Peripheral Interface" + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "linker"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + property.postBuildSteps = postBuildSteps; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.cflags = cflags; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..535cb62 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,76 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..9179094 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --define=ENABLE_MULTI_CHANNEL --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..aa18ef9 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/multi_channel/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM64X --define=ENABLE_MULTI_CHANNEL --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..d8539e5 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..0ad344b --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..85f3813 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \ + +ASM_SRCS += \ +$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"$(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: $(MCU_PLUS_SDK_PATH)/source/motor_control/position_sense/tamagawa/firmware/single_channel/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM64X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( PRUIMEM, PAGE 0 +} diff --git a/source/motor_control/position_sense/tamagawa/firmware/tamagawa_icss_reg_defs.h b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_icss_reg_defs.h new file mode 100644 index 0000000..2ea0eb5 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_icss_reg_defs.h @@ -0,0 +1,85 @@ +; Copyright (C) 2022 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions + ; are met: + ; + ; Redistributions of source code must retain the above copyright + ; notice, this list of conditions and the following disclaimer. + ; + ; Redistributions in binary form must reproduce the above copyright + ; notice, this list of conditions and the following disclaimer in the + ; documentation and/or other materials provided with the + ; distribution. + ; + ; Neither the name of Texas Instruments Incorporated nor the names of + ; its contributors may be used to endorse or promote products derived + ; from this software without specific prior written permission. + ; + ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ; + + .if !$isdefed("__tamagawa_icss_reg_defs_h") +__tamagawa_icss_reg_defs_h .set 1 + + .include "../../../../pru_io/firmware/common/icss_regs.inc" + .include "../../../../pru_io/firmware/common/icss_cfg_regs.inc" + + .asg R30.t24, TAMAGAWA_CH0_RX_EN + .asg R31.t27, TAMAGAWA_CH0_RX_CLR_OVF + .asg R31.t24, TAMAGAWA_CH0_RX_CLR_VALID + .asg R31.t27, TAMAGAWA_CH0_RX_OVF + .asg R31.t24, TAMAGAWA_CH0_RX_VALID + + .asg R30.t25, TAMAGAWA_CH1_RX_EN + .asg R31.t28, TAMAGAWA_CH1_RX_CLR_OVF + .asg R31.t25, TAMAGAWA_CH1_RX_CLR_VALID + .asg R31.t28, TAMAGAWA_CH1_RX_OVF + .asg R31.t25, TAMAGAWA_CH1_RX_VALID + + .asg R30.t26, TAMAGAWA_CH2_RX_EN + .asg R31.t29, TAMAGAWA_CH2_RX_CLR_OVF + .asg R31.t26, TAMAGAWA_CH2_RX_CLR_VALID + .asg R31.t29, TAMAGAWA_CH2_RX_OVF + .asg R31.t26, TAMAGAWA_CH2_RX_VALID + + +; Channel select bits R30[17:16] +TAMAGAWA_TX_CH0_SEL .set 0 +TAMAGAWA_TX_CH1_SEL .set 1 +TAMAGAWA_TX_CH2_SEL .set 2 + + + .asg R31.t18, TAMAGAWA_TX_CHANNEL_GO + .asg R31.t19, TAMAGAWA_TX_GLOBAL_REINIT + .asg R31.t20, TAMAGAWA_TX_GLOBAL_GO + + .asg R31.t5, TAMAGAWA_CH0_TX_GLOBAL_REINIT_ACTIVE + .asg R31.t5, TAMAGAWA_CH0_TX_BUSY + .asg R31.t0, TAMAGAWA_CH0_TX_OVERUN + .asg R31.t1, TAMAGAWA_CH0_TX_UNDERRUN + + .asg R31.t13, TAMAGAWA_CH1_TX_GLOBAL_REINIT_ACTIVE + .asg R31.t13, TAMAGAWA_CH1_TX_BUSY + .asg R31.t8, TAMAGAWA_CH1_TX_OVERUN + .asg R31.t9, TAMAGAWA_CH1_TX_UNDERRUN + + .asg R31.t21, TAMAGAWA_CH2_TX_GLOBAL_REINIT_ACTIVE + .asg R31.t21, TAMAGAWA_CH2_TX_BUSY + .asg R31.t16, TAMAGAWA_CH2_TX_OVERUN + .asg R31.t17, TAMAGAWA_CH2_TX_UNDERRUN + + +; TAMAGAWA + + .endif diff --git a/source/motor_control/position_sense/tamagawa/firmware/tamagawa_interface.h b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_interface.h new file mode 100644 index 0000000..19cbc98 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_interface.h @@ -0,0 +1,75 @@ +; Copyright (C) 2022 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions + ; are met: + ; + ; Redistributions of source code must retain the above copyright + ; notice, this list of conditions and the following disclaimer. + ; + ; Redistributions in binary form must reproduce the above copyright + ; notice, this list of conditions and the following disclaimer in the + ; documentation and/or other materials provided with the + ; distribution. + ; + ; Neither the name of Texas Instruments Incorporated nor the names of + ; its contributors may be used to endorse or promote products derived + ; from this software without specific prior written permission. + ; + ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ; + + + .if !$isdefed("__tamagawa_interface_h") +__tamagawa_interface_h .set 1 + +TAMAGAWA_OPMODE_CONFIG_OFFSET .set 0x0 +TAMAGAWA_CHANNEL_CONFIG_OFFSET .set 0x1 ;/* Select single channel (1, 2, 3 or Multi (0))- Not implemented yet*/ +TAMAGAWA_INTFC_CMD_TRIGGER_OFFSET .set 0x2 ;/* Command trigger indication to firmware*/ +TAMAGAWA_INTFC_CMD_STATUS_OFFSET .set 0x3 ;/* Status word for channel busy indication etc - Not used now*/ + +TAMAGAWA_WORD_0_OFFSET .set 0x4 ;/*Tx Data without start and stop bits*/ +TAMAGAWA_WORD_1_OFFSET .set 0x8 ;/*No. of Tx frames,Rx frames expected (first byte is Tx frames second is Rx frames)*/ + +TAMAGAWA_CH0_POSITION_DATA_WORD0_OFFSET .set 0xC ;/*Rx position data for ch0 */ +TAMAGAWA_CH0_POSITION_DATA_WORD1_OFFSET .set 0x10 ; +TAMAGAWA_CH0_POSITION_DATA_WORD2_OFFSET .set 0x14 ; +TAMAGAWA_CH0_CRC_OFFSET .set 0x18 + +TAMAGAWA_CH1_POSITION_DATA_WORD0_OFFSET .set 0x1C ;/*Rx position data for ch1 */ +TAMAGAWA_CH1_POSITION_DATA_WORD1_OFFSET .set 0x20 ; +TAMAGAWA_CH1_POSITION_DATA_WORD2_OFFSET .set 0x24 ; +TAMAGAWA_CH1_CRC_OFFSET .set 0x28 ; + +TAMAGAWA_CH2_POSITION_DATA_WORD0_OFFSET .set 0x2C ;/*Rx position data for ch2 */ +TAMAGAWA_CH2_POSITION_DATA_WORD1_OFFSET .set 0x30 ; +TAMAGAWA_CH2_POSITION_DATA_WORD2_OFFSET .set 0x34 ; +TAMAGAWA_CH2_CRC_OFFSET .set 0x38 ; + +TAMAGAWA_CHANNEL_MASK_OFFSET .set 0x3C ;/*mask for getting what channels are required*/ + +TAMAGAWA_RX_DIV_FACTOR_OFFSET .set 0x40 ;/*rx divide factor offset*/ +TAMAGAWA_TX_DIV_FACTOR_OFFSET .set 0x44 ;/*tx divide factor offset*/ +TAMAGAWA_OVERSAMPLE_RATE_OFFSET .set 0x48 ;/*oversample rate offset*/ + +TAMAGAWA_EEPROM_CMD_OFFSET .set 0x68 ;/*tamagawa eeprom command id offset*/ +TAMAGAWA_EEPROM_ADF_OFFSET .set 0x6C ;/*tamagawa eeprom adf offset*/ +TAMAGAWA_EEPROM_EDF_OFFSET .set 0x70 ;/*tamagawa eeprom edf offset*/ +TAMAGAWA_EEPROM_CRC_OFFSET .set 0x74 ;/*tamagawa eeprom crc offset*/ +TAMAGAWA_EEPROM_TX_CMD_0_CH0 .set 0x88 ;/*tamagawa eeprom tx command offset for bytes 0-3 for channel 0*/ +TAMAGAWA_EEPROM_TX_CMD_1_CH0 .set 0x8C ;/*tamagawa eeprom tx command offset for bytes 4-7 for channel 0*/ +TAMAGAWA_EEPROM_TX_CMD_0_CH1 .set 0xB0 ;/*tamagawa eeprom tx command offset for bytes 0-3 for channel 1*/ +TAMAGAWA_EEPROM_TX_CMD_1_CH1 .set 0xB4 ;/*tamagawa eeprom tx command offset for bytes 4-7 for channel 1*/ +TAMAGAWA_EEPROM_TX_CMD_0_CH2 .set 0xD8 ;/*tamagawa eeprom tx command offset for bytes 0-3 for channel 2*/ +TAMAGAWA_EEPROM_TX_CMD_1_CH2 .set 0xDC ;/*tamagawa eeprom tx command offset for bytes 4-7 for channel 2*/ + .endif diff --git a/source/motor_control/position_sense/tamagawa/firmware/tamagawa_main.asm b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_main.asm new file mode 100644 index 0000000..c63c50f --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_main.asm @@ -0,0 +1,558 @@ + +; Copyright (C) 2022 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions + ; are met: + ; + ; Redistributions of source code must retain the above copyright + ; notice, this list of conditions and the following disclaimer. + ; + ; Redistributions in binary form must reproduce the above copyright + ; notice, this list of conditions and the following disclaimer in the + ; documentation and/or other materials provided with the + ; distribution. + ; + ; Neither the name of Texas Instruments Incorporated nor the names of + ; its contributors may be used to endorse or promote products derived + ; from this software without specific prior written permission. + ; + ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ; + +CALL .macro function + JAL R8.w0, function + .endm +RET .macro + JMP R8.w0 + .endm + +CALL2 .macro function + JAL R8.w2, function + .endm +RET2 .macro + JMP R8.w2 + .endm + + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;/ +; Assembler Directives Section +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;/ + .sect ".text" + .retain ; Required for building .out with assembly file + .retainrefs ; Required for building .out with assembly file + .global TAMAGAWA_INIT + .global FN_SEND + .global FN_SEND_WAIT_TILL_TX_CH_BUSY + .global CALL + .global CALL2 + +; file: tamagawa_main.asm +; +; brief: Tamagawa protocol Interface + +;************************************* includes ************************************* + + .include "tamagawa_icss_reg_defs.h" + .include "tamagawa_interface.h" + .include "..\..\..\..\pru_io\firmware\common\icss_regs.inc" + .include "single_ch_receive_frames.h" + .include "multi_ch_receive_frames.h" + .include "firmware_version.h" + .include "tamagawa_send.h" + .include "eeprom_read.h" + .include "eeprom_write.h" + + .asg R28, SCRATCH + .asg R29, SCRATCH1 + .asg R7.b0, TAMAGAWA_ENABLE_CHx + .asg c25, PRUx_DMEM + + .asg R27.b0, TX_DATA0 + .asg R27.b1, TX_DATA1 + .asg R1.b1, TX_FRAMES + .asg R6.b0, RX_FRAMES + + +;********************** +;* MAIN * +;********************** + +main: + ;Required for the firmware_version.h file + .word ICSS_FIRMWARE_RELEASE_1, ICSS_FIRMWARE_RELEASE_2 +TAMAGAWA_INIT: + + ;If PRU0 is defined in symbols, it will select all PRU0 CFG registers. + .if $isdefed("PRU0") + ;Data Memory address for PRU0 is loaded in PRUx_DMEM + .asg PRU0_DMEM, PRUx_DMEM + .asg ICSS_CFG_PRU0_ED_CH0_CFG1, ICSS_CFG_PRUx_ED_CH0_CFG1 + .asg ICSS_CFG_PRU0_ED_CH1_CFG1, ICSS_CFG_PRUx_ED_CH1_CFG1 + .asg ICSS_CFG_PRU0_ED_CH2_CFG1, ICSS_CFG_PRUx_ED_CH2_CFG1 + .asg ICSS_CFG_PRU0_ED_CH0_CFG0, ICSS_CFG_PRUx_ED_CH0_CFG0 + .asg ICSS_CFG_PRU0_ED_CH1_CFG0, ICSS_CFG_PRUx_ED_CH1_CFG0 + .asg ICSS_CFG_PRU0_ED_CH2_CFG0, ICSS_CFG_PRUx_ED_CH2_CFG0 + .asg ICSS_CFG_PRU0_ED_TXCFG, ICSS_CFG_PRUx_ED_TXCFG + .asg ICSS_CFG_PRU0_ED_RXCFG, ICSS_CFG_PRUx_ED_RXCFG + .endif + + ;If PRU1 is defined in symbols, it will select all PRU1 CFG registers. + .if $isdefed("PRU1") + ;Data Memory address for PRU1 is loaded in PRUx_DMEM + .asg PRU1_DMEM, PRUx_DMEM + .asg ICSS_CFG_PRU1_ED_CH0_CFG1, ICSS_CFG_PRUx_ED_CH0_CFG1 + .asg ICSS_CFG_PRU1_ED_CH1_CFG1, ICSS_CFG_PRUx_ED_CH1_CFG1 + .asg ICSS_CFG_PRU1_ED_CH2_CFG1, ICSS_CFG_PRUx_ED_CH2_CFG1 + .asg ICSS_CFG_PRU1_ED_CH0_CFG0, ICSS_CFG_PRUx_ED_CH0_CFG0 + .asg ICSS_CFG_PRU1_ED_CH1_CFG0, ICSS_CFG_PRUx_ED_CH1_CFG0 + .asg ICSS_CFG_PRU1_ED_CH2_CFG0, ICSS_CFG_PRUx_ED_CH2_CFG0 + .asg ICSS_CFG_PRU1_ED_TXCFG, ICSS_CFG_PRUx_ED_TXCFG + .asg ICSS_CFG_PRU1_ED_RXCFG, ICSS_CFG_PRUx_ED_RXCFG + .endif + + ; Initalize ENDAT mode + ; ICSS_CFG.GPCFG1[27:26] = 1 + LDI R0.b0, 4 + ;It will initialize Endat Mode for PRU1 + SBCO &R0.b0, ICSS_CFG, ICSS_CFG_GPCFG1+3, 1 + + ; Initialize PRUx_TAMAGAWA_CH0_CFG0/1 by clearing all channel CFG registers + ZERO &R0, 4 + + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH0_CFG0 + SBCO &R0, ICSS_CFG, SCRATCH1.w0, 4 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH1_CFG0 + SBCO &R0, ICSS_CFG, SCRATCH1.w0, 4 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH2_CFG0 + SBCO &R0, ICSS_CFG, SCRATCH1.w0, 4 + + ; clear all registers + ZERO &R0, 120 + + ; (Channel Mask) Record channel enabled by host, save it after zeroing registers (done above) + LBCO &TAMAGAWA_ENABLE_CHx, PRUx_DMEM, TAMAGAWA_CHANNEL_CONFIG_OFFSET, 1 + + .if $defined("ENABLE_MULTI_CHANNEL")=0 + ; if no channel selected,set channel mask default to ch0 + ; if more than 1 channel selected,set channel mask default to ch0 + AND TAMAGAWA_ENABLE_CHx, TAMAGAWA_ENABLE_CHx, 0x7 + QBEQ TAMAGAWA_DEFAULT_CH, TAMAGAWA_ENABLE_CHx, 0x7 + QBEQ TAMAGAWA_DEFAULT_CH, TAMAGAWA_ENABLE_CHx, 0 + JMP TAMAGAWA_SKIP_DEFAULT_CH +TAMAGAWA_DEFAULT_CH: + LDI TAMAGAWA_ENABLE_CHx, 0x1 +TAMAGAWA_SKIP_DEFAULT_CH: + .endif + ;setting Rx and Tx clocks +TAMAGAWA_SET_CLOCK: + ;Set the TX Div Factor value based on the value of RX_CLK + ;div factor = 10 for RX_CLK: 8*2.5 MHz and div factor = 5 for RX_CLK: 8*5 MHz + LBCO &R0.w0, PRUx_DMEM, TAMAGAWA_RX_DIV_FACTOR_OFFSET, 2 + ;Set the RX Div Factor value based on the value of TX_CLK + ;div factor = 80 for TX_CLK: 2.5 MHz and div factor = 40 for TX_CLK: 5 Mhz + LBCO &R0.w2, PRUx_DMEM, TAMAGAWA_TX_DIV_FACTOR_OFFSET , 2 + ;8x oversample rate + LBCO &R1.b0, PRUx_DMEM, TAMAGAWA_OVERSAMPLE_RATE_OFFSET , 1 + ;Set clock to 2.5Mhz or 5MHz + CALL FN_SET_TX_CLK + +TAMAGAWA_SKIP_INIT_SUCCESS: + LDI R0.b0, 1 + ;Initialization successful status update ends here + SBCO &R0.b0, PRUx_DMEM, TAMAGAWA_INTFC_CMD_STATUS_OFFSET, 1 + LBCO &R0.b0, PRUx_DMEM, TAMAGAWA_OPMODE_CONFIG_OFFSET, 1 + ;If opmode=1, Host trigger is done + ;If opmode=0, Periodic trigger is done + QBNE HANDLE_HOST_TRIGGER_MODE, R0.b0, 0 + +HANDLE_HOST_TRIGGER_MODE: + ;If Host Trigger=1, request made by R5F to Firmware, now Firmware do processing and when done set trigger to 0 so that R5F application can act further. + LBCO &R0.b0, PRUx_DMEM, TAMAGAWA_INTFC_CMD_TRIGGER_OFFSET, 1 + ;wait till host trigger is set to 1. + QBEQ HANDLE_HOST_TRIGGER_MODE, R0.b0, 0 + ;load Tx data which will be loaded in Tx FIFO. + LBCO &TX_DATA0, PRUx_DMEM, TAMAGAWA_WORD_0_OFFSET, 1 + ;load Tx data which will be loaded in Tx FIFO. + LBCO &TX_DATA1, PRUx_DMEM, TAMAGAWA_WORD_0_OFFSET+1, 1 + ;load Tx frames expected + LBCO &TX_FRAMES , PRUx_DMEM, TAMAGAWA_WORD_1_OFFSET, 1 + ; load Rx frames expected + LBCO &RX_FRAMES , PRUx_DMEM, TAMAGAWA_WORD_1_OFFSET+1 , 1 + ;Call SEND RECEIVE FUNCTION + CALL FN_SEND_RECEIVE_TAMAGAWA + +TAMAGAWA_HOST_CMD_END: + LDI R3.w0, 0 + ;Clear Host Trigger + SBCO &R3.b0, PRUx_DMEM, TAMAGAWA_INTFC_CMD_TRIGGER_OFFSET, 1 + ;Handle next Position request by user. + JMP HANDLE_HOST_TRIGGER_MODE + + +;****************************************************************************************************************************************************** +; Function: FN_SEND_RECEIVE_TAMAGAWA +; +; Brief: +; 1.Select Channels +; 2.Load Tx fifo for currently selected channel by using EEPROM_READ_MACRO, EEPROM_WRITE_MACRO and TAMAGAWA_SEND_MACRO for EEPROM Read, EEPROM Write and non-EEPROM commands respectively. +; 3.Perform step 2 till all channels which are enabled are selected and their Tx FIFO is loaded. +; 4.Call FN_SEND to transmit Fifo data in different modes based on the command. +; 5.Receive data. For multi-channel, RECEIVE_FRAMES_M macro is called. For single channel, RECEIVE_FRAMES_S macro is called. +; 6.Transfer Rx data stored in Channel Registers to Tamagawa Interface variable having offset- TAMAGAWA_CHx_POSITION_DATA_WORD0_OFFSET +; Registers: +; R26.b3: Holds the value of the command id +; R30.w2: For Select Channel +; R30.b0: Load Tx fifo for selected channel +; +; Parameters: +; R11-R24: Registers used in macros for Rx data. +; R2.b1 : Rx Dataframe size +; R4.b1 : bytes_filled level +; R4.b2 : flag(explained further) +; +; ********************************************************************************************************************************************************* + + +FN_SEND_RECEIVE_TAMAGAWA: +;Select Channel (R30[17:16] tx_ch_sel) to push data into respective Tx Fifo. +;R30[17:16] tx_ch_sel=0 :Channel 0 selected +; =1: Channel 1 selected +; =2: Channel 2 selected + ;If channel 0 is asked by user,continue further + QBBC TAMAGAWA_SKIP25_CH0, TAMAGAWA_ENABLE_CHx, 0 + ;Select Channel 0 + LDI R30.w2, TAMAGAWA_TX_CH0_SEL +TAMAGAWA_SKIP25_CH0: + ;If channel 1 is asked by user,continue further + QBBC TAMAGAWA_SKIP25_CH1, TAMAGAWA_ENABLE_CHx, 1 + ;Select Channel 1 + LDI R30.w2, TAMAGAWA_TX_CH1_SEL +TAMAGAWA_SKIP25_CH1: + ;If channel 2 is asked by user,continue further + QBBC TAMAGAWA_SKIP25_CH2, TAMAGAWA_ENABLE_CHx, 2 + ;Select Channel 2 + LDI R30.w2, TAMAGAWA_TX_CH2_SEL +TAMAGAWA_SKIP25_CH2: + ;Clear the R10 register to store the channel number + ZERO &R10, 4 + ;Store the channel number from R30.b2 to R10.b0 + MOV R10.b0, R30.b2 + + ;Clear the R25 and R26 registers + ZERO &R25, 8 + ;Load the value of the type of command into R26.b3 + LBCO &R26.b3, PRUx_DMEM, TAMAGAWA_EEPROM_CMD_OFFSET, 1 + ;If the command is EEPROM Read, jump to EEPROM_READ and continue forward + QBEQ EEPROM_READ, R26.b3, EEPROM_READ_CMD_ID + ;If the command is EEPROM Write, jump to EEPROM_READ and continue forward + QBEQ EEPROM_WRITE, R26.b3, EEPROM_WRITE_CMD_ID + +FN_SEND_START: + TAMAGAWA_SEND_MACRO TX_DATA0, TX_DATA1 + ;Jump to the end of section where we send Tx data + JMP TX_END + +EEPROM_READ: + EEPROM_READ_MACRO TAMAGAWA_ENABLE_CHx, PRUx_DMEM + ;Jump to the end of section where we send Tx data + JMP TX_END + +EEPROM_WRITE: + EEPROM_WRITE_MACRO TAMAGAWA_ENABLE_CHx, PRUx_DMEM + +TX_END: + + ;R11-R24 used for Rx + ZERO &R11, 60 + ZERO &R3, 4 + ZERO &R5, 4 + AND R6,R6, 0xFF + AND R7,R7, 0xFF + ;dataframe size(8 in tamagawa) + LDI R2.b1, 8 + ;bytes_filled (no. of frames or bytes received) + LDI R4.b1, 0 + ;flag for loading last register for respective channels(initially 1) + LDI R4.b2, 1 + + .if $defined("ENABLE_MULTI_CHANNEL") +MULTI_CHANNEL_RECEIVE: + ;enable Rx for channel 0 + SET R30,R30.t24 + ;enable Rx for channel 1 + SET R30,R30.t25 + ;enable Rx for channel 2 + SET R30,R30.t26 + + RECEIVE_FRAMES_M R2.b1 ,R4.b1 , RX_FRAMES , R4.b2 , SCRATCH, SCRATCH1,TAMAGAWA_ENABLE_CHx,PRUx_DMEM +CH0_RX_TO_INTERFACE: + ;If channel 0 enabled,then load Rx data to tamagawa interface + QBBC CH1_RX_TO_INTERFACE, TAMAGAWA_ENABLE_CHx,0 + ;storing Channel 0 Rx data to Tamagawa Interface created in R5F application + SBCO &R16, PRUx_DMEM, TAMAGAWA_CH0_POSITION_DATA_WORD0_OFFSET, 12 +CH1_RX_TO_INTERFACE: + ;If channel 0 enabled,then load Rx data to tamagawa interface + QBBC CH2_RX_TO_INTERFACE, TAMAGAWA_ENABLE_CHx,1 + ;storing Channel 1 Rx data to Tamagawa Interface created in R5F application + SBCO &R19, PRUx_DMEM, TAMAGAWA_CH1_POSITION_DATA_WORD0_OFFSET, 12 +CH2_RX_TO_INTERFACE: + ;If channel 0 enabled,then load Rx data to tamagawa interface + QBBC INTERFACE_LOADED, TAMAGAWA_ENABLE_CHx,2 + ;storing Channel 2 Rx data to Tamagawa Interface created in R5F application + SBCO &R22, PRUx_DMEM, TAMAGAWA_CH2_POSITION_DATA_WORD0_OFFSET, 12 + +INTERFACE_LOADED: + + .else +SINGLE_CHANNEL_RECEIVE: + ZERO &R3,4 +CHECK_CH0: + ;If channel 0 enabled, start Rx for channel 0 + QBBC CHECK_CH1, TAMAGAWA_ENABLE_CHx,0 + ;enable Rx for channel 0 + SET R30,R30.t24 + ;4 is mid bit no. for rx oversample data for channel 0 + RECEIVE_FRAMES_S R2.b1,R4.b1,RX_FRAMES,R4.b2,SCRATCH, SCRATCH1,0x1,4,R3.b0,PRUx_DMEM,TAMAGAWA_CH0_CRC_OFFSET + ;storing Channel 0 Rx data to Tamagawa Interface created in R5F application + SBCO &R16, PRUx_DMEM, TAMAGAWA_CH0_POSITION_DATA_WORD0_OFFSET, 12 +CHECK_CH1: + ;If channel 1 enabled, start Rx for channel 1 + QBBC CHECK_CH2, TAMAGAWA_ENABLE_CHx,1 + ;enable Rx for channel 1 + SET R30,R30.t25 + ; 4+8 is mid bit no. for rx oversample data for channel 1 + RECEIVE_FRAMES_S R2.b1,R4.b1,RX_FRAMES,R4.b2,SCRATCH, SCRATCH1,0x2,4+8,R3.b0,PRUx_DMEM,TAMAGAWA_CH1_CRC_OFFSET + ;storing Channel 1 Rx data to Tamagawa Interface created in R5F application + SBCO &R16, PRUx_DMEM, TAMAGAWA_CH1_POSITION_DATA_WORD0_OFFSET, 12 +CHECK_CH2: + ;If channel 0 enabled, start Rx for channel 2 + QBBC ALL_CHANNEL_DONE, TAMAGAWA_ENABLE_CHx,2 + ;enable Rx for channel 2 + SET R30,R30.t26 + ; 4+16 is mid bit no. for rx oversample data for channel 2 + RECEIVE_FRAMES_S R2.b1,R4.b1,RX_FRAMES,R4.b2,SCRATCH, SCRATCH1,0x4,4+16,R3.b0,PRUx_DMEM,TAMAGAWA_CH2_CRC_OFFSET + ;storing Channel 2 Rx data to Tamagawa Interface created in R5F application + SBCO &R16, PRUx_DMEM, TAMAGAWA_CH2_POSITION_DATA_WORD0_OFFSET, 12 +ALL_CHANNEL_DONE: + + .endif + + RET + + + +;**************************************************************************************************** +; Function: FN_SEND +; +; Brief: +; 1.Select Rx,Tx frames size based on the command id +; 2.Wait till Tx is busy for particular channel +; 3.For triggering Tx to transmit FIFO data, CHANNEL_GO is set for single channel, GLOBAL_GO is set for multi channel +; Registers: +; ICSS_CFG_PRUx_ED_CHx_CFG0[15:11] - for selecting Tx frame size +; ICSS_CFG_PRUx_ED_CHx_CFG0[27:16] - for selecting Rx frame size +; ICSS_CFG_PRUx_ED_TXCFG - for asserting Tx Go to issue new Tx frame +; R31 - For setting CHANNEL_GO and GLOBAL_GO +; Parameters: +; R2.w1 : Rx frame size +; +; *************************************************************************************************** + +FN_SEND: + ; Program tx_frame_size ICSS_CFG_PRUx_ED_CH0_CFG0[15:11] to 10 + ; Program rx_frame_size in ICSS_CFG_PRUx_ED_CH0_CFG0[27:16] to 110 + ; loading rx frame size to maximum bits we can receive from tamagawa encoder for a particular command ID + LDI R2.w1 , 110 + ; if channel 0 is enabled, updation of frame sizes will be done. + QBBC TAMAGAWA_SKIP15_CH0, TAMAGAWA_ENABLE_CHx, 0 + ;loading PRUx_ED_CFG0 Register for updating Tx frame size + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH0_CFG0+1 + LBCO &R2.b0, ICSS_CFG, SCRATCH1.w0, 1 + ;In order to clear the previous value of Tx frame size + AND R2.b0 , R2.b0 , BIT_CLEAR_MASK + ;In case of non-EEPROM commands, use single shot mode with Tx frame size = 10 + QBEQ SINGLESHOT10_CH0, R26.b3, NON_EEPROM_CMD_ID + ;In case of EEPROM Read command, use single shot mode with Tx frame size = 30 + QBEQ SINGLESHOT30_CH0, R26.b3, EEPROM_READ_CMD_ID + ;In case of EEPROM Write command, use the Tx Continuous FIFO loading + QBEQ CONTINUOUS_MODE0, R26.b3, EEPROM_WRITE_CMD_ID +SINGLESHOT10_CH0: + ;10 is used for selecting Tx frame size for channel 0 + OR R2.b0 , R2.b0 , (NON_EEPROM_TX_FRAME_SIZE<<3) + JMP TXSIZE0_END + +SINGLESHOT30_CH0: + ;30 is used for selecting Tx frame size for channel 0 + OR R2.b0 , R2.b0 , (EEPROM_READ_TX_FRAME_SIZE<<3) + JMP TXSIZE0_END + +CONTINUOUS_MODE0: + ;In case of EEPROM Write Command, use Tx Continuous FIFO loading + AND R2.b0 , R2.b0 , (EEPROM_WRITE_TX_FRAME_SIZE<<3) +TXSIZE0_END: + + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH0_CFG0+1 + ; store Tx frame size to ICSS_CFG_PRUx_ED_CH0 for channel 0 + SBCO &R2, ICSS_CFG, SCRATCH1.w0, 1 + ;Loading Rx frame size + MOV SCRATCH.w0, R2.w1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH0_CFG0+2 + ;store rx frame size for channel 0 in ICSS_CFG_PRUx_ED_CH0 + SBCO &SCRATCH.w0, ICSS_CFG, SCRATCH1.w0, 2 + +TAMAGAWA_SKIP15_CH0: + ; if channel 1 is enabled, updation of frame sizes will be done. + QBBC TAMAGAWA_SKIP15_CH1, TAMAGAWA_ENABLE_CHx, 1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH1_CFG0+1 + LBCO &R2.b0, ICSS_CFG, SCRATCH1.w0, 1 + + ;In order to clear the previous value of Tx frame size + AND R2.b0 , R2.b0 , BIT_CLEAR_MASK + ;In case of non-EEPROM commands, use single shot mode with Tx frame size = 10 + QBEQ SINGLESHOT10_CH1, R26.b3, NON_EEPROM_CMD_ID + ;In case of EEPROM Read command, use single shot mode with Tx frame size = 30 + QBEQ SINGLESHOT30_CH1, R26.b3, EEPROM_READ_CMD_ID + ;In case of EEPROM Write command, use the Tx Continuous FIFO loading + QBEQ CONTINUOUS_MODE1, R26.b3, EEPROM_WRITE_CMD_ID + +SINGLESHOT10_CH1: + ;10 is used for selecting Tx frame size for channel 1 + OR R2.b0 , R2.b0 , (NON_EEPROM_TX_FRAME_SIZE<<3) + JMP TXSIZE1_END + +SINGLESHOT30_CH1: + ;30 is used for selecting Tx frame size for channel 1 + OR R2.b0 , R2.b0 , (EEPROM_READ_TX_FRAME_SIZE<<3) + JMP TXSIZE1_END + +CONTINUOUS_MODE1: + ;In case of EEPROM Write Command, use Tx Continuous FIFO loading + AND R2.b0 , R2.b0 , (EEPROM_WRITE_TX_FRAME_SIZE<<3) +TXSIZE1_END: + + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH1_CFG0+1 + ; store Tx frame size to ICSS_CFG_PRUx_ED_CH1 for channel 1 + SBCO &R2, ICSS_CFG, SCRATCH1.w0, 1 + + MOV SCRATCH.w0, R2.w1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH1_CFG0+2 + ;store rx frame size for channel 1 in ICSS_CFG_PRUx_ED_CH1 + SBCO &SCRATCH.w0, ICSS_CFG, SCRATCH1.w0, 2 + +TAMAGAWA_SKIP15_CH1: + ; if channel 2 is enabled, updation of frame sizes will be done. + QBBC TAMAGAWA_SKIP15_CH2, TAMAGAWA_ENABLE_CHx, 2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH2_CFG0+1 + LBCO &R2.b0, ICSS_CFG, SCRATCH1.w0, 1 + + ;In order to clear the previous value of Tx frame size + AND R2.b0 , R2.b0 , BIT_CLEAR_MASK + ;In case of non-EEPROM commands, use single shot mode with Tx frame size = 10 + QBEQ SINGLESHOT10_CH2, R26.b3, NON_EEPROM_CMD_ID + ;In case of EEPROM Read command, use single shot mode with Tx frame size = 30 + QBEQ SINGLESHOT30_CH2, R26.b3, EEPROM_READ_CMD_ID + ;In case of EEPROM Write command, use the Tx Continuous FIFO loading + QBEQ CONTINUOUS_MODE2, R26.b3, EEPROM_WRITE_CMD_ID + +SINGLESHOT10_CH2: + ;10 is used for selecting Tx frame size for channel 2 + OR R2.b0 , R2.b0 , (NON_EEPROM_TX_FRAME_SIZE<<3) + JMP TXSIZE2_END + +SINGLESHOT30_CH2: + ;30 is used for selecting Tx frame size for channel 2 + OR R2.b0 , R2.b0 , (EEPROM_READ_TX_FRAME_SIZE<<3) + JMP TXSIZE2_END + +CONTINUOUS_MODE2: + ;In case of EEPROM Write Command, use Tx Continuous FIFO loading + AND R2.b0 , R2.b0 , (EEPROM_WRITE_TX_FRAME_SIZE<<3) +TXSIZE2_END: + + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH2_CFG0+1 + ;store Tx frame size to ICSS_CFG_PRUx_ED_CH2 for channel 2 + SBCO &R2, ICSS_CFG, SCRATCH1.w0, 1 + + MOV SCRATCH.w0, R2.w1 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_CH2_CFG0+2 + ;store rx frame size for channel 2 in ICSS_CFG_PRUx_ED_CH2 + SBCO &SCRATCH.w0, ICSS_CFG, SCRATCH1.w0, 2 + +TAMAGAWA_SKIP15_CH2: + + + +FN_SEND_WAIT_TILL_TX_CH_BUSY: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_TXCFG + LBCO &R2.b3, ICSS_CFG, SCRATCH1.w0, 1 + ; Determines when you can assert tx go to issue a new TX frame + .if $defined("ENABLE_MULTI_CHANNEL") + + ; TODO : Assumption is that all 3 channels are enabled + AND R2.b3, R2.b3, 0xE0 + QBNE FN_SEND_WAIT_TILL_TX_CH_BUSY, R2.b3, 0 + .else + QBBC TAMAGAWA_SKIP17_CH0, TAMAGAWA_ENABLE_CHx, 0 + ; Wait till Ch0 is busy + QBBS FN_SEND_WAIT_TILL_TX_CH_BUSY, R2.b3, 5 +TAMAGAWA_SKIP17_CH0: + QBBC TAMAGAWA_SKIP17_CH1, TAMAGAWA_ENABLE_CHx, 1 + ; Wait till Ch1 is busy + QBBS FN_SEND_WAIT_TILL_TX_CH_BUSY, R2.b3, 6 +TAMAGAWA_SKIP17_CH1: + QBBC TAMAGAWA_SKIP17_CH2, TAMAGAWA_ENABLE_CHx, 2 + ; Wait till Ch2 is busy + QBBS FN_SEND_WAIT_TILL_TX_CH_BUSY, R2.b3, 7 +TAMAGAWA_SKIP17_CH2: + .endif + + .if $defined("ENABLE_MULTI_CHANNEL") + SET R31, TAMAGAWA_TX_GLOBAL_GO + .else + + SET R31, TAMAGAWA_TX_CHANNEL_GO + .endif + + RET2 + +;**************************************************************************************************** +; Function: FN_SET_TX_CLK +; +; Brief: Setting clock/baud rate for Tx and Rx (currently set for 2.5MHZ/2.5Mbps) +; Registers: +; ICSS_CFG_PRUx_ED_RXCFG -for setting rx clock, selecting ICSSG clock(200Mhz) +; ICSS_CFG_PRUx_ED_TXCFG - for setting tx clock +; Parameters: +; R0.w0 - DIV for RX_CLK +; R0.w2 - DIV for TX_CLK +; R1.b0 - Oversample rate for RX +; +; *************************************************************************************************** + +FN_SET_TX_CLK: + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_RXCFG+2 + ;div factor for rx = 10 or 5 based on the baud rate (value written in register is 9 or 4 respectively) + SBCO &R0.w0, ICSS_CFG, SCRATCH1.w0, 2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_TXCFG+2 + ;div factor for tx =80 or 40 based on the baud rate(value written in register is 79 or 40 respectively) + SBCO &R0.w2, ICSS_CFG, SCRATCH1.w0, 2 + LDI SCRATCH1.w0, ICSS_CFG_PRUx_ED_RXCFG + + ; For using ICSSG clock(200Mhz) + SET R1.t4 + + ; Update ICSSG clock and oversampling value + SBCO &R1.b0, ICSS_CFG, SCRATCH1.w0, 1 + RET diff --git a/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_hexpru.cmd b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_hexpru.cmd new file mode 100644 index 0000000..8d1cd0a --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_hexpru.cmd @@ -0,0 +1,3 @@ +-b +-map=tamagawa_pru_3_channel.map +SECTIONS {.text} diff --git a/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_multi_channel_bin.h b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_multi_channel_bin.h new file mode 100644 index 0000000..caec66e --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_multi_channel_bin.h @@ -0,0 +1,377 @@ +/* + * tamagawa_master_multi_channel_bin.h + * + * + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int TamagawaFirmware[]= { +0x00000208, +0x00010000, +0x24000400, +0x810f0400, +0x2eff8180, +0x2401089d, +0x809d2480, +0x2401109d, +0x809d2480, +0x2401189d, +0x809d2480, +0x2effbb80, +0x91011807, +0x91401880, +0x914418c0, +0x91481801, +0x23013888, +0x24000100, +0x81031800, +0x91001800, +0x69000001, +0x91021800, +0x570000ff, +0x9104181b, +0x9105183b, +0x91081821, +0x91091806, +0x23001f88, +0x24000083, +0x81021803, +0x21001500, +0xc9000702, +0x240000de, +0xc9010702, +0x240001de, +0xc9020702, +0x240002de, +0x2eff818a, +0x105e5e0a, +0x2eff8399, +0x9168187a, +0x51087a08, +0x51047a1f, +0x31020004, +0x101b1b1e, +0x103b3b1e, +0x05015e5e, +0x2300fec8, +0x21008f00, +0x31020016, +0xc9000705, +0x11035e1a, +0x69001a03, +0x2400881a, +0x21004100, +0xc9010705, +0x11035e1a, +0x69011a03, +0x2400b01a, +0x21004100, +0xc9020705, +0x11035e1a, +0x69021a03, +0x2400d81a, +0x21004100, +0x901a3899, +0x1079791e, +0x1059591e, +0x1039391e, +0x1019191e, +0x05015e5e, +0x2300fec8, +0x21008f00, +0x31020026, +0xc900070c, +0x11035e1a, +0x69001a0a, +0x24008c1a, +0x901a1819, +0x1019191e, +0x2400881a, +0x901a3899, +0x1079791e, +0x1059591e, +0x1039391e, +0x21006e00, +0xc901070c, +0x11035e1a, +0x69011a0a, +0x2400b41a, +0x901a1819, +0x1019191e, +0x2400b01a, +0x901a3899, +0x1079791e, +0x1059591e, +0x1039391e, +0x21006e00, +0xc902070c, +0x11035e1a, +0x69021a0a, +0x2400dc1a, +0x901a1819, +0x1019191e, +0x2400d81a, +0x901a3899, +0x1079791e, +0x1059591e, +0x1039391e, +0x21006e00, +0x05015e5e, +0x2300fec8, +0x2eff819a, +0x100a0a5e, +0x3102001d, +0xc9000709, +0x11035e1a, +0x69001a07, +0x111c1f1a, +0x4f0c1afc, +0x2400881a, +0x901a1819, +0x1019191e, +0x21008e00, +0xc9010709, +0x11035e1a, +0x69011a07, +0x111c3f1a, +0x4f0c1afc, +0x2400b01a, +0x901a1819, +0x1019191e, +0x21008e00, +0xc9020709, +0x11035e1a, +0x69021a07, +0x111c5f1a, +0x4f0c1afc, +0x2400d81a, +0x901a1819, +0x1019191e, +0x21008e00, +0x05015e5e, +0x2eff9d8b, +0x2eff8183, +0x2eff8185, +0x11ffe6e6, +0x11ffe7e7, +0x24000822, +0x24000024, +0x24000144, +0x1f18fefe, +0x1f19fefe, +0x1f1afefe, +0x10077f1c, +0x6e071cff, +0x101c1c7f, +0x0908ecec, +0x0908eded, +0x0908eeee, +0x30220010, +0x0b010b0b, +0x0b012b2b, +0x0b014b4b, +0x10077f1c, +0x6e071cff, +0xd104ff02, +0x2100a900, +0x1f070b0b, +0xd10cff02, +0x2100ac00, +0x1f072b2b, +0xd114ff02, +0x2100af00, +0x1f074b4b, +0x101c1c7f, +0x100b0b0c, +0x102b2b0d, +0x104b4b0e, +0x51010615, +0x31070013, +0x0b070b03, +0x0b074623, +0x14230345, +0x09014646, +0x09010b0b, +0x12454646, +0x0b072b43, +0x0b076663, +0x14634365, +0x09016666, +0x09012b2b, +0x12656666, +0x0b074b05, +0x0b072725, +0x14250526, +0x09012727, +0x09014b4b, +0x12262727, +0x2100d700, +0x24000003, +0x24000023, +0x24000043, +0x50460b04, +0x50662b05, +0x50274b06, +0x2100d400, +0x24000103, +0x2100cc00, +0x24000123, +0x2100cd00, +0x24000143, +0x81183883, +0x812838a3, +0x813838c3, +0x01012424, +0x05010606, +0x10077f1c, +0x6e071cff, +0x101c1c7f, +0x51042405, +0x5108240a, +0x510c240f, +0x51000614, +0x21009a00, +0x10ececf0, +0x10ededf3, +0x10eeeef6, +0x2eff858c, +0x51004412, +0x2100df00, +0x10ececf1, +0x10ededf4, +0x10eeeef7, +0x2eff858c, +0x5100440c, +0x2100df00, +0x10ececf2, +0x10ededf5, +0x10eeeef8, +0x2eff858c, +0x51004406, +0x2100df00, +0x24000044, +0x670424ed, +0x670824f2, +0x670c24f7, +0xc9000702, +0x810cb890, +0xc9010702, +0x811cb893, +0xc9020702, +0x812cb896, +0x20880000, +0x24006ea2, +0xc9000711, +0x2401099d, +0x909d0402, +0x11070202, +0x51007a03, +0x51087a04, +0x51047a05, +0x13500202, +0x21010b00, +0x13f00202, +0x21010b00, +0x11000202, +0x2401099d, +0x809d0402, +0x10a2a29c, +0x24010a9d, +0x809d049c, +0xc9010711, +0x2401119d, +0x909d0402, +0x11070202, +0x51007a03, +0x51087a04, +0x51047a05, +0x13500202, +0x21011c00, +0x13f00202, +0x21011c00, +0x11000202, +0x2401119d, +0x809d0402, +0x10a2a29c, +0x2401129d, +0x809d049c, +0xc9020711, +0x2401199d, +0x909d0402, +0x11070202, +0x51007a03, +0x51087a04, +0x51047a05, +0x13500202, +0x21012d00, +0x13f00202, +0x21012d00, +0x11000202, +0x2401199d, +0x809d0402, +0x10a2a29c, +0x24011a9d, +0x809d049c, +0x2401049d, +0x909d0462, +0x11e06262, +0x6f0062fd, +0x1f14ffff, +0x20c80000, +0x2401029d, +0x809d0480, +0x2401069d, +0x809d04c0, +0x2401009d, +0x1f04e1e1, +0x809d0401, +0x20880000 }; diff --git a/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_single_channel_bin.h b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_single_channel_bin.h new file mode 100644 index 0000000..0a9b70e --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_master_single_channel_bin.h @@ -0,0 +1,463 @@ +/* + * tamagawa_master_single_channel_bin.h + * + * + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") + * this software subject to the terms herein. With respect to the foregoing patent + * license, such license is granted solely to the extent that any such patent + * is necessary to Utilize the software alone. The patent license shall not apply to any + * combinations which include this software, other than combinations with devices + * manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce this license + * (including the above copyright notice and the disclaimer and (if applicable) source + * code license limitations below) in the documentation and/or other materials provided + * with the distribution + * + * Redistribution and use in binary form, without modification, are permitted provided + * that the following conditions are met: + * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * Any redistribution and use are licensed by TI for use only with TI Devices. + * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution of the + * source code are permitted provided that the following conditions are met: + * Any redistribution and use of the source code, including any resulting derivative works, + * are licensed by TI for use only with TI Devices. + * Any redistribution and use of any object code compiled from the source code and + * any resulting derivative works, are licensed by TI for use only with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its suppliers + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND + * TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +const unsigned int TamagawaFirmware[]= { +0x00000208, +0x00010000, +0x24000400, +0x810f0400, +0x2eff8180, +0x2401089d, +0x809d2480, +0x2401109d, +0x809d2480, +0x2401189d, +0x809d2480, +0x2effbb80, +0x91011807, +0x11070707, +0x51070703, +0x51000702, +0x21001200, +0x24000107, +0x91401880, +0x914418c0, +0x91481801, +0x23018e88, +0x24000100, +0x81031800, +0x91001800, +0x69000001, +0x91021800, +0x570000ff, +0x9104181b, +0x9105183b, +0x91081821, +0x91091806, +0x23002488, +0x24000083, +0x81021803, +0x21001a00, +0xc9000702, +0x240000de, +0xc9010702, +0x240001de, +0xc9020702, +0x240002de, +0x2eff818a, +0x105e5e0a, +0x2eff8399, +0x9168187a, +0x51087a06, +0x51047a1b, +0x101b1b1e, +0x103b3b1e, +0x230150c8, +0x21008c00, +0xc9000705, +0x11035e1a, +0x69001a03, +0x2400881a, +0x21004300, +0xc9010705, +0x11035e1a, +0x69011a03, +0x2400b01a, +0x21004300, +0xc9020705, +0x11035e1a, +0x69021a03, +0x2400d81a, +0x21004300, +0x901a3899, +0x1079791e, +0x1059591e, +0x1039391e, +0x1019191e, +0x230150c8, +0x21008c00, +0xc900070c, +0x11035e1a, +0x69001a0a, +0x24008c1a, +0x901a1819, +0x1019191e, +0x2400881a, +0x901a3899, +0x1079791e, +0x1059591e, +0x1039391e, +0x21006e00, +0xc901070c, +0x11035e1a, +0x69011a0a, +0x2400b41a, +0x901a1819, +0x1019191e, +0x2400b01a, +0x901a3899, +0x1079791e, +0x1059591e, +0x1039391e, +0x21006e00, +0xc902070c, +0x11035e1a, +0x69021a0a, +0x2400dc1a, +0x901a1819, +0x1019191e, +0x2400d81a, +0x901a3899, +0x1079791e, +0x1059591e, +0x1039391e, +0x21006e00, +0x230150c8, +0x2eff819a, +0x100a0a5e, +0xc9000709, +0x11035e1a, +0x69001a07, +0x111c1f1a, +0x4f0c1afc, +0x2400881a, +0x901a1819, +0x1019191e, +0x21008c00, +0xc9010709, +0x11035e1a, +0x69011a07, +0x111c3f1a, +0x4f0c1afc, +0x2400b01a, +0x901a1819, +0x1019191e, +0x21008c00, +0xc9020709, +0x11035e1a, +0x69021a07, +0x111c5f1a, +0x4f0c1afc, +0x2400d81a, +0x901a1819, +0x1019191e, +0x21008c00, +0x2eff9d8b, +0x2eff8183, +0x2eff8185, +0x11ffe6e6, +0x11ffe7e7, +0x24000822, +0x24000024, +0x24000144, +0x2eff8183, +0xc900073e, +0x1f18fefe, +0x2427108a, +0x240000a9, +0x0101a9a9, +0x11017f1c, +0x488aa937, +0x6f011cfd, +0x101c1c7f, +0x0908ecec, +0x30220009, +0x0b010b0b, +0x2400001d, +0x11017f1c, +0x6f011cff, +0xd104ff02, +0x2100a700, +0x1f070b0b, +0x101c1c7f, +0x100b0b0c, +0x51010609, +0x31070007, +0x0b070b23, +0x0b070343, +0x14432363, +0x09010303, +0x09010b0b, +0x12630303, +0x2100b700, +0x24000023, +0x50030b02, +0x2100b600, +0x24000123, +0x811838a3, +0x01012424, +0x05010606, +0x11017f1c, +0x6f011cff, +0x101c1c7f, +0x51042405, +0x51082408, +0x510c240b, +0x5100060e, +0x21009900, +0x10ececf0, +0x2eff818c, +0x5100440e, +0x2100bf00, +0x10ececf1, +0x2eff818c, +0x5100440a, +0x2100bf00, +0x10ececf2, +0x2eff818c, +0x51004406, +0x2100bf00, +0x24000044, +0x670424f3, +0x670824f6, +0x670c24f9, +0x13017d7d, +0x810cb890, +0xc901073e, +0x1f19fefe, +0x2427108a, +0x240000a9, +0x0101a9a9, +0x11027f1c, +0x488aa937, +0x6f021cfd, +0x101c1c7f, +0x0908ecec, +0x30220009, +0x0b010b0b, +0x2400001d, +0x11027f1c, +0x6f021cff, +0xd10cff02, +0x2100e500, +0x1f070b0b, +0x101c1c7f, +0x100b0b0c, +0x51010609, +0x31070007, +0x0b070b23, +0x0b070343, +0x14432363, +0x09010303, +0x09010b0b, +0x12630303, +0x2100f500, +0x24000023, +0x50030b02, +0x2100f400, +0x24000123, +0x812838a3, +0x01012424, +0x05010606, +0x11027f1c, +0x6f021cff, +0x101c1c7f, +0x51042405, +0x51082408, +0x510c240b, +0x5100060e, +0x2100d700, +0x10ececf0, +0x2eff818c, +0x5100440e, +0x2100fd00, +0x10ececf1, +0x2eff818c, +0x5100440a, +0x2100fd00, +0x10ececf2, +0x2eff818c, +0x51004406, +0x2100fd00, +0x24000044, +0x670424f3, +0x670824f6, +0x670c24f9, +0x13027d7d, +0x811cb890, +0xc902073e, +0x1f1afefe, +0x2427108a, +0x240000a9, +0x0101a9a9, +0x11047f1c, +0x488aa937, +0x6f041cfd, +0x101c1c7f, +0x0908ecec, +0x30220009, +0x0b010b0b, +0x2400001d, +0x11047f1c, +0x6f041cff, +0xd114ff02, +0x21012300, +0x1f070b0b, +0x101c1c7f, +0x100b0b0c, +0x51010609, +0x31070007, +0x0b070b23, +0x0b070343, +0x14432363, +0x09010303, +0x09010b0b, +0x12630303, +0x21013300, +0x24000023, +0x50030b02, +0x21013200, +0x24000123, +0x813838a3, +0x01012424, +0x05010606, +0x11047f1c, +0x6f041cff, +0x101c1c7f, +0x51042405, +0x51082408, +0x510c240b, +0x5100060e, +0x21011500, +0x10ececf0, +0x2eff818c, +0x5100440e, +0x21013b00, +0x10ececf1, +0x2eff818c, +0x5100440a, +0x21013b00, +0x10ececf2, +0x2eff818c, +0x51004406, +0x21013b00, +0x24000044, +0x670424f3, +0x670824f6, +0x670c24f9, +0x13047d7d, +0x812cb890, +0x20880000, +0x24006ea2, +0xc9000711, +0x2401099d, +0x909d0402, +0x11070202, +0x51007a03, +0x51087a04, +0x51047a05, +0x13500202, +0x21015d00, +0x13f00202, +0x21015d00, +0x11000202, +0x2401099d, +0x809d0402, +0x10a2a29c, +0x24010a9d, +0x809d049c, +0xc9010711, +0x2401119d, +0x909d0402, +0x11070202, +0x51007a03, +0x51087a04, +0x51047a05, +0x13500202, +0x21016e00, +0x13f00202, +0x21016e00, +0x11000202, +0x2401119d, +0x809d0402, +0x10a2a29c, +0x2401129d, +0x809d049c, +0xc9020711, +0x2401199d, +0x909d0402, +0x11070202, +0x51007a03, +0x51087a04, +0x51047a05, +0x13500202, +0x21017f00, +0x13f00202, +0x21017f00, +0x11000202, +0x2401199d, +0x809d0402, +0x10a2a29c, +0x24011a9d, +0x809d049c, +0x2401049d, +0x909d0462, +0xc9000702, +0xd70562fd, +0xc9010702, +0xd70662fb, +0xc9020702, +0xd70762f9, +0x1f12ffff, +0x20c80000, +0x2401029d, +0x809d0480, +0x2401069d, +0x809d04c0, +0x2401009d, +0x1f04e1e1, +0x809d0401, +0x20880000 }; diff --git a/source/motor_control/position_sense/tamagawa/firmware/tamagawa_send.h b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_send.h new file mode 100644 index 0000000..1f88565 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/firmware/tamagawa_send.h @@ -0,0 +1,101 @@ +; Copyright (C) 2022 Texas Instruments Incorporated +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions + ; are met: + ; + ; Redistributions of source code must retain the above copyright + ; notice, this list of conditions and the following disclaimer. + ; + ; Redistributions in binary form must reproduce the above copyright + ; notice, this list of conditions and the following disclaimer in the + ; documentation and/or other materials provided with the + ; distribution. + ; + ; Neither the name of Texas Instruments Incorporated nor the names of + ; its contributors may be used to endorse or promote products derived + ; from this software without specific prior written permission. + ; + ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ; + + +;************************************************************************************ +;* File: tamagawa_send.h * +;* * +;* Brief: Macro for sending commands to the Tamagawa encoder * +;************************************************************************************ + +;************************************************************************************************************************************* +; Macro: TAMAGAWA_SEND_MACRO +; +; Send the Tx data for non-EEPROM commands to the Tamagawa encoders. +; +; Registers: +; R27.b0- Stores the first byte of the TX data +; R27.b1- Stores the second byte of the TX data +; R30.b0- Used to load Tx FIFO for a selected channel +; R30.b2- Used to select the channel (R30[17:16]) +; +; +; +; PseudoCode: +; (start code) +; 1.Load the Tx FIFO with the first byte for the currently selected channel by writing to the R30.b0. +; 2.Load the Tx FIFO with the second byte for the currently selected channel by writing to the R30.b0. +; 3.Loop through the steps 1-4 thrice in case of multi-channel configuration to fill Tx FIFO for all selected channels. +; 4.Once the Tx FIFO of all the selected channels is loaded with 2 bytes, make a call to the FN_SEND function that performs Tx in single shot mode with Tx frame size = 10 bits. +; (end code) +; +; Parameters: +; tx_data0 - Stores the first byte of the tx data to be sent to the encoder +; tx_data1 - Stores the second byte of the tx data to be sent to the encoder +; +; Worst case peak cycle usage: 68 (approx.) +; For all commands except EEPROM Read and Write, the Control Field (CF) should be transmitted to the encoder in about 2.0 +/- 0.05 μs and 4.0 +/- 0.1 μs for 5 Mbps and 2.5 Mbps Tamagawa encoders respectively. +; +;************************************************************************************************************************************** + + .if !$isdefed("__tamagawa_send_h") +__tamagawa_send_h .set 1 + + .include "tamagawa_interface.h" + .include "tamagawa_constants.h" + .global FN_SEND + .global CALL + .global CALL2 + +TAMAGAWA_SEND_MACRO .macro tx_data0, tx_data1 + .if $defined("ENABLE_MULTI_CHANNEL") + ;In each iteration, channel is selected and Tx Fifo is loaded . + LOOP SEND_RECEIVE_TAMAGAWA_MULTI_CHANNEL?, 3 + .endif + ;In case of non EEPROM commands, we need to send the control field to the encoder. This control field is of 10 bits. + ;The FIFO is loaded with 16 bits first and then a call to the FN_SEND is made in order to start Tx in Single shot mode with Tx frame size = 10 bits. + ;load Tx FIFO + MOV R30.b0,tx_data0 + ;load Tx FIFO + MOV R30.b0,tx_data1 + + .if $defined("ENABLE_MULTI_CHANNEL") + ; last channel would have been selected first + ;R30[17:16] tx_ch_sel is decremented to select next channel and load Tx Fifo. + SUB R30.b2, R30.b2, 1 +SEND_RECEIVE_TAMAGAWA_MULTI_CHANNEL?: + .endif + ; Sending Tx Fifo data via Data line(PERIF0_OUT,PERIF1_OUT,PERIF2_OUT) to encoders + CALL2 FN_SEND + + .endm + + .endif diff --git a/source/motor_control/position_sense/tamagawa/include/tamagawa_drv.h b/source/motor_control/position_sense/tamagawa/include/tamagawa_drv.h new file mode 100644 index 0000000..337ddc5 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/include/tamagawa_drv.h @@ -0,0 +1,548 @@ +/* + * Copyright (C) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef TAMAGAWA_DRV_H_ +#define TAMAGAWA_DRV_H_ + +/** + * \defgroup TAMAGAWA_API_MODULE APIs for Tamagawa Encoder + * \ingroup MOTOR_CONTROL_API + * + * Here is the list of APIs used for Tamagawa encoder communication protocol + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include +#include +#include + +#include + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/** + * \brief Used to set the value of Tamagawa multi-channel mask based on the whether the Channel 0 is selected or not + */ +#define TAMAGAWA_MULTI_CH0 (1 << 0) + +/** + * \brief Used to set the value of Tamagawa multi-channel mask based on the whether the Channel 1 is selected or not + */ +#define TAMAGAWA_MULTI_CH1 (1 << 1) + +/** + * \brief Used to set the value of Tamagawa multi-channel mask based on the whether the Channel 2 is selected or not + */ +#define TAMAGAWA_MULTI_CH2 (1 << 2) + +/** + * \brief Used to set the maximum channels supported + */ +#define MAX_CHANNELS (3) + +/** + * \brief Used to set the maximum address that can be used for EEPROM Read/Write + */ +#define MAX_EEPROM_ADDRESS (127) + +/** + * \brief Used to set the maximum value that can be written in EEPROM + */ +#define MAX_EEPROM_WRITE_DATA (255) + + +/** +* \brief Data ID codes +*/ +enum data_id +{ + DATA_ID_0, /**< Data readout data in one revolution */ + DATA_ID_1, /**< Data readout multi-turn data */ + DATA_ID_2, /**< Data readout encoder ID */ + DATA_ID_3, /**< Data readout data in one revolution, encoder ID, multi-turn, encoder error */ + DATA_ID_6, /**< EEPROM write */ + DATA_ID_7, /**< Reset */ + DATA_ID_8, /**< Reset */ + DATA_ID_C, /**< Reset */ + DATA_ID_D, /**< EEPROM read */ + DATA_ID_NUM /**< Number of Data ID codes */ +}; + +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ + +/** + * \brief Structure defining tamagawa per channel interface + * + * \details Firmware per channel interface + */ +struct tamagawa_ch_info +{ + volatile uint32_t pos_word0; /** + [Byte 0] control field
**/ + volatile uint32_t word1;/**< command parameters,
+ [Byte 0] No. of Tx frames
+ [Byte 1] No. of Rx frames
+ + */ + +}; + +/** + * \brief Structure defining Tamagawa configuration interface + * + * \details Firmware configuration interface + */ +struct tamagawa_config +{ + volatile uint8_t opmode;/**< operation mode selection: 0 - periodic trigger, 1 - host trigger */ + volatile uint8_t channel;/**< channel mask (1 << channel), 0 < channel < 3. This has to be
+ selected before running firmware. Once initialization is complete,
+ it will reflect the detected channels in the selected mask.
+ Multichannel can have upto 3 selected, while single channel only one */ + volatile uint8_t trigger;/**< command trigger. Set LSB to send cmd, will be cleared upon cmd
+ completion. Note that cmd has to be setup before trigger */ + volatile uint8_t status;/**< initialization status: 1 - upon successful. */ +}; + +/** + * \brief Tamagawa Interface Received data + **/ +struct rx_frames_received +{ + uint32_t abs; /**< Data in one revolution */ + uint32_t abm; /**< Multi-turn Data */ + uint8_t cf; /**< Control Frame */ + uint8_t sf; /**< Status Frame */ + uint8_t enid; /**< Encoder ID */ + uint8_t almc; /**< Encoder error */ + uint8_t adf; /**< EEPROM address */ + uint8_t edf; /**< EEPROM data */ + uint8_t crc; /**< CRC */ +}; +/** + * \brief Tamagawa Interface + */ +struct tamagawa_interface +{ + uint8_t ch_mask; //**< Mask for what channel is required*/ + volatile uint32_t rx_div_factor; //**< Rx Divide factor*/ + + volatile uint32_t tx_div_factor; //**< Tx Divide factor*/ + + volatile uint32_t oversample_rate; //**< Oversampling rate*/ + + uint32_t version; /**< Firmware version */ + uint8_t data_id; /**< Data ID code */ + struct rx_frames_received rx_frames_received; /**< Received data */ + uint8_t tx_frames; /**< Number of Tx frames */ + uint8_t rx_frames; /**< Number of Rx frames */ +}; + +struct config +{ + uint8_t ch0; /**< config for channel 0 */ + uint8_t ch1; /**< config for channel 1 */ + uint8_t ch2; /**< config for channel 2 */ +}; + +/** + * \brief Tamagawa EEPROM Interface + */ +struct tamagawa_eeprom_interface +{ + volatile uint32_t cmd; /**< holds the value of command id for EEPROM commands */ + volatile uint32_t adf; /**< holds the value of ADF for EEPROM commands */ + volatile uint32_t edf; /**< holds the value of EDF for EEPROM Write command */ + volatile uint32_t crc; /**< holds the value of CRC for EEPROM commands */ + + volatile uint32_t word0; /**< used for CRC calculation */ + volatile uint32_t word1; /**< used for CRC calculation */ + volatile uint32_t word2; /**< used for CRC calculation */ + + uint64_t eeprom_tx_data; /**< used to store the bits for tx in eeprom read/write */ +}; + + +/** + * \brief Structure defining Tamagawa interface + * + * \details Firmware config, command and channel interface + * + */ +struct tamagawa_xchg +{ + struct tamagawa_config config;/**< config interface */ + struct tamagawa_cmd cmd;/**< command interface */ + struct tamagawa_ch_info ch[3];/**< per channel interface */ + + struct tamagawa_interface tamagawa_interface;/**< tamagawa interface */ + struct tamagawa_eeprom_interface tamagawa_eeprom_interface[3];/**< tamagawa interface for EEPROM commands */ +}; + +/** + * \brief Used to configure the Tamagawa Clock. + * + */ +struct tamagawa_clk_cfg +{ + uint16_t rx_div; /**< Rx Div factor*/ + uint16_t tx_div; /**< Tx Div factor*/ + uint16_t rx_en_cnt; + uint16_t rx_div_attr; +}; + + +/** + * \brief Used to store the register offsets depending on different PRU slices. + * + */ +struct register_offsets +{ + int32_t ICSS_CFG_PRUx_ED_CH0_CFG0; + int32_t ICSS_CFG_PRUx_ED_CH1_CFG0; + int32_t ICSS_CFG_PRUx_ED_CH2_CFG0; + int32_t ICSS_CFG_PRUx_ED_CH0_CFG1; + int32_t ICSS_CFG_PRUx_ED_CH1_CFG1; + int32_t ICSS_CFG_PRUx_ED_CH2_CFG1; + int32_t ICSS_CFG_GPCFGx; + int32_t ICSS_CFG_PRUx_ED_RXCFG; + int32_t ICSS_CFG_PRUx_ED_TXCFG; +}; + +/** + * \brief Used to structures defining the Tamagawa interface, PRU slice and register offsets. + * + */ +struct tamagawa_priv +{ + int32_t channel; /**< Holds the ID of the current channel being used*/ + uint16_t rx_en_cnt; + struct tamagawa_xchg *tamagawa_xchg; /** + * required to be invoked only if firmware indicates initialization failure
+ * to know the channels that has been detected. Initialization success implies
+ * that all channels indicated has been detected. + * + * \param[in] priv cookie returned by tamagawa_init + * + * \retval mask mask of the detected channels + * + */ +uint8_t tamagawa_multi_channel_detected(struct tamagawa_priv *priv); + +/** + * \brief In multi channel configuration, select channel before receive processing in
+ * multi channel configuration. After receive is complete, select each channel
+ * and invoke rx API's to parse data recieved in each channel. + * + * \param[in] priv cookie returned by tamagawa_init + * \param[in] ch channel number to be selected + * + */ +void tamagawa_multi_channel_set_cur(struct tamagawa_priv *priv, uint32_t ch); + + + +/** + * \brief Initialize tamagawa firmware interface address and get the pointer + * to struct tamagawa_priv instance + * + * \param[in] tamagawa_xchg tamagawa firmware interface address + * \param[in] pruss_cfg ICSS PRU config base address + * \param[in] slice_value PRUx slice value : 0 for PRU0 and 1 for PRU1 + * + * \retval priv pointer to struct tamagawa_priv instance + * + */ +struct tamagawa_priv *tamagawa_init(struct tamagawa_xchg *tamagawa_xchg, void *pruss_cfg, uint32_t slice_value); + +/** + * \brief update the current requested command id in tamagawa interface.
+ * + * + * \param[in] priv cookie returned by tamagawa_init + * \param[in] cmd tamagawa command number + * + */ + +void tamagawa_update_data_id(struct tamagawa_priv *priv, int32_t cmd); + +/** + * \brief update the adf(address of EEPROM) field entered by user for EEPROM command in tamagawa interface.
+ * + * + * \param[in] priv cookie returned by tamagawa_init + * \param[in] val ADF value to be updated + * \param[in] ch channel number that is currently selected + * + */ + +void tamagawa_update_adf(struct tamagawa_priv *priv, uint32_t val, uint32_t ch); + +/** + * \brief update the edf(data for EEPROM) field entered by user for EEPROM command in tamagawa interface.
+ * + * + * \param[in] priv cookie returned by tamagawa_init + * \param[in] val EDF value to be updated + * \param[in] ch channel number that is currently selected + * + */ + +void tamagawa_update_edf(struct tamagawa_priv *priv, uint32_t val, uint32_t ch); + + +/** + * \brief Parse the data in tamagawa interface.
+ * + * + * \param[in] cmd tamagawa command number + * \param[in] priv cookie returned by tamagawa_init + * + */ +int32_t tamagawa_parse(int32_t cmd, struct tamagawa_priv *priv); + +/** + * \brief verify the CRC computed with the encoder crc.
+ * + * + * \param[in] priv cookie returned by tamagawa_init + * + * \retval 1/0 if verify correctly, return 1 else return 0. + * + */ + +int32_t tamagawa_crc_verify(struct tamagawa_priv *priv); + +/** + * \brief Pass the values of CF(Control Field), ADF(address of EEPROM) and EDF(data for EEPROM) to the CRC calculator fucntion and update the CRC field.
+ * + * + * \param[in] priv cookie returned by tamagawa_init + * \param[in] cmd tamagawa command number + * \param[in] ch channel number that is currently selected + * + */ + +void tamagawa_update_crc(struct tamagawa_priv *priv, int32_t cmd, uint32_t ch); + +/** + * \brief Update the values for oversample rate and division factor for Tx and Rx.
+ * + * + * \param[in] priv cookie returned by tamagawa_init + * \param[in] baudrate baud rate of the tamagawa encoder + * + */ + +void tamagawa_set_baudrate(struct tamagawa_priv *priv, double baudrate); + +/** + * \brief Reset the values of the variables used in CRC calculation to 0.
+ * + * + * \param[in] priv cookie returned by tamagawa_init + * + */ + +void tamagawa_eeprom_crc_reinit(struct tamagawa_priv *priv); + +/** + * \brief Reverse the bits of a number.
+ * + * + * \param[in] data 8 bit value for any of CF(Control Field), ADF(address of EEPROM) or EDF(data for EEPROM) + * + * \retval reversed_num number obtained after reversing the bits of data provided + * + */ + +uint32_t tamagawa_reverse_bits(int8_t data); + +/** + * \brief Add the start and the stop bit to the reversed data.
+ * + * + * \param[in] eeprom_tx_data holds the value of the Tx data to be sent + * \param[in] data holds the value of CF(Control Field), ADF(address of EEPROM) or EDF(data for EEPROM) + * + * \retval eeprom_tx_data 64 bit integer that holds the value of the Tx data to be sent + * + */ + +uint64_t tamagawa_prepare_eeprom_tx_data(uint64_t eeprom_tx_data, volatile uint32_t data); + +/** + * \brief Prepare the required EEPROM command from the CF(Control Field), ADF(address of EEPROM) and EDF(data for EEPROM).
+ * + * + * \param[in] priv cookie returned by tamagawa_init + * \param[in] cmd tamagawa command number + * \param[in] ch channel number that is currently selected + * + */ + +void tamagawa_prepare_eeprom_command(struct tamagawa_priv *priv, int32_t cmd, uint32_t ch); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/motor_control/position_sense/tamagawa/makefile.am243x.r5f.ti-arm-clang b/source/motor_control/position_sense/tamagawa/makefile.am243x.r5f.ti-arm-clang new file mode 100644 index 0000000..538366a --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/makefile.am243x.r5f.ti-arm-clang @@ -0,0 +1,119 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang +AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar + +PROFILE?=release +ConfigName:=$(PROFILE) + +LIBNAME:=motorcontrol_tamagawa.am243x.r5f.ti-arm-clang.$(PROFILE).lib + +FILES_common := \ + tamagawa_drv.c \ + +FILES_PATH_common = \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/driver \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/include \ + +DEFINES_common := \ + -DSOC_AM243X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +ARFLAGS_common := \ + rc \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ifeq ($(CPLUSPLUS_BUILD), yes) +CFLAGS += $(CFLAGS_cpp_common) +endif +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE)) + +LIBDIR := lib +OBJDIR := obj/am243x/ti-arm-clang/$(PROFILE)/r5f/motorcontrol_tamagawa/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $< + +all: $(LIBDIR)/$(LIBNAME) + +$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR) + @echo . + @echo Archiving: $(LIBNAME) to $@ ... + $(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS)) + @echo Archiving: $(LIBNAME) Done !!! + @echo . + +clean: + @echo Cleaning: $(LIBNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(LIBDIR)/$(LIBNAME) + +scrub: + @echo Scrubing: $(LIBNAME) ... + -$(RMDIR) obj/ + -$(RMDIR) lib/ + +$(OBJS): | $(OBJDIR) + +$(LIBDIR) $(OBJDIR): + $(MKDIR) $@ + +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/source/motor_control/position_sense/tamagawa/makefile.am64x.r5f.ti-arm-clang b/source/motor_control/position_sense/tamagawa/makefile.am64x.r5f.ti-arm-clang new file mode 100644 index 0000000..331860c --- /dev/null +++ b/source/motor_control/position_sense/tamagawa/makefile.am64x.r5f.ti-arm-clang @@ -0,0 +1,119 @@ +# +# Auto generated makefile +# + +export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../..) +include $(MOTOR_CONTROL_SDK_PATH)/imports.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang +AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar + +PROFILE?=release +ConfigName:=$(PROFILE) + +LIBNAME:=motorcontrol_tamagawa.am64x.r5f.ti-arm-clang.$(PROFILE).lib + +FILES_common := \ + tamagawa_drv.c \ + +FILES_PATH_common = \ + ${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/driver \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source \ + -I${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa/include \ + +DEFINES_common := \ + -DSOC_AM64X \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +CFLAGS_release := \ + -Os \ + +ARFLAGS_common := \ + rc \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +ifeq ($(CPLUSPLUS_BUILD), yes) +CFLAGS += $(CFLAGS_cpp_common) +endif +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE)) + +LIBDIR := lib +OBJDIR := obj/am64x/ti-arm-clang/$(PROFILE)/r5f/motorcontrol_tamagawa/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: $(LIBNAME): $< + $(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $< + +all: $(LIBDIR)/$(LIBNAME) + +$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR) + @echo . + @echo Archiving: $(LIBNAME) to $@ ... + $(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS)) + @echo Archiving: $(LIBNAME) Done !!! + @echo . + +clean: + @echo Cleaning: $(LIBNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(LIBDIR)/$(LIBNAME) + +scrub: + @echo Scrubing: $(LIBNAME) ... + -$(RMDIR) obj/ + -$(RMDIR) lib/ + +$(OBJS): | $(OBJDIR) + +$(LIBDIR) $(OBJDIR): + $(MKDIR) $@ + +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/source/motor_control/position_sense/tamagawa_over_soc_uart/.project/project.js b/source/motor_control/position_sense/tamagawa_over_soc_uart/.project/project.js new file mode 100644 index 0000000..f6c2d16 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa_over_soc_uart/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/tamagawa_over_soc_uart/.project/project_am263x.js b/source/motor_control/position_sense/tamagawa_over_soc_uart/.project/project_am263x.js new file mode 100644 index 0000000..4d8024c --- /dev/null +++ b/source/motor_control/position_sense/tamagawa_over_soc_uart/.project/project_am263x.js @@ -0,0 +1,53 @@ +let path = require('path'); + +let device = "am263x"; + +const files = { + common: [ + "tamagawa_soc_uart_driv.c", + ], +}; + + +const filedirs = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa_over_soc_uart/driver", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/motor_control/position_sense/tamagawa_over_soc_uart/include", + ], +}; + +const buildOptionCombos = [ + { device: device, cpu: "r5f", cgt: "ti-arm-clang"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "library"; + property.name = "motorcontrol_tamagawa_over_soc_uart"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/motor_control/position_sense/tamagawa_over_soc_uart/driver/tamagawa_soc_uart_driv.c b/source/motor_control/position_sense/tamagawa_over_soc_uart/driver/tamagawa_soc_uart_driv.c new file mode 100644 index 0000000..db2cef5 --- /dev/null +++ b/source/motor_control/position_sense/tamagawa_over_soc_uart/driver/tamagawa_soc_uart_driv.c @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include +#include +#include + +#define MAX_TX_FRAME (4) +#define MAX_RX_FRAME (12) + +#define APP_UART_ASSERT_ON_FAILURE(transferOK, transaction) \ + do { \ + if((SystemP_SUCCESS != (transferOK)) || (UART_TRANSFER_STATUS_SUCCESS != transaction.status)) \ + { \ + DebugP_assert(FALSE); /* UART TX/RX failed!! */ \ + } \ + } while(0) \ + + + +uint8_t tamagawa_calculate_crc(uint8_t *s, uint8_t len) +{ + uint8_t crc = 0; + uint8_t val; + uint32_t i, j; + uint8_t data[MAX_RX_FRAME]; + + memcpy (data, s, len); + + for(i = 0; i < len; i++) + { + for(j = 0; j < 8; j++) + { + val = (data[i] >> 7) ^ (crc >> 7); + + crc <<= 1; + data[i] <<= 1; + crc |= val; + } + } + return crc; +} + +int32_t tamagawa_handle_rx(volatile struct tamagawa_uart_interface *tamagawa_interface, uint8_t *p) +{ + int ret = 0; + switch(tamagawa_interface->data_id) + { + case DATA_ID_0: + case DATA_ID_7: + case DATA_ID_8: + case DATA_ID_C: + tamagawa_interface->rx.cf = p[0]; + tamagawa_interface->rx.sf = p[1]; + tamagawa_interface->rx.abs = p[2] | (p[3] << 8) | (p[4] << 16); + tamagawa_interface->rx.crc = p[5]; + break; + + case DATA_ID_1: + tamagawa_interface->rx.cf = p[0]; + tamagawa_interface->rx.sf = p[1]; + tamagawa_interface->rx.abm = p[2] | (p[3] << 8) | (p[4] << 16); + tamagawa_interface->rx.crc = p[5]; + break; + + case DATA_ID_2: + tamagawa_interface->rx.cf = p[0]; + tamagawa_interface->rx.sf = p[1]; + tamagawa_interface->rx.enid = p[2]; + tamagawa_interface->rx.crc = p[3]; + break; + + case DATA_ID_3: + tamagawa_interface->rx.cf = p[0]; + tamagawa_interface->rx.sf = p[1]; + tamagawa_interface->rx.abs = p[2] | (p[3] << 8) | (p[4] << 16); + tamagawa_interface->rx.enid = p[5]; + tamagawa_interface->rx.abm = p[6] | (p[7] << 8) | (p[8] << 16); + tamagawa_interface->rx.almc = p[9]; + tamagawa_interface->rx.crc = p[10]; + break; + + case DATA_ID_6: + case DATA_ID_D: + tamagawa_interface->rx.cf = p[0]; + tamagawa_interface->rx.adf = p[1]; + tamagawa_interface->rx.edf = p[2]; + tamagawa_interface->rx.crc = p[3]; + break; + + default: + ret = -1; + break; + } + + return ret; +} + + +int32_t tamagawa_command_build(volatile struct tamagawa_uart_interface *tamagawa_interface, uint8_t *tx, uint8_t *tx_size, uint8_t *rx_size) +{ + int ret = 0; + + switch(tamagawa_interface->data_id) + { + case DATA_ID_0: + *tx = 0x02; + *tx_size = 1; + *rx_size = 6; + break; + + case DATA_ID_1: + *tx = 0x8A; + *tx_size = 1; + *rx_size = 6; + break; + + case DATA_ID_2: + *tx = 0x92; + *tx_size = 1; + *rx_size = 4; + break; + + case DATA_ID_3: + *tx = 0x1A; + *tx_size = 1; + *rx_size = 11; + break; + + case DATA_ID_7: + *tx = 0xBA; + *tx_size = 1; + *rx_size = 6; + break; + + case DATA_ID_8: + *tx = 0xC2; + *tx_size = 1; + *rx_size = 6; + break; + + case DATA_ID_C: + *tx = 0x62; + *tx_size = 1; + *rx_size = 6; + break; + + case DATA_ID_6: + *tx++ = 0x32; + *tx++ = tamagawa_interface->tx.adf; + *tx++ = tamagawa_interface->tx.edf; + *tx_size = 4; + *rx_size = 4; + *tx = tamagawa_calculate_crc(tx - 3, *tx_size - 1); + break; + + case DATA_ID_D: + *tx++ = 0xEA; + *tx++ = tamagawa_interface->tx.adf; + *tx_size = 3; + *rx_size = 4; + *tx = tamagawa_calculate_crc(tx - 2, *tx_size - 1); + break; + + default: + ret = -1; + break; + } + + return ret; +} + + +int32_t tamagawa_command_process(volatile struct tamagawa_uart_interface *tamagawa_interface, UART_Handle *gUartHandle, int32_t cmd) +{ + int32_t transferOK; + UART_Transaction trans; + + UART_Transaction_init(&trans); + + uint8_t tx[MAX_TX_FRAME]; + uint8_t rx[MAX_RX_FRAME]; + uint8_t tx_size = 0, rx_size = 0; + tamagawa_interface->data_id = cmd; + + /* Command build */ + cmd = tamagawa_command_build(tamagawa_interface, tx, &tx_size, &rx_size); + if(cmd < 0) + { + return cmd; + } + + /* Write data into Tx fifo*/ + trans.buf = &tx[0U]; + trans.count = tx_size; + /*configure GPIO pin high just before TX start (RTSn high)*/ + GPIO_pinWriteHigh(tamagawa_interface->gpio_base_address, tamagawa_interface->gpio_pin_number); + transferOK = UART_write(gUartHandle[tamagawa_interface->uart_instance], &trans); + /*configure GPIO pin low just after TX complete (RTSn low)*/ + GPIO_pinWriteLow(tamagawa_interface->gpio_base_address, tamagawa_interface->gpio_pin_number); + APP_UART_ASSERT_ON_FAILURE(transferOK, trans); + + /* Read data from Rx fifo */ + trans.buf = &rx[0U]; + trans.count = rx_size + tx_size; + transferOK = UART_read(gUartHandle[tamagawa_interface->uart_instance], &trans); + APP_UART_ASSERT_ON_FAILURE(transferOK, trans); + + /* parsing of recevied data*/ + cmd = tamagawa_handle_rx(tamagawa_interface, rx + tx_size); + + + /* CRC calculation*/ + tamagawa_interface->rx_crc = tamagawa_calculate_crc(rx + tx_size, rx_size - 1); + + return cmd; +} + +int32_t tamagawa_crc_verify(volatile struct tamagawa_uart_interface *tamagawa_interface) +{ + return (tamagawa_interface->rx.crc == tamagawa_interface->rx_crc) ? 1 : 0; +} + +void tamagawa_init(volatile struct tamagawa_uart_interface *tamagawa_interface, uint32_t instance , uint32_t base_address, uint32_t pin_number, uint32_t pin_direction) +{ + tamagawa_interface->uart_instance = instance; + tamagawa_interface->gpio_base_address = base_address; + tamagawa_interface->gpio_pin_number = pin_number; + /*GPIO pin configurtaion for RTSn*/ + GPIO_setDirMode(base_address, pin_number, pin_direction); +} \ No newline at end of file diff --git a/source/motor_control/position_sense/tamagawa_over_soc_uart/include/tamagawa_soc_uart_interface.h b/source/motor_control/position_sense/tamagawa_over_soc_uart/include/tamagawa_soc_uart_interface.h new file mode 100644 index 0000000..1ff70cb --- /dev/null +++ b/source/motor_control/position_sense/tamagawa_over_soc_uart/include/tamagawa_soc_uart_interface.h @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef TAMAGAWA_UART_DRV_H_ +#define TAMAGAWA_UART_DRV_H_ + /** + * \defgroup MOTOR_CONTROL_API APIs for Motor Control Encoders + * + * This module contains APIs for device drivers for various motor control encoders supported in this SDK. + */ + +/** + * \defgroup TAMAGAWA_UART_API_MODULE APIs for Tamagawa Encoder Over UART + * \ingroup MOTOR_CONTROL_API + * + * Here is the list of APIs used for Tamagawa encoder communication protocol + * + * @{ + */ +#ifdef __cplusplus +extern "C" { +#endif + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/** + * \brief Used to set the maximum address that can be used for EEPROM Read/Write + */ +#define MAX_EEPROM_ADDRESS (127) +/** +* \brief Used to set the maximum value that can be written in EEPROM +*/ +#define MAX_EEPROM_WRITE_DATA (255) +/** + * @brief Data ID codes + */ +enum data_id +{ + DATA_ID_0, /**< Data readout data in one revolution */ + DATA_ID_1, /**< Data readout multi-turn data */ + DATA_ID_2, /**< Data readout encoder ID */ + DATA_ID_3, /**< Data readout data in one revolution, encoder ID, multi-turn, encoder error */ + DATA_ID_6, /**< EEPROM write */ + DATA_ID_7, /**< Reset */ + DATA_ID_8, /**< Reset */ + DATA_ID_C, /**< Reset */ + DATA_ID_D, /**< EEPROM read */ + DATA_ID_NUM /**< Number of Data ID codes */ +}; +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ +/** + * @brief Tamagawa Interface Transmit data + */ +struct tamagawa_tx +{ + uint8_t adf; /**< EEPROM address */ + uint8_t edf; /**< EEPROM data */ +}; + +/** + * @brief Tamagawa Interface Received data + */ +struct tamagawa_rx +{ + uint32_t abs; /**< Data in one revolution */ + uint32_t abm; /**< Multi-turn Data */ + uint8_t cf; /**< Control Frame */ + uint8_t sf; /**< Status Frame */ + uint8_t enid; /**< Encoder ID */ + uint8_t almc; /**< Encoder error */ + uint8_t adf; /**< EEPROM address */ + uint8_t edf; /**< EEPROM data */ + uint8_t crc; /**< CRC */ +}; +/** + * @brief Tamagawa Interface + */ +struct tamagawa_uart_interface +{ + uint8_t data_id; /**< Data ID code */ + struct tamagawa_tx tx; /**< Transmit data */ + struct tamagawa_rx rx; /**< Received data */ + uint8_t rx_crc; /**< Calculated CRC */ + uint32_t uart_instance; /**< Uart instance*/ + uint32_t gpio_base_address; /**< GPIO pin base address*/ + uint32_t gpio_pin_number; /**