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Pull request #48: Next

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Merge in PINDSW/motor_control_sdk from next to main

* commit '13692dcd7085eee8be339f452d8fa7d89cb9c089': (64 commits)
  am243x : tirex : update the image name in package.tirex.json file
  am263x: docs: Update main page
  am263x: docs: Add release notes page for 9.0
  am263x: Tamagawa: revert default uart console baudrate
  am64x/am243x: Tamagawa: Update release note
  am64x/am243x: Endat: resolve klockwork error
  am64x/am243x: Tamagawa: Update name of defined symbols and include path
  am263x: rtlibs: Fix linker file for AM263X examples
  am263x : build : fix product.json issue for AM263x MCSDK
  am263x : build : fix gen-buildfiles issue for AM263x MCSDK
  am64x/am243x/am263x: build: Make Release mode as default configuration
  am243x: docs: Remove compiler note from release notes for 9.0
  am243x: docs: Update discovery path addition instruction
  am243x: docs: Update bug list for 9.0 release
  am243x/am263x: rtlibs: Update documentation
  am243x: rtlibs: Remove M4F examples for DCL
  am64x/am243x: EnDat: add limitations in design doc
  am243x/am263x: docs: Add manifest for 9.0 release
  am64x/am243x/am263x: docs: Update the links to IC SDK and MCU+ SDK
  am64x/am243x: hdsl: Update documentation for HDSL examples
  ...
This commit is contained in:
Naresh A 2023-09-29 08:09:39 -05:00 committed by Pratheesh Gangadhar TK
commit 32a5168c5f
567 changed files with 67276 additions and 13728 deletions
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5
.gitignore vendored
View File

@ -54,6 +54,7 @@ source/usb/tinyusb/tinyusb-stack
source/dsplib_c66x_3_4_0_0/
docs/industrial_protocol_docs
mcusdk_tagfile
mcsdk_tagfile
__pycache__/
source/position_sense/hdsl/firmware/*.lst
source/position_sense/hdsl/firmware/*.obj
@ -66,4 +67,6 @@ source/position_sense/endat/firmware/*.b00
source/position_sense/endat/firmware/*.xml
!*boardcfg_*.bin
mcu_plus_sdk
ind_comms_sdk
ind_comms_sdk
.repo/*
mcupsdk_setup

320
.metadata/.tirex/am243x.content.tirex.json
View File

@ -1,4 +1,260 @@
[
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A Direct Form 2 2nd order example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running NORTOS.",
"name": "dcl_df22",
"location": "../../examples/dcl/dcl_df22/am243x-evm/r5fss0-0_nortos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"nortos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_df22",
"r5fss0-0_nortos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A Direct Form 2 2nd order example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running FREERTOS.",
"name": "dcl_df22",
"location": "../../examples/dcl/dcl_df22/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_df22",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
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},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
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"example.gettingstarted"
],
"description": "A Direct Form 2 2nd order example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running NORTOS.",
"name": "dcl_df22",
"location": "../../examples/dcl/dcl_df22/am243x-lp/r5fss0-0_nortos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_LAUNCHPAD"
],
"kernel": [
"nortos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
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],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
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"resourceSubClass": [
"example.gettingstarted"
],
"description": "A Direct Form 2 2nd order example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running FREERTOS.",
"name": "dcl_df22",
"location": "../../examples/dcl/dcl_df22/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_LAUNCHPAD"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_df22",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A PI controller example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running NORTOS.",
"name": "dcl_pi",
"location": "../../examples/dcl/dcl_pi/am243x-evm/r5fss0-0_nortos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"nortos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_pi",
"r5fss0-0_nortos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A PI controller example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running FREERTOS.",
"name": "dcl_pi",
"location": "../../examples/dcl/dcl_pi/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_pi",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A PI controller example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running NORTOS.",
"name": "dcl_pi",
"location": "../../examples/dcl/dcl_pi/am243x-lp/r5fss0-0_nortos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_LAUNCHPAD"
],
"kernel": [
"nortos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_pi",
"r5fss0-0_nortos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A PI controller example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running FREERTOS.",
"name": "dcl_pi",
"location": "../../examples/dcl/dcl_pi/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_LAUNCHPAD"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_pi",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
@ -230,38 +486,6 @@
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Ddr Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_ddr",
"location": "../../examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"position_sense",
"hdsl_diagnostic_with_traces",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
@ -393,6 +617,38 @@
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Icss Sdfm Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "icss_sdfm",
"location": "../../examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_LAUNCHPAD"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"current_sense",
"icss_sdfm",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "web.page",
"resourceClass": [

257
.metadata/.tirex/am263x.content.tirex.json
View File

@ -1,4 +1,260 @@
[
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A Direct Form 2 2nd order example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running NORTOS.",
"name": "dcl_df22",
"location": "../../examples/dcl/dcl_df22/am263x-cc/r5fss0-0_nortos/ti-arm-clang/example.projectspec",
"devtools": [
"TMDSCNCD263"
],
"kernel": [
"nortos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_df22",
"r5fss0-0_nortos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A Direct Form 2 2nd order example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running FREERTOS.",
"name": "dcl_df22",
"location": "../../examples/dcl/dcl_df22/am263x-cc/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"TMDSCNCD263"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_df22",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A Direct Form 2 2nd order example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running NORTOS.",
"name": "dcl_df22",
"location": "../../examples/dcl/dcl_df22/am263x-lp/r5fss0-0_nortos/ti-arm-clang/example.projectspec",
"devtools": [
"LP-AM263"
],
"kernel": [
"nortos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_df22",
"r5fss0-0_nortos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A Direct Form 2 2nd order example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running FREERTOS.",
"name": "dcl_df22",
"location": "../../examples/dcl/dcl_df22/am263x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"LP-AM263"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_df22",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A PI controller example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running NORTOS.",
"name": "dcl_pi",
"location": "../../examples/dcl/dcl_pi/am263x-cc/r5fss0-0_nortos/ti-arm-clang/example.projectspec",
"devtools": [
"TMDSCNCD263"
],
"kernel": [
"nortos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_pi",
"r5fss0-0_nortos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A PI controller example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running FREERTOS.",
"name": "dcl_pi",
"location": "../../examples/dcl/dcl_pi/am263x-cc/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"TMDSCNCD263"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_pi",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A PI controller example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running NORTOS.",
"name": "dcl_pi",
"location": "../../examples/dcl/dcl_pi/am263x-lp/r5fss0-0_nortos/ti-arm-clang/example.projectspec",
"devtools": [
"LP-AM263"
],
"kernel": [
"nortos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_pi",
"r5fss0-0_nortos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.gettingstarted"
],
"description": "A PI controller example demonstrating the digital control library (DCL). CPU is R5FSS0-0 running FREERTOS.",
"name": "dcl_pi",
"location": "../../examples/dcl/dcl_pi/am263x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"LP-AM263"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"dcl",
"dcl_pi",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
@ -39,6 +295,7 @@
"name": "User Guide",
"location": "../../docs/api_guide_am263x/index.html",
"devtools": [
"TMDSCNCD263",
"LP-AM263"
],
"mainCategories": [

32
.metadata/.tirex/am64x.content.tirex.json
View File

@ -164,38 +164,6 @@
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Ddr Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_ddr",
"location": "../../examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"position_sense",
"hdsl_diagnostic_with_traces",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [

2
.metadata/.tirex/package.tirex.json
View File

@ -6,7 +6,7 @@
"rootCategory": [ "MOTOR CONTROL SDK", "MOTOR CONTROL SDK for AMXXX" ],
"version": "09.00.00.01",
"type": "software",
"image": "./mcu_plus_sdk.png",
"image": "./motor_control_sdk.png",
"license": "../../license.txt",
"devices": ["AMXXX"],
"tags": ["SDK", "Baremetal", "FreeRTOS"],

4
.metadata/product.json
View File

@ -12,11 +12,9 @@
"/kernel/dpl",
"/drivers/drivers",
"/board/board",
"/fs/fs",
"/networking/networking",
"/security/security",
"/usb/usb",
"/pru_io/pru_io",
"/xbar/xbar",
],
"devices": [
"AM64x",

6
.project/device/project_am243x.js
View File

@ -14,12 +14,13 @@ const device_defines = {
};
const example_file_list = [
"examples/dcl/dcl_df22/.project/mcsdk_project.js",
"examples/dcl/dcl_pi/.project/mcsdk_project.js",
"examples/position_sense/endat_diagnostic/single_channel/.project/project.js",
"examples/position_sense/endat_diagnostic/multi_channel_load_share/.project/project.js",
"examples/position_sense/endat_diagnostic/multi_channel_single_pru/.project/project.js",
"examples/position_sense/hdsl_diagnostic/multi_channel/.project/project.js",
"examples/position_sense/hdsl_diagnostic/single_channel/.project/project.js",
"examples/position_sense/hdsl_diagnostic_with_traces/.project/project.js",
"examples/position_sense/tamagawa_diagnostic/multi_channel/.project/project.js",
"examples/position_sense/tamagawa_diagnostic/single_channel/.project/project.js",
"examples/current_sense/icss_sdfm/.project/project.js",
@ -28,9 +29,10 @@ const example_file_list = [
"source/position_sense/endat/firmware/single_channel/.project/project.js",
"source/position_sense/endat/firmware/multi_channel_single_pru/.project/project.js",
"source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js",
"source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js",
"source/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js",
"source/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js",
"source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project.js",
"source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project.js",
"source/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js",
"source/position_sense/tamagawa/firmware/multi_channel/.project/project.js",
"source/position_sense/tamagawa/firmware/single_channel/.project/project.js",

3
.project/device/project_am263x.js
View File

@ -11,6 +11,8 @@ const device_defines = {
};
const example_file_list = [
"examples/dcl/dcl_df22/.project/mcsdk_project.js",
"examples/dcl/dcl_pi/.project/mcsdk_project.js",
"examples/position_sense/tamagawa_diagnostic_over_soc_uart/.project/project.js",
];
@ -135,5 +137,6 @@ module.exports = {
getDevToolTirex,
getProperty,
getLinuxFwName,
getProductNameProjectSpec,
getFlashAddr,
};

4
.project/device/project_am64x.js
View File

@ -19,7 +19,6 @@ const example_file_list = [
"examples/position_sense/endat_diagnostic/multi_channel_single_pru/.project/project.js",
"examples/position_sense/hdsl_diagnostic/multi_channel/.project/project.js",
"examples/position_sense/hdsl_diagnostic/single_channel/.project/project.js",
"examples/position_sense/hdsl_diagnostic_with_traces/.project/project.js",
"examples/position_sense/tamagawa_diagnostic/multi_channel/.project/project.js",
"examples/position_sense/tamagawa_diagnostic/single_channel/.project/project.js",
"examples/current_sense/icss_sdfm/.project/project.js",
@ -28,9 +27,10 @@ const example_file_list = [
"source/position_sense/endat/firmware/single_channel/.project/project.js",
"source/position_sense/endat/firmware/multi_channel_single_pru/.project/project.js",
"source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js",
"source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js",
"source/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js",
"source/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js",
"source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project.js",
"source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project.js",
"source/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js",
"source/position_sense/tamagawa/firmware/multi_channel/.project/project.js",
"source/position_sense/tamagawa/firmware/single_channel/.project/project.js",

11
.project/templates/product.json.xdt
View File

@ -20,7 +20,7 @@
"../mcu_plus_sdk/source",
],
"components": [
% if((args.device == "am64x") || (args.device == "am243x") || (args.device == "am263x")) {
% if((args.device == "am64x") || (args.device == "am243x")) {
"/motor_control",
"/kernel/dpl",
"/drivers/drivers",
@ -30,6 +30,15 @@
"/security/security",
"/usb/usb",
"/pru_io/pru_io",
% }
% if(args.device == "am263x") {
"/motor_control",
"/kernel/dpl",
"/drivers/drivers",
"/board/board",
"/networking/networking",
"/security/security",
"/xbar/xbar",
% }
],
"devices": [

2
.project/templates/projectspec_executable.xdt
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%%{
let profile_list = ["debug", "release"];
let profile_list = ["release", "debug"];
products = "";
if("syscfgfile" in args.project) {

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name="`args.project.name`_`args.project.board`_system_`args.project.tag`"
products="`products`"
configurations="
Debug,
Release,
Debug,
"
connection="TIXDS110_Connection.xml"
device="Cortex R.`args.device.getProjectSpecDevice(args.project.board)`"

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# Current Sense {#CURRENT_SENSE}
[TOC]
Current sensing is handled by the Programmable Real-Time Unit Industrial Communication Subsystem (PRU-ICSS). The PRU-ICSS is a co-processor subsystem containing Programmable Real-Time (PRU) cores which implements the low level firmware. The PRU-ICSS frees up the main ARM cores in the device for other functions, such as control and data processing.
## SDFM {#SDFM}
ICSS %SDFM is a sigma delta interface for phase current measurement in high performance motor and servo drives. During Sigma delta decimation filtering (SDDF) the PRU hardware provides hardware integrators that do the accumulation part of Sinc filtering, while the ICSS %SDFM firmware does differentiation part.
## Features Supported
- 3 %SDFM channels on single PRU core
- Normal current (NC) for data read: SINC3 filter with OSR 16 to 256
- Overcurrent (OC) for comparator: free running SINC3 filter with OSR 16 to 256
- Event generation(ARM interrupt for data read from DMEM, GPIO toggle for high and low thresholds)
- High and Low threshold comparator
- Trigger based normal current sampling
- Double update: Double normal current sampling per EPWM cycle
- %SDFM Sync with EPWM
## Features Not Supported
- Zero cross comparator
- OSR below 16
- Clock phase compensation
- Fast detect and trip generation
## ICSS SDFM Design
\subpage SDFM_DESIGN explains the design in detail.
## Example
\ref EXAMPLE_MOTORCONTROL_SDFM
## API
\ref SDFM_API_MODULE

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# %SDFM Interface Design {#SDFM_DESIGN}
[TOC]
## Introduction
This design implements Sigma delta interface on TI Sitara™ AM64x/AM243x.
ICSS %SDFM is a Sigma delta filter for phase current measurement.
Only two lines are required for each channel, differential pair each for %SDFM clock & %SDFM data.
Clock is provided by external device or internal device and data comes from sigma delta modulator in form of digital bit stream.
## System Overview
## Implementation
The Sigma delta filter is implemented on TI Sitara™ Devices.
Design is split into three parts – Sigma delta hardware support in PRU, firmware running in PRU and driver running in ARM.
Application is supposed to use the ICSS %SDFM driver APIs to leverage %SDFM functionality.
SDK example uses the %SDFM hardware capability in Slice 1 of PRU-ICSSG0.
### Specifications
<table>
<tr>
<th>Parameter
<th>Default Value
<th>Details
</tr>
<tr>
<td>Normal current OSR
<td>64
<td>Tested with 16, 32, 64, 128 and 256
</tr>
<tr>
<td>Over current OSR
<td>16
<td>Tested with 16, 32, 64, 128 and 256
</tr>
<tr>
<td>Sigma Delta Modulator Clock
<td>20 MHz
<td> Tested with 5MHz, 10MHz and 20MHz from clock from PRU-ICSSG ECAP and 5MHz clock from SoC EPWM1
</tr>
<tr>
<td>Simulated EPWM frequency
<td>8 KHz
<td>Tested up to 20KHz
</tr>
<tr>
<td>IEP frequency
<td>300 MHz
<td>Tested with 200MHz, 225MHz and 300MHz
</tr>
</table>
### ICSS SDFM PRU hardware
Refer section 6.4.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering in Technical Reference Manual(TRM) of AM243x for details.
### ICSS SDFM Firmware Implementation
Following section describes the firmware implementation of Sigma Delta Decimation Filter on PRU-ICSS.
#### Firmware Architecture
\image html SDFM_FIRMWARE_FLOWCHART.png "Overall Block Diagram"
- Firmware first clears the PRU registers and task manager.
- Then it waits for the ARM core to set %SDFM enable bit. After the enable bit is set, it sends an acknowledgement to ARM core.
- After this, the firmware does initialization of PRU-ICSSG's %SDFM hardware interface, task manager and IEP0.
- If threshold comparator is enabled, then a free run over current loop is setup, else it sets up an infinite waiting loop. In over current loop, the firmware reads sample data from the shadow copy register and does low and high theshold compersion with sample data, and depending on the configuration it toggles the GPIO pins.
- Time triggered normal current task is configured to be triggered based on IEP CMP4 event. When the CMP4 event hits, the task manager sets the program counter to normal current task. In normal current task, firmware reads sample data from accumulator and it checks for fourth normal current sample (for SINC3 filtering). If the current normal current sample belongs to fourth normal current sample, then it stores the same in data memory DMEM as normal current row data and trigger interrupt.
- At the end of normal current firmware task, execution flow comes into infinite waiting loop or over current loop.
##### Normal Curent (NC)
This section describes normal current implementation. Its implementation is trigger based. It starts execution when the trigger point is acquired (first time CMP4 event hits) and performs four continuous samplings to bring the accumulator and differntiator registers to stable state for the configured normal current OSR.
Initially the CMP4 register is configured with the first sample trigger start time and then until the next third continuous normal current sample it is updated with the normal current OSR sampling time. At the end of the fourth normal current sample again, it is updated with the second sample start time if double update is enabled otherwise with the first sample trigger start time.
\image html SDFM_NC_FLOW_CHART.png "Normal Current"
###### Single Update
Normal current sampling is done per EPWM cycle.
\image html SDFM_single_update.PNG "Single Update"
###### Double Update
Normal current sampling is done twice in one EPWM cycle.
\image html SDFM_Double_update.PNG "Double Update"
##### Over Current (OC)/Threshold Comparator
This section describes the over current implementation. It performs continuous sampling (free run) and when the sample value crosses the high or low threshold, the corresponding GPIO pin goes high.
\image html SDFM_OC_Flow_Chart.png "Over current"
\image html SDFM_GPIO_toggle.png "GPIOs behaviour for High and Low threshold"
#### Sync with EPWM and trigger timing
This section describes the EPWM to %SDFM synchronization and trigger timing for each EPWM cycle. At the end of the every EPWM cycle, the EPWM generates a sync out event that resets the IEP timer.
The firmware initiates normal current sampling at the sample trigger point in each EPWM cycle. It takes four consecutive samples to bring the accumulator and differentiator registers to stable state. It takes the first sample at the trigger point and the next three samples, each after ONE_SAMPLE_TIME.
Here ONE_SAMPLE_TIME is: OSR*(1/SD_CLK)
\image html SDFM_epwm_sync_and_trigger_timing.png "Sync with EPWM and trigger timing"
#### AM64x/AM243x EVM Pin-Multiplexing
<table>
<tr>
<th>Pin name
<th>Signal name
<th>Function
</tr>
<tr>
<td>GPIO_HIGH_TH_CH0
<td>MCU_SPI0_D1/B6
<td>Ch0 High threshold output
</tr>
<tr>
<td>GPIO_LOW_TH_CH0
<td>MCU_SPI1_D0/C7
<td>Ch0 low threshold output
</tr>
<tr>
<td>GPIO_HIGH_TH_CH1
<td>MCU_SPI1_CS0/A7
<td>Ch1 High threshold output
</tr>
<tr>
<td>GPIO_LOW_TH_CH1
<td>MCU_SPI1_CLK/D7
<td>Ch1 low threshold output
</tr>
<tr>
<td>GPIO_HIGH_TH_CH2
<td>MCU_SPI1_D1/C8
<td>Ch2 High threshold output
</tr>
<tr>
<td>GPIO_LOW_TH_CH2
<td>MCU_SPI0_CLK/E6
<td>Ch2 Low threshold output
</tr>
<tr>
<td>SD0_D
<td>PIN_PRG0_PRU0_GPO1
<td>Channel0 data input
</tr>
<tr>
<td>SD1_D
<td>PIN_PRG0_PRU0_GPO3
<td>Channel1 data input
</tr>
<tr>
<td>SD2_D
<td>PIN_PRG0_PRU0_GPO5
<td>Channel2 data input
</tr>
<tr>
<td>PRG0_ECAP0_IN_APWM_OUT
<td>PIN_PRG0_PRU1_GPO15
<td>ECAP output frequency
</tr>
<tr>
<td>GPIO_MTR_1_PWM_EN
<td>GPMC0_AD15/Y20
<td>Enable EPWM0 on 3-axis board
</tr>
<tr>
<td>SD8_CLK
<td>PIN_PRG0_PRU0_GPO16
<td>Comman %SDFM clock input pin
</tr>
</table>
\cond SOC_AM243X
#### AM243x LP Pin-Multiplexing
<table>
<tr>
<th>Pin name
<th>Signal name
<th>Function
</tr>
<tr>
<td>GPIO_HIGH_TH_CH0
<td>PRG1_PRU0_GPO18
<td>(J7.64)Ch0 High threshold output
</tr>
<tr>
<td>GPIO_LOW_TH_CH0
<td>PRG0_PRU1_GPO11
<td>(J7.70)Ch0 low threshold output
</tr>
<tr>
<td>GPIO_HIGH_TH_CH1
<td>PRG1_PRU0_GPO17
<td>(J7.65)Ch1 High threshold output
</tr>
<tr>
<td>GPIO_LOW_TH_CH1
<td>PRG1_PRU0_GPO7
<td>(J7.66)Ch1 low threshold output
</tr>
<tr>
<td>GPIO_HIGH_TH_CH2
<td>PRG0_PRU1_GPO1
<td>(J7.67)Ch2 High threshold output
</tr>
<tr>
<td>GPIO_LOW_TH_CH2
<td>PRG0_PRU1_GPO2
<td>(J7.68)Ch2 Low threshold output
</tr>
<tr>
<td>SD0_D
<td>PIN_PRG0_PRU0_GPO1
<td>(J4.32)Channel0 data input
</tr>
<tr>
<td>SD1_D
<td>PIN_PRG0_PRU0_GPO3
<td>(J2.19)Channel1 data input
</tr>
<tr>
<td>SD2_D
<td>PIN_PRG0_PRU0_GPO5
<td>(J2.13)Channel2 data input
</tr>
<tr>
<td>PRG0_ECAP0_IN_APWM_OUT
<td>PIN_PRG0_PRU1_GPO15
<td>(J6.59)ECAP output frequency
</tr>
<tr>
<td>SD8_CLK
<td>PIN_PRG0_PRU0_GPO16
<td>(J1.7)Comman %SDFM clock input pin
</tr>
</table>
\endcond

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INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/dcl/dcl.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/dcl.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/dcl_common.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/pi/dcl_pi.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/pi/dcl_pi2.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/pid/dcl_pid.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/pid/dcl_pidf64.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/df/dcl_df11.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/df/dcl_df13.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/df/dcl_df22.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/df/dcl_df23.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/common/dcl_aux.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/common/dcl_clamp.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/common/dcl_css.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/common/dcl_stability.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/common/dcl_zpk3.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/misc/dcl_error.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/misc/dcl_fdlog.h

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# Digital Control Library (DCL) {#DCL}
[TOC]
## Introduction
The Sitara™ Digital Control Library (DCL) provides a suite of robust software functions for developers of digital
control applications using the Texas Instruments Sitara MCU. DCL is a header-only library, and all functions in
the library are provided in the form of C source-code.
The DCL contains PI,PID and "Direct Form" controller types. The former are typically used to tune properties of
a transient response, while the latter are typically used to shape the open loop frequency response.
In addintion, DCL contains functions to convert controller parameters from one type to the other. As well as
functions to parameterize the controller given a transfer function.
Several utility modules such as error handling, data logging are also included as a supporting module.
## Features Supported
Supported controller modules (floating-point)
- Linear PI
- Linear PID
- Linear PI with double integrator
- Direct Form 1 (first order)
- Direct Form 1 (third order)
- Direct Form 2 (second order)
- Direct Form 2 (third order)
Other utility modules:
- Error Handling
- Testpoints
- Data Logging
## Features Not Supported
(Compared with C2000Ware's DCL)
- Fix-point controller modules
- Non-linear PID controller
- Reference Generator and performance index
- Multi-channel data logs
## Benchmark Results
A benchmark on R5F core has been conducted to observe the following results when running controller arithmetic:
<table>
<tr>
<th>Controller Function
<th>Cpu Cycles
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> PI Controller </td></tr>
<tr>
<td>DCL_runPISeries</td>
<td>49</td>
</tr>
<tr>
<td>DCL_runPIParallel</td>
<td>50</td>
</tr>
<tr>
<td>DCL_runPISeriesTustin</td>
<td>56</td>
</tr>
<tr>
<td>DCL_runPIParallelEnhanced</td>
<td>62</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> PI2 Controller </td></tr>
<tr>
<td>DCL_runPI2Series</td>
<td>74</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> PID Controller </td></tr>
<tr>
<td>DCL_runPIDSeries</td>
<td>65</td>
</tr>
<tr>
<td>DCL_runPIDParallel</td>
<td>65</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> DF11 Controller </td></tr>
<tr>
<td>DCL_runDF11</td>
<td>24</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> DF13 Controller </td></tr>
<tr>
<td>DCL_runDF13</td>
<td>43</td>
</tr>
<tr>
<td>DCL_runDF13Clamp</td>
<td>53</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> DF22 Controller </td></tr>
<tr>
<td>DCL_runDF22</td>
<td>27</td>
</tr>
<tr>
<td>DCL_runDF22Clamp</td>
<td>41</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> DF23 Controller </td></tr>
<tr>
<td>DCL_runDF23</td>
<td>29</td>
</tr>
<tr>
<td>DCL_runDF23Clamp</td>
<td>45</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> PID 64bit Controller </td></tr>
<tr>
<td>DCL_runPIDF64Series</td>
<td>185</td>
</tr>
<tr>
<td>DCL_runPIDF64Parallel</td>
<td>174</td>
</tr>
</table>
- Ran with TI Clang Compiler v2.1.3.LTS, with -Os flag and all DCL functions inlined, obtained the average result from 600 consecutive reading of running the controller with DPL CycleCountP.
- Simulated inputs are based on arbitrary sinusoidal waves and saturation condition that roughly clamps ~50% of the time. For functions with clamp (PI,PI2,PID and DF Clamps), clock cycle varies depending on clamping condition and provided inputs.
- Actual result may vary depending on provided datasets and memory configuration. For R5F, it is recommended for users to map control loops to TCM for the best performance.
## Provided Examples
The following examples has been provided to demonstrate the DCL library:
- \ref EXAMPLES_DCL_PI
- \ref EXAMPLES_DCL_DF22
## Additional References {#DCL_ADDITIONAL_REFERENCES}
N/A
## API
\ref DCL_API_MODULE

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# EnDat {#ENDAT}
[TOC]
## Introduction
EnDat is a bidirectional interface for position encoders. During EnDat operation the EnDat receiver receives position information from the EnDat position encoder.
## Features Supported
- EnDat 2.2 command set
- EnDat 2.1 command set
- Interrupted and continuous clock mode
- Cable length up to 100m @8MHz
- Propagation delay compensation (capable of handling different propagation delay of different
propagation delay of different channels in concurrent multi
channel configuration)
- Automatic estimation of propagation delay
- Receive on-the-fly CRC verification of position, parameters and additional information
- Two modes of operation - host trigger and periodic trigger
- Channel select
- Concurrent multi channel support (up-to 3 encoders with identical part number @ 8MHz maximum)
- "Multi Channel with Encoders of Different Make" using load share mode (Each of PRU, RTU-PRU, and TX-PRU from one PRU-ICSSG slice handles one channel)
- Safety Readiness: Recovery time
- Clock up to 16MHz with single channel and load share mode (multi channel)
## Features Not Supported
In general, peripherals or features not mentioned as part of "Features Supported" section are not
supported in this release, including the below
- Independent clocks on multi channel mode.
- Continuous clock mode in Multi-channel single PRU mode
### Limitations
This section describes known limitations of the current implementation in multi-channel single PRU mode.
- Clock above 8 MHz: it is not possible to over sample, downsample and store one bit for all three channels in one clock cycle time.
- Reset command CRC failure: The encoder which takes more time in reset operation will show CRC failure because the reset time is not the same for each encoder so the acknowledgment will not arrive on same time for all encoders at the master end.
## SysConfig Features
@VAR_SYSCFG_USAGE_NOTE
SysConfig can be used to configure things mentioned below:
- Selecting the ICSSG instance. (Tested on ICSSG0)
- Selecting the ICSSG0PRUx instance.(Tested on ICSSG0-PRU1)
- Configuring PINMUX.
- Channel selection.
- Selecting Multi Channel with Encoders of Different Make" using load share mode.
## ENDAT Design
\subpage ENDAT_DESIGN explains the design in detail.
## Example
\ref EXAMPLE_MOTORCONTROL_ENDAT
## API
\ref ENDAT_API_MODULE

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# EnDat Protocol Design {#ENDAT_DESIGN}
[TOC]
## Introduction
This design implements EnDat Receiver (a.k.a subsequent electronics) on TI Sitara™ AM64x/AM243x EVM.
EnDat is a digital bidirectional serial interface for position encoders, also suited fo safety related applications.
Only four signal lines are required, differential pair each for clock and data.
Clock is provided by receiver and data is bidirectional. Data is transmitted in synchronism with clock.
Transfer between receiver and encoder at the physical layer is in accordance with RS485, with transceiver at both ends.
## System Overview
Position feedback system consists of a position encoder attached to a motor, up to 100 meter of cable which provides power and serial communication and the receiver interface for position encoder.
In case of Sitara™ AM64x/AM243x processor the receiver interface for position encoder is just one function of a connected drive controller.
The AM64x/AM243x provides in addition to the resources for Industrial Ethernet and motor control application including on-chip ADCs, Delta Sigma demodulator for current measurement.
EnDat Receiver on Sitara™AM64x/AM243x processor uses one ICSSGx Slice.
Clock, data transmit, data receive and receive enable signals from PRU1 of ICSS_G is available in AM64x/AM243x EVM.
## Implementation
The EnDat receiver function is implemented on TI Sitara™ Devices.
Encoder is connected to IDK via universal Digital Interface TIDA-00179(https://www.ti.com/tool/TIDA-00179), TIDEP-01015(3-axis board) and 3 Axis Interface card.
Design is split into three parts – EnDat hardware support in PRU, firmware running in PRU and driver running in ARM.
Application is supposed to use the EnDat driver APIs to leverage EnDat functionality.
SDK examples used the EnDat hardware capability in Slice 1 (either 1 core or 3 cores based ont the confiuration) of PRU-ICSSG0.
Remaining PRUs in the AM64x/AM243x EVM are available for Industrial Ethernet communication and/or motor control interfaces.
### Specifications
<table>
<tr>
<th>Parameter
<th>Value
<th>Details
</tr>
<tr>
<td>Maximum Cable Length
<td>100m
<td>Supports up-to 8MHz with delay compensation
</tr>
<tr>
<td>Maximum Frequency
<td>16 MHz
<td>Supports up-to 20m cable
</tr>
<tr>
<td>Startup/Initialization Frequency
<td>200 KHz
<td>After power on or reset
</tr>
<tr>
<td>Frequencies supported
<td>Upto 8 MHz
<td>Changeable at run-time
</tr>
<tr>
<td>CRC
<td>6 bits
<td>Position/data verification
</tr>
<tr>
<td>Receive oversample ratio
<td>8
<td>
</tr>
</table>
### EnDat PRU hardware
Refer TRM for details
### EnDat Firmware Implementation
Following section describes the firmware implementation of EnDat receiver on PRU-ICSS.
Deterministic behavior of the 32 bit RISC core running upto 333MHz provides resolution on sampling external signals and generating external signals.
It makes uses of EnDat hardware support in PRU for data transmission.
There are three different variations of PRU-ICSS firmware.
1. Single Channel
2. Multi Channel with Encoders of Same Make
3. Multi Channel with Encoders of Different Make
#### Implementation for Single Channel and Multi Channel with Encoders of Same Make
Single core of PRU-ICSSG slice used in this configuration.
\image html endat_module_integration.png "ARM, PRU, EnDat module Integration for for "Single Channel" or "Multi Channel with Encoders of Same Make" configuration"
#### Implementation for Multi Channel with Encoders of Different Make
Each of PRU, TX-PRU and RTU-PRU handle one channel in this configuration
Enbale load share mode in case of multi make encoders.
\image html Endat_load_share_mode.png "PRU, EnDat module Integration for "Multi Channel with Encoders of Different Make" configuration"
#### Firmware Architecture
\image html endat_overall_block_diagram.png "Overall Block Diagram"
Firmware first does initialization of PRU-ICSSG's EnDat hardware interface and EnDat encoder.
Then it waits for the user to provide command (user after setting up the command, sets command trigger bit), upon detecting trigger, first it checks whether the command requested is a continuous mode or a normal command.
If it is a normal command, reads command, it’s attribute like transmit bits, receive bits etc., then it transmits the data and collected the data sent by the encoder stored onto a buffer with one byte representing a bit (since oversample ration of 8 is used).
Next it checks whether there is 2.2 command supplement to be transmitted based on attributes, if so it transmits it.
The received data is now downsampled to extract bit from oversampled 8 bits and the result written to the defined PRU RAM locations.
If command requested is continuous mode, 2.1 position command will be transmitted. During receive, it is different from the normal mode that downsampling is done on-the-fly, i.e. downsampling is done as soon as each bit is received. This is done due to the timing constraints with continuous mode, as data is continuously being received.
At the end of transaction as requested by the user, trigger bit that is set by the user is unset.
User can wait on this bit to know that the command has been completed.
EnDat driver provides API to achieve this.
##### Initialization
###### Initialization for "Single Channel" and "Multi Channel with Encoders of Same Make" configurations
\image html endat_initialization.png "Initilization for Single PRU mode"
###### Initialization for "Single Channel" and "Multi Channel with Encoders of Different Make" configuration
\image html endat_load_share_mode_initialization.png "Initilization for Load share mode"
Before executing the firmware, the ARM (R5) core needs to enable EnDat mode in PRU-ICSSG first, then configure the clock to 200KHz, with oversample ratio of 8 (hence receive clock would be 200 * 8 KHz).
The entire EnDat configuration MMRs are cleared. Through the defined interface (PRU RAM location), user requested channel is determined in Single pru configuration.
Then power-on-init as per specification is implemented, after which encoder is reset by sending reset command.
Firmware setups the command and it’s attribute for all the commands that are sent during initialization. Alarms, errors and warning are cleared.
Firmware then determines number of clock pulses for position and whether encoder supports EnDat 2.2. Propagation delay is then estimated.
If user has required for clock to be configured, it is obeyed, else it defaults to 8MHz. At the end of the initialization status is updated.
###### Synchronization among PRU cores for "Multi Channel with Encoders of Different Make" configuration
If using "Multi Channel with Encoders of Different Make" configuration where load share mode is enabled, one of the cores among enabled cores will be set as the primary core for performing global configurations of PRU-ICSSG's EnDat interface. These global configurations include clock frequency configuration and TX global re-initialization.
There needs to be a synchronization between PRUs before changing any global configuration. For this purpose, each active PRU core sets synchronization bit before any operation needing synchronization and clears the synchronization bit when it is ready. The assigned primary core will wait for all active channel's synchronization bits to be cleared and then perform the global configuration.
##### Send and Receive
\image html endat_send_receive.png "Send And Receive"
If requested command attribute indicates 2.2 command supplement, clock is configured to free run stop low mode, else to free run stop high.
Command is written to the transmit fifo and send routine followed by receive is invoked.
###### Send
\image html endat_send.png "Send"
Transmit and receive frame sizes are configured in PRU EnDat hardware.
With long cables, it may be required to configure receive frame size lesser than receive bits so that extra clocks are not sent to the encoder.
If transmit was going on, it will till it has finished and then transmit GO bit is set, which would start the new transmission.
###### Receive
\image html endat_receive.png "Receive"
Receive bits obtained via command attribute is stored as header (initial 2 bytes) in the receive buffer.
Then wait’s till receive valid flag has been set, once set, 1 byte corresponding 1 bit (because of oversampling of 8) is read and stored in receive buffer and the flags are cleared.
Receive buffer pointer is incremented & receive bit count decremented. This continues till count is zero, once zero, it extracts receive data one more time to take care of SB (receive count excludes SB).
If 2.2 command supplement is not present, transmit re-init is done.
If using "Multi Channel with Encoders of Different Make" configuration where load share mode is enabled, the primary core waits for synchronization bits for active channels to be cleared before performing TX Global Init.
\image html Endat_Load_share_receive.png "Receive In load share mode"
###### EnDat 2.2 Command Supplement Send
\image html endat_2_2_supplement_send.png "EnDAT 2.2 command supplement send"
Clock mode is configured to stop low after transmit. 2.2 command supplement to transmitted is written to fifo preceded by 7 dummy bits & SB.
Transmission is configure to transmit till end of the fifo. Transmission is started after making sure that transmit module is not busy.
###### Receive Downsample
\image html endat_receive_downsampling.png "Downsampling"
This is the most complex portion of the firmware. Received data is exposed through PRU interface in four bytes.
First two words (word = 4 bytes) holds the position data, third holds additional information 2 (if only second additional info is present or both present) or 1 (if only first additional info is present) & the last additional information 1 (if both present).
The order is as mentioned in EnDat 2.2 specification. Splitting the received data on word boundaries when additional info’s are present causes the complexity here.
If command is neither 2.2 nor position request or if no additional info is present, handling is easy – just copy the received data into initial 2 words in the order it is received.
If command is 2.2 position command and depending on the number of additional info’s, markers (used in the downsampling loop) are set to write additional info’s to next word boundaries.
If only one addinfo is present, marker “rx pos bits” stores clocks required to receive position (inclusive of CRC, F1 & F2).
If both addinfo’s are present another marker is set to 2 words (first 2 words holds the position) plus 30 bit to account for addinfo.
If markers are not required, then their values are set so that it never matches the counting receive bits, hence the value “0xff”.
After updating the marker, number of received bits is retrieved from the receive buffer header. SB is skipped for downsampling and the result registers are cleared.
Next, each byte (8 bit, oversample of 8) is read from the receive buffer, 4th bit of each decide the actual received bit. This is continued till the end of receive buffer.
If during the loop, receive bit count matches any of the marker, bit count is updated appropriately. This helps is naturally bringing the received data as per the word format specified by the interface.
In the loop, as the number of bits reaches word boundary, it will start saving received data to next word. At the end of the loop, the last word is copied to the result register.
###### Continuous mode
\image html endat_continuous_mode.png "Continuous Mode"
2.1 position command as well as it’s attribute that been setup by the user is read first. Clock is configured for free run mode. Position command is written fifo and send routine is invoked.
Then receive is done along with on-the-fly downsampling, this is required as time between receipt of successive position data is less than the time that dowsampling routine (mentioned earlier) takes.
Once data is read and dowsampled on-the-fly, command trigger interface is read to see if user wants to stop continuous mode, if so, do transmit re-init, disable receive and wait till the end of re-init.
###### Receive and On-The-Fly Downsample
\image html endat_on_fly_downsampling.png "Endat on the fly Downsampling"
Two registers (a word each) that hold the result are cleared initially. Upon receiving the first receive valid, it discards it and proceeds to wait for the next one as the first one is SB.
Thereafter for every valid flag set, 4th bit in the received byte is checked to find the actual received bit and it stored, word crossing is also taken care.
After all the bits for a position command is received, receive is disabled and is activated only after 2T clock cycles – this is to prevent falsely detecting SB immediately (upon calling this routine back-to-back as mentioned in previous section) after encoder has finished sending data as it can pull data line high for 2T more clock cycles.
#### Recovery Time Measurement
Recovery Time is measured only for Type 2.2 commands.
The factory default settings for the Recovery Time is programmed to 10us <= RT <= 30us. It can only be changed to 1.25us <= RT <=3.75us for type 2.2 mode commands. For clock pulse frequence <= 1MHz, RT must be set to 10us <= RT <= 30us.
The User can set the function parameters in word 3 at "0xB9" memory area for RT range. If bit 0th is unset and 1st bit is set of word3 then RT will belong to large range(10us-30us) and if 0th bit is set and 1st bit is unset of word3 then RT will belong to short range(1.25us to 3.75us).
##### Method for measuring the recovery time for position command
\image html Endat_Recovery_Time_For_Position.png "Endat Recovery time for Endat 2.2 position command "
\image html Endat_RT_FlowChart_for_position.png "Endat Recovery time flow-chart for Endat 2.2 position command"
1. After the CRC bits are received, there is a wait for rising clock edge.
2. Start the measurement of Recovery Time using PRU cycle counter (The cycle counter is set to zero).
3. Wait for falling edge of the data from encoder (RX).
4. Read the PRU cycle counter which gives the value of Recovery Time in PRU Clock Cycle units and store it to DMEM.
##### Method for measuring the recovery time for supplement command
\image html Endat_Recovery_Time_For_Supplement.PNG "Endat Recovery time for Endat 2.2 supplement command "
\image html Endat_RT_FlowChart_for_supplement.png "Endat Recovery time flow-chart for Endat 2.2 supplement command"
1. After TX_GO bit is set which starts the TX, wait for TX FIFO level to reach 0
2. In case of Single Channel or Multi Channel with Encoders of Different Make mode, wait for RX enable. But In case of Multi Channel with Encoders of Same Make mode, wait for TX complete.
3. After the CRC bits are received, there is a wait for rising clock edge.
4. Start the measurement of Recovery Time using PRU cycle counter (The cycle counter is set to zero).
5. Wait for falling edge of the data from encoder (RX).
6. Read the PRU cycle counter which gives the value of Recovery Time in PRU Clock Cycle units and store it to DMEM.
##### NOTE for Multi-channel Single PRU Mode
We can not measure the recovery time as accurately as single channel or multi channel load share, because same PRU has to poll for 3 channels. So we are doing a sequential polling for each channel.
1. Wait for rising edge in clock for all connected channels
2. Start the measurement of Recovery Time using PRU cycle counter (The cycle counter is set to zero).
3. Wait for RX completion on all connected channels. We start checking completion for all connected channels one by one. Whenever completion is detected for a channel, we save the PRU cycle counter value and continue the wait for remaining channels.
### EnDat Hardware interface
The physical data transmission in EnDat is done using RS-485 standard. The data is transmitted as differential signals using the RS485 between the EnDat Receiver and the Encoder.
The Receiver sends the clock to the EnDat encoder, data transmission in either direction (one at a time) occurs in synchronism with the clock. The design uses two differential signals for each of the lines (clock and data).
EnDat Receiver and the encoder is connected using the RS-485 transceiver. Data is transmitted differentially over RS-485. It has the advantages of high noise immunity and long distance transmission capabilities.
#### AM64x/AM243x EVM Pin-Multiplexing
<table>
<tr>
<th>Pin name
<th>Signal name
<th>Function
</tr>
<tr>
<td>PRG0_PRU1_GPO0
<td>pru1_endat0_clk
<td>Channel 0 clock
</tr>
<tr>
<td>PRG0_PRU1_GPO1
<td>pru1_endat0_out
<td>Channel 0 transmit
</tr>
<tr>
<td>PRG0_PRU1_GPO2
<td>pru1_endat0_outen
<td>Channel 0 transmit enable
</tr>
<tr>
<td>PRG0_PRU1_GPI13
<td>pru1_endat0_in
<td>Channel 0 receive
</tr>
<tr>
<td>PRG0_PRU1_GPO3
<td>pru1_endat1_clk
<td>Channel 1 clock
</tr>
<tr>
<td>PRG0_PRU1_GPO4
<td>pru1_endat1_out
<td>Channel 1 transmit
</tr>
<tr>
<td>PRG0_PRU1_GPO5
<td>pru1_endat1_outen
<td>Channel 1 transmit enable
</tr>
<tr>
<td>PRG0_PRU1_GPI14
<td>pru1_endat1_in
<td>Channel 1 receive
</tr>
<tr>
<td>PRG0_PRU1_GPO6
<td>pru1_endat2_clk
<td>Channel 2 clock
</tr>
<tr>
<td>PRG0_PRU1_GPO12
<td>pru1_endat2_out
<td>Channel 2 transmit
</tr>
<tr>
<td>PRG0_PRU1_GPO8
<td>pru1_endat2_outen
<td>Channel 2 transmit enable
</tr>
<tr>
<td>PRG0_PRU1_GPI11
<td>pru1_endat2_in
<td>Channel 2 receive
</tr>
<tr>
<td>GPIO42
<td>endat_en
<td>Onboard RS485 receive enable
</tr>
</table>
\cond SOC_AM243X
##### AM243x-LP Booster Pack Pin-Multiplexing
<table>
<tr>
<th>Pin name
<th>Signal name
<th>Function
</tr>
<tr>
<td>PRG0_PRU1_GPO0
<td>pru1_endat0_clk
<td>Channel 0 clock
</tr>
<tr>
<td>PRG0_PRU1_GPO1
<td>pru1_endat0_out
<td>Channel 0 transmit
</tr>
<tr>
<td>PRG0_PRU1_GPO2
<td>pru1_endat0_outen
<td>Channel 0 transmit enable
</tr>
<tr>
<td>PRG0_PRU1_GPI13
<td>pru1_endat0_in
<td>Channel 0 receive
</tr>
<tr>
<td>GPIO Pin(GPIO1_78)
<td>ENC1_EN
<td>Enbale endat mode in Axis 1 of BP (C16 GPIO pin)
</tr>
</table>
\endcond

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# HDSL {#HDSL}
[TOC]
## Introduction
The HDSL firmware running on ICSS-PRU provides a defined well interface to execute the HDSL protocol.
## Features Supported
- Safe position
- Fast position, speed
- Communication status
- External pulse synchronization
- Register interface to be compatible with SICK HDSL FPGA IP Core (apart from the differences listed in \ref HDSL_EXCEPTIONS_LIST)
- Parameter channel communication
- Short message
- Long message
- Safety
- Two channels support on am243x-evm
- Single channel support on am243x-lp
- Tested with three different encoder makes (EDM35, EKS36, EKM36)
## Features Not Supported
In general, peripherals or features not mentioned as part of "Features Supported" section are not
supported, including the below
- 100m cable
- Three channel support using single PRU-ICSSG slice
- Pipeline Channel
## SysConfig Features
@VAR_SYSCFG_USAGE_NOTE
SysConfig can be used to configure things mentioned below:
- Selecting the ICSSG0PRUx instance.(Tested on ICSSG0-PRU1)
- Configuring PINMUX
- Channel selection
- Mode Selection (Free run/Sync mode)
- Hardware selection (Booster Pack for am243x-lp)
## HDSL Design
\subpage HDSL_DESIGN explains the design in detail.
## Register List
\subpage HDSL_REGISTER_LIST contains the description of registers in TI's HDSL implementation. Please note that all the corresponding register fields are not implemented.
## Exceptions
\subpage HDSL_EXCEPTIONS_LIST lists the exceptions TI's HDSL implementation when compared with SICK HDSL FPGA IP Core. Please note that all the corresponding register fields are not implemented.
## Example
\ref EXAMPLE_MOTORCONTROL_HDSL
## API
\ref HDSL_API_MODULE

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# HDSL Protocol Design {#HDSL_DESIGN}
[TOC]
## Introduction
This document presents the firmware implementation details of the Hiperface DSL protocol (SICK STEGMANN, 2010) for the PRU0 in ICSS0 on the AM64x/AM243x EVM.
## System Overview
### Sitara™ AM64x/AM243x Processor
Refer TRM for details
#### PRU-ICSS
Refer PRU-ICSS chapter of AM64x/AM243x Technical Reference Manual
## Software Architecture
The firmware consists of two layers .On the one hand, there is the datalink layer, which is responsible for establishing a communication link to the encoder, monitoring the connection quality and preparing the data.
On the other hand, there is the transport layer that processes the data and determines what information is sent over the parameter channel. Figure "Layer Model" illustrates the relationship between the two layers.
The datalink layer assembles the information from the different channels and puts the data symbol by symbol to the channel buffers. The channel buffers are large enough to carry the data of a whole V-Frame for each channel. .
The transport layer controls the data sent over the parameter channel by setting the symbol to send for the next H-Frame in the parameter channel buffer. This buffer can carry only one symbol.
Both layers have direct access to the register interface that is provided to the higher layers.
\image html hdsl_layer_model.png "Layer Model "
Hiperface DSL specifies a state machine for the Receiver. This implementation features an additional state for loading new firmware to the PRU. Figure "State Machine" depicts the modified state machine.
Furthermore, this implementation exhibits three code sections in the firmware. The first one is for initializing the state machine up to the LOADFW state.
\image html hdsl_state_machine.png "State Machine"
The second section contains datalink functionalities that are needed for the startup phase as well as for the normal workflow. The transport layer functionalities reside in the third section.
### Datalink Layer
The datalink layer is responsible for handling the communication link to the encoder. This includes the sampling, cable delay compensation, DC line balancing, encoding and decoding of data and the monitoring of the connection quality.
#### Sampling
During the reception of the salve answer, the SCU oversamples the data by factor 8. This allows the firmware to compensate signal deficits, such as delay. During the LEARN state the receiver calculates the sample edge based on the first received bit.
Assuming the oversampled data is exactly aligned with one bit, the best position for the sample edge would be either bit 3 or bit 4. An unalignment of the oversampled data with the actual bit results in a shift of the sample edge. The unalignment can be measured by counting the number of ‘1’ in the data, whereas a count of 4 equals the worst alignment and a count of 0 or 8 equals perfect alignment. The number of ’1’ (n) in the oversampled data is determined using a LUT and the following calculation provides the position for the sample edge (E):
E=(4+n)%8
\image html hdsl_sampling.png "Sampling"
#### Delay Measurement and Compensation
During the LEARN state the encoder sends a test pattern to the receiver. This is used to determine the cable delay. While the test pattern is sent, the receiver records all incoming bits and searches for the beginning of the test pattern. The offset, where the test pattern starts, is the cable delay in units of bits.
\image html hdsl_test_pattern.png "Test Pattern"
After the cable delay is measured, the receiver uses this knowledge to compensate the cable delay in subsequent states. This is performed by waiting for the calculated amount of bits as soon as the encoder answer window starts. The next bit on the line is the first bit of the actual encoder answer.
#### Data Encoding and Decoding
The datalink layer has the responsibility to decode and encode the data according to an 8b/10b scheme (Franaszek, 1983). The 8b/10b encoding/decoding is split into two parts, 3b/4b and 5b/6b encoding/decoding. Each of the encoding and decoding processes is performed by using a LUT. Hiperface DSL assumes a transmission with LSB first. Therefore, in the encoding procedure, the index of the LUT is in MSB first order, while the LUT entries are in LSB first order (and vice versa when decoding data). This way, the firmware does not need to handle the reversing of the bit order. When encoding the data, the firmware handles the sending of the correct polarity of the sub-blocks using the measured line disparity.
During receive, the firmware detects byte errors and special characters by checking the received encoded data according to the paper (Franaszek, 1983)
#### Received Signal Strength Indication (RSSI)
The RSSI is calculated by determining the number of samples between two edges during a bit period. The samples that form the longest sequence between two edges represent the stable bit period, which is used to calculate the RSSI. Instead of calculating the stable period in the firmware, a pre-calculated LUT is utilized to speed up the process. First, the edges in a bit period are determined, which is performed by a XOR operation (Figure: hdsl_rssi)]. The searched RSSI value is looked-up in the table by using the result of the XOR operation as the index.
\image html hdsl_rssi.png "Test Pattern"
#### Cyclic Redundancy Check Algorithm
A 16bit CRC verification of the data is used on multiple occasions. It is used for the vertical channel, secondary channel and messages. In order to distribute the computation load equally over all H-Frames, the firmware calculates a running CRC for those data (except for short messages). The algorithm uses a LUT with 256 entries and 2 bytes per entry, whereas each entry is the 16bit CRC for the corresponding LUT index. The basic approach for the calculation of the 16bit CRC is shown as C code in the following:
uint16_t calc_crc(uint8_t *data, uint32_t size) { uint16_t crc = 0; uint32_t i; for(i = 0; i < size; ++i) { crc = ((*data) << 8) ^ crc; crc = lut[crc>>8] ^ (crc << 8); } return (crc ^ 0xff); }
### Transport Layer
The transport layer processes the channel information which was prepared by the datalink layer. This includes the calculation of the fast position as well as the handling of messages.
#### ∆∆Position Estimation
During normal workflow, it can occur that the received ∆∆Position data cannot be used for calculations. This is the case on either a transmission error or an internal encoder error. In order to check for a transmission error, the transport layer checks if the datalink layer detected a byte error and verifies the CRC in the acceleration channel. If no transmission error occurred, the transport layer searches for the occurrence of two K29.7 to recognize an internal encoder error. In case one of the verification of the data fails, the estimation algorithm shown in Figure
\image html hdsl_delta_pos.png "Estimation Algorithm for ∆∆Position"
## Messages
The transport layer handles the messaging. Since it is possible that the higher layers send a long and a short message at the same time, the transport layer has to decide which message to send first. In this implementation short messages are always favored over long messages.
### Short Message
Remote (DSL motor feedback system) registers that indicate interface information are mirrored in the DSL Receiver under register addresses 40h to 7Fh. These remote registers are addressed in the same way as DSL Receiver registers. As the values of remote registers are transmitted via the Parameters Channel and hence via the DSL cables, the delay between polling and answer for "short message" transactions depends on the connection cables of the systems in question. There is no delay, as this information is stored directly in the IP-Core S_PC_DATA.. The Parameters Channel can only transmit one "short message" at a time. Several remote registers can only be polled in sequence, i.e. after the previous answer has been received.
Note: It should be noted that a "short message" can be triggered during a running "long message" transaction.
## Synchronization with External Pulse {#HDSL_DESIGN_SYNC}
According to the Hiperface DSL specification, the falling edge inside the EXTRA window should coincide with the external synchronization pulse.
At the beginning of the startup phase, the firmware measures the time interval of the external pulse and calculates the required number of bits for the H-Frame.
Based on this number the stuffing length and EXTRA window size is derived.
Afterwards, the PRU waits to match its timing with the timing of the external synchronization pulse and starts the transmission.
Since it is possible to use time intervals for the external pulse that are not multiples of the bit duration, the firmware needs to adjust the H-Frame size on the fly.
Furthermore, during the EXTRA window the PRU transmits the data (sample edge) with a granularity of 13.3ns to increase the synchronization accuracy. Figure "Synchronization of External Pulse with Sample Edge in EXTRA Window" and "Illustration of Synchronization Algorithm" depict the concept.
The EXTRA_TIME_WINDOW is a fixed value that is calculated at startup to match the external pulse frequency. The TIME_REST value gives the number of overclocked ‘1’ that needs to be sent during the last bit of the EXTRA window.
\imageStyle{hdsl_external_sync.png,width:40%}
\image html hdsl_external_sync.png "Synchronization of External Pulse with Sample Edge in EXTRA Window"
In other words, the TIME_REST value represents the sample edge in a fine granularity dimension (13.3ns). While the sample edge can be send with a finer granularity, the granularity of the size of the EXTRA window is still in whole bit durations (106.67ns).
Consequently, there is an overhead, if the external pulse period is not a multiple of the bit duration. This overhead is compensated in the next H-Frame by changing the size of the EXTRA window. As a result, the size of the H-Frame is varying over time.
It is possible that these calculations lead to the excess of the maximum or minimum EXTRA window size. Therefore, the number of bits for the stuffing and EXTRA window is readjusted on a violation.
\imageStyle{hdsl_sync_algo.png,width:40%}
\image html hdsl_sync_algo.png "Illustration of Synchronization Algorithm"
The algorithm is given as C code in the following:
/* EXTRA_SIZE equals the number of bits for the EXTRA window minus 1 */
if(EXTRA_EDGE == 0)
TIME_REST += 8;
short b = (EXTRA_SIZE << 3) + TIME_REST;
short overhead = (EXTRA_SIZE << 3) + 8 - TIME_EXTRA_WINDOW;
EXTRA_SIZE = (b - overhead) >> 3;
TIME_REST = (b - overhead) - (EXTRA_SIZE << 3);
if(EXTRA_SIZE < 3) {
EXTRA_SIZE += 6;
NUM_STUFFING -= 1;
TIME_EXTRA_WINDOW += (8*6);
}
if(EXTRA_SIZE > 8) {
EXTRA_SIZE -= 6;
NUM_STUFFING += 1;
TIME_EXTRA_WINDOW -= (8*6);
}
EXTRA_EDGE represents the TIME_REST value in a format that can be pushed to the TX FIFO for transmission. For instance, if TIME_REST is 4, EXTRA_EDGE is 0xf0. The edge would be in the middle of the bit duration. The value NUM_STUFFING gives the number of stuffing blocks (each block consist of 6 bits).
For further improvement of the synchronization, the time difference (∆t) between the external pulse and the sample edge we transmit is measured (Figure "Time difference between External Pulse and Sample Edge").
\imageStyle{hdsl_external_sync_sample_edge.png,width:40%}
\image html hdsl_external_sync_sample_edge.png "Time difference between External Pulse and Sample Edge"
Sync pulse jitter is under 100ns. Please refer to the image below for jitter calculation waveforms.
\image html hdsl_sync_mode_waveforms.png "HDSL Sync mode waveforms for 2 channels"
\image html hdsl_sync_mode_jitter.jpg "HDSL Sync mode jitter analysis"

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# TI HDSL Exceptions List {#HDSL_EXCEPTIONS_LIST}
Notable exceptions in TI HDSL Solution when compared with SICK HDSL MASTER IP Core release version 1.07 are described below:
1. SPI interface is not available to access the HDSL Master. Registers are present in Data Memory of Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS), which can be accessed directly by the ARM processor core.
2. Pipeline for SensorHub Channel Data is not available.
3. Control signals similar to SICK HDSL MASTER IP Core are not available, except SYNC signal. Instead of INTERRUPT signal, interrupts are triggered to ARM processor core.
4. Test signals similar to SICK HDSL MASTER IP Core are not available.
5. TI HDSL Solution's register map is register compatible with SICK HDSL MASTER IP Core release version 1.07, with few exceptions listed below:
<table>
<tr>
<th> Register(s)
<th> Remarks
</tr>
<tr>
<td> SYS_CTRL Bits 5:0 (FRST, LOOP, PRDY, SPPE, SPOL, OEN)
<td> **Not available in TI HDSL Solution**
</tr>
<tr>
<td> EVENT_H Bit 7 (INT)
<td> **Not available in TI HDSL Solution**
</tr>
<tr>
<td> EVENT_H Bit 1 (DTE) <br/>
MASK_H Bit 1 (MDTE) <br/>
ONLINE_STATUS_D_H Bit 1 (DTE)
<td> **Not available in TI HDSL Solution**
</tr>
<tr>
<td> EDGES
<td> **Not available in TI HDSL Solution in this release**<br/>
This will be available in future releases.
</tr>
<tr>
<td> VERSION<br/>
VERSION2
<td> **Different implementation from SICK HDSL MASTER IP Core**<br/>
"Major Release Number" field is 4 bits wide instead of 2 bits. "Coding" field is not available.
</tr>
<tr>
<td> RELEASE
<td> **Not available in TI HDSL Solution**
</tr>
<tr>
<td> MIR_SUM
<td> **Not available in TI HDSL Solution**<br/>
Please see SAFE_SUM (0x36) for getting summary information.
</tr>
<tr>
<td> PIPE_S<br/>
PIPE_D
<td> **Not available in TI HDSL Solution**
</tr>
<tr>
<td> PC_DATA
<td> **Not available in TI HDSL Solution**<br/>
Please see S_PC_DATA (0x37) for “short message” transactions.
</tr>
<tr>
<td> ACC_ERR_CNT
<td> **Different implementation from SICK HDSL MASTER IP Core**<br/>
- This register gives the count of transmitted fast position values with consecutive transmission errors.
- Writing to this register does not set any threshold for setting an error signal. ACC_ERR_CNT_TRESH (0x41) register allows triggering protocol reset if ACC_ERR_CNT crosses a threshold.
- This count is a 8 bit value.
</tr>
<tr>
<td> MAXACC<br/>
MAXDEV
<td> **Not available in TI HDSL Solution**
</tr>
<tr>
<td> ENC2_ID
<td> **Not available in TI HDSL Solution**
</tr>
<tr>
<td> EVENT_S Bit 7 (SINT)
<td> **Not available in TI HDSL Solution**
</tr>
<tr>
<td> POSTX<br/>
ONLINE_STATUS_D_L Bits 7:6 (POSTX) <br/>
ONLINE_STATUS_1_L Bits 7:6 (POSTX)<br/>
ONLINE_STATUS_2_L Bits 7:6 (POSTX)
<td> **Different implementation from SICK HDSL MASTER IP Core**<br/>
POSTX bits are available in a separate register POSTX register (0x4F) instead of ONLINE_STATUS_D_L, ONLINE_STATUS_1_L and ONLINE_STATUS_2_L registers.
</tr>
<tr>
<td> ONLINE_STATUS_D_H Bit 7 (INT) <br/>
ONLINE_STATUS_1_H Bit 7 (SINT)
<td> **Not available in TI HDSL Solution**
</tr>
<tr>
<td> ONLINE_STATUS_D_H Bit 6 (SUM)
<td> **Different implementation from SICK HDSL MASTER IP Core** <br/>
SAFE_SUM is used instead of MIR_SUM.
</tr>
<tr>
<td> VERSION2<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x44 instead of 0x0B
</tr>
<tr>
<td>
ENC2_ID<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x45 instead of 0x0F
</tr>
<tr>
<td>
STATUS2<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x46 instead of 0x18
</tr>
<tr>
<td>
VPOS24<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x47 instead of 0x19
</tr>
<tr>
<td>
VPOS23<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x48 instead of 0x1A
</tr>
<tr>
<td>
VPOS22<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x49 instead of 0x1B
</tr>
<tr>
<td>
VPOS21<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x4A instead of 0x1C
</tr>
<tr>
<td>
VPOS20<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x4B instead of 0x1D
</tr>
<tr>
<td>
VPOSCRC2_H<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x4C instead of 0x1E
</tr>
<tr>
<td>
VPOSCRC2_L<br/>
<td> **Register address is different from SICK HDSL MASTER IP Core** <br/>
TI implementation uses 0x4D instead of 0x1F
</tr>
</table>
6. Reset values of registers are not same as SICK HDSL MASTER IP Core.
7. As registers are implemented using Data Memory of Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS), the application has a read-write access for all registers.
8. When safe position is invalid (VPOS bit is set in EVENT_S), 0xFDFDFDFDFD value is not set in fast and safe position registers.

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# Position Sense {#POSITION_SENSE}
[TOC]
\cond SOC_AM64X || SOC_AM243X
Real-time communication with encoders and current sensing is typically handled by the Programmable Real-Time Unit Industrial Communication Subsystem (PRU-ICSS). The PRU-ICSS is a co-processor subsystem containing Programmable Real-Time (PRU) cores which implement the low level firmware. The PRU-ICSS frees up the main ARM cores in the device for other functions, such as control and data processing.
Applications and PRU-ICSS firmwares for following position sense encoders are provided in the SDK.
- \subpage ENDAT
- \subpage HDSL
- \subpage TAMAGAWA
\endcond
\cond SOC_AM263X
Application for following position sense encoder is provided in the SDK.
- \subpage TAMAGAWA_OVER_UART
\endcond

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# Tamagawa {#TAMAGAWA}
[TOC]
## Introduction
The Tamagawa receiver firmware running on PRU-ICSS provides a defined well interface to execute the Tamagawa protocol. The Tamagawa diagnostic application interacts with the Tamagawa receiver firmware interface.
\note
Tamagawa firmware and examples are based on EnDAT hardware interface from PRU-ICSSG.
## Features Supported
- Supports full-absolute SmartAbs & SmartInc encoders compatible with Smartceiver AU5561N1
- Channel selection
- Baud rate selection
- 2.5 Mbps and 5 Mbps encoder support
- Supports all Data Readout, Reset and EEPROM commands
## Features Not Supported
In general, peripherals or features not mentioned as part of "Features Supported" section are not supported, including the below
- Other baud rates.
## SysConfig Features
@VAR_SYSCFG_USAGE_NOTE
SysConfig can be used to configure things mentioned below:
- Selecting the ICSSG instance
- Selecting the PRUx slice (Tested on ICSSG0-PRU1)
- Configuring PINMUX, GPIO and ICSS clock to 200MHz
- Channel selection
- Baud rate selection
## Tamagawa Design
\subpage TAMAGAWA_DESIGN explains the design in detail.
## Example
- \ref EXAMPLE_MOTORCONTROL_TAMAGAWA

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# Tamagawa Protocol Design {#TAMAGAWA_DESIGN}
[TOC]
## Introduction
This document presents the firmware implementation details of the Tamagawa receiver protocol.
## Tamagawa encoder receiver
It is an encoder technology used for obtaining high-precision position information in machine tools, robotics, and so forth. Tamagawa rotary encoders consist broadly of two types: incremental or absolute. Incremental encoders provide a train of pulses, while the absolute-type provides digital values. The absolute encoder group contains the single-turn types that provide outputs which can be open collector or emitter follower. The absolute encoder types include the pure digital encoder types, which provide a digital word output through a line driver such as an RS485, or a semi-absolute encoder, which provides both digital word and pulse train outputs. Of the RS485 line-driver output absolute encoders that provide only digital output, another classification is the full absolute encoder. A full absolute encoder provides multi-turn digital data, which is known as SmartAbs, and is compatible with the Tamagawa Smartceiver AU5561N1. Another type of encoders, known as SmartInc, provide single-turn information in digital format with an RS485 line driver output. The AM64x/AM243x Tamagawa receiver implementation is equivalent to the Smartceiver AU5561N1, which can communicate with Tamagawa SmartAbs as well as SmartInc encoders.
The AM64x/AM243x Tamagawa receiver communicates with Tamagawa SmartAbs and SmartInc encoders and provides drive control with digital information to and from the encoder. Tamagawa communication is broadly classified into three types: data readout, reset, and EEPROM transactions. Four data readout transactions occur: absolute data in one revolution, multi-turn data, encoder ID, and a combination of all of these along with the encoder error status. The reset transaction always returns the absolute data in one revolution while performing different types of resets. Three types of reset are available: reset of absolute data in one revolution, reset of multi-turn data, and error reset. The EEPROM transaction allows the system to read and write to the EEPROM in the encoder. Each transaction has a unique data ID and consists of different fields, namely control, status, data, cyclic redundancy check (CRC), EEPROM address, and EEPROM data depending on the type of transaction, that is, data ID.
Each field is 10-bits long, beginning with a start bit and ending with a delimiter. The 8 bits between these start bits and delimiters depends on the field type. The control field contains the data ID information. Data, status, and CRC fields similarly contain data, status, and CRC in those 8 bits. The receiver initially sends the control field to start the communication. This action indicates the type of transaction to the encoder and the encoder returns this information based on the data ID, as the previous paragraph explains. The encoder always returns the control field back to the receiver. In the case of data readout and reset transactions, the encoder returns the control field followed by the status, data, and ending with the CRC field at the end. In the case of an EEPROM read or write, the receiver, in addition to the control field, sends the EEPROM address field (and EEPROM data field for write) followed by the CRC. The encoder returns the control field, followed by the EEPROM address, EEPROM data, and CRC fields. The physical layer communication is RS422/RS485 based.
## System Overview
### Sitara™ AM64x/AM243x Processor
Refer TRM for details
#### PRU-ICSS
Refer PRU-ICSS chapter of AM64x/AM243x Technical Reference Manual
## Software Description
At start-up, the application running on the ARM Cortex-R5 initializes the module clocks and configures the pinmux. The PRU is initialized and the PRU firmware is loaded on PRU slice of choice for a chosen ICSS instance (tested on PRU1 on ICSSG0). After the PRU1 starts executing, the Tamagawa interface is operational and the application can use it to communicate with an encoder. Use the Tamagawa diagnostic example to learn more about initialization and communication with the Tamagawa interface. This Tamagawa diagnostic example, also provides an easy way to validate the Tamagawa transactions. The diagnostic example provides menu options on the host PC in a serial terminal application, where the user can select the data ID code to be sent. Based on the data ID code, the application updates the Tamagwa interface with the data ID code and trigger transaction. The application then waits until it receives an indication of complete transaction by the firmware through the interface before displaying the result.
### PRU Firmware Design
The firmware first initializes the PRU hardware, after which it waits until a command has been triggered through the interface. Upon triggering, the transmit data is set up based on the data ID code and the data is transmitted. The data ID code then waits until receiving all the data that depends on the data ID. The parsing over the received data then commences, which is again based on the data ID, and the interface is updated with the result. The CRC verification occurs next and the interface indicates command completion. The firmware then waits for the next command trigger from the interface.
\image html Tamagawa_flowchart.JPG "Overview Flow Chart"
### Initialization
PRU is set to EnDat mode first. The entire EnDat configuration MMR’s are cleared(CFG registers). Tx global reinit bit in R31 is set to put all channels in default mode. The clock source is selected (ICSSG clock is selected with 200MHZ frequency). In Tx mode, the output data is read from the Tx FIFO at this 1x clock rate. In Rx mode, the input data is sampled at the Oversampling (OS) clock rate. Hence, Tx clock(1x clock) and Rx clock(Oversampling (OS) clock) are setup by selecting oversampling factor(x8). At the end of the initialization status is updated and wait until trigger from user occurs for tamagawa commands.
\image html Tamagawa_initialization_flow_chart.JPG "Initialization Flow Chart"
### Setup Transmit Data
The transmit and receive sizes are determined based on the data ID in the interface.
\image html Tamagawa_setup_tx_data.png "Setup Transmit Data Flow Chart"
### Transmit and Receive
In the current implementation, the Transmit data is loaded into the Tx FIFO byte wise. For data readout and reset commands, the requirement is to send 1 frame of 10 bits. So, 2 bytes of data is first loaded into the Tx FIFO and Tx frame size is set to 10 bits to send right data to Encoder. Similarly, for EEPROM Read command, the requirement is to send 3 frames of 10 bits each, so 30 bits in total. For this, 4 byes of data is first loaded into the Tx FIFO and then Tx frame size is set to 30 bits to send right data to Encoder. This is done by using the Tx - Single Shot mode.
\image html Tamagawa_tx_flow_chart.png "Transmit Flow Chart for data readout, reset and EEPROM Read commands"
In case of EEPROM Write command, the requirement is to send 4 frames of 10 bits each - 40 bits in total. For this, 4 bytes of data is first loaded into the Tx FIFO and then transmission is started in Tx - Continuous FIFO loading mode. FIFO byte level is constantly monitored and the FIFO is reloaded with the last byte when the FIFO level reaches 3 bytes.
\image html Tamagawa_eeprom_write_flow_chart.png "Transmit Flow Chart for EEPROM Write command"
Once the Transmission is complete, the encoder starts sending the data and the firmware copies the receive FIFO contents onto the receive buffer, individually, until all the data has been received.
\image html Tamagawa_rx_flow_chart.png "Receive Flow Chart"
### Receive Data Parse
Depending on the data ID used for initiating the transfer, the firmware parses the received data and copies it onto relevant fields in the interface, accordingly.
\image html Tamagawa_parse_data.png "Receive Data Parse Flow Chart"
### Verify CRC
The CRC is the last byte of the received data. The firmware then calculates the CRC of the received data excluding the last byte, compares it with the received CRC value, and updates the CRC status in the interface.
\image html Tamagawa_verify_crc.png "Verify CRC Flow Chart"

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# TAMAGAWA OVER UART {#TAMAGAWA_OVER_UART}
[TOC]
## Introduction
The Tamagawa over UART module provides a support for SoC UART instance to execute the Tamagawa protocol.
## Features Supported
- Single channel
- Baud rate selection
- 2.5 Mbps and 5 Mbps encoder support
- Supports all Data Readout, Reset and EEPROM commands
## Features Not Supported
- Other baud rates
- Long cable length
## SysConfig Features
@VAR_SYSCFG_USAGE_NOTE
SysConfig can be used to configure things mentioned below:
- Baud rate selection(2461538 bps for 2.5 Mbps encoder, 4923076 bps for 5Mbps encoder)
- Communication mode selection (Tested on polling mode)
- Configuring GPIO62 signal with J2 pin (RTSn pin for software based flow control)
- UART instance selection
## Example
- \ref EXAMPLE_MOTORCONTROL_TAMAGAWA_OVER_UART

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INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/position_sense.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/endat.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/endat_design.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/hdsl.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/hdsl_design.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/tamagawa.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/tamagawa_design.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/current_sense/current_sense.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/current_sense/sdfm_design.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/endat/include/endat_api.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/endat/include/endat_drv.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/hdsl/include/hdsl_drv.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/tamagawa/include/tamagawa_drv.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/current_sense/sdfm/include/sdfm_api.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/current_sense/sdfm/include/sdfm_drv.h

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INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/examples.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/hdsl_example.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/endat_example.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/tamagawa_example.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/sdfm_example.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/dcl/dcl_pi/dcl_pi.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/dcl/dcl_df22/dcl_df22.md

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# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
# double-quotes, unless you are using Doxywizard) that should identify the
# project for which the documentation is generated. This name is used in the
# title of most generated pages and in a few other places.
# The default value is: My Project.
PROJECT_NAME = "AM243x Motor Control SDK"
INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/main_page/main_page.md
INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/migration_guides/mcusdk_migration_guide.md
INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes.md
INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_00_00.md
@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/examples.cfg
@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/components.cfg
@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/dcl/dcl.cfg
# Used to selectively pick DEVICE specific sections within .md files
ENABLED_SECTIONS = SOC_AM243X
# SOC specific aliases
ALIASES+=VAR_SOC_NAME="AM243X"
ALIASES+=VAR_SOC_NAME_LOWER="am243x"
ALIASES+=VAR_BOARD_NAME="AM243X-EVM"
ALIASES+=VAR_BOARD_NAME_LOWER="am243x-evm"
ALIASES+=VAR_LP_BOARD_NAME="AM243X-LP"
ALIASES+=VAR_LP_BOARD_NAME_LOWER="am243x-lp"
ALIASES+=VAR_SOC_MANIFEST="motor_control_sdk_am243x_manifest.html"
ALIASES+=VAR_MCU_SDK_DOCS_PATH="../../mcu_plus_sdk/docs/api_guide_am243x"
ALIASES+=VAR_IC_SDK_DOCS_PATH="../../ind_comms_sdk/docs/api_guide_am243x"

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# Release Notes {#RELEASE_NOTES_PAGE}
[TOC]
Refer the below pages for release specific information
- \subpage RELEASE_NOTES_09_00_00_PAGE

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# Release Notes 09.00.00 {#RELEASE_NOTES_09_00_00_PAGE}
[TOC]
\attention Also refer to individual module pages for more details on each feature, unsupported features, important usage guidelines.
\attention For release notes of Industrial Communications SDK and MCU+ SDK, please refer to <a href="@VAR_IC_SDK_DOCS_PATH/RELEASE_NOTES_09_00_00_PAGE.html" target="_blank"> @VAR_SOC_NAME Industrial Communications SDK Release Notes 09.00.00</a> and <a href="@VAR_MCU_SDK_DOCS_PATH/RELEASE_NOTES_09_00_00_PAGE.html" target="_blank"> @VAR_SOC_NAME MCU+ SDK Release Notes 09.00.00</a> respectively.
\note The examples will show usage of SW modules and APIs on a specific CPU instance and OS combination. \n
Unless noted otherwise, the SW modules would work in both FreeRTOS and NORTOS environment. \n
Unless noted otherwise, the SW modules would work on any of the R5F's present on the SOC. \n
Unless noted otherwise, the SW modules would work on all supported EVMs \n
\note Tamagawa over SoC UART example is not supported for AM243x
## New in this Release
Feature | Module
------------------------------------------------------------------------------------------------|-----------------------------------
SYNC Mode Support with 2 channels | Position Sense HDSL
16 MHz EnDat clock frequency support | Position Sense EnDat
Long cable support | Position Sense EnDat
Trigger based normal current sampling | Current Sense %SDFM
Double sampling per PWM cycle | Current Sense %SDFM
Digital Control Library | Real Time Libraries
## Device and Validation Information
SOC | Supported CPUs | Boards | Host PC
-------|-----------------|-------------------------------------------------------------------------------------------------------------|-----------------------------------
AM243x | R5F | AM243x GP EVM (referred to as am243x-evm in code), \n AM243x LAUNCHPAD (referred to as am243x-lp in code) | Windows 10 64b or Ubuntu 18.04 64b
## Tools, Compiler and Other Open Source SW Module Information
Tools / SW module | Supported CPUs | Version
------------------------|----------------|-----------------------
Code Composer Studio | R5F, M4F, A53 | @VAR_CCS_VERSION
SysConfig | R5F, M4F, A53 | @VAR_SYSCFG_VERSION, build @VAR_SYSCFG_BUILD
TI ARM CLANG | R5F, M4F | @VAR_TI_ARM_CLANG_VERSION
FreeRTOS Kernel | R5F, M4F, A53 | @VAR_FREERTOS_KERNEL_VERSION
FreeRTOS SMP Kernel | A53 | @VAR_FREERTOS_SMP_KERNEL_VERSION
## Key Features
<!-- ### Experimental Features
\attention Features listed below are early versions and should be considered as "experimental".
\attention Users can evaluate the feature, however the feature is not fully tested at TI side.
\attention TI would not support these feature on public e2e.
\attention Experimental features will be enabled with limited examples and SW modules.
Feature | Module
--------------------------------------------------------------------|--------------------------
| -->
<!-- ### Features not supported in release -->
<!-- ### AM243X LAUNCHPAD not tested/not supported features
Below features are not support on AM243X LAUNCHPAD due to SOC or board constraints, -->
### Position Sense
Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested
-------------|----------------|-------------------|-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------
EnDat | R5F | YES | FreeRTOS, NORTOS | Single channel, Multi channel, Continuous mode for single channel, Load share mode, Recovery Time for 2.2 command set, Boosterpack with AM243x-LP | Encoder receive communication command
HDSL | R5F | YES | FreeRTOS, NORTOS | Freerun mode(300MHz,225MHz), Sync mode(225MHz), Short Message Read & Write, Long Message Read & Write, Boosterpack with AM243x-LP | Long cables
Tamagawa | R5F | YES | FreeRTOS, NORTOS | Absolute position, Encoder ID, Reset, EEPROM Read, EEPROM Write, 2.5 Mbps and 5 Mbps Encoder Support, Boosterpack with AM243x-LP | -
### Current Sense
Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested
-------------|----------------|-------------------|-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------
%SDFM | R5F | YES | FreeRTOS, NORTOS | 3 %SDFM channels on single PRU core, %SDFM Sync with EPWM, Overcurrent, single normal current sampling per PWM cycle, Double normal current sampling per PWM cycle, High and Low threshold comparator, Tested with SDFM clock from ECAP, Tested with 5MHz Clock from EPWM | -
## Fixed Issues
<table>
<tr>
<th> ID
<th> Head Line
<th> Module
<th> Applicable Releases
<th> Resolution/Comments
</tr>
<tr>
<td> PINDSW-5538
<td> HDSL: Long message not working with multi-channel application
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-5651
<td> HDSL: Multi-turn bits of fast position do not contain correct data
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-5681
<td> EnDat: Recovery Time not correct for 2.1 commands
<td> Position Sense EnDat
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-5689
<td> HDSL: High deviation in fast position when encoder shaft is fixed
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-6487
<td> HDSL: FIX bits in ONLINE STATUS 1 register are losing the expected fix value
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-6488
<td> HDSL: SUM/SSUM bit not working in ONLINE STATUS registers
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-6489
<td> HDSL: Offsets for ONLINE STATUS registers in C structure are not correct
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-6492
<td> HDSL: Protocol reset is not working
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-6526
<td> HDSL: FREL/FRES bits in EVENT/EVENT_S registers are not sticky
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-6530
<td> HDSL: QMLW bit not working in ONLINE STATUS registers
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-6607
<td> %SDFM: NULL pointer dereferenced in \ref SDFM_getFilterData
<td> Current Sense %SDFM
<td> -
<td> -
</tr>
</table>
## Known Issues
<table>
<tr>
<th> ID
<th> Head Line
<th> Module
<th> Applicable Releases
<th> Workaround
</tr>
<tr>
<td> PINDSW-5537
<td> HDSL not working with 225 MHz PRU-ICSSG Core Clock Frequency
<td> Position Sense HDSL
<td> 9.0 onwards
<td> Use 300 MHz frequency for PRU-ICSSG Core Clock
</tr>
<tr>
<td> PINDSW-5690
<td> HDSL: EDGE register is not updated
<td> Position Sense HDSL
<td> 9.0 onwards
<td> -
</tr>
<tr>
<td> PINDSW-6486
<td> HDSL: RSSI register shows higher values than expected for a non-noisy setup
<td> Position Sense HDSL
<td> 9.0 onwards
<td> -
</tr>
<tr>
<td> PINDSW-6544
<td> %SDFM: Incorrect samples seen intermittently with EPWM as %SDFM clock
<td> Current Sense %SDFM
<td> 9.0 onwards
<td> Use 5MHz %SDFM clock from EPWM1 (tested with 5MHz clock from EPWM) or use PRU-ICSSG ECAP as %SDFM clock source
</tr>
<tr>
<td> PINDSW-6628
<td> HDSL: Reset value of PRST bit is not correct
<td> Position Sense HDSL
<td> 9.0 onwards
<td> -
</tr>
<tr>
<td> PINDSW-6629
<td> HDSL: SSUM bit in EVENT_S is not set when SUMMARY is non-zero
<td> Position Sense HDSL
<td> 9.0 onwards
<td> -
</tr>
<tr>
<td> PINDSW-6630
<td> HDSL: POS bit is not set during initial fast position alignment
<td> Position Sense HDSL
<td> 9.0 onwards
<td> -
</tr>
<tr>
<td> PINDSW-6931
<td> Tamagawa: Firmware build failing
<td> Position Sense Tamagawa
<td> 9.0 onwards
<td>1. Update include path of icss_regs.inc and icss_cfg_regs.inc files to `../../../../mcu_plus_sdk/source/pru_io/firmware/common/ ` path in `tamagawa_main.asm` and `tamagawa_icss_reg_defs.h` files.<br>2. Replace ED with ENDAT in symbol definitions in tamagawa_main.asm file's lines 101 to 122. (For example, update `ICSS_CFG_PRU0_ED_CH0_CFG1` to `ICSS_CFG_PRU0_ENDAT_CH0_CFG1` )</td>
</tr>
</table>
<!-- ## Errata
<table>
<tr>
<th> ID
<th> Head Line
<th> Module
<th> SDK Status
</tr>
<tr>
<td> i2311
<td> USART: Spurious DMA Interrupts
<td> UART
<td> Implemented
</tr>
<tr>
<td> i2313
<td> GPMC: Sub-32-bit read issue with NAND and FPGA/FIFO
<td> GPMC
<td> Implemented
</tr>
<tr>
<td> i2331
<td> CPSW: Device lockup when reading CPSW registers
<td> CPSW, SBL
<td> Implemented
</tr>
<tr>
<td> i2345
<td> CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks
<td> CPSW
<td> Implemented
</tr>
<tr>
<td> i2326
<td> PCIe: MAIN_PLLx operating in fractional mode, which is required for enabling SSC, is not compliant with PCIe Refclk jitter limits
<td> PCIe
<td> Open
</tr>
<tr>
<td> i2312
<td> MMCSD: HS200 and SDR104 Command Timeout Window Too Small
<td> MMCSD
<td> Open
</tr>
<tr>
<td> i2310
<td> USART: Erroneous clear/trigger of timeout interrupt
<td> UART
<td> Open
</tr>
<tr>
<td> i2279
<td> MCAN: Specification Update for dedicated Tx Buffers and Tx Queues configured with same Message ID
<td> MCAN
<td> Open
</tr>
<tr>
<td> i2278
<td> MCAN: Message Transmit order not guaranteed from dedicated Tx Buffers configured with same Message ID
<td> MCAN
<td> Open
</tr>
</table> -->
## Limitations
<table>
<tr>
<th> ID
<th> Head Line
<th> Module
<th> Reported in Release
<th> Applicable Devices
<th> Workaround
</tr>
<tr>
<td> MCUSDK-208
<td> gmake with -j can sometimes lock up Windows command prompt
<td> Build
<td> 7.3.0
<td> AM64x, AM243x
<td> Use bash for windows as part of git for windows or don't use -j option
</tr>
</table>
## Upgrade and Compatibility Information {#UPGRADE_AND_COMPATIBILITY_INFORMATION_9_0_0}
<!-- \attention When migrating from MCU+ SDK, see \ref MIGRATION_GUIDES for more details -->
This section lists changes which could affect user applications developed using older SDK versions.
Read this carefully to see if you need to do any changes in your existing application when migrating to this SDK version relative to
previous SDK version. Also refer to older SDK version release notes to see changes in
earlier SDKs.
<!-- ### Compiler Options
<table>
<tr>
<th> Module
<th> Affected API
<th> Change
<th> Additional Remarks
</tr>
<tr>
<td>
<td>
<td>
<td>
</tr>
</table> -->
### Examples
<table>
<tr>
<th> Module
<th> Affected API
<th> Change
<th> Additional Remarks
</tr>
<tr>
<td> Current Sense %SDFM
<td> Structure `SdfmPrms_s`
<td> Added variables `iep_clock`, `sd_clock`, `en_second_update`, `firstSampTrigTime` and `secondSampTrigTime`
<td>
</tr>
</table>
### Drivers
<table>
<tr>
<th> Module
<th> Affected API
<th> Change
<th> Additional Remarks
</tr>
<tr>
<td> Position Sense EnDat
<td> \ref endat_init
<td> Added API parameter `pruss_iep`
<td> Needed for periodic mode
</tr>
<tr>
<td> Position Sense EnDat
<td> Structure \ref endat_priv
<td> Added variables `pruss_iep`, `cmp3`, `cmp5` and `cmp6`
<td> Needed for periodic mode
</tr>
<tr>
<td> Position Sense EnDat
<td> Structure \ref cmd_supplement
<td> Added variables `cmp3`, `cmp5` and `cmp6`
<td> Needed for periodic mode
</tr>
<tr>
<td> Current Sense %SDFM
<td> `SDFM_setSampleReadingTime`
<td> Changed name of API \ref SDFM_setSampleTriggerTime and updated a parameter name `samp_trig_time`
<td> -
</tr>
<tr>
<td> Current Sense %SDFM
<td> \ref SDFM_setFilterOverSamplingRatio
<td> Removed `oc_osr` parameter
<td> -
</tr>
<tr>
<td> Current Sense %SDFM
<td> \ref SDFM_setCompFilterOverSamplingRatio
<td> Changed type of osr parameter
<td> uint8_t to uint16_t
</tr>
<tr>
<td> Current Sense %SDFM
<td> `SDFM_setAccOverSamplingRatio`
<td> Removed this API
<td> -
</tr>
<tr>
<td> Current Sense %SDFM
<td> Structure \ref SDFM_Ctrl
<td> Removed variables: `ctrl` and `stat`, and added variables `sdfm_en`, `sdfm_en_ack` and `sdfm_pru_id`
<td> -
</tr>
<tr>
<td> Current Sense %SDFM
<td> Structure \ref SDFM_CfgTrigger
<td> Removed variables `trig_samp_time`, `oc_prd_iep_cnt` and `sample_count`, and added variables `en_double_nc_sampling`, `first_samp_trig_time` and `second_samp_trig_time`
<td> -
</tr>
</table>

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@ -0,0 +1,4 @@
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/position_sense.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/tamagawa_uart.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/tamagawa_over_soc_uart/include/tamagawa_soc_uart_interface.h

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@ -0,0 +1,4 @@
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/examples.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/tamagawa_uart_example.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/dcl/dcl_pi/dcl_pi.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/dcl/dcl_df22/dcl_df22.md

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# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
# double-quotes, unless you are using Doxywizard) that should identify the
# project for which the documentation is generated. This name is used in the
# title of most generated pages and in a few other places.
# The default value is: My Project.
PROJECT_NAME = "AM263x Motor Control SDK"
INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/main_page/main_page.md
INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/migration_guides/mcusdk_migration_guide.md
INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes.md
INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_00_00.md
@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/examples.cfg
@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/components.cfg
@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/dcl/dcl.cfg
# Used to selectively pick DEVICE specific sections within .md files
ENABLED_SECTIONS = SOC_AM263X
# SOC specific aliases
ALIASES+=VAR_SOC_NAME="AM263X"
ALIASES+=VAR_SOC_NAME_LOWER="am263x"
ALIASES+=VAR_BOARD_NAME="AM263X-CC"
ALIASES+=VAR_BOARD_NAME_LOWER="am263x-cc"
ALIASES+=VAR_LP_BOARD_NAME="AM263X-LP"
ALIASES+=VAR_LP_BOARD_NAME_LOWER="am263x-lp"
ALIASES+=VAR_SOC_MANIFEST="motor_control_sdk_am263x_manifest.html"
ALIASES+=VAR_MCU_SDK_DOCS_PATH="../../mcu_plus_sdk/docs/api_guide_am263x"
ALIASES+=VAR_IC_SDK_DOCS_PATH="../../ind_comms_sdk/docs/api_guide_am263x"

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# Release Notes {#RELEASE_NOTES_PAGE}
[TOC]
Refer the below pages for release specific information
- \subpage RELEASE_NOTES_09_00_00_PAGE

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# Release Notes 09.00.00 {#RELEASE_NOTES_09_00_00_PAGE}
[TOC]
\attention Also refer to individual module pages for more details on each feature, unsupported features, important usage guidelines.
\attention For release notes of Industrial Communications SDK and MCU+ SDK, please refer to <a href="@VAR_IC_SDK_DOCS_PATH/RELEASE_NOTES_09_00_00_PAGE.html" target="_blank"> @VAR_SOC_NAME Industrial Communications SDK Release Notes 09.00.00</a> and <a href="@VAR_MCU_SDK_DOCS_PATH/RELEASE_NOTES_09_00_00_PAGE.html" target="_blank"> @VAR_SOC_NAME MCU+ SDK Release Notes 09.00.00</a> respectively.
\note The examples will show usage of SW modules and APIs on a specific CPU instance and OS combination. \n
Unless noted otherwise, the SW modules would work in both FreeRTOS and NORTOS environment. \n
Unless noted otherwise, the SW modules would work on any of the R5F's present on the SOC. \n
Unless noted otherwise, the SW modules would work on all supported EVMs \n
## New in this Release
Feature | Module
------------------------------------------------------------------------------------------------|-----------------------------------
Digital Control Library | Real Time Libraries
## Device and Validation Information
SOC | Supported CPUs | EVM | Host PC
------|-----------------|------------------------------------------------------------------------------|-----------------------------------------
AM263x| R5F | AM263x ControlCard Revision E1 (referred to as am263x-cc in code). \n | Windows 10 64b or Ubuntu 18.04 64b
AM263x| R5F | AM263x LaunchPad Revision E2 (referred to as am263x-lp in code) | Windows 10 64b or Ubuntu 18.04 64b
## Tools, Compiler and Other Open Source SW Module Information
Tools | Supported CPUs | Version
------------------------|----------------|--------------------------------------------------------------
Code Composer Studio | R5F | @VAR_CCS_VERSION_AM263X
SysConfig | R5F | @VAR_SYSCFG_VERSION_AM263X, build @VAR_SYSCFG_BUILD_AM263X
TI ARM CLANG | R5F | @VAR_TI_ARM_CLANG_VERSION
FreeRTOS Kernel | R5F | @VAR_FREERTOS_KERNEL_VERSION
## Key Features
### Position Sense
Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested
-------------|----------------|-------------------|-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------
Tamagawa | R5F | YES | FreeRTOS | Absolute position, Encoder ID, Reset, EEPROM Read, EEPROM Write, 2.5 Mbps and 5 Mbps Encoder Support | -
<!-- ## Fixed Issues
<table>
<tr>
<th> ID
<th> Head Line
<th> Module
<th> Applicable Releases
<th> Resolution/Comments
</tr>
</table> -->
<!-- ## Known Issues
<table>
<tr>
<th> ID
<th> Head Line
<th> Module
<th> Applicable Releases
<th> Workaround
</tr>
</table> -->
<!-- ## Errata
<table>
<tr>
<th> ID
<th> Head Line
<th> Module
<th> SDK Status
</tr>
<tr>
<td> i2311
<td> USART: Spurious DMA Interrupts
<td> UART
<td> Implemented
</tr>
<tr>
<td> i2313
<td> GPMC: Sub-32-bit read issue with NAND and FPGA/FIFO
<td> GPMC
<td> Implemented
</tr>
<tr>
<td> i2331
<td> CPSW: Device lockup when reading CPSW registers
<td> CPSW, SBL
<td> Implemented
</tr>
<tr>
<td> i2345
<td> CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks
<td> CPSW
<td> Implemented
</tr>
<tr>
<td> i2326
<td> PCIe: MAIN_PLLx operating in fractional mode, which is required for enabling SSC, is not compliant with PCIe Refclk jitter limits
<td> PCIe
<td> Open
</tr>
<tr>
<td> i2312
<td> MMCSD: HS200 and SDR104 Command Timeout Window Too Small
<td> MMCSD
<td> Open
</tr>
<tr>
<td> i2310
<td> USART: Erroneous clear/trigger of timeout interrupt
<td> UART
<td> Open
</tr>
<tr>
<td> i2279
<td> MCAN: Specification Update for dedicated Tx Buffers and Tx Queues configured with same Message ID
<td> MCAN
<td> Open
</tr>
<tr>
<td> i2278
<td> MCAN: Message Transmit order not guaranteed from dedicated Tx Buffers configured with same Message ID
<td> MCAN
<td> Open
</tr>
</table> -->
## Limitations
<table>
<tr>
<th> ID
<th> Head Line
<th> Module
<th> Reported in Release
<th> Applicable Devices
<th> Workaround
</tr>
<tr>
<td> MCUSDK-208
<td> gmake with -j can sometimes lock up Windows command prompt
<td> Build
<td> 7.3.0
<td> AM64x, AM243x
<td> Use bash for windows as part of git for windows or don't use -j option
</tr>
</table>
<!-- ## Upgrade and Compatibility Information {#UPGRADE_AND_COMPATIBILITY_INFORMATION_9_0_0} -->
<!-- \attention When migrating from MCU+ SDK, see \ref MIGRATION_GUIDES for more details -->
<!-- This section lists changes which could affect user applications developed using older SDK versions.
Read this carefully to see if you need to do any changes in your existing application when migrating to this SDK version relative to
previous SDK version. Also refer to older SDK version release notes to see changes in
earlier SDKs. -->
<!-- ### Compiler Options
<table>
<tr>
<th> Module
<th> Affected API
<th> Change
<th> Additional Remarks
</tr>
<tr>
<td>
<td>
<td>
<td>
</tr>
</table> -->
<!-- ### Examples
<table>
<tr>
<th> Module
<th> Affected API
<th> Change
<th> Additional Remarks
</tr>
</table>
### Drivers
<table>
<tr>
<th> Module
<th> Affected API
<th> Change
<th> Additional Remarks
</tr>
</table> -->

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INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/position_sense.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/endat.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/endat_design.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/hdsl.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/hdsl_design.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/tamagawa.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/tamagawa_design.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/current_sense/current_sense.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/current_sense/sdfm_design.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/endat/include/endat_api.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/endat/include/endat_drv.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/hdsl/include/hdsl_drv.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/tamagawa/include/tamagawa_drv.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/current_sense/sdfm/include/sdfm_api.h
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/current_sense/sdfm/include/sdfm_drv.h

5
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@ -0,0 +1,5 @@
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/examples.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/hdsl_example.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/endat_example.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/tamagawa_example.md
INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/examples/sdfm_example.md

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@ -0,0 +1,26 @@
# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
# double-quotes, unless you are using Doxywizard) that should identify the
# project for which the documentation is generated. This name is used in the
# title of most generated pages and in a few other places.
# The default value is: My Project.
PROJECT_NAME = "AM64x Motor Control SDK"
INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/main_page/main_page.md
@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/examples.cfg
@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/components.cfg
# Used to selectively pick DEVICE specific sections within .md files
ENABLED_SECTIONS = SOC_AM64X
# SOC specific aliases
ALIASES+=VAR_SOC_NAME="AM64X"
ALIASES+=VAR_SOC_NAME_LOWER="am64x"
ALIASES+=VAR_BOARD_NAME="AM64X-EVM"
ALIASES+=VAR_BOARD_NAME_LOWER="am64x-evm"
ALIASES+=VAR_SK_BOARD_NAME="AM64X-SK"
ALIASES+=VAR_SK_BOARD_NAME_LOWER="am64x-sk"
ALIASES+=VAR_SOC_MANIFEST="motor_control_sdk_am64x_manifest.html"
ALIASES+=VAR_MCU_SDK_DOCS_PATH="../../mcu_plus_sdk/docs/api_guide_am64x"
ALIASES+=VAR_IC_SDK_DOCS_PATH="../../ind_comms_sdk/docs/api_guide_am64x"

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# DCL DF22 Test {#EXAMPLES_DCL_DF22}
[TOC]
Simple DCL DF22 controller demonstration
This example leverages a direct form 2 2nd order (DF22) compensator from
the digital control library (DCL).
It demonstrates how to setup and run the DF22 controller. The example first
initializes the datalog DCL_FDLOG to the test vector, run the controller
based on the test input and compare the output with the expected value.
## Files and directory structure
<table>
<tr>
<th>Folder/Files
<th>Description
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/examples/dcl/dcl_df22/</td></tr>
<tr>
<td>df22_test.c</td>
<td>Main function for DF22 testing</td>
</tr>
<tr>
<td>df22_test.h</td>
<td>Contains all initialization of needed strctures</td>
</tr>
<tr>
<td>data/</td>
<td>Contains pre-generated data files result compares with</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/source/dcl</td></tr>
<tr>
<td>dcl/</td>
<td>Folder containing DCL library source</td>
</tr>
</table>
# Supported Combinations {#EXAMPLES_DCL_DF22_COMBO}
\cond SOC_AM243X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 nortos
^ | r5fss0-0 freertos
Toolchain | ti-arm-clang
Boards | @VAR_BOARD_NAME_LOWER, @VAR_LP_BOARD_NAME_LOWER
Example folder | examples/dcl/dcl_df22
\endcond
\cond SOC_AM263X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 nortos
^ | r5fss0-0 freertos
Toolchain | ti-arm-clang
Boards | @VAR_BOARD_NAME_LOWER, @VAR_LP_BOARD_NAME_LOWER
Example folder | examples/dcl/dcl_df22
\endcond
# Steps to Run the Example
- **When using CCS projects to build**, import the CCS project for the required combination and build it using the CCS project menu (see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_PROJECTS_PAGE.html" target="_blank"> Using SDK with CCS Projects </a>).
- **When using makefiles to build**, note the required combination and build using make command (see <a href="@VAR_MCU_SDK_DOCS_PATH/MAKEFILE_BUILD_PAGE.html" target="_blank"> Using SDK with Makefiles </a>).
- Launch a CCS debug session and run the executable, see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_LAUNCH_PAGE.html" target="_blank"> CCS Launch, Load and Run </a>
### Sample Output
Shown below is a sample output when the application is run:
\code
DF22 test produced 0 error
\endcode

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# DCL PI Test {#EXAMPLES_DCL_PI}
[TOC]
Simple DCL PI controller demonstration
This example leverages a PI controller from the digital control library(DCL).
It demonstrates how to setup and run the PI controller. The example first
initializes the datalog DCL_FDLOG to the test vector, run the controller
based on the test input and compare the output with the expected value.
## Files and directory structure
<table>
<tr>
<th>Folder/Files
<th>Description
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/examples/dcl/dcl_pi/</td></tr>
<tr>
<td>pi_test.c</td>
<td>Main function for PI testing</td>
</tr>
<tr>
<td>pi_test.h</td>
<td>Contains all initialization of needed strctures</td>
</tr>
<tr>
<td>data/</td>
<td>Contains pre-generated data files result compares with</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/source/dcl</td></tr>
<tr>
<td>dcl/</td>
<td>Folder containing DCL library source</td>
</tr>
</table>
# Supported Combinations {#EXAMPLES_DCL_PI_COMBOS}
\cond SOC_AM243X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 nortos
^ | r5fss0-0 freertos
Toolchain | ti-arm-clang
Boards | @VAR_BOARD_NAME_LOWER, @VAR_LP_BOARD_NAME_LOWER
Example folder | examples/dcl/dcl_pi
\endcond
\cond SOC_AM263X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 nortos
^ | r5fss0-0 freertos
Toolchain | ti-arm-clang
Boards | @VAR_BOARD_NAME_LOWER, @VAR_LP_BOARD_NAME_LOWER
Example folder | examples/dcl/dcl_pi
\endcond
# Steps to Run the Example
- **When using CCS projects to build**, import the CCS project for the required combination and build it using the CCS project menu (see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_PROJECTS_PAGE.html" target="_blank"> Using SDK with CCS Projects </a>).
- **When using makefiles to build**, note the required combination and build using make command (see <a href="@VAR_MCU_SDK_DOCS_PATH/MAKEFILE_BUILD_PAGE.html" target="_blank"> Using SDK with Makefiles </a>).
- Launch a CCS debug session and run the executable, see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_LAUNCH_PAGE.html" target="_blank"> CCS Launch, Load and Run </a>
### Sample Output
Shown below is a sample output when the application is run:
\code
PI test produced 0 error
\endcode

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# EnDAT Diagnostic {#EXAMPLE_MOTORCONTROL_ENDAT}
[TOC]
The EnDat diagnostic application, described here,
demonstrates the EnDat receiver operation.
The EnDat driver provides a well defined set of APIs to expose EnDat
receiver interface.
The diagnostic invokes these APIs to
- initialize EnDat,
- select one configuration among concurrent multi channel with Encoders of Same make, multi channel with Encoders of Different Make and single channel configuration based on SysConfig.
- select the channel (channels in the case of concurrent multi channel with encoders of same make or multi channel with Encoders of Different Make),
- configure the host trigger mode,
- and run the firmware.
- If using "Multi Channel with Encoders of Different Make" configuration is selected" :
- enable load share mode.
- select primary core for global configuration.
- configuration of synchronization bits.
Once these steps are executed,
- the driver waits for the EnDat to be initialized.
- It then sets clock frequency to 200KHz (as propagation delay is not yet compensated)
- and obtains the encoder details including serial number, position resolution etc, and displays on the console/UART.
- Based on the whether encoder is 2.2 or 2.1 type, it sets clock to either 8MHz or 1MHz respectively.
- While configuring clock, propagation delay is taken care using the automatically estimated propagation delay (user can override it too).
- In the case of concurrent Multi Channel with Encoders of Same Make or Multi Channel with Encoders of Different Make, if propagation delay between various channels are different, that too is automatically taken care.
Once initial setup is over,
- the diagnostic provides the user with a self explanatory menu.
- Two types of menu options are presented. One type (1-14) will send an EnDat command as per EnDat 2.2 specification.
- The other type (100-108) allows the user to configure clock frequency, various timing parameters, simulate motor control loop using 2.1 command as well as 2.2 command with safety (redundant position information), switch to continuous clock mode and monitor raw data.
- Concurrent multi channel with Encoder of Same Make configuration can work simultaneously for up-to three encoders with identical part number, all variants of 2.2 position commands as well as the 2.1 position command is supported and an additional option (109) to configure wire delay (useful when propagation delay in each channel is different) is available.
- Single PRU core handles enabled channels in single channel and Multi Channel with Encoders of Same Make configuration.
- Application by default, handles wire delay as required, the menu option provides a way to override it.
After the user selects an EnDat command,
- the diagnostic asks for more details to frame the command and performs a basic sanity check on the user entered values.
- Then the EnDat APIs are invoked to process the command set, set the host trigger bit and waiting until the host trigger bit cleared, If multi-channel with Encoders of Different make is used, these operations are done for each channel".
- The received EnDat is processed & validated using the defined APIs. The result is then presented to the user.
### Channel Selection In Sysconfig
\image html EnDat_channel_selection_In_sysconfig.PNG "Channel Selection In Sysconfig"
\image html Endat_channel_selection_configuration.png "EnDAT configuration seletion between Single/Multi channel "
### Endat Example Implementation
Following section describes the Example implementation of EnDat on ARM(R5F).
\image html Endat_Example_Implementation.png "Endat Example"
## Important files and directory structure
<table>
<tr>
<th>Folder/Files
<th>Description
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/examples/position_sense/endat_diagnostic</td></tr>
<tr>
<td>endat_diagnostic.c</td>
<td>EnDAT diagnostic application</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/source/position_sense/endat</td></tr>
<tr>
<td>firmware/</td>
<td>Folder containing EnDAT firmware sources.</td>
</tr>
<tr>
<td>driver/</td>
<td>EnDAT diagnostic driver.</td>
</tr>
</table>
# Supported Combinations {#EXAMPLES_MOTORCONTROL_ENDAT_COMBOS}
\cond SOC_AM64X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 freertos
ICSSG | ICSSG0
PRU | PRU1, TXPRU1 and RTUPRU1
Toolchain | ti-arm-clang
Board | @VAR_BOARD_NAME_LOWER
Example folder | examples/position_sense/endat_diagnostic
\endcond
\cond SOC_AM243X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 freertos
ICSSG | ICSSG0
PRU | PRU1, TXPRU1 and RTUPRU1
Toolchain | ti-arm-clang
Board | @VAR_BOARD_NAME_LOWER, @VAR_LP_BOARD_NAME_LOWER
Example folder | examples/position_sense/endat_diagnostic
\endcond
# Steps to Run the Example
## Hardware Prerequisites
Other than the basic EVM setup mentioned in <a href="@VAR_MCU_SDK_DOCS_PATH/EVM_SETUP_PAGE.html" target="_blank"> EVM Setup </a>, below additional HW is required to run this demo
- EnDAT encoder
- <a href="http://www.ti.com/tool/TIDA-00179" target="_blank"> TIDA-00179 Universal Digital Interface to Absolute Position Encoders </a>
- TIDEP-01015 3 Axis board
- Interface card connecting EVM and TIDEP-01015 3 Axis board
\cond SOC_AM243X
### Hardware Prerequisities for Booster Pack
- EnDat encoder
- AM243x-LP board
- <a href="https://www.ti.com/tool/BP-AM2BLDCSERVO" target="_blank"> BP-AM2BLDCSERVO </a>
\endcond
## Hardware Setup
\imageStyle{EnDAT_Connections.png,width:40%}
\image html EnDAT_Connections.png "Hardware Setup"
\cond SOC_AM243X
## Hardware Setup(Using Booster Pack & AM243x-LP)
\imageStyle{EnDat_Booster_Pack.png,width:40%}
\image html EnDat_Booster_Pack.png "Hardware Setup of Booster Pack + LP for EnDat"
#### Booster Pack Jumper Configuration
<table>
<tr>
<th>Designator</th>
<th>ON/OFF</th>
<th>Description</th>
</tr>
<tr>
<td>J11</td>
<td>OFF</td>
<td>VSENSE/ISENSE select</td>
</tr>
<tr>
<td>J13</td>
<td>OFF</td>
<td>VSENSE/ISENSE select</td>
</tr>
<tr>
<td>J17</td>
<td>Pin 1-2 Connected</td>
<td>%SDFM Clock Feedback Select</td>
</tr>
<tr>
<td>J18/J19</td>
<td>J18 OFF & J19 ON</td>
<td>Axis 1: Encoder/Resolver Voltage Select</td>
</tr>
<tr>
<td>J20/J21</td>
<td>J20 ON & J21 OFF</td>
<td>Axis 2: Encoder/Resolver Voltage Select</td>
</tr>
<tr>
<td>J22</td>
<td>OFF</td>
<td>Axis 1: Manchester Encoding Select</td>
</tr>
<tr>
<td>J23</td>
<td>OFF</td>
<td>Axis 2: Manchester Encoding Select</td>
</tr>
<tr>
<td>J24</td>
<td>OFF</td>
<td>Axis 1: RS485/DSL MUX</td>
</tr>
<tr>
<td>J25</td>
<td>OFF</td>
<td>Axis 2: RS485/DSL MUX</td>
</tr>
<tr>
<td>J26</td>
<td>OFF</td>
<td>VSENSE/ISENSE Select</td>
</tr>
<tr>
<td>J27</td>
<td>ON</td>
<td>3WIRE/%SDFM MUX</td>
</tr>
<tr>
<td>J28</td>
<td>OFF</td>
<td>3WIRE MUX</td>
</tr>
</table>
\endcond
## Build, load and run
- **When using CCS projects to build**, import the CCS project and build it using the CCS project menu (see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_PROJECTS_PAGE.html" target="_blank"> Using SDK with CCS Projects </a>).
- **When using makefiles to build**, note the required combination and build using
make command (see <a href="@VAR_MCU_SDK_DOCS_PATH/MAKEFILE_BUILD_PAGE.html" target="_blank"> Using SDK with Makefiles </a>)
- Launch a CCS debug session and run the executable, see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_LAUNCH_PAGE.html" target="_blank"> CCS Launch, Load and Run </a>
- Refer to UART terminal for user interface menu options.
### Sample Output
Shown below is a sample output when the application is run:
\imageStyle{EnDAT_Initialization_UART_PRINT.png,width:60%}
\image html EnDAT_Initialization_UART_PRINT.png "EnDAT Usage"
### Test Case Description
<table>
<tr>
<th style="width:4%">S.No</th>
<th>Test detail
<th>Steps
<th>Pass/fail crieteria
</tr>
<tr>
<td style="text-align: center">1.</td>
<td style="text-align: center">To check position value</td>
<td>1. Enter 1 to select "Encoder send position values"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="4" style="text-align: center">2.</td>
<td rowspan="4" style="text-align: center">To receive encoder's operating parameters (Error Message)</td>
<td>1. Enter 2 to select "Selection of memory area"</td>
<td></td>
</tr>
<tr>
<td>2. Enter "B9" in MRS code to select "Operating parameters"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 4 to select "Encoder to send parameter"</td>
<td></td>
</tr>
<tr>
<td>4. Enter 00 in "parameter address" for selecting "Error message"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="4" style="text-align: center">3.</td>
<td rowspan="4" style="text-align: center">To receive encoder's operating parameters (Warning message)</td>
<td>1. Enter 2 to select "Selection of memory area"</td>
<td></td>
</tr>
<tr>
<td>2. Enter "B9" in MRS code to select "Operating parameters"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 4 to select "Encoder to send parameter"</td>
<td></td>
</tr>
<tr>
<td>4. Enter 01 in "parameter address" for selecting "Error message"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="4" style="text-align: center">4.</td>
<td rowspan="4" style="text-align: center">To receive encoder's manufacture parameters for Endat 2.2</td>
<td>1. Enter 2 to select "Selection of memory area"</td>
<td></td>
</tr>
<tr>
<td>2. Enter "BD" in MRS code to select "Parameters of encoder manufacturer for Endat 2.2"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 4 to select "Encoder to send parameter"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>4. Enter 0 in "parameter address" for selecting "Status of additional info 1"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="5" style="text-align: center">5.</td>
<td rowspan="5" style="text-align: center">To set values to encoder's operating parameters (Clear error message)</td>
<td>1. Enter 2 to select "Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "B9" in MRS code to select "Operating parameters"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 3 to select "Encoder to receive parameter"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter 0 in "parameter address" for selecting "Error message"</td>
<td></td>
</tr>
<tr>
<td>5. Enter 0 in "parameter value" for seting value in " Error message"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="5" style="text-align: center">6.</td>
<td rowspan="5" style="text-align: center">To set values to encoder's operating parameters (Clear warning message)</td>
<td>1. Enter 2 to select "Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "B9" in MRS code to select "Operating parameters"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 3 to select "Encoder to receive parameter"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter 01 in "parameter address" for selecting "Error message"</td>
<td></td>
</tr>
<tr>
<td>5. Enter 0 in "parameter value" for seting value in " Error message"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="8" style="text-align: center">7.</td>
<td rowspan="8" style="text-align: center">To set values to encoder's manufacturing parameters for Endat 2.2(Status of additional info)</td>
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td></td>
</tr>
<tr>
<td>2. Enter "45" in MRS code to select "Parameters of encoder manufacturer for Endat 2.2"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>4. Enter "BD" in MRS code to select "Memory parameter (LSB)" of Additional Information 1</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>5. Enter 10 to select "Encoder send position values + Additional Information(s) and receive parameter"</td>
<td></td>
</tr>
<tr>
<td>6. Enter 0 in "parameter address" for selecting "Status of additional info"</td>
<td></td>
</tr>
<tr>
<td>7. Enter 1235 (or any 2 byte value) in "parameter value" for seting value in " Status of additional info"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>8. Enter 8 to select "Encoder send position values + Additional Information(s)"<br>&emsp; <b>Note: Write is not permenant. When read again using Command 11, encoder will return the default value</b></td>
<td style="text-align: center">Values followed by 0x45 represents last byte of the data received by encoder<br> Crc success </td>
</tr>
<tr>
<td style="text-align: center">8.</td>
<td style="text-align: center">To reset encoder</td>
<td>1. Enter 5 to select "Encoder receive reset"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="3" style="text-align: center">9.</td>
<td rowspan="3" style="text-align: center">To receive test values from encoder with port address "0"</td>
<td>1. Enter 7 to select "Encoder receive test command"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter 0 in "enter port address" </td>
<td> </td>
</tr>
<tr>
<td>3. Enter 6 to select "Encoder send test values"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="3" style="text-align: center">10.</td>
<td rowspan="3" style="text-align: center">To receive test values from encoder with port address "E" </td>
<td>1. Enter 7 to select "Encoder receive test command"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "E" in "enter port address" </td>
<td> </td>
</tr>
<tr>
<td>3. Enter 6 to select "Encoder send test values"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="5" style="text-align: center">11.</td>
<td rowspan="5" style="text-align: center">To check position value with aditional info.</td>
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>2. Enter "47" in MRS code to select "Acknowledge MRS code" of Additional Information 1</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter "56" in MRS code to select "Asynchronous Position value word 1 LSB" of Additional Information 2</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>5. Enter 8 to select "Encoder send position values + Additional Information(s)"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="7" style="text-align: center">12.</td>
<td rowspan="7" style="text-align: center">To receive encoder's operating parameters(error messege)
+receive position value with additional info
</td>
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "45" in MRS code to select "Memory parameter (LSB)" of Additional Information 1</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter "B9" in MRS code to select "Operating parameters"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>5. Enter 11 to select "Encoder send position values + Additional Information(s) and send parameter"</td>
<td> </td>
</tr>
<tr>
<td>6. Enter 0 in "parameter address" for selecting "Error message"</td>
<td style="text-align: center">CRC success</td>
</tr>
<tr>
<td>7. Enter 8 to select "Encoder send position values + Additional Information(s)"</td>
<td style="text-align: center">CRC success</td>
</tr>
<tr>
<td rowspan="7" style="text-align: center">13.</td>
<td rowspan="7" style="text-align: center">To receive encoder's manufacture parameters
for Endat 2.2 +receive position value with additional info
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "45" in MRS code to select "Memory parameter (LSB)" of Additional Information 1</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter "BD" in MRS code to select "Parameters of encoder manufacturer for Endat 2.2"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>5. Enter 11 to select "Encoder send position values + Additional Information(s) and send parameter"</td>
<td> </td>
</tr>
<tr>
<td>6. Enter 0 in "parameter address" for selecting "Status of additional info 1"</td>
<td> </td>
</tr>
<tr>
<td>7. Enter 8 to select "Encoder send position values + Additional Information(s)"</td>
<td style="text-align: center">CRC success</td>
</tr>
<tr>
<td rowspan="5" style="text-align: center">14.</td>
<td rowspan="5" style="text-align: center">To acknowledge MRS code for Endat 2.2
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "47" in MRS code to select "Acknowledge MRS code" of Additional Information 1</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area</td>
<td> </td>
</tr>
<tr>
<td>4. Enter "BD" or any other valid MRS code </td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>5. Enter 8 to select "Encoder send position values + Additional Information(s)"</td>
<td style="text-align: center">Additional Information 1:0x47bd00<br>&emsp;&emsp;&emsp;&emsp;(for MRS code = BD) </td>
</tr>
<tr>
<td rowspan="5" style="text-align: center">15.</td>
<td rowspan="5" style="text-align: center">To set values to encoder's operating parameters (error message)
+receive position value with additional info
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "B9" in MRS code to select "Operating parameters"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 10 to select "Encoder send position values + Additional Information(s) and receive parameter"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter 0 in "parameter address" for selecting "Error message"</td>
<td> </td>
</tr>
<tr>
<td>5. Enter 0 in "parameter value" for seting value in "Error message"</td>
<td style="text-align: center">CRC success</td>
</tr>
<tr>
<td rowspan="5" style="text-align: center">16.</td>
<td rowspan="5" style="text-align: center">To set values to encoder's manufacturing parameters for Endat 2.2(Status of additional info)
+receive position value with additional info
</td>
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "BD" in MRS code to select "Parameters of encoder manufacturer for Endat 2.2"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 10 to select "Encoder send position values + Additional Information(s) and receive parameter"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter 0 in "parameter address" for selecting "Status of additional info"</td>
<td> </td>
</tr>
<tr>
<td>5. Enter 0 in "parameter value" for seting value in " Status of additional info"</td>
<td style="text-align: center">CRC success</td>
</tr>
<tr>
<td rowspan="7" style="text-align: center">17.</td>
<td rowspan="7" style="text-align: center">To receive encoder's OEM (Original Equipment Manufacturer) data </td>
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "45" in MRS code to select "Memory parameter (LSB)" of Additional Information 1</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter A9 (or AB or AD) in MRS code to select the OEM memory</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>5. Enter 11 to select "Encoder send position values + Additional Information(s) and send parameter"</td>
<td> </td>
</tr>
<tr>
<td>6. Enter 40 in "parameter address" </td>
<td> </td>
</tr>
<tr>
<td>7. Enter 8 to select "Encoder send position values + Additional Information(s)"</td>
<td style="text-align: center">CRC success</td>
</tr>
<tr>
<td rowspan="5" style="text-align: center">18.</td>
<td rowspan="5" style="text-align: center">To set values in OEM memory area </td>
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter "A9" in MRS code to select "Operating parameters"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter 10 to select "Encoder send position values + Additional Information(s) and receive parameter"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter 40 in "parameter address" </td>
<td> </td>
</tr>
<tr>
<td>5. Enter E9 in "parameter value"</td>
<td style="text-align: center">CRC success</td>
</tr>
<tr>
<td rowspan="7" style="text-align: center">19.</td>
<td rowspan="7" style="text-align: center">To reset encoder +receive position value with additional info</td>
<td>1. Enter 12 to select "Encoder send position values + Additional Information(s) and receive error reset"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>1. Enter 14 to select "Encoder receive communication command"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>2. Enter ______in "enter encoder address" </td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter _____ in "instruction hex value"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>1. Enter 14 to select "Encoder receive communication command"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>2. Enter ______in "enter encoder address" </td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td>3. Enter _____ in "instruction hex value"</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="2" style="text-align: center">20.</td>
<td rowspan="2" style="text-align: center">Configure Clock </td>
<td>1. Enter 100 to select "configure clock"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter ___ for clock frequency(in Hz)</td>
<td style="text-align: center">CRC success(Tested up to 8MHz)</td>
</tr>
<tr>
<td rowspan="3" style="text-align: center">21.</td>
<td rowspan="3" style="text-align: center">Simulate motor control 2.1 position loop</td>
<td>1. Enter 101 to select "Simulate motor control 2.1 position loop"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter 1000 to select "clock frequency"</td>
<td> </td>
</tr>
<tr>
<td>3. Rotate the rotor of motor and see the changes in Position value on UART</td>
<td style="text-align: center">Position Values are changing when rotor moves </td>
</tr>
<tr>
<td rowspan="2" style="text-align: center">22.</td>
<td rowspan="2" style="text-align: center">Toggle raw data display</td>
<td>1. Enter 102 to select "Toggle raw data display"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter 1 to select "Encoder send position value"</td>
<td style="text-align: center">raw data can be displayed </td>
</tr>
<tr>
<td style="text-align: center">23.</td>
<td style="text-align: center">Configure TST delay</td>
<td></td>
<td> </td>
</tr>
<tr>
<td rowspan="2" style="text-align: center">24.</td>
<td rowspan="2" style="text-align: center">Start continuous mode</td>
<td>1. Enter 104 to select "Start continuous mode"</td>
<td> </td>
</tr>
<tr>
<td>2. Rotate the rotor of motor and see the changes in Position value on UART</td>
<td style="text-align: center">Position Values are changing when rotor moves </td>
</tr>
<tr>
<td rowspan="3" style="text-align: center">25.</td>
<td rowspan="3" style="text-align: center">Configure rx arm counter</td>
<td>1. Enter 105 to select "Configure rx arm counter" </td>
<td> </td>
</tr>
<tr>
<td>2. Enter 0 to select channel 0 </td>
<td> </td>
</tr>
<tr>
<td>3. Enter ___ to "select time in ns"</td>
<td> </td>
</tr>
<tr>
<td rowspan="3" style="text-align: center">26.</td>
<td rowspan="3" style="text-align: center">configure rx clock disable time</td>
<td>1. Enter 106 to select "configure rx clock disable time"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter 0 to select channel 0</td>
<td> </td>
</tr>
<tr>
<td>3. Enter ___ to "select time in ns"</td>
<td> </td>
</tr>
<tr>
<td rowspan="3" style="text-align: center">27.</td>
<td rowspan="3" style="text-align: center">Simulate motor control 2.2 position loop(safety)</td>
<td>1. Enter 107 to select "Simulate motor control 2.2 position loop"</td>
<td> </td>
</tr>
<tr>
<td>2. Enter 1000 to select "clock frequency"</td>
<td> </td>
</tr>
<tr>
<td>3. Rotate the rotor of motor and see the changes in Position value on UART</td>
<td style="text-align: center">Position Values are changing when rotor moves </td>
</tr>
<tr>
<td rowspan="2" style="text-align: center">28.</td>
<td rowspan="2" style="text-align: center">Configure propogation delay(td)</td>
<td>1. Enter 108 to select configure propagation delay </td>
<td> </td>
</tr>
<tr>
<td>2. Enter 0 to select channel 0</td>
<td> </td>
</tr>
<tr>
<td rowspan="5" style="text-align: center">29.</td>
<td rowspan="5" style="text-align: center">Configure Recovery time (tr) using EnDat 2.2 mode transmission</td>
<td>1. Enter 9 to select "Encoder send position values + Additional Information(s) and Selection of memory area" </td>
<td> </td>
</tr>
<tr>
<td>2. Enter "B9" in MRS code to select "Operating parameters"</td>
<td> </td>
</tr>
<tr>
<td>3. Enter 10 to select "Encoder send position values + Additional Information(s) and receive parameter"</td>
<td> </td>
</tr>
<tr>
<td>4. Enter 03 in "parameter address" for selecting "Initializing the functions"</td>
<td> </td>
</tr>
<tr>
<td>5. Enter 01 in "parameter value" for selecting low recovery time<br>&emsp;&emsp;&emsp;&emsp;&emsp;&emsp;&emsp;&emsp;&emsp;&emsp;&emsp;&emsp;&emsp;&emsp; or <br>&nbsp; &nbsp;Enter 02 in "parameter value" for selecting high recovery time</td>
<td style="text-align: center">CRC success </td>
</tr>
<tr>
<td rowspan="2" style="text-align: center">30.</td>
<td rowspan="2" style="text-align: center">To read Recovery Time</td>
<td>1. Enter 8 to select "Encoder send position values + Additional Information(s)" </td>
<td style="text-align: center">CRC Success </td>
</tr>
<tr>
<td>2. Enter 110 for read recovery time from DMEM </td>
<td style="text-align: center">Recovery Time is set to 1.25 us <= RT <= 3.75us or 10 us <= RT <= 30 us</td>
</tr>
<tr>
<td rowspan="2" style="text-align: center">31.</td>
<td rowspan="2" style="text-align: center">To test periodic continuous mode</td>
<td>1. Enter 200 to enable periodic mode </td>
<td style="text-align: center"> </td>
</tr>
<tr>
<td>2. Enter 5000 (in ns) for position read time </td>
<td style="text-align: center">Position Values are changing when rotor moves </td>
</tr>
<tr>
<td rowspan="2" style="text-align: center">32.</td>
<td rowspan="2" style="text-align: center">Long term test</td>
<td>1. Enter 111 to enable Long time continuous mode </td>
<td></td>
</tr>
<tr>
<td>2. press enter to stop the long term test</td>
<td style="text-align: center">The result shows the number of position command sent and the number of CRC failures received</td>
</tr>
</table>

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# Examples and Demos {#EXAMPLES}
This page lists all the examples and demos supported in this SDK.
\cond SOC_AM64X
- Position Sense
-# \subpage EXAMPLE_MOTORCONTROL_ENDAT
-# \subpage EXAMPLE_MOTORCONTROL_HDSL
-# \subpage EXAMPLE_MOTORCONTROL_TAMAGAWA
- Current Sense
-# \subpage EXAMPLE_MOTORCONTROL_SDFM
\endcond
\cond SOC_AM243X
- Position Sense
-# \subpage EXAMPLE_MOTORCONTROL_ENDAT
-# \subpage EXAMPLE_MOTORCONTROL_HDSL
-# \subpage EXAMPLE_MOTORCONTROL_TAMAGAWA
- Current Sense
-# \subpage EXAMPLE_MOTORCONTROL_SDFM
- RTLibs
-# \subpage EXAMPLES_DCL_PI
-# \subpage EXAMPLES_DCL_DF22
\endcond
\cond SOC_AM263X
- Position Sense
-# \subpage EXAMPLE_MOTORCONTROL_TAMAGAWA_OVER_UART
- RTLibs
-# \subpage EXAMPLES_DCL_PI
-# \subpage EXAMPLES_DCL_DF22
\endcond

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# HDSL Diagnostic {#EXAMPLE_MOTORCONTROL_HDSL}
[TOC]
## Introduction
The HDSL diagnostic application described here interacts with the firmware interface.
HDSL diagnostic application does below,
- Configures pinmux, GPIO, ICSS clock to 300MHz,
- Initializes ICSS0-PRU1, ICSS0-IEP0 and IEP1(for SYNC mode support.Timesync router is used to latch the loopback.),
- Loads lookup table for encoding/decoding of Hiperface data
- Loads the initialization section of PRU firmware & executes it.
Firmware is split to three sections, initialization, datalink and transport.
At startup, the application displays details about encoder and status.
It then presents the user with menu options, based on the option selected, application communicates with HDSL interface and the result is presented to the user.
This example also allows the capability to save the HDSL register data into memory for the defined duration.
\cond SOC_AM243X
- For @VAR_BOARD_NAME_LOWER example, the data is stored in DDR.
- For @VAR_LP_BOARD_NAME_LOWER example, the data is stored in MSRAM.
\endcond
\note The HDSL register trace option is only available with debug mode builds for single channel examples.
## Important files and directory structure
<table>
<tr>
<th>Folder/Files
<th>Description
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/examples/position_sense/hdsl_diagnostic</td></tr>
<tr>
<td>hdsl_diagnostic.c
hdsl_diagnostic.h</td>
<td> Source and Header files </td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/source/position_sense/hdsl</td></tr>
<tr>
<td>driver/</td>
<td>Folder containing HDSL PRU driver sources.</td>
</tr>
<tr>
<td>include/</td>
<td>Folder containing HDSL PRU header sources.</td>
</tr>
<tr>
<td>firmware/</td>
<td>Folder containing HDSL PRU firmware sources.</td>
</tr>
</table>
\cond SOC_AM64X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 freertos
ICSSG | ICSSG0
PRU | PRU1
Toolchain | ti-arm-clang
Board | @VAR_BOARD_NAME_LOWER
Example folder | examples/position_sense/hdsl_diagnostic
\endcond
\cond SOC_AM243X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 freertos
ICSSG | ICSSG0
PRU | PRU1
Toolchain | ti-arm-clang
Board | @VAR_BOARD_NAME_LOWER (2 channel and 1 channel examples), @VAR_LP_BOARD_NAME_LOWER (1 channel example)
Example folder | examples/position_sense/hdsl_diagnostic
\endcond
# Steps to Run the Example
## Hardware Prerequisites
Other than the basic EVM setup mentioned in <a href="@VAR_MCU_SDK_DOCS_PATH/EVM_SETUP_PAGE.html" target="_blank"> EVM Setup </a>, below additional HW is required to run this demo
- HDSL encoder
- Below are two options to connect encoder to AM64x/AM243x EVM.
- **Option 1**
- <a href="http://www.ti.com/tool/TIDA-00179" target="_blank"> TIDA-00179 Universal Digital Interface to Absolute Position Encoders </a>
- TIDEP-01015 3 Axis board
- Interface card connecting EVM and TIDEP-01015 3 Axis board
- Connect the Hiperface DSL encoder to HDSL+/-(Pin number 6 and 7) signals available on header J7 or Sub-D15 connector of the "Universal Digital Interface to Absolute Position Encoders" board.
- **Option 2**
- HDSL AM64xE1 Transceiver. If application is using this card, define the macro HDSL_AM64xE1_TRANSCEIVER in the CCS project/make file.
- Connect the Hiperface DSL encoder to J10.
- HDSL AM64xE1 Transceiver supports two channels that can be used to support HDSL safety, multi axis servo drives.
- Schematics are shared in the MCU+SDK package. For more design details of the transceiver card, please contact TI via E2E/FAE.
- <a href="../HDSL_AM64xE1_Schematics.pdf" target="_blank"> HDSL Transceiver Card Schematics </a> document.
\cond SOC_AM243X
### Hardware Prerequisities for Booster Pack
- HDSL encoder
- AM243x-LP board
- <a href="https://www.ti.com/tool/BP-AM2BLDCSERVO" target="_blank"> BP-AM2BLDCSERVO </a>
\endcond
## Hardware Setup(Using TIDA-00179, TIDEP-01015 and Interface board)
\imageStyle{HDSL_Connections.png,width:40%}
\image html HDSL_Connections.png "Hardware Setup"
## Hardware Setup(Using HDSL AM64xE1 Transceiver)
\imageStyle{HDSL_AM64xE1.png,width:60%}
\image html HDSL_AM64xE1.png "Hardware Setup"
\cond SOC_AM243X
## Hardware Setup(Using Booster Pack & AM243x-LP)
\imageStyle{HDSL_Booster_Pack.png,width:40%}
\image html HDSL_Booster_Pack.png "Hardware Setup of Booster Pack + LP for HDSL"
#### Booster Pack Jumper Configuration
<table>
<tr>
<th>Designator</th>
<th>ON/OFF</th>
<th>Description</th>
</tr>
<tr>
<td>J11</td>
<td>OFF</td>
<td>VSENSE/ISENSE select</td>
</tr>
<tr>
<td>J13</td>
<td>OFF</td>
<td>VSENSE/ISENSE select</td>
</tr>
<tr>
<td>J17</td>
<td>Pin 1-2 Connected</td>
<td>%SDFM Clock Feedback Select</td>
</tr>
<tr>
<td>J18/J19</td>
<td>J18 OFF & J19 ON</td>
<td>Axis 1: Encoder/Resolver Voltage Select</td>
</tr>
<tr>
<td>J20/J21</td>
<td>J20 ON & J21 OFF</td>
<td>Axis 2: Encoder/Resolver Voltage Select</td>
</tr>
<tr>
<td>J22</td>
<td>OFF</td>
<td>Axis 1: Manchester Encoding Select</td>
</tr>
<tr>
<td>J23</td>
<td>OFF</td>
<td>Axis 2: Manchester Encoding Select</td>
</tr>
<tr>
<td>J24</td>
<td>ON</td>
<td>Axis 1: RS485/DSL MUX</td>
</tr>
<tr>
<td>J25</td>
<td>OFF</td>
<td>Axis 2: RS485/DSL MUX</td>
</tr>
<tr>
<td>J26</td>
<td>OFF</td>
<td>VSENSE/ISENSE Select</td>
</tr>
<tr>
<td>J27</td>
<td>ON</td>
<td>3WIRE/%SDFM MUX</td>
</tr>
<tr>
<td>J28</td>
<td>OFF</td>
<td>3WIRE MUX</td>
</tr>
</table>
\endcond
## Build, load and run
- **When using CCS projects to build**, import the CCS project and build it using the CCS project menu (see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_PROJECTS_PAGE.html" target="_blank"> Using SDK with CCS Projects </a>).
- **When using makefiles to build**, note the required combination and build using
make command (see <a href="@VAR_MCU_SDK_DOCS_PATH/MAKEFILE_BUILD_PAGE.html" target="_blank"> Using SDK with Makefiles </a>)
- Launch a CCS debug session and run the executable, see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_LAUNCH_PAGE.html" target="_blank"> CCS Launch, Load and Run </a>
- Refer to UART terminal for user interface menu options.
# Mode, Channel(s) and Board Selection from sysconfig:
- Select Mode from sysconfig menu (Freerun/sync mode).
- Select Channel 0/channel 1 from sysconfig menu for channel selection.
- Select Boosterpack option from sysconfig for running application on AM243x-LP.
\imageStyle{hdsl_sysconfig_menu.png,width:60%}
\image html hdsl_sysconfig_menu.png "HDSL SYSCONFIG Menu"
# Sample Output
Shown below is a sample output when the application is run
- Freerun mode
\image html hdsl_freerun_menu.png "HDSL Freerun mode Menu"
\image html hdsl_positional_commands_menu.png "HDSL Freerun mode Menu"
- Sync Mode
This is a test feature. In real application, PWM syncout will be connected to Latch input instead of IEP1 sync.
Enter 6000 as period in UART menu after loading application. Refer \ref HDSL_DESIGN_SYNC for more details about sync mode.
\image html hdsl_sync_mode_menu1.png "HDSL Sync mode Menu"
\image html hdsl_sync_mode_menu2.png "HDSL Sync mode Menu"
\image html hdsl_positional_commands_menu.png "HDSL Sync mode Menu"

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# %SDFM {#EXAMPLE_MOTORCONTROL_SDFM}
[TOC]
The ICSS %SDFM driver provides a well defined set of APIs to expose sigma delta interface.
The ICSS %SDFM example invokes these APIs to
- Set %SDFM channels
- Set ACC source, NC OSR, OC OSR, Clock source & Clock inversion
- Enable & disable threshold comparators
- Set high and low threshold values
- configure normal current sample trigger time (time for read sample)
- Enable & disable double update
- Inform firmware to enable %SDFM mode
- Configure GPIO pins for high and low threshold
Once these steps are executed
- ICSS %SDFM example waits for a interrupt (trigger by %SDFM firmware) to read sample data
- when interrupt occurs, example reads sample data from DMEM and again comes back to waiting loop
### ICSS SDFM Example Implementation
Following section describes the Example implementation of ICSS %SDFM on ARM(R5F).
\image html SDFM_EXAMPLE_FLOWCHART.png "ICSS SDFM Example"
## Important files and directory structure
<table>
<tr>
<th>Folder/Files
<th>Description
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm</td></tr>
<tr>
<td>app_sdfm.c & sdfm.c</td>
<td>ICSS %SDFM application</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/source/current_sense/sdfm</td></tr>
<tr>
<td>firmware/</td>
<td>Folder containing %SDFM firmware sources</td>
</tr>
<tr>
<td>driver/</td>
<td>ICSS %SDFM driver</td>
</tr>
<tr>
<td>include/</td>
<td>Folder containing ICSS %SDFM structures & APIs sources</td>
</tr>
</table>
# Supported Combinations {#EXAMPLES_MOTORCONTROL_SDFM_COMBOS}
\cond SOC_AM64X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 freertos
ICSSG | ICSSG0
PRU | PRU0
Toolchain | ti-arm-clang
Board | @VAR_BOARD_NAME_LOWER
Example folder | examples/current_sense/icss_sdfm
\endcond
\cond SOC_AM243X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 freertos
ICSSG | ICSSG0
PRU | PRU0
Toolchain | ti-arm-clang
Board | @VAR_BOARD_NAME_LOWER, @VAR_LP_BOARD_NAME_LOWER
Example folder | examples/current_sense/icss_sdfm
\endcond
# Steps to Run the Example
## Hardware Prerequisites
Other than the basic EVM setup mentioned in <a href="@VAR_MCU_SDK_DOCS_PATH/EVM_SETUP_PAGE.html" target="_blank"> EVM Setup </a>, below additional HW is required to run this demo
- TIDEP-01015 3 Axis board
- Interface card connecting EVM and TIDEP-01015 3 Axis board
- Signal generator
### Hardware Setup
\image html SDFM_HwSetup_image.PNG "Hardware Setup SDFM"
\image html SDFM_EVM_HW_setup.png "SDFM: EVM and 3axis board setup view"
\cond SOC_AM243X
### Hardware Prerequisities for LP
- AMC1035EVM
- AM243x-LP board
- Signal generator
#### LP Hardware set up
\image html SDFM_LpHwSetup_image.png "LP Hardware setup"
\image html SDFM_LpHwSetup.png "SDFM: LP setup view"
\endcond
## Build, load and run
- **When using CCS projects to build**, import the CCS project and build it using the CCS project menu (see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_PROJECTS_PAGE.html" target="_blank"> Using SDK with CCS Projects </a>).
- **When using makefiles to build**, note the required combination and build using
make command (see <a href="@VAR_MCU_SDK_DOCS_PATH/MAKEFILE_BUILD_PAGE.html" target="_blank"> Using SDK with Makefiles </a>)
- Launch a CCS debug session and run the executable, see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_LAUNCH_PAGE.html" target="_blank"> CCS Launch, Load and Run </a>
- Refer to UART terminal for user interface menu options.
### Test Case Description
<table>
<tr>
<th>Test detail
<th>Steps
<th>Pass/fail crieteria
</tr>
<tr>
<td>1. Normal current sample data</td>
<td>1. Run icss sdfm example on am64x/am243x board</td>
<td>he drawn graph and raw data should look like the attached image</td>
</tr>
<tr>
<td></td>
<td>2. Draw the graph of sdfm_ch0_samples, sdfm_ch1_samples and sdfm_ch2_samples arrays</td>
<td>\image html SDFM_sample_output.PNG "NC sample data"</td>
</tr>
<tr>
<td>2. To check raw data for Single Update (64 NC OSR)</td>
<td>1. Set NC OSR to 64</td>
<td>The drawn graph and raw data should look like the attached image</td>
</tr>
<tr>
<td></td>
<td>2. Set single update trigger time to half of epwm cycle time </td>
<td></td>
</tr>
<tr>
<td></td>
<td>3. Disable double update</td>
<td></td>
</tr>
<tr>
<td></td>
<td>3. Build and run icss sdfm example </td>
<td></td>
</tr>
<tr>
<td></td>
<td>4. Draw graph for Raw data</td>
<td>\image html SDFM_Single_update_64OSR.PNG "Single Update Raw data"</td>
</tr>
<tr>
<td>3. To check Raw data for Double Update</td>
<td>1. Set NC OSR to 64</td>
<td>drawn Graphs and raw data should look like attached image</td>
</tr>
<tr>
<td></td>
<td>2. Enable double update</td>
<td></td>
</tr>
<tr>
<td></td>
<td>3. Set single update trigger time to 1/4 of epwm cycle time</td>
<td></td>
</tr>
<tr>
<td></td>
<td>4. Set double update trigger time to 3/4 of epwm cycle time</td>
<td></td>
</tr>
<tr>
<td></td>
<td>5. Build and run icss sdfm example</td>
<td></td>
</tr>
<tr>
<td></td>
<td>6. Draw graph for Raw data</td>
<td>\image html SDFM_Double_update_64OSR.PNG "Double Update Raw data"</td>
</tr>
<tr>
<td></td>
<td></td>
<td>The pattern of the graph should be different from the single update graph. It takes 2 samples in one EPWM cycle so the graph pattern should look more like a sine wave compare to single update graph</td>
</tr>
<tr>
<td>4. To check Threshold comparator and Over current</td>
<td>1. Set High Threshold to 3500 and low threshold to 2500</td>
<td>Logic analyzer capture for High & Low Thresholds </td>
</tr>
<tr>
<td></td>
<td>2. Set Over current OSR to 32</td>
<td>\image html SDFM_threshold_comparator_salea_capture.png "Logic analyzer Capture"</td>
</tr>
<tr>
<td></td>
<td>3. Probe Ch0 high, low threshold GPIO pins & input signal </td>
<td></td>
</tr>
<tr>
<td></td>
<td>4. Build and run icss sdfm example</td>
<td></td>
</tr>
<tr>
<td></td>
<td>5. Capture signal in Logic analyzer</td>
<td></td>
</tr>
<tr>
<td>5. To check NC Samples with Different NC OSR Values</td>
<td>1. Set NC OSR values between 16 to 255 </td>
<td>Raw data should have different resolution for different OSR values </td>
</tr>
<tr>
<td></td>
<td>2. Build and run icss sdfm example</td>
<td></td>
</tr>
<tr>
<td></td>
<td>3. Observe resolution of raw data</td>
<td></td>
</tr>
<tr>
<td>6. To check NC samples with different sdfm clock values</td>
<td>1. Set NC OSR to 64</td>
<td> Raw data should have different resolution for different sdfm clock values </td>
</tr>
<tr>
<td></td>
<td>2. Set ecap_divider variable in sdfm.c file for different sd clock generation</td>
<td></td>
</tr>
<tr>
<td></td>
<td>3. Set Sigma delta clock equal to ecap generated clock</td>
<td></td>
</tr>
<tr>
<td></td>
<td>4. Build and run example</td>
<td></td>
</tr>
<tr>
<td></td>
<td>5. Observe resolution of raw data</td>
<td></td>
</tr>
\cond SOC_AM243X
<tr>
<td>7.Testing with sdfm clock from EPWM </td>
<td>1. Make hardware set up like attached image </td>
<td>All test cases results should match with ECAP test case results</td>
</tr>
<tr>
<td></td>
<td>2. \image html SDFM_EPWM1_HW_Setup.png "SDFM: Hw set for clock from EPWM"</td>
<td></td>
</tr>
<tr>
<td></td>
<td>3. Enable "APP_EPWM1_ENABLE" macro in app_sdfm.c file</td>
<td></td>
</tr>
<tr>
<td></td>
<td>4. Set EPWM1 out put frequency to 12.5MHz or 5MHz in app_sdfm.c file</td>
<td></td>
</tr>
<tr>
<td></td>
<td>5. Set Sigma delta clock equal to EPWM1 output frequency</td>
<td></td>
</tr>
<tr>
<td></td>
<td>6. Build and run icss sdfm example</td>
<td></td>
</tr>
<tr>
<td></td>
<td>7. Test all tese cases from 1 to 5 with EPWM clock</td>
<td></td>
</tr>
\endcond
</table>

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# Tamagawa Diagnostic {#EXAMPLE_MOTORCONTROL_TAMAGAWA}
[TOC]
\note
Starting with MCU+ SDK version 08.05.00, the Tamagawa firmware and examples are based on EnDAT hardware interface from PRU-ICSSG.
## Introduction
Tamagawa diagnostic application does below,
Configures pinmux, GPIO, UART, ICSS clock to 200MHz,
Initializes ICSS0-PRU1,
Loads the initialization section of PRU firmware & executes it.
This application is controlled with a terminal interface using a serial over USB connection between the PC host and the EVM.
Please connect a USB cable between the PC and the EVM/LP.
A serial terminal application (like teraterm/ hyperterminal/ minicom) is then run on the host.
To configure, select the serial port corresponding to the port emulated over USB by the EVM.
The host serial port should be configured to 115200 baud, no parity, 1 stop bit and no flow control.
Connect the Tamagawa encoders via TIDA-00179 cards on a 3 axis board (TIDEP-01015) to the EVM.
On AM243x LP, a Tamagawa encoder can be directly connected using a TIDA-00179 card.
\note
Only single channel configuration with Channel 0 is supported as of now on LP.
The connections between AM243x LP and TIDA-00179 for Channel 0 are:
TAMAGAWA_CHANNEL0_TX -> PRG0_PRU1_GPO1,
TAMAGAWA_CHANNEL0_TX_ENABLE -> PRG0_PRU1_GPO2,
TAMAGAWA_CHANNEL0_RX -> PRG0_PRU1_GPO13,
TAMAGAWA_CHANNEL0_CLK -> PRG0_PRU1_GPO0.
The Tamagawa receiver firmware running on ICSS0-PRU1 provides a defined interface. The Tamagawa diagnostic application interacts with the Tamagawa receiver firmware interface. It then presents the user with menu options to select Data ID code (as defined by Tamagawa) to be sent to the encoder. The application collects the data entered by the user and configures the relevant interface. Then via the Tamagawa receiver interface, the command is triggered. Once the command completion is indicated by the interface, the status of the transaction is checked. If the Status indicates success, the result is presented to the user.
## Important files and directory structure
<table>
<tr>
<th>Folder/Files
<th>Description
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/examples/position_sense/tamagawa_diagnostic</td></tr>
<tr>
<td>tamagawa_diagnostic.c</td>
<td>Tamagawa diagnostic application</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/source/position_sense/tamagawa</td></tr>
<tr>
<td>firmware/</td>
<td>Folder containing TAMAGAWA PRU firmware sources.</td>
</tr>
<tr>
<td>driver/</td>
<td>Tamagawa diagnostic driver.</td>
</tr>
</table>
# Supported Combinations {#EXAMPLES_MOTORCONTROL_TAMAGAWA_COMBOS}
\cond SOC_AM64X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 freertos
ICSSG | ICSSG0
PRU | PRU1
Toolchain | ti-arm-clang
Board | @VAR_BOARD_NAME_LOWER
Example folder | examples/position_sense/tamagawa_diagnostic
\endcond
\cond SOC_AM243X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 freertos
ICSSG | ICSSG0
PRU | PRU1
Toolchain | ti-arm-clang
Board | @VAR_BOARD_NAME_LOWER, @VAR_LP_BOARD_NAME_LOWER (E3 Revision)
Example folder | examples/position_sense/tamagawa_diagnostic
\endcond
# Steps to Run the Example
## Hardware Prerequisites
Other than the basic EVM setup mentioned in <a href="@VAR_MCU_SDK_DOCS_PATH/EVM_SETUP_PAGE.html" target="_blank"> EVM Setup </a>, additional hardware required to run this demo is mentioned below
- Tamagawa Encoders
- <a href="http://www.ti.com/tool/TIDA-00179" target="_blank"> TIDA-00179 Universal Digital Interface to Absolute Position Encoders </a>
- TIDEP-01015 3 Axis board
- Interface card connecting EVM and TIDEP-01015 3 Axis board
\cond SOC_AM243X
### Hardware Prerequisities for Booster Pack
- Tamagawa encoder
- AM243x-LP board
- <a href="https://www.ti.com/tool/BP-AM2BLDCSERVO" target="_blank"> BP-AM2BLDCSERVO </a>
\endcond
## Hardware Setup
\imageStyle{Tamagawa_setup.jpg,width:60%}
\image html Tamagawa_setup.jpg "Hardware Setup for 3 channels on EVM"
\imageStyle{Tamagawa_connections.JPG,width:60%}
\image html Tamagawa_connections.JPG "Tamagawa Encoder Hardware Setup for 3 channels"
\cond SOC_AM243X
\imageStyle{Tamagawa_Setup_am243x_lp.jpeg,width:60%}
\image html Tamagawa_Setup_am243x_lp.jpeg "Hardware Setup for 1 channel on AM243x Launchpad"
## Hardware Setup(Using Booster Pack & AM243x-LP)
\imageStyle{Tamagawa_Booster_Pack.png,width:40%}
\image html Tamagawa_Booster_Pack.png "Hardware Setup of Booster Pack + LP for Tamagawa"
#### Booster Pack Jumper Configuration
<table>
<tr>
<th>Designator</th>
<th>ON/OFF</th>
<th>Description</th>
</tr>
<tr>
<td>J11</td>
<td>OFF</td>
<td>VSENSE/ISENSE select</td>
</tr>
<tr>
<td>J13</td>
<td>OFF</td>
<td>VSENSE/ISENSE select</td>
</tr>
<tr>
<td>J17</td>
<td>Pin 1-2 Connected</td>
<td>%SDFM Clock Feedback Select</td>
</tr>
<tr>
<td>J18/J19</td>
<td>J18 OFF & J19 ON</td>
<td>Axis 1: Encoder/Resolver Voltage Select</td>
</tr>
<tr>
<td>J20/J21</td>
<td>J20 ON & J21 OFF</td>
<td>Axis 2: Encoder/Resolver Voltage Select</td>
</tr>
<tr>
<td>J22</td>
<td>OFF</td>
<td>Axis 1: Manchester Encoding Select</td>
</tr>
<tr>
<td>J23</td>
<td>OFF</td>
<td>Axis 2: Manchester Encoding Select</td>
</tr>
<tr>
<td>J24</td>
<td>OFF</td>
<td>Axis 1: RS485/DSL MUX</td>
</tr>
<tr>
<td>J25</td>
<td>OFF</td>
<td>Axis 2: RS485/DSL MUX</td>
</tr>
<tr>
<td>J26</td>
<td>OFF</td>
<td>VSENSE/ISENSE Select</td>
</tr>
<tr>
<td>J27</td>
<td>ON</td>
<td>3WIRE/%SDFM MUX</td>
</tr>
<tr>
<td>J28</td>
<td>OFF</td>
<td>3WIRE MUX</td>
</tr>
</table>
\endcond
## Build, load and run
- **When using CCS projects to build**, import the CCS project and build it using the CCS project menu (see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_PROJECTS_PAGE.html" target="_blank"> Using SDK with CCS Projects </a>).
- **When using makefiles to build**, note the required combination and build using
make command (see <a href="@VAR_MCU_SDK_DOCS_PATH/MAKEFILE_BUILD_PAGE.html" target="_blank"> Using SDK with Makefiles </a>)
- Launch a CCS debug session and run the executable, see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_LAUNCH_PAGE.html" target="_blank"> CCS Launch, Load and Run </a>
- Refer to UART terminal for user interface menu options.
### Sample Output
Shown below is a sample output when the application is run:
\imageStyle{Tamagawa_SampleOutput.JPG,width:60%}
\image html Tamagawa_SampleOutput.JPG "Tamagawa Sample Output"
### Test Case Description
<table>
<tr>
<th>Data_ID
<th>Name
<th>Description
<th>Pass/fail Criteria
</tr>
<tr>
<td>Data ID 0</td>
<td>Data readout (absolute position data)</td>
<td>In this command we will receive:
Absolute rotor position value in field name ABS..
Errors and warnings in field name SF(status field)
</td>
<td>CRC success with ABS, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 1</td>
<td>Data readout (multi-turn data)</td>
<td>In this command we will receive data about:
No. of rotor turns in field name ABM.
Errors and warnings in field name SF(status field).
</td>
<td>CRC success with ABM, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 2</td>
<td>Endoder-ID</td>
<td>In this command we will receive data about :
Tamagawa encoder make-ID in ENID field .
Errors and warnings in field name SF(status field)
</td>
<td>CRC success with ENID, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 3</td>
<td>Data readout(absolute+multiturn+encoder-ID)</td>
<td>In this command we will receive :
Absolute rotor position value in field name ABS.
No. of rotor turns in field name ABM.
Tamagawa encoder make-ID in ENID field .
Errors and warnings in field name SF(status field)
Other warnings in field name ALMC
</td>
<td>CRC success with ABS, ENID, ABM, ALMC, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 6</td>
<td>Writing to EEPROM</td>
<td>In this command you provide :
Proper address of the EEPROM where you want to write
Proper data that you want to write.<br>
As a response you recieve:
Control Field for EEPROM Write command
EEPROM address that you want to write to
Data that you want to write to the EEPROM
CRC value
</td>
<td>CRC success with EDF, ADF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID D</td>
<td>Readout from EEPROM</td>
<td>In this command you provide :
Proper address of the EEPROM that you want to read.<br>
As a response you recieve:
Control Field for EEPROM Write command
EEPROM address that you want to write to
Data that you want to write to the EEPROM
CRC value
</td>
<td>CRC success with EDF, ADF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 7</td>
<td>Reset-Error</td>
<td>This command used to reset errors. </td>
<td>CRC success with ABS, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 8</td>
<td>Reset - absolute</td>
<td>This command is used to reset absolute position data(ABS). In order to reset the ABS value, send this command 10 times and send Data ID 0. </td>
<td>CRC success with ABS value set to 0 along with SF, CF and CRC values printed in the terminal.</td>
</tr> <tr>
<td>Data ID C</td>
<td>Reset - multiturn</td>
<td>This command is used to reset multi-turn data(ABM). In order to reset the ABM value, send this command 10 times and send Data ID 1. </td>
<td>CRC success with ABM value set to 0 along with SF, CF and CRC values printed in the terminal.</td>
</tr>
</table>

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# Tamagawa over Uart Example {#EXAMPLE_MOTORCONTROL_TAMAGAWA_OVER_UART}
[TOC]
## Introduction
Tamagawa over uart application does below,
- Configures pinmux, GPIO, UART (UART clock to 192MHz, Baud rate, etc.)
- Initializes UART0 for debug log & UART1 for communication
- Load and executes tamagawa example on R5_0
Connect the Tamagawa encoder via RS-485 Half-Duplex EVM to Am263x-LP.
The connections between AM263x LP and RS-485
UART RX Pin(UART1_RXD)->JMP1-R,
UART TX Pin(UART1_TXD)->JMP4-D,
GPIO Pin(GPIO62)->JM3-DE
The tamagawa over uart example runs on R5 and communicates with tamagawa encoder by UART1. It presents the user with menu options to select Data ID code (as defined by Tamagawa) to be sent to the encoder. The application collects the data entered by the user and configures the relevant command. Then via the UART1 write API, the command is passed to encoder. Once the command is sent, the encoder starts to respond, and UART1 read API starts to read this response. Response is stored in the tamagawa interface, the status of the transaction is check by CRC calculation. If the status indicates success, the result is presented to the user otherwise print CRC failure.
### Example Flow-Chart
\image html Tamagawa_uart_flow_chart.png "Tamagawa UART example flow-chart"
## Important files and directory structure
<table>
<tr>
<th>Folder/Files
<th>Description
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/examples/position_sense/tamagawa_diagnostic_over_soc_uart</td></tr>
<tr>
<td>uart_tamagawa.c</td>
<td>Tamagawa UART application</td>
</tr>
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/source/position_sense/tamagawa_over_soc_uart</td></tr>
<tr>
<td>include/</td>
<td>Folder containing tamagawa interface file.</td>
</tr>
<tr>
<td>driver/</td>
<td>Tamagawa uart driver</td>
</tr>
</table>
# Supported Combinations
\cond SOC_AM263X
Parameter | Value
---------------|-----------
CPU + OS | r5fss0-0 freertos
Toolchain | ti-arm-clang
Board | @VAR_LP_BOARD_NAME_LOWER
Example folder | examples/position_sense/tamagawa_diagnostic_over_soc_uart
\endcond
# Steps to Run the Example
## Hardware Prerequisites
- Tamagawa Encoders
- AM263x LP
- RS-485 Half Duplex EVM
- 5V and 3.3V power supplier
## Hardware Setup
\imageStyle{Tamagawa_Uart_Hw_Setup.PNG,width:60%}
\image html Tamagawa_Uart_Hw_Setup.PNG "Tamagawa Encoder Hardware Setup with AM263x"
\imageStyle{Tamagawa_Setup_image.jpg,width:60%}
\image html Tamagawa_Setup_image.jpg "Hardware Setup For AM263x-LP"
## Build, load and run
- **When using CCS projects to build**, import the CCS project and build it using the CCS project menu (see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_PROJECTS_PAGE.html" target="_blank"> Using SDK with CCS Projects </a>).
- **When using makefiles to build**, note the required combination and build using
make command (see <a href="@VAR_MCU_SDK_DOCS_PATH/MAKEFILE_BUILD_PAGE.html" target="_blank"> Using SDK with Makefiles </a>)
- Launch a CCS debug session and run the executable, see <a href="@VAR_MCU_SDK_DOCS_PATH/CCS_LAUNCH_PAGE.html" target="_blank"> CCS Launch, Load and Run </a>
- Refer to UART terminal for user interface menu options.
### Sample Output
Shown below is a sample output when the application is run:
\imageStyle{Tamagawa_UART_output.PNG,width:60%}
\image html Tamagawa_UART_output.PNG "Tamagawa UART Sample Output"
### Test Case Description
<table>
<tr>
<th>Data_ID
<th>Name
<th>Description
<th>Pass/fail Criteria
</tr>
<tr>
<td>Data ID 0</td>
<td>Data readout (absolute position data)</td>
<td>In this command we will receive:
Absolute rotor position value in field name ABS.
Errors and warnings in field name SF(status field)
</td>
<td>CRC success with ABS, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 1</td>
<td>Data readout (multi-turn data)</td>
<td>In this command we will receive data about:
No. of rotor turns in field name ABM.
Errors and warnings in field name SF(status field).
</td>
<td>CRC success with ABM, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 2</td>
<td>Endoder-ID</td>
<td>In this command we will receive data about :
Tamagawa encoder make-ID in ENID field.
Errors and warnings in field name SF(status field)
</td>
<td>CRC success with ENID, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 3</td>
<td>Data readout(absolute+multiturn+encoder-ID)</td>
<td>In this command we will receive :
Absolute rotor position value in field name ABS.
No. of rotor turns in field name ABM.
Tamagawa encoder make-ID in ENID field.
Errors and warnings in field name SF(status field)
Other warnings in field name ALMC
</td>
<td>CRC success with ABS, ENID, ABM, ALMC, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 6</td>
<td>Writing to EEPROM</td>
<td>In this command you provide :
Proper address of the EEPROM where you want to write
Proper data that you want to write.<br>
As a response you recieve:
Control Field for EEPROM Write command
EEPROM address that you want to write to
Data that you want to write to the EEPROM
CRC value
</td>
<td>CRC success with EDF, ADF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID D</td>
<td>Readout from EEPROM</td>
<td>In this command you provide :
Proper address of the EEPROM that you want to read.<br>
As a response you recieve:
Control Field for EEPROM Write command
EEPROM address that you want to write to
Data that you want to write to the EEPROM
CRC value
</td>
<td>CRC success with EDF, ADF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 7</td>
<td>Reset-Error</td>
<td>This command used to reset errors. </td>
<td>CRC success with ABS, SF, CF and CRC values printed in the terminal.</td>
</tr>
<tr>
<td>Data ID 8</td>
<td>Reset- absolute</td>
<td>This command used to reset absolute position data(ABS) </td>
<td>CRC success with ABS, SF, CF and CRC values printed in the terminal.</td>
</tr> <tr>
<td>Data ID C</td>
<td>Reset- multiturn</td>
<td>This command used to reset multi-turn data(ABM) </td>
<td>CRC success with ABS, SF, CF and CRC values printed in the terminal.</td>
</tr>
</table>

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