1234 lines
42 KiB
C
1234 lines
42 KiB
C
//###########################################################################
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//
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// FILE: sysctl.h
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//
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// TITLE: CM system control driver.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef SYSCTL_H
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#define SYSCTL_H
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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//! \addtogroup sysctl_api SysCtl
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//! \brief The System Control module is used for miscellaneous system
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//! configurations.
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//! @{
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "inc/hw_memmap.h"
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#include "inc/hw_nmi.h"
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#include "inc/hw_sysctl.h"
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#include "inc/hw_types.h"
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#include "inc/hw_wwd.h"
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#include "debug.h"
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#include "cpu.h"
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//*****************************************************************************
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//
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// Defines for system control functions. Not intended for use by application
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// code.
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//
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//*****************************************************************************
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//
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// Shifted pattern for WDCR register's WDCHK field.
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//
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#define SYSCTL_WD_CHKBITS 0x0028U
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//
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// Keys for WDKEY field. The first enables resets and the second resets.
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//
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#define SYSCTL_WD_ENRSTKEY 0x0055U
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#define SYSCTL_WD_RSTKEY 0x00AAU
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//
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// Values to help decode peripheral parameter
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//
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#define SYSCTL_PERIPH_REG_M 0x001FU
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#define SYSCTL_PERIPH_REG_S 0x0000U
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#define SYSCTL_PERIPH_BIT_M 0x1F00U
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#define SYSCTL_PERIPH_BIT_S 0x0008U
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//
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//Keys for the NMI registers write protection
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//
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#define SYSCTL_CMNMIFLGCLR_KEY 0x5674U
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#define SYSCTL_CMNMIFLGFRC_KEY 0x2732U
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#define SYSCTL_CMNMICFG_KEY 0x6789U
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#define SYSCTL_CMNMIWDPRD_KEY 0x9238U
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//
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//Keys for the CPU Sysctrl registers write protection
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//
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#define SYSCTL_CMSYSCTL_KEY 0x5634U
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//
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//Keys for the WD registers write protection
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//
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#define SYSCTL_WWD_KEY 0x1234U
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//
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//Enable / disable the ETHERCAT I2C Loopback
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//
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#define SYSCTL_ETHERCAT_I2C_LOOPBACK 0x1U
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//
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//Enable / disable the Global NMI
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//
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#define SYSCTL_NMI_GLOBAL 0x1U
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//*****************************************************************************
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//
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// Values that can be passed to SysCtl_clearNMIStatus(),
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// SysCtl_forceNMIFlags(), SysCtl_isNMIFlagSet(), and
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// SysCtl_isNMIShadowFlagSet() as the nmiFlags parameter and returned by
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// SysCtl_getNMIFlagStatus() and SysCtl_getNMIShadowFlagStatus().
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//
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//*****************************************************************************
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#define SYSCTL_NMI_NMIINT 0x0001U //!< Non-maskable interrupt
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#define SYSCTL_NMI_CLOCKFAIL 0x0002U //!< Clock Failure
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#define SYSCTL_NMI_MEMUNCERR 0x0004U //!< RAM/ROM Uncorrectable error
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#define SYSCTL_NMI_FLUNCERR 0x0008U //!< Uncorrectable Flash error
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#define SYSCTL_NMI_MCANUNCERR 0x0010U //!< MCAN Uncorrectable Error
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#define SYSCTL_NMI_WWDNMI 0x0020U //!< CM Windowed Watchdog
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#define SYSCTL_NMI_ECATNMI 0x0040U //!< EtherCAT reset out
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//*****************************************************************************
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//
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// The following are values that can be passed to the SysCtl_clearResetCause()
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// API as rstCauses or returned by the SysCtl_getResetCause() API.
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//
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//*****************************************************************************
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#define SYSCTL_CAUSE_PORESETN 0x00000001U //!< Power-on reset
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#define SYSCTL_CAUSE_XRSN 0x00000002U //!< External reset pin
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#define SYSCTL_CAUSE_CPU1WDRSN 0x00000004U //!< CPU1 Watchdog reset
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#define SYSCTL_CAUSE_CPU1NMIWDRSN 0x00000008U //!< CPU1 NMI WD reset
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#define SYSCTL_CAUSE_CPU1SYSRSN 0x00000010U //!< CPU1 System reset
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#define SYSCTL_CAUSE_CPU1SCCRESETN 0x00000020U //!< CPU1 SCCRESETn reset
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#define SYSCTL_CAUSE_ECAT_RESET_OUT 0x00000040U //!< ECAT Reset
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#define SYSCTL_CAUSE_CPU1SIMRESET_CPURSN 0x00000080U //!< SIMRESET_CPURSn-CPU1
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#define SYSCTL_CAUSE_CMRSTCTLRESETREQ 0x00000100U //!< Reset req from CM
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#define SYSCTL_CAUSE_CMVECTRESETN 0x00010000U //!< CM Vector Reset
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#define SYSCTL_CAUSE_CMSYSRESETREQ 0x00020000U //!< CM System reset
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#define SYSCTL_CAUSE_CMNMIWDRSTN 0x00040000U //!< CM NMI WD Reset
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#define SYSCTL_CAUSE_CMEOLRESETN 0x00080000U //!< CM Execute Override
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//!< Logic reset
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//*****************************************************************************
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//
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// The following are values that can be passed to the
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// SysCtl_lockAccessControlRegs() API as access protection of
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// which control Registers.
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//
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//*****************************************************************************
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#define SYSCTL_CMECATCTL_LOCK 0x1U //!<block writes to CM-Ethercat control Reg
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//*****************************************************************************
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//
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// This frequency will be the CM clock frequency driven by c28x.
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//
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//*****************************************************************************
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#ifndef CM_CLK_FREQ
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#define CM_CLK_FREQ 125000000U
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#endif
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//*****************************************************************************
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//
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// SysCtl delay macro defined to allow a delay of fixed cycles.
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// This asm macro would be called through the SysCtl_delay API.
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//
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//*****************************************************************************
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#define SYSCTL_DELAY __asm( " .sect \".TI.ramfunc\"\n" \
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" .clink\n" \
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" .thumbfunc SysCtl_delay\n" \
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" .thumb\n" \
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" .global SysCtl_delay\n" \
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"SysCtl_delay:\n" \
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" subs r0, #1\n" \
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" bne.n SysCtl_delay\n" \
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" bx lr\n");
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//*****************************************************************************
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//
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//! The following are values that can be passed to SysCtl_enablePeripheral()
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//! and SysCtl_disablePeripheral() as the \e peripheral parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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//
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// PCLKCR0
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//
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SYSCTL_PERIPH_CLK_UART0 = 0x0000U, //!< UART0 clock
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SYSCTL_PERIPH_CLK_SSI0 = 0x0400U, //!< SSI0 clock
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SYSCTL_PERIPH_CLK_I2C0 = 0x0800U, //!< I2C0 clock
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SYSCTL_PERIPH_CLK_USB = 0x0C00U, //!< USB clock
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//
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// PCLKCR1
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//
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SYSCTL_PERIPH_CLK_ENET = 0x0001U, //!< ENET clock
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SYSCTL_PERIPH_CLK_ECAT = 0x0201U, //!< ECAT clock
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SYSCTL_PERIPH_CLK_CAN_A = 0x0401U, //!< CAN_A clock
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SYSCTL_PERIPH_CLK_CAN_B = 0x0501U, //!< CAN_B clock
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SYSCTL_PERIPH_CLK_MCAN_A = 0x0801U, //!< MCAN_A clock
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//
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// PCLKCR2
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//
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SYSCTL_PERIPH_CLK_TIMER0 = 0x0002U, //!< CPUtimer0 clock
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SYSCTL_PERIPH_CLK_TIMER1 = 0x0102U, //!< CPUtimer1 clock
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SYSCTL_PERIPH_CLK_TIMER2 = 0x0202U, //!< CPUtimer2 clock
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SYSCTL_PERIPH_CLK_UDMA = 0x0402U, //!< UDMA clock
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SYSCTL_PERIPH_CLK_AESIP = 0x0602U, //!< AESIP clock
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SYSCTL_PERIPH_CLK_GCRC = 0x0802U, //!< GCRC clock
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} SysCtl_PeripheralPCLOCKCR;
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//*****************************************************************************
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//
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//! The following are values that can be passed to SysCtl_resetPeripheral() as
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//! the \e peripheral parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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//
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// SOFTPRES0
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//
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SYSCTL_PERIPH_RES_UART0 = 0x0000U, //!< UART0 Reset
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SYSCTL_PERIPH_RES_SSI0 = 0x0400U, //!< SSI0 Reset
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SYSCTL_PERIPH_RES_I2C0 = 0x0800U, //!< I2C0 Reset
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SYSCTL_PERIPH_RES_USB = 0x0C00U, //!< USB Reset
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//
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// SOFTPRES1
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//
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SYSCTL_PERIPH_RES_ENET = 0x0001U, //!< ENET Reset
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SYSCTL_PERIPH_RES_ECAT = 0x0201U, //!< ECAT Reset
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SYSCTL_PERIPH_RES_CAN_A = 0x0401U, //!< CAN_A Reset
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SYSCTL_PERIPH_RES_CAN_B = 0x0501U, //!< CAN_B Reset
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SYSCTL_PERIPH_RES_MCAN_A = 0x0801U, //!< MCAN_A Reset
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//
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// SOFTPRES2
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//
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SYSCTL_PERIPH_RES_AESIP = 0x0602U, //!< AESIP Reset
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SYSCTL_PERIPH_RES_GCRC = 0x0802U, //!<GCRC Reset
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} SysCtl_PeripheralSOFTPRES;
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//*****************************************************************************
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//
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//! The following are values that can be passed to
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//! SysCtl_isPeripheralClockStopAcked()as the \e peripheral parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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//
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// CMCLKSTOPACK1
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//
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SYSCTL_PERIPH_ACK_MCAN_A = 0x0800U, //!< MCAN_A clock
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} SysCtl_PeripheralCMCLKSTOPACK;
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//*****************************************************************************
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//
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//! The following are values that can be passed to
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//! SysCtl_reqPeripheralClockStop()as the \e peripheral parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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//
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//CMCLKSTOPREQ1
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//
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SYSCTL_PERIPH_REQ_MCAN_A = 0x0801U, //!< MCAN_A clock
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} SysCtl_PeripheralCMCLKSTOPREQ;
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//*****************************************************************************
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//
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//! The following are values that can be passed to
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//! SysCtl_setWatchdogPredivider() as the \e predivider parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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SYSCTL_WD_PREDIV_2 = 0x800U, //!< PREDIVCLK = INTOSC1 / 2
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SYSCTL_WD_PREDIV_4 = 0x900U, //!< PREDIVCLK = INTOSC1 / 4
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SYSCTL_WD_PREDIV_8 = 0xA00U, //!< PREDIVCLK = INTOSC1 / 8
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SYSCTL_WD_PREDIV_16 = 0xB00U, //!< PREDIVCLK = INTOSC1 / 16
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SYSCTL_WD_PREDIV_32 = 0xC00U, //!< PREDIVCLK = INTOSC1 / 32
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SYSCTL_WD_PREDIV_64 = 0xD00U, //!< PREDIVCLK = INTOSC1 / 64
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SYSCTL_WD_PREDIV_128 = 0xE00U, //!< PREDIVCLK = INTOSC1 / 128
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SYSCTL_WD_PREDIV_256 = 0xF00U, //!< PREDIVCLK = INTOSC1 / 256
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SYSCTL_WD_PREDIV_512 = 0x000U, //!< PREDIVCLK = INTOSC1 / 512
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SYSCTL_WD_PREDIV_1024 = 0x100U, //!< PREDIVCLK = INTOSC1 / 1024
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SYSCTL_WD_PREDIV_2048 = 0x200U, //!< PREDIVCLK = INTOSC1 / 2048
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SYSCTL_WD_PREDIV_4096 = 0x300U //!< PREDIVCLK = INTOSC1 / 4096
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} SysCtl_WDPredivider;
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//*****************************************************************************
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//
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//! The following are values that can be passed to
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//! SysCtl_setWatchdogPrescaler() as the \e prescaler parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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SYSCTL_WD_PRESCALE_1 = 1U, //!< WDCLK = PREDIVCLK / 1
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SYSCTL_WD_PRESCALE_2 = 2U, //!< WDCLK = PREDIVCLK / 2
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SYSCTL_WD_PRESCALE_4 = 3U, //!< WDCLK = PREDIVCLK / 4
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SYSCTL_WD_PRESCALE_8 = 4U, //!< WDCLK = PREDIVCLK / 8
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SYSCTL_WD_PRESCALE_16 = 5U, //!< WDCLK = PREDIVCLK / 16
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SYSCTL_WD_PRESCALE_32 = 6U, //!< WDCLK = PREDIVCLK / 32
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SYSCTL_WD_PRESCALE_64 = 7U //!< WDCLK = PREDIVCLK / 64
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} SysCtl_WDPrescaler;
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//*****************************************************************************
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//
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// Prototypes for the APIs.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! Gets the reason for a reset.
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//!
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//! This function will return the reason(s) for a reset. Since the reset
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//! reasons are sticky until either cleared by software or an external reset,
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//! multiple reset reasons may be returned if multiple resets have occurred.
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//! The reset reason will be a logical OR of
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//! - \b SYSCTL_CAUSE_PORESETN - Power-on reset
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//! - \b SYSCTL_CAUSE_XRSN - External reset pin
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//! - \b SYSCTL_CAUSE_CPU1WDRSN - Watchdog reset from CPU1
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//! - \b SYSCTL_CAUSE_CPU1NMIWDRSN -NMI Watchdog reset from CPU1
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//! - \b SYSCTL_CAUSE_CPU1SYSRSN - System reset from CPU1
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//! - \b SYSCTL_CAUSE_CPU1SCCRESETN - SCCRESETn from CPU1
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//! - \b SYSCTL_CAUSE_ECAT_RESET_OUT - ECAT reset
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//! - \b SYSCTL_CAUSE_CPU1SIMRESET_CPURSN - SIMRESET from CPU1
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//! - \b SYSCTL_CAUSE_CMRSTCTLRESETREQ - System reset request from CM4
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//! - \b SYSCTL_CAUSE_CMVECTRESETN - Vectreset from CM4
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//! - \b SYSCTL_CAUSE_CMSYSRESETREQ - System reset request from CPU1
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//! - \b SYSCTL_CAUSE_CMNMIWDRSTN - NMI watchdog reset from CM4
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//! - \b SYSCTL_CAUSE_CMEOLRESETN - EOLRESETn reset from CM4
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//!
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//! \return Returns the reason(s) for a reset.
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//
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//*****************************************************************************
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static inline uint32_t
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SysCtl_getResetCause(void)
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{
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//
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// Return the reset reasons.
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//
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return(HWREG(CMSYSCTL_BASE + SYSCTL_O_CMRESC) &
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((uint32_t)SYSCTL_CMRESC_PORESETN | (uint32_t)SYSCTL_CMRESC_XRSN |
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(uint32_t)SYSCTL_CMRESC_CPU1_WDRSN |
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(uint32_t)SYSCTL_CMRESC_CPU1_SYSRSN |
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(uint32_t)SYSCTL_CMRESC_CMNMIWDRSTN |
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(uint32_t)SYSCTL_CMRESC_CMEOLRESETN |
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(uint32_t)SYSCTL_CMRESC_CPU1_NMIWDRSN |
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(uint32_t)SYSCTL_CMRESC_CPU1_SCCRESETN |
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(uint32_t)SYSCTL_CMRESC_ECAT_RESET_OUT |
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(uint32_t)SYSCTL_CMRESC_CMRSTCTL_RESETREQ |
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(uint32_t)SYSCTL_CMRESC_CPU1_SIMRESET_CPURSN |
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(uint32_t)SYSCTL_CMRESC_CMSYSRESETREQ |
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(uint32_t)SYSCTL_CMRESC_CMVECTRESETN));
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}
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//*****************************************************************************
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//
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//! Clears reset reasons.
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//!
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//! \param rstCauses are the reset causes to be cleared; must be a logical
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//! OR of \b SYSCTL_CAUSE_PORESETN, \b SYSCTL_CAUSE_XRSN,
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//! \b SYSCTL_CAUSE_CPU1WDRSN,\b SYSCTL_CAUSE_CPU1NMIWDRSN,
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//! \b SYSCTL_CAUSE_CPU1SYSRSN ,\b SYSCTL_CAUSE_CPU1SCCRESETN,
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//! \b SYSCTL_CAUSE_ECAT_RESET_OUT , \b SYSCTL_CAUSE_CPU1SIMRESET_CPURSN,
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//! \b SYSCTL_CAUSE_CMRSTCTLRESETREQ ,\b SYSCTL_CAUSE_CMVECTRESETN,
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//! \b SYSCTL_CAUSE_CMSYSRESETREQ,
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//! \b SYSCTL_CAUSE_CMNMIWDRSN and/or \b SYSCTL_CAUSE_CMEOLRESETN.
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//!
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//! This function clears the specified sticky reset reasons. Once cleared,
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//! another reset for the same reason can be detected, and a reset for a
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//! different reason can be distinguished (instead of having two reset causes
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//! set). If the reset reason is used by an application, all reset causes
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//! should be cleared after they are retrieved with SysCtl_getResetCause().
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//!
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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SysCtl_clearResetCause(uint32_t rstCauses)
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{
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//
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// Clear the given reset reasons.
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//
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HWREG(CMSYSCTL_BASE + SYSCTL_O_CMRESCCLR) = rstCauses;
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}
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//*****************************************************************************
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//
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//! Disables the watchdog.
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//!
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//! This function disables the watchdog timer. Note that the watchdog timer is
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//! enabled on reset.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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SysCtl_disableWatchdog(void)
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{
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//
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// Set the disable bit.
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//
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HWREGH(WD_BASE + WWD_O_WDCR) |= SYSCTL_WD_CHKBITS | WWD_WDCR_WDDIS;
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}
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//*****************************************************************************
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//
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//! Enables the watchdog.
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//!
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//! This function enables the watchdog timer. Note that the watchdog timer is
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//! enabled on reset.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_enableWatchdog(void)
|
|
{
|
|
|
|
//
|
|
// Clear the disable bit.
|
|
//
|
|
HWREGH(WD_BASE + WWD_O_WDCR) = (HWREGH(WD_BASE + WWD_O_WDCR) &
|
|
~WWD_WDCR_WDDIS) | SYSCTL_WD_CHKBITS;
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Services the watchdog.
|
|
//!
|
|
//! This function resets the watchdog.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_serviceWatchdog(void)
|
|
{
|
|
|
|
//
|
|
// Enable the counter to be reset and then reset it.
|
|
//
|
|
HWREGH(WD_BASE + WWD_O_WDKEY) = SYSCTL_WD_ENRSTKEY;
|
|
HWREGH(WD_BASE + WWD_O_WDKEY) = SYSCTL_WD_RSTKEY;
|
|
|
|
}
|
|
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets up watchdog clock (WDCLK) pre-divider.
|
|
//!
|
|
//! \param predivider is the value that configures the pre-divider.
|
|
//!
|
|
//! This function sets up the watchdog clock (WDCLK) pre-divider. There are two
|
|
//! dividers that scale INTOSC1 to WDCLK. The \e predivider parameter divides
|
|
//! INTOSC1 down to PREDIVCLK and the prescaler (set by the
|
|
//! SysCtl_setWatchdogPrescaler() function) divides PREDIVCLK down to WDCLK.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_setWatchdogPredivider(SysCtl_WDPredivider predivider)
|
|
{
|
|
uint16_t regVal;
|
|
|
|
regVal = (uint16_t)predivider | (uint16_t)SYSCTL_WD_CHKBITS;
|
|
|
|
//
|
|
// Write the predivider to the appropriate register.
|
|
//
|
|
HWREGH(WD_BASE + WWD_O_WDCR) = (HWREGH(WD_BASE + WWD_O_WDCR) &
|
|
~(WWD_WDCR_WDPRECLKDIV_M)) | regVal;
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets up watchdog clock (WDCLK) prescaler.
|
|
//!
|
|
//! \param prescaler is the value that configures the watchdog clock relative
|
|
//! to the value from the pre-divider.
|
|
//!
|
|
//! This function sets up the watchdog clock (WDCLK) prescaler. There are two
|
|
//! dividers that scale INTOSC1 to WDCLK. The predivider (set with the
|
|
//! SysCtl_setWatchdogPredivider() function) divides INTOSC1 down to PREDIVCLK
|
|
//! and the \e prescaler parameter divides PREDIVCLK down to WDCLK.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_setWatchdogPrescaler(SysCtl_WDPrescaler prescaler)
|
|
{
|
|
uint16_t regVal;
|
|
|
|
regVal = (uint16_t)prescaler | (uint16_t)SYSCTL_WD_CHKBITS;
|
|
|
|
//
|
|
// Write the prescaler to the appropriate register.
|
|
//
|
|
HWREGH(WD_BASE + WWD_O_WDCR) = (HWREGH(WD_BASE + WWD_O_WDCR) &
|
|
~(WWD_WDCR_WDPS_M)) | regVal;
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the watchdog counter value.
|
|
//!
|
|
//! \return Returns the current value of the 8-bit watchdog counter. If this
|
|
//! count value overflows, a watchdog output pulse is generated.
|
|
//
|
|
//*****************************************************************************
|
|
static inline uint16_t
|
|
SysCtl_getWatchdogCounterValue(void)
|
|
{
|
|
//
|
|
// Read and return the value of the watchdog counter.
|
|
//
|
|
return(HWREGH(WD_BASE + WWD_O_WDCNTR));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the watchdog status.
|
|
//!
|
|
//!This function returns the watchdog status.
|
|
//!This bit, if set, indicates a NMI was fired to CM4 from WWD.
|
|
//!This bit remains latched until the user writes a 1 to clear the condition.
|
|
//!Writes of 0 will be ignored.
|
|
//!
|
|
//! \return Returns \b true if the watchdog generated the NMI condition.
|
|
//
|
|
//*****************************************************************************
|
|
static inline bool
|
|
SysCtl_getWatchdogStatus(void)
|
|
{
|
|
//
|
|
// Read and return the status of the watchdog status flag.
|
|
//
|
|
return((HWREGH(WD_BASE + WWD_O_WDCR) & WWD_WDCR_WDFLG) != 0U);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears the watchdog status.
|
|
//!
|
|
//! This function clears the watchdog status. To check if it was set
|
|
//! first, see SysCtl_getWatchdogStatus().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_clearWatchdogStatus(void)
|
|
{
|
|
//
|
|
// Clears the status of the watchdog reset flag.
|
|
//
|
|
HWREGH(WD_BASE + WWD_O_WDCR) |= SYSCTL_WD_CHKBITS | WWD_WDCR_WDFLG;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Set the minimum threshold value for windowed watchdog
|
|
//!
|
|
//! \param value is the value to set the window threshold
|
|
//!
|
|
//! This function sets the minimum threshold value used to define the lower
|
|
//! limit of the windowed watchdog functionality.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_setWatchdogWindowValue(uint16_t value)
|
|
{
|
|
uint16_t clearvalue, wvalue;
|
|
uint32_t readval;
|
|
|
|
wvalue = value;
|
|
|
|
//
|
|
//Write will succeed only if a matching key value is written
|
|
//to the KEY field
|
|
// Clear the windowed value
|
|
//
|
|
readval = HWREGH(WD_BASE + WWD_O_WDWCR);
|
|
clearvalue = (uint16_t)readval;
|
|
clearvalue &= ~((uint16_t)WWD_WDWCR_MIN_M);
|
|
HWREG(WD_BASE + WWD_O_WDWCR) = (((uint32_t)SYSCTL_WWD_KEY << 16U) &
|
|
WWD_WDWCR_KEY_M) | clearvalue;
|
|
//
|
|
// Set the windowed value
|
|
//
|
|
wvalue &= (uint16_t)WWD_WDWCR_MIN_M;
|
|
HWREG(WD_BASE + WWD_O_WDWCR) |= ((((uint32_t)SYSCTL_WWD_KEY << 16U) &
|
|
WWD_WDWCR_KEY_M) | wvalue);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Read NMI interrupts.
|
|
//!
|
|
//! Read the current state of NMI interrupt.
|
|
//!
|
|
//! \return \b true if NMI interrupt is triggered, \b false if not.
|
|
//
|
|
//*****************************************************************************
|
|
static inline bool
|
|
SysCtl_getNMIStatus(void)
|
|
{
|
|
//
|
|
// Read and return the current value of the NMI flag register, masking out
|
|
// all but the NMI bit.
|
|
//
|
|
return((HWREGH(NMI_BASE + NMI_O_CMNMIFLG) & NMI_CMNMIFLG_NMIINT) != 0U);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Read NMI Flags.
|
|
//!
|
|
//! Read the current state of individual NMI interrupts
|
|
//!
|
|
//! \return Value of NMIFLG register. These defines are provided to decode
|
|
//! the value:
|
|
//! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt
|
|
//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure
|
|
//! - \b SYSCTL_NMI_MEMUNCERR - RAM, ROM Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error
|
|
//! - \b SYSCTL_NMI_MCANUNCERR -MCAN Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_WWDNMI- CM WWD
|
|
//! - \b SYSCTL_NMI_ECATNMI -EtherCAT reset out
|
|
//
|
|
//*****************************************************************************
|
|
static inline uint16_t
|
|
SysCtl_getNMIFlagStatus(void)
|
|
{
|
|
//
|
|
// Read and return the current value of the NMI flag register.
|
|
//
|
|
return(HWREGH(NMI_BASE + NMI_O_CMNMIFLG));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Check if the individual NMI interrupts are set.
|
|
//!
|
|
//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear.
|
|
//! The bit format of this parameter is same as of the NMIFLG register. These
|
|
//! defines are provided:
|
|
//! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt
|
|
//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure
|
|
//! - \b SYSCTL_NMI_MEMUNCERR -RAM, ROM Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error
|
|
//! - \b SYSCTL_NMI_MCANUNCERR -MCAN Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_WWDNMI- CM WWD
|
|
//! - \b SYSCTL_NMI_ECATNMI -EtherCAT reset out
|
|
//!
|
|
//! Check if interrupt flags corresponding to the passed in bit mask are
|
|
//! asserted.
|
|
//!
|
|
//! \return \b true if any of the NMI asked for in the parameter bit mask
|
|
//! is set. \b false if none of the NMI requested in the parameter bit mask are
|
|
//! set.
|
|
//
|
|
//*****************************************************************************
|
|
static inline bool
|
|
SysCtl_isNMIFlagSet(uint32_t nmiFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
// Make sure if reserved bits are not set in nmiFlags.
|
|
//
|
|
ASSERT((nmiFlags & ~(SYSCTL_NMI_NMIINT | SYSCTL_NMI_CLOCKFAIL |
|
|
SYSCTL_NMI_MEMUNCERR | SYSCTL_NMI_FLUNCERR |
|
|
SYSCTL_NMI_MCANUNCERR | SYSCTL_NMI_ECATNMI |
|
|
SYSCTL_NMI_WWDNMI)) == 0U);
|
|
|
|
//
|
|
// Read the flag register and return true if any of them are set.
|
|
//
|
|
return((HWREGH(NMI_BASE + NMI_O_CMNMIFLG) & nmiFlags) != 0U);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Function to clear individual NMI interrupts.
|
|
//!
|
|
//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear.
|
|
//! The bit format of this parameter is same as of the CMNMIFLG register. These
|
|
//! defines are provided:
|
|
//! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt
|
|
//! - \b SYSCTL_NMI_CLOCKFAIL -Clock Failure
|
|
//! - \b SYSCTL_NMI_MEMUNCERR - RAM, ROM Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error
|
|
//! - \b SYSCTL_NMI_MCANUNCERR -MCAN Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_WWDNMI- CM WWD
|
|
//! - \b SYSCTL_NMI_ECATNMI -EtherCAT reset out
|
|
//!
|
|
//! Clear NMI interrupt flags that correspond with the passed in bit mask.
|
|
//!
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_clearNMIStatus(uint32_t nmiFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
// Make sure if reserved bits are not set in nmiFlags.
|
|
//
|
|
ASSERT((nmiFlags & ~(SYSCTL_NMI_NMIINT | SYSCTL_NMI_CLOCKFAIL |
|
|
SYSCTL_NMI_MEMUNCERR | SYSCTL_NMI_FLUNCERR |
|
|
SYSCTL_NMI_MCANUNCERR | SYSCTL_NMI_ECATNMI |
|
|
SYSCTL_NMI_WWDNMI)) == 0U);
|
|
|
|
//
|
|
// Clear the individual flags
|
|
//
|
|
HWREG(NMI_BASE + NMI_O_CMNMIFLGCLR) = nmiFlags |
|
|
(((uint32_t)SYSCTL_CMNMIFLGCLR_KEY
|
|
<< 16U) & NMI_CMNMIFLGCLR_KEY_M);
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clear all the NMI Flags.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_clearAllNMIFlags(void)
|
|
{
|
|
uint32_t nmiFlags;
|
|
|
|
//
|
|
// Directly write to the clear register,
|
|
// clearing all the flags.
|
|
//
|
|
|
|
nmiFlags = ((uint32_t)SYSCTL_NMI_NMIINT | (uint32_t)SYSCTL_NMI_CLOCKFAIL |
|
|
(uint32_t)SYSCTL_NMI_MEMUNCERR | (uint32_t)SYSCTL_NMI_FLUNCERR |
|
|
(uint32_t)SYSCTL_NMI_MCANUNCERR | (uint32_t)SYSCTL_NMI_ECATNMI |
|
|
(uint32_t)SYSCTL_NMI_WWDNMI);
|
|
|
|
HWREG(NMI_BASE + NMI_O_CMNMIFLGCLR) = nmiFlags |
|
|
(((uint32_t)SYSCTL_CMNMIFLGCLR_KEY
|
|
<< 16U) & NMI_CMNMIFLGCLR_KEY_M);
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Function to force individual NMI interrupt fail flags
|
|
//!
|
|
//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear.
|
|
//! The bit format of this parameter is same as of the NMIFLG register. These
|
|
//! defines are provided:
|
|
//! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt
|
|
//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure
|
|
//! - \b SYSCTL_NMI_MEMUNCERR - RAM, ROM Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error
|
|
//! - \b SYSCTL_NMI_MCANUNCERR -MCAN Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_WWDNMI- CM WWD
|
|
//! - \b SYSCTL_NMI_ECATNMI -EtherCAT reset out
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_forceNMIFlags(uint32_t nmiFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
// Make sure if reserved bits are not set in nmiFlags.
|
|
//
|
|
ASSERT((nmiFlags & ~(SYSCTL_NMI_NMIINT | SYSCTL_NMI_CLOCKFAIL |
|
|
SYSCTL_NMI_MEMUNCERR | SYSCTL_NMI_FLUNCERR |
|
|
SYSCTL_NMI_MCANUNCERR | SYSCTL_NMI_ECATNMI |
|
|
SYSCTL_NMI_WWDNMI)) == 0U);
|
|
|
|
//
|
|
// Write to any of the fields will succeed only if right key appears on the
|
|
// KEY field.
|
|
// Set the Flags for the individual interrupts in the NMI flag
|
|
// force register
|
|
//
|
|
HWREG(NMI_BASE + NMI_O_CMNMIFLGFRC) |= (nmiFlags |
|
|
(((uint32_t)SYSCTL_CMNMIFLGFRC_KEY
|
|
<< 16U) & NMI_CMNMIFLGFRC_KEY_M));
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the NMI watchdog counter value.
|
|
//!
|
|
//! \b Note: The counter is clocked at the SYSCLKOUT rate.
|
|
//!
|
|
//! \return Returns the NMI watchdog counter register's current value.
|
|
//
|
|
//*****************************************************************************
|
|
static inline uint16_t
|
|
SysCtl_getNMIWatchdogCounter(void)
|
|
{
|
|
//
|
|
// Read and return the NMI watchdog counter register's value.
|
|
//
|
|
return(HWREGH(NMI_BASE + NMI_O_CMNMIWDCNT));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the NMI watchdog period value.
|
|
//!
|
|
//! \param wdPeriod is the 16-bit value at which a reset is generated.
|
|
//!
|
|
//! This function writes to the NMI watchdog period register that holds the
|
|
//! value to which the NMI watchdog counter is compared. When the two registers
|
|
//! match, a reset is generated. By default, the period is 0xFFFF.
|
|
//!
|
|
//! \note If a value smaller than the current counter value is passed into the
|
|
//! \e wdPeriod parameter, a NMIRSn will be forced.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_setNMIWatchdogPeriod(uint16_t wdPeriod)
|
|
{
|
|
|
|
//
|
|
// Write to the period register.
|
|
//
|
|
HWREG(NMI_BASE + NMI_O_CMNMIWDPRD) = (((uint32_t)SYSCTL_CMNMIWDPRD_KEY
|
|
<< 16U) & NMI_CMNMIWDPRD_KEY_M)
|
|
| wdPeriod ;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the NMI watchdog period value.
|
|
//!
|
|
//! \return Returns the NMI watchdog period register's current value.
|
|
//
|
|
//*****************************************************************************
|
|
static inline uint16_t
|
|
SysCtl_getNMIWatchdogPeriod(void)
|
|
{
|
|
//
|
|
// Read and return the NMI watchdog period register's value.
|
|
//
|
|
return(HWREGH(NMI_BASE + NMI_O_CMNMIWDPRD));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Read NMI Shadow Flags.
|
|
//!
|
|
//! Read the current state of individual NMI interrupts
|
|
//!
|
|
//! \return Value of CMNMISHDFLG register. These defines are provided to decode
|
|
//! the value:
|
|
//! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt
|
|
//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure
|
|
//! - \b SYSCTL_NMI_MEMUNCERR - RAM, ROM Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error
|
|
//! - \b SYSCTL_NMI_MCANUNCERR -MCAN Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_WWDNMI- CM WWD
|
|
//! - \b SYSCTL_NMI_ECATNMI -EtherCAT reset out
|
|
//
|
|
//*****************************************************************************
|
|
static inline uint16_t
|
|
SysCtl_getNMIShadowFlagStatus(void)
|
|
{
|
|
//
|
|
// Read and return the current value of the NMI shadow flag register.
|
|
//
|
|
return(HWREGH(NMI_BASE + NMI_O_CMNMISHDWFLG));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Check if the individual NMI shadow flags are set.
|
|
//!
|
|
//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear.
|
|
//! The bit format of this parameter is same as of the CMNMIFLG register. These
|
|
//! defines are provided:
|
|
//! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt
|
|
//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure
|
|
//! - \b SYSCTL_NMI_MEMUNCERR - RAM, ROM Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error
|
|
//! - \b SYSCTL_NMI_MCANUNCERR -MCAN Uncorrectable Error
|
|
//! - \b SYSCTL_NMI_WWDNMI- CM WWD
|
|
//! - \b SYSCTL_NMI_ECATNMI -EtherCAT reset out
|
|
//!
|
|
//! Check if interrupt flags corresponding to the passed in bit mask are
|
|
//! asserted.
|
|
//!
|
|
//! \return \b true if any of the NMI asked for in the parameter bit mask
|
|
//! is set. \b false if none of the NMI requested in the parameter bit mask are
|
|
//! set.
|
|
//
|
|
//*****************************************************************************
|
|
static inline bool
|
|
SysCtl_isNMIShadowFlagSet(uint32_t nmiFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
// Make sure if reserved bits are not set in nmiFlags.
|
|
//
|
|
ASSERT((nmiFlags & ~(SYSCTL_NMI_NMIINT | SYSCTL_NMI_CLOCKFAIL |
|
|
SYSCTL_NMI_MEMUNCERR | SYSCTL_NMI_FLUNCERR |
|
|
SYSCTL_NMI_MCANUNCERR | SYSCTL_NMI_ECATNMI |
|
|
SYSCTL_NMI_WWDNMI)) == 0U);
|
|
|
|
|
|
//
|
|
// Read the flag register and return true if any of them are set.
|
|
//
|
|
return((HWREGH(NMI_BASE + NMI_O_CMNMISHDWFLG) & nmiFlags) != 0U);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Blocks writes to the CM System control registers
|
|
//!
|
|
//! \param controlreg is the Control Register whose access is blocked.
|
|
//! SYSCTL_CMECATCTL_LOCK is for the CMECATCTL register
|
|
//!
|
|
//! This function locks the configuration registers of CM System Control
|
|
//! register.
|
|
//!
|
|
//!\b Note: Today only writes to the CMECATCTL register are blocked .
|
|
//!\b Writes to CMECATCTL register is unblocked on reset .
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_lockAccessControlRegs(uint16_t controlreg)
|
|
{
|
|
HWREGH(CMSYSCTL_BASE + SYSCTL_O_CMSYSCTLLOCK) = controlreg;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//! Puts the processor into sleep mode.
|
|
//!
|
|
//! This function places the processor into sleep mode
|
|
//!
|
|
//! \return None.
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_sleep(void)
|
|
{
|
|
//
|
|
// Wait for an interrupt.
|
|
//
|
|
CPU_wfi();
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enable the Global NMI
|
|
//!
|
|
//! This function writes to the NMI configuration register that enables the
|
|
//! global NMI.
|
|
//!
|
|
//! \note Global NMI is disabled on reset
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
SysCtl_enableGlobalNMI(void)
|
|
{
|
|
|
|
//
|
|
// Write to the NMI config register to enable global NMI.
|
|
//
|
|
HWREG(NMI_BASE + NMI_O_CMNMICFG) = (((uint32_t)SYSCTL_CMNMICFG_KEY << 16U) &
|
|
NMI_CMNMICFG_KEY_M) | SYSCTL_NMI_GLOBAL;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Check if the Watchdog First Valid Key Detect Flag is set or not.
|
|
//!
|
|
//! \return \b true if the First Valid key after non-zero MIN configuration
|
|
//! got detected \b false if the First Valid Key after non-zero MIN
|
|
//! configuration has not happened
|
|
//
|
|
//*****************************************************************************
|
|
|
|
static inline bool
|
|
SysCtl_isWatchdogFirstKeyDetectFlagset(void)
|
|
{
|
|
//
|
|
// Read the First Valid Key Detect and return true if set.
|
|
//
|
|
return((HWREGH(WD_BASE + WWD_O_WDWCR) & WWD_WDWCR_FIRSTKEY) != 0U);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Check if the MCAN wakeup event has occured.
|
|
//!
|
|
//! \return \b true if the MCAN wakeup event has occured.
|
|
//! \b false if the MCAN wakeup event has not occured.
|
|
//
|
|
//*****************************************************************************
|
|
|
|
static inline bool
|
|
SysCtl_isMCANWakeStatusSet(void)
|
|
{
|
|
//
|
|
// Read the MCAN wakeup event status and return true if set.
|
|
//
|
|
return((HWREGH(CMSYSCTL_BASE + SYSCTL_O_MCANWAKESTATUS) &
|
|
SYSCTL_MCANWAKESTATUS_WAKE) != 0U);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears the MCAN wakeup event status.
|
|
//!
|
|
//! This function clears the MCAN wakeup event status. To check if it was set
|
|
//! first, see SysCtl_isMCANWakeStatusSet().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
|
|
static inline void
|
|
SysCtl_clearMCANWakeStatus(void)
|
|
{
|
|
//
|
|
// Clear the MCAN wakeup event status
|
|
//
|
|
HWREGH(CMSYSCTL_BASE +
|
|
SYSCTL_O_MCANWAKESTATUSCLR) |= SYSCTL_MCANWAKESTATUSCLR_WAKE ;
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Delays for a fixed number of cycles.
|
|
//!
|
|
//! \param count is the number of delay loop iterations to perform.
|
|
//!
|
|
//! This function generates a constant length delay using assembly code. The
|
|
//! loop takes around 6 cycles per iteration plus 9 cycles of overhead.
|
|
//!
|
|
//! It is important to note that this function is a fairly accurate
|
|
//! timing mechanism. Although the delay loop is deterministic,
|
|
//! the execution time of the loop will vary dramatically depending upon the
|
|
//! application's interrupt environment (the loop will be interrupted unless
|
|
//! run with interrupts disabled and this is generally an unwise thing to do)
|
|
//! and also the current system clock rate and flash timings (wait states and
|
|
//! the operation of the prefetch buffer affect the timing).
|
|
//!
|
|
//! For best accuracy, a system timer should be used with code either polling
|
|
//! for a particular timer value being exceeded or processing the timer
|
|
//! interrupt to determine when a particular time period has elapsed.
|
|
//!
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
|
|
extern void
|
|
SysCtl_delay(uint32_t count);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Resets a peripheral
|
|
//!
|
|
//! \param peripheral is the peripheral to reset.
|
|
//!
|
|
//! This function uses the SOFTPRESx registers to reset a specified peripheral.
|
|
//! Module registers will be returned to their reset states.
|
|
//!
|
|
//! \note This includes registers containing trim values.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
extern void
|
|
SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral);
|
|
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables a peripheral.
|
|
//!
|
|
//! \param peripheral is the peripheral to enable.
|
|
//!
|
|
//! Peripherals are enabled with this function. At power-up, all peripherals
|
|
//! are disabled; they must be enabled in order to operate or respond to
|
|
//! register reads/writes.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
extern void
|
|
SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables a peripheral.
|
|
//!
|
|
//! \param peripheral is the peripheral to disable.
|
|
//!
|
|
//! Peripherals are disabled with this function. Once disabled, they will not
|
|
//! operate or respond to register reads/writes.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
extern void
|
|
SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Request to stop the clock to a Peripheral.
|
|
//!
|
|
//! \param peripheral is the peripheral to which the Stop clock request
|
|
//! is sent.
|
|
//! \param enable is the value to be written to the Clk stop request register.
|
|
//! This can take values of either 1U(enable) or 0U(disable).
|
|
//!
|
|
//! Once set, this bit is cleared either explicitly by passing a 0U to the API
|
|
//! or when clock to peripheral is turned on as a result of a wakeup event in
|
|
//! hardware
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
extern void
|
|
SysCtl_requestPeripheralClockStop(SysCtl_PeripheralCMCLKSTOPREQ peripheral,
|
|
uint16_t enable);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Check if request to stop the clock to a Peripheral is Acked or Not.
|
|
//!
|
|
//! \param peripheral is the peripheral which acked the Stop clock Req or not .
|
|
//!
|
|
//! \return \b true if the peripheral acked the Stop clock Request
|
|
//! \b false if peripheral did not ack the Stop clock Request
|
|
//
|
|
//*****************************************************************************
|
|
extern bool
|
|
SysCtl_isPeripheralClockStopAcked(SysCtl_PeripheralCMCLKSTOPACK peripheral);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the value of the Peripheral clock Stop register.
|
|
//!
|
|
//! \param peripheral is the peripheral to which the Stop clock request
|
|
//! is sent.
|
|
//!
|
|
//! \return Value of CMCLKSTOPREQ register.
|
|
//
|
|
//*****************************************************************************
|
|
extern uint16_t
|
|
SysCtl_getPeripheralClockStop(SysCtl_PeripheralCMCLKSTOPREQ peripheral);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//****************************************************************************
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Mark the end of the C bindings section for C++ compilers.
|
|
//
|
|
//*****************************************************************************
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // __SYSCTL_H__
|