fix: проверен и работает с ПЧ2П rev.1$ ECAT порты - справа
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@ -1,7 +1,7 @@
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******************************************************************************
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TI ARM Linker PC v20.2.7
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******************************************************************************
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>> Linked Thu Nov 28 09:33:18 2024
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>> Linked Thu Nov 28 11:24:21 2024
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OUTPUT FILE NAME: <f2838x_cm_cia402_solution.out>
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ENTRY POINT SYMBOL: "_c_int00_noargs" address: 20007ff1
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File diff suppressed because it is too large
Load Diff
@ -1015,8 +1015,8 @@ void MainLoop(void)
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/* FreeRun-Mode: bEscIntEnabled = FALSE, bDcSyncActive = FALSE
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Synchron-Mode: bEscIntEnabled = TRUE, bDcSyncActive = FALSE
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DC-Mode: bEscIntEnabled = TRUE, bDcSyncActive = TRUE */
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Synchron-Mode: bEscIntEnabled = TRUE, bDcSyncActive = FALSE
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DC-Mode: bEscIntEnabled = TRUE, bDcSyncActive = TRUE */
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if (
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(!bEscIntEnabled || !bEcatFirstOutputsReceived) /* SM-Synchronous, but not SM-event received */
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/*ET9300 Project Handler :(#if MAX_PD_OUTPUT_SIZE > 0 #else) lines 1422 to 1424 deleted*/
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262
sysctl.c
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262
sysctl.c
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@ -0,0 +1,262 @@
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//###########################################################################
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//
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// FILE: sysctl.c
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//
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// TITLE: CM system control driver.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#include "sysctl.h"
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//*****************************************************************************
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//
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// SysCtl_delay()
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//
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//*****************************************************************************
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//
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//SYSCTL_DELAY define for delay of fixed cycles.
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//
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SYSCTL_DELAY
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//*****************************************************************************
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//
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// Prototypes for the APIs.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// SysCtl_resetPeripheral()
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//
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//*****************************************************************************
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void
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SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral)
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{
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uint16_t regIndex;
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uint16_t bitIndex;
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uint32_t clearvalue;
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//
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// Decode the peripheral variable.
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//
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regIndex = (uint16_t)4U * ((uint16_t)peripheral &
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(uint16_t)SYSCTL_PERIPH_REG_M);
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bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >>
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SYSCTL_PERIPH_BIT_S;
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//
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//Write will succeed only if a matching key value is written
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//to the KEY field
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//Sets the appropriate reset bit and then clears it.
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//
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HWREG(CMSYSCTL_BASE + SYSCTL_O_CMSOFTPRESET0 + regIndex) |=
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(((uint32_t)1U << bitIndex) |
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(((uint32_t)SYSCTL_CMSYSCTL_KEY << 16U ) &
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SYSCTL_CMSOFTPRESET0_KEY_M));
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clearvalue = HWREG(CMSYSCTL_BASE + SYSCTL_O_CMSOFTPRESET0 + regIndex);
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clearvalue &= ~((uint32_t)1U << bitIndex);
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HWREG(CMSYSCTL_BASE + SYSCTL_O_CMSOFTPRESET0 + regIndex) =
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(((uint32_t)SYSCTL_CMSYSCTL_KEY << 16U) &
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SYSCTL_CMPCLKCR0_KEY_M) | clearvalue;
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}
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//*****************************************************************************
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//
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// SysCtl_enablePeripheral()
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//
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//*****************************************************************************
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void
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SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral)
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{
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uint16_t regIndex;
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uint16_t bitIndex;
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//
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// Decode the peripheral variable.
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//
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regIndex = (uint16_t)4U * ((uint16_t)peripheral &
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(uint16_t)SYSCTL_PERIPH_REG_M);
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bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >>
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SYSCTL_PERIPH_BIT_S;
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//
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// Write will succeed only if a matching key value is written to
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// the KEY field
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// Turn on the module clock.
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//
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HWREG(CMSYSCTL_BASE + SYSCTL_O_CMPCLKCR0 + regIndex) |=
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(((uint32_t)1U << bitIndex) |
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(((uint32_t)SYSCTL_CMSYSCTL_KEY << 16U ) &
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SYSCTL_CMPCLKCR0_KEY_M));
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}
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//*****************************************************************************
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//
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// SysCtl_disablePeripheral()
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//
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//*****************************************************************************
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void
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SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral)
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{
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uint16_t regIndex;
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uint16_t bitIndex;
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uint32_t clearvalue;
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//
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// Decode the peripheral variable.
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//
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regIndex = (uint16_t)4U * ((uint16_t)peripheral &
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(uint16_t)SYSCTL_PERIPH_REG_M);
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bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >>
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SYSCTL_PERIPH_BIT_S;
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//
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//Write will succeed only if a matching key value is written
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// to the KEY field
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// Turn off the module clock.
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//
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clearvalue = HWREG(CMSYSCTL_BASE + SYSCTL_O_CMPCLKCR0 + regIndex);
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clearvalue &= ~((uint32_t)1U << bitIndex);
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HWREG(CMSYSCTL_BASE + SYSCTL_O_CMPCLKCR0 + regIndex) =
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(((uint32_t)SYSCTL_CMSYSCTL_KEY << 16U) &
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SYSCTL_CMPCLKCR0_KEY_M) | clearvalue;
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}
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//*****************************************************************************
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//
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// SysCtl_requestPeripheralClockStop()
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//
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//*****************************************************************************
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void
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SysCtl_requestPeripheralClockStop(SysCtl_PeripheralCMCLKSTOPREQ peripheral,
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uint16_t enable)
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{
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uint16_t regIndex;
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uint16_t bitIndex;
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uint32_t clearvalue;
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//
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// Decode the peripheral variable.
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//
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regIndex = (uint16_t)4U * ((uint16_t)peripheral &
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(uint16_t)SYSCTL_PERIPH_REG_M);
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bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >>
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SYSCTL_PERIPH_BIT_S;
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//
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//Write will succeed only if a matching key value is written
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//to the KEY field
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// Request to stop the clock
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//
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if(enable == 1U) //enable the peripheral clock Stop
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{
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HWREG(CMSYSCTL_BASE + SYSCTL_O_CMCLKSTOPREQ0 + regIndex) |=
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(((uint32_t)1U << bitIndex) |
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(((uint32_t)SYSCTL_CMSYSCTL_KEY << 16U) &
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SYSCTL_CMCLKSTOPREQ0_KEY_M));
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}
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else //disable the peripheral clock Stop
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{
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clearvalue = HWREG(CMSYSCTL_BASE + SYSCTL_O_CMCLKSTOPREQ0 + regIndex);
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clearvalue &= ~((uint32_t)1U << bitIndex);
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HWREG(CMSYSCTL_BASE + SYSCTL_O_CMCLKSTOPREQ0 + regIndex) =
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(((uint32_t)SYSCTL_CMSYSCTL_KEY << 16U) &
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SYSCTL_CMCLKSTOPREQ0_KEY_M) | clearvalue;
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}
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}
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//*****************************************************************************
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//
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// SysCtl_isPeripheralClockStopAcked()
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//
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//*****************************************************************************
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bool
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SysCtl_isPeripheralClockStopAcked(SysCtl_PeripheralCMCLKSTOPACK peripheral)
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{
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uint16_t regIndex;
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uint16_t bitIndex;
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//
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// Decode the peripheral variable.
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//
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regIndex = (uint16_t)4U * ((uint16_t)peripheral &
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(uint16_t)SYSCTL_PERIPH_REG_M);
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bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >>
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SYSCTL_PERIPH_BIT_S;
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//
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// Read the register and return true if the clk stop Req is acked or not.
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//
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return((HWREGH(CMSYSCTL_BASE + SYSCTL_O_CMCLKSTOPACK1 + regIndex) &
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((uint32_t)1U << bitIndex)) != 0U);
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}
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//*****************************************************************************
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//
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// SysCtl_getPeripheralClockStop()
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//
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//*****************************************************************************
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uint16_t
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SysCtl_getPeripheralClockStop(SysCtl_PeripheralCMCLKSTOPREQ peripheral)
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{
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uint16_t regIndex;
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//
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// Decode the peripheral variable.
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//
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regIndex = (uint16_t)4U * ((uint16_t)peripheral &
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(uint16_t)SYSCTL_PERIPH_REG_M);
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//
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// Read the register and return the value of clk stop Req
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//
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return(HWREGH(CMSYSCTL_BASE + SYSCTL_O_CMCLKSTOPREQ0 + regIndex));
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}
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