528 lines
13 KiB
C
528 lines
13 KiB
C
/*
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* spi_init.c
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*
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* Created on: 5 ñåíò. 2023 ã.
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* Author: seklyuts
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*/
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#include "f28x_project.h"
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#include "biss.h"
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#define SPI_PROGRAM_CS_GPAMUX1 GpioCtrlRegs.GPDMUX1.bit.GPIO98
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#define SPI_PROGRAM_CS_GPAGMUX1 GpioCtrlRegs.GPDGMUX1.bit.GPIO98
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#define SPI_PROGRAM_CS_GPADIR GpioCtrlRegs.GPDDIR.bit.GPIO98
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#define SPI_PROGRAM_CS_GPADAT GpioDataRegs.GPDDAT.bit.GPIO98
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uint16_t BissCount = BISS_C_BITS;
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__interrupt void spia_rx_isr(void);
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__interrupt void spia_tx_isr(void);
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__interrupt void spib_rx_isr(void);
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__interrupt void spib_tx_isr(void);
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__interrupt void spic_rx_isr(void);
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__interrupt void spic_tx_isr(void);
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uint16_t rxBuff[BISS_C_BITS];
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uint16_t indexRxBuff = 0;
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void SpiAInit(void)
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{
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//
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// Initialize SPI-A
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//
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//
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// Initialize SPI FIFO registers
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//
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CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
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SpiaRegs.SPIFFTX.all = 0xE040;
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SpiaRegs.SPIFFRX.all = 0x2044;
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SpiaRegs.SPIFFCT.all = 0x0;
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//
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// Initialize core SPI registers
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//
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//
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// Set reset low before configuration changes
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// Clock polarity (0 == rising, 1 == falling)
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// 16-bit character
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// Enable loop-back
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//
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SpiaRegs.SPICCR.bit.SPISWRESET = 0;
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SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
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SpiaRegs.SPICCR.bit.SPICHAR = (8 - 1);
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SpiaRegs.SPICCR.bit.SPILBK = 0;
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//
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// Enable master (0 == slave, 1 == master)
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// Enable transmission (Talk)
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// Clock phase (0 == normal, 1 == delayed)
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// SPI interrupts are disabled
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//
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SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
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SpiaRegs.SPICTL.bit.TALK = 1;
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SpiaRegs.SPICTL.bit.CLK_PHASE = 1;
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SpiaRegs.SPICTL.bit.SPIINTENA = 0;
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PieCtrlRegs.PIEIER6.bit.INTx1 = 0;
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PieCtrlRegs.PIEIER6.bit.INTx2 = 0;
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PieVectTable.SPIA_RX_INT = &spia_rx_isr;
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PieVectTable.SPIA_TX_INT = &spia_tx_isr;
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//
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// Set the baud rate using a 1 MHz SPICLK
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// BRR = (LSPCLK / SPICLK) - 1
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//
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SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = ((50000000 / 1000000) - 1);
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// Set FREE bit
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// Halting on a breakpoint will not halt the SPI
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//
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SpiaRegs.SPIPRI.bit.FREE = 1;
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//
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// Release the SPI from reset
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//
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SpiaRegs.SPICCR.bit.SPISWRESET = 1;
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}
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void SpiAGpioInit(void)
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{
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EALLOW;
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//
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// Enable internal pull-up for the selected pins
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//
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// Pull-ups can be enabled or disabled by the user.
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// This will enable the pullups for the specified pins.
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//
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GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on (SPISIMOA)
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GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on (SPISOMIA)
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GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on (SPICLKA)
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GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up on (SPISTEA)
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//
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// Set qualification for selected pins to asynch only
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//
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// This will select asynch (no qualification) for the selected pins.
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//
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GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input (SPISIMOA)
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GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input (SPISOMIA)
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GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3; // Asynch input (SPICLKA)
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GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 3; // Asynch input (SPISTEA)
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//
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// Configure SPI-A pins
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//
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// This specifies which of the possible GPIO pins will be SPI functional
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// pins.
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//
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GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 3; // Configure GPIO32 as SPISIMOA
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GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 3; // Configure GPIO33 as SPISOMIA
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GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // Configure GPIO34 as SPICLKA
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GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA
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SPI_PROGRAM_CS_GPAMUX1 = 0;//program CS for BL25CM1A
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SPI_PROGRAM_CS_GPAGMUX1 = 0;
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SPI_PROGRAM_CS_GPADIR = 1;
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SPI_PROGRAM_CS_GPADAT = 0;
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EDIS;
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}
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void spi_TurnOnCS1_GD25Q16E(void)
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{
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EALLOW;
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GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA
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EDIS;
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}
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void spi_TurnOffCS1_GD25Q16E(void)
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{
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EALLOW;
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GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0;
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GpioDataRegs.GPBDAT.bit.GPIO35 = 1;
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EDIS;
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}
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void Gpio_SPI_CS_BL25CM1A(uint16_t out_bit)
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{
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EALLOW;
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SPI_PROGRAM_CS_GPADAT = out_bit;
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EDIS;
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}
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void spi_transmitAData(uint16_t a)
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{
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SpiaRegs.SPITXBUF = a<<8;
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}
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__interrupt void spia_rx_isr(void)
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{
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uint16_t temp = SpiaRegs.SPISTS.all;
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
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}
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__interrupt void spia_tx_isr(void)
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{
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uint16_t temp = SpiaRegs.SPISTS.all;
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
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}
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void SpiBInit(void)
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{
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CpuSysRegs.PCLKCR8.bit.SPI_B = 1;
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SpibRegs.SPIFFTX.all = 0xE04F;
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SpibRegs.SPIFFRX.all = 0x2026;//RXFIFORESET = 1; RXFFINTCLR = 1; RXFFIENA = 1; RXFFIL = 6
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SpibRegs.SPIFFCT.all = 0x0;
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//
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// Initialize core SPI registers
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//
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//
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// Set reset low before configuration changes
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// Clock polarity (0 == rising, 1 == falling)
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// 16-bit character
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// Enable loop-back
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//
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SpibRegs.SPICCR.bit.SPISWRESET = 0;
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SpibRegs.SPICCR.bit.CLKPOLARITY = 0;
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SpibRegs.SPICCR.bit.SPICHAR = 0xF; //16
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SpibRegs.SPICCR.bit.SPILBK = 0;
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SpibRegs.SPICCR.bit.HS_MODE = 1;
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//
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// Enable master (0 == slave, 1 == master)
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// Enable transmission (Talk)
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// Clock phase (0 == normal, 1 == delayed)
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// SPI interrupts are enabled
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//
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SpibRegs.SPICTL.bit.MASTER_SLAVE = 0;//Slave
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SpibRegs.SPICTL.bit.TALK = 1;
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SpibRegs.SPICTL.bit.CLK_PHASE = 1;
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SpibRegs.SPICTL.bit.SPIINTENA = 1;
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EALLOW;
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PieVectTable.SPIB_RX_INT = &spib_rx_isr;
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PieVectTable.SPIB_TX_INT = &spib_tx_isr;
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EDIS;
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IER |= M_INT6;
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PieCtrlRegs.PIEIER6.bit.INTx3 = 1; //3.4.5 PIE Channel Mapping str 150 of trm
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PieCtrlRegs.PIEIER6.bit.INTx4 = 1; // 3 - RX, 4 - TX
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SpibRegs.SPIFFTX.bit.TXFFIENA = 0;
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SpibRegs.SPIFFRX.bit.RXFFIENA = 1;
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//
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// Set the baud rate using a 1 MHz SPICLK
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// BRR = (LSPCLK / SPICLK) - 1
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//
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SpibRegs.SPIBRR.bit.SPI_BIT_RATE = ((50000000 / 1000000) - 1);
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// Set FREE bit
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// Halting on a breakpoint will not halt the SPI
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//
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SpibRegs.SPIPRI.bit.FREE = 1;
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//
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// Release the SPI from reset
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//
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SpibRegs.SPICCR.bit.SPISWRESET = 1;
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}
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void SpiBGpioInit(void)
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{
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EALLOW;
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//
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// Enable internal pull-up for the selected pins
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//
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// Pull-ups can be enabled or disabled by the user.
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// This will enable the pullups for the specified pins.
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//
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GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on GPIO16 (SPISIMOB)
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// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO17 (SPISOMIB)
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GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on GPIO18 (SPICLKB)
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// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO18 (SPICLKB)
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GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO19 (SPISTEB)
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//
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// Set qualification for selected pins to asynch only
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//
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// This will select asynch (no qualification) for the selected pins.
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//
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GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input GPIO16 (SPISIMOB)
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// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO17 (SPISOMIB)
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GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input GPIO18 (SPICLKB)
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// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO18 (SPICLKB)
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GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO19 (SPISTEB)
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GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;
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GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0;
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GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1;
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GpioDataRegs.GPDDAT.bit.GPIO99 = 0;
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//
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// Configure SPI-A pins
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//
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// This specifies which of the possible GPIO pins will be SPI functional
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// pins.
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//
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GPIO_SetupPinMux(100, 0, 6);
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// GPIO_SetupPinMux(25, 0, 6);
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GPIO_SetupPinMux(102, 0, 6);
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// GPIO_SetupPinMux(26, 0, 6);
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GPIO_SetupPinMux(27, 0, 6);
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// SpibRegs.SPITXBUF = 0xFFFF;
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// GpioCtrlRegs.GPAMUX1.bit.GPIO24 = 2; // Configure GPIO16 as SPISIMOA
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// GpioCtrlRegs.GPAMUX1.bit.GPIO25 = 2; // Configure GPIO17 as SPISOMIA
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// GpioCtrlRegs.GPAMUX1.bit.GPIO26 = 2; // Configure GPIO18 as SPICLKA
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// GpioCtrlRegs.GPAMUX1.bit.GPIO27 = 2; // Configure GPIO19 as SPISTEA
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// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO16 as SPISIMOA
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// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO17 as SPISOMIA
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// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO18 as SPICLKA
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// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO19 as SPISTEA
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EDIS;
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}
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void transmitBData(uint16_t a)
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{
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SpibRegs.SPITXBUF = a;
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}
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__interrupt void spib_rx_isr(void)
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{
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// SpibRegs.SPIFFRX.all = 0x2036;//RXFIFORESET = 1; RXFFINTCLR = 1; RXFFIENA = 1; RXFFIL = 6
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uint16_t temp = SpibRegs.SPISTS.all;
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
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SpibRegs.SPIFFRX.bit.RXFFIL = 6;
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SpibRegs.SPIFFRX.bit.RXFFIENA = 1;
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SpibRegs.SPIFFRX.bit.RXFFINTCLR = 1;
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}
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__interrupt void spib_tx_isr(void)
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{
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uint16_t temp = SpibRegs.SPISTS.all;
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
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SpibRegs.SPIFFTX.all = 0xE04F;
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SpibRegs.SPIFFTX.bit.TXFFIL = 0x0;
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// SpibRegs.SPIFFTX.bit.TXFFIENA = 1;
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SpibRegs.SPIFFTX.bit.TXFFINTCLR = 1;
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}
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//Spi-C
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void SpiCInit(void)
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{
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CpuSysRegs.PCLKCR8.bit.SPI_C = 1;
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SpicRegs.SPIFFTX.all = 0xE04F;
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SpicRegs.SPIFFRX.all = 0x2026;//RXFIFORESET = 1; RXFFINTCLR = 1; RXFFIENA = 1; RXFFIL = 6
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SpicRegs.SPIFFCT.all = 0x0;
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SpicRegs.SPIFFRX.bit.RXFFIL = BissCount;
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//
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// Initialize core SPI registers
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//
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//
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// Set reset low before configuration changes
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// Clock polarity (0 == rising, 1 == falling)
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// 16-bit character
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// Enable loop-back
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//
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SpicRegs.SPICCR.bit.SPISWRESET = 0;
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SpicRegs.SPICCR.bit.CLKPOLARITY = BISS_CLK_POL;
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SpicRegs.SPICCR.bit.SPICHAR = 0xF; //16
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SpicRegs.SPICCR.bit.SPILBK = 0;
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SpicRegs.SPICCR.bit.HS_MODE = 1;
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//
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// Enable master (0 == slave, 1 == master)
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// Enable transmission (Talk)
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// Clock phase (0 == normal, 1 == delayed)
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// SPI interrupts are enabled
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//
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SpicRegs.SPICTL.bit.MASTER_SLAVE = 0;//Slave
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SpicRegs.SPICTL.bit.TALK = 1;
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SpicRegs.SPICTL.bit.CLK_PHASE = BISS_CLK_PHASE;
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SpicRegs.SPICTL.bit.SPIINTENA = 1;
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EALLOW;
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PieVectTable.SPIC_RX_INT = &spic_rx_isr;
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PieVectTable.SPIC_TX_INT = &spic_tx_isr;
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EDIS;
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IER |= M_INT6;
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PieCtrlRegs.PIEIER6.bit.INTx9 = 1; //3.4.5 PIE Channel Mapping str 150 of trm
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PieCtrlRegs.PIEIER6.bit.INTx10 = 1; // 3 - RX, 4 - TX
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SpicRegs.SPIFFTX.bit.TXFFIENA = 0;
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SpicRegs.SPIFFRX.bit.RXFFIENA = 1;
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//
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// Set the baud rate using a 1 MHz SPICLK
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// BRR = (LSPCLK / SPICLK) - 1
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//
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SpicRegs.SPIBRR.bit.SPI_BIT_RATE = ((50000000 / 1000000) - 1);
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// Set FREE bit
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// Halting on a breakpoint will not halt the SPI
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//
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SpicRegs.SPIPRI.bit.FREE = 1;
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SpicRegs.SPIPRI.bit.STEINV = 1;
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//
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// Release the SPI from reset
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//
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SpicRegs.SPICCR.bit.SPISWRESET = 1;
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}
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void SpiCGpioInit(void)
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{
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EALLOW;
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//
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// Enable internal pull-up for the selected pins
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//
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// Pull-ups can be enabled or disabled by the user.
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// This will enable the pullups for the specified pins.
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//
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GpioCtrlRegs.GPDPUD.bit.GPIO100 = 0; // Enable pull-up on (SPISIMOB)
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GpioCtrlRegs.GPDPUD.bit.GPIO102 = 0; // Enable pull-up on (SPICLKB)
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GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0; // Enable pull-up on (SPISTEB)
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//
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// Set qualification for selected pins to asynch only
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//
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// This will select asynch (no qualification) for the selected pins.
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//
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GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 3; // Asynch input(SPISIMOB)
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GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 3; // Asynch input(SPICLKB)
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GpioCtrlRegs.GPCQSEL1.bit.GPIO72 = 3; // Asynch input(SPISTEB)
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GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;
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GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 0;
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GpioCtrlRegs.GPDDIR.bit.GPIO99 = 1;
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GpioDataRegs.GPDDAT.bit.GPIO99 = 0;
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//
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// Configure SPI-A pins
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//
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// This specifies which of the possible GPIO pins will be SPI functional
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// pins.
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//
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GPIO_SetupPinMux(100, 0, 6);
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GPIO_SetupPinMux(102, 0, 6);
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GPIO_SetupPinMux(72, 0, 15);
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EDIS;
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}
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void transmitCData(uint16_t a)
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{
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SpicRegs.SPITXBUF = a;
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}
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void resetIndexRxBuff(void)
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{
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indexRxBuff = 0;
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}
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uint64_t BissTest = 0;
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uint16_t BissErrRead = 0;
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uint32_t BissTestShift0[16];
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__interrupt void spic_rx_isr(void)
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{
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uint16_t BissEmptyBits = 0;
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for(indexRxBuff = 0; indexRxBuff < BissCount; indexRxBuff++)
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{
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rxBuff[indexRxBuff] = SpicRegs.SPIRXBUF;
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}
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BissTest = ((uint64_t)rxBuff[0] << 48) + ((uint64_t)rxBuff[1] << 32) + ((uint64_t)rxBuff[2] << 16) + ((uint64_t)rxBuff[3]);
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while(((BissTest & 0xC000000000000000) != 0x8000000000000000) && (BissEmptyBits < 15))
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{
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BissTest = BissTest << 1;
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BissEmptyBits++;
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}
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BissTestShift0[BissEmptyBits]++;
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if( (BissTest & 0xC000000000000000) == 0x8000000000000000) BissCalc(BissTest);
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else BissErrRead++;
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uint16_t temp = SpicRegs.SPISTS.all;
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
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SpicRegs.SPIFFRX.bit.RXFFIL = BissCount;
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SpicRegs.SPIFFRX.bit.RXFFIENA = 1;
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SpicRegs.SPIFFRX.bit.RXFFINTCLR = 1;
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}
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__interrupt void spic_tx_isr(void)
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{
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uint16_t temp = SpibRegs.SPISTS.all;
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
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SpicRegs.SPIFFTX.all = 0xE04F;
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SpicRegs.SPIFFTX.bit.TXFFIL = 0x0;
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// SpibRegs.SPIFFTX.bit.TXFFIENA = 1;
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SpicRegs.SPIFFTX.bit.TXFFINTCLR = 1;
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}
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