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рабочий вариант с первой итерацией (чисто клоки) с контрольной суммой

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seklyuts 2024-03-12 15:17:39 +03:00
parent 48fe9bdad8
commit e107e97589
16 changed files with 6692 additions and 10 deletions
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89
Projects/epwm_test/src/CLB/bebug.h Normal file
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//###########################################################################
//
// FILE: debug.h
//
// TITLE: Assert definition macro for debug.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DEBUG_H
#define DEBUG_H
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build. It is the
// application's responsibility to define the __error__ function.
//
//*****************************************************************************
//extern void __error__(const char *filename, uint32_t line);
//__error__(__FILE__, __LINE__);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#ifdef __TMS320C28XX__
//
// When called from C28x application
//
#define ASSERT(expr) do \
{ \
if(!(expr)) \
{ \
ESTOP0; \
} \
} \
while((_Bool)0)
#else
//
// When called from CLA application. Update as needed.
//
#define ASSERT(expr) do \
{ \
if(!(expr)) \
{ \
__mdebugstop(); \
} \
} \
while((_Bool)0)
#endif
#else
#define ASSERT(expr)
#endif
#endif // DEBUG_H

208
Projects/epwm_test/src/CLB/board.c Normal file
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/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "f28x_project.h"
#include "board.h"
#include "clb.h"
#include "xbar.h"
#include "xbar1.h"
//*****************************************************************************
//
// Board Configurations
// Initializes the rest of the modules.
// Call this function in your application if you wish to do all module
// initialization.
// If you wish to not use some of the initializations, instead of the
// Board_init use the individual Module_inits
//
//*****************************************************************************
void Board_init()
{
EALLOW;
//PinMux_init();
CLB_init();
CLB_OUTPUTXBAR_init();
EDIS;
}
//*****************************************************************************
//
// PINMUX Configurations
//
//*****************************************************************************
void PinMux_init()
{
//
// PinMux for modules assigned to CPU1
//
//
// CLB_OUTPUTXBAR6 -> CLB_OUTPUTXBAR_CLKGEN_CLK_M Pinmux
//
// GPIO_setPinConfig(CLB_OUTPUTXBAR_CLKGEN_CLK_M_CLBOUTPUTXBAR_PIN_CONFIG);
//
// CLB_OUTPUTXBAR7 -> CLB_OUTPUTXBAR_CLKGEN_CLK_S Pinmux
//
// GPIO_setPinConfig(CLB_OUTPUTXBAR_CLKGEN_CLK_S_CLBOUTPUTXBAR_PIN_CONFIG);
}
//*****************************************************************************
//
// CLB Configurations
//
//*****************************************************************************
void CLB_init(){
CLB_TILE_CLKGEN_M_init();
CLB_TILE_CLKGEN_S_init();
}
void CLB_TILE_CLKGEN_M_init(){
CLB_setOutputMask(CLB_TILE_CLKGEN_M_BASE,
(0UL << 0UL) |
(1UL << 17UL), true);
CLB_enableOutputMaskUpdates(CLB_TILE_CLKGEN_M_BASE);
//
// CLB_TILE_CLKGEN_M SPI Buffer Configuration
//
CLB_disableSPIBufferAccess(CLB_TILE_CLKGEN_M_BASE);
CLB_configSPIBufferLoadSignal(CLB_TILE_CLKGEN_M_BASE, 0);
CLB_configSPIBufferShift(CLB_TILE_CLKGEN_M_BASE, 0);
//
// CLB_TILE_CLKGEN_M CLB_IN0 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
CLB_configLocalInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configGlobalInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM1A);
CLB_configGPInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN0, CLB_GP_IN_MUX_GP_REG);
CLB_selectInputFilter(CLB_TILE_CLKGEN_M_BASE, CLB_IN0, CLB_FILTER_NONE);
CLB_disableInputPipelineMode(CLB_TILE_CLKGEN_M_BASE, CLB_IN0);
//
// CLB_TILE_CLKGEN_M CLB_IN1 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
CLB_configLocalInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configGlobalInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_EPWM1A);
CLB_configGPInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN1, CLB_GP_IN_MUX_GP_REG);
CLB_selectInputFilter(CLB_TILE_CLKGEN_M_BASE, CLB_IN1, CLB_FILTER_NONE);
CLB_disableInputPipelineMode(CLB_TILE_CLKGEN_M_BASE, CLB_IN1);
CLB_setGPREG(CLB_TILE_CLKGEN_M_BASE,0);
initCLB_CLKGEN_M(CLB_TILE_CLKGEN_M_BASE);
CLB_enableCLB(CLB_TILE_CLKGEN_M_BASE);
}
void CLB_TILE_CLKGEN_S_init(){
CLB_setOutputMask(CLB_TILE_CLKGEN_S_BASE,
(0UL << 0UL), true);
CLB_enableOutputMaskUpdates(CLB_TILE_CLKGEN_S_BASE);
//
// CLB_TILE_CLKGEN_S SPI Buffer Configuration
//
CLB_disableSPIBufferAccess(CLB_TILE_CLKGEN_S_BASE);
CLB_configSPIBufferLoadSignal(CLB_TILE_CLKGEN_S_BASE, 0);
CLB_configSPIBufferShift(CLB_TILE_CLKGEN_S_BASE, 0);
//
// CLB_TILE_CLKGEN_S CLB_IN0 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
CLB_configLocalInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configGlobalInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM1A);
CLB_configGPInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN0, CLB_GP_IN_MUX_GP_REG);
CLB_selectInputFilter(CLB_TILE_CLKGEN_S_BASE, CLB_IN0, CLB_FILTER_NONE);
CLB_disableInputPipelineMode(CLB_TILE_CLKGEN_S_BASE, CLB_IN0);
//
// CLB_TILE_CLKGEN_S CLB_IN1 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
CLB_configLocalInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configGlobalInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_CLB1_OUT17);
CLB_configGPInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN1, CLB_GP_IN_MUX_EXTERNAL);
CLB_selectInputFilter(CLB_TILE_CLKGEN_S_BASE, CLB_IN1, CLB_FILTER_NONE);
CLB_enableInputPipelineMode(CLB_TILE_CLKGEN_S_BASE, CLB_IN1);
CLB_setGPREG(CLB_TILE_CLKGEN_S_BASE,0);
initCLB_CLKGEN_S(CLB_TILE_CLKGEN_S_BASE);
CLB_enableCLB(CLB_TILE_CLKGEN_S_BASE);
}
//*****************************************************************************
//
// CLBOUTPUTXBAR Configurations
//
//*****************************************************************************
void CLB_OUTPUTXBAR_init(){
CLB_OUTPUTXBAR_CLKGEN_CLK_M_init();
CLB_OUTPUTXBAR_CLKGEN_CLK_S_init();
}
void CLB_OUTPUTXBAR_CLKGEN_CLK_M_init(){
XBAR_setOutputLatchMode(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_M, false);
XBAR_invertOutputSignal(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_M, false);
//
//Mux configuration
//
XBAR_setOutputMuxConfig(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_M, XBAR_OUT_MUX00_CLB1_OUT0);
XBAR_enableOutputMux(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_M, XBAR_MUX00);
}
void CLB_OUTPUTXBAR_CLKGEN_CLK_S_init(){
XBAR_setOutputLatchMode(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_S, false);
XBAR_invertOutputSignal(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_S, false);
//
//Mux configuration
//
XBAR_setOutputMuxConfig(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_S, XBAR_OUT_MUX08_CLB2_OUT0);
XBAR_enableOutputMux(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_S, XBAR_MUX08);
}

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/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef BOARD_H
#define BOARD_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//
// Included Files
//
#include "f28x_project.h"
#include "clb.h"
//*****************************************************************************
//
// PinMux Configurations
//
//*****************************************************************************
//
// CLB_OUTPUTXBAR6 -> CLB_OUTPUTXBAR_CLKGEN_CLK_M Pinmux
//
//
// CLB_OUTPUTXBAR6 - GPIO Settings
//
#define GPIO_PIN_CLB_OUTPUTXBAR6 96
#define CLB_OUTPUTXBAR_CLKGEN_CLK_M_CLBOUTPUTXBAR_GPIO 96
#define CLB_OUTPUTXBAR_CLKGEN_CLK_M_CLBOUTPUTXBAR_PIN_CONFIG GPIO_96_CLB_OUTPUTXBAR6
//
// CLB_OUTPUTXBAR7 -> CLB_OUTPUTXBAR_CLKGEN_CLK_S Pinmux
//
//
// CLB_OUTPUTXBAR7 - GPIO Settings
//
#define GPIO_PIN_CLB_OUTPUTXBAR7 97
#define CLB_OUTPUTXBAR_CLKGEN_CLK_S_CLBOUTPUTXBAR_GPIO 97
#define CLB_OUTPUTXBAR_CLKGEN_CLK_S_CLBOUTPUTXBAR_PIN_CONFIG GPIO_97_CLB_OUTPUTXBAR7
//*****************************************************************************
//
// CLB Configurations
//
//*****************************************************************************
#define CLB_TILE_CLKGEN_M_BASE CLB1_BASE
void CLB_TILE_CLKGEN_M_init();
#define CLB_TILE_CLKGEN_S_BASE CLB2_BASE
void CLB_TILE_CLKGEN_S_init();
//
// Tile Configurations for all CLBs are in this file
//
#include "clb_config.h"
//*****************************************************************************
//
// CLBOUTPUTXBAR Configurations
//
//*****************************************************************************
void CLB_OUTPUTXBAR_CLKGEN_CLK_M_init();
#define CLB_OUTPUTXBAR_CLKGEN_CLK_M XBAR_OUTPUT6
#define CLB_OUTPUTXBAR_CLKGEN_CLK_M_ENABLED_MUXES (XBAR_MUX00)
void CLB_OUTPUTXBAR_CLKGEN_CLK_S_init();
#define CLB_OUTPUTXBAR_CLKGEN_CLK_S XBAR_OUTPUT7
#define CLB_OUTPUTXBAR_CLKGEN_CLK_S_ENABLED_MUXES (XBAR_MUX08)
//*****************************************************************************
//
// Board Configurations
//
//*****************************************************************************
void Board_init();
void CLB_init();
void CLB_OUTPUTXBAR_init();
void PinMux_init();
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // end of BOARD_H definition

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//###########################################################################
//
// FILE: clb.c
//
// TITLE: C28x CLB driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "f28x_project.h"
#include "clb.h"
//*****************************************************************************
//
// CLB_configCounterLoadMatch
//
//*****************************************************************************
void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID,
uint32_t load, uint32_t match1, uint32_t match2)
{
ASSERT(CLB_isBaseValid(base));
EALLOW;
switch(counterID)
{
case CLB_CTR0:
CLB_writeInterface(base, CLB_ADDR_COUNTER_0_LOAD, load);
CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH1, match1);
CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH2, match2);
break;
case CLB_CTR1:
CLB_writeInterface(base, CLB_ADDR_COUNTER_1_LOAD, load);
CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH1, match1);
CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH2, match2);
break;
case CLB_CTR2:
CLB_writeInterface(base, CLB_ADDR_COUNTER_2_LOAD, load);
CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH1, match1);
CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH2, match2);
break;
default:
//
// Invalid counterID value
//
break;
}
EDIS;
}
//*****************************************************************************
//
// CLB_clearFIFOs
//
//*****************************************************************************
void CLB_clearFIFOs(uint32_t base)
{
uint16_t i;
ASSERT(CLB_isBaseValid(base));
for(i = 0U; i < CLB_FIFO_SIZE; i++)
{
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(i)) = 0U;
}
HWREG(base + CLB_LOGICCTL + CLB_O_BUF_PTR) = 0U;
}
//*****************************************************************************
//
// CLB_writeFIFOs
//
//*****************************************************************************
void CLB_writeFIFOs(uint32_t base , const uint32_t pullData[])
{
ASSERT(CLB_isBaseValid(base));
//
// Clear the FIFO and pointer
//
CLB_clearFIFOs(base);
//
// Write data into the FIFO.
//
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(0)) = pullData[0U];
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(1)) = pullData[1U];
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(2)) = pullData[2U];
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(3)) = pullData[3U];
}
//*****************************************************************************
//
// CLB_readFIFOs
//
//*****************************************************************************
void CLB_readFIFOs(uint32_t base , uint32_t pushData[])
{
ASSERT(CLB_isBaseValid(base));
//
// Read data from the FIFO.
//
pushData[0U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(0)) ;
pushData[1U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(1)) ;
pushData[2U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(2)) ;
pushData[3U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(3)) ;
}

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/*
* ======== clb.c ========
* DO NOT EDIT - This file is generated by the SysConfig tool.
*/
#include "f28x_project.h"
//#include "driverlib.h"
//#include "device.h"
#include "clb_config.h"
#include "clb.h"
const uint32_t CLB_CLKGEN_M_HLC_initFIFOData[4] = {CLB_CLKGEN_M_HLC_FIFO0_INIT, CLB_CLKGEN_M_HLC_FIFO1_INIT, CLB_CLKGEN_M_HLC_FIFO2_INIT, CLB_CLKGEN_M_HLC_FIFO3_INIT};
uint16_t CLB_CLKGEN_MHLCInstr[CLB_NUM_HLC_INSTR + 1] =
{
CLB_CLKGEN_M_HLCINSTR_0,
CLB_CLKGEN_M_HLCINSTR_1,
CLB_CLKGEN_M_HLCINSTR_2,
CLB_CLKGEN_M_HLCINSTR_3,
CLB_CLKGEN_M_HLCINSTR_4,
CLB_CLKGEN_M_HLCINSTR_5,
CLB_CLKGEN_M_HLCINSTR_6,
CLB_CLKGEN_M_HLCINSTR_7,
CLB_CLKGEN_M_HLCINSTR_8,
CLB_CLKGEN_M_HLCINSTR_9,
CLB_CLKGEN_M_HLCINSTR_10,
CLB_CLKGEN_M_HLCINSTR_11,
CLB_CLKGEN_M_HLCINSTR_12,
CLB_CLKGEN_M_HLCINSTR_13,
CLB_CLKGEN_M_HLCINSTR_14,
CLB_CLKGEN_M_HLCINSTR_15,
CLB_CLKGEN_M_HLCINSTR_16,
CLB_CLKGEN_M_HLCINSTR_17,
CLB_CLKGEN_M_HLCINSTR_18,
CLB_CLKGEN_M_HLCINSTR_19,
CLB_CLKGEN_M_HLCINSTR_20,
CLB_CLKGEN_M_HLCINSTR_21,
CLB_CLKGEN_M_HLCINSTR_22,
CLB_CLKGEN_M_HLCINSTR_23,
CLB_CLKGEN_M_HLCINSTR_24,
CLB_CLKGEN_M_HLCINSTR_25,
CLB_CLKGEN_M_HLCINSTR_26,
CLB_CLKGEN_M_HLCINSTR_27,
CLB_CLKGEN_M_HLCINSTR_28,
CLB_CLKGEN_M_HLCINSTR_29,
CLB_CLKGEN_M_HLCINSTR_30,
CLB_CLKGEN_M_HLCINSTR_31
};
const uint32_t CLB_CLKGEN_S_HLC_initFIFOData[4] = {CLB_CLKGEN_S_HLC_FIFO0_INIT, CLB_CLKGEN_S_HLC_FIFO1_INIT, CLB_CLKGEN_S_HLC_FIFO2_INIT, CLB_CLKGEN_S_HLC_FIFO3_INIT};
uint16_t CLB_CLKGEN_SHLCInstr[CLB_NUM_HLC_INSTR + 1] =
{
CLB_CLKGEN_S_HLCINSTR_0,
CLB_CLKGEN_S_HLCINSTR_1,
CLB_CLKGEN_S_HLCINSTR_2,
CLB_CLKGEN_S_HLCINSTR_3,
CLB_CLKGEN_S_HLCINSTR_4,
CLB_CLKGEN_S_HLCINSTR_5,
CLB_CLKGEN_S_HLCINSTR_6,
CLB_CLKGEN_S_HLCINSTR_7,
CLB_CLKGEN_S_HLCINSTR_8,
CLB_CLKGEN_S_HLCINSTR_9,
CLB_CLKGEN_S_HLCINSTR_10,
CLB_CLKGEN_S_HLCINSTR_11,
CLB_CLKGEN_S_HLCINSTR_12,
CLB_CLKGEN_S_HLCINSTR_13,
CLB_CLKGEN_S_HLCINSTR_14,
CLB_CLKGEN_S_HLCINSTR_15,
CLB_CLKGEN_S_HLCINSTR_16,
CLB_CLKGEN_S_HLCINSTR_17,
CLB_CLKGEN_S_HLCINSTR_18,
CLB_CLKGEN_S_HLCINSTR_19,
CLB_CLKGEN_S_HLCINSTR_20,
CLB_CLKGEN_S_HLCINSTR_21,
CLB_CLKGEN_S_HLCINSTR_22,
CLB_CLKGEN_S_HLCINSTR_23,
CLB_CLKGEN_S_HLCINSTR_24,
CLB_CLKGEN_S_HLCINSTR_25,
CLB_CLKGEN_S_HLCINSTR_26,
CLB_CLKGEN_S_HLCINSTR_27,
CLB_CLKGEN_S_HLCINSTR_28,
CLB_CLKGEN_S_HLCINSTR_29,
CLB_CLKGEN_S_HLCINSTR_30,
CLB_CLKGEN_S_HLCINSTR_31
};
void initCLB_CLKGEN_M(uint32_t base)
{
uint16_t i;
//
// Pipeline Mode
//
CLB_disablePipelineMode(base);
//
// Output LUT
//
//
// Equation for Output Look-Up Table Block 0 for CLB_CLKGEN_M: i0
//
// User Description for Output Look-Up Table 0 for CLB_CLKGEN_M
/*
CLK_M
*/
//
CLB_configOutputLUT(base, CLB_OUT0, CLB_CLKGEN_M_CFG_OUTLUT_0);
//
// Equation for Output Look-Up Table Block 1 for CLB_CLKGEN_M: i0 & i1
//
//
// User Description for Output Look-Up Table 1 for CLB_CLKGEN_M
/*
RUN_S
*/
//
CLB_configOutputLUT(base, CLB_OUT1, CLB_CLKGEN_M_CFG_OUTLUT_1);
CLB_configOutputLUT(base, CLB_OUT2, CLB_CLKGEN_M_CFG_OUTLUT_2);
CLB_configOutputLUT(base, CLB_OUT3, CLB_CLKGEN_M_CFG_OUTLUT_3);
CLB_configOutputLUT(base, CLB_OUT4, CLB_CLKGEN_M_CFG_OUTLUT_4);
CLB_configOutputLUT(base, CLB_OUT5, CLB_CLKGEN_M_CFG_OUTLUT_5);
CLB_configOutputLUT(base, CLB_OUT6, CLB_CLKGEN_M_CFG_OUTLUT_6);
CLB_configOutputLUT(base, CLB_OUT7, CLB_CLKGEN_M_CFG_OUTLUT_7);
//
// AOC
//
CLB_configAOC(base, CLB_AOC0, CLB_CLKGEN_M_OUTPUT_COND_CTR_0);
CLB_configAOC(base, CLB_AOC1, CLB_CLKGEN_M_OUTPUT_COND_CTR_1);
CLB_configAOC(base, CLB_AOC2, CLB_CLKGEN_M_OUTPUT_COND_CTR_2);
CLB_configAOC(base, CLB_AOC3, CLB_CLKGEN_M_OUTPUT_COND_CTR_3);
CLB_configAOC(base, CLB_AOC4, CLB_CLKGEN_M_OUTPUT_COND_CTR_4);
CLB_configAOC(base, CLB_AOC5, CLB_CLKGEN_M_OUTPUT_COND_CTR_5);
CLB_configAOC(base, CLB_AOC6, CLB_CLKGEN_M_OUTPUT_COND_CTR_6);
CLB_configAOC(base, CLB_AOC7, CLB_CLKGEN_M_OUTPUT_COND_CTR_7);
//
// LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
// CLB_selectLUT4Inputs and CLB_configLUT4Function
//
//
// Equation for Look-Up Table Block 0 for CLB_CLKGEN_M: i0 & !i1
// User Description for Look-Up Table Block 0 for CLB_CLKGEN_M
/*
LOAD
*/
//
// Equation for Look-Up Table Block 1 for CLB_CLKGEN_M: i0 & i1
// User Description for Look-Up Table Block 1 for CLB_CLKGEN_M
/*
DONE
*/
//
// Equation for Look-Up Table Block 2 for CLB_CLKGEN_M: i0 & i1
// User Description for Look-Up Table Block 2 for CLB_CLKGEN_M
/*
CLK_PULSE
*/
//
// LUT Configuration
//
CLB_selectLUT4Inputs(base, CLB_CLKGEN_M_CFG_LUT4_IN0, CLB_CLKGEN_M_CFG_LUT4_IN1, CLB_CLKGEN_M_CFG_LUT4_IN2, CLB_CLKGEN_M_CFG_LUT4_IN3);
CLB_configLUT4Function(base, CLB_CLKGEN_M_CFG_LUT4_FN10, CLB_CLKGEN_M_CFG_LUT4_FN2);
//
// FSM 0 - 2 are configured in <file>
//
// State 0 output equation for Finite State Machine 0 for CLB_CLKGEN_M: (e0 & !e1 & !s1 & !s0) | (!e0 & !e1 & !s1 & s0) | (e0 & !e1 & !s1 & s0)
// State 1 output equation for Finite State Machine 0 for CLB_CLKGEN_M: (e0 & e1 & !s1 & s0) | (e0 & !e1 & s1 & !s0) | (e0 & e1 & s1 & !s0)
//
// User Description for Finite State Machine 0 for CLB_CLKGEN_M
/*
ENABLE_PHASE_COUNTER
*/
// State 0 output equation for Finite State Machine 1 for CLB_CLKGEN_M: (e0 & !e1 & !s1 & !s0) | (!e0 & !e1 & !s1 & s0) | (e0 & !e1 & !s1 & s0)
// State 1 output equation for Finite State Machine 1 for CLB_CLKGEN_M: (e0 & e1 & !s1 & s0) | (e0 & !e1 & s1 & !s0) | (e0 & e1 & s1 & !s0)
//
// User Description for Finite State Machine 1 for CLB_CLKGEN_M
/*
ENABLE_CLK_PULSE_COUNTER
*/
// State 0 output equation for Finite State Machine 2 for CLB_CLKGEN_M: s0 ^ e0
// User Description for Finite State Machine 2 for CLB_CLKGEN_M
/*
CLK_OUTPUT
*/
//
// FSM
//
CLB_selectFSMInputs(base, CLB_CLKGEN_M_CFG_FSM_EXT_IN0, CLB_CLKGEN_M_CFG_FSM_EXT_IN1, CLB_CLKGEN_M_CFG_FSM_EXTRA_IN0, CLB_CLKGEN_M_CFG_FSM_EXTRA_IN1);
CLB_configFSMNextState(base, CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_0, CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_1, CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_2);
CLB_configFSMLUTFunction(base, CLB_CLKGEN_M_CFG_FSM_LUT_FN10, CLB_CLKGEN_M_CFG_FSM_LUT_FN2);
//
// Counter 0 - 2 are configured in <file>
//
// User Description for Counter 0 for CLB_CLKGEN_M
/*
CLK_PULSE_COUNTER
*/
// User Description for Counter 1 for CLB_CLKGEN_M
/*
CLK_BURST_COUNTER
*/
// User Description for Counter 2 for CLB_CLKGEN_M
/*
PHASE_COUNTER
*/
//
// Counters
//
CLB_selectCounterInputs(base, CLB_CLKGEN_M_CFG_COUNTER_RESET, CLB_CLKGEN_M_CFG_COUNTER_EVENT, CLB_CLKGEN_M_CFG_COUNTER_MODE_0, CLB_CLKGEN_M_CFG_COUNTER_MODE_1);
CLB_configMiscCtrlModes(base, CLB_CLKGEN_M_CFG_MISC_CONTROL);
CLB_configCounterLoadMatch(base, CLB_CTR0, CLB_CLKGEN_M_COUNTER_0_LOAD_VAL, CLB_CLKGEN_M_COUNTER_0_MATCH1_VAL, CLB_CLKGEN_M_COUNTER_0_MATCH2_VAL);
CLB_configCounterLoadMatch(base, CLB_CTR1, CLB_CLKGEN_M_COUNTER_1_LOAD_VAL, CLB_CLKGEN_M_COUNTER_1_MATCH1_VAL, CLB_CLKGEN_M_COUNTER_1_MATCH2_VAL);
CLB_configCounterLoadMatch(base, CLB_CTR2, CLB_CLKGEN_M_COUNTER_2_LOAD_VAL, CLB_CLKGEN_M_COUNTER_2_MATCH1_VAL, CLB_CLKGEN_M_COUNTER_2_MATCH2_VAL);
CLB_configCounterTapSelects(base, CLB_CLKGEN_M_CFG_TAP_SEL);
//
// HLC is configured in <file>
//
// User Description for the High Level Controller for CLB_CLKGEN_M
/*
*/
//
// HLC
//
CLB_configHLCEventSelect(base, CLB_CLKGEN_M_HLC_EVENT_SEL);
CLB_setHLCRegisters(base, CLB_CLKGEN_M_HLC_R0_INIT, CLB_CLKGEN_M_HLC_R1_INIT, CLB_CLKGEN_M_HLC_R2_INIT, CLB_CLKGEN_M_HLC_R3_INIT);
CLB_writeFIFOs(base, CLB_CLKGEN_M_HLC_initFIFOData);
for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
{
CLB_programHLCInstruction(base, i, CLB_CLKGEN_MHLCInstr[i]);
}
}
void initCLB_CLKGEN_S(uint32_t base)
{
uint16_t i;
//
// Pipeline Mode
//
CLB_disablePipelineMode(base);
//
// Output LUT
//
//
// Equation for Output Look-Up Table Block 0 for CLB_CLKGEN_S: i0
//
// User Description for Output Look-Up Table 0 for CLB_CLKGEN_S
/*
CLK_S
*/
//
CLB_configOutputLUT(base, CLB_OUT0, CLB_CLKGEN_S_CFG_OUTLUT_0);
CLB_configOutputLUT(base, CLB_OUT1, CLB_CLKGEN_S_CFG_OUTLUT_1);
CLB_configOutputLUT(base, CLB_OUT2, CLB_CLKGEN_S_CFG_OUTLUT_2);
CLB_configOutputLUT(base, CLB_OUT3, CLB_CLKGEN_S_CFG_OUTLUT_3);
CLB_configOutputLUT(base, CLB_OUT4, CLB_CLKGEN_S_CFG_OUTLUT_4);
CLB_configOutputLUT(base, CLB_OUT5, CLB_CLKGEN_S_CFG_OUTLUT_5);
CLB_configOutputLUT(base, CLB_OUT6, CLB_CLKGEN_S_CFG_OUTLUT_6);
CLB_configOutputLUT(base, CLB_OUT7, CLB_CLKGEN_S_CFG_OUTLUT_7);
//
// AOC
//
CLB_configAOC(base, CLB_AOC0, CLB_CLKGEN_S_OUTPUT_COND_CTR_0);
CLB_configAOC(base, CLB_AOC1, CLB_CLKGEN_S_OUTPUT_COND_CTR_1);
CLB_configAOC(base, CLB_AOC2, CLB_CLKGEN_S_OUTPUT_COND_CTR_2);
CLB_configAOC(base, CLB_AOC3, CLB_CLKGEN_S_OUTPUT_COND_CTR_3);
CLB_configAOC(base, CLB_AOC4, CLB_CLKGEN_S_OUTPUT_COND_CTR_4);
CLB_configAOC(base, CLB_AOC5, CLB_CLKGEN_S_OUTPUT_COND_CTR_5);
CLB_configAOC(base, CLB_AOC6, CLB_CLKGEN_S_OUTPUT_COND_CTR_6);
CLB_configAOC(base, CLB_AOC7, CLB_CLKGEN_S_OUTPUT_COND_CTR_7);
//
// LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
// CLB_selectLUT4Inputs and CLB_configLUT4Function
//
//
// Equation for Look-Up Table Block 0 for CLB_CLKGEN_S: i0 & !i1
// User Description for Look-Up Table Block 0 for CLB_CLKGEN_S
/*
LOAD
*/
//
// Equation for Look-Up Table Block 1 for CLB_CLKGEN_S: i0 & i1
// User Description for Look-Up Table Block 1 for CLB_CLKGEN_S
/*
DONE
*/
//
// Equation for Look-Up Table Block 2 for CLB_CLKGEN_S: i0 & i1
// User Description for Look-Up Table Block 2 for CLB_CLKGEN_S
/*
CLK_PULSE
*/
//
// LUT Configuration
//
CLB_selectLUT4Inputs(base, CLB_CLKGEN_S_CFG_LUT4_IN0, CLB_CLKGEN_S_CFG_LUT4_IN1, CLB_CLKGEN_S_CFG_LUT4_IN2, CLB_CLKGEN_S_CFG_LUT4_IN3);
CLB_configLUT4Function(base, CLB_CLKGEN_S_CFG_LUT4_FN10, CLB_CLKGEN_S_CFG_LUT4_FN2);
//
// FSM 0 - 2 are configured in <file>
//
// State 0 output equation for Finite State Machine 1 for CLB_CLKGEN_S: (e0 & !e1 & !s1 & !s0) | (!e0 & !e1 & !s1 & s0) | (e0 & !e1 & !s1 & s0)
// State 1 output equation for Finite State Machine 1 for CLB_CLKGEN_S: (e0 & e1 & !s1 & s0) | (e0 & !e1 & s1 & !s0) | (e0 & e1 & s1 & !s0)
//
// User Description for Finite State Machine 1 for CLB_CLKGEN_S
/*
ENABLE_CLK_PULSE_COUNTER
*/
// State 0 output equation for Finite State Machine 2 for CLB_CLKGEN_S: s0 ^ e0
// User Description for Finite State Machine 2 for CLB_CLKGEN_S
/*
CLK_OUTPUT
*/
//
// FSM
//
CLB_selectFSMInputs(base, CLB_CLKGEN_S_CFG_FSM_EXT_IN0, CLB_CLKGEN_S_CFG_FSM_EXT_IN1, CLB_CLKGEN_S_CFG_FSM_EXTRA_IN0, CLB_CLKGEN_S_CFG_FSM_EXTRA_IN1);
CLB_configFSMNextState(base, CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_0, CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_1, CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_2);
CLB_configFSMLUTFunction(base, CLB_CLKGEN_S_CFG_FSM_LUT_FN10, CLB_CLKGEN_S_CFG_FSM_LUT_FN2);
//
// Counter 0 - 2 are configured in <file>
//
// User Description for Counter 0 for CLB_CLKGEN_S
/*
CLK_PULSE_COUNTER
*/
// User Description for Counter 1 for CLB_CLKGEN_S
/*
CLK_BURST_COUNTER
*/
//
// Counters
//
CLB_selectCounterInputs(base, CLB_CLKGEN_S_CFG_COUNTER_RESET, CLB_CLKGEN_S_CFG_COUNTER_EVENT, CLB_CLKGEN_S_CFG_COUNTER_MODE_0, CLB_CLKGEN_S_CFG_COUNTER_MODE_1);
CLB_configMiscCtrlModes(base, CLB_CLKGEN_S_CFG_MISC_CONTROL);
CLB_configCounterLoadMatch(base, CLB_CTR0, CLB_CLKGEN_S_COUNTER_0_LOAD_VAL, CLB_CLKGEN_S_COUNTER_0_MATCH1_VAL, CLB_CLKGEN_S_COUNTER_0_MATCH2_VAL);
CLB_configCounterLoadMatch(base, CLB_CTR1, CLB_CLKGEN_S_COUNTER_1_LOAD_VAL, CLB_CLKGEN_S_COUNTER_1_MATCH1_VAL, CLB_CLKGEN_S_COUNTER_1_MATCH2_VAL);
CLB_configCounterLoadMatch(base, CLB_CTR2, CLB_CLKGEN_S_COUNTER_2_LOAD_VAL, CLB_CLKGEN_S_COUNTER_2_MATCH1_VAL, CLB_CLKGEN_S_COUNTER_2_MATCH2_VAL);
CLB_configCounterTapSelects(base, CLB_CLKGEN_S_CFG_TAP_SEL);
//
// HLC is configured in <file>
//
// User Description for the High Level Controller for CLB_CLKGEN_S
/*
*/
//
// HLC
//
CLB_configHLCEventSelect(base, CLB_CLKGEN_S_HLC_EVENT_SEL);
CLB_setHLCRegisters(base, CLB_CLKGEN_S_HLC_R0_INIT, CLB_CLKGEN_S_HLC_R1_INIT, CLB_CLKGEN_S_HLC_R2_INIT, CLB_CLKGEN_S_HLC_R3_INIT);
CLB_writeFIFOs(base, CLB_CLKGEN_S_HLC_initFIFOData);
for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
{
CLB_programHLCInstruction(base, i, CLB_CLKGEN_SHLCInstr[i]);
}
}

252
Projects/epwm_test/src/CLB/clb_config.h Normal file
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@ -0,0 +1,252 @@
/*
* ======== clb.h ========
* DO NOT EDIT - This file is generated by the SysConfig tool.
*/
#ifndef ti_clb_h
#define ti_clb_h
#include <stdint.h>
#ifdef __cplusplus
extern "C" { // support C++ sources
#endif
// HLC Instruction Register Field definitions
#define HLC_OPCODE_R0 0x0
#define HLC_OPCODE_R1 0x1
#define HLC_OPCODE_R2 0x2
#define HLC_OPCODE_R3 0x3
#define HLC_OPCODE_C0 0x4
#define HLC_OPCODE_C1 0x5
#define HLC_OPCODE_C2 0x6
#define HLC_OPCODE_MOV 0x00
#define HLC_OPCODE_MOV_T1 0x01
#define HLC_OPCODE_MOV_T2 0x02
#define HLC_OPCODE_PUSH 0x03
#define HLC_OPCODE_PULL 0x04
#define HLC_OPCODE_ADD 0x05
#define HLC_OPCODE_SUB 0x06
#define HLC_OPCODE_INTR 0x07
//---------------------------------------------------------------------------
// CLB_CLKGEN_M
//---------------------------------------------------------------------------
#define CLB_CLKGEN_M_PIPELINE_MODE 0
#define CLB_CLKGEN_M_CFG_OUTLUT_0 0x550014
#define CLB_CLKGEN_M_CFG_OUTLUT_1 0x440093
#define CLB_CLKGEN_M_CFG_OUTLUT_2 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_3 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_4 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_5 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_6 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_7 0x0
#define CLB_CLKGEN_M_CFG_LUT4_IN0 0xc78
#define CLB_CLKGEN_M_CFG_LUT4_IN1 0x316c
#define CLB_CLKGEN_M_CFG_LUT4_IN2 0x0
#define CLB_CLKGEN_M_CFG_LUT4_IN3 0x0
#define CLB_CLKGEN_M_CFG_LUT4_FN10 ((0x88880000) | 0x2222)
#define CLB_CLKGEN_M_CFG_LUT4_FN2 0x8888
#define CLB_CLKGEN_M_CFG_FSM_EXT_IN0 0x5f39
#define CLB_CLKGEN_M_CFG_FSM_EXT_IN1 0x1f3
#define CLB_CLKGEN_M_CFG_FSM_EXTRA_IN0 0x0
#define CLB_CLKGEN_M_CFG_FSM_EXTRA_IN1 0x0
#define CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_0 ((0x60400000) | 0x32)
#define CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_1 ((0x60400000) | 0x32)
#define CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_2 ((0x00000) | 0x5a5a)
#define CLB_CLKGEN_M_CFG_FSM_LUT_FN10 ((0x00000) | 0x0)
#define CLB_CLKGEN_M_CFG_FSM_LUT_FN2 0x0
#define CLB_CLKGEN_M_FSM_MISC_CONTROL 0x0
#define CLB_CLKGEN_M_CFG_COUNTER_RESET 0x4de3
#define CLB_CLKGEN_M_CFG_COUNTER_EVENT 0x60
#define CLB_CLKGEN_M_CFG_COUNTER_MODE_0 0x100c
#define CLB_CLKGEN_M_CFG_COUNTER_MODE_1 0x2008
#define CLB_CLKGEN_M_CFG_TAP_SEL 0x0
#define CLB_CLKGEN_M_CFG_MISC_CONTROL (0x38 | CLB_CLKGEN_M_FSM_MISC_CONTROL)
#define CLB_CLKGEN_M_COUNTER_0_MATCH1_VAL 0
#define CLB_CLKGEN_M_COUNTER_0_MATCH2_VAL 0
#define CLB_CLKGEN_M_COUNTER_0_LOAD_VAL 0
#define CLB_CLKGEN_M_COUNTER_1_MATCH1_VAL 0
#define CLB_CLKGEN_M_COUNTER_1_MATCH2_VAL 0
#define CLB_CLKGEN_M_COUNTER_1_LOAD_VAL 1
#define CLB_CLKGEN_M_COUNTER_2_MATCH1_VAL 0
#define CLB_CLKGEN_M_COUNTER_2_MATCH2_VAL 0
#define CLB_CLKGEN_M_COUNTER_2_LOAD_VAL 0
#define CLB_CLKGEN_M_SPI_EN 0
#define CLB_CLKGEN_M_HLC_EVENT_SEL 0x1e7
#define CLB_CLKGEN_M_HLC_R0_INIT 0
#define CLB_CLKGEN_M_HLC_R1_INIT 0
#define CLB_CLKGEN_M_HLC_R2_INIT 0
#define CLB_CLKGEN_M_HLC_R3_INIT 0
#define CLB_CLKGEN_M_HLC_FIFO0_INIT 0
#define CLB_CLKGEN_M_HLC_FIFO1_INIT 0
#define CLB_CLKGEN_M_HLC_FIFO2_INIT 0
#define CLB_CLKGEN_M_HLC_FIFO3_INIT 0
#define CLB_CLKGEN_M_HLCINSTR_0 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_M_HLCINSTR_1 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C0)
#define CLB_CLKGEN_M_HLCINSTR_2 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_M_HLCINSTR_3 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C1)
#define CLB_CLKGEN_M_HLCINSTR_4 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_M_HLCINSTR_5 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C2)
#define CLB_CLKGEN_M_HLCINSTR_6 (1 << 11 | HLC_OPCODE_PUSH << 6 | HLC_OPCODE_R0<<3)
#define CLB_CLKGEN_M_HLCINSTR_7 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_8 (1 << 11 | HLC_OPCODE_PUSH << 6 | HLC_OPCODE_R0<<3)
#define CLB_CLKGEN_M_HLCINSTR_9 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_10 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_11 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_12 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_13 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_14 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_15 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_16 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_17 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_18 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_19 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_20 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_21 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_22 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_23 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_24 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_25 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_26 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_27 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_28 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_29 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_30 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_31 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_0 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_1 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_2 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_3 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_4 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_5 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_6 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_7 0x0
//---------------------------------------------------------------------------
// CLB_CLKGEN_S
//---------------------------------------------------------------------------
#define CLB_CLKGEN_S_PIPELINE_MODE 0
#define CLB_CLKGEN_S_CFG_OUTLUT_0 0x550014
#define CLB_CLKGEN_S_CFG_OUTLUT_1 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_2 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_3 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_4 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_5 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_6 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_7 0x0
#define CLB_CLKGEN_S_CFG_LUT4_IN0 0xc78
#define CLB_CLKGEN_S_CFG_LUT4_IN1 0x316c
#define CLB_CLKGEN_S_CFG_LUT4_IN2 0x0
#define CLB_CLKGEN_S_CFG_LUT4_IN3 0x0
#define CLB_CLKGEN_S_CFG_LUT4_FN10 ((0x88880000) | 0x2222)
#define CLB_CLKGEN_S_CFG_LUT4_FN2 0x8888
#define CLB_CLKGEN_S_CFG_FSM_EXT_IN0 0x5f20
#define CLB_CLKGEN_S_CFG_FSM_EXT_IN1 0x1e0
#define CLB_CLKGEN_S_CFG_FSM_EXTRA_IN0 0x0
#define CLB_CLKGEN_S_CFG_FSM_EXTRA_IN1 0x0
#define CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_0 ((0x00000) | 0x0)
#define CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_1 ((0x60400000) | 0x32)
#define CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_2 ((0x00000) | 0x5a5a)
#define CLB_CLKGEN_S_CFG_FSM_LUT_FN10 ((0x00000) | 0x0)
#define CLB_CLKGEN_S_CFG_FSM_LUT_FN2 0x0
#define CLB_CLKGEN_S_FSM_MISC_CONTROL 0x0
#define CLB_CLKGEN_S_CFG_COUNTER_RESET 0x1e3
#define CLB_CLKGEN_S_CFG_COUNTER_EVENT 0x60
#define CLB_CLKGEN_S_CFG_COUNTER_MODE_0 0xc
#define CLB_CLKGEN_S_CFG_COUNTER_MODE_1 0x8
#define CLB_CLKGEN_S_CFG_TAP_SEL 0x0
#define CLB_CLKGEN_S_CFG_MISC_CONTROL (0x38 | CLB_CLKGEN_S_FSM_MISC_CONTROL)
#define CLB_CLKGEN_S_COUNTER_0_MATCH1_VAL 0
#define CLB_CLKGEN_S_COUNTER_0_MATCH2_VAL 0
#define CLB_CLKGEN_S_COUNTER_0_LOAD_VAL 0
#define CLB_CLKGEN_S_COUNTER_1_MATCH1_VAL 0
#define CLB_CLKGEN_S_COUNTER_1_MATCH2_VAL 0
#define CLB_CLKGEN_S_COUNTER_1_LOAD_VAL 1
#define CLB_CLKGEN_S_COUNTER_2_MATCH1_VAL 0
#define CLB_CLKGEN_S_COUNTER_2_MATCH2_VAL 0
#define CLB_CLKGEN_S_COUNTER_2_LOAD_VAL 0
#define CLB_CLKGEN_S_SPI_EN 0
#define CLB_CLKGEN_S_HLC_EVENT_SEL 0x1e7
#define CLB_CLKGEN_S_HLC_R0_INIT 0
#define CLB_CLKGEN_S_HLC_R1_INIT 0
#define CLB_CLKGEN_S_HLC_R2_INIT 0
#define CLB_CLKGEN_S_HLC_R3_INIT 0
#define CLB_CLKGEN_S_HLC_FIFO0_INIT 0
#define CLB_CLKGEN_S_HLC_FIFO1_INIT 0
#define CLB_CLKGEN_S_HLC_FIFO2_INIT 0
#define CLB_CLKGEN_S_HLC_FIFO3_INIT 0
#define CLB_CLKGEN_S_HLCINSTR_0 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_S_HLCINSTR_1 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C0)
#define CLB_CLKGEN_S_HLCINSTR_2 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_S_HLCINSTR_3 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C1)
#define CLB_CLKGEN_S_HLCINSTR_4 (1 << 11 | HLC_OPCODE_PUSH << 6 | HLC_OPCODE_R0<<3)
#define CLB_CLKGEN_S_HLCINSTR_5 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_6 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_7 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_8 (1 << 11 | HLC_OPCODE_PUSH << 6 | HLC_OPCODE_R0<<3)
#define CLB_CLKGEN_S_HLCINSTR_9 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_10 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_11 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_12 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_13 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_14 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_15 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_16 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_17 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_18 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_19 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_20 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_21 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_22 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_23 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_24 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_25 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_26 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_27 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_28 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_29 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_30 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_31 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_0 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_1 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_2 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_3 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_4 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_5 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_6 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_7 0x0
void initCLB_CLKGEN_M(uint32_t base);
void initCLB_CLKGEN_S(uint32_t base);
#ifdef __cplusplus
}
#endif
#endif // ti_clb_h

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//###########################################################################
//
// FILE: hw_memmap.h
//
// TITLE: Macros defining the memory map of the C28x.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_MEMMAP_H
#define HW_MEMMAP_H
//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals.
//
//*****************************************************************************
#define M0_RAM_BASE 0x00000000U
#define M1_RAM_BASE 0x00000400U
#define ADCARESULT_BASE 0x00000B00U
#define ADCBRESULT_BASE 0x00000B20U
#define ADCCRESULT_BASE 0x00000B40U
#define ADCDRESULT_BASE 0x00000B60U
#define CPUTIMER0_BASE 0x00000C00U
#define CPUTIMER1_BASE 0x00000C08U
#define CPUTIMER2_BASE 0x00000C10U
#define PIECTRL_BASE 0x00000CE0U
#define PIEVECTTABLE_BASE 0x00000D00U
#define DMA_BASE 0x00001000U
#define DMA_CH1_BASE 0x00001020U
#define DMA_CH2_BASE 0x00001040U
#define DMA_CH3_BASE 0x00001060U
#define DMA_CH4_BASE 0x00001080U
#define DMA_CH5_BASE 0x000010A0U
#define DMA_CH6_BASE 0x000010C0U
#define CLA1_BASE 0x00001400U
#define CLATOCPU_RAM_BASE 0x00001480U
#define CPUTOCLA_RAM_BASE 0x00001500U
#define CLATODMA_RAM_BASE 0x00001680U
#define DMATOCLA_RAM_BASE 0x00001700U
#define CLB1_BASE 0x00003000U
#define CLB1_LOGICCFG_BASE 0x00003000U
#define CLB1_LOGICCTL_BASE 0x00003100U
#define CLB1_DATAEXCH_BASE 0x00003180U
#define CLB2_BASE 0x00003200U
#define CLB2_LOGICCFG_BASE 0x00003200U
#define CLB2_LOGICCTL_BASE 0x00003300U
#define CLB2_DATAEXCH_BASE 0x00003380U
#define CLB3_BASE 0x00003400U
#define CLB3_LOGICCFG_BASE 0x00003400U
#define CLB3_LOGICCTL_BASE 0x00003500U
#define CLB3_DATAEXCH_BASE 0x00003580U
#define CLB4_BASE 0x00003600U
#define CLB4_LOGICCFG_BASE 0x00003600U
#define CLB4_LOGICCTL_BASE 0x00003700U
#define CLB4_DATAEXCH_BASE 0x00003780U
#define CLB5_BASE 0x00003800U
#define CLB5_LOGICCFG_BASE 0x00003800U
#define CLB5_LOGICCTL_BASE 0x00003900U
#define CLB5_DATAEXCH_BASE 0x00003980U
#define CLB6_BASE 0x00003A00U
#define CLB6_LOGICCFG_BASE 0x00003A00U
#define CLB6_LOGICCTL_BASE 0x00003B00U
#define CLB6_DATAEXCH_BASE 0x00003B80U
#define CLB7_BASE 0x00003C00U
#define CLB7_LOGICCFG_BASE 0x00003C00U
#define CLB7_LOGICCTL_BASE 0x00003D00U
#define CLB7_DATAEXCH_BASE 0x00003D80U
#define CLB8_BASE 0x00003E00U
#define CLB8_LOGICCFG_BASE 0x00003E00U
#define CLB8_LOGICCTL_BASE 0x00003F00U
#define CLB8_DATAEXCH_BASE 0x00003F80U
#define EPWM1_BASE 0x00004000U
#define EPWM2_BASE 0x00004100U
#define EPWM3_BASE 0x00004200U
#define EPWM4_BASE 0x00004300U
#define EPWM5_BASE 0x00004400U
#define EPWM6_BASE 0x00004500U
#define EPWM7_BASE 0x00004600U
#define EPWM8_BASE 0x00004700U
#define EPWM9_BASE 0x00004800U
#define EPWM10_BASE 0x00004900U
#define EPWM11_BASE 0x00004A00U
#define EPWM12_BASE 0x00004B00U
#define EPWM13_BASE 0x00004C00U
#define EPWM14_BASE 0x00004D00U
#define EPWM15_BASE 0x00004E00U
#define EPWM16_BASE 0x00004F00U
#define EQEP1_BASE 0x00005100U
#define EQEP2_BASE 0x00005140U
#define EQEP3_BASE 0x00005180U
#define ECAP1_BASE 0x00005200U
#define ECAP2_BASE 0x00005240U
#define ECAP3_BASE 0x00005280U
#define ECAP4_BASE 0x000052C0U
#define ECAP5_BASE 0x00005300U
#define ECAP6_BASE 0x00005340U
#define HRCAP6_BASE 0x00005360U
#define ECAP7_BASE 0x00005380U
#define HRCAP7_BASE 0x000053A0U
#define DACA_BASE 0x00005C00U
#define DACB_BASE 0x00005C10U
#define DACC_BASE 0x00005C20U
#define CMPSS1_BASE 0x00005C80U
#define CMPSS2_BASE 0x00005CA0U
#define CMPSS3_BASE 0x00005CC0U
#define CMPSS4_BASE 0x00005CE0U
#define CMPSS5_BASE 0x00005D00U
#define CMPSS6_BASE 0x00005D20U
#define CMPSS7_BASE 0x00005D40U
#define CMPSS8_BASE 0x00005D60U
#define SDFM1_BASE 0x00005E00U
#define SDFM2_BASE 0x00005E80U
#define MCBSPA_BASE 0x00006000U
#define MCBSPB_BASE 0x00006040U
#define SPIA_BASE 0x00006100U
#define SPIB_BASE 0x00006110U
#define SPIC_BASE 0x00006120U
#define SPID_BASE 0x00006130U
#define BGCRC_CPU_BASE 0x00006340U
#define BGCRC_CLA1_BASE 0x00006380U
#define PMBUSA_BASE 0x00006400U
#define FSITXA_BASE 0x00006600U
#define FSIRXA_BASE 0x00006680U
#define FSITXB_BASE 0x00006700U
#define FSIRXB_BASE 0x00006780U
#define FSIRXC_BASE 0x00006880U
#define FSIRXD_BASE 0x00006980U
#define FSIRXE_BASE 0x00006A80U
#define FSIRXF_BASE 0x00006B80U
#define FSIRXG_BASE 0x00006C80U
#define FSIRXH_BASE 0x00006D80U
#define WD_BASE 0x00007000U
#define NMI_BASE 0x00007060U
#define XINT_BASE 0x00007070U
#define SCIA_BASE 0x00007200U
#define SCIB_BASE 0x00007210U
#define SCIC_BASE 0x00007220U
#define SCID_BASE 0x00007230U
#define I2CA_BASE 0x00007300U
#define I2CB_BASE 0x00007340U
#define ADCA_BASE 0x00007400U
#define ADCB_BASE 0x00007480U
#define ADCC_BASE 0x00007500U
#define ADCD_BASE 0x00007580U
#define INPUTXBAR_BASE 0x00007900U
#define XBAR_BASE 0x00007920U
#define SYNCSOC_BASE 0x00007940U
#define CLBINPUTXBAR_BASE 0x00007960U
#define DMACLASRCSEL_BASE 0x00007980U
#define EPWMXBAR_BASE 0x00007A00U
#define CLBXBAR_BASE 0x00007A40U
#define OUTPUTXBAR_BASE 0x00007A80U
#define CLBOUTPUTXBAR_BASE 0x00007BC0U
#define GPIOCTRL_BASE 0x00007C00U
#define GPIODATA_BASE 0x00007F00U
#define GPIODATAREAD_BASE 0x00007F80U
#define LS0_RAM_BASE 0x00008000U
#define LS1_RAM_BASE 0x00008800U
#define LS2_RAM_BASE 0x00009000U
#define LS3_RAM_BASE 0x00009800U
#define LS4_RAM_BASE 0x0000A000U
#define LS5_RAM_BASE 0x0000A800U
#define LS6_RAM_BASE 0x0000B000U
#define LS7_RAM_BASE 0x0000B800U
#define D0_RAM_BASE 0x0000C000U
#define D1_RAM_BASE 0x0000C800U
#define GS0_RAM_BASE 0x0000D000U
#define GS1_RAM_BASE 0x0000E000U
#define GS2_RAM_BASE 0x0000F000U
#define GS3_RAM_BASE 0x00010000U
#define GS4_RAM_BASE 0x00011000U
#define GS5_RAM_BASE 0x00012000U
#define GS6_RAM_BASE 0x00013000U
#define GS7_RAM_BASE 0x00014000U
#define GS8_RAM_BASE 0x00015000U
#define GS9_RAM_BASE 0x00016000U
#define GS10_RAM_BASE 0x00017000U
#define GS11_RAM_BASE 0x00018000U
#define GS12_RAM_BASE 0x00019000U
#define GS13_RAM_BASE 0x0001A000U
#define GS14_RAM_BASE 0x0001B000U
#define GS15_RAM_BASE 0x0001C000U
#define CMTOCPUXMSGRAM0_BASE 0x00038000U
#define CMTOCPUXMSGRAM1_BASE 0x00038400U
#define CPUXTOCMMSGRAM0_BASE 0x00039000U
#define CPUXTOCMMSGRAM1_BASE 0x00039400U
#define CPU1TOCPU2MSGRAM0_BASE 0x0003A000U
#define CPU1TOCPU2MSGRAM1_BASE 0x0003A400U
#define CPU2TOCPU1MSGRAM0_BASE 0x0003B000U
#define CPU2TOCPU1MSGRAM1_BASE 0x0003B400U
#define USBA_BASE 0x00040000U
#define EMIF1_BASE 0x00047000U
#define EMIF2_BASE 0x00047800U
#define CANA_BASE 0x00048000U
#define CANA_MSG_RAM_BASE 0x00049000U
#define CANB_BASE 0x0004A000U
#define CANB_MSG_RAM_BASE 0x0004B000U
#define ESC_SS_BASE 0x00057E00U
#define ESC_SS_CONFIG_BASE 0x00057F00U
#define MCANA_DRIVER_BASE 0x00058000U
#define MCANA_MSG_RAM_BASE 0x00058000U
#define MCANASS_BASE 0x0005C400U
#define MCANA_BASE 0x0005C600U
#define MCANA_ERROR_BASE 0x0005C800U
#define IPC_CPUXTOCPUX_BASE 0x0005CE00U
#define FLASHPUMPSEMAPHORE_BASE 0x0005CE24U
#define IPC_CPUXTOCM_BASE 0x0005CE40U
#define DEVCFG_BASE 0x0005D000U
#define CLKCFG_BASE 0x0005D200U
#define CPUSYS_BASE 0x0005D300U
#define SYSSTAT_BASE 0x0005D400U
#define PERIPHAC_BASE 0x0005D500U
#define PERIPHAC_BASE 0x0005D500U
#define ANALOGSUBSYS_BASE 0x0005D700U
#define CMCONF_BASE 0x0005DC00U
#define HWBIST_BASE 0x0005E000U
#define PBIST_BASE 0x0005E200U
#define DCC0_BASE 0x0005E700U
#define DCC1_BASE 0x0005E740U
#define DCC2_BASE 0x0005E780U
#define ERAD_GLOBAL_BASE 0x0005E800U
#define ERAD_HWBP1_BASE 0x0005E900U
#define ERAD_HWBP2_BASE 0x0005E908U
#define ERAD_HWBP3_BASE 0x0005E910U
#define ERAD_HWBP4_BASE 0x0005E918U
#define ERAD_HWBP5_BASE 0x0005E920U
#define ERAD_HWBP6_BASE 0x0005E928U
#define ERAD_HWBP7_BASE 0x0005E930U
#define ERAD_HWBP8_BASE 0x0005E938U
#define ERAD_COUNTER1_BASE 0x0005E980U
#define ERAD_COUNTER2_BASE 0x0005E990U
#define ERAD_COUNTER3_BASE 0x0005E9A0U
#define ERAD_COUNTER4_BASE 0x0005E9B0U
#define ERAD_CRC_GLOBAL_BASE 0x0005EA00U
#define ERAD_CRC1_BASE 0x0005EA10U
#define ERAD_CRC2_BASE 0x0005EA20U
#define ERAD_CRC3_BASE 0x0005EA30U
#define ERAD_CRC4_BASE 0x0005EA40U
#define ERAD_CRC5_BASE 0x0005EA50U
#define ERAD_CRC6_BASE 0x0005EA60U
#define ERAD_CRC7_BASE 0x0005EA70U
#define ERAD_CRC8_BASE 0x0005EA80U
#define DCSM_Z1_BASE 0x0005F000U
#define DCSM_Z2_BASE 0x0005F080U
#define DCSMCOMMON_BASE 0x0005F0C0U
#define MEMCFG_BASE 0x0005F400U
#define EMIF1CONFIG_BASE 0x0005F4C0U
#define EMIF2CONFIG_BASE 0x0005F4E0U
#define ACCESSPROTECTION_BASE 0x0005F500U
#define MEMORYERROR_BASE 0x0005F540U
#define ROMWAITSTATE_BASE 0x0005F580U
#define ROMPREFETCH_BASE 0x0005F588U
#define TESTERROR_BASE 0x0005F590U
#define FLASH0CTRL_BASE 0x0005F800U
#define FLASH0ECC_BASE 0x0005FB00U
#define UID_BASE 0x00070200U
#define CPUID_BASE 0x00070223U
#define DCSM_Z1OTP_BASE 0x00078000U
#define DCSM_Z2OTP_BASE 0x00078200U
#if defined(__TMS320C28XX_CLA2__)
#define CLA1_ONLY_BASE 0x00000C00U
#endif
#endif

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//###########################################################################
//
// FILE: hw_types.h
//
// TITLE: Type definitions used in driverlib functions.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_TYPES_H
#define HW_TYPES_H
//*****************************************************************************
//
// Define dummy 8 bit types for USB Driver code.
//
//*****************************************************************************
typedef uint16_t uint8_t;
typedef int16_t int8_t;
//*****************************************************************************
//
// Macros for hardware access
//
//*****************************************************************************
#if defined(__TMS320C28XX_CLA__)
#define HWREG(x) \
(*((volatile uint32_t *)((uintptr_t)(x))))
#define HWREGH(x) \
(*((volatile uint16_t *)((uintptr_t)(x))))
#else
#define HWREG(x) \
(*((volatile uint32_t *)(x)))
#define HWREGH(x) \
(*((volatile uint16_t *)(x)))
#endif
#define HWREG_BP(x) \
__byte_peripheral_32((uint32_t *)(x))
#define HWREGB(x) \
__byte((int16_t *)(x),0)
//
// Emulated Bitbanded write
//
#define HWREGBITW(address, mask, value) \
(*(volatile uint32_t *)(address)) = \
((*(volatile uint32_t *)(address)) & ~((uint32_t)1 << mask)) \
| ((uint32_t)value << mask)
//
// Emulated Bitbanded read
//
#define HWREGBITR(address, mask) \
(((*(volatile uint32_t *)(address)) & ((uint32_t)1 << mask)) >> mask)
//
// Emulated Bitbanded write
//
#define HWREGBITHW(address, mask, value) \
(*(volatile uint16_t *)(address)) = \
((*(volatile uint16_t *)(address)) & ~((uint16_t)1 << mask)) \
| ((uint16_t)value << mask)
//
// Emulated Bitbanded read
//
#define HWREGBITHR(address, mask) \
(((*(volatile uint16_t *)(address)) & ((uint16_t)1 << mask)) >> mask)
//*****************************************************************************
//
// SUCCESS and FAILURE for API return value
//
//*****************************************************************************
#define STATUS_S_SUCCESS (0)
#define STATUS_E_FAILURE (-1)
//****************************************************************************
//
// For checking NULL pointers
//
//****************************************************************************
#ifndef NULL
#define NULL ((void *)0x0)
#endif
//*****************************************************************************
//
// 32-bit float type
//
//*****************************************************************************
#ifndef C2000_IEEE754_TYPES
#define C2000_IEEE754_TYPES
typedef float float32_t;
#ifdef __TI_EABI__
typedef double float64_t;
#else // TI COFF
typedef long double float64_t;
#endif // __TI_EABI__
#endif // C2000_IEEE754_TYPES
//*****************************************************************************
//
// Extern compiler intrinsic prototypes. See compiler User's Guide for details.
// These are provided to satisfy static analysis tools. The #ifndef is required
// because the '&' is for a C++-style reference, and although it is the correct
// prototype, it will not build in C code.
//
//*****************************************************************************
#if(defined(__TMS320C28XX__) || defined(__TMS320C28XX_CLA__))
#else
extern int16_t &__byte(int16_t *array, uint16_t byte_index);
extern uint32_t &__byte_peripheral_32(uint32_t *x);
#endif
//
// C++ Bool Compatibility
//
#if defined(__cplusplus)
typedef bool _Bool;
#endif
/* To fix Misra-C errors */
#ifndef TRUE
#define TRUE ((bool) 1)
#endif
#ifndef FALSE
#define FALSE ((bool) 0)
#endif
#endif // HW_TYPES_H

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//###########################################################################
//
// FILE: xbar.h
//
// TITLE: C28x X-BAR driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef XBAR_H
#define XBAR_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************
#define XBAR_O_INPUT1SELECT 0x0U // INPUT1 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT2SELECT 0x1U // INPUT2 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT3SELECT 0x2U // INPUT3 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT4SELECT 0x3U // INPUT4 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT5SELECT 0x4U // INPUT5 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT6SELECT 0x5U // INPUT6 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT7SELECT 0x6U // INPUT7 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT8SELECT 0x7U // INPUT8 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT9SELECT 0x8U // INPUT9 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT10SELECT 0x9U // INPUT10 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT11SELECT 0xAU // INPUT11 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT12SELECT 0xBU // INPUT12 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT13SELECT 0xCU // INPUT13 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT14SELECT 0xDU // INPUT14 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT15SELECT 0xEU // INPUT15 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT16SELECT 0xFU // INPUT16 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUTSELECTLOCK 0x1EU // Input Select Lock Register
#define XBAR_INPUT_FLG_INPUT_M 0x00FFU
#define XBAR_INPUT_FLG_REG_M 0xFF00U
#define XBAR_INPUT_FLG_REG_1 0x0000U
#define XBAR_INPUT_FLG_REG_2 0x0100U
#define XBAR_INPUT_FLG_REG_3 0x0200U
#define XBAR_INPUT_FLG_REG_4 0x0300U
#define XBAR_GPIO_MAX_CNT 168U
#define XBAR_NON_GPIO_MIN_CNT 0xFFFDU
#define XBAR_NON_GPIO_MAX_CNT 0xFFFFU
//*****************************************************************************
//
//! \addtogroup xbar_api XBAR
//! @{
//
//*****************************************************************************
#define XBAR_MUX00 0x00000001U //!< Mask for X-BAR mux 0
#define XBAR_MUX01 0x00000002U //!< Mask for X-BAR mux 1
#define XBAR_MUX02 0x00000004U //!< Mask for X-BAR mux 2
#define XBAR_MUX03 0x00000008U //!< Mask for X-BAR mux 3
#define XBAR_MUX04 0x00000010U //!< Mask for X-BAR mux 4
#define XBAR_MUX05 0x00000020U //!< Mask for X-BAR mux 5
#define XBAR_MUX06 0x00000040U //!< Mask for X-BAR mux 6
#define XBAR_MUX07 0x00000080U //!< Mask for X-BAR mux 7
#define XBAR_MUX08 0x00000100U //!< Mask for X-BAR mux 8
#define XBAR_MUX09 0x00000200U //!< Mask for X-BAR mux 9
#define XBAR_MUX10 0x00000400U //!< Mask for X-BAR mux 10
#define XBAR_MUX11 0x00000800U //!< Mask for X-BAR mux 11
#define XBAR_MUX12 0x00001000U //!< Mask for X-BAR mux 12
#define XBAR_MUX13 0x00002000U //!< Mask for X-BAR mux 13
#define XBAR_MUX14 0x00004000U //!< Mask for X-BAR mux 14
#define XBAR_MUX15 0x00008000U //!< Mask for X-BAR mux 15
#define XBAR_MUX16 0x00010000U //!< Mask for X-BAR mux 16
#define XBAR_MUX17 0x00020000U //!< Mask for X-BAR mux 17
#define XBAR_MUX18 0x00040000U //!< Mask for X-BAR mux 18
#define XBAR_MUX19 0x00080000U //!< Mask for X-BAR mux 19
#define XBAR_MUX20 0x00100000U //!< Mask for X-BAR mux 20
#define XBAR_MUX21 0x00200000U //!< Mask for X-BAR mux 21
#define XBAR_MUX22 0x00400000U //!< Mask for X-BAR mux 22
#define XBAR_MUX23 0x00800000U //!< Mask for X-BAR mux 23
#define XBAR_MUX24 0x01000000U //!< Mask for X-BAR mux 24
#define XBAR_MUX25 0x02000000U //!< Mask for X-BAR mux 25
#define XBAR_MUX26 0x04000000U //!< Mask for X-BAR mux 26
#define XBAR_MUX27 0x08000000U //!< Mask for X-BAR mux 27
#define XBAR_MUX28 0x10000000U //!< Mask for X-BAR mux 28
#define XBAR_MUX29 0x20000000U //!< Mask for X-BAR mux 29
#define XBAR_MUX30 0x40000000U //!< Mask for X-BAR mux 30
#define XBAR_MUX31 0x80000000U //!< Mask for X-BAR mux 31
//*****************************************************************************
//
//! The following values define the \e input parameter for XBAR_setInputPin().
//
//*****************************************************************************
typedef enum
{
XBAR_INPUT1, //!< ePWM[TZ1], ePWM[TRIP1], X-BARs, eCAPs
XBAR_INPUT2, //!< ePWM[TZ2], ePWM[TRIP2], X-BARs, eCAPs
XBAR_INPUT3, //!< ePWM[TZ3], ePWM[TRIP3], X-BARs, eCAPs
XBAR_INPUT4, //!< ADC wrappers, X-BARs, XINT1, eCAPs
XBAR_INPUT5, //!< EXTSYNCIN1, X-BARs, XINT2, eCAPs
XBAR_INPUT6, //!< EXTSYNCIN2, ePWM[TRIP6], X-BARs, XINT3, eCAPs
XBAR_INPUT7, //!< X-BARs, eCAPs
XBAR_INPUT8, //!< X-BARs, eCAPs
XBAR_INPUT9, //!< X-BARs, eCAPs
XBAR_INPUT10, //!< X-BARs, eCAPs
XBAR_INPUT11, //!< X-BARs, eCAPs
XBAR_INPUT12, //!< X-BARs, eCAPs
XBAR_INPUT13, //!< XINT4, X-BARs, eCAPs
XBAR_INPUT14, //!< XINT5, X-BARs, eCAPs
XBAR_INPUT15, //!< eCAPs
XBAR_INPUT16 //!< eCAPs
} XBAR_InputNum;
//*****************************************************************************
//
//! The following values define the \e muxConfig parameter for
//! XBAR_setOutputMuxConfig().
//
//*****************************************************************************
typedef enum
{
//
//OUTPUTXBAR
//
XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH = 0x0000,
XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH_OR_L = 0x0001,
XBAR_OUT_MUX00_ADCAEVT1 = 0x0002,
XBAR_OUT_MUX00_ECAP1_OUT = 0x0003,
XBAR_OUT_MUX01_CMPSS1_CTRIPOUTL = 0x0200,
XBAR_OUT_MUX01_INPUTXBAR1 = 0x0201,
XBAR_OUT_MUX01_CLB1_OUT4 = 0x0202,
XBAR_OUT_MUX01_ADCCEVT1 = 0x0203,
XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH = 0x0400,
XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH_OR_L = 0x0401,
XBAR_OUT_MUX02_ADCAEVT2 = 0x0402,
XBAR_OUT_MUX02_ECAP2_OUT = 0x0403,
XBAR_OUT_MUX03_CMPSS2_CTRIPOUTL = 0x0600,
XBAR_OUT_MUX03_INPUTXBAR2 = 0x0601,
XBAR_OUT_MUX03_CLB1_OUT5 = 0x0602,
XBAR_OUT_MUX03_ADCCEVT2 = 0x0603,
XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH = 0x0800,
XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH_OR_L = 0x0801,
XBAR_OUT_MUX04_ADCAEVT3 = 0x0802,
XBAR_OUT_MUX04_ECAP3_OUT = 0x0803,
XBAR_OUT_MUX05_CMPSS3_CTRIPOUTL = 0x0A00,
XBAR_OUT_MUX05_INPUTXBAR3 = 0x0A01,
XBAR_OUT_MUX05_CLB2_OUT4 = 0x0A02,
XBAR_OUT_MUX05_ADCCEVT3 = 0x0A03,
XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH = 0x0C00,
XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH_OR_L = 0x0C01,
XBAR_OUT_MUX06_ADCAEVT4 = 0x0C02,
XBAR_OUT_MUX06_ECAP4_OUT = 0x0C03,
XBAR_OUT_MUX07_CMPSS4_CTRIPOUTL = 0x0E00,
XBAR_OUT_MUX07_INPUTXBAR4 = 0x0E01,
XBAR_OUT_MUX07_CLB2_OUT5 = 0x0E02,
XBAR_OUT_MUX07_ADCCEVT4 = 0x0E03,
XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH = 0x1000,
XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH_OR_L = 0x1001,
XBAR_OUT_MUX08_ADCBEVT1 = 0x1002,
XBAR_OUT_MUX08_ECAP5_OUT = 0x1003,
XBAR_OUT_MUX09_CMPSS5_CTRIPOUTL = 0x1200,
XBAR_OUT_MUX09_INPUTXBAR5 = 0x1201,
XBAR_OUT_MUX09_CLB3_OUT4 = 0x1202,
XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH = 0x1400,
XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH_OR_L = 0x1401,
XBAR_OUT_MUX10_ADCBEVT2 = 0x1402,
XBAR_OUT_MUX10_ECAP6_OUT = 0x1403,
XBAR_OUT_MUX11_CMPSS6_CTRIPOUTL = 0x1600,
XBAR_OUT_MUX11_INPUTXBAR6 = 0x1601,
XBAR_OUT_MUX11_CLB3_OUT5 = 0x1602,
XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH = 0x1800,
XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH_OR_L = 0x1801,
XBAR_OUT_MUX12_ADCBEVT3 = 0x1802,
XBAR_OUT_MUX12_ECAP7_OUT = 0x1803,
XBAR_OUT_MUX13_CMPSS7_CTRIPOUTL = 0x1A00,
XBAR_OUT_MUX13_ADCSOCA = 0x1A01,
XBAR_OUT_MUX13_CLB4_OUT4 = 0x1A02,
XBAR_OUT_MUX14_ADCBEVT4 = 0x1C02,
XBAR_OUT_MUX14_EXTSYNCOUT = 0x1C03,
XBAR_OUT_MUX15_ADCSOCB = 0x1E01,
XBAR_OUT_MUX15_CLB4_OUT5 = 0x1E02,
XBAR_OUT_MUX16_SD1FLT1_CEVT1 = 0x2000,
XBAR_OUT_MUX16_SD1FLT1_CEVT1_OR_CEVT2 = 0x2001,
XBAR_OUT_MUX17_SD1FLT1_CEVT2 = 0x2200,
XBAR_OUT_MUX17_CLB5_OUT4 = 0x2202,
XBAR_OUT_MUX17_CLAHALT = 0x2203,
XBAR_OUT_MUX18_SD1FLT2_CEVT1 = 0x2400,
XBAR_OUT_MUX18_SD1FLT2_CEVT1_OR_CEVT2 = 0x2401,
XBAR_OUT_MUX19_SD1FLT2_CEVT2 = 0x2600,
XBAR_OUT_MUX19_CLB5_OUT5 = 0x2602,
XBAR_OUT_MUX20_SD1FLT3_CEVT1 = 0x2800,
XBAR_OUT_MUX20_SD1FLT3_CEVT1_OR_CEVT2 = 0x2801,
XBAR_OUT_MUX21_SD1FLT3_CEVT2 = 0x2A00,
XBAR_OUT_MUX21_CLB6_OUT4 = 0x2A02,
XBAR_OUT_MUX22_SD1FLT4_CEVT1 = 0x2C00,
XBAR_OUT_MUX22_SD1FLT4_CEVT1_OR_CEVT2 = 0x2C01,
XBAR_OUT_MUX23_SD1FLT4_CEVT2 = 0x2E00,
XBAR_OUT_MUX23_CLB6_OUT5 = 0x2E02,
XBAR_OUT_MUX24_SD2FLT1_CEVT1 = 0x3000,
XBAR_OUT_MUX24_SD2FLT1_CEVT1_OR_CEVT2 = 0x3001,
XBAR_OUT_MUX25_SD2FLT1_CEVT2 = 0x3200,
XBAR_OUT_MUX25_CLB7_OUT4 = 0x3203,
XBAR_OUT_MUX26_SD2FLT2_CEVT1 = 0x3400,
XBAR_OUT_MUX26_SD2FLT2_CEVT1_OR_CEVT2 = 0x3401,
XBAR_OUT_MUX27_SD2FLT2_CEVT2 = 0x3600,
XBAR_OUT_MUX27_ERRORSTS = 0x3602,
XBAR_OUT_MUX27_CLB7_OUT5 = 0x3603,
XBAR_OUT_MUX28_SD2FLT3_CEVT1 = 0x3800,
XBAR_OUT_MUX28_SD2FLT3_CEVT1_OR_CEVT2 = 0x3801,
XBAR_OUT_MUX28_XCLKOUT = 0x3802,
XBAR_OUT_MUX29_SD2FLT3_CEVT2 = 0x3A00,
XBAR_OUT_MUX29_CLB8_OUT4 = 0x3A03,
XBAR_OUT_MUX30_SD2FLT4_CEVT1 = 0x3C00,
XBAR_OUT_MUX30_SD2FLT4_CEVT1_OR_CEVT2 = 0x3C01,
XBAR_OUT_MUX31_SD2FLT4_CEVT2 = 0x3E00,
XBAR_OUT_MUX31_CLB8_OUT5 = 0x3E03,
//
//CLBOUTPUTXBAR
//
XBAR_OUT_MUX00_CLB1_OUT0 = 0x0000,
XBAR_OUT_MUX00_CLB5_OUT0 = 0x0001,
XBAR_OUT_MUX01_CLB1_OUT1 = 0x0200,
XBAR_OUT_MUX01_CLB5_OUT1 = 0x0201,
XBAR_OUT_MUX02_CLB1_OUT2 = 0x0400,
XBAR_OUT_MUX02_CLB5_OUT2 = 0x0401,
XBAR_OUT_MUX03_CLB1_OUT3 = 0x0600,
XBAR_OUT_MUX03_CLB5_OUT3 = 0x0601,
XBAR_OUT_MUX04_CLB1_OUT4 = 0x0800,
XBAR_OUT_MUX04_CLB5_OUT4 = 0x0801,
XBAR_OUT_MUX05_CLB1_OUT5 = 0x0A00,
XBAR_OUT_MUX05_CLB5_OUT5 = 0x0A01,
XBAR_OUT_MUX06_CLB1_OUT6 = 0x0C00,
XBAR_OUT_MUX06_CLB5_OUT6 = 0x0C01,
XBAR_OUT_MUX07_CLB1_OUT7 = 0x0E00,
XBAR_OUT_MUX07_CLB5_OUT7 = 0x0E01,
XBAR_OUT_MUX08_CLB2_OUT0 = 0x1000,
XBAR_OUT_MUX08_CLB6_OUT0 = 0x1001,
XBAR_OUT_MUX09_CLB2_OUT1 = 0x1200,
XBAR_OUT_MUX09_CLB6_OUT1 = 0x1201,
XBAR_OUT_MUX10_CLB2_OUT2 = 0x1400,
XBAR_OUT_MUX10_CLB6_OUT2 = 0x1401,
XBAR_OUT_MUX11_CLB2_OUT3 = 0x1600,
XBAR_OUT_MUX11_CLB6_OUT3 = 0x1601,
XBAR_OUT_MUX12_CLB2_OUT4 = 0x1800,
XBAR_OUT_MUX12_CLB6_OUT4 = 0x1801,
XBAR_OUT_MUX13_CLB2_OUT5 = 0x1A00,
XBAR_OUT_MUX13_CLB6_OUT5 = 0x1A01,
XBAR_OUT_MUX14_CLB2_OUT6 = 0x1C00,
XBAR_OUT_MUX14_CLB6_OUT6 = 0x1C01,
XBAR_OUT_MUX15_CLB2_OUT7 = 0x1E00,
XBAR_OUT_MUX15_CLB6_OUT7 = 0x1E01,
XBAR_OUT_MUX16_CLB3_OUT0 = 0x2000,
XBAR_OUT_MUX16_CLB7_OUT0 = 0x2001,
XBAR_OUT_MUX17_CLB3_OUT1 = 0x2200,
XBAR_OUT_MUX17_CLB7_OUT1 = 0x2201,
XBAR_OUT_MUX18_CLB3_OUT2 = 0x2400,
XBAR_OUT_MUX18_CLB7_OUT2 = 0x2401,
XBAR_OUT_MUX19_CLB3_OUT3 = 0x2600,
XBAR_OUT_MUX19_CLB7_OUT3 = 0x2601,
XBAR_OUT_MUX20_CLB3_OUT4 = 0x2800,
XBAR_OUT_MUX20_CLB7_OUT4 = 0x2801,
XBAR_OUT_MUX21_CLB3_OUT5 = 0x2A00,
XBAR_OUT_MUX21_CLB7_OUT5 = 0x2A01,
XBAR_OUT_MUX22_CLB3_OUT6 = 0x2C00,
XBAR_OUT_MUX22_CLB7_OUT6 = 0x2C01,
XBAR_OUT_MUX23_CLB3_OUT7 = 0x2E00,
XBAR_OUT_MUX23_CLB7_OUT7 = 0x2E01,
XBAR_OUT_MUX24_CLB4_OUT0 = 0x3000,
XBAR_OUT_MUX24_CLB8_OUT0 = 0x3001,
XBAR_OUT_MUX25_CLB4_OUT1 = 0x3200,
XBAR_OUT_MUX25_CLB8_OUT1 = 0x3201,
XBAR_OUT_MUX26_CLB4_OUT2 = 0x3400,
XBAR_OUT_MUX26_CLB8_OUT2 = 0x3401,
XBAR_OUT_MUX27_CLB4_OUT3 = 0x3600,
XBAR_OUT_MUX27_CLB8_OUT3 = 0x3601,
XBAR_OUT_MUX28_CLB4_OUT4 = 0x3800,
XBAR_OUT_MUX28_CLB8_OUT4 = 0x3801,
XBAR_OUT_MUX29_CLB4_OUT5 = 0x3A00,
XBAR_OUT_MUX29_CLB8_OUT5 = 0x3A01,
XBAR_OUT_MUX30_CLB4_OUT6 = 0x3C00,
XBAR_OUT_MUX30_CLB8_OUT6 = 0x3C01,
XBAR_OUT_MUX31_CLB4_OUT7 = 0x3E00,
XBAR_OUT_MUX31_CLB8_OUT7 = 0x3E01,
} XBAR_OutputMuxConfig;
//*****************************************************************************
//
//! The following values define the \e output parameter for
//! XBAR_setOutputMuxConfig(), XBAR_enableOutputMux(), and
//! XBAR_disableOutputMux().
//
//*****************************************************************************
typedef enum
{
XBAR_OUTPUT1 = 0, //!< OUTPUT1 of the Output X-BAR
XBAR_OUTPUT2 = 2, //!< OUTPUT2 of the Output X-BAR
XBAR_OUTPUT3 = 4, //!< OUTPUT3 of the Output X-BAR
XBAR_OUTPUT4 = 6, //!< OUTPUT4 of the Output X-BAR
XBAR_OUTPUT5 = 8, //!< OUTPUT5 of the Output X-BAR
XBAR_OUTPUT6 = 10, //!< OUTPUT6 of the Output X-BAR
XBAR_OUTPUT7 = 12, //!< OUTPUT7 of the Output X-BAR
XBAR_OUTPUT8 = 14, //!< OUTPUT8 of the Output X-BAR
} XBAR_OutputNum;
//*****************************************************************************
//
//! The following values define the \e trip parameter for
//! XBAR_setEPWMMuxConfig(), XBAR_invertEPWMSignal(), XBAR_enableEPWMMux(),
//! and XBAR_disableEPWMMux().
//
//*****************************************************************************
typedef enum
{
XBAR_TRIP4 = 0, //!< TRIP4 of the ePWM X-BAR
XBAR_TRIP5 = 2, //!< TRIP5 of the ePWM X-BAR
XBAR_TRIP7 = 4, //!< TRIP7 of the ePWM X-BAR
XBAR_TRIP8 = 6, //!< TRIP8 of the ePWM X-BAR
XBAR_TRIP9 = 8, //!< TRIP9 of the ePWM X-BAR
XBAR_TRIP10 = 10, //!< TRIP10 of the ePWM X-BAR
XBAR_TRIP11 = 12, //!< TRIP11 of the ePWM X-BAR
XBAR_TRIP12 = 14 //!< TRIP12 of the ePWM X-BAR
} XBAR_TripNum;
//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************
#define XBAR_O_OUTPUT1MUX0TO15CFG 0x0U // Output X-BAR Mux Configuration for Output 1
#define XBAR_O_OUTPUT1MUX16TO31CFG 0x2U // Output X-BAR Mux Configuration for Output 1
#define XBAR_O_OUTPUT2MUX0TO15CFG 0x4U // Output X-BAR Mux Configuration for Output 2
#define XBAR_O_OUTPUT2MUX16TO31CFG 0x6U // Output X-BAR Mux Configuration for Output 2
#define XBAR_O_OUTPUT3MUX0TO15CFG 0x8U // Output X-BAR Mux Configuration for Output 3
#define XBAR_O_OUTPUT3MUX16TO31CFG 0xAU // Output X-BAR Mux Configuration for Output 3
#define XBAR_O_OUTPUT4MUX0TO15CFG 0xCU // Output X-BAR Mux Configuration for Output 4
#define XBAR_O_OUTPUT4MUX16TO31CFG 0xEU // Output X-BAR Mux Configuration for Output 4
#define XBAR_O_OUTPUT5MUX0TO15CFG 0x10U // Output X-BAR Mux Configuration for Output 5
#define XBAR_O_OUTPUT5MUX16TO31CFG 0x12U // Output X-BAR Mux Configuration for Output 5
#define XBAR_O_OUTPUT6MUX0TO15CFG 0x14U // Output X-BAR Mux Configuration for Output 6
#define XBAR_O_OUTPUT6MUX16TO31CFG 0x16U // Output X-BAR Mux Configuration for Output 6
#define XBAR_O_OUTPUT7MUX0TO15CFG 0x18U // Output X-BAR Mux Configuration for Output 7
#define XBAR_O_OUTPUT7MUX16TO31CFG 0x1AU // Output X-BAR Mux Configuration for Output 7
#define XBAR_O_OUTPUT8MUX0TO15CFG 0x1CU // Output X-BAR Mux Configuration for Output 8
#define XBAR_O_OUTPUT8MUX16TO31CFG 0x1EU // Output X-BAR Mux Configuration for Output 8
#define XBAR_O_OUTPUT1MUXENABLE 0x20U // Output X-BAR Mux Enable for Output 1
#define XBAR_O_OUTPUT2MUXENABLE 0x22U // Output X-BAR Mux Enable for Output 2
#define XBAR_O_OUTPUT3MUXENABLE 0x24U // Output X-BAR Mux Enable for Output 3
#define XBAR_O_OUTPUT4MUXENABLE 0x26U // Output X-BAR Mux Enable for Output 4
#define XBAR_O_OUTPUT5MUXENABLE 0x28U // Output X-BAR Mux Enable for Output 5
#define XBAR_O_OUTPUT6MUXENABLE 0x2AU // Output X-BAR Mux Enable for Output 6
#define XBAR_O_OUTPUT7MUXENABLE 0x2CU // Output X-BAR Mux Enable for Output 7
#define XBAR_O_OUTPUT8MUXENABLE 0x2EU // Output X-BAR Mux Enable for Output 8
#define XBAR_O_OUTPUTLATCH 0x30U // Output X-BAR Output Latch
#define XBAR_O_OUTPUTLATCHCLR 0x32U // Output X-BAR Output Latch Clear
#define XBAR_O_OUTPUTLATCHFRC 0x34U // Output X-BAR Output Latch Clear
#define XBAR_O_OUTPUTLATCHENABLE 0x36U // Output X-BAR Output Latch Enable
#define XBAR_O_OUTPUTINV 0x38U // Output X-BAR Output Inversion
#define XBAR_O_OUTPUTLOCK 0x3EU // Output X-BAR Configuration Lock register
XBAR_isBaseValid(uint32_t base)
{
return((base == OUTPUTXBAR_BASE) ||
(base == CLBOUTPUTXBAR_BASE) || (base == CLBINPUTXBAR_BASE ) ||
(base == INPUTXBAR_BASE));
}
//*****************************************************************************
//
//! Sets the GPIO / non-GPIO pin for an Input X-BAR input.
//!
//! \param base specifies the X-BAR base address.
//! \param input is the X-BAR input being configured.
//! \param pin is the identifying number of the pin.
//!
//! The \e base parameter can take base addresses
//! INPUTXBAR_BASE
//! or CLBINPUTXBAR_BASE.
//!
//! This function configures which GPIO is assigned to an Input X-BAR input.
//! The \e input parameter is a value in the form of a define \b XBAR_INPUTy
//! where y is a the input number for the Input X-BAR.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! For the other non - GPIO values:
//! 0xFFFD: '1' will be driven to the destination
//! 0xFFFE: '1' will be driven to the destination
//! 0xFFFF: '0' will be driven to the destination
//! NOTE: Pin value greater than the available number of GPIO pins on a
//! device (except 0xFFFF) will cause the destination to be driven '1'.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_setInputPin(uint32_t base, XBAR_InputNum input, uint16_t pin)
{
//
// Check the argument.
//
ASSERT((pin <= XBAR_GPIO_MAX_CNT) ||
((pin >= XBAR_NON_GPIO_MIN_CNT) && (pin <= XBAR_NON_GPIO_MAX_CNT)));
ASSERT(XBAR_isBaseValid(base));
//
// Write the requested pin to the appropriate input select register.
//
EALLOW;
HWREGH(base + XBAR_O_INPUT1SELECT + (uint16_t)input) = pin;
EDIS;
}
#ifdef __cplusplus
}
#endif
#endif // XBAR_H

215
Projects/epwm_test/src/CLB/xbar1.h Normal file
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@ -0,0 +1,215 @@
/*
* xbar1.h
*
* Created on: 20 ôåâð. 2024 ã.
* Author: seklyuts
*/
#ifndef SRC_CLB_XBAR1_H_
#define SRC_CLB_XBAR1_H_
//*****************************************************************************
//
//! Enables or disables the output latch to drive the selected output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8.
//! \param enable is a flag that determines whether or not the latch is
//! selected to drive the X-BAR output.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function sets the Output X-BAR output signal latch mode. If the
//! \e enable parameter is \b true, the output specified by \e output will be
//! driven by the output latch.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_setOutputLatchMode(uint32_t base, XBAR_OutputNum output, bool enable)
{
//
// Check the arguments.
//
EALLOW;
//
// Set or clear the latch setting bit based on the enable parameter.
//
if(enable)
{
HWREGH(base + XBAR_O_OUTPUTLATCHENABLE) |=
0x1U << ((uint16_t)output / 2U);
}
else
{
HWREGH(base + XBAR_O_OUTPUTLATCHENABLE) &=
~(0x1U << ((uint16_t)output / 2U));
}
EDIS;
}
//*****************************************************************************
//
//! Configures the polarity of an Output X-BAR output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8.
//! \param invert is a flag that determines whether the output is active-high
//! or active-low.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function inverts the Output X-BAR signal if the \e invert parameter is
//! \b true. If \e invert is \b false, the signal will be passed as is. The
//! \e output parameter is a value \b XBAR_OUTPUTy where y is the output
//! number between 1 and 8 inclusive.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_invertOutputSignal(uint32_t base, XBAR_OutputNum output, bool invert)
{
//
// Check the arguments.
//
//
// Set or clear the polarity setting bit based on the invert parameter.
//
EALLOW;
if(invert)
{
HWREGH(base + XBAR_O_OUTPUTINV) |=
0x1U << ((uint16_t)output / 2U);
}
else
{
HWREGH(base + XBAR_O_OUTPUTINV) &=
~(0x1U << ((uint16_t)output / 2U));
}
EDIS;
}
//*****************************************************************************
//
//! Enables the Output X-BAR mux values to be passed to the output signal.
//!
//! \param base specifies the X-BAR Enable register base address.
//! \param output is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be enabled.
//!
//! This function enables the mux values to be passed to the X-BAR output
//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is
//! the output number between 1 and 8 inclusive.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! The \e muxes parameter is a bit field of the muxes being enabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be OR'd together to enable several
//! muxes on an output at the same time. For example, passing this function
//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would enable muxes 4 and 10.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_enableOutputMux(uint32_t base, XBAR_OutputNum output, uint32_t muxes)
{
uint16_t outputNum = (uint16_t)output;
//
// Check the arguments.
//
//
// Set the enable bit.
//
EALLOW;
HWREG(base + XBAR_O_OUTPUT1MUXENABLE + outputNum) |= muxes;
EDIS;
}
//*****************************************************************************
//
// XBAR_setOutputMuxConfig
//
//*****************************************************************************
void
XBAR_setOutputMuxConfig(uint32_t base, XBAR_OutputNum output,
XBAR_OutputMuxConfig muxConfig)
{
//
// Check the arguments.
//
uint32_t shift;
uint16_t offset;
//
// If the configuration is for MUX16-31, we'll need an odd value to index
// into the config registers.
//
if(((uint32_t)muxConfig & 0x2000U) != 0U)
{
offset = ((uint16_t)output << 1U) + 2U;
}
else
{
offset = (uint16_t)output << 1U;
}
//
// Extract the shift from the input value.
//
shift = ((uint32_t)muxConfig >> 8U) & 0x1FU;
//
// Write the requested muxing value for this XBAR output.
//
EALLOW;
HWREG(base + XBAR_O_OUTPUT1MUX0TO15CFG + offset) =
(HWREG(base + XBAR_O_OUTPUT1MUX0TO15CFG + offset) &
~((uint32_t)0x3U << shift)) |
(((uint32_t)muxConfig & 0x3U) << shift);
EDIS;
}
#endif /* SRC_CLB_XBAR1_H_ */

2
Projects/epwm_test/src/Peripherals/pwm_interrupts.c
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@ -16,6 +16,7 @@
#include "sdfm.h"
#include "adc_init.h"
#include <pwm_init.h>
#include "biss.h"
volatile uint16_t AutoChange = 0;
@ -134,6 +135,7 @@ __interrupt void epwm2_isr(void)
PwmFlagStartADC = 0;
FMSTREnableSet();
AdcStartSet();
BissStartSet();
PWM_ABC_StopAllClose();
PWM_motor.UA = PERIOD_2;
PWM_motor.UB = PERIOD_2;

26
Projects/epwm_test/src/biss.c
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@ -11,6 +11,7 @@
#include "CLB/board.h"
#include "crc.h"
#define DEVICE_SYSCLK_FREQ 200000000
#define CLB_CLOCK_FREQ (DEVICE_SYSCLK_FREQ / 2)
@ -24,6 +25,7 @@
uint16_t biss_on = 0;
uint16_t biss_auto = 1;
uint32_t BissBrr = BISS_BR;
void BissInit(void)
{
@ -46,7 +48,9 @@ void BissInit(void)
Board_init();
BissClkgenSetup(16*BISS_C_BITS, 16*BISS_C_BITS, BISS_BR, 2);
// clkgen_setup(16*BISS_C_BITS, 16*BISS_C_BITS, BissBrr, 0);
BissClkgenSetup(16*BISS_C_BITS, 16*BISS_C_BITS, BissBrr, 0);
// InputXbarRegs.INPUT1SELECT = 100;
@ -58,6 +62,8 @@ void BissInit(void)
void BissGpioInit(void)
{
EALLOW;
@ -123,19 +129,23 @@ void BissClkgenSetup(unsigned int bits_num_m,
CLB_clearFIFOs2();
}
uint16_t bissReInit = 0;
void BissClkgenRun(void) {
if(biss_on)
{
biss_on = 0;
Clb1LogicCtrlRegs.CLB_GP_REG.all = CLKGEN_RUN_GP_FLAG;
DELAY_US(10);
Clb1LogicCtrlRegs.CLB_GP_REG.all = 0;
while ((((Clb1LogicCtrlRegs.CLB_BUF_PTR.all >> 16) & 0x03) == 0) && (((Clb2LogicCtrlRegs.CLB_BUF_PTR.all >> 16) & 0x03) == 0));
biss_on = 0;
Clb1LogicCtrlRegs.CLB_GP_REG.all = CLKGEN_RUN_GP_FLAG;
DELAY_US(10);
Clb1LogicCtrlRegs.CLB_GP_REG.all = 0;
CLB_clearFIFOs1();
CLB_clearFIFOs2();
while ((((Clb1LogicCtrlRegs.CLB_BUF_PTR.all >> 16) & 0x03) == 0) && (((Clb2LogicCtrlRegs.CLB_BUF_PTR.all >> 16) & 0x03) == 0));
CLB_clearFIFOs1();
CLB_clearFIFOs2();
}
}

2
Projects/epwm_test/src/biss.h
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@ -13,7 +13,7 @@
#define BISS_CLK_POL 1
#define BISS_CLK_PHASE 1
#define BISS_BR 1500000
#define BISS_BR 1000000
void BissInit(void);
void BissGpioInit(void);

3
Projects/epwm_test/src/init_perif.c
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@ -80,8 +80,9 @@ void InitPerif(void)
SpiCInit();
SpiCGpioInit();
BissInit();
BissGpioInit();
BissInit();
// SpiGpioInit();