- TEMP_REG1 was being used by QM_ADD and ONLINE STATUS update in
v-frame processing
- Update version to 0.4
Fixes: PINDSW-6487
Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
- Mask was not applied to QM register before checking the low value
- Enable QMLW/POS checks for all H-frames
Fixes: PINDSW-6530
Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
- Firmware should not clear these bits in EVENT/EVENT_S registers
- Update the version to 0.3
Fixes: PINDSW-6526
Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
- Update the version to 0.2
- Use the VERSION and VERSION2 register
- Remove the hardcoding from driver
Fixes: PINDSW-6518
Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
- MASK_SUM should not be used for masking SUMMARY while updating these
SUM and SSUM bits in ONLINE STATUS registers
- Fix the mask for SCE and VPOS updates
Fixes: PINDSW-6487, PINDSW-6488
Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
- Fix sign extension in estimator for relative position and acceleration
addition
- Fix sign estimation for relative position calculation
- Remove an unnecessary RET instruction
- Fix register corruption for ALIGN_PH
- Fix register usage for DTE error signaling
Fixes: PINDSW-5689
Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
- Fix the address of ONLINE STATUS bytes by adding a reserved byte
- Create separate entries for low and high bytes of ONLINE STATUS registers
- Add SAFE_CTRL and POSTX registers
- Use high and low addresses in firmware for ONLINE STATUS registers
Fixes: PINDSW-6489
Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
