External/motor-control-sdk
8
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Pull request #84: am243x/am64x: hdsl: Fix stuffing in learn state

Browse Source 
Merge in PINDSW/motor_control_sdk from PINDSW-7129_fix_hdsl_learn_state to next

* commit 'a5f10acb7b98f6a7f0e9f0242f0731e8df3b9088':
  am243x/am64x: hdsl: Fix stuffing in learn state
This commit is contained in:
Dhaval Khandla 2023-12-19 03:33:05 -06:00 committed by Pratheesh Gangadhar TK
commit e6cf3c58ad
8 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
source/position_sense/hdsl/firmware/datalink_init.asm
View File

@ -485,8 +485,8 @@ datalink_learn_pattern:
PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff PUSH_FIFO_CONST 0xff
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff PUSH_FIFO_CONST 0xff
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0x00
PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0x00
@ -499,8 +499,8 @@ datalink_learn_pattern:
PUSH_FIFO_CONST 0xff PUSH_FIFO_CONST 0xff
WAIT_TX_FIFO_FREE WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff PUSH_FIFO_CONST 0xff
PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0x00
@ -513,8 +513,8 @@ datalink_learn_pattern:
PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff PUSH_FIFO_CONST 0xff
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0x00
WAIT_TX_FIFO_FREE
PUSH_FIFO_CONST 0xff PUSH_FIFO_CONST 0xff
PUSH_FIFO_CONST 0xff PUSH_FIFO_CONST 0xff
.else .else

2
source/position_sense/hdsl/firmware/defines.inc
View File

@ -34,7 +34,7 @@
; bit7..4 major number ; bit7..4 major number
FIRMWARE_VERSION_MAJOR .set 0x0 FIRMWARE_VERSION_MAJOR .set 0x0
; bit3..0 minor number ; bit3..0 minor number
FIRMWARE_VERSION_MINOR .set 0xB FIRMWARE_VERSION_MINOR .set 0xC
ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0))

2
source/position_sense/hdsl/firmware/hdsl_master_icssg_freerun_225_mhz_bin.h
View File

@ -1382,7 +1382,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81080580, 0x81080580,
0x240017c0, 0x240017c0,
0x810605c0, 0x810605c0,
0x24000b00, 0x24000c00,
0x810b1800, 0x810b1800,
0x81441800, 0x81441800,
0x2eff8383, 0x2eff8383,

8
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
View File

@ -1657,7 +1657,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81080580, 0x81080580,
0x240003c0, 0x240003c0,
0x810605c0, 0x810605c0,
0x24000b00, 0x24000c00,
0x810b1800, 0x810b1800,
0x81441800, 0x81441800,
0x2eff8383, 0x2eff8383,
@ -1843,9 +1843,9 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0x2400ff1e, 0x2400ff1e,
0x2400ff1e,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0x2400ff1e,
0x2400001e, 0x2400001e,
0x2400001e, 0x2400001e,
0xd104ff00, 0xd104ff00,
@ -1859,9 +1859,9 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0x2400001e, 0x2400001e,
0x2400001e,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0x2400001e,
0x2400ff1e, 0x2400ff1e,
0x2400001e, 0x2400001e,
0xd104ff00, 0xd104ff00,
@ -1875,9 +1875,9 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0x2400ff1e, 0x2400ff1e,
0x2400001e,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0x2400001e,
0x2400ff1e, 0x2400ff1e,
0x2400ff1e, 0x2400ff1e,
0x24000065, 0x24000065,

2
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h
View File

@ -1787,7 +1787,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81080580, 0x81080580,
0x240003c0, 0x240003c0,
0x810605c0, 0x810605c0,
0x24000b00, 0x24000c00,
0x810b1800, 0x810b1800,
0x81441800, 0x81441800,
0x2eff8383, 0x2eff8383,

8
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h
View File

@ -1658,7 +1658,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81100580, 0x81100580,
0x240003c0, 0x240003c0,
0x810605c0, 0x810605c0,
0x24000b00, 0x24000c00,
0x810b1800, 0x810b1800,
0x81441800, 0x81441800,
0x2eff8383, 0x2eff8383,
@ -1844,9 +1844,9 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd10cff00, 0xd10cff00,
0xd70bffff, 0xd70bffff,
0x2400ff1e, 0x2400ff1e,
0x2400ff1e,
0xd10cff00, 0xd10cff00,
0xd70bffff, 0xd70bffff,
0x2400ff1e,
0x2400001e, 0x2400001e,
0x2400001e, 0x2400001e,
0xd10cff00, 0xd10cff00,
@ -1860,9 +1860,9 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd10cff00, 0xd10cff00,
0xd70bffff, 0xd70bffff,
0x2400001e, 0x2400001e,
0x2400001e,
0xd10cff00, 0xd10cff00,
0xd70bffff, 0xd70bffff,
0x2400001e,
0x2400ff1e, 0x2400ff1e,
0x2400001e, 0x2400001e,
0xd10cff00, 0xd10cff00,
@ -1876,9 +1876,9 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd10cff00, 0xd10cff00,
0xd70bffff, 0xd70bffff,
0x2400ff1e, 0x2400ff1e,
0x2400001e,
0xd10cff00, 0xd10cff00,
0xd70bffff, 0xd70bffff,
0x2400001e,
0x2400ff1e, 0x2400ff1e,
0x2400ff1e, 0x2400ff1e,
0x24000065, 0x24000065,

2
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h
View File

@ -1788,7 +1788,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81100580, 0x81100580,
0x240003c0, 0x240003c0,
0x810605c0, 0x810605c0,
0x24000b00, 0x24000c00,
0x810b1800, 0x810b1800,
0x81441800, 0x81441800,
0x2eff8383, 0x2eff8383,

2
source/position_sense/hdsl/firmware/hdsl_master_icssg_sync_225_mhz_bin.h
View File

@ -1516,7 +1516,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81080580, 0x81080580,
0x240017c0, 0x240017c0,
0x810605c0, 0x810605c0,
0x24000b00, 0x24000c00,
0x810b1800, 0x810b1800,
0x81441800, 0x81441800,
0x2eff8383, 0x2eff8383,