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am64x/am243x: hdsl: Fix the QM update for safe channel 2

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- Remove increment by 1 after CRC check success on safe channel 2 data
- For CRC check failure, decrement by 8

Fixes: PINDSW-6944

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
This commit is contained in:
Dhaval Khandla 2023-09-22 18:43:53 +05:30
parent 35788f6e64
commit 2f0a4eed8a
2 changed files with 18 additions and 23 deletions
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35
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
View File

@ -1,5 +1,5 @@
const uint32_t Hiperface_DSL2_0_RTU_0[] = { const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x21077f00, 0x21077c00,
0x2eff8f8e, 0x2eff8f8e,
0x24000725, 0x24000725,
0x24041e8d, 0x24041e8d,
@ -62,7 +62,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x23032cd1, 0x23032cd1,
0x1d03c4c4, 0x1d03c4c4,
0x2302cbd1, 0x2302cbd1,
0x23059d9d, 0x23059a9d,
0x05014545, 0x05014545,
0x51074514, 0x51074514,
0x49004502, 0x49004502,
@ -636,7 +636,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x79000002, 0x79000002,
0x2400ff1e, 0x2400ff1e,
0x09017979, 0x09017979,
0x21051200, 0x21050f00,
0xd1077905, 0xd1077905,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
@ -693,7 +693,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x106d6d79, 0x106d6d79,
0x2400027b, 0x2400027b,
0x21035700, 0x21035700,
0x21043d00, 0x21043a00,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0xd1074d03, 0xd1074d03,
@ -809,7 +809,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91a91800, 0x91a91800,
0x01010000, 0x01010000,
0x81a91800, 0x81a91800,
0x21062f00, 0x21062c00,
0x20d10000, 0x20d10000,
0x117f6666, 0x117f6666,
0xc9066604, 0xc9066604,
@ -887,7 +887,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400017b, 0x2400017b,
0x2102b700, 0x2102b700,
0x2400017b, 0x2400017b,
0x21043d00, 0x21043a00,
0xd104ff00, 0xd104ff00,
0xd703ffff, 0xd703ffff,
0xd1077903, 0xd1077903,
@ -915,7 +915,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400ff1e, 0x2400ff1e,
0x09017979, 0x09017979,
0x2400017b, 0x2400017b,
0x21043d00, 0x21043a00,
0x2eff838e, 0x2eff838e,
0x24003f00, 0x24003f00,
0x81401800, 0x81401800,
@ -977,7 +977,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x686e5303, 0x686e5303,
0x24000019, 0x24000019,
0x79000002, 0x79000002,
0x23060fd1, 0x23060cd1,
0x10535300, 0x10535300,
0x10333320, 0x10333320,
0x10131340, 0x10131340,
@ -1017,15 +1017,12 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x5100c007, 0x5100c007,
0x1f058000, 0x1f058000,
0x81541800, 0x81541800,
0x2400060d, 0x2400080d,
0x040d6666, 0x040d6666,
0x23032cd1, 0x23032cd1,
0x79000017, 0x79000014,
0x1d058000, 0x1d058000,
0x81541800, 0x81541800,
0x2400010d,
0x000d6666,
0x23032cd1,
0x91541800, 0x91541800,
0x69fd6204, 0x69fd6204,
0x1f028000, 0x1f028000,
@ -1186,7 +1183,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x24003001, 0x24003001,
0xd1066b0e, 0xd1066b0e,
0x2400010d, 0x2400010d,
0x230771d1, 0x23076ed1,
0x68ab8d45, 0x68ab8d45,
0x13803b3b, 0x13803b3b,
0x913d1880, 0x913d1880,
@ -1199,7 +1196,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81531800, 0x81531800,
0x7900003b, 0x7900003b,
0x2400020d, 0x2400020d,
0x230771d1, 0x23076ed1,
0x688b8d38, 0x688b8d38,
0x8137184b, 0x8137184b,
0x13803b3b, 0x13803b3b,
@ -1242,7 +1239,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1d09c4c4, 0x1d09c4c4,
0x2400040d, 0x2400040d,
0x24003001, 0x24003001,
0x230771d1, 0x23076ed1,
0x15ff8d9c, 0x15ff8d9c,
0x69005c34, 0x69005c34,
0x51009c33, 0x51009c33,
@ -1483,7 +1480,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff, 0xd703ffff,
0x2400001e, 0x2400001e,
0x2400001e, 0x2400001e,
0x2305f6d1, 0x2305f3d1,
0x108b8b9d, 0x108b8b9d,
0x91aa1800, 0x91aa1800,
0x1f018000, 0x1f018000,
@ -1507,7 +1504,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff, 0xd703ffff,
0x2400001e, 0x2400001e,
0x2400001e, 0x2400001e,
0x2305f6d1, 0x2305f3d1,
0x91983880, 0x91983880,
0x10eeeee1, 0x10eeeee1,
0x24000061, 0x24000061,
@ -1921,5 +1918,5 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91003c82, 0x91003c82,
0x1308e2e2, 0x1308e2e2,
0x81003c82, 0x81003c82,
0x21062f00}; 0x21062c00};

6
source/position_sense/hdsl/firmware/transport.asm
View File

@ -285,16 +285,14 @@ transport_on_v_frame_2:
; set SCE2 bit in ONLINE_STATUS_2 ; set SCE2 bit in ONLINE_STATUS_2
set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2
sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
QM_SUB 6 QM_SUB 8
transport_on_v_frame_dont_update_qm_secondary_channel: transport_on_v_frame_dont_update_qm_secondary_channel:
qba transport_on_v_frame_2_exit qba transport_on_v_frame_2_exit
check_for_slave_error_on_secondary_channel: check_for_slave_error_on_secondary_channel:
; clear SCE2 bit in ONLINE_STATUS_2 ; clear SCE2 bit in ONLINE_STATUS_2
clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2
sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 sbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
;CRC was correct -> add 1 to QM ; No QM updates for CRC check success with safe channel 2
QM_ADD 1
; NOTE: QM_ADD uses REG_TMP0. Loading REG_TMP0 again here. It can be optimized.
lbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 lbco &REG_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1
;check for special character: K29.7 is sent in first byte of secondary vertical channel if slave error occured ;check for special character: K29.7 is sent in first byte of secondary vertical channel if slave error occured
; assumption: r21.b3 contains the first byte of secondary vertical channel ; assumption: r21.b3 contains the first byte of secondary vertical channel