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am64x/am243x: hdsl: Fix the reset value of PRST bit in status/event

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- Set the bit during initialization for status and event registers
- Unset the bit in status registers after link_check state

Fixes: PINDSW-6628

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
This commit is contained in:
Dhaval Khandla 2023-09-22 16:24:52 +05:30
parent b9eb2b68ae
commit 35788f6e64
4 changed files with 111 additions and 194 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
source/position_sense/hdsl/firmware/datalink.asm
View File

@ -1470,23 +1470,23 @@ is_val_FC:
qba adjustment_done
is_val_F8:
qbne is_val_F0, EXTRA_EDGE_SELF, 0xF8
sub REG_TMP0, REG_TMP0, 12
sub REG_TMP0, REG_TMP0, 12
qba adjustment_done
is_val_F0:
qbne is_val_E0, EXTRA_EDGE_SELF, 0xF0
sub REG_TMP0, REG_TMP0, 16
sub REG_TMP0, REG_TMP0, 16
qba adjustment_done
is_val_E0:
qbne is_val_C0, EXTRA_EDGE_SELF, 0xE0
sub REG_TMP0, REG_TMP0, 20
sub REG_TMP0, REG_TMP0, 20
qba adjustment_done
is_val_C0:
qbne is_val_80, EXTRA_EDGE_SELF, 0xC0
sub REG_TMP0, REG_TMP0, 24
sub REG_TMP0, REG_TMP0, 24
qba adjustment_done
is_val_80:
qbne adjustment_done,EXTRA_EDGE_SELF, 0x80
sub REG_TMP0, REG_TMP0, 28
sub REG_TMP0, REG_TMP0, 28
qba adjustment_done
adjustment_done:
sbco &REG_TMP0, MASTER_REGS_CONST, EXTRA_EDGE_TIMESTAMP, 4
@ -1570,7 +1570,6 @@ log_done1:
;HINT: we have processing time here (~168 cycles)
;check if we reset protocol
lbco &FIFO_L, MASTER_REGS_CONST, SYS_CTRL, 1
;ERROR: qbbc datalink_abort2 is not working, though no compiler error
qbbc SYS_CTRL_PRST_cleared,FIFO_L, SYS_CTRL_PRST
jmp No_long_short_msg
SYS_CTRL_PRST_cleared:
@ -1879,31 +1878,6 @@ datalink_abort_no_wait:
lbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
add REG_TMP0.b0, REG_TMP0.b0, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
; Set EVENT_PRST in EVENT register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
set REG_TMP0.w0, REG_TMP0.w0, EVENT_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2
qbbc update_events_no_int2, REG_TMP0.w2, EVENT_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int2:
; Set EVENT_S_PRST in EVENT_S register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int18, REG_TMP0.b1, EVENT_S_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int18:
; Set PRST bits in ONLINE_STATUS registers
lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
set REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST
set REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST
set REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
jmp datalink_reset
;--------------------------------------------------------------------------------------------------
;Function: switch_clk (RET_ADDR1)

56
source/position_sense/hdsl/firmware/datalink_init.asm
View File

@ -101,30 +101,48 @@ datalink_reset:
;reset SAFE_CTRL register
zero &REG_TMP0.b0, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, SAFE_CTRL, 1
; Set EVENT_PRST in EVENT_H register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
set REG_TMP0.w0, REG_TMP0.w0, EVENT_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2
qbbc update_events_no_int15, REG_TMP0.w2, EVENT_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int15:
; Set EVENT_S_PRST in EVENT_S register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int22, REG_TMP0.b1, EVENT_S_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int22:
; Initialize ONLINE_STATUS_D, ONLINE_STATUS_1 and ONLINE_STATUS_2
; In ONLINE_STATUS_D high, bit 2 is FIX0, bit 4 is FIX1 and bit 5 is FIX0
; In ONLINE_STATUS_D low, bit 0 is FIX0 and bit 3 is FIX0
lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 2
; clearing bits
ldi REG_TMP0.w0, 0
; setting bits with fix1
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_D_HIGH_BIT4_FIX1)
; setting bits with fix1 and PRST bit
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_D_HIGH_BIT4_FIX1) | (1<<ONLINE_STATUS_D_PRST)
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 2
; In ONLINE_STATUS_1 high, bit 1 is FIX0, bit 3 is FIX0 and bit 4 is FIX1
; In ONLINE_STATUS_1 low, bit 1 is FIX0, bit 3 is FIX0 and bit 4 is FIX0
lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 2
; clearing bits
ldi REG_TMP0.w0, 0
; setting bits with fix1
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_1_HIGH_BIT4_FIX1)
; setting bits with fix1 and PRST bit
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_1_HIGH_BIT4_FIX1) | (1<<ONLINE_STATUS_1_PRST)
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 2
; In ONLINE_STATUS_2 high, bit 1 is FIX0, bit 3 is FIX0, bit 4 is FIX1 and bit7 is FIX1
; In ONLINE_STATUS_2 low, bits 0, 1, 3, 4, 5 are FIX0
lbco &REG_TMP0.w0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 2
; clearing bits
ldi REG_TMP0.w0, 0
; setting bits with fix1
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_2_HIGH_BIT4_FIX1)
; setting bits with fix1 and PRST bit
or REG_TMP0.w0, REG_TMP0.w0, (1<<ONLINE_STATUS_2_HIGH_BIT4_FIX1) | (1<<ONLINE_STATUS_2_PRST)
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 2
;check for SPOL and configure eCAP accordingly
ldi REG_TMP1, (ECAP+ECAP_ECCTL1)
@ -560,24 +578,6 @@ datalink_abort2_no_wait:
lbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
add REG_TMP0.b0, REG_TMP0.b0, 1
sbco &REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
; Set EVENT_PRST in EVENT_H register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
set REG_TMP0.w0, REG_TMP0.w0, EVENT_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2
qbbc update_events_no_int15, REG_TMP0.w2, EVENT_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ
update_events_no_int15:
; Set EVENT_S_PRST in EVENT_S register
lbco &REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST
;save events
sbco &REG_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1
qbbc update_events_no_int22, REG_TMP0.b1, EVENT_S_PRST
; generate interrupt
ldi r31.w0, PRU0_ARM_IRQ4
update_events_no_int22:
;we need rel. jump here
qba datalink_reset
;--------------------------------------------------------------------------------------------------
@ -627,6 +627,14 @@ datalink_line_check:
qblt datalink_line_check, LOOP_CNT.b1, 0
;qba datalink_line_check
datalink_line_check_end:
; Clear PRST bits in ONLINE_STATUS registers
lbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
clr REG_TMP0.w0, REG_TMP0.w0, ONLINE_STATUS_D_PRST
clr REG_TMP0.w2, REG_TMP0.w2, ONLINE_STATUS_1_PRST
clr REG_TMP1.w0, REG_TMP1.w0, ONLINE_STATUS_2_PRST
sbco &REG_TMP0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 6
;--------------------------------------------------------------------------------------------------
;State ID REQ
;save delay to master registers after all checks were successful

2
source/position_sense/hdsl/firmware/defines.inc
View File

@ -34,7 +34,7 @@
; bit7..4 major number
FIRMWARE_VERSION_MAJOR .set 0x0
; bit3..0 minor number
FIRMWARE_VERSION_MINOR .set 0x5
FIRMWARE_VERSION_MINOR .set 0x6
ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0))

211
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
View File

@ -1,60 +1,5 @@
/*
* hdsl_master_icssg_multichannel_ch0_bin.h
*
*
* Copyright (c) 2021-2023, Texas Instruments Incorporated
* All rights reserved not granted herein.
*
* Limited License.
*
* Texas Instruments Incorporated grants a world-wide, royalty-free,
* non-exclusive license under copyrights and patents it now or hereafter
* owns or controls to make, have made, use, import, offer to sell and sell ("Utilize")
* this software subject to the terms herein. With respect to the foregoing patent
* license, such license is granted solely to the extent that any such patent
* is necessary to Utilize the software alone. The patent license shall not apply to any
* combinations which include this software, other than combinations with devices
* manufactured by or for TI ('TI Devices'). No hardware patent is licensed hereunder.
*
* Redistributions must preserve existing copyright notices and reproduce this license
* (including the above copyright notice and the disclaimer and (if applicable) source
* code license limitations below) in the documentation and/or other materials provided
* with the distribution
*
* Redistribution and use in binary form, without modification, are permitted provided
* that the following conditions are met:
* No reverse engineering, decompilation, or disassembly of this software is
* permitted with respect to any software provided in binary form.
* Any redistribution and use are licensed by TI for use only with TI Devices.
* Nothing shall obligate TI to provide you with source code for the software
* licensed and provided to you in object code.
*
* If software source code is provided to you, modification and redistribution of the
* source code are permitted provided that the following conditions are met:
* Any redistribution and use of the source code, including any resulting derivative works,
* are licensed by TI for use only with TI Devices.
* Any redistribution and use of any object code compiled from the source code and
* any resulting derivative works, are licensed by TI for use only with TI Devices.
*
* Neither the name of Texas Instruments Incorporated nor the names of its suppliers
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* DISCLAIMER.
*
* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND
* TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x21078900,
0x21077f00,
0x2eff8f8e,
0x24000725,
0x24041e8d,
@ -105,19 +50,19 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x5101450a,
0x2400040d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000009,
0x69014508,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000004,
0x2400010d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x1d03c4c4,
0x2302cbd1,
0x2305ac9d,
0x23059d9d,
0x05014545,
0x51074514,
0x49004502,
@ -146,7 +91,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400001e,
0x7f0000c5,
0x24002005,
0x230349d1,
0x23033ad1,
0x24000080,
0x2405a4eb,
0x2eff8992,
@ -159,7 +104,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f6,
0x24001d05,
0xc918ff00,
@ -171,7 +116,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0105f6,
0xc918ff00,
0x101f1f00,
@ -272,7 +217,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -291,7 +236,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -314,7 +259,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230361d1,
0x230352d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -339,7 +284,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -358,7 +303,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230361d1,
0x230352d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -381,7 +326,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230361d1,
0x230352d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -398,7 +343,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x20d10000,
0x24000605,
0x2eff8283,
0x230349d1,
0x23033ad1,
0x240000c0,
0x2400002d,
0x2300d0d1,
@ -452,32 +397,32 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f04c4c4,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000006,
0xc9005005,
0x51fd0304,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0xc9017005,
0x2400010d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000005,
0xc9015004,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0xc9027004,
0x2400010d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x111870e0,
0x5100e006,
0x1f03c4c4,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000008,
0xc9035002,
0x69fd2403,
@ -485,7 +430,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x51fd0404,
0x2400020d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x2400052d,
0x24000605,
0x230113d1,
@ -509,7 +454,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f05c4c4,
0x2400080d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x14637878,
0x69014502,
0x15ff7878,
@ -575,14 +520,14 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400ff1e,
0x2103ac00,
0x21039d00,
0x69074507,
0xc901c405,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x21040000,
0x2103f100,
0x51000c2d,
0x51015b04,
0x100c0c02,
@ -691,7 +636,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21052100,
0x21051200,
0xd1077905,
0xd104ff00,
0xd703ffff,
@ -743,12 +688,12 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd1047905,
0x106d6d79,
0x2400037b,
0x21036600,
0x21035700,
0x2102b600,
0x106d6d79,
0x2400027b,
0x21036600,
0x21044c00,
0x21035700,
0x21043d00,
0xd104ff00,
0xd703ffff,
0xd1074d03,
@ -855,7 +800,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10d1d18b,
0x2400040d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x108b8bd1,
0x810c3c80,
0x20d10000,
@ -864,28 +809,13 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91505880,
0x1f008080,
0x1f00c0c0,
0x1f008181,
0x81505880,
0x21063e00,
0x21062f00,
0x20d10000,
0x117f6666,
0xc9066604,
0x24000066,
0x81031866,
0x7f0000e6,
0x7f0000f5,
0x710f6602,
0x24000f66,
0x590e6604,
@ -957,7 +887,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400017b,
0x2102b700,
0x2400017b,
0x21044c00,
0x21043d00,
0xd104ff00,
0xd703ffff,
0xd1077903,
@ -985,7 +915,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400ff1e,
0x09017979,
0x2400017b,
0x21044c00,
0x21043d00,
0x2eff838e,
0x24003f00,
0x81401800,
@ -1013,7 +943,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81521802,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x7900002e,
0xd104ff00,
0xd703ffff,
@ -1021,7 +951,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400ff1e,
0x2400010d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x69fd7309,
0x913d1880,
0x1f040000,
@ -1047,7 +977,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x686e5303,
0x24000019,
0x79000002,
0x23061ed1,
0x23060fd1,
0x10535300,
0x10333320,
0x10131340,
@ -1059,7 +989,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x2103f300,
0x2103e400,
0x31010004,
0xd104ff00,
0xd703ffff,
@ -1089,13 +1019,13 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81541800,
0x2400060d,
0x040d6666,
0x23033bd1,
0x23032cd1,
0x79000017,
0x1d058000,
0x81541800,
0x2400010d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x91541800,
0x69fd6204,
0x1f028000,
@ -1256,7 +1186,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x24003001,
0xd1066b0e,
0x2400010d,
0x23077bd1,
0x230771d1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
@ -1269,7 +1199,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81531800,
0x7900003b,
0x2400020d,
0x23077bd1,
0x230771d1,
0x688b8d38,
0x8137184b,
0x13803b3b,
@ -1312,7 +1242,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1d09c4c4,
0x2400040d,
0x24003001,
0x23077bd1,
0x230771d1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1553,7 +1483,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x230605d1,
0x2305f6d1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
@ -1577,7 +1507,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x230605d1,
0x2305f6d1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1666,11 +1596,11 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81080580,
0x240003c0,
0x810605c0,
0x24000500,
0x24000600,
0x810b1800,
0x81441800,
0x2eff8383,
0x2303a49d,
0x2303959d,
0x24000866,
0x2400000c,
0x2400002c,
@ -1679,17 +1609,27 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81001800,
0x2eff8000,
0x81351800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x91501880,
0x24000080,
0x13108080,
0x13118080,
0x81501880,
0x91521880,
0x24000080,
0x13108080,
0x13118080,
0x81521880,
0x91541880,
0x24000080,
0x13108080,
0x13118080,
0x81541880,
0x240128e1,
0x90e13382,
@ -1895,7 +1835,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10656546,
0x05012525,
0x4f002560,
0x79000013,
0x79000009,
0xd118fe04,
0xd105ff00,
0x31080002,
@ -1903,23 +1843,13 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x91043880,
0x1f008080,
0x81041880,
0xc900c002,
0x2400229f,
0x913d1880,
0x1f020000,
0x813d1800,
0xc9022002,
0x2400269f,
0x7d0000fb,
0x24000925,
0x24001b8d,
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010ded,
0x6f010df7,
0x05012525,
0x4f0025fa,
0x24001025,
@ -1927,18 +1857,23 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2301d19d,
0x23005b9d,
0x230095d1,
0x6f010de1,
0x6f010deb,
0x05012525,
0x4f0025fa,
0x91505880,
0x1d008080,
0x1d00c0c0,
0x1d008181,
0x81505880,
0x810a1846,
0x24001d8d,
0x2301d19d,
0x2301569d,
0x6e0403da,
0x6e2423d9,
0x6e0403df,
0x6e2423de,
0x110f4300,
0x0b044320,
0x6e2000d6,
0x6e2000db,
0x10848480,
0x10434340,
0x10404001,
@ -1947,7 +1882,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x810d3801,
0x2400000d,
0x000d6666,
0x23033bd1,
0x23032cd1,
0x1f08c4c4,
0x110fe05d,
0x01085d5d,
@ -1986,5 +1921,5 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x21063e00};
0x21062f00};