External/motor-control-sdk
8
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

am243x: docs: Update bug list for 9.0 release

Browse Source 
Fixes: PINDSW-6925

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
This commit is contained in:
Dhaval Khandla 2023-09-17 13:53:28 +05:30
parent af246e93a6
commit 2af7fde88a
1 changed files with 35 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

77
docs_src/docs/api_guide/device/am243x/release_notes_09_00_00.md
View File

@ -88,6 +88,13 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
<th> Applicable Releases <th> Applicable Releases
<th> Resolution/Comments <th> Resolution/Comments
</tr> </tr>
<tr>
<td> PINDSW-5538
<td> HDSL: Long message not working with multi-channel application
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr> <tr>
<td> PINDSW-5651 <td> PINDSW-5651
<td> HDSL: Multi-turn bits of fast position do not contain correct data <td> HDSL: Multi-turn bits of fast position do not contain correct data
@ -95,6 +102,13 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
<td> - <td> -
<td> - <td> -
</tr> </tr>
<tr>
<td> PINDSW-5681
<td> EnDat: Recovery Time not correct for 2.1 commands
<td> Position Sense EnDat
<td> -
<td> -
</tr>
<tr> <tr>
<td> PINDSW-5689 <td> PINDSW-5689
<td> HDSL: High deviation in fast position when encoder shaft is fixed <td> HDSL: High deviation in fast position when encoder shaft is fixed
@ -116,6 +130,13 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
<td> - <td> -
<td> - <td> -
</tr> </tr>
<tr>
<td> PINDSW-6489
<td> HDSL: Offsets for ONLINE STATUS registers in C structure are not correct
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr> <tr>
<td> PINDSW-6492 <td> PINDSW-6492
<td> HDSL: Protocol reset is not working <td> HDSL: Protocol reset is not working
@ -123,6 +144,13 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
<td> - <td> -
<td> - <td> -
</tr> </tr>
<tr>
<td> PINDSW-6526
<td> HDSL: FREL/FRES bits in EVENT/EVENT_S registers are not sticky
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr> <tr>
<td> PINDSW-6530 <td> PINDSW-6530
<td> HDSL: QMLW bit not working in ONLINE STATUS registers <td> HDSL: QMLW bit not working in ONLINE STATUS registers
@ -130,20 +158,6 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
<td> - <td> -
<td> - <td> -
</tr> </tr>
<tr>
<td> PINDSW-5538
<td> HDSL: Long message not working with multi-channel application
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-6489
<td> HDSL: Offsets for ONLINE STATUS registers in C structure are not correct
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr> <tr>
<td> PINDSW-6607 <td> PINDSW-6607
<td> %SDFM: NULL pointer dereferenced in \ref SDFM_getFilterData <td> %SDFM: NULL pointer dereferenced in \ref SDFM_getFilterData
@ -151,27 +165,6 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
<td> - <td> -
<td> - <td> -
</tr> </tr>
<tr>
<td> PINDSW-6526
<td> HDSL: FREL/FRES bits in EVENT/EVENT_S registers are not sticky
<td> Position Sense HDSL
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-5681
<td> EnDat: Recovery Time not correct for 2.1 commands
<td> Position Sense EnDat
<td> -
<td> -
</tr>
<tr>
<td> PINDSW-5681
<td> %SDFM: Sampling does not work with EPWM as %SDFM clock
<td> Current Sense %SDFM
<td> -
<td> -
</tr>
</table> </table>
## Known Issues ## Known Issues
@ -184,13 +177,6 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
<th> Applicable Releases <th> Applicable Releases
<th> Workaround <th> Workaround
</tr> </tr>
<tr>
<td> PINDSW-5690
<td> HDSL: EDGE register is not updated
<td> Position Sense HDSL
<td> 9.0 onwards
<td> -
</tr>
<tr> <tr>
<td> PINDSW-5537 <td> PINDSW-5537
<td> HDSL not working with 225 MHz PRU-ICSSG Core Clock Frequency <td> HDSL not working with 225 MHz PRU-ICSSG Core Clock Frequency
@ -198,6 +184,13 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
<td> 9.0 onwards <td> 9.0 onwards
<td> Use 300 MHz frequency for PRU-ICSSG Core Clock <td> Use 300 MHz frequency for PRU-ICSSG Core Clock
</tr> </tr>
<tr>
<td> PINDSW-5690
<td> HDSL: EDGE register is not updated
<td> Position Sense HDSL
<td> 9.0 onwards
<td> -
</tr>
<tr> <tr>
<td> PINDSW-6486 <td> PINDSW-6486
<td> HDSL: RSSI register shows higher values than expected for a non-noisy setup <td> HDSL: RSSI register shows higher values than expected for a non-noisy setup