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ECAT_Slave_in_ПЧ2П_c402
0.8
Реализация EtherCAT Slave для CM TMS320F28388D
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ECAT_Slave_in_ПЧ2П_c402
0.8
Реализация EtherCAT Slave для CM TMS320F28388D
|
EtherCAT Slave Controller related defines and Types. Подробнее...
#include "ecat_def.h"Структуры данных | |
| struct | STRUCT_PACKED_START |
| Data structure to handle the process data transmitted via 0x1A00 (csp/csv TxPDO) Подробнее... | |
Макросы | |
| #define | SIZEOF_SM_REGISTER 8 |
| Each SyncManger has 8Byte Configuration/Status Registers. Подробнее... | |
| #define | MAX_NO_OF_SYNC_MAN 16 |
| Maximum Number of SyncManager channels supported by an ESC. Подробнее... | |
| #define | BL_PAGE_SIZE 512 |
| #define | ESC_INFO_OFFSET 0x0000 |
| ESC information registers startoffset. Подробнее... | |
| #define | ESC_COMM_INFO_OFFSET 0x0004 |
| Communication information registers startoffset. Подробнее... | |
| #define | ESC_DPRAM_SIZE_OFFSET 0x0006 |
| Register Description: Size of the supported DPRAM in KB. Подробнее... | |
| #define | ESC_SM_CHANNELS_OFFSET 0x0005 |
| Register Description: Number of supported SyncManager channels (or entities) of the EtherCAT Slave Controller. Подробнее... | |
| #define | ESC_FEATURES_OFFSET 0x0008 |
| Register indicating ESC features. Подробнее... | |
| #define | ESC_DC_32BIT_MASK 0x00000008 |
| register 0x0008.3 indicates if the DC Unit supports 32Bit/64Bit DC Подробнее... | |
| #define | ESC_SLAVE_ADDRESS_OFFSET 0x0010 |
| Register Description: Address used for node addressing (FPxx commands) Подробнее... | |
| #define | ESC_AL_CONTROL_OFFSET 0x0120 |
| Register Description: Initiate State Transition of the Device State Machine. Подробнее... | |
| #define | ESC_AL_STATUS_OFFSET 0x0130 |
| Register Description: Actual State of the Device State Machine. Подробнее... | |
| #define | ESC_AL_STATUS_CODE_OFFSET 0x0134 |
| Register Description: AL Status Code. Подробнее... | |
| #define | ESC_RUN_LED_OVERRIDE 0x0138 |
| Register Description: Set Ecat Run indication via ESC. (not all ESC types support this feature) Подробнее... | |
| #define | ESC_ERROR_LED_OVERRIDE 0x0139 |
| Register Description: Set Ecat Error indication via ESC. (not all ESC types support this feature) Подробнее... | |
| #define | ESC_PDI_CONTROL_OFFSET 0x0140 |
| Register Description: Specifies the process data interface. Подробнее... | |
| #define | ESC_DEVICE_EMULATION 0x0100 |
| Device emulation bit. Подробнее... | |
| #define | ESC_PDI_CONFIGURATION 0x0151 |
| Register Description: PDI configuration register (values defined by the ESC configuration data) Подробнее... | |
| #define | ESC_SYNC0_MAPPED_TO_ALEVENT 0x08 |
| bit indicating if the Sync0 event is mapped to the AL Event register Подробнее... | |
| #define | ESC_SYNC1_MAPPED_TO_ALEVENT 0x80 |
| bit indicating if the Sync1 event is mapped to the AL Event register Подробнее... | |
| #define | ESC_AL_EVENTMASK_OFFSET 0x0204 |
| Register Description: AL Event masking of the AL Event Request register Events for mapping to PDI IRQ signal. Подробнее... | |
| #define | ESC_AL_EVENT_OFFSET 0x0220 |
| Register Description: "Mirror" register for ESC events. Подробнее... | |
| #define | ESC_WD_DIVIDER_OFFSET 0x0400 |
| Register Description: Number of 25 MHz tics (minus 2) that represents the basic watchdog increment. (Default value is 100us = 2498) Подробнее... | |
| #define | ESC_PD_WD_TIME 0x0420 |
| Register Description: Number of basic watchdog increments (Default value with Watchdog divider 100us means 100ms Watchdog) Подробнее... | |
| #define | ESC_PD_WD_STATE 0x0440 |
| Register Description: Watchdog Status of Process Data (triggered by SyncManagers) Подробнее... | |
| #define | ESC_PD_WD_TRIGGER_MASK 0x0001 |
| Trigger state of the process data watchdog. Подробнее... | |
| #define | ESC_EEPROM_CONFIG_OFFSET 0x0500 |
| Register Description: EEPROM Access Configuration. Подробнее... | |
| #define | ESC_EEPROM_ASSIGN_TO_PDI_MASK 0x0001 |
| Description (0x500.0): PDI has EEPROM control. Подробнее... | |
| #define | ESC_EEPROM_LOCKED_BY_PDI_MASK 0x0100 |
| Description (0x500.8): PDI locked EEPROM access. Подробнее... | |
| #define | ESC_EEPROM_CONTROL_OFFSET 0x0502 |
| #define | ESC_EEPROM_SUPPORTED_READBYTES_MASK 0x0040 |
| Description (0x502.6): Supported number of EEPROM read bytes: 0-> 4 Bytes; 1 -> 8 Bytes. Подробнее... | |
| #define | ESC_EEPROM_CMD_MASK 0x0700 |
| Description (0x502.8:10): Command bit mask. Подробнее... | |
| #define | ESC_EEPROM_CMD_READ_MASK 0x0100 |
| Description (0x502.8): Currently executed read command. Подробнее... | |
| #define | ESC_EEPROM_CMD_WRITE_MASK 0x0200 |
| Description (0x502.9): Initialize Write Command. Подробнее... | |
| #define | ESC_EEPROM_CMD_RELOAD_MASK 0x0400 |
| Description (0x502.10): Trigger EEPROM reload. Подробнее... | |
| #define | ESC_EEPROM_ERROR_MASK 0x7800 |
| Description : Mask all EEPROM error bits; Checksum error (0x0502.11); EEPROM not loaded (0x0502.12); Missing EEPROM Acknowledge (0x0502.13); Write Error (0x0502.14) Подробнее... | |
| #define | ESC_EEPROM_ERROR_CRC 0x0800 |
| Description (0x502.11): EEPROM CRC Error. Подробнее... | |
| #define | ESC_EEPROM_ERROR_LOAD 0x1000 |
| Description (0x502.11): EEPROM loading status (0 = OK) Подробнее... | |
| #define | ESC_EEPROM_ERROR_CMD_ACK 0x2000 |
| Description (0x502.13): EEPROM Acknowledge/Command. Подробнее... | |
| #define | ESC_EEPROM_BUSY_MASK 0x8000 |
| Description (0x502.15): EEPROM Busy. Подробнее... | |
| #define | ESC_EEPROM_ADDRESS_OFFSET 0x0504 |
| #define | ESC_EEPROM_DATA_OFFSET 0x0508 |
| #define | ESC_SYNCMAN_REG_OFFSET 0x0800 |
| Register Description: Start address of the SyncManager Configuration/Staus registers. Подробнее... | |
| #define | ESC_SYNCMAN_CONTROL_OFFSET 0x0804 |
| Register Description: SyncManager Setting Register. Подробнее... | |
| #define | ESC_SYNCMAN_STATUS_OFFSET 0x0805 |
| Register Description: SyncManager Status Register. Подробнее... | |
| #define | ESC_SYNCMAN_ACTIVE_OFFSET 0x0806 |
| Register Description: SyncManager Activation Register. Подробнее... | |
| #define | ESC_SM_PDICONTROL_OFFSET 0x0807 |
| #define | ESC_SYSTEMTIME_OFFSET 0x0910 |
| Register Description: Local copy of the System Time. Подробнее... | |
| #define | ESC_DC_UNIT_CONTROL_OFFSET 0x0980 |
| Register Description: Control registers for Cycle and Sync Unit (can be predefined with the "AssignActivate" Element in the device description, for further information see ETG.2000) Подробнее... | |
| #define | ESC_DC_SYNC_ACTIVATION_OFFSET 0x0981 |
| Register Description: Sync Configuration. Подробнее... | |
| #define | ESC_DC_SYNC_UNIT_ACTIVE_MASK 0x01 |
| Description (0x981.0): Sync Out Unit is activated. Подробнее... | |
| #define | ESC_DC_SYNC0_ACTIVE_MASK 0x02 |
| Description (0x981.1): Sync0 generation is activated. Подробнее... | |
| #define | ESC_DC_SYNC1_ACTIVE_MASK 0x04 |
| Description (0x981.2): Sync1 generation is activated. Подробнее... | |
| #define | ESC_DC_SYNC_UNIT_AUTO_ACTIVE_MASK 0x08 |
| Description (0x980.11): Sync Out Unit is activated automatic when System time was written. Подробнее... | |
| #define | ESC_DC_SYNC_STATUS 0x098C |
| Register Description: register 0x98E and 0x98F reflecting the status of Sync0 and Sync1. Подробнее... | |
| #define | ESC_DC_SYNC0_CYCLETIME_OFFSET 0x09A0 |
| Register Description: 32Bit Time between two consecutive SYNC0 pulses in ns. Подробнее... | |
| #define | ESC_DC_SYNC1_CYCLETIME_OFFSET 0x09A4 |
| Register Description: 32Bit Time between two consecutive SYNC1 pulses in ns. Подробнее... | |
| #define | SM_SETTING_CONTROL_OFFSET 0 |
| Offset to value of register 0x0804. Подробнее... | |
| #define | SM_SETTING_MODE_MASK 0x02 |
| SyncManager mode mask. Подробнее... | |
| #define | SM_SETTING_MODE_THREE_BUFFER_VALUE 0x00 |
| SyncManager 3Buffer mode value. Подробнее... | |
| #define | SM_SETTING_MODE_ONE_BUFFER_VALUE 0x02 |
| SyncManager 1Buffer mode value. Подробнее... | |
| #define | SM_SETTING_DIRECTION_MASK 0x0C |
| SyncManager direction mask. Подробнее... | |
| #define | SM_SETTING_DIRECTION_READ_VALUE 0x00 |
| SyncManager read direction. Подробнее... | |
| #define | SM_SETTING_DIRECTION_WRITE_VALUE 0x04 |
| SyncManager write direction. Подробнее... | |
| #define | SM_SETTING_WATCHDOG_VALUE 0x40 |
| SyncManager watchdog value. Подробнее... | |
| #define | SM_SETTING_STATUS_OFFSET 1 |
| Offset to value of register 0x0805. Подробнее... | |
| #define | SM_STATUS_MBX_BUFFER_FULL 0x08 |
| Indicates in one buffer mode if buffer was completely written (based on "ESC_SYNCMAN_STATUS_OFFSET") Подробнее... | |
| #define | SM_SETTING_ACTIVATE_OFFSET 2 |
| Offset to value of register 0x0806. Подробнее... | |
| #define | SM_SETTING_ENABLE_VALUE 0x01 |
| SyncManager enable. Подробнее... | |
| #define | SM_SETTING_REPAET_REQ_MASK 0x02 |
| SyncManager Repeat request. Подробнее... | |
| #define | SM_SETTING_REPEAT_REQ_SHIFT 0 |
| SyncManager Repeat request shift. Подробнее... | |
| #define | SM_SETTING_PDICONTROL_OFFSET 3 |
| Offset to value of register 0x0807. Подробнее... | |
| #define | SM_SETTING_PDI_DISABLE 0x01 |
| Bit0 of register 0x0807 (if 1 SM is disabled from PDI) Подробнее... | |
| #define | SM_SETTING_REPEAT_ACK 0x02 |
| Bit1 of register 0x0807. Подробнее... | |
Определения типов | |
| typedef struct STRUCT_PACKED_START | TSYNCMAN |
| SyncManager register structure. Подробнее... | |
EtherCAT Slave Controller related defines and Types.
Changes to version V5.01:
V5.10 ESC1: Update address register offset for 32Bit ESC access
V5.10 ESC2: Check if defined SM settings do not exceed the available DPRAM range (in error case AL Status 0x14 is returned)
V5.10 ESC3: Handle DC cControl register values in case of 32Bit ESC access (a Sync activation mask need to defined/used)
Changes to version - :
V5.01 : Start file change log
См. определение в файле esc.h
| #define SM_SETTING_ACTIVATE_OFFSET 2 |
| #define SM_SETTING_CONTROL_OFFSET 0 |
| #define SM_SETTING_DIRECTION_MASK 0x0C |
| #define SM_SETTING_DIRECTION_READ_VALUE 0x00 |
| #define SM_SETTING_DIRECTION_WRITE_VALUE 0x04 |
| #define SM_SETTING_MODE_ONE_BUFFER_VALUE 0x02 |
| #define SM_SETTING_MODE_THREE_BUFFER_VALUE 0x00 |
| #define SM_SETTING_PDI_DISABLE 0x01 |
| #define SM_SETTING_PDICONTROL_OFFSET 3 |
| #define SM_SETTING_REPAET_REQ_MASK 0x02 |
| #define SM_SETTING_REPEAT_ACK 0x02 |
| #define SM_SETTING_REPEAT_REQ_SHIFT 0 |
| #define SM_SETTING_STATUS_OFFSET 1 |
| #define SM_SETTING_WATCHDOG_VALUE 0x40 |
1.9.1