432 lines
16 KiB
C
432 lines
16 KiB
C
//###########################################################################
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//
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// FILE: cpu1bootrom.h
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//
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// TITLE: BootROM Definitions.
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//
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//###########################################################################
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// $TI Release: F280013x Support Library v4.03.00.00 $
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// $Release Date: 02-02-2023 $
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// $Copyright:
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// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.co/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef C_BOOTROM_H_
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#define C_BOOTROM_H_
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#include <stdint.h>
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#include "hw_types.h"
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#include "hw_memmap.h"
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#include "sysctl.h"
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#include "cpu.h"
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//#include "flash.h"
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//#include "hw_flash_command.h"
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#include "hw_dcsm.h"
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#include "pin_map.h"
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#include "gpio.h"
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#include "spi.h"
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#include "dcc.h"
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//#include "cpu1brom_boot_modes.h"
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//#include "cpu1brom_escape_point_table.h"
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//#include "cpu1brom_pbist.h"
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//#include "hw_memcfg.h"
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//#include "cpu1brom_trims.h"
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//#include "bootloader_can.h"
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//#include "bootloader_i2c.h"
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//#include "bootloader_parallel.h"
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//#include "bootloader_sci.h"
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//#include "bootloader_spi.h"
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//
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//Start Address of Boot ROM
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//
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#define ROM_START_ADDRESS 0x3F9800UL
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//
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//Length of ROM in KB
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//
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#define ROM_REGION_LENGTH 64UL
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#define RAM_LSX_NOT_DONE 0x0U
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#define BROM_PLL_CONFIG_ERROR 0xFFFFU
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#define BROM_PLL_CONFIG_SUCCESS 0x0U
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#define EFUSE_SINGLE_BIT_ERROR (0x15UL)
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//
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// Flash Configurations
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//
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#define CPU1_FLASH_15MHZ_RWAIT (0x3UL)
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#define CPU1_FLASH_DEFAULT_RWAIT (0xFUL)
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#define CPU1_FLASH_15MHZ_TRIMENGRRWAIT (0x4UL)
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#define CPU1_FLASH_DEFAULT_TRIMENGRRWAIT (0xFUL)
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//When the ROM is run with an emulator connected, these four addresses are used
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//to emulate OTP configuration.
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#define EMU_BOOTPIN_CONFIG 0xD00 //Equivalent to GPREG1
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#define EMU_BOOT_GPREG2 0xD02 //Equivalent to GPREG2
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#define EMU_BOOTDEF_LOW 0xD04 //Equivalent to GPREG3
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#define EMU_BOOTDEF_HIGH 0xD06 //Equivalent to BOOTCTRL
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//Emulation boot pin configuration fields. Currently, only EMU_BOOTPIN_CONFIG_KEY
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//is used.
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#define EMU_BOOTPIN_CONFIG_KEY ((HWREG(EMU_BOOTPIN_CONFIG) & (uint32_t)0xFF000000UL) >> 24)
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#define EMU_BOOTDEF_L(x) ((HWREG(EMU_BOOTDEF_LOW) & ((uint32_t)0xFFU << (8U*x))) >> (8U*x))
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#define EMU_BOOTDEF_H(x) ((HWREG(EMU_BOOTDEF_HIGH) & ((uint32_t)0xFFU << (8U*x))) >> (8U*x))
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//
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// Standalone Boot Defines
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//
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//
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// DCSM OTP Boot Configuration Registers
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//
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#define Z1_OTP_BOOTPIN_CONFIG (DCSM_Z1_BASE + (uint32_t)DCSM_O_Z1_GPREG1)
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#define Z1_OTP_BOOT_GPREG2 (DCSM_Z1_BASE + (uint32_t)DCSM_O_Z1_GPREG2)
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#define Z1_OTP_BOOTDEF_LOW (DCSM_Z1_BASE + (uint32_t)DCSM_O_Z1_GPREG3)
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#define Z1_OTP_BOOTDEF_HIGH (DCSM_Z1_BASE + (uint32_t)DCSM_O_Z1_GPREG4)
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#define Z2_OTP_BOOTPIN_CONFIG (DCSM_Z2_BASE + (uint32_t)DCSM_O_Z2_GPREG1)
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#define Z2_OTP_BOOT_GPREG2 (DCSM_Z2_BASE + (uint32_t)DCSM_O_Z2_GPREG2)
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#define Z2_OTP_BOOTDEF_LOW (DCSM_Z2_BASE + (uint32_t)DCSM_O_Z2_GPREG3)
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#define Z2_OTP_BOOTDEF_HIGH (DCSM_Z2_BASE + (uint32_t)DCSM_O_Z2_GPREG4)
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//
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//DCSM Z1 CSM Key Mask Values
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//
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#define DCSM_Z1_CSMKEY0_MASK 0xFFFFFFFFUL
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#define DCSM_Z1_CSMKEY1_MASK 0xFFFFFFFFUL
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#define DCSM_Z1_CSMKEY2_MASK 0xFFFFFFFFUL
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#define DCSM_Z1_CSMKEY3_MASK 0xFFFFFFFFUL
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//
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//DCSM Z2 CSM Key Mask Values
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//
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#define DCSM_Z2_CSMKEY0_MASK 0xFFFFFFFFUL
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#define DCSM_Z2_CSMKEY1_MASK 0xFFFFFFFFUL
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#define DCSM_Z2_CSMKEY2_MASK 0xFFFFFFFFUL
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#define DCSM_Z2_CSMKEY3_MASK 0xFFFFFFFFUL
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/*
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Z1-GPREG2[31:24] => VALIDITY_KEY (=0x5A);
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Z1-GPREG2[23:8] => RESERVED; no usage defined yet.
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Z1-GPREG2[7:6] => 00 - Run PBIST with PLL disabled (10MHz internal oscillator)
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(includes CRC test on 64KB unsecure ROM)
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01 - Run PBIST at 115MHz
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10 - Run PBIST at 57.5MHz
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11 - Do not run PBIST
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Z1-GPREG2[5:4] => ERROR_STS_PIN config; this tells which GPIO pin is supposed to be used as ERROR_PIN and boot ROM configures the mux as such for the said pin.
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0 - GPIO24, MUX Option 13
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1 - GPIO28, MUX Option 13
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2 - GPIO29, MUX Option 13
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3 - ERROR_STS function Disable (default)
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Z1-GPREG2[3:0] => CJTAGNODEID[3:0];
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boot ROM takes this values and programs the lower 4 bits of the CJTAGNODEID register.
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*/
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#define HWREAD_Z1_OTP_BOOT_GPREG2_KEY ((HWREG(Z1_OTP_BOOT_GPREG2) & (uint32_t)0xFF000000UL) >> 24U)
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#define HWREAD_Z2_OTP_BOOT_GPREG2_KEY ((HWREG(Z2_OTP_BOOT_GPREG2) & (uint32_t)0xFF000000UL) >> 24U)
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#define ERRORSTS_OTP_VALUE_Z1 ((HWREG(Z1_OTP_BOOT_GPREG2) & (uint32_t)0x00000030UL) >> 4U)
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#define ERRORSTS_OTP_VALUE_Z2 ((HWREG(Z2_OTP_BOOT_GPREG2) & (uint32_t)0x00000030UL) >> 4U)
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#define ERRORSTS_PIN_NUMBER_1 24UL
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#define ERRORSTS_PIN_NUMBER_2 28UL
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#define ERRORSTS_PIN_NUMBER_3 29UL
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#define ERRORSTS_PIN_NUMBER_INVALID 0xFFFFFFFFUL
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#define ERRORSTS_PIN_24 0x0UL
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#define ERRORSTS_PIN_28 0x1UL
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#define ERRORSTS_PIN_29 0x2UL
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#define GPREG2_KEY 0x5AU
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#define GPREG2_PBIST_RUN_PLL_BYPASS 0x0UL
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#define GPREG2_PBIST_RUN_SYSCLK_95MHZ 0x1UL
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#define GPREG2_PBIST_RUN_SYSCLK_47_5MHZ 0x2UL
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#define GPREG2_PBIST_DISABLED 0x3UL
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#define PBIST_CHECKSUM_SUCCESS 0x0U
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//
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// Get key to validate Z1 OTP BOOTPIN_CONFIG
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//
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#define HWREAD_Z1_OTP_BOOTPIN_CONFIG_KEY ((HWREG(Z1_OTP_BOOTPIN_CONFIG) & (uint32_t)0xFF000000UL) >> 24U)
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#define HWREAD_Z2_OTP_BOOTPIN_CONFIG_KEY ((HWREG(Z2_OTP_BOOTPIN_CONFIG) & (uint32_t)0xFF000000UL) >> 24U)
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//
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// Standalone macros to extract boot definition from BOOTDEF table at
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// specified index
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//
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#define HWREAD_Z1_OTP_BOOTDEF_L(x) ((HWREG(Z1_OTP_BOOTDEF_LOW) & ((uint32_t)0xFFUL << (8UL*(x)))) >> (8UL*(x)))
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#define HWREAD_Z1_OTP_BOOTDEF_H(x) ((HWREG(Z1_OTP_BOOTDEF_HIGH) & ((uint32_t)0xFFUL << (8UL*(x)))) >> (8UL*(x)))
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#define HWREAD_Z2_OTP_BOOTDEF_L(x) ((HWREG(Z2_OTP_BOOTDEF_LOW) & ((uint32_t)0xFFUL << (8UL*(x)))) >> (8UL*(x)))
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#define HWREAD_Z2_OTP_BOOTDEF_H(x) ((HWREG(Z2_OTP_BOOTDEF_HIGH) & ((uint32_t)0xFFUL << (8UL*(x)))) >> (8UL*(x)))
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#define FACTORY_DEFAULT_BMSP0 32 //GPIO32
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#define FACTORY_DEFAULT_BMSP1 24 //GPIO24
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#define HWREAD_FLASH_ENTRY_POINT_OVERRIDE_KEY (HWREG(0x711D2UL))
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#define HWREAD_FLASH_ENTRY_POINT_OVERRIDE_ADDR (HWREG(0x711D4UL))
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//---------------------------------------------------------------------------
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// Device Configuration
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//
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#define HWREAD_TI_OTP_PARTID_L (HWREG(0x711C2UL))
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#define HWREAD_TI_OTP_PARTID_H (HWREG(0x711C4UL))
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#define TI_OTP_ADDR_DC11 (0x711C7UL)
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#define TI_OTP_ADDR_DC31 (0x711C8UL)
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#define TI_OTP_ADDR_CPUROM_DC1 (0x711D6UL)
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#define TI_OTP_ADDR_CPUROM_DC2 (0x711D7UL)
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#define BROM_DCX_ENABLE_HIGH 0xFFFF0000UL
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#define HWREAD_TI_OTP_PKG_TYPE (HWREGH(0x711C6UL))
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#define PKG_TYPE_KEY 0x5AU
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#define PKG_TPYE_32_QFN 0xCUL
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#define TI_OTP_ANAREFCTL_ADDR (0x711CBUL)
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#define TI_OTP_ADDR_PERCNF1 (0x711C9UL)
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#define TI_OTP_ADDR_PERCNF2 (0x711CAUL)
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#define PERCNF1_MASK 0x10U
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#define PERCNF2_MASK 0x3U
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#define TI_OTP_REG_VREGCTL_ENMASK (HWREGH(0x711E6UL))
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#define BROM_ANALOG_SYSCTL_O_VREGCTL 0x006AU
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#define VREGCTL_ENMASK_KEY 0x5AU
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//bits15:8 is the KEY ; if Value == 0x5A then the remaining bits are valid
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//bits 7:2 => reserved
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//bits 0:1 if set to b'00 BROM will program 0x01 in VREGCTL.ENMASK
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// - any other value the VREGCTL.ENMASK will be left at reset state.
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#define TI_OTP_REG_VREGCTL_ENMASK_VAL ((TI_OTP_REG_VREGCTL_ENMASK) & 0x03U)
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#define TI_OTP_REG_VREGCTL_ENMASK_KEY (((TI_OTP_REG_VREGCTL_ENMASK) & 0xFF00U) >> 0x8U)
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//Bits [1:0] If 01, enable the PLL, otherwise leave it disabled
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//Bits [7:2] PLL divider to use when the PLL is enabled
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//Bits [31:24] If 0x5A, use this configuration word, otherwise use the default settings
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#define OTP_BOOT_CONFIGURE_WORD_ADDRESS 0x711E0UL
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#define BOOT_CONFIGURE_ENABLE_PLL 0x1U
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//Bit 23 is used for enabling watchdog monitoring during boot time
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//if the bit is 1 then it means the watchdog monitoring is enabled
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#define BOOT_CONFIG_ENABLE_WD_S 23U
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#define OTP_BOOT_CONFIG_M 0x000000FCUL
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#define OTP_BOOT_CONFIG_S 0x2U
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#define BOOTPIN_CONFIG_STANDALONE_KEY 0xA5U
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#define BOOTPIN_CONFIG_KEY 0x5AUL
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#define BOOTPIN_COFIG_KEY_MASK 0xFF000000UL
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#define BOOTPIN_COFIG_KEY_START 24U
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#define APLL_MULT_38 38UL
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#define APLL_DIV_2 1UL
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#define SYSCLK_DIV_1 0U
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#define SYSCLK_DIV_2 1U
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#define SYSCLK_DIV_4 2U
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//
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// Boot Selection Defines
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//
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#define CPU1_ALL_BMSP_DISABLED_MASK 0x00FFFFFFUL
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#define CPU1_PIN_CONFIG_MASK 0xFFU
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#define CPU1_BMSP_DISABLED 0xFFU
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//
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// OTP Keys
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//
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#define TI_OTP_KEY 0x5A5AU
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#define TI_OTP_KEY_32B 0x5A5A5A5AUL
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//
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// SIMRESET Key
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//
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#define SIMRESET_KEY 0xA5A5UL
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//
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// DFT Keys
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//
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#define DFT_BOOT_DMLED_KEY 0xAA55AA55UL
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#define DFT_BOOT_TEST_ALT_KEY 0x55AA55AAUL
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//
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// GPIO Pullup Config
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//
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#define HWREAD_TI_OTP_GPXPUD_KEY (HWREG(0x711CCUL))
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#define HWREAD_TI_OTP_GPA_PUD_CONFIG (HWREG(0x711CEUL))
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#define HWREAD_TI_OTP_GPB_PUD_CONFIG (HWREG(0x711D0UL))
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//
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//Masks for writes to GPA and GPB registers
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//to pull up unbonded pins
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//
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#define GPA_WRITE_MASK 0xFFFFFFFFUL
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#define GPB_WRITE_MASK 0xFFFFFFFFUL
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//
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// DCSM Offset Defines
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//
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#define DCSM_O_Zx_EXEONLYRAM 0x0UL
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#define DCSM_O_Zx_EXEONLYSECT 0x2UL
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#define DCSM_O_Zx_GRABRAM 0x4UL
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#define DCSM_O_Zx_GRABSECT 0x6UL
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//
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// CPU1 Boot ROM Status Bit Fields
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//
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#define CPU1_BOOTROM_BOOTSTS_BOOT_MASK 0x000000FFUL
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//
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// CPU1 Boot mode status bit field starts from 0 and ends at 7
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// It can take any values in the range 0 to 0xFF
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//
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#define CPU1_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001UL //Set during the initialization phase of the boot ROM
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#define CPU1_BOOTROM_BOOTSTS_IN_FLASH_BOOT 0x00000002UL
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#define CPU1_BOOTROM_BOOTSTS_IN_SECURE_FLASH_BOOT 0x00000003UL
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#define CPU1_BOOTROM_BOOTSTS_IN_PARALLEL_BOOT 0x00000004UL
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#define CPU1_BOOTROM_BOOTSTS_IN_RAM_BOOT 0x00000005UL
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#define CPU1_BOOTROM_BOOTSTS_IN_SCI_BOOT 0x00000006UL
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#define CPU1_BOOTROM_BOOTSTS_IN_SPI_BOOT 0x00000007UL
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#define CPU1_BOOTROM_BOOTSTS_IN_I2C_BOOT 0x00000008UL
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#define CPU1_BOOTROM_BOOTSTS_IN_CAN_BOOT 0x00000009UL
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#define CPU1_BOOTROM_BOOTSTS_IN_WAIT_BOOT 0x0000000BUL
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#define CPU1_BOOTROM_RAM_INIT_COMPLETE 0x00000100UL
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#define CPU1_BOOTROM_DCSM_INIT_COMPLETE 0x00000200UL
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#define CPU1_BOOTROM_POR_MEM_TEST_COMPLETE 0x00000400UL
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#define CPU1_BOOTROM_RESC_HANDLED 0x00000800UL
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#define CPU1_BOOTROM_HANDLED_XRSN 0x00001000UL
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#define CPU1_BOOTROM_HANDLED_POR 0x00002000UL
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#define CPU1_BOOTROM_WATCHDOG_SELFTEST_FAIL 0x00004000UL
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#define CPU1_BOOTROM_BOOT_COMPLETE 0x00008000UL
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#define CPU1_BOOTROM_GOT_ITRAP 0x00010000UL
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#define CPU1_BOOTROM_GOT_A_PIE_MISMATCH 0x00020000UL
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#define CPU1_BOOTROM_GOT_AN_ERAD_NMI 0x00040000UL
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#define CPU1_BOOTROM_GOT_A_RL_NMI 0x00080000UL
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#define CPU1_BOOTROM_GOT_A_MEM_UNCERR_NMI 0x00100000UL
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#define CPU1_BOOTROM_GOT_A_MCLK_NMI 0x00400000UL
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#define BOOTROM_PLL_ENABLE_SUCCESS 0x01000000UL
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#define CPU1_BOOTROM_DCSM_INIT_INVALID_LP 0x02000000UL
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#define CPU1_BOOTROM_DCSM_INIT_LP_ERROR_SET 0x04000000UL
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#define CPU1_BOOTROM_FLASH_VERIFICATION_ERROR 0x08000000UL
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#define CPU1_BOOTROM_RAM_INIT_ERROR 0x10000000UL
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#define CPU1_BOOTROM_TRIM_LOAD_ERROR 0x20000000UL
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#define CPU1_BOOTROM_FLASH_2T_NOT_READY 0x40000000UL
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#define BROM_FLASH_ALL_START 0x80000UL
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#define BROM_FLASH_ALL_END 0xA0000UL
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//
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//Mask for NMI enable bit (bit 0)
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//
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#define NMI_ENABLE_MASK 0x1U
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//
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// Lower word mask
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//
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#define WORD_MASK 0xFFFFU
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#ifndef LDRA_FILEIO
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//
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// Watchdog prescaler and prediv values
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//
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//
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// setting prescale and prediv values to get timeout of 209.6 ms
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//
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#define WD_PRESCALE_VALUE SYSCTL_WD_PRESCALE_8
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#define WD_PREDIV_VALUE SYSCTL_WD_PREDIV_1024
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#else
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#define WD_PRESCALE_VALUE SYSCTL_WD_PRESCALE_16
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#define WD_PREDIV_VALUE SYSCTL_WD_PREDIV_2048
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#endif
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//
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// the reset values of prescalar and prediv
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//
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#define WD_DEF_PRESCALE_VALUE SYSCTL_WD_PRESCALE_1
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#define WD_DEF_PREDIV_VALUE SYSCTL_WD_PREDIV_512
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#ifndef LDRA_FILEIO
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//
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// min values of prediv and prescale values so as to ensure maximum speed for watchdog clk
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//
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#define WD_PRESCALE_VALUE_MIN SYSCTL_WD_PRESCALE_1
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#define WD_PREDIV_VALUE_MIN SYSCTL_WD_PREDIV_2
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#else
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//
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// min values of prediv and prescale values so as to ensure maximum speed for watchdog clk
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//
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#define WD_PRESCALE_VALUE_MIN SYSCTL_WD_PRESCALE_8
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#define WD_PREDIV_VALUE_MIN SYSCTL_WD_PREDIV_512
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#endif
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//
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// Function prototypes
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//
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extern void cbrom_configure_flash(void);
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extern uint32_t Gather_Bx_Zx_ZSB(uint16_t bank, uint16_t zone, uint32_t *csmkey);
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extern interrupt void CPU1BROM_itrapISR(void);
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extern interrupt void CPU1BROM_nmiHandler(void);
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extern uint32_t I2C_Boot(uint32_t bootMode);
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extern uint32_t SCI_Boot(uint32_t bootMode);
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extern uint32_t SPI_Boot(uint32_t bootMode);
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uint32_t DCAN_Boot(uint32_t bootMode, uint32_t bitTimingRegValue, uint16_t switchToXTAL);
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extern uint32_t SPI_Alternate_IO_Boot(void);
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extern uint32_t Parallel_Boot(uint32_t BootMode);
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extern uint32_t CPU1BROM_selectBootMode(void);
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extern void CPU1BROM_triggerSysPLLLock(uint32_t multiplier, uint32_t divider);
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extern uint16_t CPU1BROM_switchToPLL(uint32_t bootConfig);
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extern uint32_t PBIST_PORMemoryTest(void);
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extern void CPU1BROM_devcalInit(void);
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extern void CPU1BROM_configureHardwarePatching(uint32_t startAddress);
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#endif //C_BOOTROM_H_
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