275 lines
13 KiB
C++
275 lines
13 KiB
C++
/*
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* RegAMC1210.h
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*
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* Created on: 15 íîÿá. 2016 ã.
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* Author: titov
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*/
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#ifndef SOURCE_DRIVER_REGISTER_TREGAMC1210_H_
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#define SOURCE_DRIVER_REGISTER_TREGAMC1210_H_
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namespace driver { namespace detail { namespace reg {
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//!Îïèñàíèå ðåãèñòðîâ ìèêðîñõåìû AMC1210
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struct RegAMC1210 {
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typedef unsigned short TStatusRegister;
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enum TStatusMask : unsigned short {
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IO0 = 0x0001, //!<Integrator overflow for filter module 1.
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TO0 = 0x0002, //!<Time counter overflow for filter module 2.
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IO1 = 0x0004, //!<Integrator overflow for filter module 2.
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TO1 = 0x0008, //!<Time counter overflow for filter module 2.
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IO2 = 0x0010, //!<Integrator overflow for filter module 3.
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TO2 = 0x0020, //!<Time counter overflow for filter module 3.
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IO3 = 0x0040, //!<Integrator overflow for filter module 4.
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TO3 = 0x0080, //!<Time counter overflow for filter module 4.
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MAF0 = 0x0100, //!<Manchester failure status for filter module 1.
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MAF1 = 0x0200, //!<Manchester failure status for filter module 2.
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MAF2 = 0x0400, //!<Manchester failure status for filter module 3.
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MAF3 = 0x0800, //!<Manchester failure status for filter module 4.
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MAL0 = 0x1000, //!<Manchester locked status for filter module 1.
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MAL1 = 0x2000, //!<Manchester locked status for filter module 2.
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MAL2 = 0x4000, //!<Manchester locked status for filter module 3.
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MAL3 = 0x8000 //!<Manchester locked status for filter module 4.
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};
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//!Ñòðóêòóðà îïèñûâàþùàÿ íàñòðîéêè ðåãèñòðà FilterControl.
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struct TFilterControlParameter_bits
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{
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unsigned short MOD:2; //!<\brief Delta-Sigma Modulator mode.
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//!<\n 00: The clock speed is equal to the data rate from the modulator
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//!<\n 01: The clock rate is half of the data rate from the modulator
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//!<\n 10: The data from the modulator is Manchester decoded
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//!<\n 11: The clock rate is twice the data rate of the modulator
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unsigned short TM:1; //!<\brief Time measure mode.
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//!<\n 0: The time is measured from the last filter update to the last rising edge of the selected sample-and-hold signal
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//!<\n 1: The time is measured between two rising edges of the selected sample-and-hold signal
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unsigned short SHS:1; //!<\brief Sample-and-hold select.
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//!<\n 0: Signal SH1 is chosen as sample-and-hold signal
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//!<\n 1: Signal SH2 is chosen as sample-and-hold signal
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unsigned short CD:1; //!<\brief Input clock direction.
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//!<\n 0: Pin CLKx is an input
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//!<\n 1: Pin CLKx is an output. The outgoing clock comes from the modulator clock divider.
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unsigned short MS:11; //!< Manchester status
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};
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//!Íàñòðîéêè ðåãèñòðà FilterControl.
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union TFilterControlParameter
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{
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TFilterControlParameter_bits structured; //!<Ñòðóêòóðèðîâàííîå ïðåäñòàâëåíèå.
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unsigned short all; //!<Öåëî÷èñëåííîå ïðåäñòàâëåíèå.
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};
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//!Ñòðóêòóðà îïèñûâàþùàÿ íàñòðîéêè ðåãèñòðà FilterSinc.
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struct TFilterSincParameter_bits
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{
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unsigned short SOSR:8; //!<\brief Oversampling ratio. The actual rate is SOSR + 1.
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//!< These bits set the oversampling ratio of the filter.
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//!< 0xFF represents an oversampling ratio of 256.
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unsigned short FEN:1; //!<\brief Filter enable.
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//!<\n 0: The filter is disabled and no data is produced
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//!<\n 1: The filter is enabled and data are produced in the sinc filter and/or integrator
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unsigned short AE:1; //!<\brief Acknowledge enable.
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//!<\n 0: The acknowledge flag is disabled for the particular filter
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//!<\n 1: The acknowledge flag is enabled for the particular filter
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unsigned short SST:2; //!<\brief Sinc filter structure.
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//!<\n 00: Sinc filter runs with a sincfast structure
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//!<\n 01: Sinc filter runs with a Sinc1 structure
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//!<\n 10: Sinc filter runs with a Sinc2 structure
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//!<\n 11: Sinc filter runs with a Sinc3 structure
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unsigned short unused:4; //!<\brief Unused. Always read '0'.
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};
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//!Íàñòðîéêè ðåãèñòðà FilterControl.
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union TFilterSincParameter
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{
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TFilterSincParameter_bits structured; //!<Ñòðóêòóðèðîâàííîå ïðåäñòàâëåíèå.
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unsigned short all; //!<Öåëî÷èñëåííîå ïðåäñòàâëåíèå.
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};
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//!Ñòðóêòóðà îïèñûâàþùàÿ íàñòðîéêè ðåãèñòðà FilterIntegrator.
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struct TFilterIntegratorParameter_bits
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{
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unsigned short IOSR:7; //!<\brief Oversampling ratio. The actual rate is IOSR + 1.
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//!<\n These bits set the oversampling ratio of the integrator.
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//!<\n 0x03 represents an oversampling ratio of 4.
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unsigned short IMOD:1; //!<\brief Integrator mode.
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//!<\n 0: The oversampling mode updates the data output of the integrator
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//!<\n 1: The selected sample-and-hold signal updates the data output of the integrator
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unsigned short IEN:1; //!<\brief Integrator enable.
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//!<\n 0: The data from the sinc filter output is stored in the register map
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//!<\n 1: The data from the integrator is stored in the register map
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unsigned short DEN:1; //!<\brief Demodulation enable.
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//!<\n 0: The demodulation for resolver applications is disabled
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//!<\n 1: The demodulation for resolver applications is enabled
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unsigned short DR:1; //!<\brief Data representation.
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//!<\n 0: The data is stored in 16-bit two's complement
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//!<\n 1: The data is stored in 32-bit two's complement
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unsigned short SH:5; //!<\brief Shift control.
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//!<\n These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen.
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};
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//!Íàñòðîéêè ðåãèñòðà FilterIntegrator.
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union TFilterIntegratorParameter
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{
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TFilterIntegratorParameter_bits structured; //!<Ñòðóêòóðèðîâàííîå ïðåäñòàâëåíèå.
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unsigned short all; //!<Öåëî÷èñëåííîå ïðåäñòàâëåíèå.
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};
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//!Ñòðóêòóðà îïèñûâàþùàÿ íàñòðîéêè ðåãèñòðà FilterComparator.
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struct TFilterComparatorParameter_bits
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{
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unsigned short COSR:5; //!<\brief Oversampling ratio. The actual rate is COSR + 1.
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//!<\n These bits set the oversampling ratio of the filter.
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//!<\n 0xFF represents an oversampling ratio of 256.
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unsigned short IEH:1; //!<\brief High-level interrupt enable.
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//!<\n 0: The high-level interrupt flag as well as the output INT is disabled for this particular flag
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//!<\n 1: The high-level interrupt flag is enabled
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unsigned short IEL:1; //!<\brief Low-level interrupt enable.
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//!<\n 0: The low-level interrupt flag as well as the output INT is disabled for this particular flag
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//!<\n 1: The low-level interrupt flag is enabled
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unsigned short CS:2; //!<\brief Comparator filter structure.
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//!<\n 00: Comparator filter runs with a sincfast structure
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//!<\n 01: Comparator filter runs with a Sinc1 structure
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//!<\n 10: Comparator filter runs with a Sinc2 structure
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//!<\n 11: Comparator filter runs with a Sinc3 structure
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unsigned short MFIE:1; //!<\brief Modulator failure interrupt enable.
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//!<\n 0: The modulator failure flag as well as the output INT is disabled for this particular flag
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//!<\n 1: The modulator failure flag is enabled
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unsigned short unused:6; //!<\brief Unused. Always read '0'.
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};
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//!Íàñòðîéêè ðåãèñòðà FilterComparator.
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union TFilterComparatorParameter
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{
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TFilterComparatorParameter_bits structured; //!<Ñòðóêòóðèðîâàííîå ïðåäñòàâëåíèå.
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unsigned short all; //!<Öåëî÷èñëåííîå ïðåäñòàâëåíèå.
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};
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//!Íàñòðîéêè ìîäóëÿ ôèëüòðà FilterModule.
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struct TFilterModuleConfig
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{
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TFilterControlParameter ControlParameter;
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TFilterSincParameter SincFilterParameter;
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TFilterIntegratorParameter IntegratorParameter;
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unsigned short HiLevelThreshold;
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unsigned short LoLevelThreshold;
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TFilterComparatorParameter ComparatorParameter;
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};
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//!Ñòðóêòóðà îïèñûâàþùàÿ íàñòðîéêè ClockDivider
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struct TClockDividerRegister_bits
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{
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unsigned short SignalGeneratorClockDivider:4; //!<\brief Modulator clock divider. The coding is equal to the first eight codes in SD; see below.
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//!<\n Signal generator clock divider.
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//!<\n 0000: Clock divider is off, outgoing clock equals incoming clock
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//!<\n 0001: Outgoing clock is divided by 2
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//!<\n 0010: Outgoing clock is divided by 3
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//!<\n 0011: Outgoing clock is divided by 4
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//!<\n 0100: Outgoing clock is divided by 5
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//!<\n 0101: Outgoing clock is divided by 6
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//!<\n 0110: Outgoing clock is divided by 7
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//!<\n 0111: Outgoing clock is divided by 8
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//!<\n 1000: Outgoing clock is divided by 9
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//!<\n 1001: Outgoing clock is divided by 10
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//!<\n 1010: Outgoing clock is divided by 11
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//!<\n 1011: Outgoing clock is divided by 12
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//!<\n 1100: Outgoing clock is divided by 13
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//!<\n 1101: Outgoing clock is divided by 14
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//!<\n 1110: Outgoing clock is divided by 15
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//!<\n 1111: Outgoing clock is divided by 16
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unsigned short ModulatorClockDivider:3; //!<\brief Modulator clock divider. The first eight codes in SD; see below.
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unsigned short SignalGeneratorControl:2; //!<\brief Signal generator Control Select (necessary for Phase Calibration and Demodulation on the selected channel).
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//!<\n 00: The phase calibration is performed on filter module 1.
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//!<\n 01: The phase calibration is performed on filter module 2.
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//!<\n 10: The phase calibration is performed on filter module 3.
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//!<\n 11: The phase calibration is performed on filter module 4.
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unsigned short PhaseCorrect:1; //!<\brief Start of phase correction.
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//!<\n Writing a '1' to this bit starts the phase calibration. Reading this bit shows the phase calibration status:
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//!<\n 1: The phase calibration is performing
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//!<\n 0: No phase calibration is performing
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unsigned short SignalGeneratorEnable:1; //!<\brief Signal Generator enable.
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//!<\n 0: Signal generator is disabled
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//!<\n 1: Signal generator is enabled
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unsigned short MasterFilter:1; //!<\brief Master Filter Enable. Functionally AND'ed with bit FEN in the Sinc Filter Parameter
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//!<\n 0: giinstcefri.lter units of all filter modules are disabled.
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//!<\n 1: Sinc filter units can be enabled if bit FEN is '1'.
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unsigned short SignalHighCurrent:1; //!<\brief Signal Generator High-Current Output.
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//!<\n 0: The high current option for pins PWM1 and PWM2 is disabled
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//!<\n 1: The PWM1 and PWM2 outputs are in High Current Mode
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};
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//!Ñòðóêòóðà îòâåòà AMC1210.
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struct TResulOutput
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{
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//!Äëèííà ñîîáùåíèÿ â áàéòàõ.
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static const short messageLength = 4;
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//
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short DataRegister; //!<Äàííûå ïî êàíàëó.
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unsigned short TimeRegister; //!<Âðåìÿ îò ïîñëåäíåãî îáíîâëåíèÿ, åñëè âêë.
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//!Ñåðèàëèçàöèÿ â áàéòû.
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void serialize(char (&buff)[messageLength]) const {
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const char * bytes = reinterpret_cast<const char *>(&DataRegister);
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buff[0] = *(bytes + 1);
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buff[1] = *(bytes + 0);
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// bytes = reinterpret_cast<const char *>(&TimeRegister);
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// buff[2] = *(bytes + 3);
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// buff[3] = *(bytes + 2);
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}
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//!Äåñåðèàëèçàöèÿ èç áàéòîãî ìàññèâà.
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void deserialize(const char (&buff)[messageLength]) {
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char * bytes = reinterpret_cast<char *>(&DataRegister);
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*(bytes + 0) = buff[1];
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*(bytes + 1) = buff[0];
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// bytes = reinterpret_cast<char *>(&TimeRegister); //TODO funcition edit prev_data[0].DataRegister!!!!
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// *(bytes + 2) = buff[3];
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// *(bytes + 3) = buff[2];
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}
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};
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//!Íàñòðîéêè ìîäóëÿ äåëèòåëÿ âðåìåíè ClockDivider.
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union TClockDividerRegister {
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TClockDividerRegister_bits structured; //!<Ñòðóêòóðèðîâàííîå ïðåäñòàâëåíèå.
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unsigned short all; //!<Öåëî÷èñëåííîå ïðåäñòàâëåíèå.
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};
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//!Ñòðóêòóðà îïèñûâàþùàÿ âñå íàñòðîéêè ÷èïà AMC1210.
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struct TResolverDriverConfig
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{
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unsigned short InterruptRegister; //!<Íàñòðîéêè ðåãèñòðà îáðàáîòêè ïðåðûâàíèé â AMC1210.
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TFilterModuleConfig FilterModuleConfig[4]; //!<Íàñòðîéêè ìîäóëåé ôèëüòðàöèè.
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unsigned short ControlRegister; //!<Íàñòðîéêè óïðàâëÿþùèõ ðåãèñòðîâ.
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unsigned short PatternRegister; //!<Ïåðåìåííàÿ äëÿ çàïèñè øàáëîíà ãåíåðàöèè îïîðíîãî ñèãíàëà.
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TClockDividerRegister ClockDividerRegister; //!<Íàñòðîéêè ðåãèñòðà äåëèòåëÿ ÷àñòîòû.
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TStatusRegister StatusRegister; //!<Ðåãèñòð ñîñòîÿíèÿ AMC1210.
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};
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//!Íàñòðîéêè AMC1210.
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union TResolverDriverConfigUnion
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{
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TResolverDriverConfig structured; //!<Ñòðóêòóðèðîâàííîå ïðåäñòàâëåíèå.
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unsigned short array[36]; //!<Öåëî÷èñëåííîå ïðåäñòàâëåíèå.
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// char bytes[72]; //!<Ïðåäñòàâëåíèå â áàéòàõ.
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};
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//!NO!
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union TFilterDriverConfigUnion
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{
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unsigned short InterruptRegister; //!<Íàñòðîéêè ðåãèñòðà îáðàáîòêè ïðåðûâàíèé â AMC1210.
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TFilterModuleConfig FilterModuleConfig[4]; //!<Íàñòðîéêè ìîäóëåé ôèëüòðàöèè.
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unsigned short ControlRegister; //!<Íàñòðîéêè óïðàâëÿþùèõ ðåãèñòðîâ.
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TClockDividerRegister ClockDividerRegister; //!<Íàñòðîéêè ðåãèñòðà äåëèòåëÿ ÷àñòîòû.
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TStatusRegister StatusRegister; //!<Ðåãèñòð ñîñòîÿíèÿ AMC1210.
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};
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};
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} } }
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#endif /* SOURCE_DRIVER_REGISTER_TREGAMC1210_H_ */
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