/*
 * RegAMC1210.h
 *
 *  Created on: 15 нояб. 2016 г.
 *      Author: titov
 */

#ifndef SOURCE_DRIVER_REGISTER_TREGAMC1210_H_
#define SOURCE_DRIVER_REGISTER_TREGAMC1210_H_

namespace driver { namespace detail { namespace reg {

//!Описание регистров микросхемы AMC1210
struct RegAMC1210 {

	typedef unsigned short TStatusRegister;

	enum TStatusMask : unsigned short {
		IO0 	= 0x0001, 	//!<Integrator overflow for filter module 1.
		TO0 	= 0x0002,	//!<Time counter overflow for filter module 2.
		IO1 	= 0x0004,	//!<Integrator overflow for filter module 2.
		TO1 	= 0x0008,	//!<Time counter overflow for filter module 2.
		IO2 	= 0x0010,	//!<Integrator overflow for filter module 3.
		TO2 	= 0x0020,	//!<Time counter overflow for filter module 3.
		IO3 	= 0x0040,	//!<Integrator overflow for filter module 4.
		TO3 	= 0x0080,	//!<Time counter overflow for filter module 4.
		MAF0 	= 0x0100,	//!<Manchester failure status for filter module 1.
		MAF1 	= 0x0200,	//!<Manchester failure status for filter module 2.
		MAF2 	= 0x0400,	//!<Manchester failure status for filter module 3.
		MAF3 	= 0x0800,	//!<Manchester failure status for filter module 4.
		MAL0 	= 0x1000,	//!<Manchester locked status for filter module 1.
		MAL1 	= 0x2000,	//!<Manchester locked status for filter module 2.
		MAL2 	= 0x4000,	//!<Manchester locked status for filter module 3.
		MAL3 	= 0x8000	//!<Manchester locked status for filter module 4.
	};
	//!Структура описывающая настройки регистра FilterControl.
	struct TFilterControlParameter_bits
	{
		unsigned short MOD:2;			//!<\brief Delta-Sigma Modulator mode.
								//!<\n 	00: The clock speed is equal to the data rate from the modulator
								//!<\n	01: The clock rate is half of the data rate from the modulator
								//!<\n	10: The data from the modulator is Manchester decoded
								//!<\n	11: The clock rate is twice the data rate of the modulator
		unsigned short TM:1;			//!<\brief Time measure mode.
								//!<\n 	0: The time is measured from the last filter update to the last rising edge of the selected sample-and-hold signal
								//!<\n	1: The time is measured between two rising edges of the selected sample-and-hold signal
		unsigned short SHS:1;			//!<\brief Sample-and-hold select.
								//!<\n 	0: Signal SH1 is chosen as sample-and-hold signal
								//!<\n 	1: Signal SH2 is chosen as sample-and-hold signal
		unsigned short CD:1;			//!<\brief Input clock direction.
								//!<\n 	0: Pin CLKx is an input
								//!<\n 	1: Pin CLKx is an output. The outgoing clock comes from the modulator clock divider.
		unsigned short MS:11;			//!< Manchester status
	};

	//!Настройки регистра FilterControl.
	union TFilterControlParameter
	{
		TFilterControlParameter_bits structured;	//!<Структурированное представление.
		unsigned short all;									//!<Целочисленное представление.
	};

	//!Структура описывающая настройки регистра FilterSinc.
	struct TFilterSincParameter_bits
	{
		unsigned short SOSR:8;			//!<\brief Oversampling ratio. The actual rate is SOSR + 1.
								//!< These bits set the oversampling ratio of the filter.
								//!< 0xFF represents an oversampling ratio of 256.
		unsigned short FEN:1;			//!<\brief Filter enable.
								//!<\n	0: The filter is disabled and no data is produced
								//!<\n	1: The filter is enabled and data are produced in the sinc filter and/or integrator
		unsigned short AE:1;			//!<\brief Acknowledge enable.
								//!<\n	0: The acknowledge flag is disabled for the particular filter
								//!<\n	1: The acknowledge flag is enabled for the particular filter
		unsigned short SST:2;			//!<\brief Sinc filter structure.
								//!<\n	00: Sinc filter runs with a sincfast structure
								//!<\n	01: Sinc filter runs with a Sinc1 structure
								//!<\n	10: Sinc filter runs with a Sinc2 structure
								//!<\n	11: Sinc filter runs with a Sinc3 structure
		unsigned short unused:4;		//!<\brief Unused. Always read '0'.
	};

	//!Настройки регистра FilterControl.
	union TFilterSincParameter
	{
		TFilterSincParameter_bits structured;	//!<Структурированное представление.
		unsigned short all;								//!<Целочисленное представление.
	};

	//!Структура описывающая настройки регистра FilterIntegrator.
	struct TFilterIntegratorParameter_bits
	{
		unsigned short IOSR:7;			//!<\brief Oversampling ratio. The actual rate is IOSR + 1.
								//!<\n	These bits set the oversampling ratio of the integrator.
								//!<\n	0x03 represents an oversampling ratio of 4.
		unsigned short IMOD:1;			//!<\brief Integrator mode.
								//!<\n	0: The oversampling mode updates the data output of the integrator
								//!<\n	1: The selected sample-and-hold signal updates the data output of the integrator
		unsigned short IEN:1;			//!<\brief Integrator enable.
								//!<\n 0: The data from the sinc filter output is stored in the register map
								//!<\n 1: The data from the integrator is stored in the register map
		unsigned short DEN:1;			//!<\brief Demodulation enable.
								//!<\n 	0: The demodulation for resolver applications is disabled
								//!<\n	1: The demodulation for resolver applications is enabled
		unsigned short DR:1;			//!<\brief Data representation.
								//!<\n	0: The data is stored in 16-bit two's complement
								//!<\n	1: The data is stored in 32-bit two's complement
		unsigned short SH:5;			//!<\brief Shift control.
								//!<\n These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen.
	};

	//!Настройки регистра FilterIntegrator.
	union TFilterIntegratorParameter
	{
		TFilterIntegratorParameter_bits structured;	//!<Структурированное представление.
		unsigned short all;									//!<Целочисленное представление.
	};

	//!Структура описывающая настройки регистра FilterComparator.
	struct TFilterComparatorParameter_bits
	{
		unsigned short COSR:5;			//!<\brief Oversampling ratio. The actual rate is COSR + 1.
								//!<\n	These bits set the oversampling ratio of the filter.
								//!<\n	0xFF represents an oversampling ratio of 256.
		unsigned short IEH:1;			//!<\brief High-level interrupt enable.
								//!<\n	0: The high-level interrupt flag as well as the output INT is disabled for this particular flag
								//!<\n 	1: The high-level interrupt flag is enabled
		unsigned short IEL:1;			//!<\brief Low-level interrupt enable.
								//!<\n	0: The low-level interrupt flag as well as the output INT is disabled for this particular flag
								//!<\n	1: The low-level interrupt flag is enabled
		unsigned short CS:2;			//!<\brief Comparator filter structure.
								//!<\n	00: Comparator filter runs with a sincfast structure
								//!<\n	01: Comparator filter runs with a Sinc1 structure
								//!<\n	10: Comparator filter runs with a Sinc2 structure
								//!<\n	11: Comparator filter runs with a Sinc3 structure
		unsigned short MFIE:1;			//!<\brief Modulator failure interrupt enable.
								//!<\n	0: The modulator failure flag as well as the output INT is disabled for this particular flag
								//!<\n	1: The modulator failure flag is enabled
		unsigned short unused:6;		//!<\brief Unused. Always read '0'.
	};

	//!Настройки регистра FilterComparator.
	union TFilterComparatorParameter
	{
		TFilterComparatorParameter_bits structured;	//!<Структурированное представление.
		unsigned short all;									//!<Целочисленное представление.
	};

	//!Настройки модуля фильтра FilterModule.
	struct TFilterModuleConfig
	{
		TFilterControlParameter ControlParameter;
		TFilterSincParameter SincFilterParameter;
		TFilterIntegratorParameter IntegratorParameter;
		unsigned short HiLevelThreshold;
		unsigned short LoLevelThreshold;
		TFilterComparatorParameter ComparatorParameter;
	};

	//!Структура описывающая настройки ClockDivider
	struct TClockDividerRegister_bits
	{
		unsigned short SignalGeneratorClockDivider:4;	//!<\brief Modulator clock divider. The coding is equal to the first eight codes in SD; see below.
												//!<\n	Signal generator clock divider.
												//!<\n 	0000: Clock divider is off, outgoing clock equals incoming clock
												//!<\n 	0001: Outgoing clock is divided by 2
												//!<\n 	0010: Outgoing clock is divided by 3
												//!<\n	0011: Outgoing clock is divided by 4
												//!<\n	0100: Outgoing clock is divided by 5
												//!<\n	0101: Outgoing clock is divided by 6
												//!<\n	0110: Outgoing clock is divided by 7
												//!<\n	0111: Outgoing clock is divided by 8
												//!<\n	1000: Outgoing clock is divided by 9
												//!<\n 	1001: Outgoing clock is divided by 10
												//!<\n	1010: Outgoing clock is divided by 11
												//!<\n	1011: Outgoing clock is divided by 12
												//!<\n	1100: Outgoing clock is divided by 13
												//!<\n	1101: Outgoing clock is divided by 14
												//!<\n	1110: Outgoing clock is divided by 15
												//!<\n	1111: Outgoing clock is divided by 16
		unsigned short ModulatorClockDivider:3;			//!<\brief Modulator clock divider. The first eight codes in SD; see below.
		unsigned short SignalGeneratorControl:2;		//!<\brief Signal generator Control Select (necessary for Phase Calibration and Demodulation on the selected channel).
												//!<\n	00: The phase calibration is performed on filter module 1.
												//!<\n	01: The phase calibration is performed on filter module 2.
												//!<\n	10: The phase calibration is performed on filter module 3.
												//!<\n	11: The phase calibration is performed on filter module 4.
		unsigned short PhaseCorrect:1;					//!<\brief Start of phase correction.
												//!<\n	Writing a '1' to this bit starts the phase calibration. Reading this bit shows the phase calibration status:
												//!<\n	1: The phase calibration is performing
												//!<\n	0: No phase calibration is performing
		unsigned short SignalGeneratorEnable:1;			//!<\brief Signal Generator enable.
												//!<\n	0: Signal generator is disabled
												//!<\n	1: Signal generator is enabled
		unsigned short MasterFilter:1;					//!<\brief Master Filter Enable. Functionally AND'ed with bit FEN in the Sinc Filter Parameter
												//!<\n	0: giinstcefri.lter units of all filter modules are disabled.
												//!<\n	1: Sinc filter units can be enabled if bit FEN is '1'.
		unsigned short SignalHighCurrent:1;				//!<\brief Signal Generator High-Current Output.
												//!<\n	0: The high current option for pins PWM1 and PWM2 is disabled
												//!<\n	1: The PWM1 and PWM2 outputs are in High Current Mode
	};

	//!Структура ответа AMC1210.
	struct TResulOutput
	{
		//!Длинна сообщения в байтах.
		static const short messageLength = 4;
		//
		short DataRegister;							//!<Данные по каналу.
		unsigned short TimeRegister;				//!<Время от последнего обновления, если вкл.
		//!Сериализация в байты.
		void serialize(char (&buff)[messageLength]) const {

			const char * bytes = reinterpret_cast<const char *>(&DataRegister);
			buff[0] = *(bytes + 1);
			buff[1] = *(bytes + 0);

//			bytes = reinterpret_cast<const char *>(&TimeRegister);
//			buff[2] = *(bytes + 3);
//			buff[3] = *(bytes + 2);
		}
		//!Десериализация из байтого массива.
		void deserialize(const char (&buff)[messageLength]) {
			char * bytes = reinterpret_cast<char *>(&DataRegister);
			*(bytes + 0) = buff[1];
			*(bytes + 1) = buff[0];

//			bytes = reinterpret_cast<char *>(&TimeRegister); //TODO funcition edit prev_data[0].DataRegister!!!!
//			*(bytes + 2) = buff[3];
//			*(bytes + 3) = buff[2];
		}
	};

	//!Настройки модуля делителя времени ClockDivider.
	union TClockDividerRegister {
		TClockDividerRegister_bits structured;	//!<Структурированное представление.
		unsigned short all;								//!<Целочисленное представление.
	};

	//!Структура описывающая все настройки чипа AMC1210.
	struct TResolverDriverConfig
	{
		unsigned short InterruptRegister;					//!<Настройки регистра обработки прерываний в AMC1210.
		TFilterModuleConfig FilterModuleConfig[4];	//!<Настройки модулей фильтрации.
		unsigned short ControlRegister;						//!<Настройки управляющих регистров.
		unsigned short PatternRegister;						//!<Переменная для записи шаблона генерации опорного сигнала.
		TClockDividerRegister ClockDividerRegister;	//!<Настройки регистра делителя частоты.
		TStatusRegister StatusRegister;						//!<Регистр состояния AMC1210.
	};

	//!Настройки AMC1210.
	union TResolverDriverConfigUnion
	{
		TResolverDriverConfig structured;		//!<Структурированное представление.
		unsigned short array[36];				//!<Целочисленное представление.
	//	char bytes[72];							//!<Представление в байтах.
	};

	//!NO!
	union TFilterDriverConfigUnion
	{
        unsigned short InterruptRegister;                   //!<Настройки регистра обработки прерываний в AMC1210.
        TFilterModuleConfig FilterModuleConfig[4];  //!<Настройки модулей фильтрации.
        unsigned short ControlRegister;                     //!<Настройки управляющих регистров.
        TClockDividerRegister ClockDividerRegister; //!<Настройки регистра делителя частоты.
        TStatusRegister StatusRegister;                     //!<Регистр состояния AMC1210.
	};

};

} } }



#endif /* SOURCE_DRIVER_REGISTER_TREGAMC1210_H_ */