From fe2fe40ad95fb96edda21c97b82d5038bcb63cd3 Mon Sep 17 00:00:00 2001 From: Eugene Date: Wed, 6 Dec 2023 10:09:24 +0300 Subject: [PATCH] =?UTF-8?q?=D1=80=D0=B0=D0=B7=D0=B4=D0=B5=D0=BB=D0=B5?= =?UTF-8?q?=D0=BD=D0=B8=D0=B5=20=D0=BD=D0=B0=20=D0=B4=D0=B5=D0=B1=D0=B0?= =?UTF-8?q?=D0=B6=D0=BD=D1=83=D1=8E=20=D0=B8=20=D1=80=D0=B0=D0=B1=D0=BE?= =?UTF-8?q?=D1=87=D1=83=D1=8E=20=D1=81=20=D1=80=D0=B0=D0=B7=D0=BD=D1=8B?= =?UTF-8?q?=D0=BC=D0=B8=20=D1=87=D0=B0=D1=81=D1=82=D0=BE=D1=82=D0=B0=D0=BC?= =?UTF-8?q?=D0=B8=20=D0=BA=D0=B2=D0=B0=D1=80=D1=86=D0=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Projects/mem_test/.cproject | 227 +++++++++++++++++- Projects/mem_test/.gitignore | 6 +- .../org.eclipse.core.resources.prefs | 34 +-- Projects/mem_test/lib/f2838x_emif.c | 16 +- Projects/mem_test/lib/f2838x_sysctrl.c | 7 +- Projects/mem_test/src/Peripherals/emif_init.c | 49 ++-- Projects/mem_test/src/Peripherals/ipc_init.c | 3 +- 7 files changed, 281 insertions(+), 61 deletions(-) diff --git a/Projects/mem_test/.cproject b/Projects/mem_test/.cproject index 5711252..1522c78 100644 --- a/Projects/mem_test/.cproject +++ b/Projects/mem_test/.cproject @@ -2,7 +2,7 @@ - + @@ -13,9 +13,9 @@ - + - + @@ -327,7 +334,7 @@ - + @@ -338,9 +345,9 @@ - + - + @@ -439,6 +454,196 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Projects/mem_test/.gitignore b/Projects/mem_test/.gitignore index 056e2bf..bc4f766 100644 --- a/Projects/mem_test/.gitignore +++ b/Projects/mem_test/.gitignore @@ -1,3 +1,5 @@ /CPU1_FLASH/ -/CPU1_RAM/ -/CPU2_RAM/ +/CPU1_RAM_DEBUG/ +/CPU1_RAM_RELEASE/ +/CPU2_RAM_RELEASE/ + diff --git a/Projects/mem_test/.settings/org.eclipse.core.resources.prefs b/Projects/mem_test/.settings/org.eclipse.core.resources.prefs index 7c820b1..8592db8 100644 --- a/Projects/mem_test/.settings/org.eclipse.core.resources.prefs +++ b/Projects/mem_test/.settings/org.eclipse.core.resources.prefs @@ -1,21 +1,21 @@ eclipse.preferences.version=1 -encoding//CPU1_RAM/Freemaster/subdir_rules.mk=UTF-8 -encoding//CPU1_RAM/Freemaster/subdir_vars.mk=UTF-8 -encoding//CPU1_RAM/device/subdir_rules.mk=UTF-8 -encoding//CPU1_RAM/device/subdir_vars.mk=UTF-8 -encoding//CPU1_RAM/lib/subdir_rules.mk=UTF-8 -encoding//CPU1_RAM/lib/subdir_vars.mk=UTF-8 -encoding//CPU1_RAM/makefile=UTF-8 -encoding//CPU1_RAM/objects.mk=UTF-8 -encoding//CPU1_RAM/sources.mk=UTF-8 -encoding//CPU1_RAM/src/ExternalEEPROM/subdir_rules.mk=UTF-8 -encoding//CPU1_RAM/src/ExternalEEPROM/subdir_vars.mk=UTF-8 -encoding//CPU1_RAM/src/Peripherals/subdir_rules.mk=UTF-8 -encoding//CPU1_RAM/src/Peripherals/subdir_vars.mk=UTF-8 -encoding//CPU1_RAM/src/subdir_rules.mk=UTF-8 -encoding//CPU1_RAM/src/subdir_vars.mk=UTF-8 -encoding//CPU1_RAM/subdir_rules.mk=UTF-8 -encoding//CPU1_RAM/subdir_vars.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/Freemaster/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/Freemaster/subdir_vars.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/device/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/device/subdir_vars.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/lib/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/lib/subdir_vars.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/makefile=UTF-8 +encoding//CPU1_RAM_RELEASE/objects.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/sources.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/src/ExternalEEPROM/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/src/ExternalEEPROM/subdir_vars.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/src/Peripherals/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/src/Peripherals/subdir_vars.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/src/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/src/subdir_vars.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM_RELEASE/subdir_vars.mk=UTF-8 encoding//CPU2_RAM/device/subdir_rules.mk=UTF-8 encoding//CPU2_RAM/device/subdir_vars.mk=UTF-8 encoding//CPU2_RAM/lib/subdir_rules.mk=UTF-8 diff --git a/Projects/mem_test/lib/f2838x_emif.c b/Projects/mem_test/lib/f2838x_emif.c index c1d0888..679f09e 100644 --- a/Projects/mem_test/lib/f2838x_emif.c +++ b/Projects/mem_test/lib/f2838x_emif.c @@ -250,7 +250,7 @@ void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel) { Uint16 i; - for (i=38; i<=52; i++) + for (i=48; i<=52; i++)//38 to 52 { if ((i != 42) && (i != 43)) { @@ -259,11 +259,17 @@ void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel) } - for (i=69; i<=92; i++) + for (i=76; i<=82; i++) //69 to 82 { - if ((i != 83) && (i != 84) && (i != 85)) { - GPIO_SetupPinMux(i,cpu_sel,2);//D2 - D15, A13 - A19 + GPIO_SetupPinMux(i,cpu_sel,2);//D2 - D15 + } + } + + for (i=86; i<=92; i++) //86 to 92 + { + { + GPIO_SetupPinMux(i,cpu_sel,2);//A13 - A19 } } @@ -278,7 +284,7 @@ void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel) GpioDataRegs.GPADAT.bit.GPIO26 = 1; GpioCtrlRegs.GPADIR.bit.GPIO27 = 1; - GpioDataRegs.GPADAT.bit.GPIO27 = 1; + GpioDataRegs.GPADAT.bit.GPIO27 = 0;//Byte mode GPIO_SetupPinMux(29,cpu_sel,9);//CS3 GPIO_SetupPinMux(31,cpu_sel,2);//WEN diff --git a/Projects/mem_test/lib/f2838x_sysctrl.c b/Projects/mem_test/lib/f2838x_sysctrl.c index e6da39b..d7294fb 100644 --- a/Projects/mem_test/lib/f2838x_sysctrl.c +++ b/Projects/mem_test/lib/f2838x_sysctrl.c @@ -213,7 +213,7 @@ void InitSysCtrl(void) ESTOP0; while(1); } - +#ifdef DEBUG // // Initialize the SYSPLL control to generate a 200Mhz clock // @@ -258,10 +258,11 @@ void InitSysCtrl(void) // registers and the calibrated values will be lost. // Device_cal(); -#endif - +#endif // _FLASH +#endif // DEBUG #endif // CPU1 + // // Turn on all peripherals // diff --git a/Projects/mem_test/src/Peripherals/emif_init.c b/Projects/mem_test/src/Peripherals/emif_init.c index 5cf8374..43a570b 100644 --- a/Projects/mem_test/src/Peripherals/emif_init.c +++ b/Projects/mem_test/src/Peripherals/emif_init.c @@ -10,7 +10,8 @@ #define TEST_PASS 0xABCDABCD #define TEST_FAIL 0xDEADDEAD #define ASRAM_CS2_START_ADDR 0x100000 -#define ASRAM_CS2_SIZE 0x8000 +#define ASRAM_CS2_SIZE 0x100000 +#define STEP 0x100 #define EMIF1 0 #define EMIF2 1 #define MEM_D_WIDTH 1 // 16Bit Memory Interface @@ -43,13 +44,15 @@ extern void setup_emif1_pinmux_async_16bit(Uint16); // mem_read_write - This function performs simple read/write word accesses // to memory. // +uint16_t Arr1[256], Arr2[256]; + char -mem_read_write(Uint32 start_addr, Uint32 mem_size) +mem_read_write(Uint32 start_addr, Uint32 mem_size, Uint16 step) { unsigned long mem_rds; unsigned long mem_wds; long *XMEM_ps; - unsigned int i; + Uint32 i; // //Write data @@ -60,9 +63,11 @@ mem_read_write(Uint32 start_addr, Uint32 mem_size) //Fill memory // mem_wds = 0x01234567; - for (i=0; i < mem_size; i++) + for (i=0; i < mem_size; i+=step) { - *XMEM_ps++ = mem_wds; + *XMEM_ps = mem_wds; + if(i < 256) Arr1[i] = mem_wds & 0x1FF; + XMEM_ps += step; mem_wds += 0x11111111; } @@ -71,14 +76,14 @@ mem_read_write(Uint32 start_addr, Uint32 mem_size) // mem_wds = 0x01234567; XMEM_ps = (long *)start_addr; - for (i=0; i < mem_size; i++) + for (i=0; i < mem_size; i+=step) { mem_rds = *XMEM_ps; - if( mem_rds != mem_wds) + if( (mem_rds & 0x1FF) != (mem_wds & 0x1FF) ) { - return(1); + if(i < 256) Arr2[i] = mem_rds & 0x1FF; } - XMEM_ps++; + XMEM_ps+= step; mem_wds += 0x11111111; } return(0); @@ -325,8 +330,10 @@ void emif_init(void) // setup_emif1_pinmux_async_16bit(0); + Emif1Regs.ASYNC_WCCR.bit.WP0 = 0; + // - //Configure the access timing for CS2 space + //Configure the access timing for CS3 space // Emif1Regs.ASYNC_CS3_CR.all = (EMIF_ASYNC_ASIZE_16 | // 16Bit Memory // Interface @@ -338,41 +345,41 @@ void emif_init(void) // of 4 Emif Clock EMIF_ASYNC_RSETUP_1 | // Read Setup time // of 1 Emif Clock - EMIF_ASYNC_WHOLD_1 | // Write Hold time + EMIF_ASYNC_WHOLD_8 | // Write Hold time // of 1 Emif Clock - EMIF_ASYNC_WSTROBE_1 | // Write Strobe time + EMIF_ASYNC_WSTROBE_32 | // Write Strobe time // of 1 Emif Clock EMIF_ASYNC_WSETUP_1 | // Write Setup time // of 1 Emif Clock - EMIF_ASYNC_EW_DISABLE | // Extended Wait + EMIF_ASYNC_EW_ENABLE | // Extended Wait // Disable. - EMIF_ASYNC_SS_DISABLE // Strobe Select Mode + EMIF_ASYNC_SS_ENABLE // Strobe Select Mode // Disable. ); // //Check basic RD/WR access to CS2 space // - ErrCount_local = mem_read_write(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE); + ErrCount_local = mem_read_write(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE, STEP); ErrCount = ErrCount + ErrCount_local; // //Address walk checks (Tested for Memory with address width of 16bit) // - ErrCount_local = mem_addr_walk(ASRAM_CS2_START_ADDR, 16); - ErrCount = ErrCount + ErrCount_local; +// ErrCount_local = mem_addr_walk(ASRAM_CS2_START_ADDR, 16); +// ErrCount = ErrCount + ErrCount_local; // //Data walk checks // - ErrCount_local = mem_data_walk(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE); - ErrCount = ErrCount + ErrCount_local; +// ErrCount_local = mem_data_walk(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE); +// ErrCount = ErrCount + ErrCount_local; // //Data size checks // - ErrCount_local = mem_data_size(ASRAM_CS2_START_ADDR, 4); - ErrCount = ErrCount + ErrCount_local; +// ErrCount_local = mem_data_size(ASRAM_CS2_START_ADDR, 4); + // ErrCount = ErrCount + ErrCount_local; if (ErrCount == 0x0) { diff --git a/Projects/mem_test/src/Peripherals/ipc_init.c b/Projects/mem_test/src/Peripherals/ipc_init.c index cf7ea80..f4bf392 100644 --- a/Projects/mem_test/src/Peripherals/ipc_init.c +++ b/Projects/mem_test/src/Peripherals/ipc_init.c @@ -384,12 +384,11 @@ void ipc_run(void) if((InCommand >> 16) == RESET_NOW) { // CpuSysRegs.SIMRESET.all = 0xA5A50002;//bit.XRSn - // EALLOW; // CmConfRegs.CMRESCTL.all = SYSCTL_CMRESCTL_RESET | SYSCTL_REG_KEY;//.bit.RESETSTS = 1; // DevCfgRegs.CPU2RESCTL.all = ((uint32_t)SYSCTL_CPU2RESCTL_RESET |(SYSCTL_REG_KEY & SYSCTL_CPU2RESCTL_KEY_M)); //.bit.RESET = 1; // EDIS; - CpuSysRegs.SIMRESET.all = ((uint32_t)SYSCTL_REG_KEY | (uint32_t)1); + CpuSysRegs.SIMRESET.all = ((uint32_t)SYSCTL_REG_KEY | (uint32_t)1);//программный сброс всех контроллеров IPC_sendCommand(IPC_CPU1_L_CM_R, COMMAND_ACCEPTED, ZD24C02A_2K_I2C, 0, 0); IPC_setFlagLtoR(IPC_CPU1_L_CM_R,(1<<0)); ReadFromCm = 0;