From 5e0cbb504ab22a4315ebd570d4fd7262c83aaf4c Mon Sep 17 00:00:00 2001 From: Eugene Date: Mon, 4 Sep 2023 09:40:41 +0300 Subject: [PATCH] =?UTF-8?q?=D0=98=D1=81=D0=BF=D1=80=D0=B0=D0=B2=D0=BB?= =?UTF-8?q?=D0=B5=D0=BD=D1=8B=20=D0=BE=D1=88=D0=B8=D0=B1=D0=BA=D0=B8=20?= =?UTF-8?q?=D0=B2=20=D0=BE=D0=B1=D1=80=D0=B0=D0=B1=D0=BE=D1=82=D0=BA=D0=B5?= =?UTF-8?q?=20=D1=84=D1=80=D0=B8=D0=BC=D0=B0=D1=81=D1=82=D0=B5=D1=80=D0=B0?= =?UTF-8?q?=20=D0=9D=D0=B0=D1=81=D1=82=D1=80=D0=BE=D0=B5=D0=BD=20=D0=B4?= =?UTF-8?q?=D0=B0=D1=82=D1=87=D0=B8=D0=BA=20=D1=82=D0=BE=D0=BA=D0=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../Freemaster/PE_freemaster_56F8xxx.c | 13 +- .../Freemaster/PE_freemaster_56F8xxx.h | 2 +- .../Freemaster/PE_freemaster_protocol.c | 2 +- .../epwm_test/Freemaster/PE_freemaster_rec.c | 4 +- Projects/epwm_test/Start_rfm.pmp | Bin 2320 -> 4763 bytes Projects/epwm_test/epwm_test.c | 27 +- Projects/epwm_test/src/frm_uart.c | 17 + Projects/epwm_test/src/frm_uart.h | 4 +- Projects/epwm_test/src/init_perif.c | 51 +-- Projects/epwm_test/src/pwm_init.c | 380 ++++-------------- Projects/epwm_test/src/pwm_init.h | 8 +- Projects/epwm_test/src/pwm_interrupts.c | 192 +-------- 12 files changed, 177 insertions(+), 523 deletions(-) diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.c b/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.c index 5cfe59e..cd97838 100644 --- a/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.c +++ b/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.c @@ -82,6 +82,8 @@ void FMSTR_CopyMemory(FMSTR_ADDR nDestAddr, FMSTR_ADDR nSrcAddr, FMSTR_SIZE8 nSi FMSTR_U8* ps = (FMSTR_U8*) nSrcAddr; FMSTR_U8* pd = (FMSTR_U8*) nDestAddr; +// nSize = nSize>>1; + while(nSize--) *pd++ = *ps++; } @@ -114,11 +116,11 @@ FMSTR_BPTR FMSTR_CopyToBuffer(FMSTR_BPTR pDestBuff, FMSTR_ADDR nSrcAddr, FMSTR_S FMSTR_U8* pd = (FMSTR_U8*) pDestBuff; nSize = nSize>>1; - + //Texas code composer variant while(nSize--) { *pd++ = *ps; - *pd++ = (*ps++) >> 8; + *pd++ = (*ps++) >> 8; //*pd++ = *ps++; } return (FMSTR_BPTR) pd; } @@ -149,11 +151,14 @@ FMSTR_BPTR FMSTR_CopyFromBuffer(FMSTR_ADDR nDestAddr, FMSTR_BPTR pSrcBuff, FMSTR { FMSTR_U8* ps = (FMSTR_U8*) pSrcBuff; FMSTR_U8* pd = (FMSTR_U8*) nDestAddr; - + //Texas code composer variant + + nSize = nSize>>1; + while(nSize--) { *pd = *ps++; - *pd++ += (*ps++)<<8; + *pd++ += (*ps++)<<8; // *pd++ = *ps++; } return (FMSTR_BPTR) ps; } diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.h b/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.h index 46ae1b4..87b8e95 100644 --- a/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.h +++ b/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.h @@ -46,7 +46,7 @@ #define FMSTR_PROT_VER 3U /* protocol version 3 */ #define FMSTR_CFG_FLAGS 0U /* board info flags */ -#define FMSTR_CFG_BUS_WIDTH 1U /* data bus width */ +#define FMSTR_CFG_BUS_WIDTH 2U /* data bus width = 1*/ #define FMSTR_GLOB_VERSION_MAJOR 2U /* driver version */ #define FMSTR_GLOB_VERSION_MINOR 0U #define FMSTR_IDT_STRING "56F8xxx FreeMASTER Driver" diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_protocol.c b/Projects/epwm_test/Freemaster/PE_freemaster_protocol.c index 174118a..3694bf1 100644 --- a/Projects/epwm_test/Freemaster/PE_freemaster_protocol.c +++ b/Projects/epwm_test/Freemaster/PE_freemaster_protocol.c @@ -220,7 +220,7 @@ void FMSTR_ProtocolDecoder(FMSTR_BPTR pMessageIO) /*lint -fallthrough */ case FMSTR_CMD_GETRECBUFF: #endif - pResponseEnd = FMSTR_GetRecBuff(pMessageIO); + pResponseEnd = FMSTR_GetRecBuff(pMessageIO);//recorder here break; #endif /* FMSTR_USE_RECORDER */ diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_rec.c b/Projects/epwm_test/Freemaster/PE_freemaster_rec.c index aa1b015..d7c5302 100644 --- a/Projects/epwm_test/Freemaster/PE_freemaster_rec.c +++ b/Projects/epwm_test/Freemaster/PE_freemaster_rec.c @@ -185,7 +185,7 @@ FMSTR_BPTR FMSTR_SetUpRec(FMSTR_BPTR pMessageIO) #else /* size in native sizeof units (=bytes on most platforms) */ pcm_wRecBuffSize = (FMSTR_SIZE)FMSTR_REC_BUFF_SIZE; - FMSTR_ARR2ADDR(pcm_nRecBuffAddr, pcm_pOwnRecBuffer); + FMSTR_ARR2ADDR(pcm_nRecBuffAddr, pcm_pOwnRecBuffer); // заполнение буфера #endif /* seek the setup data */ @@ -629,7 +629,7 @@ static void FMSTR_Recorder2(void) for (i=0U; iC%0A}4P! zFfcJNFaX8CfG00sAvdu&TR}tDP?IOnK+n)r!A93m$58YCe+C8~24}z0+>oL)pUga? z07e5KG-Nf@Gch%RYKK$orFq$T`Q>?x46GnAmWlas3S5q*CHc-7iFxU%aEBm?SxkIh z&d4}%zP@BYxNm%ZDZ;hvPytJ*3OzB_lGNf7L%1mru0GJWazNiE=a=S{q!t;$rQsq* z8=r?UGV)KhV{+x$wuZ*Aj!=#iIHcrBD3h^ z0%n%U+gXY=*nxq?%)r9H&cMOI$-o8l88ZVYV0amv1B$XdOHy-#lk*Ewr6zl@x-)WZ zp1|tO#4Ft(g$VD-fvk3nEMN&KkVbB}#-P+>DF!y*U?UR)1CXjr76wM3`5^pOR}W|p zhy{u&h8}ki2?U@>lZadiWKeC8!=4IQ*DD?$s z2MbsjW_7j5I`@ZFE&C@2vWN(&IDmv9;DbGgJ^41fueL%1h$#dlKs1C`0c3$33*i|7 sSs=%Zauvrk0Gf@S3;+NC delta 195 zcmbQOIzfn8mVs#^vofR3CMPA.bit.CMPA < PWM_MAX) + { + EPwmRegs[Num]->CMPA.bit.CMPA++; + } + else + { + EPwm_DB_Direction[Num] = COUNT_DOWN; + EPwmRegs[Num]->CMPA.bit.CMPA--; + } + } + else + { + if(EPwmRegs[Num]->CMPA.bit.CMPA <= PWM_MIN) + { + EPwm_DB_Direction[Num] = COUNT_UP; + EPwmRegs[Num]->CMPA.bit.CMPA++; + } + else + { + EPwmRegs[Num]->CMPA.bit.CMPA--; + } + } + + EPwmTimerIntCount[Num]++; +} + + +void PWMAllInit(void) +{ +// +// Initialize the Device Peripherals: +// + EALLOW; + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0; + EDIS; + + uint16_t i; + + for(i = 2; i<=5; i++) + { + PWMInit(i, PERIOD); + } + PWMInit(11, PERIOD); + + EALLOW; + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1; + EDIS; +} + void PWMInitGpio(void) { @@ -18,17 +78,18 @@ void PWMInitGpio(void) InitEPwm3Gpio(); InitEPwm4Gpio(); InitEPwm5Gpio(); - InitEPwm6Gpio(); +// InitEPwm6Gpio(); } void PWMInitEnable(void) { - CpuSysRegs.PCLKCR2.bit.EPWM1=1; +// CpuSysRegs.PCLKCR2.bit.EPWM1=1; CpuSysRegs.PCLKCR2.bit.EPWM2=1; CpuSysRegs.PCLKCR2.bit.EPWM3=1; CpuSysRegs.PCLKCR2.bit.EPWM4=1; CpuSysRegs.PCLKCR2.bit.EPWM5=1; - CpuSysRegs.PCLKCR2.bit.EPWM6=1; +// CpuSysRegs.PCLKCR2.bit.EPWM6=1; + CpuSysRegs.PCLKCR2.bit.EPWM11=1; } void PWMInitInterruptEn(void) @@ -46,12 +107,26 @@ void PWMInitInterruptEn(void) EDIS; // This is needed to disable write to EALLOW protected registers + // Enable CPU INT3 which is connected to EPWM1-3 INT: + // + IER |= M_INT3; + + // + // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 + // +// PieCtrlRegs.PIEIER3.bit.INTx1 = 1; + PieCtrlRegs.PIEIER3.bit.INTx2 = 1; + PieCtrlRegs.PIEIER3.bit.INTx3 = 1; + PieCtrlRegs.PIEIER3.bit.INTx4 = 1; + PieCtrlRegs.PIEIER3.bit.INTx5 = 1; + // PieCtrlRegs.PIEIER3.bit.INTx6 = 1; + } -void PWMInit(uint16_t Num) +void PWMInit(uint16_t Num, uint16_t Period) { - EPwmRegs[Num]->TBPRD = PERIOD; // Set timer period + EPwmRegs[Num]->TBPRD = Period; // Set timer period EPwmRegs[Num]->TBPHS.bit.TBPHS = 0x0000; // Phase is 0 EPwmRegs[Num]->TBCTR = 0x0000; // Clear counter @@ -71,7 +146,7 @@ void PWMInit(uint16_t Num) // // Setup compare // - EPwmRegs[Num]->CMPA.bit.CMPA = PERIOD_2; + EPwmRegs[Num]->CMPA.bit.CMPA = Period/2; // // Set actions @@ -100,298 +175,5 @@ void PWMInit(uint16_t Num) } -void InitEPwm1Example() -{ - EPwm1Regs.TBPRD = PERIOD; // Set timer period - EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0 - EPwm1Regs.TBCTR = 0x0000; // Clear counter - - // - // Setup TBCLK - // - EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up - EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading - EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT - EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; - - EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO - EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; - EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; - EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; - - // - // Setup compare - // - EPwm1Regs.CMPA.bit.CMPA = PERIOD_2; - - // - // Set actions - // - EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero - EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; - - EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero - EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; - - // - // Active Low PWMs - Setup Deadband - // - EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; - EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; - EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; - EPwm1Regs.DBRED.bit.DBRED = EPWM_DB; - EPwm1Regs.DBFED.bit.DBFED = EPWM_DB; -// EPwm1_DB_Direction = COUNT_UP; - - // - // Interrupt where we will change the Deadband - // - EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event - EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT - EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event -} - -// -// InitEPwm2Example - Initialize EPWM2 configuration -// -void InitEPwm2Example() -{ - EPwm2Regs.TBPRD = PERIOD; // Set timer period - EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0 - EPwm2Regs.TBCTR = 0x0000; // Clear counter - - // - // Setup TBCLK - // - EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up - EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading - EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT - EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on - // the scope - - // - // Setup compare - // - EPwm2Regs.CMPA.bit.CMPA = PERIOD_2; - - // - // Set actions - // - EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero - EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; - - EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero - EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; - - // - // Active Low complementary PWMs - setup the deadband - // - EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; - EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; - EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; - EPwm2Regs.DBRED.bit.DBRED = EPWM_DB; - EPwm2Regs.DBFED.bit.DBFED = EPWM_DB; -// EPwm2_DB_Direction = COUNT_UP; - - // - // Interrupt where we will modify the deadband - // - EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event - EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT - EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event -} - -// -// InitEPwm3Example - Initialize EPWM3 configuration -// -void InitEPwm3Example() -{ - EPwm3Regs.TBPRD = PERIOD; // Set timer period - EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0 - EPwm3Regs.TBCTR = 0x0000; // Clear counter - - // - // Setup TBCLK - // - EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up - EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading - EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT - EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on - // the scope - - // - // Setup compare - // - EPwm3Regs.CMPA.bit.CMPA = PERIOD_2; - - // - // Set actions - // - EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero - EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; - - EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero - EPwm3Regs.AQCTLB.bit.CAD = AQ_SET; - - // - // Active high complementary PWMs - Setup the deadband - // - EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; - EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; - EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; - EPwm3Regs.DBRED.bit.DBRED = EPWM_DB; - EPwm3Regs.DBFED.bit.DBFED = EPWM_DB; -// EPwm3_DB_Direction = COUNT_UP; - - // - // Interrupt where we will change the deadband - // - EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event - EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT - EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event -} - - -void InitEPwm4Example() -{ - EPwm4Regs.TBPRD = PERIOD; // Set timer period - EPwm4Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0 - EPwm4Regs.TBCTR = 0x0000; // Clear counter - - // - // Setup TBCLK - // - EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up - EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading - EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT - EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on - // the scope - - // - // Setup compare - // - EPwm4Regs.CMPA.bit.CMPA = PERIOD_2; - - // - // Set actions - // - EPwm4Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero - EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR; - - EPwm4Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero - EPwm4Regs.AQCTLB.bit.CAD = AQ_SET; - - // - // Active high complementary PWMs - Setup the deadband - // - EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; - EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; - EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL; - EPwm4Regs.DBRED.bit.DBRED = EPWM_DB; - EPwm4Regs.DBFED.bit.DBFED = EPWM_DB; -// EPwm4_DB_Direction = COUNT_UP; - - // - // Interrupt where we will change the deadband - // - EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event - EPwm4Regs.ETSEL.bit.INTEN = 1; // Enable INT - EPwm4Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event -} - - -void InitEPwm5Example() -{ - EPwm5Regs.TBPRD = PERIOD; // Set timer period - EPwm5Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0 - EPwm5Regs.TBCTR = 0x0000; // Clear counter - - // - // Setup TBCLK - // - EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up - EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading - EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT - EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on - // the scope - - // - // Setup compare - // - EPwm5Regs.CMPA.bit.CMPA = PERIOD_2; - - // - // Set actions - // - EPwm5Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero - EPwm5Regs.AQCTLA.bit.CAD = AQ_CLEAR; - - EPwm5Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero - EPwm5Regs.AQCTLB.bit.CAD = AQ_SET; - - // - // Active high complementary PWMs - Setup the deadband - // - EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; - EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; - EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL; - EPwm5Regs.DBRED.bit.DBRED = EPWM_DB; - EPwm5Regs.DBFED.bit.DBFED = EPWM_DB; -// EPwm5_DB_Direction = COUNT_UP; - - // - // Interrupt where we will change the deadband - // - EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event - EPwm5Regs.ETSEL.bit.INTEN = 1; // Enable INT - EPwm5Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event -} - -void InitEPwm6Example() -{ - EPwm6Regs.TBPRD = PERIOD; // Set timer period - EPwm6Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0 - EPwm6Regs.TBCTR = 0x0000; // Clear counter - - // - // Setup TBCLK - // - EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up - EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading - EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT - EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on - // the scope - - // - // Setup compare - // - EPwm6Regs.CMPA.bit.CMPA = PERIOD_2; - - // - // Set actions - // - EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero - EPwm6Regs.AQCTLA.bit.CAD = AQ_CLEAR; - - EPwm6Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero - EPwm6Regs.AQCTLB.bit.CAD = AQ_SET; - - // - // Active high complementary PWMs - Setup the deadband - // - EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; - EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; - EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL; - EPwm6Regs.DBRED.bit.DBRED = EPWM_DB; - EPwm6Regs.DBFED.bit.DBFED = EPWM_DB; -// EPwm6_DB_Direction = COUNT_UP; - - // - // Interrupt where we will change the deadband - // - EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event - EPwm6Regs.ETSEL.bit.INTEN = 1; // Enable INT - EPwm6Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event -} diff --git a/Projects/epwm_test/src/pwm_init.h b/Projects/epwm_test/src/pwm_init.h index aca3052..1009be8 100644 --- a/Projects/epwm_test/src/pwm_init.h +++ b/Projects/epwm_test/src/pwm_init.h @@ -12,14 +12,15 @@ #define PERIOD 5000 #define EPWM_DB 300 #define PERIOD_2 PERIOD/2 -#define PWM_MAX PERIOD - 2*EPWM_DB +#define PWM_MAX PERIOD - EPWM_DB #define PWM_MIN EPWM_DB -void PWMInit(uint16_t Num); +void PWMInit(uint16_t Num, uint16_t Period); void PWMInitGpio(void); void PWMInitEnable(void); void PWMInitInterruptEn(void); +void PWMAllInit(void); void InitEPwm1Example(void); void InitEPwm2Example(void); @@ -28,8 +29,7 @@ void InitEPwm4Example(void); void InitEPwm5Example(void); void InitEPwm6Example(void); - - +void pwm_AutoChange(uint16_t Num); #endif /* SRC_PWM_INIT_H_ */ diff --git a/Projects/epwm_test/src/pwm_interrupts.c b/Projects/epwm_test/src/pwm_interrupts.c index 19f6830..3049f7b 100644 --- a/Projects/epwm_test/src/pwm_interrupts.c +++ b/Projects/epwm_test/src/pwm_interrupts.c @@ -7,24 +7,11 @@ #include "f28x_project.h" #include "pwm_init.h" +#include"frm_uart.h" -#define COUNT_UP 1 -#define COUNT_DOWN 0 - -Uint32 EPwm1TimerIntCount; -Uint32 EPwm2TimerIntCount; -Uint32 EPwm3TimerIntCount; -Uint32 EPwm4TimerIntCount; -Uint32 EPwm5TimerIntCount; -Uint32 EPwm6TimerIntCount; - -Uint16 EPwm1_DB_Direction; -Uint16 EPwm2_DB_Direction; -Uint16 EPwm3_DB_Direction; -Uint16 EPwm4_DB_Direction; -Uint16 EPwm5_DB_Direction; -Uint16 EPwm6_DB_Direction; +volatile Uint16 AutoChange = 1; +volatile Uint16 PWM_out = PERIOD_2; // @@ -32,33 +19,8 @@ Uint16 EPwm6_DB_Direction; // __interrupt void epwm1_isr(void) { - if(EPwm1_DB_Direction == COUNT_UP) - { - if(EPwm1Regs.CMPA.bit.CMPA < PWM_MAX) - { - EPwm1Regs.CMPA.bit.CMPA++; - } - else - { - EPwm1_DB_Direction = COUNT_DOWN; - EPwm1Regs.CMPA.bit.CMPA--; - } - } - else - { - if(EPwm1Regs.CMPA.bit.CMPA <= PWM_MIN) - { - EPwm1_DB_Direction = COUNT_UP; - EPwm1Regs.CMPA.bit.CMPA++; - } - else - { - EPwm1Regs.CMPA.bit.CMPA--; - } - } - - - EPwm1TimerIntCount++; + if(AutoChange) pwm_AutoChange(1); + else EPwm1Regs.CMPA.bit.CMPA = PWM_out; // // Clear INT flag for this timer @@ -76,32 +38,10 @@ __interrupt void epwm1_isr(void) // __interrupt void epwm2_isr(void) { - if(EPwm2_DB_Direction == COUNT_UP) - { - if(EPwm2Regs.CMPA.bit.CMPA < PWM_MAX) - { - EPwm2Regs.CMPA.bit.CMPA++; - } - else - { - EPwm2_DB_Direction = COUNT_DOWN; - EPwm2Regs.CMPA.bit.CMPA--; - } - } - else - { - if(EPwm2Regs.CMPA.bit.CMPA <= PWM_MIN) - { - EPwm2_DB_Direction = COUNT_UP; - EPwm2Regs.CMPA.bit.CMPA++; - } - else - { - EPwm2Regs.CMPA.bit.CMPA--; - } - } - EPwm2TimerIntCount++; - + if(AutoChange) pwm_AutoChange(2); + else EPwm2Regs.CMPA.bit.CMPA = PWM_out; + GpioDataRegs.GPADAT.bit.GPIO10 = 1; + FMSTR_enable_set(); // // Clear INT flag for this timer // @@ -111,6 +51,7 @@ __interrupt void epwm2_isr(void) // Acknowledge this interrupt to receive more interrupts from group 3 // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + GpioDataRegs.GPADAT.bit.GPIO10 = 0; } // @@ -118,32 +59,9 @@ __interrupt void epwm2_isr(void) // __interrupt void epwm3_isr(void) { - if(EPwm3_DB_Direction == COUNT_UP) - { - if(EPwm3Regs.CMPA.bit.CMPA < PWM_MAX) - { - EPwm3Regs.CMPA.bit.CMPA++; - } - else - { - EPwm3_DB_Direction = COUNT_DOWN; - EPwm3Regs.CMPA.bit.CMPA--; - } - } - else - { - if(EPwm3Regs.CMPA.bit.CMPA <= PWM_MIN) - { - EPwm3_DB_Direction = COUNT_UP; - EPwm3Regs.CMPA.bit.CMPA++; - } - else - { - EPwm3Regs.CMPA.bit.CMPA--; - } - } - EPwm3TimerIntCount++; - + if(AutoChange) pwm_AutoChange(3); + else EPwm3Regs.CMPA.bit.CMPA = PWM_out; + GpioDataRegs.GPADAT.bit.GPIO11 = 1; // // Clear INT flag for this timer // @@ -153,36 +71,13 @@ __interrupt void epwm3_isr(void) // Acknowledge this interrupt to receive more interrupts from group 3 // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + GpioDataRegs.GPADAT.bit.GPIO11 = 0; } __interrupt void epwm4_isr(void) { - if(EPwm4_DB_Direction == COUNT_UP) - { - if(EPwm4Regs.CMPA.bit.CMPA < PWM_MAX) - { - EPwm4Regs.CMPA.bit.CMPA++; - } - else - { - EPwm4_DB_Direction = COUNT_DOWN; - EPwm4Regs.CMPA.bit.CMPA--; - } - } - else - { - if(EPwm4Regs.CMPA.bit.CMPA <= PWM_MIN) - { - EPwm4_DB_Direction = COUNT_UP; - EPwm4Regs.CMPA.bit.CMPA++; - } - else - { - EPwm4Regs.CMPA.bit.CMPA--; - } - } - EPwm4TimerIntCount++; - + if(AutoChange) pwm_AutoChange(4); + else EPwm4Regs.CMPA.bit.CMPA = PWM_out; // // Clear INT flag for this timer // @@ -196,32 +91,8 @@ __interrupt void epwm4_isr(void) __interrupt void epwm5_isr(void) { - if(EPwm5_DB_Direction == COUNT_UP) - { - if(EPwm5Regs.CMPA.bit.CMPA < PWM_MAX) - { - EPwm5Regs.CMPA.bit.CMPA++; - } - else - { - EPwm5_DB_Direction = COUNT_DOWN; - EPwm5Regs.CMPA.bit.CMPA--; - } - } - else - { - if(EPwm5Regs.CMPA.bit.CMPA <= PWM_MIN) - { - EPwm5_DB_Direction = COUNT_UP; - EPwm5Regs.CMPA.bit.CMPA++; - } - else - { - EPwm5Regs.CMPA.bit.CMPA--; - } - } - EPwm5TimerIntCount++; - + if(AutoChange) pwm_AutoChange(5); + else EPwm5Regs.CMPA.bit.CMPA = PWM_out; // // Clear INT flag for this timer // @@ -235,32 +106,9 @@ __interrupt void epwm5_isr(void) __interrupt void epwm6_isr(void) { - if(EPwm6_DB_Direction == COUNT_UP) - { - if(EPwm6Regs.CMPA.bit.CMPA < PWM_MAX) - { - EPwm6Regs.CMPA.bit.CMPA++; - } - else - { - EPwm6_DB_Direction = COUNT_DOWN; - EPwm6Regs.CMPA.bit.CMPA--; - } - } - else - { - if(EPwm6Regs.CMPA.bit.CMPA <= PWM_MIN) - { - EPwm6_DB_Direction = COUNT_UP; - EPwm6Regs.CMPA.bit.CMPA++; - } - else - { - EPwm6Regs.CMPA.bit.CMPA--; - } - } - EPwm6TimerIntCount++; + if(AutoChange) pwm_AutoChange(6); + else EPwm6Regs.CMPA.bit.CMPA = PWM_out; // // Clear INT flag for this timer //