Ввёл настройки PLL для SYS = 160, AUX = 60

This commit is contained in:
Eugene 2023-12-07 15:05:47 +03:00
parent f6852a4bec
commit 2bd2955417
4 changed files with 332 additions and 37 deletions

View File

@ -66,6 +66,7 @@
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DEFINE.1001775310" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DEFINE" valueType="definedSymbols">
<listOptionValue builtIn="false" value="${COM_TI_C2000WARE_SOFTWARE_PACKAGE_SYMBOLS}"/>
<listOptionValue builtIn="false" value="SYS_160_AUX_60"/>
<listOptionValue builtIn="false" value="${SYSCONFIG_TOOL_SYMBOLS}"/>
<listOptionValue builtIn="false" value="CPU1"/>
<listOptionValue builtIn="false" value="USE_20MHZ_XTAL"/>
@ -396,6 +397,7 @@
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<listOptionValue builtIn="false" value="${COM_TI_C2000WARE_SOFTWARE_PACKAGE_SYMBOLS}"/>
<listOptionValue builtIn="false" value="SYS_160_AUX_60"/>
<listOptionValue builtIn="false" value="${SYSCONFIG_TOOL_SYMBOLS}"/>
<listOptionValue builtIn="false" value="CPU2"/>
<listOptionValue builtIn="false" value="USE_20MHZ_XTAL"/>
@ -519,9 +521,10 @@
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DEFINE.189898346" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DEFINE" valueType="definedSymbols">
<listOptionValue builtIn="false" value="${COM_TI_C2000WARE_SOFTWARE_PACKAGE_SYMBOLS}"/>
<listOptionValue builtIn="false" value="SYS_160_AUX_60"/>
<listOptionValue builtIn="false" value="${SYSCONFIG_TOOL_SYMBOLS}"/>
<listOptionValue builtIn="false" value="CPU1"/>
<listOptionValue builtIn="false" value="USE_20MHZ_XTAL"/>
<listOptionValue builtIn="false" value="USE_25MHZ_XTAL"/>
<listOptionValue builtIn="false" value="DEBUG"/>
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View File

@ -1,4 +1,21 @@
eclipse.preferences.version=1
encoding//CPU1_RAM_DEBUG/Freemaster/subdir_rules.mk=UTF-8
encoding//CPU1_RAM_DEBUG/Freemaster/subdir_vars.mk=UTF-8
encoding//CPU1_RAM_DEBUG/device/subdir_rules.mk=UTF-8
encoding//CPU1_RAM_DEBUG/device/subdir_vars.mk=UTF-8
encoding//CPU1_RAM_DEBUG/lib/subdir_rules.mk=UTF-8
encoding//CPU1_RAM_DEBUG/lib/subdir_vars.mk=UTF-8
encoding//CPU1_RAM_DEBUG/makefile=UTF-8
encoding//CPU1_RAM_DEBUG/objects.mk=UTF-8
encoding//CPU1_RAM_DEBUG/sources.mk=UTF-8
encoding//CPU1_RAM_DEBUG/src/ExternalEEPROM/subdir_rules.mk=UTF-8
encoding//CPU1_RAM_DEBUG/src/ExternalEEPROM/subdir_vars.mk=UTF-8
encoding//CPU1_RAM_DEBUG/src/Peripherals/subdir_rules.mk=UTF-8
encoding//CPU1_RAM_DEBUG/src/Peripherals/subdir_vars.mk=UTF-8
encoding//CPU1_RAM_DEBUG/src/subdir_rules.mk=UTF-8
encoding//CPU1_RAM_DEBUG/src/subdir_vars.mk=UTF-8
encoding//CPU1_RAM_DEBUG/subdir_rules.mk=UTF-8
encoding//CPU1_RAM_DEBUG/subdir_vars.mk=UTF-8
encoding//CPU1_RAM_RELEASE/Freemaster/subdir_rules.mk=UTF-8
encoding//CPU1_RAM_RELEASE/Freemaster/subdir_vars.mk=UTF-8
encoding//CPU1_RAM_RELEASE/device/subdir_rules.mk=UTF-8

View File

@ -74,6 +74,24 @@
#define OSC_FREQ 20
#ifdef SYS_160_AUX_60
//
// Multipliers and dividers to configure 160MHz SYSPLL output from 20MHz XTAL
//
#define SYS_IMULT IMULT_32
#define SYS_REFDIV REFDIV_2
#define SYS_ODIV ODIV_2
#define SYS_DIV PLLCLK_BY_1
//
// Multipliers and dividers to configure 60MHz AUXPLL output from 20MHz XTAL
//
#define AUX_IMULT IMULT_48
#define AUX_REFDIV REFDIV_2
#define AUX_ODIV ODIV_4
#define AUX_DIV AUXPLLRAWCLK_BY_2
#else //SYS200_AUX_125
//
// Multipliers and dividers to configure 200MHz SYSPLL output from 20MHz XTAL
//
@ -89,12 +107,30 @@
#define AUX_REFDIV REFDIV_2
#define AUX_ODIV ODIV_4
#define AUX_DIV AUXPLLRAWCLK_BY_1
#endif //SYS_160_AUX_200
#else // USE_25MHZ_XTAL
#define OSC_FREQ 25
#ifdef SYS_160_AUX_60
//
// Multipliers and dividers to configure 160MHz SYSPLL output from 20MHz XTAL
//
#define SYS_IMULT IMULT_64
#define SYS_REFDIV REFDIV_2
#define SYS_ODIV ODIV_5
#define SYS_DIV PLLCLK_BY_1
//
// Multipliers and dividers to configure 60MHz AUXPLL output from 20MHz XTAL
//
#define AUX_IMULT IMULT_24
#define AUX_REFDIV REFDIV_2
#define AUX_ODIV ODIV_5
#define AUX_DIV AUXPLLRAWCLK_BY_1
#else //SYS200_AUX_125
//
// Multipliers and dividers to configure 200MHz SYSPLL output from 25MHz XTAL
//
@ -111,8 +147,9 @@
#define AUX_ODIV ODIV_4
#define AUX_DIV AUXPLLRAWCLK_BY_1
#endif
#endif //SYS_160_AUX_60
#endif //USE_25MHZ_XTAL
//
// InitSysCtrl - Initialization of system resources.
//

View File

@ -1,6 +1,13 @@
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@ -23,7 +30,14 @@
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@ -46,7 +60,14 @@
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@ -69,7 +90,14 @@
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@ -92,7 +120,14 @@
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@ -115,7 +150,14 @@
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@ -138,7 +180,14 @@
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@ -161,7 +210,14 @@
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@ -184,7 +240,14 @@
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@ -207,7 +270,14 @@
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@ -230,7 +300,14 @@
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@ -253,7 +330,14 @@
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@ -276,7 +360,14 @@
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@ -299,7 +390,14 @@
<device HW_revision="1" XML_version="1.2" description="" id="TMS320F28388D_0" partnum="TMS320F28388D" simulation="no">
@ -322,7 +420,14 @@
<router HW_revision="1.0" XML_version="1.2" description="ICEPick_C router" id="IcePick_C_0" isa="ICEPICK_C">
@ -345,7 +450,14 @@
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@ -368,7 +480,14 @@
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@ -391,7 +510,14 @@
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@ -414,7 +540,14 @@
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@ -437,7 +570,14 @@
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@ -460,7 +600,14 @@
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@ -483,7 +630,14 @@
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@ -506,7 +660,14 @@
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@ -529,7 +690,14 @@
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@ -736,7 +960,14 @@
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@ -759,7 +990,14 @@
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