diff --git a/Projects/epwm_test/.ccsproject b/Projects/epwm_test/.ccsproject
new file mode 100644
index 0000000..36457b0
--- /dev/null
+++ b/Projects/epwm_test/.ccsproject
@@ -0,0 +1,18 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Projects/epwm_test/.cproject b/Projects/epwm_test/.cproject
new file mode 100644
index 0000000..4ee4a35
--- /dev/null
+++ b/Projects/epwm_test/.cproject
@@ -0,0 +1,253 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Projects/epwm_test/.gitignore b/Projects/epwm_test/.gitignore
new file mode 100644
index 0000000..0356e98
--- /dev/null
+++ b/Projects/epwm_test/.gitignore
@@ -0,0 +1,2 @@
+/CPU1_FLASH/
+/CPU1_RAM/
diff --git a/Projects/epwm_test/.project b/Projects/epwm_test/.project
new file mode 100644
index 0000000..6717ede
--- /dev/null
+++ b/Projects/epwm_test/.project
@@ -0,0 +1,37 @@
+
+
+ epwm_test
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ com.ti.ccstudio.core.ccsNature
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.core.ccnature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
+ C2000WARE_COMMON_INCLUDE
+ $%7BCOM_TI_C2000WARE_SOFTWARE_PACKAGE_INSTALL_DIR%7D/device_support/f2838x/common/include
+
+
+ C2000WARE_HEADERS_INCLUDE
+ $%7BCOM_TI_C2000WARE_SOFTWARE_PACKAGE_INSTALL_DIR%7D/device_support/f2838x/headers/include
+
+
+
diff --git a/Projects/epwm_test/.settings/org.eclipse.cdt.codan.core.prefs b/Projects/epwm_test/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644
index 0000000..f653028
--- /dev/null
+++ b/Projects/epwm_test/.settings/org.eclipse.cdt.codan.core.prefs
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
diff --git a/Projects/epwm_test/.settings/org.eclipse.cdt.debug.core.prefs b/Projects/epwm_test/.settings/org.eclipse.cdt.debug.core.prefs
new file mode 100644
index 0000000..2adc7b1
--- /dev/null
+++ b/Projects/epwm_test/.settings/org.eclipse.cdt.debug.core.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
diff --git a/Projects/epwm_test/.settings/org.eclipse.core.resources.prefs b/Projects/epwm_test/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 0000000..e7ef01a
--- /dev/null
+++ b/Projects/epwm_test/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,31 @@
+eclipse.preferences.version=1
+encoding//CPU1_FLASH/Freemaster/subdir_rules.mk=UTF-8
+encoding//CPU1_FLASH/Freemaster/subdir_vars.mk=UTF-8
+encoding//CPU1_FLASH/lib/subdir_rules.mk=UTF-8
+encoding//CPU1_FLASH/lib/subdir_vars.mk=UTF-8
+encoding//CPU1_FLASH/makefile=UTF-8
+encoding//CPU1_FLASH/objects.mk=UTF-8
+encoding//CPU1_FLASH/sources.mk=UTF-8
+encoding//CPU1_FLASH/src/ExternalEEPROM/subdir_rules.mk=UTF-8
+encoding//CPU1_FLASH/src/ExternalEEPROM/subdir_vars.mk=UTF-8
+encoding//CPU1_FLASH/src/Peripherals/subdir_rules.mk=UTF-8
+encoding//CPU1_FLASH/src/Peripherals/subdir_vars.mk=UTF-8
+encoding//CPU1_FLASH/src/subdir_rules.mk=UTF-8
+encoding//CPU1_FLASH/src/subdir_vars.mk=UTF-8
+encoding//CPU1_FLASH/subdir_rules.mk=UTF-8
+encoding//CPU1_FLASH/subdir_vars.mk=UTF-8
+encoding//CPU1_RAM/Freemaster/subdir_rules.mk=UTF-8
+encoding//CPU1_RAM/Freemaster/subdir_vars.mk=UTF-8
+encoding//CPU1_RAM/lib/subdir_rules.mk=UTF-8
+encoding//CPU1_RAM/lib/subdir_vars.mk=UTF-8
+encoding//CPU1_RAM/makefile=UTF-8
+encoding//CPU1_RAM/objects.mk=UTF-8
+encoding//CPU1_RAM/sources.mk=UTF-8
+encoding//CPU1_RAM/src/ExternalEEPROM/subdir_rules.mk=UTF-8
+encoding//CPU1_RAM/src/ExternalEEPROM/subdir_vars.mk=UTF-8
+encoding//CPU1_RAM/src/Peripherals/subdir_rules.mk=UTF-8
+encoding//CPU1_RAM/src/Peripherals/subdir_vars.mk=UTF-8
+encoding//CPU1_RAM/src/subdir_rules.mk=UTF-8
+encoding//CPU1_RAM/src/subdir_vars.mk=UTF-8
+encoding//CPU1_RAM/subdir_rules.mk=UTF-8
+encoding//CPU1_RAM/subdir_vars.mk=UTF-8
diff --git a/Projects/epwm_test/2838x_FLASH_lnk_cpu1.cmd b/Projects/epwm_test/2838x_FLASH_lnk_cpu1.cmd
new file mode 100644
index 0000000..f85e32f
--- /dev/null
+++ b/Projects/epwm_test/2838x_FLASH_lnk_cpu1.cmd
@@ -0,0 +1,137 @@
+
+MEMORY
+{
+ /* BEGIN is used for the "boot to Flash" bootloader mode */
+ BEGIN : origin = 0x080000, length = 0x000002
+ BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
+ RAMM0 : origin = 0x0001B1, length = 0x00024F
+ RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
+// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
+ RAMD0 : origin = 0x00C000, length = 0x000800
+ RAMD1 : origin = 0x00C800, length = 0x000800
+ RAMLS0 : origin = 0x008000, length = 0x000800
+ RAMLS1 : origin = 0x008800, length = 0x000800
+ RAMLS2 : origin = 0x009000, length = 0x000800
+ RAMLS3 : origin = 0x009800, length = 0x000800
+ RAMLS4 : origin = 0x00A000, length = 0x000800
+ RAMLS5 : origin = 0x00A800, length = 0x000800
+ RAMLS6 : origin = 0x00B000, length = 0x000800
+ RAMLS7 : origin = 0x00B800, length = 0x000800
+ RAMGS0 : origin = 0x00D000, length = 0x001000
+ RAMGS1 : origin = 0x00E000, length = 0x001000
+ RAMGS2 : origin = 0x00F000, length = 0x001000
+ RAMGS3 : origin = 0x010000, length = 0x001000
+ RAMGS4 : origin = 0x011000, length = 0x001000
+ RAMGS5 : origin = 0x012000, length = 0x001000
+ RAMGS6 : origin = 0x013000, length = 0x001000
+ RAMGS7 : origin = 0x014000, length = 0x001000
+ RAMGS8 : origin = 0x015000, length = 0x001000
+ RAMGS9 : origin = 0x016000, length = 0x001000
+ RAMGS10 : origin = 0x017000, length = 0x001000
+ RAMGS11 : origin = 0x018000, length = 0x001000
+ RAMGS12 : origin = 0x019000, length = 0x001000
+ RAMGS13 : origin = 0x01A000, length = 0x001000
+ RAMGS14 : origin = 0x01B000, length = 0x001000
+ RAMGS15 : origin = 0x01C000, length = 0x000FF8
+// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
+
+ /* Flash sectors */
+ FLASH0 : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
+ FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
+ FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
+ FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
+ FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
+ FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
+ FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
+ FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
+ FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
+ FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
+ FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
+ FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
+ FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
+ FLASH13 : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
+// FLASH13_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
+
+ CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
+ CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
+ CPUTOCMRAM : origin = 0x039000, length = 0x000800
+ CMTOCPURAM : origin = 0x038000, length = 0x000800
+
+ CANA_MSG_RAM : origin = 0x049000, length = 0x000800
+ CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
+
+ RESET : origin = 0x3FFFC0, length = 0x000002
+}
+
+SECTIONS
+{
+ codestart : > BEGIN, ALIGN(8)
+ .text : >> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(8)
+ .cinit : > FLASH4, ALIGN(8)
+ .switch : > FLASH1, ALIGN(8)
+ .reset : > RESET, TYPE = DSECT /* not used, */
+ .stack : > RAMM1
+
+#if defined(__TI_EABI__)
+ .init_array : > FLASH1, ALIGN(8)
+ .bss : > RAMGS0
+ .bss:output : > RAMLS3
+ .bss:cio : > RAMLS5
+ .data : > RAMLS5
+ .sysmem : > RAMLS5
+ /* Initalized sections go in Flash */
+ .const : > FLASH5, ALIGN(8)
+#else
+ .pinit : > FLASH1, ALIGN(8)
+ .ebss : > RAMLS5
+ .esysmem : > RAMLS5
+ .cio : > RAMLS5
+ /* Initalized sections go in Flash */
+ .econst : >> FLASH4 | FLASH5, ALIGN(8)
+#endif
+
+ ramgs0 : > RAMGS0, type=NOINIT
+ ramgs1 : > RAMGS1, type=NOINIT
+
+ MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
+ MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
+ MSGRAM_CPU_TO_CM : > CPUTOCMRAM, type=NOINIT
+ MSGRAM_CM_TO_CPU : > CMTOCPURAM, type=NOINIT
+
+ /* The following section definition are for SDFM examples */
+ Filter_RegsFile : > RAMGS0
+ Filter1_RegsFile : > RAMGS1, fill=0x1111
+ Filter2_RegsFile : > RAMGS2, fill=0x2222
+ Filter3_RegsFile : > RAMGS3, fill=0x3333
+ Filter4_RegsFile : > RAMGS4, fill=0x4444
+ Difference_RegsFile : >RAMGS5, fill=0x3333
+
+ #if defined(__TI_EABI__)
+ .TI.ramfunc : {} LOAD = FLASH3,
+ RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+ LOAD_START(RamfuncsLoadStart),
+ LOAD_SIZE(RamfuncsLoadSize),
+ LOAD_END(RamfuncsLoadEnd),
+ RUN_START(RamfuncsRunStart),
+ RUN_SIZE(RamfuncsRunSize),
+ RUN_END(RamfuncsRunEnd),
+ ALIGN(8)
+ #else
+ .TI.ramfunc : {} LOAD = FLASH3,
+ RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+ LOAD_START(_RamfuncsLoadStart),
+ LOAD_SIZE(_RamfuncsLoadSize),
+ LOAD_END(_RamfuncsLoadEnd),
+ RUN_START(_RamfuncsRunStart),
+ RUN_SIZE(_RamfuncsRunSize),
+ RUN_END(_RamfuncsRunEnd),
+ ALIGN(8)
+ #endif
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
diff --git a/Projects/epwm_test/2838x_RAM_combined_lnk_cpu1.cmd b/Projects/epwm_test/2838x_RAM_combined_lnk_cpu1.cmd
new file mode 100644
index 0000000..b16fad2
--- /dev/null
+++ b/Projects/epwm_test/2838x_RAM_combined_lnk_cpu1.cmd
@@ -0,0 +1,97 @@
+MEMORY
+{
+ /* BEGIN is used for the "boot to SARAM" bootloader mode */
+ BEGIN : origin = 0x000000, length = 0x000002
+ BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
+ RAMM0 : origin = 0x0001B1, length = 0x00024F
+ RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
+// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
+ RAMD01 : origin = 0x00C000, length = 0x001000
+ RAMLS02 : origin = 0x008000, length = 0x001800
+ RAMLS3 : origin = 0x009800, length = 0x000800
+ RAMLS4 : origin = 0x00A000, length = 0x000800
+ RAMLS56 : origin = 0x00A800, length = 0x001000
+ RAMLS7 : origin = 0x00B800, length = 0x000800
+ RAMGS0 : origin = 0x00D000, length = 0x001000
+ RAMGS1 : origin = 0x00E000, length = 0x001000
+ RAMGS2 : origin = 0x00F000, length = 0x001000
+ RAMGS3 : origin = 0x010000, length = 0x001000
+ RAMGS4 : origin = 0x011000, length = 0x001000
+ RAMGS5 : origin = 0x012000, length = 0x001000
+ RAMGS6 : origin = 0x013000, length = 0x001000
+ RAMGS7 : origin = 0x014000, length = 0x001000
+ RAMGS8 : origin = 0x015000, length = 0x001000
+ RAMGS9 : origin = 0x016000, length = 0x001000
+ RAMGS101112 : origin = 0x017000, length = 0x003000
+ RAMGS13 : origin = 0x01A000, length = 0x001000
+ RAMGS14 : origin = 0x01B000, length = 0x001000
+ RAMGS15 : origin = 0x01C000, length = 0x000FF8
+// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
+
+ /* Flash sectors */
+ FLASH0 : origin = 0x080000, length = 0x002000 /* on-chip Flash */
+ FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
+ FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
+ FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
+ FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
+ FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
+ FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
+ FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
+ FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
+ FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
+ FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
+ FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
+ FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
+ FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
+ CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
+ CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
+
+ CPUTOCMRAM : origin = 0x039000, length = 0x000800
+ CMTOCPURAM : origin = 0x038000, length = 0x000800
+
+ CANA_MSG_RAM : origin = 0x049000, length = 0x000800
+ CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
+ RESET : origin = 0x3FFFC0, length = 0x000002
+}
+
+
+SECTIONS
+{
+ codestart : > BEGIN
+ .text : >> RAMD01 | RAMLS02 | RAMLS3 | RAMGS101112
+ .cinit : > RAMM0
+ .switch : > RAMM0
+ .reset : > RESET, TYPE = DSECT /* not used, */
+
+ .stack : > RAMM1
+#if defined(__TI_EABI__)
+ .bss : >> RAMLS56 | RAMGS101112
+ .bss:output : > RAMLS3
+ .init_array : > RAMM0
+ .const : > RAMLS56
+ .data : >> RAMLS56 | RAMLS7 | RAMGS101112
+ .sysmem : > RAMLS4
+#else
+ .pinit : > RAMM0
+ .ebss : >> RAMLS56
+ .econst : > RAMLS56
+ .esysmem : > RAMLS56
+#endif
+
+ ramgs0 : > RAMGS0, type=NOINIT
+ ramgs1 : > RAMGS1, type=NOINIT
+
+ MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
+ MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
+ MSGRAM_CPU_TO_CM > CPUTOCMRAM, type=NOINIT
+ MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT
+
+ .TI.ramfunc : {} > RAMM0
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster.h b/Projects/epwm_test/Freemaster/PE_freemaster.h
new file mode 100644
index 0000000..9039b84
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster.h
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster.h
+*
+* @brief FreeMASTER Driver main API header file
+*
+* @version 1.0.10.0
+*
+* @date Oct-22-2007
+*
+*******************************************************************************
+*
+* This is the only header file needed to be included by the user application
+* to implement the FreeMASTER interface. In addition, user has to write her
+* "PE_freemaster_cfg.h" configuration file and put it anywhere on the #include path
+*
+*******************************************************************************/
+
+#ifndef __FREEMASTER_H
+#define __FREEMASTER_H
+
+/* identify our current platform */
+#define FMSTR_PLATFORM_56F8xxx 1
+
+/* user configuration */
+#include "PE_freemaster_cfg.h"
+
+/*****************************************************************************
+* Global types
+******************************************************************************/
+
+
+
+typedef unsigned long FMSTR_ADDR; /* CPU address type (use integer data type on 56F8xxx) */
+typedef unsigned short FMSTR_SIZE; /* general size type (at least 16 bits) */
+typedef unsigned short FMSTR_BOOL; /* general boolean type */
+
+/* application command-specific types */
+typedef unsigned short FMSTR_APPCMD_CODE;
+typedef unsigned short FMSTR_APPCMD_DATA, *FMSTR_APPCMD_PDATA;
+typedef unsigned short FMSTR_APPCMD_RESULT;
+
+/* pointer to application command callback handler */
+typedef FMSTR_APPCMD_RESULT (*FMSTR_PAPPCMDFUNC)(FMSTR_APPCMD_CODE,FMSTR_APPCMD_PDATA,FMSTR_SIZE);
+
+/* pipe-related types */
+typedef void* FMSTR_HPIPE; /* pipe handle */
+typedef unsigned short FMSTR_PIPE_PORT; /* pipe port identifier (unsigned, 7 bits used) */
+typedef unsigned short FMSTR_PIPE_SIZE; /* pipe buffer size type (unsigned, at least 8 bits) */
+
+/* pointer to pipe event handler */
+typedef void (*FMSTR_PPIPEFUNC)(FMSTR_HPIPE);
+
+/*****************************************************************************
+* TSA-related user types and macros
+******************************************************************************/
+
+#include "PE_freemaster_tsa.h"
+
+/*****************************************************************************
+* Constants
+******************************************************************************/
+
+/* application command status information */
+#define FMSTR_APPCMDRESULT_NOCMD 0xffU
+#define FMSTR_APPCMDRESULT_RUNNING 0xfeU
+#define MFSTR_APPCMDRESULT_LASTVALID 0xf7U /* F8-FF are reserved */
+
+/* recorder time base declaration helpers */
+#define FMSTR_REC_BASE_SECONDS(x) ((x) & 0x3fffU)
+#define FMSTR_REC_BASE_MILLISEC(x) (((x) & 0x3fffU) | 0x4000U)
+#define FMSTR_REC_BASE_MICROSEC(x) (((x) & 0x3fffU) | 0x8000U)
+#define FMSTR_REC_BASE_NANOSEC(x) (((x) & 0x3fffU) | 0xc000U)
+
+/*****************************************************************************
+* Global functions
+******************************************************************************/
+
+/* FreeMASTER serial communication API */
+void FMSTR_Init(void); /* general initiazlation */
+void FMSTR_Poll(void); /* polling call, use in SHORT_INTR and POLL_DRIVEN modes */
+void FMSTR_Isr(void); /* SCI/JTAG interrupt handler for LONG_INTR and SHORT_INTR modes */
+
+/* recorder API */
+void FMSTR_Recorder(void);
+void FMSTR_TriggerRec(void);
+void FMSTR_SetUpRecBuff(FMSTR_ADDR nBuffAddr, FMSTR_SIZE nBuffSize);
+
+/* Application commands API */
+FMSTR_APPCMD_CODE FMSTR_GetAppCmd(void);
+FMSTR_APPCMD_PDATA FMSTR_GetAppCmdData(FMSTR_SIZE* pDataLen);
+FMSTR_BOOL FMSTR_RegisterAppCmdCall(FMSTR_APPCMD_CODE nAppCmdCode, FMSTR_PAPPCMDFUNC pCallbackFunc);
+
+void FMSTR_AppCmdAck(FMSTR_APPCMD_RESULT nResultCode);
+void FMSTR_AppCmdSetResponseData(FMSTR_ADDR nResultDataAddr, FMSTR_SIZE nResultDataLen);
+
+/* Transport layer API */
+FMSTR_HPIPE FMSTR_PipeOpen(FMSTR_PIPE_PORT nPort, FMSTR_PPIPEFUNC pCallback,
+ FMSTR_ADDR pRxBuff, FMSTR_PIPE_SIZE nRxSize,
+ FMSTR_ADDR pTxBuff, FMSTR_PIPE_SIZE nTxSize);
+void FMSTR_PipeClose(FMSTR_HPIPE hpipe);
+FMSTR_PIPE_SIZE FMSTR_PipeWrite(FMSTR_HPIPE hpipe, FMSTR_ADDR addr, FMSTR_PIPE_SIZE size);
+FMSTR_PIPE_SIZE FMSTR_PipeRead(FMSTR_HPIPE hpipe, FMSTR_ADDR addr, FMSTR_PIPE_SIZE size);
+
+#endif /* __FREEMASTER_H */
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.c b/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.c
new file mode 100644
index 0000000..cd97838
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.c
@@ -0,0 +1,306 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2007 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_56F8xxx.c
+*
+* @brief FreeMASTER Driver 56F800E-hardware dependent stuff
+*
+* @version 1.0.9.0
+*
+* @date May-17-2007
+*
+*******************************************************************************/
+
+#include "PE_freemaster.h"
+#include "PE_freemaster_private.h"
+
+/*******************************************************************************
+*
+* @brief API: Main SCI/JTAG Interrupt handler call
+*
+* This Interrupt Service Routine handles the SCI interrupts for the FreeMASTER
+* driver. In case you want to handle the interrupt in the application yourselves,
+* call the FMSTR_ProcessSCI function which does the same job but is not compiled
+* as an Interrupt Service Routine.
+*
+* In poll-driven mode (FMSTR_POLL_DRIVEN) this function does nothing.
+*
+*******************************************************************************/
+
+/* 56F8xxx interrupt routine declaration, user has to */
+/* direct vector to the FMSTR_Isr function */
+
+
+void FMSTR_Isr(void)
+{
+#if FMSTR_LONG_INTR || FMSTR_SHORT_INTR
+
+ /* process serial interface */
+#if FMSTR_USE_SCI
+ FMSTR_ProcessSCI();
+
+#elif FMSTR_USE_JTAG
+ FMSTR_ProcessJTAG();
+#endif
+
+#endif
+}
+
+/* automatic inlining may cause problems with C calling convention assumed below */
+
+
+/**************************************************************************//*!
+*
+* @brief The "memcpy" used internally in FreeMASTER driver
+*
+* @param nDestAddr - destination memory address
+* @param nSrcAddr - source memory address
+* @param nSize - memory size (always in bytes)
+*
+* @return This function returns a pointer to next destination byte
+*
+******************************************************************************
+*
+* This function accepts both 16bit or 32bit address and works correctly
+* even in the SDM mode. Buffer address is a standard ANSI C pointer
+*
+* Warning: This call assumes CodeWarrior style of passing parameters,
+* i.e. 32 bit operands passed in A and B accumulators
+*
+* Warning2: FMSTR_ADDR type MUST be numeric! (UWord type)
+*
+******************************************************************************/
+
+void FMSTR_CopyMemory(FMSTR_ADDR nDestAddr, FMSTR_ADDR nSrcAddr, FMSTR_SIZE8 nSize)
+{
+ FMSTR_U8* ps = (FMSTR_U8*) nSrcAddr;
+ FMSTR_U8* pd = (FMSTR_U8*) nDestAddr;
+
+// nSize = nSize>>1;
+
+ while(nSize--)
+ *pd++ = *ps++;
+}
+
+/**************************************************************************//*!
+*
+* @brief Write-into the communication buffer memory
+*
+* @param pDestBuff - pointer to destination memory in communication buffer
+* @param nSrcAddr - source memory address
+* @param nSize - buffer size (always in bytes)
+*
+* @return This function returns a pointer to next byte in comm. buffer
+*
+******************************************************************************
+*
+* This function accepts both 16bit or 32bit address and works correctly
+* even in the SDM mode. Buffer address is a standard ANSI C pointer
+*
+* Warning: This call assumes CodeWarrior style of passing parameters,
+* i.e. 32 bit operands passed in A and B accumulators
+*
+* Warning2: FMSTR_ADDR type MUST be numeric! (UWord type)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_CopyToBuffer(FMSTR_BPTR pDestBuff, FMSTR_ADDR nSrcAddr, FMSTR_SIZE8 nSize)
+{
+ FMSTR_U8* ps = (FMSTR_U8*) nSrcAddr;
+ FMSTR_U8* pd = (FMSTR_U8*) pDestBuff;
+
+ nSize = nSize>>1;
+ //Texas code composer variant
+ while(nSize--)
+ {
+ *pd++ = *ps;
+ *pd++ = (*ps++) >> 8; //*pd++ = *ps++;
+ }
+ return (FMSTR_BPTR) pd;
+}
+
+/**************************************************************************//*!
+*
+* @brief Read-out memory from communication buffer
+*
+* @param nDestAddr - destination memory address
+* @param pSrcBuff - pointer to source memory in communication buffer
+* @param nSize - buffer size (always in bytes)
+*
+* @return This function returns a pointer to next byte in comm. buffer
+*
+******************************************************************************
+*
+* This function accepts both 16bit or 32bit address and works correctly
+* even in the SDM mode. Buffer address is a standard ANSI C pointer
+*
+* Warning: This call assumes CodeWarrior style of passing parameters,
+* i.e. 32 bit operands passed in A and B accumulators
+*
+* Warning2: FMSTR_ADDR type MUST be numeric! (UWord type)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_CopyFromBuffer(FMSTR_ADDR nDestAddr, FMSTR_BPTR pSrcBuff, FMSTR_SIZE8 nSize)
+{
+ FMSTR_U8* ps = (FMSTR_U8*) pSrcBuff;
+ FMSTR_U8* pd = (FMSTR_U8*) nDestAddr;
+ //Texas code composer variant
+
+ nSize = nSize>>1;
+
+ while(nSize--)
+ {
+ *pd = *ps++;
+ *pd++ += (*ps++)<<8; // *pd++ = *ps++;
+ }
+ return (FMSTR_BPTR) ps;
+}
+
+
+/**************************************************************************//*!
+*
+* @brief Read-out memory from communication buffer, perform AND-masking
+*
+* @param nDestAddr - destination memory address
+* @param pSrcBuff - source memory in communication buffer, mask follows data
+* @param nSize - buffer size (always in bytes)
+*
+******************************************************************************
+*
+* This function accepts both 16bit or 32bit address and works correctly
+* even in the SDM mode. Buffer address is a standard ANSI C pointer
+*
+* Warning: This call assumes CodeWarrior style of passing parameters,
+* i.e. 32 bit operands passed in A and B accumulators
+*
+* Warning2: FMSTR_ADDR type MUST be numeric! (UWord type)
+*
+******************************************************************************/
+
+void FMSTR_CopyFromBufferWithMask(FMSTR_ADDR nDestAddr, FMSTR_BPTR pSrcBuff, FMSTR_SIZE8 nSize)
+{
+ FMSTR_U8* ps = (FMSTR_U8*) pSrcBuff;
+ FMSTR_U8* pd = (FMSTR_U8*) nDestAddr;
+ FMSTR_U8* pm = ps + nSize;
+ FMSTR_U8 mask, stmp, dtmp;
+
+ while(nSize--)
+ {
+ mask = *pm++;
+ stmp = *ps++;
+ dtmp = *pd;
+
+ /* perform AND-masking */
+ stmp = (FMSTR_U8) ((stmp & mask) | (dtmp & ~mask));
+
+ /* put the result back */
+ *pd++ = stmp;
+ }
+}
+
+
+/**************************************************************************//*!
+*
+* @brief Select an address size to be used in next access to a comm. buffer
+*
+* @param bNextAddrIsEx - when non zero, next expected address is 32bit wide
+* - when zero, next expected address is 16bit wide
+*
+******************************************************************************/
+
+#if FMSTR_USE_EX_CMDS && FMSTR_USE_NOEX_CMDS
+
+static FMSTR_BOOL pcm_bUseExAddr;
+
+void FMSTR_SetExAddr(FMSTR_BOOL bNextAddrIsEx)
+{
+ pcm_bUseExAddr = bNextAddrIsEx;
+}
+
+#endif
+
+/**************************************************************************//*!
+*
+* @brief Fetch 16/32 bit address from buffer
+*
+* @param pAddr - ANSI C pointer to a variable which is to receive the result
+* @param pSrc - pointer to a source memory in communication buffer
+*
+* @return This function returns a pointer to next byte in comm. buffer
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_AddressFromBuffer(FMSTR_ADDR* pAddr, FMSTR_BPTR pSrc)
+{
+ /* do we have to differentiate the EX and non-EX access? */
+#if FMSTR_USE_EX_CMDS && FMSTR_USE_NOEX_CMDS
+ if(pcm_bUseExAddr)
+#endif
+ {
+#if FMSTR_USE_EX_CMDS
+ /* fetch 32bit value */
+ FMSTR_U32 nAddr32;
+ pSrc = FMSTR_ValueFromBuffer32(&nAddr32, pSrc);
+ /* and convert it to the address type */
+ *pAddr = (FMSTR_ADDR) nAddr32;
+#endif
+ }
+#if FMSTR_USE_EX_CMDS && FMSTR_USE_NOEX_CMDS
+ else
+#endif
+ {
+#if FMSTR_USE_NOEX_CMDS
+ /* fetch 16bit value */
+ FMSTR_U16 nAddr16;
+ pSrc = FMSTR_ValueFromBuffer16(&nAddr16, pSrc);
+ /* and convert it to the address type */
+ *pAddr = (FMSTR_ADDR) nAddr16; //+ ((FMSTR_ADDR) *(&nAddr16+1))<<8;
+#endif
+ }
+
+ return pSrc;
+}
+
+/**************************************************************************//*!
+*
+* @brief Store 16/32 bit address to buffer
+*
+* @param pDest - pointer to a destination memory in communication buffer
+* @param pSrc - memory address value
+*
+* @return This function returns a pointer to next byte in comm. buffer
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_AddressToBuffer(FMSTR_BPTR pDest, FMSTR_ADDR nAddr)
+{
+ /* do we have to differentiate the EX and non-EX access? */
+#if FMSTR_USE_EX_CMDS && FMSTR_USE_NOEX_CMDS
+ if(pcm_bUseExAddr)
+#endif
+ {
+#if FMSTR_USE_EX_CMDS
+ /* put the address as a 32bit value */
+ pDest = FMSTR_ValueToBuffer32(pDest, (FMSTR_U32) nAddr);
+#endif
+ }
+#if FMSTR_USE_EX_CMDS && FMSTR_USE_NOEX_CMDS
+ else
+#endif
+ {
+#if FMSTR_USE_NOEX_CMDS
+ /* put the address as a 16bit value */
+ pDest = FMSTR_ValueToBuffer16(pDest, (FMSTR_U16) nAddr);
+#endif
+ }
+
+ return pDest;
+}
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.h b/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.h
new file mode 100644
index 0000000..87b8e95
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_56F8xxx.h
@@ -0,0 +1,377 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_56F8xxx.h
+*
+* @brief FreeMASTER Driver hardware dependent stuff
+*
+* @version 1.0.8.0
+*
+* @date May-17-2007
+*
+*******************************************************************************/
+
+#ifndef __FREEMASTER_56F8xxx_H
+#define __FREEMASTER_56F8xxx_H
+
+#include "PE_freemaster.h"
+/******************************************************************************
+* platform-specific default configuration
+******************************************************************************/
+
+/* using 16bit addressing commands */
+#ifndef FMSTR_USE_NOEX_CMDS
+#define FMSTR_USE_NOEX_CMDS 1
+#endif
+
+/* using 32bit addressing commands */
+#ifndef FMSTR_USE_EX_CMDS
+#define FMSTR_USE_EX_CMDS 1
+#endif
+
+/* using inline access to buffer memory */
+#ifndef FMSTR_USE_INLINE_BUFFER_ACCESS
+#define FMSTR_USE_INLINE_BUFFER_ACCESS 0
+#endif
+
+/*****************************************************************************
+* Board configuration information
+******************************************************************************/
+
+#define FMSTR_PROT_VER 3U /* protocol version 3 */
+#define FMSTR_CFG_FLAGS 0U /* board info flags */
+#define FMSTR_CFG_BUS_WIDTH 2U /* data bus width = 1*/
+#define FMSTR_GLOB_VERSION_MAJOR 2U /* driver version */
+#define FMSTR_GLOB_VERSION_MINOR 0U
+#define FMSTR_IDT_STRING "56F8xxx FreeMASTER Driver"
+#define FMSTR_TSA_FLAGS FMSTR_TSA_INFO_HV2BA /* HawkV2 TSA workaround */
+
+/******************************************************************************
+* platform-specific types
+******************************************************************************/
+
+typedef unsigned char FMSTR_U8; /* smallest memory entity (mostly 8bit) */
+typedef unsigned short FMSTR_U16; /* 16bit value */
+typedef unsigned long FMSTR_U32; /* 32bit value */
+
+typedef signed char FMSTR_S8; /* signed 8bit value */
+typedef signed short FMSTR_S16; /* signed 16bit value */
+typedef signed long FMSTR_S32; /* signed 32bit value */
+
+typedef unsigned short FMSTR_FLAGS; /* type to be union-ed with flags (at least 8 bits) */
+typedef unsigned short FMSTR_SIZE8; /* size value (at least 8 bits) */
+typedef signed short FMSTR_INDEX; /* general for-loop index (must be signed) */
+
+typedef unsigned char FMSTR_BCHR; /* type of a single character in comm.buffer */
+typedef unsigned char* FMSTR_BPTR; /* pointer within a communication buffer */
+
+typedef unsigned short FMSTR_SCISR; /* data type to store SCI status register */
+
+/******************************************************************************
+* communication buffer access functions (non-inline)
+******************************************************************************/
+
+void FMSTR_CopyMemory(FMSTR_ADDR nDestAddr, FMSTR_ADDR nSrcAddr, FMSTR_SIZE8 nSize);
+FMSTR_BPTR FMSTR_CopyToBuffer(FMSTR_BPTR pDestBuff, FMSTR_ADDR nSrcAddr, FMSTR_SIZE8 nSize);
+FMSTR_BPTR FMSTR_CopyFromBuffer(FMSTR_ADDR nDestAddr, FMSTR_BPTR pSrcBuff, FMSTR_SIZE8 nSize);
+void FMSTR_CopyFromBufferWithMask(FMSTR_ADDR nDestAddr, FMSTR_BPTR pSrcBuff, FMSTR_SIZE8 nSize);
+FMSTR_BPTR FMSTR_AddressFromBuffer(FMSTR_ADDR* pAddr, FMSTR_BPTR pSrc);
+FMSTR_BPTR FMSTR_AddressToBuffer(FMSTR_BPTR pDest, FMSTR_ADDR nAddr);
+
+/* FMSTR_SetExAddr is needed only if both EX and non-EX commands are used */
+#if FMSTR_USE_EX_CMDS && FMSTR_USE_NOEX_CMDS
+void FMSTR_SetExAddr(FMSTR_BOOL bNextAddrIsEx);
+#else
+/* otherwise, we know what addresses are used, (ignore FMSTR_SetExAddr) */
+#define FMSTR_SetExAddr(bNextAddrIsEx)
+#endif
+
+/******************************************************************************
+* communication buffer access functions (inlines/functions - depending on cfg)
+******************************************************************************/
+
+#if FMSTR_USE_INLINE_BUFFER_ACCESS
+
+__inline FMSTR_BPTR FMSTR_ValueFromBuffer16(FMSTR_U16* pDest, FMSTR_BPTR pSrc)
+{
+ return FMSTR_CopyFromBuffer((FMSTR_ADDR)(FMSTR_U8*)pDest, pSrc, 2);
+}
+
+__inline FMSTR_BPTR FMSTR_ValueFromBuffer32(FMSTR_U32* pDest, FMSTR_BPTR pSrc)
+{
+ return FMSTR_CopyFromBuffer((FMSTR_ADDR)(FMSTR_U8*)pDest, pSrc, 4);
+}
+
+FMSTR_BPTR FMSTR_ValueToBuffer16(FMSTR_BPTR pDest, FMSTR_U16 src)
+{
+ return FMSTR_CopyToBuffer(pDest, (FMSTR_ADDR)(FMSTR_U8*)&src, 2);
+}
+
+__inline FMSTR_BPTR FMSTR_ValueToBuffer32(FMSTR_BPTR pDest, FMSTR_U32 src)
+{
+ return FMSTR_CopyToBuffer(pDest, (FMSTR_ADDR)(FMSTR_U8*)&src, 4);
+}
+
+#else /* FMSTR_USE_INLINE_BUFFER_ACCESS */
+
+__inline FMSTR_BPTR FMSTR_ValueFromBuffer16(FMSTR_U16* pDest, FMSTR_BPTR pSrc)
+{
+ return FMSTR_CopyFromBuffer((FMSTR_ADDR)(FMSTR_U8*)pDest, pSrc, 2);
+}
+
+__inline FMSTR_BPTR FMSTR_ValueFromBuffer32(FMSTR_U32* pDest, FMSTR_BPTR pSrc)
+{
+ return FMSTR_CopyFromBuffer((FMSTR_ADDR)(FMSTR_U8*)pDest, pSrc, 4);
+}
+
+__inline FMSTR_BPTR FMSTR_ValueToBuffer16(FMSTR_BPTR pDest, FMSTR_U16 src)
+{
+ return FMSTR_CopyToBuffer(pDest, (FMSTR_ADDR)(FMSTR_U8*)&src, 2);
+}
+
+__inline FMSTR_BPTR FMSTR_ValueToBuffer32(FMSTR_BPTR pDest, FMSTR_U32 src)
+{
+ return FMSTR_CopyToBuffer(pDest, (FMSTR_ADDR)(FMSTR_U8*)&src, 4);
+}
+
+#endif /* FMSTR_USE_INLINE_BUFFER_ACCESS */
+
+/******************************************************************************
+* communication buffer access inlines
+******************************************************************************/
+
+__inline FMSTR_BPTR FMSTR_SkipInBuffer(FMSTR_BPTR pDest, FMSTR_SIZE8 nSize)
+{
+ return pDest + nSize;
+}
+
+__inline FMSTR_BPTR FMSTR_ValueFromBuffer8(FMSTR_U8* pDest, register FMSTR_BPTR pSrc)
+{
+ *pDest = *pSrc++;
+ return pSrc;
+}
+
+__inline FMSTR_BPTR FMSTR_ValueToBuffer8(FMSTR_BPTR pDest, FMSTR_U8 src)
+{
+ *pDest++ = src;
+ return pDest;
+}
+
+__inline FMSTR_BPTR FMSTR_ConstToBuffer8(FMSTR_BPTR pDest, FMSTR_U8 src)
+{
+ *pDest++ = src;
+ return pDest;
+}
+
+__inline FMSTR_BPTR FMSTR_ConstToBuffer16(FMSTR_BPTR pDest, FMSTR_U16 src)
+{
+ return FMSTR_ConstToBuffer8(FMSTR_ConstToBuffer8(pDest, (FMSTR_U8) src), (FMSTR_U8)(src>>8));
+}
+
+/****************************************************************************************
+* memory access helper macros (used in recorder trigger compare routines)
+*****************************************************************************************/
+
+#define FMSTR_GetS8(addr) ( *(FMSTR_S8*)(addr) )
+
+#define FMSTR_GetU8(addr) ( *(FMSTR_U8*)(addr) )
+
+#define FMSTR_GetS16(addr) ( *(FMSTR_S16*)(addr) )
+
+#define FMSTR_GetU16(addr) ( *(FMSTR_U16*)(addr) )
+
+#define FMSTR_GetS32(addr) ( *(FMSTR_S32*)(addr) )
+
+#define FMSTR_GetU32(addr) ( *(FMSTR_U32*)(addr) )
+
+/****************************************************************************************
+* Other helper macros
+*****************************************************************************************/
+
+/* This macro assigns C pointer to FMSTR_ADDR-typed variable */
+/* should be done in assembly not to trim far-space pointers in SDM */
+
+#define FMSTR_ARR2ADDR FMSTR_PTR2ADDR
+
+
+
+#define FMSTR_PTR2ADDR(tmpAddr, ptr) ( /*lint -e{923} */ tmpAddr = (FMSTR_ADDR) (FMSTR_U8*) ptr )
+
+/****************************************************************************************
+* Platform-specific configuration check
+*****************************************************************************************/
+
+/* sanity check, at least one of the modes should be enabled */
+#if (!FMSTR_USE_EX_CMDS) && (!FMSTR_USE_NOEX_CMDS)
+#error At least one of FMSTR_USE_EX_CMDS or FMSTR_USE_NOEX_CMDS should be set non-zero
+#endif
+
+/* JTAG / SCI selection */
+#if FMSTR_USE_JTAG
+ /* hardwired JTAG address on all HawkV2 devices */
+ #ifndef FMSTR_JTAG_BASE
+ #define FMSTR_JTAG_BASE 0xFFFF00
+ #endif
+
+#elif FMSTR_USE_SCI
+ /* user must select what SCI to use */
+ #ifndef FMSTR_SCI_BASE
+ #error You have to define FMSTR_SCI_BASE as a base address of SCI register space
+ #endif
+#endif
+
+#if FMSTR_USE_SCI && FMSTR_USE_JTAG
+#error You have to enable one of JTAG or SCI interface, not both
+#endif
+
+/****************************************************************************************
+* General peripheral space access macros
+*****************************************************************************************/
+
+/*
+#define FMSTR_SETBIT(base, offset, bit) (*(volatile FMSTR_U16*)(((FMSTR_U32)(base))+(offset)) |= bit)
+#define FMSTR_CLRBIT(base, offset, bit) (*(volatile FMSTR_U16*)(((FMSTR_U32)(base))+(offset)) &= (FMSTR_U16)~((FMSTR_U16)(bit)))
+#define FMSTR_SETREG(base, offset, value) (*(volatile FMSTR_U16*)(((FMSTR_U32)(base))+(offset)) = value)
+#define FMSTR_GETREG(base, offset) (*(volatile FMSTR_U16*)(((FMSTR_U32)(base))+(offset)))
+#define FMSTR_SETREG32(base, offset, value) (*(volatile FMSTR_U32*)(((FMSTR_U32)(base))+(offset)) = value)
+#define FMSTR_GETREG32(base, offset) (*(volatile FMSTR_U32*)(((FMSTR_U32)(base))+(offset)))
+*/
+/****************************************************************************************
+* SCI module constants
+*****************************************************************************************/
+
+/* SCI module registers */
+#define FMSTR_SCIBR_OFFSET 0U
+#define FMSTR_SCICR_OFFSET 1U
+#define FMSTR_SCISR_OFFSET 3U
+#define FMSTR_SCIDR_OFFSET 4U
+
+/* SCI Control Register bits */
+#define FMSTR_SCICR_LOOP 0x8000U
+#define FMSTR_SCICR_SWAI 0x4000U
+#define FMSTR_SCICR_RSRC 0x2000U
+#define FMSTR_SCICR_M 0x1000U
+#define FMSTR_SCICR_WAKE 0x0800U
+#define FMSTR_SCICR_POL 0x0400U
+#define FMSTR_SCICR_PE 0x0200U
+#define FMSTR_SCICR_PT 0x0100U
+#define FMSTR_SCICR_TEIE 0x0080U
+#define FMSTR_SCICR_TIIE 0x0040U
+#define FMSTR_SCICR_RFIE 0x0020U
+#define FMSTR_SCICR_REIE 0x0010U
+#define FMSTR_SCICR_TE 0x0008U
+#define FMSTR_SCICR_RE 0x0004U
+#define FMSTR_SCICR_RWU 0x0002U
+#define FMSTR_SCICR_SBK 0x0001U
+
+/* SCI Status registers bits */
+#define FMSTR_SCISR_TDRE 0x8000U
+#define FMSTR_SCISR_TIDLE 0x4000U
+#define FMSTR_SCISR_RDRF 0x2000U
+#define FMSTR_SCISR_RIDLE 0x1000U
+#define FMSTR_SCISR_OR 0x0800U
+#define FMSTR_SCISR_NF 0x0400U
+#define FMSTR_SCISR_FE 0x0200U
+#define FMSTR_SCISR_PF 0x0100U
+#define FMSTR_SCISR_RAF 0x0001U
+
+/*******************************************************************************************
+* SCI access macros
+*****************************************************************************************/
+
+/* transmitter enable/disable */
+/*lint -emacro(923,FMSTR_SCI_TE, FMSTR_SCI_TD) : casting long to pointer */
+//#define FMSTR_SCI_TE() FMSTR_SETBIT(FMSTR_SCI_BASE, FMSTR_SCICR_OFFSET, FMSTR_SCICR_TE)
+//#define FMSTR_SCI_TD() FMSTR_CLRBIT(FMSTR_SCI_BASE, FMSTR_SCICR_OFFSET, FMSTR_SCICR_TE)
+
+/* receiver enable/disable */
+/*lint -emacro(923,FMSTR_SCI_RE, FMSTR_SCI_RD) : casting long to pointer */
+//#define
+//#define
+
+/* Transmitter-empty interrupt enable/disable : casting long to pointer */
+/*lint -emacro(923,FMSTR_SCI_ETXI, FMSTR_SCI_DTXI) */
+//#define FMSTR_SCI_ETXI() FMSTR_SETBIT(FMSTR_SCI_BASE, FMSTR_SCICR_OFFSET, FMSTR_SCICR_TEIE)
+//#define FMSTR_SCI_DTXI() FMSTR_CLRBIT(FMSTR_SCI_BASE, FMSTR_SCICR_OFFSET, FMSTR_SCICR_TEIE)
+
+/* Receiver-full interrupt enable/disable : casting long to pointer */
+/*lint -emacro(923,FMSTR_SCI_ERXI, FMSTR_SCI_DRXI) */
+//#define FMSTR_SCI_ERXI() FMSTR_SETBIT(FMSTR_SCI_BASE, FMSTR_SCICR_OFFSET, FMSTR_SCICR_RFIE)
+//#define FMSTR_SCI_DRXI() FMSTR_CLRBIT(FMSTR_SCI_BASE, FMSTR_SCICR_OFFSET, FMSTR_SCICR_RFIE)
+
+/* Tranmsit character */
+/*lint -emacro(923,FMSTR_SCI_PUTCHAR) : casting long to pointer */
+//#define FMSTR_SCI_PUTCHAR(ch) FMSTR_SETREG(FMSTR_SCI_BASE, FMSTR_SCIDR_OFFSET, ch)
+
+/* Get received character */
+/*lint -emacro(923,FMSTR_SCI_GETCHAR) : casting long to pointer */
+//#define FMSTR_SCI_GETCHAR() FMSTR_GETREG(FMSTR_SCI_BASE, FMSTR_SCIDR_OFFSET)
+
+/* read status register */
+/*lint -emacro(923,FMSTR_SCI_GETSR) : casting long to pointer */
+//#define FMSTR_SCI_GETSR() FMSTR_GETREG(FMSTR_SCI_BASE, FMSTR_SCISR_OFFSET)
+
+/* read & clear status register (clears error status bits only) */
+/*lint -emacro(923,FMSTR_SCI_RDCLRSR) : casting long to pointer */
+//#define FMSTR_SCI_RDCLRSR() FMSTR_SETREG(FMSTR_SCI_BASE, FMSTR_SCISR_OFFSET, FMSTR_GETREG(FMSTR_SCI_BASE, FMSTR_SCISR_OFFSET))
+
+/*******************************************************************************************
+* JTAG access macros
+*******************************************************************************************/
+
+#define FMSTR_JTAG_OTXRXSR_OFFSET 0xfdU
+#define FMSTR_JTAG_ORX_OFFSET 0xfeU
+#define FMSTR_JTAG_OTX_OFFSET 0xfeU
+#define FMSTR_JTAG_ORX1_OFFSET 0xffU
+#define FMSTR_JTAG_OTX1_OFFSET 0xffU
+
+/* OTXRXSR register */
+#define FMSTR_JTAG_OTXRXSR_RDF 0x01U
+#define FMSTR_JTAG_OTXRXSR_TDF 0x02U
+#define FMSTR_JTAG_OTXRXSR_RIE 0x04U
+#define FMSTR_JTAG_OTXRXSR_TIE 0x08U
+
+#define _CHECK \
+ if(FMSTR_GETREG(FMSTR_JTAG_BASE, FMSTR_JTAG_OTXRXSR_OFFSET) & FMSTR_JTAG_OTXRXSR_RIE) \
+ ioctl(GPIO_A, GPIO_SET_PIN, BIT_1); \
+ else \
+ ioctl(GPIO_A, GPIO_CLEAR_PIN, BIT_1)
+
+/* enable/disable JTAG Rx-full interrupt */
+/*lint -emacro(923,FMSTR_JTAG_ERXI,FMSTR_JTAG_DRXI) : casting long to pointer */
+#define FMSTR_JTAG_ERXI() FMSTR_SETBIT(FMSTR_JTAG_BASE, FMSTR_JTAG_OTXRXSR_OFFSET, FMSTR_JTAG_OTXRXSR_RIE)
+#define FMSTR_JTAG_DRXI() FMSTR_CLRBIT(FMSTR_JTAG_BASE, FMSTR_JTAG_OTXRXSR_OFFSET, FMSTR_JTAG_OTXRXSR_RIE)
+
+/* enable/disable JTAG Tx-empty interrupt */
+/*lint -emacro(923,FMSTR_JTAG_ETXI,FMSTR_JTAG_DTXI) : casting long to pointer */
+#define FMSTR_JTAG_ETXI() FMSTR_SETBIT(FMSTR_JTAG_BASE, FMSTR_JTAG_OTXRXSR_OFFSET, FMSTR_JTAG_OTXRXSR_TIE)
+#define FMSTR_JTAG_DTXI() FMSTR_CLRBIT(FMSTR_JTAG_BASE, FMSTR_JTAG_OTXRXSR_OFFSET, FMSTR_JTAG_OTXRXSR_TIE)
+
+/* this macro verifies if the RIE bit is set (note that RIE is held low by HW until JTAG init) */
+/*lint -emacro(923,FMSTR_JTAG_ERXI_CHECK,FMSTR_JTAG_ETXI_CHECK) : casting long to pointer */
+#define FMSTR_JTAG_ERXI_CHECK() (FMSTR_GETREG(FMSTR_JTAG_BASE, FMSTR_JTAG_OTXRXSR_OFFSET) & FMSTR_JTAG_OTXRXSR_RIE)
+#define FMSTR_JTAG_ETXI_CHECK() (FMSTR_GETREG(FMSTR_JTAG_BASE, FMSTR_JTAG_OTXRXSR_OFFSET) & FMSTR_JTAG_OTXRXSR_TIE)
+
+/* get JTAG status register */
+/*lint -emacro(923,FMSTR_JTAG_GETSR) : casting long to pointer */
+#define FMSTR_JTAG_GETSR() FMSTR_GETREG(FMSTR_JTAG_BASE, FMSTR_JTAG_OTXRXSR_OFFSET)
+
+/* Tranmsit JTAG word */
+/*lint -emacro(923,FMSTR_JTAG_PUTDWORD) : casting long to pointer */
+#define FMSTR_JTAG_PUTDWORD(ch) FMSTR_SETREG32(FMSTR_JTAG_BASE, FMSTR_JTAG_OTX_OFFSET, ch)
+
+/* Get received word */
+/*lint -emacro(923,FMSTR_JTAG_GETDWORD) : casting long to pointer */
+#define FMSTR_JTAG_GETDWORD() FMSTR_GETREG32(FMSTR_JTAG_BASE, FMSTR_JTAG_ORX_OFFSET)
+
+/* Get upper 16bit of received word */
+/*lint -emacro(923,FMSTR_JTAG_GETWORD) : casting long to pointer */
+#define FMSTR_JTAG_GETWORD() FMSTR_GETREG(FMSTR_JTAG_BASE, FMSTR_JTAG_ORX1_OFFSET)
+
+#endif /* __FREEMASTER_56F8xxx_H */
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_appcmd.c b/Projects/epwm_test/Freemaster/PE_freemaster_appcmd.c
new file mode 100644
index 0000000..2261f77
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_appcmd.c
@@ -0,0 +1,453 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2007 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_appcmd.c
+*
+* @brief FreeMASTER Application Commands implementation
+*
+* @version 1.0.9.0
+*
+* @date Oct-19-2007
+*
+*******************************************************************************/
+
+#include "PE_freemaster.h"
+#include "PE_freemaster_private.h"
+#include "PE_freemaster_protocol.h"
+
+#if FMSTR_USE_APPCMD
+
+/***********************************
+* local variables
+***********************************/
+
+static FMSTR_APPCMD_CODE pcm_nAppCmd; /* app.cmd code (to application) */
+static FMSTR_APPCMD_DATA pcm_pAppCmdBuff[FMSTR_APPCMD_BUFF_SIZE]; /* app.cmd data buffer */
+static FMSTR_SIZE pcm_nAppCmdLen; /* app.cmd data length */
+
+static FMSTR_APPCMD_RESULT pcm_nAppCmdResult; /* app.cmd result code (from application) */
+static FMSTR_SIZE8 pcm_nAppCmdResultDataLen;
+
+#if FMSTR_MAX_APPCMD_CALLS > 0
+static FMSTR_APPCMD_CODE pcm_pAppCmdCallId[FMSTR_MAX_APPCMD_CALLS]; /* registerred callback commands */
+static FMSTR_PAPPCMDFUNC pcm_pAppCmdCallFunc[FMSTR_MAX_APPCMD_CALLS]; /* registerred callback handlers */
+#endif
+
+/***********************************
+* local functions
+***********************************/
+
+static FMSTR_INDEX FMSTR_FindAppCmdCallIndex(FMSTR_APPCMD_CODE nAppcmdCode);
+
+/**************************************************************************//*!
+*
+* @brief Initialize app.cmds interface
+*
+******************************************************************************/
+
+void FMSTR_InitAppCmds(void)
+{
+#if FMSTR_MAX_APPCMD_CALLS
+ FMSTR_INDEX i;
+
+ for(i=0; i (FMSTR_SIZE8) FMSTR_APPCMD_BUFF_SIZE)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVBUFF);
+ }
+
+ /* store command data into dedicated buffer */
+ pcm_nAppCmd = nCode;
+ pcm_nAppCmdLen = nArgsLen;
+
+ /* data copy */
+ if(nArgsLen)
+ {
+ FMSTR_ADDR appCmdBuffAddr;
+ FMSTR_ARR2ADDR(appCmdBuffAddr, pcm_pAppCmdBuff);
+
+ /*lint -e{534} ignoring return value */
+ FMSTR_CopyFromBuffer(appCmdBuffAddr, pMessageIO, (FMSTR_SIZE8) nArgsLen);
+ }
+
+ /* mark command as "running" (without any response data) */
+ pcm_nAppCmdResult = FMSTR_APPCMDRESULT_RUNNING;
+ pcm_nAppCmdResultDataLen = 0U;
+
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling GETAPPCMDSTS command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+* @note The callback-registerred commands are processed at the moment the PC
+* tries to get the result for the first time. At this moment, we are
+* sure the PC already got the command delivery packet acknowledged.
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_GetAppCmdStatus(FMSTR_BPTR pMessageIO)
+{
+#if FMSTR_MAX_APPCMD_CALLS
+ FMSTR_PAPPCMDFUNC pFunc = NULL;
+ FMSTR_INDEX nIndex;
+
+ /* time to execute the command's callback */
+ if((nIndex = FMSTR_FindAppCmdCallIndex(pcm_nAppCmd)) >= 0)
+ {
+ pFunc = pcm_pAppCmdCallFunc[nIndex];
+ }
+
+ /* valid callback function found? */
+ if(pFunc)
+ {
+ /* do execute callback, return value is app.cmd result code */
+ pcm_nAppCmdResult = pFunc(pcm_nAppCmd, pcm_pAppCmdBuff, pcm_nAppCmdLen);
+
+ /* nothing more to do with this command (i.e. command acknowledged) */
+ pcm_nAppCmd = FMSTR_APPCMDRESULT_NOCMD;
+ }
+#endif
+
+ pMessageIO = FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STS_OK);
+ return FMSTR_ValueToBuffer8(pMessageIO, (FMSTR_U8) pcm_nAppCmdResult);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling GETAPPCMDDATA command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_GetAppCmdRespData(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_U8 nDataLen;
+ FMSTR_U8 nDataOffset;
+
+ /* the previous command not yet processed */
+ if(pcm_nAppCmd != FMSTR_APPCMDRESULT_NOCMD)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_SERVBUSY);
+ }
+
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 1U);
+ pMessageIO = FMSTR_ValueFromBuffer8(&nDataLen, pMessageIO);
+ pMessageIO = FMSTR_ValueFromBuffer8(&nDataOffset, pMessageIO);
+
+ /* the response would not fit into comm buffer */
+ if(nDataLen > (FMSTR_U16)FMSTR_COMM_BUFFER_SIZE)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_RSPBUFFOVF);
+ }
+
+ /* the data would be fetched outside the app.cmd response data */
+ if((((FMSTR_U16)nDataOffset) + nDataLen) > (FMSTR_SIZE8)pcm_nAppCmdResultDataLen)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVSIZE);
+ }
+
+ pResponse = FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+
+ /* copy to buffer */
+ {
+ FMSTR_ADDR appCmdBuffAddr;
+ FMSTR_ARR2ADDR(appCmdBuffAddr, pcm_pAppCmdBuff);
+ pResponse = FMSTR_CopyToBuffer(pResponse, appCmdBuffAddr, (FMSTR_SIZE8)nDataLen);
+ }
+
+ return pResponse;
+}
+
+/**************************************************************************//*!
+*
+* @brief Find index of registerred app.cmd callback
+*
+* @param nAppcmdCode - App. command ID
+*
+* @return Index of function pointer in our local tables
+*
+******************************************************************************/
+
+static FMSTR_INDEX FMSTR_FindAppCmdCallIndex(FMSTR_APPCMD_CODE nAppcmdCode)
+{
+#if FMSTR_MAX_APPCMD_CALLS > 0
+ FMSTR_INDEX i;
+
+ for(i=0; i (FMSTR_SIZE8) FMSTR_APPCMD_BUFF_SIZE)
+ {
+ pcm_nAppCmdResultDataLen = (FMSTR_SIZE8) FMSTR_APPCMD_BUFF_SIZE;
+ }
+
+ if(pcm_nAppCmdResultDataLen > 0U)
+ {
+ FMSTR_ADDR appCmdBuffAddr;
+ FMSTR_ARR2ADDR(appCmdBuffAddr, pcm_pAppCmdBuff);
+ FMSTR_CopyMemory(appCmdBuffAddr, nResultDataAddr, pcm_nAppCmdResultDataLen);
+ }
+ }
+ else
+ {
+ /* no data being returned at all (same effect as pure FMSTR_AppCmdAck) */
+ pcm_nAppCmdResultDataLen = 0U;
+ }
+}
+
+/**************************************************************************//*!
+*
+* @brief API: Fetch the application command code if one is ready for processing
+*
+* @return A command code stored in the application cmd buffer.
+* The return value is FMSTR_APPCMDRESULT_NOCMD if there is no
+* new command since the last call to FMSTR_AppCmdAck
+*
+******************************************************************************/
+
+FMSTR_APPCMD_CODE FMSTR_GetAppCmd(void)
+{
+#if FMSTR_MAX_APPCMD_CALLS
+ /* the user can never see the callback-registerred commands */
+ if(FMSTR_FindAppCmdCallIndex(pcm_nAppCmd) >= 0)
+ {
+ return FMSTR_APPCMDRESULT_NOCMD;
+ }
+#endif
+
+ /* otherwise, return the appcomand pending */
+ return pcm_nAppCmd;
+}
+
+/**************************************************************************//*!
+*
+* @brief API: Get a pointer to application command data
+*
+* @param pDataLen - A pointer to variable which receives the data length
+*
+* @return Pointer to the "application command" data
+*
+******************************************************************************/
+
+FMSTR_APPCMD_PDATA FMSTR_GetAppCmdData(FMSTR_SIZE* pDataLen)
+{
+ /* no command, no data */
+ if(pcm_nAppCmd == FMSTR_APPCMDRESULT_NOCMD)
+ {
+ return NULL;
+ }
+
+#if FMSTR_MAX_APPCMD_CALLS
+ /* the user never sees the callback-registerred commands */
+ if(FMSTR_FindAppCmdCallIndex(pcm_nAppCmd) >= 0)
+ {
+ return NULL;
+ }
+#endif
+
+ /* caller want to know the data length */
+ if(pDataLen)
+ {
+ *pDataLen = pcm_nAppCmdLen;
+ }
+
+ /* data are saved in out buffer */
+ return pcm_nAppCmdLen ? pcm_pAppCmdBuff : (FMSTR_APPCMD_PDATA) NULL;
+}
+
+/**************************************************************************//*!
+*
+* @brief API: Register or unregister app.cmd callback handler
+*
+* @param nAppCmdCode - App.command ID
+* @param pCallbackFunc - Pointer to handler function (NULL to unregister)
+*
+* @return Non-zero if successfull, zero if maximum callbacks already set
+*
+******************************************************************************/
+
+FMSTR_BOOL FMSTR_RegisterAppCmdCall(FMSTR_APPCMD_CODE nAppCmdCode, FMSTR_PAPPCMDFUNC pCallbackFunc)
+{
+#if FMSTR_MAX_APPCMD_CALLS > 0
+
+ FMSTR_INDEX nIndex;
+
+ /* keep "void" ID as reserved */
+ if(nAppCmdCode == FMSTR_APPCMDRESULT_NOCMD)
+ {
+ return FMSTR_FALSE;
+ }
+
+ /* get index of app.cmd ID (if already set) */
+ nIndex = FMSTR_FindAppCmdCallIndex(nAppCmdCode);
+
+ /* when not found, get a free slot (only if registerring new callback) */
+ if(nIndex < 0 && pCallbackFunc != NULL)
+ {
+ nIndex = FMSTR_FindAppCmdCallIndex(FMSTR_APPCMDRESULT_NOCMD);
+ }
+
+ /* failed? */
+ if(nIndex < 0)
+ {
+ return FMSTR_FALSE;
+ }
+
+ /* register handler */
+ pcm_pAppCmdCallFunc[nIndex] = pCallbackFunc;
+ pcm_pAppCmdCallId[nIndex] = (FMSTR_APPCMD_CODE) (pCallbackFunc ?
+ nAppCmdCode : FMSTR_APPCMDRESULT_NOCMD);
+
+ return FMSTR_TRUE;
+
+#else
+ FMSTR_UNUSED(pCallbackFunc);
+ FMSTR_UNUSED(nAppCmdCode);
+
+ /* app.cmd callback not implemented */
+ return FMSTR_FALSE;
+
+#endif
+}
+
+#else /* FMSTR_USE_APPCMD */
+
+/* void Application Command API functions */
+
+void FMSTR_AppCmdAck(FMSTR_APPCMD_RESULT nResultCode)
+{
+// FMSTR_UNUSED(nResultCode);
+}
+
+void FMSTR_AppCmdSetResponseData(FMSTR_ADDR pResultData, FMSTR_SIZE nResultDataLen)
+{
+// FMSTR_UNUSED(pResultData);
+// FMSTR_UNUSED(nResultDataLen);
+}
+
+FMSTR_APPCMD_CODE FMSTR_GetAppCmd(void)
+{
+ return FMSTR_APPCMDRESULT_NOCMD;
+}
+
+FMSTR_APPCMD_PDATA FMSTR_GetAppCmdData(FMSTR_SIZE* pDataLen)
+{
+// FMSTR_UNUSED(pDataLen);
+ return NULL;
+}
+
+FMSTR_BOOL FMSTR_RegisterAppCmdCall(FMSTR_APPCMD_CODE nAppCmdCode, FMSTR_PAPPCMDFUNC pCallbackFunc)
+{
+ // FMSTR_UNUSED(nAppCmdCode);
+ // FMSTR_UNUSED(pCallbackFunc);
+ return FMSTR_FALSE;
+}
+
+/*lint -efile(766, PE_freemaster_protocol.h) include file is not used in this case */
+
+#endif /* FMSTR_USE_APPCMD */
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_cfg.h b/Projects/epwm_test/Freemaster/PE_freemaster_cfg.h
new file mode 100644
index 0000000..ece205b
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_cfg.h
@@ -0,0 +1,78 @@
+/** ###################################################################
+** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
+** Filename : freemaster_cfg.H
+** Project : Test
+** Processor : 56F8323
+** Version : Component 01.006, Driver 01.03, CPU db: 2.87.081
+** Compiler : Metrowerks DSP C Compiler
+** Date/Time : 17.10.2012, 17:58
+** Abstract :
+** FreeMASTER Serial Communication Driver configuration file
+**
+** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http : www.freescale.com
+** mail : support@freescale.com
+** ###################################################################*/
+
+#ifndef __FREEMASTER_CFG_H
+#define __FREEMASTER_CFG_H
+
+/* Select interrupt or poll-driven serial communication */
+#define FMSTR_LONG_INTR 0
+#define FMSTR_SHORT_INTR 0
+#define FMSTR_POLL_DRIVEN 1 /* No interrupt needed, polling only */
+
+/* SCI communication */
+#define FMSTR_USE_SCI 1 /* Use SCI interface */
+#define FMSTR_SCI_BASE 62080 /* SCI Base address is same as SCI Baud Rate register address */
+#define FMSTR_USE_JTAG 0 /* Disable JTAG interface */
+
+/* FreeMaster communication buffer */
+#define FMSTR_COMM_BUFFER_SIZE 64 /* Input/output communication buffer size */
+#if FMSTR_SHORT_INTR
+#define FMSTR_COMM_RQUEUE_SIZE 32 /* Receive FIFO queue size (use with FMSTR_SHORT_INTR only) */
+#endif
+
+/* Application command support */
+#define FMSTR_USE_APPCMD 0 /* Application commands support disabled */
+
+/* Oscilloscope support */
+#define FMSTR_USE_SCOPE 1 /* Scope enabled */
+#define FMSTR_MAX_SCOPE_VARS 8 /* Max. number of scope variables (2..8) */
+
+/* Recorder support */
+#define FMSTR_USE_RECORDER 1 /* Recorder support enabled */
+#define FMSTR_REC_BUFF_SIZE 2048 /* Recorder buffer size */
+#define FMSTR_USE_FASTREC 0 /* Fast recorder support disabled */
+#define FMSTR_REC_OWNBUFF 0 /* User-allocated rec. buffer is not used */
+#define FMSTR_REC_FARBUFF 0 /* Buffer is not putted in "fardata" section */
+#define FMSTR_MAX_REC_VARS 8 /* Max. number of recorder variables (2..8) */
+#define FMSTR_REC_TIMEBASE 32868 /* Recorder timebase */
+#define FMSTR_USE_BRIEFINFO 0 /* Full board information structure is required becouse recorder is used */
+
+/* Target-side addressing support */
+#define FMSTR_USE_TSA 0 /* Disable TSA functionality */
+
+#define FMSTR_USE_READMEM 1 /* Enable read memory commands */
+#define FMSTR_USE_WRITEMEM 1 /* Enable write memory commands */
+#define FMSTR_USE_WRITEMEMMASK 1 /* Enable masked write memory commands */
+
+#define FMSTR_USE_READVAR 0 /* Disable read variable fast commands */
+#define FMSTR_USE_WRITEVAR 0 /* Disable write variable fast commands */
+#define FMSTR_USE_WRITEVARMASK 0 /* Disable write variable bits fast commands */
+
+/* SFIO support */
+#define FMSTR_USE_SFIO 0 /* SFIO support disabled */
+
+#endif /* __FREEMASTER_CFG_H */
+
+/*
+** ###################################################################
+**
+** This file was created by Processor Expert 3.00 [04.35]
+** for the Freescale 56800 series of microcontrollers.
+**
+** ###################################################################
+*/
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_fastrec.c b/Projects/epwm_test/Freemaster/PE_freemaster_fastrec.c
new file mode 100644
index 0000000..aa8f7b9
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_fastrec.c
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_fastrec.c
+*
+* @brief FreeMASTER 56F800E-hardware dependent fast-recorder routines
+*
+* @version 1.0.2.0
+*
+* @date Sep-6-2006
+*
+*******************************************************************************/
+
+#include "PE_freemaster.h"
+#include "PE_freemaster_private.h"
+
+#if FMSTR_USE_RECORDER && FMSTR_USE_FASTREC
+
+#include "PE_freemaster_fastrec.h"
+
+/* global variables */
+FMSTR_ADDR pcm_dwFastRecWritePtr;
+FMSTR_ADDR pcm_dwFastRecStartBuffPtr;
+FMSTR_ADDR pcm_dwFastRecEndBuffPtr;
+
+/* statically allocated recorder buffer (FMSTR_REC_OWNBUFF is FALSE) */
+#if FMSTR_REC_FARBUFF
+#pragma section fardata begin
+#endif /* FMSTR_REC_FARBUFF */
+static FMSTR_U16 pcm_pFastRecBuffer[FMSTR_REC_BUFF_SIZE/2];
+/* end of far memory section */
+#if FMSTR_REC_FARBUFF
+#pragma section fardata end
+#endif /* FMSTR_REC_FARBUFF */
+
+/**************************************************************************//*!
+*
+* @brief Fast Recorder Initialization
+*
+******************************************************************************/
+
+void FMSTR_InitFastRec(void)
+{
+ /* get array pointer as 32bit value */
+ FMSTR_ARR2ADDR(pcm_dwFastRecStartBuffPtr, pcm_pFastRecBuffer);
+
+ /* base driver requires byte-addressing */
+ FMSTR_SetUpRecBuff(pcm_dwFastRecStartBuffPtr * 2, FMSTR_REC_BUFF_SIZE);
+}
+
+/**************************************************************************//*!
+*
+* @brief Check if recorder configuration can be used in fast-recorder mode
+*
+******************************************************************************/
+
+FMSTR_BOOL FMSTR_SetUpFastRec(void)
+{
+ FMSTR_INDEX i;
+
+ /* check all recorder variables */
+ for(i=0; ipcm_pRecVarAddr, padrs; \
+ move.w pcm_nRecVarCount, tmp; \
+ \
+ do tmp, copy_loop_end; \
+ move.l X:(padrs)+, ptemp; \
+ move.w X:(ptemp), tmp; \
+ move.w tmp, X:(pdest)+; \
+ \
+ copy_loop_end: \
+ } \
+ }
+
+#define FMSTR_FASTREC_VAR16(var16) \
+ asm \
+ { \
+ move.w var16, tmp; \
+ move.w tmp, X:(pdest)+; \
+ }
+
+#define FMSTR_FASTREC_END() \
+ asm \
+ { \
+ /* compare pdest with a wrap location */ \
+ move.l pcm_dwFastRecEndBuffPtr, ptemp; \
+ cmpa pdest, ptemp; \
+ bgt no_wrap; \
+ \
+ /* do wrap, reset write pointer to buffer start */ \
+ move.l pcm_dwFastRecStartBuffPtr, pdest; \
+ \
+ /* remember virgin cycle is over (trigger now enabled) */ \
+ bfclr FMSTR_REC_FLAG_bInvirginCycle, flags; \
+ \
+ no_wrap: \
+ /* save write pointer back to memory */ \
+ move.l pdest, pcm_dwFastRecWritePtr; \
+ \
+ /* save flags back to memory */ \
+ move.w flags, pcm_wRecFlags.all; \
+ \
+ skip_all: \
+ } \
+}
+
+
+inline FMSTR_FastRecorder(register FMSTR_BOOL bTriggerNow)
+{
+ FMSTR_FASTREC_BEGIN(1)
+ FMSTR_FASTREC_STDVARS()
+ FMSTR_FASTREC_TRIGGER_FULL(bTriggerNow)
+ FMSTR_FASTREC_END()
+ }
+
+/* normal recorder call emulated using fast recorder routine */
+
+inline void FMSTR_Recorder(void)
+{
+ FMSTR_FastRecorder(0);
+}
+
+#else /* FMSTR_USE_FASTREC */
+
+/* fast recorder is de-activated, emulate using normal recorder */
+
+inline void FMSTR_FastRecorder(FMSTR_BOOL bTriggerNow)
+{
+ if(bTriggerNow)
+ FMSTR_TriggerRec();
+
+ FMSTR_Recorder();
+}
+
+#endif /* FMSTR_USE_FASTREC */
+
+#else /* FMSTR_USE_RECORDER */
+
+/* recorder is not implemented, use empty fast-recorder call */
+
+inline void FMSTR_FastRecorder(FMSTR_BOOL bTriggerNow)
+{
+}
+
+#endif /* FMSTR_USE_RECORDER */
+#endif /* __FREEMASTER_FASTREC_H */
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_private.h b/Projects/epwm_test/Freemaster/PE_freemaster_private.h
new file mode 100644
index 0000000..a620504
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_private.h
@@ -0,0 +1,530 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2007 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_private.h
+*
+* @brief FreeMASTER driver private declarations, used internally by the driver
+*
+* @version 1.0.21.0
+*
+* @date Oct-22-2007
+*
+*******************************************************************************/
+
+#ifndef __FREEMASTER_PRIVATE_H
+#define __FREEMASTER_PRIVATE_H
+
+#ifndef __FREEMASTER_H
+#error Please include the PE_freemaster.h master header file before the PE_freemaster_private.h
+#endif
+
+#include "PE_freemaster_cfg.h"
+
+/******************************************************************************
+* Platform-dependent types, macros and functions
+******************************************************************************/
+
+#undef FMSTR_PLATFORM
+
+/* platform macro FMSTR_PLATFORM_xxxxxxx should be defined */
+/* as "non-zero" in the "PE_freemaster.h" file */
+
+#if defined(FMSTR_PLATFORM_56F8xx)
+ #if FMSTR_PLATFORM_56F8xx
+ #include "PE_freemaster_56F8xx.h"
+ #define FMSTR_PLATFORM 56F8xx
+ #else
+ #undef FMSTR_PLATFORM_56F8xx
+ #endif
+#endif
+
+#if defined(FMSTR_PLATFORM_56F8xxx)
+ #if FMSTR_PLATFORM_56F8xxx
+ #include "PE_freemaster_56F8xxx.h"
+ #define FMSTR_PLATFORM 56F8xxx
+ #else
+ #undef FMSTR_PLATFORM_56F8xxx
+ #endif
+#endif
+
+#if defined(FMSTR_PLATFORM_HC12)
+ #if FMSTR_PLATFORM_HC12
+ #include "PE_freemaster_HC12.h"
+ #define FMSTR_PLATFORM HC12
+ #else
+ #undef FMSTR_PLATFORM_HC12
+ #endif
+#endif
+
+#if defined(FMSTR_PLATFORM_HC08)
+ #if FMSTR_PLATFORM_HC08
+ #include "PE_freemaster_HC08.h"
+ #define FMSTR_PLATFORM HC08
+ #else
+ #undef FMSTR_PLATFORM_HC08
+ #endif
+#endif
+
+#if defined(FMSTR_PLATFORM_MPC55xx)
+ #if FMSTR_PLATFORM_MPC55xx
+ #include "PE_freemaster_MPC55xx.h"
+ #define FMSTR_PLATFORM MPC55xx
+ #else
+ #undef FMSTR_PLATFORM_MPC55xx
+ #endif
+#endif
+
+#if defined(FMSTR_PLATFORM_MPC5xx)
+ #if FMSTR_PLATFORM_MPC5xx
+ #include "PE_freemaster_MPC5xx.h"
+ #define FMSTR_PLATFORM MPC5xx
+ #else
+ #undef FMSTR_PLATFORM_MPC5xx
+ #endif
+#endif
+
+#if defined(FMSTR_PLATFORM_MCF51xx)
+ #if FMSTR_PLATFORM_MCF51xx
+ #include "PE_freemaster_MCF51xx.h"
+ #define FMSTR_PLATFORM MCF51xx
+ #else
+ #undef FMSTR_PLATFORM_MCF51xx
+ #endif
+#endif
+
+#if defined(FMSTR_PLATFORM_MCF52xx)
+ #if FMSTR_PLATFORM_MCF52xx
+ #include "PE_freemaster_MCF52xx.h"
+ #define FMSTR_PLATFORM MCF52xx
+ #else
+ #undef FMSTR_PLATFORM_MCF52xx
+ #endif
+#endif
+
+#ifndef FMSTR_PLATFORM
+#error Unknown FreeMASTER driver platform
+#endif
+
+/******************************************************************************
+* NULL needed
+******************************************************************************/
+
+#ifndef NULL
+#define NULL ((void *) 0)
+#endif
+
+/******************************************************************************
+* Boolean values
+******************************************************************************/
+
+#ifndef FMSTR_TRUE
+#define FMSTR_TRUE (1U)
+#endif
+
+#ifndef FMSTR_FALSE
+#define FMSTR_FALSE (0U)
+#endif
+
+/******************************************************************************
+* Global non-API functions (used internally in FreeMASTER driver)
+******************************************************************************/
+
+void FMSTR_InitSerial(void);
+void FMSTR_ProtocolDecoder(FMSTR_BPTR pMessageIO);
+void FMSTR_SendResponse(FMSTR_BPTR pMessageIO, FMSTR_SIZE8 nLength);
+void FMSTR_ProcessSCI(void);
+void FMSTR_ProcessJTAG(void);
+
+FMSTR_BPTR FMSTR_GetBoardInfo(FMSTR_BPTR pMessageIO);
+
+FMSTR_BPTR FMSTR_ReadMem(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_ReadVar(FMSTR_BPTR pMessageIO, FMSTR_SIZE8 nSize);
+FMSTR_BPTR FMSTR_WriteMem(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_WriteVar(FMSTR_BPTR pMessageIO, FMSTR_SIZE8 nSize);
+FMSTR_BPTR FMSTR_WriteVarMask(FMSTR_BPTR pMessageIO, FMSTR_SIZE8 nSize);
+FMSTR_BPTR FMSTR_WriteMemMask(FMSTR_BPTR pMessageIO);
+
+void FMSTR_InitAppCmds(void);
+FMSTR_BPTR FMSTR_StoreAppCmd(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_GetAppCmdStatus(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_GetAppCmdRespData(FMSTR_BPTR pMessageIO);
+
+void FMSTR_InitScope(void);
+FMSTR_BPTR FMSTR_SetUpScope(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_ReadScope(FMSTR_BPTR pMessageIO);
+
+void FMSTR_InitRec(void);
+FMSTR_BPTR FMSTR_SetUpRec(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_StartRec(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_StopRec(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_GetRecStatus(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_GetRecBuff(FMSTR_BPTR pMessageIO);
+FMSTR_BOOL FMSTR_IsInRecBuffer(FMSTR_ADDR nAddr, FMSTR_SIZE8 nSize);
+FMSTR_SIZE FMSTR_GetRecBuffSize(void);
+void FMSTR_AbortRec(void);
+
+void FMSTR_InitTsa(void);
+FMSTR_BPTR FMSTR_GetTsaInfo(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_GetStringLen(FMSTR_BPTR pMessageIO);
+FMSTR_BOOL FMSTR_CheckTsaSpace(FMSTR_ADDR nAddr, FMSTR_SIZE8 nSize, FMSTR_BOOL bWriteAccess);
+FMSTR_U16 FMSTR_StrLen(FMSTR_ADDR nAddr);
+
+void FMSTR_InitSfio(void);
+FMSTR_BPTR FMSTR_SfioFrame(FMSTR_BPTR pMessageIO);
+FMSTR_BPTR FMSTR_SfioGetResp(FMSTR_BPTR pMessageIO);
+
+void FMSTR_InitPipes(void);
+FMSTR_BPTR FMSTR_PipeFrame(FMSTR_BPTR pMessageIO);
+
+/****************************************************************************************
+* Potentialy unused variable declaration
+*****************************************************************************************/
+
+#ifdef _lint
+#define FMSTR_UNUSED(sym) /*lint -esym(715,sym) -esym(818,sym) -esym(529,sym) -e{960} */
+#else
+#define FMSTR_UNUSED(sym) ((sym),0)
+#endif
+
+/******************************************************************************
+* Configuration check
+******************************************************************************/
+
+/* polling mode as default when nothing selected */
+#if !defined(FMSTR_POLL_DRIVEN) && !defined(FMSTR_LONG_INTR) && !defined(FMSTR_SHORT_INTR)
+ #define FMSTR_LONG_INTR 0
+ #define FMSTR_SHORT_INTR 0
+ #define FMSTR_POLL_DRIVEN 1
+#endif
+
+/* otherwise, "undefined" means false for all three options */
+#ifndef FMSTR_POLL_DRIVEN
+#define FMSTR_POLL_DRIVEN 0
+#endif
+#ifndef FMSTR_LONG_INTR
+#define FMSTR_LONG_INTR 0
+#endif
+#ifndef FMSTR_SHORT_INTR
+#define FMSTR_SHORT_INTR 0
+#endif
+
+#if (FMSTR_LONG_INTR && (FMSTR_SHORT_INTR || FMSTR_POLL_DRIVEN)) || \
+ (FMSTR_SHORT_INTR && (FMSTR_LONG_INTR || FMSTR_POLL_DRIVEN)) || \
+ (FMSTR_POLL_DRIVEN && (FMSTR_LONG_INTR || FMSTR_SHORT_INTR)) || \
+ !(FMSTR_POLL_DRIVEN || FMSTR_LONG_INTR || FMSTR_SHORT_INTR)
+ /* mismatch in interrupt modes, only one can be selected */
+ #error You have to enable exctly one of FMSTR_LONG_INTR or FMSTR_SHORT_INTR or FMSTR_POLL_DRIVEN
+#endif
+
+#if FMSTR_SHORT_INTR
+ /* default short-interrupt FIFO size */
+ #ifndef FMSTR_COMM_RQUEUE_SIZE
+ #define FMSTR_COMM_RQUEUE_SIZE 32
+ #endif
+
+ #if !FMSTR_COMM_RQUEUE_SIZE
+ #undef FMSTR_COMM_RQUEUE_SIZE
+ #define FMSTR_COMM_RQUEUE_SIZE 32
+ #endif
+
+ #if FMSTR_COMM_RQUEUE_SIZE < 1
+ #error Error in FMSTR_COMM_RQUEUE_SIZE value.
+ #endif
+#endif
+
+/* disable both JTAG and SCI by default */
+/* one of these is typically already enabled in PE_freemaster_cfg.h */
+#ifndef FMSTR_USE_JTAG
+#define FMSTR_USE_JTAG 0
+#endif
+#ifndef FMSTR_USE_SCI
+ #if defined(FMSTR_SCI_BASE) && !FMSTR_USE_JTAG
+ #define FMSTR_USE_SCI 1
+ #else
+ #define FMSTR_USE_SCI 0
+ #endif
+#endif
+
+/* SCI does not have a transmission double buffer (kind of queue) */
+/* (if not specified differently in platform-dependent header file) */
+#if FMSTR_USE_SCI
+#ifndef FMSTR_SCI_HAS_TXQUEUE
+#define FMSTR_SCI_HAS_TXQUEUE 0
+#endif
+#endif
+
+/* read memory commands are ENABLED by default */
+#ifndef FMSTR_USE_READMEM
+#define FMSTR_USE_READMEM 1
+#endif
+#ifndef FMSTR_USE_WRITEMEM
+#define FMSTR_USE_WRITEMEM 1
+#endif
+#ifndef FMSTR_USE_WRITEMEMMASK
+#define FMSTR_USE_WRITEMEMMASK 1
+#endif
+
+/* read variable commands are DISABLED by default */
+#ifndef FMSTR_USE_READVAR
+#define FMSTR_USE_READVAR 0
+#endif
+#ifndef FMSTR_USE_WRITEVAR
+#define FMSTR_USE_WRITEVAR 0
+#endif
+#ifndef FMSTR_USE_WRITEVARMASK
+#define FMSTR_USE_WRITEVARMASK 0
+#endif
+
+/* default scope settings */
+#ifndef FMSTR_USE_SCOPE
+#define FMSTR_USE_SCOPE 0
+#endif
+
+#ifndef FMSTR_MAX_SCOPE_VARS
+#define FMSTR_MAX_SCOPE_VARS 8
+#endif
+
+/* check scope settings */
+#if FMSTR_USE_SCOPE
+ #if FMSTR_MAX_SCOPE_VARS > 8 || FMSTR_MAX_SCOPE_VARS < 2
+ #error Error in FMSTR_MAX_SCOPE_VARS value. Use a value in range 2..8
+ #endif
+#endif
+
+/* default recorder settings */
+#ifndef FMSTR_USE_RECORDER
+#define FMSTR_USE_RECORDER 0
+#endif
+
+#ifndef FMSTR_MAX_REC_VARS
+#define FMSTR_MAX_REC_VARS 8
+#endif
+
+#ifndef FMSTR_REC_FARBUFF
+#define FMSTR_REC_FARBUFF 0
+#endif
+
+#ifndef FMSTR_REC_OWNBUFF
+#define FMSTR_REC_OWNBUFF 0
+#endif
+
+#ifndef FMSTR_USE_FASTREC
+#define FMSTR_USE_FASTREC 0
+#endif
+
+/* check recorder settings */
+#if FMSTR_USE_RECORDER || FMSTR_USE_FASTREC
+ #if FMSTR_MAX_REC_VARS > 8 || FMSTR_MAX_REC_VARS < 2
+ #error Error in FMSTR_MAX_REC_VARS value. Use a value in range 2..8
+ #endif
+
+ /* 0 means recorder time base is "unknown" */
+ #ifndef FMSTR_REC_TIMEBASE
+ #define FMSTR_REC_TIMEBASE 0
+ #endif
+
+ /* default recorder buffer size is 256 */
+ #ifndef FMSTR_REC_BUFF_SIZE
+ #define FMSTR_REC_BUFF_SIZE 256
+ #endif
+
+ #if !FMSTR_USE_READMEM
+ #error Recorder needs the FMSTR_USE_READMEM feature
+ #endif
+#endif
+
+/* fast recorder requires its own allocation of recorder buffer */
+#if FMSTR_USE_FASTREC
+ #if FMSTR_REC_OWNBUFF
+ #error Fast recorder requires its own buffer allocation
+ #endif
+#endif
+
+/* default app.cmds settings */
+#ifndef FMSTR_USE_APPCMD
+#define FMSTR_USE_APPCMD 0
+#endif
+
+#ifndef FMSTR_APPCMD_BUFF_SIZE
+#define FMSTR_APPCMD_BUFF_SIZE 16
+#endif
+
+#ifndef FMSTR_MAX_APPCMD_CALLS
+#define FMSTR_MAX_APPCMD_CALLS 0
+#endif
+
+/* TSA configuration check */
+#ifndef FMSTR_USE_TSA
+#define FMSTR_USE_TSA 0
+#endif
+
+#ifndef FMSTR_USE_TSA_SAFETY
+#define FMSTR_USE_TSA_SAFETY 0
+#endif
+
+#if FMSTR_USE_TSA
+ #if !FMSTR_USE_READMEM
+ #error TSA needs the FMSTR_USE_READMEM feature
+ #endif
+#endif
+
+/* SFIO not used by default */
+#ifndef FMSTR_USE_SFIO
+#define FMSTR_USE_SFIO 0
+#endif
+
+/* check SFIO settings */
+#if FMSTR_USE_SFIO
+
+ /* The SFIO configuration files (sfio.h and optionally also the sfio_cfg.h) exist
+ in project to define SFIO parameters. */
+ #include "sfio.h"
+
+ #ifndef SFIO_MAX_INPUT_DATA_LENGTH
+ #error SFIO_MAX_INPUT_DATA_LENGTH was not defined in sfio_cfg.h
+ #endif
+ #ifndef SFIO_MAX_OUTPUT_DATA_LENGTH
+ #error SFIO_MAX_OUTPUT_DATA_LENGTH was not defined in sfio_cfg.h
+ #endif
+
+#endif
+
+/* use transport "pipe" functionality */
+#ifndef FMSTR_USE_PIPES
+#define FMSTR_USE_PIPES 0
+#endif
+
+#if FMSTR_USE_PIPES
+
+ #warning FreeMASTER Pipes feature is still in a prototype/experimental version.
+
+ #ifndef FMSTR_MAX_PIPES_COUNT
+ #define FMSTR_MAX_PIPES_COUNT 1
+ #endif
+
+ /* at least one */
+ #if FMSTR_MAX_PIPES_COUNT < 1
+ #warning No sense to allocate zero-count pipes. Disabling pipes.
+ #undef FMSTR_USE_PIPES
+ #define FMSTR_USE_PIPES 0
+ #endif
+
+#endif
+
+/* what kind of board information structure will be sent? */
+#ifndef FMSTR_USE_BRIEFINFO
+ #if FMSTR_USE_RECORDER
+ /* recorder requires full info */
+ #define FMSTR_USE_BRIEFINFO 0
+ #else
+ /* otherwise no brief info is enough */
+ #define FMSTR_USE_BRIEFINFO 1
+ #endif
+#endif
+
+/* check what kind of board info is sent */
+#if FMSTR_USE_BRIEFINFO
+ #if FMSTR_USE_RECORDER
+ #warning The full information structure must be used when recorder is to be used
+ #undef FMSTR_USE_BRIEFINFO
+ #define FMSTR_USE_BRIEFINFO 1
+ #endif
+#endif
+
+/* automatic buffer size by default */
+#ifndef FMSTR_COMM_BUFFER_SIZE
+#define FMSTR_COMM_BUFFER_SIZE 0
+#endif
+
+/* check minimal buffer size required for all enabled features */
+#if FMSTR_COMM_BUFFER_SIZE
+
+ /* basic commands (getinfobrief, write/read memory etc.) */
+ #if FMSTR_USE_BRIEFINFO && FMSTR_COMM_BUFFER_SIZE < 11
+ #error FMSTR_COMM_BUFFER_SIZE set too small for basic FreeMASTER commands (11 bytes)
+ #endif
+
+ /* full info required */
+ #if !(FMSTR_USE_BRIEFINFO) && FMSTR_COMM_BUFFER_SIZE < 35
+ #error FMSTR_COMM_BUFFER_SIZE set too small for GETINFO command (size 35)
+ #endif
+
+ /* application commands */
+ #if FMSTR_USE_APPCMD && FMSTR_COMM_BUFFER_SIZE < ((FMSTR_APPCMD_BUFF_SIZE)+1)
+ #error FMSTR_COMM_BUFFER_SIZE set too small for SENDAPPCMD command (size FMSTR_APPCMD_BUFF_SIZE+1)
+ #endif
+
+ /* configuring scope (EX) */
+ #if FMSTR_USE_SCOPE && FMSTR_COMM_BUFFER_SIZE < ((FMSTR_MAX_SCOPE_VARS)*5+1)
+ #error FMSTR_COMM_BUFFER_SIZE set too small for SETUPSCOPEEX command (size FMSTR_MAX_SCOPE_VARS*5+1)
+ #endif
+
+ /* configuring recorder (EX) */
+ #if FMSTR_USE_RECORDER && FMSTR_COMM_BUFFER_SIZE < ((FMSTR_MAX_REC_VARS)*5+18)
+ #error FMSTR_COMM_BUFFER_SIZE set too small for SETUPRECEX command (size FMSTR_MAX_REC_VARS*5+18)
+ #endif
+
+ /* SFIO encapsulation */
+ #if FMSTR_USE_SFIO
+ #if (FMSTR_COMM_BUFFER_SIZE < ((SFIO_MAX_INPUT_DATA_LENGTH)+1)) || \
+ (FMSTR_COMM_BUFFER_SIZE < ((SFIO_MAX_OUTPUT_DATA_LENGTH)+1))
+ #error FMSTR_COMM_BUFFER_SIZE set too small for SFIO encapsulation (see SFIO_MAX_xxx_DATA_LENGTH)
+ #endif
+ #endif
+
+/* automatic: determine required buffer size based on features enabled */
+#else
+ /* smallest for basic commands (getinfobrief, write/read memory etc.) */
+ #undef FMSTR_COMM_BUFFER_SIZE
+ #define FMSTR_COMM_BUFFER_SIZE 11
+
+ /* full info required */
+ #if !(FMSTR_USE_BRIEFINFO) && FMSTR_COMM_BUFFER_SIZE < 35
+ #undef FMSTR_COMM_BUFFER_SIZE
+ #define FMSTR_COMM_BUFFER_SIZE 35
+ #endif
+
+ /* using application commands (must accomodate maximal app.cmd data length) */
+ #if FMSTR_USE_APPCMD && FMSTR_COMM_BUFFER_SIZE < ((FMSTR_APPCMD_BUFF_SIZE)+1)
+ #undef FMSTR_COMM_BUFFER_SIZE
+ #define FMSTR_COMM_BUFFER_SIZE ((FMSTR_APPCMD_BUFF_SIZE)+1)
+ #endif
+
+ /* configuring scope (EX) */
+ #if FMSTR_USE_SCOPE && FMSTR_COMM_BUFFER_SIZE < ((FMSTR_MAX_SCOPE_VARS)*5+1)
+ #undef FMSTR_COMM_BUFFER_SIZE
+ #define FMSTR_COMM_BUFFER_SIZE ((FMSTR_MAX_SCOPE_VARS)*5+1)
+ #endif
+
+ /* configuring recorder (EX) */
+ #if FMSTR_USE_RECORDER && FMSTR_COMM_BUFFER_SIZE < ((FMSTR_MAX_REC_VARS)*5+18)
+ #undef FMSTR_COMM_BUFFER_SIZE
+ #define FMSTR_COMM_BUFFER_SIZE ((FMSTR_MAX_REC_VARS)*5+18)
+ #endif
+
+ /* SFIO encapsulation (in buffer) */
+ #if FMSTR_USE_SFIO
+ #if FMSTR_COMM_BUFFER_SIZE < ((SFIO_MAX_INPUT_DATA_LENGTH)+1)
+ #undef FMSTR_COMM_BUFFER_SIZE
+ #define FMSTR_COMM_BUFFER_SIZE ((SFIO_MAX_INPUT_DATA_LENGTH)+1)
+ #endif
+ #endif
+
+ /* SFIO encapsulation (out buffer) */
+ #if FMSTR_USE_SFIO
+ #if FMSTR_COMM_BUFFER_SIZE < ((SFIO_MAX_OUTPUT_DATA_LENGTH)+1)
+ #undef FMSTR_COMM_BUFFER_SIZE
+ #define FMSTR_COMM_BUFFER_SIZE ((SFIO_MAX_OUTPUT_DATA_LENGTH)+1)
+ #endif
+ #endif
+
+#endif
+
+#endif /* __FREEMASTER_PRIVATE_H */
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_protocol.c b/Projects/epwm_test/Freemaster/PE_freemaster_protocol.c
new file mode 100644
index 0000000..3694bf1
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_protocol.c
@@ -0,0 +1,658 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_protocol.c
+*
+* @brief FreeMASTER protocol handler
+*
+* @version 1.0.11.0
+*
+* @date Apr-11-2007
+*
+*******************************************************************************
+*
+* This file contains the FreeMASTER protocol decoder and also the handlers
+* of basic protocol commands (read/write memory etc).
+*
+*******************************************************************************/
+
+#include "PE_freemaster.h"
+#include "PE_freemaster_private.h"
+#include "PE_freemaster_protocol.h"
+
+extern __inline FMSTR_BPTR FMSTR_ConstToBuffer16(FMSTR_BPTR pDest, FMSTR_U16 src);
+extern __inline FMSTR_BPTR FMSTR_ConstToBuffer8(FMSTR_BPTR pDest, FMSTR_U8 src);
+extern __inline FMSTR_BPTR FMSTR_ValueFromBuffer16(FMSTR_U16* pDest, FMSTR_BPTR pSrc);
+extern __inline FMSTR_BPTR FMSTR_ValueFromBuffer8(FMSTR_U8* pDest, register FMSTR_BPTR pSrc);
+extern __inline FMSTR_BPTR FMSTR_SkipInBuffer(FMSTR_BPTR pDest, FMSTR_SIZE8 nSize);
+extern __inline FMSTR_BPTR FMSTR_ValueToBuffer16(FMSTR_BPTR pDest, FMSTR_U16 src);
+extern __inline FMSTR_BPTR FMSTR_ValueToBuffer32(FMSTR_BPTR pDest, FMSTR_U32 src);
+extern __inline FMSTR_BPTR FMSTR_ValueToBuffer8(FMSTR_BPTR pDest, FMSTR_U8 src);
+extern __inline FMSTR_BPTR FMSTR_ValueFromBuffer32(FMSTR_U32* pDest, FMSTR_BPTR pSrc);
+
+/**************************************************************************//*!
+*
+* @brief FreeMASTER driver initialization
+*
+******************************************************************************/
+
+void FMSTR_Init(void)
+{
+#if FMSTR_USE_TSA
+ /* initialize TSA */
+ FMSTR_InitTsa();
+#endif
+
+#if FMSTR_USE_SCOPE
+ /* initialize Scope */
+ FMSTR_InitScope();
+#endif
+
+#if FMSTR_USE_RECORDER
+ /* initialize Recorder */
+ FMSTR_InitRec();
+#endif
+
+#if FMSTR_USE_APPCMD
+ /* initialize application commands */
+ FMSTR_InitAppCmds();
+#endif
+
+#if FMSTR_USE_SFIO
+ /* initiazlize SFIO encapsulation layer */
+ FMSTR_InitSfio();
+#endif
+
+#if FMSTR_USE_PIPES
+ /* initialize PIPES interface */
+ FMSTR_InitPipes();
+#endif
+
+#if FMSTR_USE_SCI || FMSTR_USE_JTAG
+ /* initialize communication and start listening for commands */
+ FMSTR_InitSerial();
+#endif
+}
+
+/**************************************************************************//*!
+*
+* @brief Decodes the FreeMASTER protocol and calls appropriate handlers
+*
+* @param pMessageIO - message in/out buffer
+*
+*
+* This Function decodes given message and invokes proper command handler
+* which fills in the response. The response transmission is initiated
+* in this call as well.
+*
+******************************************************************************/
+
+void FMSTR_ProtocolDecoder(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponseEnd;
+ FMSTR_U8 nCmd;
+
+ /* no EX access by default */
+ FMSTR_SetExAddr(FMSTR_FALSE);
+
+ /* command code comes first in the message */
+ /*lint -e{534} return value is not used */
+ FMSTR_ValueFromBuffer8(&nCmd, pMessageIO);
+
+ /* process command */
+ switch (nCmd)
+ {
+
+#if FMSTR_USE_READVAR
+
+ /* read byte */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_READVAR8_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#endif
+#if FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_READVAR8:
+#endif
+ pResponseEnd = FMSTR_ReadVar(pMessageIO, 1U);
+ break;
+
+ /* read word */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_READVAR16_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#endif
+#if FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_READVAR16:
+#endif
+ pResponseEnd = FMSTR_ReadVar(pMessageIO, 2U);
+ break;
+
+ /* read dword */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_READVAR32_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#endif
+#if FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_READVAR32:
+#endif
+ pResponseEnd = FMSTR_ReadVar(pMessageIO, 4U);
+ break;
+#endif /* FMSTR_USE_READVAR */
+
+#if FMSTR_USE_READMEM
+
+ /* read a block of memory */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_READMEM_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#endif
+#if FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_READMEM:
+#endif
+ pResponseEnd = FMSTR_ReadMem(pMessageIO); //Сюда после первого чтения
+ break;
+
+#endif /* FMSTR_USE_READMEM */
+
+#if FMSTR_USE_SCOPE
+
+ /* prepare scope variables */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_SETUPSCOPE_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#endif
+#if FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_SETUPSCOPE:
+#endif
+ pResponseEnd = FMSTR_SetUpScope(pMessageIO);
+ break;
+
+ case FMSTR_CMD_READSCOPE:
+ pResponseEnd = FMSTR_ReadScope(pMessageIO);
+ break;
+#endif /* FMSTR_USE_SCOPE */
+
+#if FMSTR_USE_RECORDER
+
+ /* get recorder status */
+ case FMSTR_CMD_GETRECSTS:
+ pResponseEnd = FMSTR_GetRecStatus(pMessageIO);
+ break;
+
+ /* start recorder */
+ case FMSTR_CMD_STARTREC:
+ pResponseEnd = FMSTR_StartRec(pMessageIO);
+ break;
+
+ /* stop recorder */
+ case FMSTR_CMD_STOPREC:
+ pResponseEnd = FMSTR_StopRec(pMessageIO);
+ break;
+
+ /* setup recorder */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_SETUPREC_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#endif
+#if FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_SETUPREC:
+#endif
+ pResponseEnd = FMSTR_SetUpRec(pMessageIO);
+ break;
+
+ /* get recorder buffer information (force EX instead of non-EX) */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_GETRECBUFF_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#elif FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_GETRECBUFF:
+#endif
+ pResponseEnd = FMSTR_GetRecBuff(pMessageIO);//recorder here
+ break;
+#endif /* FMSTR_USE_RECORDER */
+
+#if FMSTR_USE_APPCMD
+
+ /* accept the application command */
+ case FMSTR_CMD_SENDAPPCMD:
+ pResponseEnd = FMSTR_StoreAppCmd(pMessageIO);
+ break;
+
+ /* get the application command status */
+ case FMSTR_CMD_GETAPPCMDSTS:
+ pResponseEnd = FMSTR_GetAppCmdStatus(pMessageIO);
+ break;
+
+ /* get the application command data */
+ case FMSTR_CMD_GETAPPCMDDATA:
+ pResponseEnd = FMSTR_GetAppCmdRespData(pMessageIO);
+ break;
+#endif /* FMSTR_USE_APPCMD */
+
+#if FMSTR_USE_WRITEMEM
+
+ /* write a block of memory */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_WRITEMEM_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#endif
+#if FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_WRITEMEM:
+#endif
+ pResponseEnd = FMSTR_WriteMem(pMessageIO);
+ break;
+#endif /* FMSTR_USE_WRITEMEM */
+
+#if FMSTR_USE_WRITEMEMMASK
+
+ /* write block of memory with a bit mask */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_WRITEMEMMASK_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#endif
+#if FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_WRITEMEMMASK:
+#endif
+ pResponseEnd = FMSTR_WriteMemMask(pMessageIO);
+ break;
+#endif /* FMSTR_USE_WRITEMEMMASK */
+
+#if FMSTR_USE_WRITEVAR && FMSTR_USE_NOEX_CMDS
+
+ /* write byte */
+ case FMSTR_CMD_WRITEVAR8:
+ pResponseEnd = FMSTR_WriteVar(pMessageIO, 1U);
+ break;
+
+ /* write word */
+ case FMSTR_CMD_WRITEVAR16:
+ pResponseEnd = FMSTR_WriteVar(pMessageIO, 2U);
+ break;
+
+ /* write dword */
+ case FMSTR_CMD_WRITEVAR32:
+ pResponseEnd = FMSTR_WriteVar(pMessageIO, 4U);
+ break;
+#endif /* FMSTR_USE_WRITEVAR && FMSTR_USE_NOEX_CMDS */
+
+#if FMSTR_USE_WRITEVARMASK && FMSTR_USE_NOEX_CMDS
+
+ /* write byte with mask */
+ case FMSTR_CMD_WRITEVAR8MASK:
+ pResponseEnd = FMSTR_WriteVarMask(pMessageIO, 1U);
+ break;
+
+ /* write word with mask */
+ case FMSTR_CMD_WRITEVAR16MASK:
+ pResponseEnd = FMSTR_WriteVarMask(pMessageIO, 2U);
+ break;
+
+#endif /* FMSTR_USE_WRITEVARMASK && FMSTR_USE_NOEX_CMDS */
+
+#if FMSTR_USE_TSA
+
+ /* get TSA table (force EX instead of non-EX) */
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_GETTSAINFO_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#elif FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_GETTSAINFO:
+#endif
+ pResponseEnd = FMSTR_GetTsaInfo(pMessageIO);
+ break;
+
+#if FMSTR_USE_EX_CMDS
+ case FMSTR_CMD_GETSTRLEN_EX:
+ FMSTR_SetExAddr(FMSTR_TRUE);
+#endif
+#if FMSTR_USE_NOEX_CMDS
+ /*lint -fallthrough */
+ case FMSTR_CMD_GETSTRLEN:
+#endif
+ pResponseEnd = FMSTR_GetStringLen(pMessageIO);
+ break;
+
+#endif /* FMSTR_USE_TSA */
+
+#if FMSTR_USE_BRIEFINFO
+ /* retrieve a subset of board information structure */
+ case FMSTR_CMD_GETINFOBRIEF:
+#else
+ /* retrieve board information structure */
+ case FMSTR_CMD_GETINFO:
+#endif
+ pResponseEnd = FMSTR_GetBoardInfo(pMessageIO);
+ break;
+
+#if FMSTR_USE_SFIO
+ case FMSTR_CMD_SFIOFRAME_0:
+ case FMSTR_CMD_SFIOFRAME_1:
+ pResponseEnd = FMSTR_SfioFrame(pMessageIO);
+ break;
+ case FMSTR_CMD_SFIOGETRESP_0:
+ case FMSTR_CMD_SFIOGETRESP_1:
+ pResponseEnd = FMSTR_SfioGetResp(pMessageIO);
+ break;
+#endif /* FMSTR_USE_SFIO */
+
+#if FMSTR_USE_PIPES
+ case FMSTR_CMD_PIPE:
+ pResponseEnd = FMSTR_PipeFrame(pMessageIO);
+ break;
+#endif /* FMSTR_USE_PIPES */
+
+ /* unknown command */
+ default:
+ pResponseEnd = FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_INVCMD);
+ break;
+ }
+
+ /* anything to send back? */
+ if(pResponseEnd != pMessageIO)
+ {
+ /*lint -e{946,960} subtracting pointers is appropriate here */
+ FMSTR_SIZE8 nSize = (FMSTR_SIZE8)(pResponseEnd - pMessageIO);
+ FMSTR_SendResponse(pMessageIO, nSize);
+ }
+}
+
+
+/**************************************************************************//*!
+*
+* @brief Handling GETINFO or GETINFO_BRIEF
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_GetBoardInfo(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_U16 wTmp;
+ FMSTR_U8* pStr;
+
+ pResponse = FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+ pResponse = FMSTR_ConstToBuffer8(pResponse, (FMSTR_U8)(FMSTR_PROT_VER)); /* protVer */
+ pResponse = FMSTR_ConstToBuffer8(pResponse, (FMSTR_U8)(FMSTR_CFG_FLAGS)); /* cfgFlags */
+ pResponse = FMSTR_ConstToBuffer8(pResponse, (FMSTR_U8)(FMSTR_CFG_BUS_WIDTH)); /* dataBusWdt */
+ pResponse = FMSTR_ConstToBuffer8(pResponse, (FMSTR_U8)(FMSTR_GLOB_VERSION_MAJOR)); /* globVerMajor */
+ pResponse = FMSTR_ConstToBuffer8(pResponse, (FMSTR_U8)(FMSTR_GLOB_VERSION_MINOR)); /* globVerMinor */
+ pResponse = FMSTR_ConstToBuffer8(pResponse, (FMSTR_U8)(FMSTR_COMM_BUFFER_SIZE)); /* cmdBuffSize */
+
+ /* that is all for brief info */
+#if FMSTR_USE_BRIEFINFO
+ FMSTR_UNUSED(pStr);
+ FMSTR_UNUSED(wTmp);
+
+#else /* FMSTR_USE_BRIEFINFO */
+
+#if FMSTR_USE_RECORDER
+
+ /* recorder buffer size is always mesured in bytes */
+ wTmp = FMSTR_GetRecBuffSize();
+ wTmp *= FMSTR_CFG_BUS_WIDTH;
+
+ /* send size and timebase */
+ pResponse = FMSTR_ValueToBuffer16(pResponse, wTmp);
+ pResponse = FMSTR_ConstToBuffer16(pResponse, (FMSTR_U16) FMSTR_REC_TIMEBASE);
+#else /* FMSTR_USE_RECORDER */
+
+ FMSTR_UNUSED(wTmp);
+
+ /* recorder info zeroed */
+ pResponse = FMSTR_ConstToBuffer16(pResponse, 0);
+ pResponse = FMSTR_ConstToBuffer16(pResponse, 0);
+#endif /* FMSTR_USE_RECORDER */
+
+ /* description string */
+ pStr = (FMSTR_U8*) FMSTR_IDT_STRING;
+ for(wTmp = 0U; wTmp < (FMSTR_U8)(FMSTR_DESCR_SIZE); wTmp++)
+ {
+ pResponse = FMSTR_ValueToBuffer8(pResponse, *pStr);
+
+ /* terminating zero used to clear the remainder of the buffer */
+ if(*pStr)
+ {
+ pStr ++;
+ }
+ }
+#endif /* FMSTR_USE_BRIEFINFO */
+
+ return pResponse;
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling READMEM and READMEM_EX commands
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_ReadMem(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_ADDR nAddr;
+ FMSTR_U8 nSize;
+
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 2U);
+ pMessageIO = FMSTR_ValueFromBuffer8(&nSize, pMessageIO);
+ pMessageIO = FMSTR_AddressFromBuffer(&nAddr, pMessageIO);
+
+#if FMSTR_USE_TSA && FMSTR_USE_TSA_SAFETY
+ if(!FMSTR_CheckTsaSpace(nAddr, (FMSTR_SIZE8) nSize, FMSTR_FALSE))
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_EACCESS);
+ }
+#endif
+
+ /* check the response will safely fit into comm buffer */
+ if(nSize > (FMSTR_U8)FMSTR_COMM_BUFFER_SIZE)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_RSPBUFFOVF);
+ }
+
+ /* success */
+ pResponse = FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+
+ return FMSTR_CopyToBuffer(pResponse, nAddr, (FMSTR_SIZE8) nSize);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling READVAR and READVAR_EX commands (for all sizes 1,2,4)
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_ReadVar(FMSTR_BPTR pMessageIO, FMSTR_SIZE8 nSize)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_ADDR nAddr;
+
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 1U);
+ pMessageIO = FMSTR_AddressFromBuffer(&nAddr, pMessageIO);
+
+#if FMSTR_USE_TSA && FMSTR_USE_TSA_SAFETY
+ if(!FMSTR_CheckTsaSpace(nAddr, nSize, FMSTR_FALSE))
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_EACCESS);
+ }
+#endif
+
+ /* success */
+ pResponse = FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+
+ return FMSTR_CopyToBuffer(pResponse, nAddr, nSize);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling WRITEMEM and WRITEMEM_EX commands
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_WriteMem(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_ADDR nAddr;
+ FMSTR_U8 nSize;
+
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 2U);
+ pMessageIO = FMSTR_ValueFromBuffer8(&nSize, pMessageIO);
+ pMessageIO = FMSTR_AddressFromBuffer(&nAddr, pMessageIO);
+
+#if FMSTR_USE_TSA && FMSTR_USE_TSA_SAFETY
+ if(!FMSTR_CheckTsaSpace(nAddr, (FMSTR_SIZE8) nSize, FMSTR_TRUE))
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_EACCESS);
+ }
+#endif
+
+ /*lint -e{534} ignoring function return value */
+ FMSTR_CopyFromBuffer(nAddr, pMessageIO, (FMSTR_SIZE8) nSize);
+
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling WRITEVAR command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+* @param nSize - variable size
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_WriteVar(FMSTR_BPTR pMessageIO, FMSTR_SIZE8 nSize)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_ADDR nAddr;
+
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 1U);
+ pMessageIO = FMSTR_AddressFromBuffer(&nAddr, pMessageIO);
+
+#if FMSTR_USE_TSA && FMSTR_USE_TSA_SAFETY
+ if(!FMSTR_CheckTsaSpace(nAddr, nSize, FMSTR_TRUE))
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_EACCESS);
+ }
+#endif
+
+ /*lint -e{534} ignoring function return value */
+ FMSTR_CopyFromBuffer(nAddr, pMessageIO, nSize);
+
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+}
+
+
+/**************************************************************************//*!
+*
+* @brief Handling WRITEMEMMASK and WRITEMEMMASK_EX commands
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_WriteMemMask(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_ADDR nAddr;
+ FMSTR_U8 nSize;
+
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 2U);
+ pMessageIO = FMSTR_ValueFromBuffer8(&nSize, pMessageIO);
+ pMessageIO = FMSTR_AddressFromBuffer(&nAddr, pMessageIO);
+
+#if FMSTR_USE_TSA && FMSTR_USE_TSA_SAFETY
+ if(!FMSTR_CheckTsaSpace(nAddr, (FMSTR_SIZE8)nSize, FMSTR_TRUE))
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_EACCESS);
+ }
+#endif
+
+#if FMSTR_CFG_BUS_WIDTH > 1U
+ /* size must be divisible by bus width (mask must not begin in half of memory word) */
+ if(nSize % FMSTR_CFG_BUS_WIDTH)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVSIZE);
+ }
+#endif
+
+ /* put the data */
+ FMSTR_CopyFromBufferWithMask(nAddr, pMessageIO, (FMSTR_SIZE8)nSize);
+
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling WRITEVARMASK command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+* @param nSize - variable size
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_WriteVarMask(FMSTR_BPTR pMessageIO, FMSTR_SIZE8 nSize)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_ADDR nAddr;
+
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 1U);
+ pMessageIO = FMSTR_AddressFromBuffer(&nAddr, pMessageIO);
+
+#if FMSTR_USE_TSA && FMSTR_USE_TSA_SAFETY
+ if(!FMSTR_CheckTsaSpace(nAddr, nSize, FMSTR_TRUE))
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_EACCESS);
+ }
+#endif
+
+ /* put the data */
+ FMSTR_CopyFromBufferWithMask(nAddr, pMessageIO, nSize);
+
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+}
+
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_protocol.h b/Projects/epwm_test/Freemaster/PE_freemaster_protocol.h
new file mode 100644
index 0000000..799defe
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_protocol.h
@@ -0,0 +1,130 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_protocol.h
+*
+* @brief FreeMASTER protocol header file
+*
+* @version 1.0.8.0
+*
+* @date Apr-11-2007
+*
+*******************************************************************************/
+
+#ifndef __FREEMASTER_PROTOCOL_H
+#define __FREEMASTER_PROTOCOL_H
+
+/*-------------------------------------
+ command message - standard commands
+ -------------------------------------*/
+
+#define FMSTR_CMD_READMEM 0x01U
+#define FMSTR_CMD_WRITEMEM 0x02U
+#define FMSTR_CMD_WRITEMEMMASK 0x03U
+#define FMSTR_CMD_READMEM_EX 0x04U /* read a block of memory */
+#define FMSTR_CMD_WRITEMEM_EX 0x05U /* write a block of memory */
+#define FMSTR_CMD_WRITEMEMMASK_EX 0x06U /* write block of memory with bit mask */
+#define FMSTR_CMD_SETUPSCOPE 0x08U
+#define FMSTR_CMD_SETUPREC 0x09U
+#define FMSTR_CMD_SETUPSCOPE_EX 0x0aU /* setup the osciloscope */
+#define FMSTR_CMD_SETUPREC_EX 0x0bU /* setup the recorder */
+#define FMSTR_CMD_SENDAPPCMD 0x10U /* send the application command */
+#define FMSTR_CMD_GETTSAINFO 0x11U /* get TSA info */
+#define FMSTR_CMD_GETTSAINFO_EX 0x12U /* get TSA info 32bit */
+#define FMSTR_CMD_SFIOFRAME_1 0x13U /* deliver & execute SFIO frame (even) */
+#define FMSTR_CMD_SFIOFRAME_0 0x14U /* deliver & execute SFIO frame (odd) */
+#define FMSTR_CMD_PIPE 0x15U /* read/write pipe data */
+
+/*-------------------------------------
+ command message - Fast Commands
+ -------------------------------------*/
+
+/* no data part */
+#define FMSTR_CMD_GETINFO 0xc0U /* retrieve board information structure */
+#define FMSTR_CMD_STARTREC 0xc1U /* start data recorder */
+#define FMSTR_CMD_STOPREC 0xc2U /* stop data recorder */
+#define FMSTR_CMD_GETRECSTS 0xc3U /* get the recorder status */
+#define FMSTR_CMD_GETRECBUFF 0xc4U
+#define FMSTR_CMD_READSCOPE 0xc5U /* read the scope data */
+#define FMSTR_CMD_GETAPPCMDSTS 0xc6U /* get the application command status */
+#define FMSTR_CMD_GETINFOBRIEF 0xc8U /* retrieve a subset of board information structure */
+#define FMSTR_CMD_GETRECBUFF_EX 0xc9U /* get the recorder data */
+#define FMSTR_CMD_SFIOGETRESP_0 0xcaU /* retry to get last SFIO response (even) */
+#define FMSTR_CMD_SFIOGETRESP_1 0xcbU /* retry to get last SFIO response (odd) */
+
+/* 2 bytes data part */
+#define FMSTR_CMD_READVAR8 0xD0U
+#define FMSTR_CMD_READVAR16 0xD1U
+#define FMSTR_CMD_READVAR32 0xD2U
+#define FMSTR_CMD_GETAPPCMDDATA 0xD3U /* get the application command data */
+#define FMSTR_CMD_GETSTRLEN 0xD4U /* get string length (required by TSA) */
+
+/* 4 bytes data part */
+#define FMSTR_CMD_READVAR8_EX 0xe0U /* read byte variable */
+#define FMSTR_CMD_READVAR16_EX 0xe1U /* read word variable */
+#define FMSTR_CMD_READVAR32_EX 0xe2U /* read dword variable */
+#define FMSTR_CMD_WRITEVAR8 0xe3U /* write byte variable */
+#define FMSTR_CMD_WRITEVAR16 0xe4U /* write word variable */
+#define FMSTR_CMD_WRITEVAR8MASK 0xe5U /* write specified bits in byte variable */
+#define FMSTR_CMD_GETSTRLEN_EX 0xe6U /* get string length (required by TSA) */
+
+/* 6 bytes data part */
+#define FMSTR_CMD_WRITEVAR32 0xf0U /* write dword variable */
+#define FMSTR_CMD_WRITEVAR16MASK 0xf1U /* write specified bits in word variable */
+
+/*-------------------------------------
+ response message - status byte
+ -------------------------------------*/
+
+/* flags in response codes */
+#define FMSTR_STSF_ERROR 0x80U /* FLAG: error answer (no response data) */
+#define FMSTR_STSF_VARLEN 0x40U /* FLAG: variable-length answer (length byte) */
+#define FMSTR_STSF_EVENT 0x20U /* FLAG: reserved */
+
+/* confirmation codes */
+#define FMSTR_STS_OK 0x00U /* operation finished successfuly */
+#define FMSTR_STS_RECRUN 0x01U /* data recorder is running */
+#define FMSTR_STS_RECDONE 0x02U /* data recorder is stopped */
+
+/* error codes */
+#define FMSTR_STC_INVCMD 0x81U /* unknown command code */
+#define FMSTR_STC_CMDCSERR 0x82U /* command checksum error */
+#define FMSTR_STC_CMDTOOLONG 0x83U /* comand is too long */
+#define FMSTR_STC_RSPBUFFOVF 0x84U /* the response would not fit into transmit buffer */
+#define FMSTR_STC_INVBUFF 0x85U /* invalid buffer length or operation */
+#define FMSTR_STC_INVSIZE 0x86U /* invalid size specified */
+#define FMSTR_STC_SERVBUSY 0x87U /* service is busy */
+#define FMSTR_STC_NOTINIT 0x88U /* service is not initialised */
+#define FMSTR_STC_EACCESS 0x89U /* access is denied */
+#define FMSTR_STC_SFIOERR 0x8AU /* Error in SFIO frame */
+#define FMSTR_STC_SFIOUNMATCH 0x8BU /* Even/odd mismatch in SFIO transaction */
+#define FMSTR_STC_PIPEERR 0x8CU /* Pipe error */
+#define FMSTR_STC_FASTRECERR 0x8DU /* Feature not implemented in Fast Recorder */
+
+/******************************************************************************
+* Protocol constants
+*******************************************************************************/
+
+#define FMSTR_SOB 0x2bU /* '+' - start of message*/
+#define FMSTR_FASTCMD 0xc0U /* code of fast cmd 0xc0> */
+#define FMSTR_FASTCMD_DATALEN_MASK 0x30U /* mask of data length part of fast command */
+#define FMSTR_FASTCMD_DATALEN_SHIFT 3
+#define FMSTR_DESCR_SIZE 25U /* length board desription string */
+
+/* Board configuration flags */
+#define FMSTR_CFGFLAG_BIGENDIAN 0x01U /*/< used when CPU is big endian */
+
+/* TSA-global flags */
+#define FMSTR_TSA_INFO_VERSION_MASK 0x000fU /*/< TSA version */
+#define FMSTR_TSA_INFO_32BIT 0x0100U /*/< TSA address format (16/32 bit) */
+#define FMSTR_TSA_INFO_HV2BA 0x0200U /*/< TSA HawkV2 byte-addressing mode */
+
+#endif /* __FREEMASTER_PROTOCOL_H */
+
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_rec.c b/Projects/epwm_test/Freemaster/PE_freemaster_rec.c
new file mode 100644
index 0000000..d7c5302
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_rec.c
@@ -0,0 +1,723 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_rec.c
+*
+* @brief FreeMASTER Recorder implementation.
+*
+* @version 1.0.10.0
+*
+* @date Oct-22-2007
+*
+*******************************************************************************/
+
+#include "PE_freemaster.h"
+#include "PE_freemaster_private.h"
+#include "PE_freemaster_protocol.h"
+
+#if FMSTR_USE_RECORDER
+
+#include "PE_freemaster_rec.h"
+
+#if FMSTR_USE_FASTREC
+#include "PE_freemaster_fastrec.h"
+#endif
+
+/********************************************************
+* global variables (shared with FastRecorder if used)
+********************************************************/
+
+/* configuration variables */
+FMSTR_U16 pcm_wRecTotalSmps; /* number of samples to measure */
+FMSTR_U16 pcm_wRecPostTrigger; /* number of post-trigger samples to keep */
+FMSTR_U8 pcm_nRecTriggerMode; /* triger mode (0 = disabled, 1 = _/, 2 = \_) */
+FMSTR_U16 pcm_wRecTimeDiv; /* divisor of recorder "clock" */
+
+FMSTR_U8 pcm_nRecVarCount; /* number of active recorder variables */
+FMSTR_ADDR pcm_pRecVarAddr[FMSTR_MAX_SCOPE_VARS]; /* addresses of recorded variables */
+FMSTR_SIZE8 pcm_pRecVarSize[FMSTR_MAX_SCOPE_VARS]; /* sizes of recorded variables */
+
+/* runtime variables */
+FMSTR_U16 pcm_wRecBuffStartIx; /* first sample index */
+
+FMSTR_ADDR pcm_dwRecWritePtr; /* write pointer in recorder buffer */
+FMSTR_ADDR pcm_dwRecEndBuffPtr; /* pointer to end of active recorder buffer */
+FMSTR_U16 pcm_wRecTimeDivCtr; /* recorder "clock" divisor counter */
+FMSTR_U16 pcm_wStoprecCountDown; /* post-trigger countdown counter */
+
+/* recorder flags */
+FMSTR_REC_FLAGS pcm_wRecFlags;
+
+/***********************************
+* local variables
+***********************************/
+
+/* configuration variables */
+static FMSTR_ADDR pcm_nTrgVarAddr; /* trigger variable address */
+static FMSTR_U8 pcm_nTrgVarSize; /* trigger variable threshold size */
+static FMSTR_U8 pcm_bTrgVarSigned; /* trigger compare mode (0 = unsigned, 1 = signed) */
+
+/*lint -e{960} using union */
+static union
+{
+#if FMSTR_CFG_BUS_WIDTH == 1
+ FMSTR_U8 u8;
+ FMSTR_S8 s8;
+#endif
+ FMSTR_U16 u16;
+ FMSTR_S16 s16;
+ FMSTR_U32 u32;
+ FMSTR_S32 s32;
+} pcm_uTrgThreshold; /* trigger threshold level (1,2 or 4 bytes) */
+
+static FMSTR_ADDR pcm_nRecBuffAddr; /* recorder buffer address */
+static FMSTR_SIZE pcm_wRecBuffSize; /* recorder buffer size */
+
+/* compare functions prototype */
+typedef FMSTR_BOOL (*FMSTR_PCOMPAREFUNC)(void);
+
+/*/ pointer to active compare function */
+static FMSTR_PCOMPAREFUNC pcm_pCompareFunc;
+
+#if !FMSTR_REC_OWNBUFF && !FMSTR_USE_FASTREC
+/* put buffer into far memory ? */
+#if FMSTR_REC_FARBUFF
+#pragma section fardata begin
+#endif /* FMSTR_REC_FARBUFF */
+/* statically allocated recorder buffer (FMSTR_REC_OWNBUFF is FALSE) */
+static FMSTR_U8 pcm_pOwnRecBuffer[FMSTR_REC_BUFF_SIZE];
+/* end of far memory section */
+#if FMSTR_REC_FARBUFF
+#pragma section fardata end
+#endif /* FMSTR_REC_FARBUFF */
+#endif /* FMSTR_REC_OWNBUFF */
+
+/***********************************
+* local functions
+***********************************/
+
+static FMSTR_BOOL FMSTR_Compare8S(void);
+static FMSTR_BOOL FMSTR_Compare8U(void);
+static FMSTR_BOOL FMSTR_Compare16S(void);
+static FMSTR_BOOL FMSTR_Compare16U(void);
+static FMSTR_BOOL FMSTR_Compare32S(void);
+static FMSTR_BOOL FMSTR_Compare32U(void);
+static void FMSTR_Recorder2(void);
+
+/**************************************************************************//*!
+*
+* @brief Recorder Initialization
+*
+******************************************************************************/
+
+void FMSTR_InitRec(void)
+{
+ /* setup buffer pointer and size so IsInRecBuffer works even
+ before the recorder is first initialized and used */
+
+#if FMSTR_REC_OWNBUFF || FMSTR_USE_FASTREC
+ /* user wants to use his own buffer */
+ pcm_nRecBuffAddr = 0U;
+ pcm_wRecBuffSize = 0U;
+#else
+ /* size in native sizeof units (=bytes on most platforms) */
+ pcm_wRecBuffSize = (FMSTR_SIZE) FMSTR_REC_BUFF_SIZE;
+ FMSTR_ARR2ADDR(pcm_nRecBuffAddr, pcm_pOwnRecBuffer);
+
+ /*lint -esym(528, pcm_pOwnRecBuffer) this symbol is used outside of lint sight */
+#endif
+
+#if FMSTR_USE_FASTREC
+ FMSTR_InitFastRec();
+#endif
+}
+
+/**************************************************************************//*!
+*
+* @brief API: Replacing the recorder buffer with the user's one
+*
+* @param pBuffer - user buffer pointer
+* @param wBuffSize - buffer size
+*
+* @note Use the FMSTR_SetUpBuff32 to pass the forced 32bit address in SDM
+*
+******************************************************************************/
+
+void FMSTR_SetUpRecBuff(FMSTR_ADDR pBuffer, FMSTR_SIZE nBuffSize)
+{
+ pcm_nRecBuffAddr = pBuffer;
+ pcm_wRecBuffSize = nBuffSize;
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling SETUPREC and SETUPREC_EX commands
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_SetUpRec(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_SIZE8 nRecVarsetSize;
+ FMSTR_SIZE blen;
+ FMSTR_U8 i, sz;
+
+ /* de-initialize first */
+ FMSTR_AbortRec();
+
+#if FMSTR_REC_OWNBUFF || FMSTR_USE_FASTREC
+ /* user wants to use his own buffer, check if it is valid */
+ if(!pcm_nRecBuffAddr || !pcm_wRecBuffSize)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVBUFF);
+ }
+#else
+ /* size in native sizeof units (=bytes on most platforms) */
+ pcm_wRecBuffSize = (FMSTR_SIZE)FMSTR_REC_BUFF_SIZE;
+ FMSTR_ARR2ADDR(pcm_nRecBuffAddr, pcm_pOwnRecBuffer); // заполнение буфера
+#endif
+
+ /* seek the setup data */
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 2U);
+ pMessageIO = FMSTR_ValueFromBuffer8(&pcm_nRecTriggerMode, pMessageIO);
+ pMessageIO = FMSTR_ValueFromBuffer16(&pcm_wRecTotalSmps, pMessageIO);
+ pMessageIO = FMSTR_ValueFromBuffer16(&pcm_wRecPostTrigger, pMessageIO);
+ pMessageIO = FMSTR_ValueFromBuffer16(&pcm_wRecTimeDiv, pMessageIO);
+
+ /* address & size of trigger variable */
+ pMessageIO = FMSTR_AddressFromBuffer(&pcm_nTrgVarAddr, pMessageIO);
+ pMessageIO = FMSTR_ValueFromBuffer8(&pcm_nTrgVarSize, pMessageIO);
+
+ /* trigger compare mode */
+ pMessageIO = FMSTR_ValueFromBuffer8(&pcm_bTrgVarSigned, pMessageIO);
+
+ /* threshold value */
+ pMessageIO = FMSTR_ValueFromBuffer32(&pcm_uTrgThreshold.u32, pMessageIO);
+
+ /* recorder variable count */
+ pMessageIO = FMSTR_ValueFromBuffer8(&pcm_nRecVarCount, pMessageIO);
+
+ /* rec variable information must fit into our buffers */
+ if(!pcm_nRecVarCount || pcm_nRecVarCount > (FMSTR_U8)FMSTR_MAX_REC_VARS)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVBUFF);
+ }
+
+ /* calculate sum of sizes of all variables */
+ nRecVarsetSize = 0U;
+
+ /* get all addresses and sizes */
+ for(i=0U; i 8U)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVSIZE);
+ }
+
+#if FMSTR_CFG_BUS_WIDTH > 1U
+ /* even sizes only */
+ if(sz & 0x1)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVSIZE);
+ }
+#endif
+
+#if FMSTR_USE_TSA && FMSTR_USE_TSA_SAFETY
+ if(!FMSTR_CheckTsaSpace(pcm_pRecVarAddr[i], (FMSTR_SIZE8)sz, 0U))
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_EACCESS);
+ }
+#endif
+ }
+
+ /* fast recorder handles trigger by itself */
+#if !FMSTR_USE_FASTREC
+ /* any trigger? */
+ pcm_pCompareFunc = NULL;
+ if(pcm_nRecTriggerMode)
+ {
+ /* access to trigger variable? */
+#if FMSTR_USE_TSA && FMSTR_USE_TSA_SAFETY
+ if(!FMSTR_CheckTsaSpace(pcm_nTrgVarAddr, (FMSTR_SIZE8)pcm_nTrgVarSize, 0U))
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_EACCESS);
+ }
+#endif
+ /* get compare function */
+ switch(pcm_nTrgVarSize)
+ {
+#if FMSTR_CFG_BUS_WIDTH == 1U
+ case 1: pcm_pCompareFunc = pcm_bTrgVarSigned ? FMSTR_Compare8S : FMSTR_Compare8U; break;
+#endif
+ case 2: pcm_pCompareFunc = pcm_bTrgVarSigned ? FMSTR_Compare16S : FMSTR_Compare16U; break;
+ case 4: pcm_pCompareFunc = pcm_bTrgVarSigned ? FMSTR_Compare32S : FMSTR_Compare32U; break;
+
+ /* invalid trigger variable size */
+ default:
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVSIZE);
+ }
+ }
+#endif /* !FMSTR_USE_FASTREC */
+
+ /* total recorder buffer length in native sizeof units (=bytes on most platforms) */
+ blen = (FMSTR_SIZE) (pcm_wRecTotalSmps * nRecVarsetSize / FMSTR_CFG_BUS_WIDTH);
+
+ /* recorder memory available? */
+ if(blen > pcm_wRecBuffSize)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVSIZE);
+ }
+
+ /* remember the effective end of circular buffer */
+ pcm_dwRecEndBuffPtr = pcm_nRecBuffAddr + blen;
+
+#if FMSTR_USE_FASTREC
+ if(!FMSTR_SetUpFastRec())
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_FASTRECERR);
+#endif
+
+ /* everything is okay */
+ pcm_wRecFlags.flg.bIsConfigured = 1U;
+
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+}
+
+/**************************************************************************//*!
+*
+* @brief Abort and de-initialize recorder
+*
+******************************************************************************/
+
+void FMSTR_AbortRec(void)
+{
+ /* clear flags */
+ pcm_wRecFlags.all = 0U;
+}
+
+/**************************************************************************//*!
+*
+* @brief Check wether given memory region is inside the recorder buffer
+*
+* @param dwAddr - address of the memory to be checked
+* @param wSize - size of the memory to be checked
+*
+* @return This function returns non-zero if user space is in recorder buffer
+*
+* This function is called as a pert of TSA-checking process when the PC host
+* is requesting memory contents
+*
+******************************************************************************/
+
+FMSTR_BOOL FMSTR_IsInRecBuffer(FMSTR_ADDR dwAddr, FMSTR_SIZE8 nSize)
+{
+ FMSTR_BOOL bRet = 0U;
+
+ if(dwAddr >= pcm_nRecBuffAddr)
+ {
+ bRet = (FMSTR_BOOL)((dwAddr + nSize) <= (pcm_nRecBuffAddr + FMSTR_GetRecBuffSize()) ? FMSTR_TRUE : FMSTR_FALSE);
+ }
+
+ return bRet;
+}
+
+/**************************************************************************//*!
+*
+* @brief Get recorder memory size
+*
+* @return Recorder memory size in native sizeof units (=bytes on most platforms)
+*
+******************************************************************************/
+
+FMSTR_SIZE FMSTR_GetRecBuffSize()
+{
+#if FMSTR_REC_OWNBUFF || FMSTR_USE_FASTREC
+ return pcm_wRecBuffSize;
+#else
+ return (FMSTR_SIZE) FMSTR_REC_BUFF_SIZE;
+#endif
+}
+
+/**************************************************************************//*!
+*
+* @brief API: Pull the trigger of the recorder
+*
+* This function starts the post-trigger stop countdown
+*
+******************************************************************************/
+
+void FMSTR_TriggerRec(void)
+{
+ if(!pcm_wRecFlags.flg.bIsStopping)
+ {
+ pcm_wRecFlags.flg.bIsStopping = 1U;
+ pcm_wStoprecCountDown = pcm_wRecPostTrigger;
+
+#if FMSTR_USE_FASTREC
+ FMSTR_TriggerFastRec();
+#endif
+ }
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling STARTREC command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the length
+* of the response filled into the buffer (including status byte)
+*
+* This function starts recording (initializes internal recording variables
+* and flags)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_StartRec(FMSTR_BPTR pMessageIO)
+{
+ /* must be configured */
+ if(!pcm_wRecFlags.flg.bIsConfigured)
+ {
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_NOTINIT);
+ }
+
+ /* already running ? */
+ if(pcm_wRecFlags.flg.bIsRunning)
+ {
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STS_RECRUN);
+ }
+
+ /* initialize write pointer */
+ pcm_dwRecWritePtr = pcm_nRecBuffAddr;
+
+ /* current (first) sample index */
+ pcm_wRecBuffStartIx = 0U;
+
+ /* initialize time divisor */
+ pcm_wRecTimeDivCtr = 0U;
+
+ /* initiate virgin cycle */
+ pcm_wRecFlags.flg.bIsStopping = 0U; /* no trigger active */
+ pcm_wRecFlags.flg.bTrgCrossActive = 0U; /* waiting for threshold crossing */
+ pcm_wRecFlags.flg.bInvirginCycle = 1U; /* initial cycle */
+
+ /* start fast recorder */
+#if FMSTR_USE_FASTREC
+ FMSTR_StartFastRec();
+#endif
+
+ /* run now */
+ pcm_wRecFlags.flg.bIsRunning = 1U; /* is running now! */
+
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STS_OK);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling STOPREC command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the length
+* of the response filled into the buffer (including status byte)
+*
+* This function stops recording (same as manual trigger)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_StopRec(FMSTR_BPTR pMessageIO)
+{
+ /* must be configured */
+ if(!pcm_wRecFlags.flg.bIsConfigured)
+ {
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_NOTINIT);
+ }
+
+ /* already stopped ? */
+ if(!pcm_wRecFlags.flg.bIsRunning)
+ {
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STS_RECDONE);
+ }
+
+ /* simulate trigger */
+ FMSTR_TriggerRec();
+
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STS_OK);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling GETRECSTS command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+* This function returns current recorder status
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_GetRecStatus(FMSTR_BPTR pMessageIO)
+{
+ /* must be configured */
+ if(!pcm_wRecFlags.flg.bIsConfigured)
+ {
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_NOTINIT);
+ }
+
+ /* get run/stop status */
+ return FMSTR_ConstToBuffer8(pMessageIO, (FMSTR_U8)(pcm_wRecFlags.flg.bIsRunning ?
+ FMSTR_STS_RECRUN : FMSTR_STS_RECDONE));
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling GETRECBUFF and GETRECBUFF_EX command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+* This function returns recorder buffer information
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_GetRecBuff(FMSTR_BPTR pMessageIO)
+{
+ /* must be configured */
+ if(!pcm_wRecFlags.flg.bIsConfigured)
+ {
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_NOTINIT);
+ }
+
+ /* must be stopped */
+ if(pcm_wRecFlags.flg.bIsRunning)
+ {
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_SERVBUSY);
+ }
+
+#if FMSTR_USE_FASTREC
+ FMSTR_GetFastRecBuff();
+#endif
+
+ /* fill the return info */
+ pMessageIO = FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STS_OK);
+ pMessageIO = FMSTR_AddressToBuffer(pMessageIO, pcm_nRecBuffAddr);
+
+ return FMSTR_ValueToBuffer16(pMessageIO, pcm_wRecBuffStartIx);
+}
+
+/* now follows the sampling routines, skip that if FastRecorder is used */
+#if !FMSTR_USE_FASTREC
+
+/**************************************************************************//*!
+*
+* @brief Compare macro used in trigger detection
+*
+* @param v - original command
+* @param t - response buffer
+*
+* @return zero when value is lower than threshold.
+* @return non-zero when value is greater than or equal as treshold
+*
+******************************************************************************/
+
+#define CMP(v,t) ((FMSTR_BOOL)(((v) < (t)) ? 0 : 1))
+
+#if FMSTR_CFG_BUS_WIDTH == 1U
+
+static FMSTR_BOOL FMSTR_Compare8S()
+{
+ return CMP(FMSTR_GetS8(pcm_nTrgVarAddr), pcm_uTrgThreshold.s8);
+}
+
+static FMSTR_BOOL FMSTR_Compare8U()
+{
+ return CMP(FMSTR_GetU8(pcm_nTrgVarAddr), pcm_uTrgThreshold.u8);
+}
+
+#endif
+
+static FMSTR_BOOL FMSTR_Compare16S()
+{
+ return CMP(FMSTR_GetS16(pcm_nTrgVarAddr), pcm_uTrgThreshold.s16);
+}
+
+static FMSTR_BOOL FMSTR_Compare16U()
+{
+ return CMP(FMSTR_GetU16(pcm_nTrgVarAddr), pcm_uTrgThreshold.u16);
+}
+
+static FMSTR_BOOL FMSTR_Compare32S()
+{
+ return CMP(FMSTR_GetS32(pcm_nTrgVarAddr), pcm_uTrgThreshold.s32);
+}
+
+static FMSTR_BOOL FMSTR_Compare32U()
+{
+ return CMP(FMSTR_GetU32(pcm_nTrgVarAddr), pcm_uTrgThreshold.u32);
+}
+
+/**************************************************************************//*!
+*
+* @brief API: Recorder worker routine - can be called from application's timer ISR
+*
+*
+* This returns quickly if recorder is not running, otherwise it calls quite lengthy
+* recorder routine which does all the recorder work (sampling, triggering)
+*
+******************************************************************************/
+
+void FMSTR_Recorder(void)
+{
+ /* recorder not active */
+ if(!pcm_wRecFlags.flg.bIsRunning)
+ {
+ return ;
+ }
+
+ /* do the hard work */
+ FMSTR_Recorder2();
+}
+
+/**************************************************************************//*!
+*
+* @brief Recorder function called when recorder is active
+*
+******************************************************************************/
+
+static void FMSTR_Recorder2(void)
+{
+ FMSTR_SIZE8 sz;
+ FMSTR_BOOL cmp;
+ FMSTR_U8 i;
+
+ /* skip this call ? */
+ if(pcm_wRecTimeDivCtr)
+ {
+ /* maybe next time... */
+ pcm_wRecTimeDivCtr--;
+ return;
+ }
+
+ /* re-initialize divider */
+ pcm_wRecTimeDivCtr = pcm_wRecTimeDiv;
+
+ /* take snapshot of variable values */
+ for (i=0U; i= pcm_dwRecEndBuffPtr)
+ {
+ pcm_dwRecWritePtr = pcm_nRecBuffAddr;
+ pcm_wRecFlags.flg.bInvirginCycle = 0U;
+ pcm_wRecBuffStartIx = 0U;
+ }
+
+ /* no trigger testing in virgin cycle */
+ if(pcm_wRecFlags.flg.bInvirginCycle)
+ {
+ return;
+ }
+
+ /* test trigger condition if still running */
+ if(!pcm_wRecFlags.flg.bIsStopping && pcm_pCompareFunc != NULL)
+ {
+ /* compare trigger threshold */
+ cmp = pcm_pCompareFunc();
+
+ /* negated logic (falling-edge) ? */
+ if(pcm_nRecTriggerMode == 2U)
+ {
+ cmp = (FMSTR_BOOL) !cmp;
+ }
+
+ /* above threshold ? */
+ if(cmp)
+ {
+ /* were we at least once below threshold ? */
+ if(pcm_wRecFlags.flg.bTrgCrossActive)
+ {
+ /* EDGE TRIGGER ! */
+ FMSTR_TriggerRec();
+ }
+ }
+ else
+ {
+ /* we got bellow threshold, now wait for being above threshold */
+ pcm_wRecFlags.flg.bTrgCrossActive = 1U;
+ }
+ }
+
+ /* in stopping mode ? (note that this bit might have been set just above!) */
+ if(pcm_wRecFlags.flg.bIsStopping)
+ {
+ /* count down post-trigger samples expired ? */
+ if(!pcm_wStoprecCountDown)
+ {
+ /* STOP RECORDER */
+ pcm_wRecFlags.flg.bIsRunning = 0U;
+ return;
+ }
+
+ /* perhaps next time */
+ pcm_wStoprecCountDown--;
+ }
+}
+
+#endif /* !FMSTR_USE_FASTREC */
+
+#else /* FMSTR_USE_RECORDER */
+
+/* use void recorder API functions */
+void FMSTR_Recorder(void)
+{
+}
+
+void FMSTR_TriggerRec(void)
+{
+}
+
+void FMSTR_SetUpRecBuff(FMSTR_ADDR pBuffer, FMSTR_SIZE wBuffSize)
+{
+ FMSTR_UNUSED(pBuffer);
+ FMSTR_UNUSED(wBuffSize);
+}
+
+/*lint -efile(766, PE_freemaster_protocol.h) include file is not used in this case */
+
+#endif /* FMSTR_USE_RECORDER */
+
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_rec.h b/Projects/epwm_test/Freemaster/PE_freemaster_rec.h
new file mode 100644
index 0000000..4e1ee7c
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_rec.h
@@ -0,0 +1,83 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_rec.h
+*
+* @brief FreeMASTER Recorder implementation.
+*
+* @version 1.0.2.0
+*
+* @date Aug-15-2007
+*
+*******************************************************************************/
+
+#ifndef __FREEMASTER_REC_H
+#define __FREEMASTER_REC_H
+
+#ifndef __FREEMASTER_H
+#error Please include PE_freemaster_rec.h after PE_freemaster.h main header file.
+#endif
+
+#include "PE_freemaster.h"
+#include "PE_freemaster_private.h"
+
+/***********************************
+* global recorder types
+***********************************/
+
+/* recorder runtime flags */
+typedef volatile union
+{
+ FMSTR_FLAGS all;
+
+ struct
+ {
+ unsigned bIsConfigured : 1; /* recorder is configured */
+ unsigned bIsRunning : 1; /* recorder is running */
+ unsigned bIsStopping : 1; /* trigger activated, sample countdown */
+ unsigned bInvirginCycle : 1; /* virgin cycle of the circular buffer in-progress */
+ unsigned bTrgCrossActive : 1; /* trigger trheshold was crossed */
+ } flg;
+
+} FMSTR_REC_FLAGS;
+
+/* the same flags for optimized asm access (see fast recorder) */
+#if defined(FMSTR_PLATFORM_56F8xxx) /* flag allocation tested on 56f8xxx only */
+#define FMSTR_REC_FLAG_bIsConfigured 0x01
+#define FMSTR_REC_FLAG_bIsRunning 0x02
+#define FMSTR_REC_FLAG_bIsStopping 0x04
+#define FMSTR_REC_FLAG_bInvirginCycle 0x08
+#define FMSTR_REC_FLAG_bTrgCrossActive 0x10
+#endif
+
+/***********************************
+* global recorder variables
+***********************************/
+
+/* configuration variables */
+extern FMSTR_U16 pcm_wRecTotalSmps; /* number of samples to measure */
+extern FMSTR_U16 pcm_wRecPostTrigger; /* number of post-trigger samples to keep */
+extern FMSTR_U8 pcm_nRecTriggerMode; /* triger mode (0 = disabled, 1 = _/, 2 = \_) */
+extern FMSTR_U16 pcm_wRecTimeDiv; /* divisor of recorder "clock" */
+
+extern FMSTR_U8 pcm_nRecVarCount; /* number of active recorder variables */
+extern FMSTR_ADDR pcm_pRecVarAddr[FMSTR_MAX_SCOPE_VARS]; /* addresses of recorded variables */
+extern FMSTR_SIZE8 pcm_pRecVarSize[FMSTR_MAX_SCOPE_VARS]; /* sizes of recorded variables */
+
+/* runtime variables */
+extern FMSTR_U16 pcm_wRecBuffStartIx; /* first sample index */
+
+extern FMSTR_ADDR pcm_dwRecWritePtr; /* write pointer in recorder buffer */
+extern FMSTR_ADDR pcm_dwRecEndBuffPtr; /* pointer to end of active recorder buffer */
+extern FMSTR_U16 pcm_wRecTimeDivCtr; /* recorder "clock" divisor counter */
+extern FMSTR_U16 pcm_wStoprecCountDown; /* post-trigger countdown counter */
+
+extern FMSTR_REC_FLAGS pcm_wRecFlags;
+
+#endif /* __FREEMASTER_REC_H */
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_scope.c b/Projects/epwm_test/Freemaster/PE_freemaster_scope.c
new file mode 100644
index 0000000..cf72b60
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_scope.c
@@ -0,0 +1,152 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_scope.c
+*
+* @brief FreeMASTER Oscilloscope implementation
+*
+* @version 1.0.4.0
+*
+* @date Apr-11-2007
+*
+*******************************************************************************/
+
+#include "PE_freemaster.h"
+#include "PE_freemaster_private.h"
+#include "PE_freemaster_protocol.h"
+
+#if FMSTR_USE_SCOPE
+
+/***********************************
+* local variables
+***********************************/
+
+static FMSTR_U8 pcm_nScopeVarCount; /* number of active scope variables */
+static FMSTR_ADDR pcm_pScopeVarAddr[FMSTR_MAX_SCOPE_VARS]; /* addresses of scope variables */
+static FMSTR_SIZE8 pcm_pScopeVarSize[FMSTR_MAX_SCOPE_VARS]; /* sizes of scope variables */
+
+/**************************************************************************//*!
+*
+* @brief Scope Initialization
+*
+******************************************************************************/
+
+void FMSTR_InitScope(void)
+{
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling SETUPSCOPE and SETUPSCOPE_EX command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_SetUpScope(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_U8 i, sz, nVarCnt;
+
+ /* uninitialize scope */
+ pcm_nScopeVarCount = 0U;
+
+ /* seek the setup data */
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 2U);
+
+ /* scope variable count */
+ pMessageIO = FMSTR_ValueFromBuffer8(&nVarCnt, pMessageIO);
+
+ /* scope variable information must fit into our buffers */
+ if(!nVarCnt || nVarCnt > (FMSTR_U8)FMSTR_MAX_SCOPE_VARS)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVBUFF);
+ }
+
+ /* get all addresses and sizes */
+ for(i=0U; i 8U)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVSIZE);
+ }
+
+#if FMSTR_CFG_BUS_WIDTH > 1U
+ /* even sizes only */
+ if(sz & 0x1)
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_INVSIZE);
+ }
+#endif
+
+#if FMSTR_USE_TSA && FMSTR_USE_TSA_SAFETY
+ if(!FMSTR_CheckTsaSpace(pcm_pScopeVarAddr[i], (FMSTR_SIZE8) sz, 0U))
+ {
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_EACCESS);
+ }
+#endif
+
+ }
+
+ /* activate scope */
+ pcm_nScopeVarCount = nVarCnt;
+
+ /* return just a status */
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling READSCOPE command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_ReadScope(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_U8 i;
+
+ if(!pcm_nScopeVarCount)
+ {
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_NOTINIT);
+ }
+
+ /* success */
+ pMessageIO = FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STS_OK);
+
+ for (i=0U; i 0U)
+ {
+ /* add padding bytes */
+ while(!(pcm_wJtagTxCtr & 4U))
+ {
+ pcm_wJtagTxData = (pcm_wJtagTxData << 8U) | 0xffU;
+ pcm_wJtagTxCtr++;
+ }
+
+ /* send the word just completed */
+ FMSTR_JTAG_PUTDWORD(pcm_wJtagTxData);
+
+ /* done, bTxActive will be deactivated next time */
+ pcm_wJtagTxCtr = 0U;
+ }
+#endif
+ /* transmission finished, start listening again */
+ else
+ {
+ /* when SCI TX buffering is enabled, we must first wait until all
+ characters are physically transmitted (before disabling transmitter) */
+#if FMSTR_USE_SCI && FMSTR_SCI_HAS_TXQUEUE
+ pcm_wFlags.flg.bTxWaitTC = 1;
+
+ /* wait for SCI TC interrupt */
+ #if FMSTR_SHORT_INTR || FMSTR_LONG_INTR
+ FMSTR_SCI_ETCI();
+ #endif
+#else
+ /* start listening immediatelly */
+ FMSTR_Listen();
+#endif
+ }
+}
+
+
+/**************************************************************************//*!
+*
+* @brief Handle received character
+*
+* @param nRxChar The character to be processed
+*
+* Handle the character received and -if the message is complete- call the
+* protocol decode routine.
+*
+******************************************************************************/
+
+static void FMSTR_Rx(FMSTR_BCHR nRxChar)
+{
+ /* first, handle the replicated SOB characters */
+ if(nRxChar == FMSTR_SOB)
+ {
+ /* this is the 2nd byte of replicated SOB char */
+ if(pcm_wFlags.flg.bRxLastCharSOB)
+ {
+ /* join the two SOBs into one 0x2b character and continue processing */
+ pcm_wFlags.flg.bRxLastCharSOB = 0U;
+ }
+ /* this is either the first byte of replicated SOB or a */
+ /* real Start-of-Block mark - we will decide next time in FMSTR_Rx */
+ else
+ {
+ pcm_wFlags.flg.bRxLastCharSOB = 1U;
+ return;
+ }
+ }
+
+ /* we have got a common character preceeded by the SOB - */
+ /* this is the command code! */
+ if(pcm_wFlags.flg.bRxLastCharSOB)
+ {
+ /* reset reciving process */
+ pcm_pRxBuff = pcm_pCommBuffer;
+ *pcm_pRxBuff++ = nRxChar;
+
+ /* start computing the checksum */
+ pcm_nRxCheckSum = nRxChar;
+ pcm_nRxTodo = 0U;
+
+ /* fast command? */
+ if((nRxChar & FMSTR_FASTCMD) == FMSTR_FASTCMD)
+ {
+ /* there will be no length information */
+ pcm_wFlags.flg.bRxMsgLengthNext = 0U;
+ /* as it is encoded in the command byte directly */
+ pcm_nRxTodo = (FMSTR_SIZE8)
+ (((((FMSTR_SIZE8)nRxChar) & FMSTR_FASTCMD_DATALEN_MASK) >> FMSTR_FASTCMD_DATALEN_SHIFT) + 1U);
+ }
+ /* standard command */
+ else
+ {
+ /* the message length will come in next byte */
+ pcm_wFlags.flg.bRxMsgLengthNext = 1U;
+ }
+
+ /* command code stored & processed */
+ pcm_wFlags.flg.bRxLastCharSOB = 0U;
+ return;
+ }
+
+ /* we are waiting for the length byte */
+ if(pcm_wFlags.flg.bRxMsgLengthNext)
+ {
+ /* this byte, total data length and the checksum */
+ pcm_nRxTodo = (FMSTR_SIZE8) (1U + ((FMSTR_SIZE8)nRxChar) + 1U);
+ /* now read the data bytes */
+ pcm_wFlags.flg.bRxMsgLengthNext = 0U;
+
+ }
+
+ /* waiting for a data byte? */
+ if(pcm_nRxTodo)
+ {
+ /* add this byte to checksum */
+ pcm_nRxCheckSum += nRxChar;
+
+ /* was it the last byte of the message (checksum)? */
+ if(!--pcm_nRxTodo)
+ {
+ /* receive buffer overflow? */
+ if(pcm_pRxBuff == NULL)
+ {
+ FMSTR_SendError(FMSTR_STC_CMDTOOLONG);
+ }
+ /* checksum error? */
+ else if((pcm_nRxCheckSum & 0xffU) != 0U)
+ {
+ FMSTR_SendError(FMSTR_STC_CMDCSERR);
+ }
+ /* message is okay */
+ else
+ {
+ /* do decode now! */
+ FMSTR_ProtocolDecoder(pcm_pCommBuffer);
+ }
+ }
+ /* not the last character yet */
+ else
+ {
+ /* is there still a space in the buffer? */
+ if(pcm_pRxBuff)
+ {
+ /*lint -e{946} pointer arithmetic is okay here (same array) */
+ if(pcm_pRxBuff < (pcm_pCommBuffer + FMSTR_COMM_BUFFER_SIZE))
+ {
+ /* store byte */
+ *pcm_pRxBuff++ = nRxChar;
+ }
+ /* buffer is full! */
+ else
+ {
+ /* NULL rx pointer means buffer overflow - but we still need */
+ /* to receive all message characters (for the single-wire mode) */
+ /* so keep "receiving" - but throw away all characters from now */
+ pcm_pRxBuff = NULL;
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+*
+* @brief Routine to quick-receive a character (put to a queue only)
+*
+* This function puts received character into a queue and exits as soon as possible.
+*
+*******************************************************************************/
+
+#if FMSTR_SHORT_INTR
+
+static void FMSTR_RxQueue(FMSTR_BCHR nRxChar)
+{
+ /* future value of write pointer */
+ FMSTR_BPTR wpnext = pcm_pRQueueWP + 1;
+
+ /*lint -e{946} pointer arithmetic is okay here (same array) */
+ if(wpnext >= (pcm_pRQueueBuffer + FMSTR_COMM_RQUEUE_SIZE))
+ {
+ wpnext = pcm_pRQueueBuffer;
+ }
+
+ /* any space in queue? */
+ if(wpnext != pcm_pRQueueRP)
+ {
+ *pcm_pRQueueWP = (FMSTR_U8) nRxChar;
+ pcm_pRQueueWP = wpnext;
+ }
+}
+
+#endif /* FMSTR_SHORT_INTR */
+
+/*******************************************************************************
+*
+* @brief Late processing of queued characters
+*
+* This function takes the queued characters and calls FMSTR_Rx() for each of them,
+* just like as the characters would be received from SCI one by one.
+*
+*******************************************************************************/
+
+#if FMSTR_SHORT_INTR
+
+static void FMSTR_RxDequeue(void)
+{
+ FMSTR_BCHR nChar = 0U;
+
+ /* get all queued characters */
+ while(pcm_pRQueueRP != pcm_pRQueueWP)
+ {
+ nChar = *pcm_pRQueueRP++;
+
+ /*lint -e{946} pointer arithmetic is okay here (same array) */
+ if(pcm_pRQueueRP >= (pcm_pRQueueBuffer + FMSTR_COMM_RQUEUE_SIZE))
+ {
+ pcm_pRQueueRP = pcm_pRQueueBuffer;
+ }
+
+ /* emulate the SCI receive event */
+ if(!pcm_wFlags.flg.bTxActive)
+ {
+ FMSTR_Rx(nChar);
+ }
+ }
+}
+
+#endif /* FMSTR_SHORT_INTR */
+
+/**************************************************************************//*!
+*
+* @brief Handle SCI communication (both TX and RX)
+*
+* This function checks the SCI flags and calls the Rx and/or Tx functions
+*
+* @note This function can be called either from SCI ISR or from the polling routine
+*
+******************************************************************************/
+
+#if FMSTR_USE_SCI
+
+void FMSTR_ProcessSCI(void)
+{
+ /* read & clear status */
+ FMSTR_SCISR wSciSR = FMSTR_SCI_RDCLRSR();
+
+ /* transmitter active and empty? */
+ if (pcm_wFlags.flg.bTxActive)
+ {
+ /* able to accept another character? */
+ if(wSciSR & FMSTR_SCISR_TDRE)
+ {
+ FMSTR_Tx();
+ }
+
+ /* read-out and ignore any received character (loopback) */
+ if(wSciSR & FMSTR_SCISR_RDRF)
+ {
+ /*lint -esym(550, nRxChar) */
+ volatile FMSTR_U16 nRxChar;
+ nRxChar = FMSTR_SCI_GETCHAR();
+ }
+ }
+ /* transmitter not active, able to receive */
+ else
+ {
+ /* data byte received? */
+ if (wSciSR & FMSTR_SCISR_RDRF)
+ {
+ FMSTR_BCHR nRxChar = 0U;
+ nRxChar = (FMSTR_BCHR) FMSTR_SCI_GETCHAR();
+
+ FMSTR_Rx(nRxChar);
+ // FMSTR_Tx();
+ }
+ }
+}
+
+#endif
+
+/**************************************************************************//*!
+*
+* @brief Handle JTAG communication (both TX and RX)
+*
+* This function checks the JTAG flags and calls the Rx and/or Tx functions
+*
+* @note This function can be called either from JTAG ISR or from the polling routine
+*
+******************************************************************************/
+
+#if FMSTR_USE_JTAG
+
+void FMSTR_ProcessJTAG(void)
+{
+ /* read & clear status */
+ register FMSTR_U16 wJtagSR = FMSTR_JTAG_GETSR();
+
+ /* transmitter active? */
+ if (pcm_wFlags.flg.bTxActive)
+ {
+ /* able to transmit a new character? (TX must be empty = read-out by PC) */
+ if(!(wJtagSR & FMSTR_JTAG_OTXRXSR_TDF))
+ {
+
+#if FMSTR_USE_JTAG_TXFIX
+ /* if TDF bit is useless due to silicon bug, use the RX flag */
+ /* instead (PC sends us a dummy word to kick the RX flag on) */
+ if(wJtagSR & FMSTR_JTAG_OTXRXSR_RDF)
+#endif
+ {
+ /* send one byte always */
+ FMSTR_Tx();
+
+ /* try to fill-up the full 32bit JTAG word */
+ while(pcm_wFlags.flg.bTxActive && pcm_wJtagTxCtr)
+ {
+ FMSTR_Tx();
+ }
+ }
+ }
+
+ /* ignore (read-out) the JTAG-received word */
+ if(wJtagSR & FMSTR_JTAG_OTXRXSR_RDF)
+ {
+ /*lint -esym(550, nRxWord) */
+ volatile FMSTR_U16 nRxWord;
+ nRxWord = FMSTR_JTAG_GETWORD();
+ }
+ }
+ /* transmitter not active */
+ else
+ {
+ /* JTAG 32bit word (four bytes) received? */
+ if(wJtagSR & FMSTR_JTAG_OTXRXSR_RDF)
+ {
+ register FMSTR_U32 nRxDWord;
+ FMSTR_INDEX i;
+
+ nRxDWord = FMSTR_JTAG_GETDWORD();
+
+ /* process all bytes, MSB first */
+ for(i=0; i<4; i++)
+ {
+#if FMSTR_SHORT_INTR
+ FMSTR_RxQueue((FMSTR_BCHR)((nRxDWord >> 24U) & 0xffU));
+
+#else
+ FMSTR_Rx((FMSTR_BCHR)((nRxDWord >> 24U) & 0xffU));
+
+ /* ignore the rest if previous bytes triggered a transmission */
+ /* (i.e. the packet was complete and only filled-up to 32bit word) */
+ if(pcm_wFlags.flg.bTxActive)
+ {
+ break;
+ }
+#endif
+ /* next byte of 32bit word */
+ nRxDWord = nRxDWord << 8;
+ }
+ }
+ }
+}
+
+#endif
+
+/*******************************************************************************
+*
+* @brief API: Main "Polling" call from the application main loop
+*
+* This function either handles all the SCI communictaion (polling-only mode =
+* FMSTR_POLL_DRIVEN) or decodes messages received on the background by SCI interrupt
+* (short-interrupt mode = FMSTR_SHORT_INTR).
+*
+* In the JTAG interrupt-driven mode (both short and long), this function also checks
+* if setting the JTAG RIE bit failed recently. This may happen because of the
+* RIE is held low by the EONCE hardware until the EONCE is first accessed from host.
+* FMSTR_Init (->FMSTR_Listen) is often called while the PC-side FreeMASTER is still
+* turned off. So really, the JTAG is not enabled by this time and RIE bit is not set.
+* This problem is detected (see how bJtagRIEPending is set above in FSMTR_Listen)
+* and it is tried to be fixed periodically here in FMSTR_Poll.
+*
+*******************************************************************************/
+
+void FMSTR_Poll(void)
+{
+ FMSTR_ProcessSCI();
+}
+
+#else /* FMSTR_USE_SCI || FMSTR_USE_JTAG */
+
+/* Empty implementation of communication functions
+
+ Without a SCI and JTAG the FreeMASTER driver still passes the compilation,
+ but no communication is supported. The user may imlement his own communication
+ protocol and use FreeMASTER by calling FMSTR_ProtocolDecoder and
+ overriding the FMSTR_SendResponse calls
+*/
+
+void FMSTR_SendResponse(FMSTR_BPTR pResponse, FMSTR_SIZE8 nLength)
+{
+ FMSTR_UNUSED(pResponse);
+ FMSTR_UNUSED(nLength);
+}
+
+void FMSTR_Poll(void)
+{
+}
+
+/*lint -efile(766, PE_freemaster_protocol.h) include file is not used in this case */
+
+#endif /* FMSTR_USE_SCI || FMSTR_USE_JTAG */
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_sfio.c b/Projects/epwm_test/Freemaster/PE_freemaster_sfio.c
new file mode 100644
index 0000000..5fc4643
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_sfio.c
@@ -0,0 +1,165 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_sfio.c
+*
+* @brief FreeMASTER SFIO (Matlab/Simulink interface) encapsulation handler
+*
+* @version 1.0.2.0
+*
+* @date Aug-17-2006
+*
+*******************************************************************************
+*
+* This file contains the SFIO communication handler and enables the SFIO tool
+* to run over FreeMASTER. For more information, see Freescale SFIO documentation.
+*
+*******************************************************************************/
+
+#include "PE_freemaster.h"
+#include "PE_freemaster_private.h"
+#include "PE_freemaster_protocol.h"
+
+#if FMSTR_USE_SFIO
+
+/* the sfiolib needs to be added to the project */
+#include "sfiolib.h"
+
+/***********************************
+* local variables
+***********************************/
+
+static FMSTR_U8 pcm_nSfioRespLen;
+
+/* recorder runtime flags */
+static volatile union
+{
+ FMSTR_FLAGS all;
+
+ struct
+ {
+ unsigned bEvenRun : 1; /* last command executed was the even one */
+ unsigned bLastOK : 1; /* last command executed properly */
+ } flg;
+
+} pcm_wSfioFlags;
+
+/**************************************************************************//*!
+*
+* @brief Initialization of SFIO communication layer
+*
+******************************************************************************/
+
+void FMSTR_InitSfio(void)
+{
+ pcm_wSfioFlags.all = 0;
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling SFIOFRAME (even and odd) commands
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @note This function handles the SFIO (Matlab/Simulink Interface) command
+* encapsulated into FreeMASTER protocol. It emulates the SFIO serial
+* char-by-char communication.
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_SfioFrame(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_U8 i, nFrameLen, nByte;
+ SFIO_U16 nRet = 0;
+
+ /* get command and remember if it was even/odd */
+ pMessageIO = FMSTR_ValueFromBuffer8(&nByte, pMessageIO);
+ pcm_wSfioFlags.flg.bEvenRun = (nByte & 1) ? 0 : 1;
+ pcm_wSfioFlags.flg.bLastOK = 0;
+
+ /* get data length */
+ pMessageIO = FMSTR_ValueFromBuffer8(&nFrameLen, pMessageIO);
+
+ /* feed the SFIO engine byte-by-byte */
+ for(i=0; nRet == 0 && i FMSTR_COMM_BUFFER_SIZE)
+ return FMSTR_ConstToBuffer8(pResponse, FMSTR_STC_RSPBUFFOVF);
+
+ /* remember this command had executed properly */
+ pcm_nSfioRespLen = (FMSTR_U8) nRet;
+ pcm_wSfioFlags.flg.bLastOK = 1;
+
+ /* SFIO response to return */
+ pResponse = FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK | FMSTR_STSF_VARLEN);
+ pResponse = FMSTR_ValueToBuffer8(pResponse, pcm_nSfioRespLen);
+ return FMSTR_CopyToBuffer(pResponse, (FMSTR_ADDR) SFIO_GetOutputBuffer(), pcm_nSfioRespLen);
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling SFIOGETRESP (even and odd) commands
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @note This function handles the retried request for the last SFIO response.
+* PC may request this retry when the last frame execution took too long
+* (e.g. due to breakpoint) but is still finished properly. The original
+* SFIOFRAME command returned timeout, so the PC will use SFIOGETRESP
+* to finish data.
+*
+* The even/odd matching is here to have some dgree of robustness for
+* a case when SFIOFRAME packet gets lost without ever reaching SFIO engine.
+* Without any checking, the SFIOGETRESP would just blindly return the
+* pre-last result and would definietelly cause Simulink problems.
+* Having the check implemented, the PC can determine the even/odd mismatch
+* and may re-send the last SFIOFRAME command.
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_SfioGetResp(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_U8 nByte;
+
+ /* get command and determine if it is even/odd */
+ FMSTR_ValueFromBuffer8(&nByte, pMessageIO);
+
+ /* last command must have been finished propely */
+ if(!pcm_wSfioFlags.flg.bLastOK)
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_SFIOERR);
+
+ /* only respond to "matching" request (even to even, odd to odd) */
+ if(nByte & 1)
+ {
+ if(pcm_wSfioFlags.flg.bEvenRun)
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_SFIOUNMATCH);
+ }
+ else
+ {
+ if(!pcm_wSfioFlags.flg.bEvenRun)
+ return FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STC_SFIOUNMATCH);
+ }
+
+ /* SFIO response to return */
+ pMessageIO = FMSTR_ConstToBuffer8(pMessageIO, FMSTR_STS_OK | FMSTR_STSF_VARLEN);
+ pMessageIO = FMSTR_ValueToBuffer8(pMessageIO, pcm_nSfioRespLen);
+ return FMSTR_CopyToBuffer(pMessageIO, (FMSTR_ADDR) SFIO_GetOutputBuffer(), pcm_nSfioRespLen);
+}
+
+#endif /* FMSTR_USE_SFIO */
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_tsa.c b/Projects/epwm_test/Freemaster/PE_freemaster_tsa.c
new file mode 100644
index 0000000..ba98ca8
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_tsa.c
@@ -0,0 +1,321 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_tsa.c
+*
+* @brief FreeMASTER TSA implementation
+*
+* @version 1.0.9.0
+*
+* @date Oct-22-2007
+*
+*******************************************************************************
+*
+* This file implements a new FreeMASTER feature called Targer-side address
+* translation.
+*
+*******************************************************************************/
+
+#include "PE_freemaster.h"
+#include "PE_freemaster_private.h"
+#include "PE_freemaster_protocol.h"
+
+#if FMSTR_USE_TSA
+
+/**************************************************************************//*!
+*
+* @brief TSA Initialization
+*
+******************************************************************************/
+
+void FMSTR_InitTsa(void)
+{
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling GETTSAINFO and GETTSAINFO_EX command
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_GetTsaInfo(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ const FMSTR_TSA_ENTRY* pTbl;
+ FMSTR_TSA_TINDEX nTblIndex;
+ FMSTR_TSA_TSIZE nTblSize = 0U;
+ FMSTR_ADDR tmpAddr;
+ FMSTR_U16 tmp16;
+
+ /* get index of table the PC is requesting */
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 2U);
+ pMessageIO = FMSTR_ValueFromBuffer16(&nTblIndex, pMessageIO);
+
+ /* TSA flags */
+ tmp16 = FMSTR_TSA_VERSION | FMSTR_TSA_FLAGS;
+
+ /* sizeof TSA table entry items */
+ /*lint -e{506,774} constant value boolean */
+ if((sizeof(FMSTR_TSA_ENTRY)/4U) == 4U)
+ {
+ tmp16 |= FMSTR_TSA_INFO_32BIT; /* 32bit TSA entries */
+ }
+
+ /* get the table (or NULL if no table on given index) */
+ pTbl = FMSTR_TsaGetTable(nTblIndex, &nTblSize);
+
+ /* success, flags */
+ pResponse = FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+ pResponse = FMSTR_ValueToBuffer16(pResponse, tmp16);
+
+ /* table size in bytes */
+ nTblSize *= FMSTR_CFG_BUS_WIDTH;
+ pResponse = FMSTR_ValueToBuffer16(pResponse, nTblSize);
+
+ /* table address */
+ FMSTR_PTR2ADDR(tmpAddr, pTbl);
+ return FMSTR_AddressToBuffer(pResponse, tmpAddr);
+}
+
+/**************************************************************************//*!
+*
+* @brief Private inline implementation of "strlen"
+*
+******************************************************************************/
+
+FMSTR_U16 FMSTR_StrLen(FMSTR_ADDR nAddr)
+{
+ const FMSTR_U8* pStr;
+ FMSTR_U16 nLen = 0U;
+
+ #ifdef __HCS12X__
+ /* convert from logical to global if needed */
+ nAddr = FMSTR_FixHcs12xAddr(nAddr);
+ #endif
+
+ /*lint -e{923} casting address value to pointer */
+ pStr = (const FMSTR_U8*) nAddr;
+
+ while(*pStr++)
+ {
+ nLen++;
+ }
+
+ return nLen;
+}
+
+/**************************************************************************//*!
+*
+* @brief Handling GETSTRLEN and GETSTRLEN_EX commands
+*
+* @param pMessageIO - original command (in) and response buffer (out)
+*
+* @return As all command handlers, the return value should be the buffer
+* pointer where the response output finished (except checksum)
+*
+******************************************************************************/
+
+FMSTR_BPTR FMSTR_GetStringLen(FMSTR_BPTR pMessageIO)
+{
+ FMSTR_BPTR pResponse = pMessageIO;
+ FMSTR_ADDR nAddr;
+ FMSTR_U16 nLen = 0U;
+
+ pMessageIO = FMSTR_SkipInBuffer(pMessageIO, 1U);
+ pMessageIO = FMSTR_AddressFromBuffer(&nAddr, pMessageIO);
+
+ nLen = FMSTR_StrLen(nAddr);
+
+ /* return strign size in bytes (even on 16bit DSP) */
+ nLen *= FMSTR_CFG_BUS_WIDTH ;
+
+ pResponse = FMSTR_ConstToBuffer8(pResponse, FMSTR_STS_OK);
+ return FMSTR_ValueToBuffer16(pResponse, nLen);
+}
+
+/**************************************************************************//*!
+*
+* @brief Helper (inline) function for TSA memory region check
+*
+* @param nAddrUser - address of region to be checked
+* @param nSizeUser - size of region to be checked
+* @param nAddrSafe - address of known "safe" region
+* @param wSizeSafe - size of safe region
+*
+* @return This function returns non-zero if given user space is safe
+* (i.e. it lies in given safe space)
+*
+******************************************************************************/
+
+#if defined(FMSTR_PLATFORM_56F8xxx) || defined(FMSTR_PLATFORM_56F8xx)
+/* make inline */
+inline FMSTR_BOOL FMSTR_CheckMemSpace(FMSTR_ADDR nAddrUser, FMSTR_SIZE8 nSizeUser,
+ FMSTR_ADDR nAddrSafe, FMSTR_SIZE wSizeSafe);
+
+inline
+#else
+/* declare function prototype */
+static FMSTR_BOOL FMSTR_CheckMemSpace(FMSTR_ADDR nAddrUser, FMSTR_SIZE8 nSizeUser,
+ FMSTR_ADDR nAddrSafe, FMSTR_SIZE wSizeSafe);
+
+static
+#endif
+
+FMSTR_BOOL FMSTR_CheckMemSpace(FMSTR_ADDR nAddrUser, FMSTR_SIZE8 nSizeUser,
+ FMSTR_ADDR nAddrSafe, FMSTR_SIZE wSizeSafe)
+{
+ FMSTR_BOOL bRet = FMSTR_FALSE;
+
+ #ifdef __HCS12X__
+ /* convert from logical to global if needed */
+ nAddrUser = FMSTR_FixHcs12xAddr(nAddrUser);
+ nAddrSafe = FMSTR_FixHcs12xAddr(nAddrSafe);
+ #endif
+
+ if(nAddrUser >= nAddrSafe)
+ {
+ bRet = (FMSTR_BOOL)
+ (((nAddrUser + nSizeUser) <= (nAddrSafe + wSizeSafe)) ? FMSTR_TRUE : FMSTR_FALSE);
+ }
+
+ return bRet;
+}
+
+/**************************************************************************//*!
+*
+* @brief Check wether given memory region is "safe" (covered by TSA)
+*
+* @param dwAddr - address of the memory to be checked
+* @param nSize - size of the memory to be checked
+* @param bWriteAccess - write access is required
+*
+* @return This function returns non-zero if user space is safe
+*
+******************************************************************************/
+
+FMSTR_BOOL FMSTR_CheckTsaSpace(FMSTR_ADDR dwAddr, FMSTR_SIZE8 nSize, FMSTR_BOOL bWriteAccess)
+{
+ const FMSTR_TSA_ENTRY* pte;
+ FMSTR_TSA_TINDEX nTableIndex;
+ FMSTR_TSA_TSIZE i, cnt;
+ FMSTR_SIZE nInfo;
+
+#if FMSTR_CFG_BUS_WIDTH >= 2U
+ /* TSA tables use sizeof() operator which returns size in "bus-widths" (e.g. 56F8xx) */
+ nSize = (nSize + 1) / FMSTR_CFG_BUS_WIDTH;
+#endif
+
+ /* to be as fast as possible during normal opearaion,
+ check variable entries in all tables first */
+ for(nTableIndex=0U; (pte=FMSTR_TsaGetTable(nTableIndex, &cnt)) != NULL; nTableIndex++)
+ {
+ /* number of items in a table */
+ cnt /= (FMSTR_TSA_TSIZE) sizeof(FMSTR_TSA_ENTRY);
+
+ /* all table entries */
+ for(i=0U; iinfo.n;
+
+ /* variable entry only (also check read-write flag) */
+ if((nInfo & FMSTR_TSA_INFO_VAR_FLAG) && (!bWriteAccess || (nInfo & FMSTR_TSA_INFO_RWV_FLAG)))
+ {
+ /* need to take the larger of the two in union (will be optimized by compiler anyway) */
+ /*lint -e{506,774} condition always true/false */
+ if(sizeof(pte->addr.p) < sizeof(pte->addr.n))
+ {
+ if(FMSTR_CheckMemSpace(dwAddr, nSize, (FMSTR_ADDR) pte->addr.n, (FMSTR_SIZE) (nInfo >> 2)))
+ {
+ return FMSTR_TRUE; /* access granted! */
+ }
+ }
+ else
+ {
+ /*lint -e{923} casting pointer to long (on some architectures) */
+ if(FMSTR_CheckMemSpace(dwAddr, nSize, (FMSTR_ADDR) pte->addr.p, (FMSTR_SIZE) (nInfo >> 2)))
+ {
+ return FMSTR_TRUE; /* access granted! */
+ }
+ }
+ }
+
+ pte++;
+ }
+ }
+
+ /* no more writeable memory chunks available */
+ if(bWriteAccess)
+ {
+ return FMSTR_FALSE;
+ }
+
+ /* allow reading of recorder buffer */
+#if FMSTR_USE_RECORDER
+ if(FMSTR_IsInRecBuffer(dwAddr, nSize))
+ {
+ return FMSTR_TRUE;
+ }
+#endif
+
+ /* allow reading of any C-constant string referenced in TSA tables */
+ for(nTableIndex=0U; (pte=FMSTR_TsaGetTable(nTableIndex, &cnt)) != NULL; nTableIndex++)
+ {
+ FMSTR_ADDR tmpAddr;
+
+ /* allow reading of the TSA table itself */
+ FMSTR_PTR2ADDR(tmpAddr, pte);
+ if(FMSTR_CheckMemSpace(dwAddr, nSize, tmpAddr, cnt))
+ {
+ return FMSTR_TRUE;
+ }
+
+ /* number of items in a table */
+ cnt /= (FMSTR_TSA_TSIZE) sizeof(FMSTR_TSA_ENTRY);
+
+ /* all table entries */
+ for(i=0U; iname.p);
+ if(pte->name.p)
+ {
+ if(FMSTR_CheckMemSpace(dwAddr, nSize, tmpAddr, FMSTR_StrLen(tmpAddr)))
+ {
+ return FMSTR_TRUE;
+ }
+ }
+
+ FMSTR_PTR2ADDR(tmpAddr, pte->type.p);
+ if(pte->type.p)
+ {
+ if(FMSTR_CheckMemSpace(dwAddr, nSize, tmpAddr, FMSTR_StrLen(tmpAddr)))
+ {
+ return FMSTR_TRUE;
+ }
+ }
+
+ pte++;
+ }
+ }
+
+ /* no valid TSA entry found => not-safe to access the memory */
+ return FMSTR_FALSE;
+}
+
+#else /* FMSTR_USE_TSA */
+
+/*lint -efile(766, PE_freemaster_protocol.h) include file is not used in this case */
+
+#endif /* FMSTR_USE_TSA */
+
diff --git a/Projects/epwm_test/Freemaster/PE_freemaster_tsa.h b/Projects/epwm_test/Freemaster/PE_freemaster_tsa.h
new file mode 100644
index 0000000..e9823a6
--- /dev/null
+++ b/Projects/epwm_test/Freemaster/PE_freemaster_tsa.h
@@ -0,0 +1,167 @@
+/******************************************************************************
+*
+* Freescale Semiconductor Inc.
+* (c) Copyright 2004-2006 Freescale Semiconductor, Inc.
+* (c) Copyright 2001-2004 Motorola, Inc.
+* ALL RIGHTS RESERVED.
+*
+****************************************************************************//*!
+*
+* @file PE_freemaster_tsa.h
+*
+* @brief FreeMASTER Driver TSA feature
+*
+* @version 1.0.6.0
+*
+* @date Apr-11-2007
+*
+*******************************************************************************/
+
+#ifndef __FREEMASTER_TSA_H
+#define __FREEMASTER_TSA_H
+
+#include "PE_freemaster_cfg.h"
+
+/*****************************************************************************
+ Target-side Address translation structures and macros
+******************************************************************************/
+
+/* current TSA version */
+#define FMSTR_TSA_VERSION 2U
+
+/* TSA flags carried in TSA_ENTRY.info (except the first entry in table) */
+#define FMSTR_TSA_INFO_ENTRYTYPE_MASK 0x0003U /* flags reserved for TSA_ENTRY use */
+#define FMSTR_TSA_INFO_STRUCT 0x0000U /* ENTRYTYPE: structure parent type */
+#define FMSTR_TSA_INFO_RO_VAR 0x0001U /* ENTRYTYPE: read-only variable */
+#define FMSTR_TSA_INFO_MEMBER 0x0002U /* ENTRYTYPE: structure member */
+#define FMSTR_TSA_INFO_RW_VAR 0x0003U /* ENTRYTYPE: read-write variable */
+#define FMSTR_TSA_INFO_VAR_FLAG 0x0001U /* ENTRYTYPE: FLAG: any variable */
+#define FMSTR_TSA_INFO_RWV_FLAG 0x0002U /* ENTRYTYPE: FLAG: R/W access */
+
+/* TSA table index and size (both unsigned, at least 16 bit wide) */
+typedef FMSTR_SIZE FMSTR_TSA_TINDEX;
+typedef FMSTR_SIZE FMSTR_TSA_TSIZE;
+
+/* pointer types used in TSA tables can be overridden in PE_freemaster.h */
+/* (this is why macros are used instead of typedefs) */
+#ifndef FMSTR_TSATBL_STRPTR
+#define FMSTR_TSATBL_STRPTR const char*
+#endif
+#ifndef FMSTR_TSATBL_STRPTR_CAST
+#define FMSTR_TSATBL_STRPTR_CAST(x) ((FMSTR_TSATBL_STRPTR)(x))
+#endif
+#ifndef FMSTR_TSATBL_VOIDPTR
+#define FMSTR_TSATBL_VOIDPTR const void*
+#endif
+#ifndef FMSTR_TSATBL_VOIDPTR_CAST
+#define FMSTR_TSATBL_VOIDPTR_CAST(x) ((FMSTR_TSATBL_VOIDPTR)(x))
+#endif
+
+/* TSA table entry. The unions inside assures variables sized enough to */
+/* accomodate both the C-pointer and the user-requested size (FMSTR_ADDR) */
+typedef struct
+{
+ union { FMSTR_TSATBL_STRPTR p; FMSTR_ADDR n; } name;
+ union { FMSTR_TSATBL_STRPTR p; FMSTR_ADDR n; } type;
+ union { FMSTR_TSATBL_VOIDPTR p; FMSTR_ADDR n; } addr;
+ union { FMSTR_TSATBL_VOIDPTR p; FMSTR_ADDR n; } info;
+} FMSTR_TSA_ENTRY;
+
+/* TSA table allocation modifier */
+#ifndef FMSTR_USE_TSA_INROM
+#define FMSTR_USE_TSA_INROM 0
+#endif
+#if FMSTR_USE_TSA_INROM
+#define FMSTR_TSA_CDECL const
+#else
+#define FMSTR_TSA_CDECL
+#endif
+
+/*//////////////////////////////////////////////// */
+/* single table-building macros */
+
+#define FMSTR_TSA_FUNC(id) FMSTR_TsaGetTable_##id
+#define FMSTR_TSA_FUNC_PROTO(id) const FMSTR_TSA_ENTRY* FMSTR_TSA_FUNC(id) (FMSTR_TSA_TSIZE* pTableSize)
+
+#define FMSTR_TSA_TABLE_BEGIN(id) \
+ FMSTR_TSA_FUNC_PROTO(id); \
+ FMSTR_TSA_FUNC_PROTO(id) { \
+ static FMSTR_TSA_CDECL FMSTR_TSA_ENTRY fmstr_tsatable[] = {
+
+/* entry info */
+#define FMSTR_TSA_INFO1(elem, flags) FMSTR_TSATBL_VOIDPTR_CAST(((sizeof(elem))<<2)|(flags))
+#define FMSTR_TSA_INFO2(size, flags) FMSTR_TSATBL_VOIDPTR_CAST(((size)<<2)|(flags))
+
+#define FMSTR_TSA_STRUCT(name) \
+ { FMSTR_TSATBL_STRPTR_CAST(#name), FMSTR_TSATBL_STRPTR_CAST(NULL), FMSTR_TSATBL_VOIDPTR_CAST(NULL), FMSTR_TSA_INFO1(name, FMSTR_TSA_INFO_STRUCT) },
+
+#define FMSTR_TSA_MEMBER(parenttype,name,type) \
+ { FMSTR_TSATBL_STRPTR_CAST(#name), FMSTR_TSATBL_STRPTR_CAST(type), FMSTR_TSATBL_VOIDPTR_CAST(&((parenttype*)0)->name), FMSTR_TSA_INFO1(((parenttype*)0)->name, FMSTR_TSA_INFO_MEMBER) },
+
+#define FMSTR_TSA_RO_VAR(name,type) \
+ { FMSTR_TSATBL_STRPTR_CAST(#name), FMSTR_TSATBL_STRPTR_CAST(type), FMSTR_TSATBL_VOIDPTR_CAST(&(name)), FMSTR_TSA_INFO1(name, FMSTR_TSA_INFO_RO_VAR) },
+
+#define FMSTR_TSA_RW_VAR(name,type) \
+ { FMSTR_TSATBL_STRPTR_CAST(#name), FMSTR_TSATBL_STRPTR_CAST(type), FMSTR_TSATBL_VOIDPTR_CAST(&(name)), FMSTR_TSA_INFO1(name, FMSTR_TSA_INFO_RW_VAR) },
+
+#define FMSTR_TSA_RO_MEM(name,type,addr,size) \
+ { FMSTR_TSATBL_STRPTR_CAST(#name), FMSTR_TSATBL_STRPTR_CAST(type), FMSTR_TSATBL_VOIDPTR_CAST(addr), FMSTR_TSA_INFO2(size, FMSTR_TSA_INFO_RO_VAR) },
+
+#define FMSTR_TSA_RW_MEM(name,type,addr,size) \
+ { FMSTR_TSATBL_STRPTR_CAST(#name), FMSTR_TSATBL_STRPTR_CAST(type), FMSTR_TSATBL_VOIDPTR_CAST(addr), FMSTR_TSA_INFO2(size, FMSTR_TSA_INFO_RW_VAR) },
+
+#define FMSTR_TSA_TABLE_END() }; \
+ if(pTableSize) *pTableSize = sizeof(fmstr_tsatable); \
+ return fmstr_tsatable; }
+
+/*///////////////////////////////////////////////////////////////////// */
+/* TSA "Base Types", all are implemented as a one-char strings */
+/* retrieved by PC and parsed according to the binary scheme */
+/* "111STTZZ" where TT=type[int,frac,fp,x] S=signed ZZ=size[1,2,4,8] */
+
+#define FMSTR_TSA_UINT8 "\xE0"
+#define FMSTR_TSA_UINT16 "\xE1"
+#define FMSTR_TSA_UINT32 "\xE2"
+#define FMSTR_TSA_UINT64 "\xE3"
+#define FMSTR_TSA_SINT8 "\xF0"
+#define FMSTR_TSA_SINT16 "\xF1"
+#define FMSTR_TSA_SINT32 "\xF2"
+#define FMSTR_TSA_SINT64 "\xF3"
+#define FMSTR_TSA_UFRAC16 "\xE5"
+#define FMSTR_TSA_UFRAC32 "\xE6"
+#define FMSTR_TSA_FRAC16 "\xF5"
+#define FMSTR_TSA_FRAC32 "\xF6"
+#define FMSTR_TSA_FLOAT "\xFA"
+#define FMSTR_TSA_DOUBLE "\xFB"
+
+/* macro used to describe "User Type" */
+#define FMSTR_TSA_USERTYPE(type) #type
+
+/* macro used to describe pure memory space */
+#define FMSTR_TSA_MEMORY NULL
+
+
+/*//////////////////////////////////////////////// */
+/* master TSA table-retrival building macros */
+
+#define FMSTR_TSA_TABLE_LIST_BEGIN() \
+ const FMSTR_TSA_ENTRY* FMSTR_TsaGetTable(FMSTR_TSA_TINDEX nTableIndex, FMSTR_TSA_TSIZE* pTableSize) {
+
+#define FMSTR_TSA_TABLE(id) \
+ if(!nTableIndex--) { \
+ FMSTR_TSA_FUNC_PROTO(id); \
+ return FMSTR_TSA_FUNC(id)(pTableSize); \
+ } else
+
+#define FMSTR_TSA_TABLE_LIST_END() \
+ { return NULL; } }
+
+/*****************************************************************************
+ Target-side Address translation functions
+******************************************************************************/
+
+/* master TSA table-retrival function */
+const FMSTR_TSA_ENTRY* FMSTR_TsaGetTable(FMSTR_TSA_TINDEX nTableIndex, FMSTR_TSA_TSIZE* pTableSize);
+
+#endif /* __FREEMASTER_TSA_H */
+
diff --git a/Projects/epwm_test/Start_rfm.pmp b/Projects/epwm_test/Start_rfm.pmp
new file mode 100644
index 0000000..81597d6
Binary files /dev/null and b/Projects/epwm_test/Start_rfm.pmp differ
diff --git a/Projects/epwm_test/epwm_test.c b/Projects/epwm_test/epwm_test.c
new file mode 100644
index 0000000..c3f8720
--- /dev/null
+++ b/Projects/epwm_test/epwm_test.c
@@ -0,0 +1,38 @@
+//###########################################################################
+//
+// FILE: epwm_test.c
+//
+
+//
+//
+//###########################################################################
+//
+
+//###########################################################################
+
+//
+// Included Files
+//
+#include "f28x_project.h"
+#include "init_perif.h"
+#include "frmmstr_run.h"
+#include "ExtEEPROM.h"
+
+
+void main(void)
+{
+
+ InitPerif();
+
+ for(;;)
+ {
+ asm (" NOP");
+ ExtEEPROM_run();
+ frmmstr_run();
+ }
+}
+
+
+//
+// End of file
+//
diff --git a/Projects/epwm_test/f2838x_headers_nonBIOS_cpu1.cmd b/Projects/epwm_test/f2838x_headers_nonBIOS_cpu1.cmd
new file mode 100644
index 0000000..475a56a
--- /dev/null
+++ b/Projects/epwm_test/f2838x_headers_nonBIOS_cpu1.cmd
@@ -0,0 +1,388 @@
+MEMORY
+{
+ PAGE 0: /* Program Memory */
+ PAGE 1: /* Data Memory */
+ ACCESSPROTECTION : origin = 0x0005F500, length = 0x00000040
+ ADCA : origin = 0x00007400, length = 0x00000080
+ ADCB : origin = 0x00007480, length = 0x00000080
+ ADCC : origin = 0x00007500, length = 0x00000080
+ ADCD : origin = 0x00007580, length = 0x00000080
+ ADCARESULT : origin = 0x00000B00, length = 0x00000018
+ ADCBRESULT : origin = 0x00000B20, length = 0x00000018
+ ADCCRESULT : origin = 0x00000B40, length = 0x00000018
+ ADCDRESULT : origin = 0x00000B60, length = 0x00000018
+ ANALOGSUBSYS : origin = 0x0005D700, length = 0x00000100
+ BGCRCCPU : origin = 0x00006340, length = 0x00000040
+ BGCRCCLA1 : origin = 0x00006380, length = 0x00000040
+ CANA : origin = 0x00048000, length = 0x00000200
+ CANB : origin = 0x0004A000, length = 0x00000200
+ CLA1 : origin = 0x00001400, length = 0x00000080
+ CLB1DATAEXCH : origin = 0x00003180, length = 0x00000080
+ CLB2DATAEXCH : origin = 0x00003380, length = 0x00000080
+ CLB3DATAEXCH : origin = 0x00003580, length = 0x00000080
+ CLB4DATAEXCH : origin = 0x00003780, length = 0x00000080
+ CLB5DATAEXCH : origin = 0x00003980, length = 0x00000080
+ CLB6DATAEXCH : origin = 0x00003B80, length = 0x00000080
+ CLB7DATAEXCH : origin = 0x00003D80, length = 0x00000080
+ CLB8DATAEXCH : origin = 0x00003F80, length = 0x00000080
+ CLB1LOGICCFG : origin = 0x00003000, length = 0x00000052
+ CLB2LOGICCFG : origin = 0x00003200, length = 0x00000052
+ CLB3LOGICCFG : origin = 0x00003400, length = 0x00000052
+ CLB4LOGICCFG : origin = 0x00003600, length = 0x00000052
+ CLB5LOGICCFG : origin = 0x00003800, length = 0x00000052
+ CLB6LOGICCFG : origin = 0x00003A00, length = 0x00000052
+ CLB7LOGICCFG : origin = 0x00003C00, length = 0x00000052
+ CLB8LOGICCFG : origin = 0x00003E00, length = 0x00000052
+ CLB1LOGICCTRL : origin = 0x00003100, length = 0x00000040
+ CLB2LOGICCTRL : origin = 0x00003300, length = 0x00000040
+ CLB3LOGICCTRL : origin = 0x00003500, length = 0x00000040
+ CLB4LOGICCTRL : origin = 0x00003700, length = 0x00000040
+ CLB5LOGICCTRL : origin = 0x00003900, length = 0x00000040
+ CLB6LOGICCTRL : origin = 0x00003B00, length = 0x00000040
+ CLB7LOGICCTRL : origin = 0x00003D00, length = 0x00000040
+ CLB8LOGICCTRL : origin = 0x00003F00, length = 0x00000040
+ CLBXBAR : origin = 0x00007A40, length = 0x00000040
+ CLKCFG : origin = 0x0005D200, length = 0x00000100
+ CMPSS1 : origin = 0x00005C80, length = 0x00000020
+ CMPSS2 : origin = 0x00005CA0, length = 0x00000020
+ CMPSS3 : origin = 0x00005CC0, length = 0x00000020
+ CMPSS4 : origin = 0x00005CE0, length = 0x00000020
+ CMPSS5 : origin = 0x00005D00, length = 0x00000020
+ CMPSS6 : origin = 0x00005D20, length = 0x00000020
+ CMPSS7 : origin = 0x00005D40, length = 0x00000020
+ CMPSS8 : origin = 0x00005D60, length = 0x00000020
+ CMCONF : origin = 0x0005DC00, length = 0x00000400
+ CPU1TOCMIPC : origin = 0x0005CE40, length = 0x00000026
+ CPU1TOCPU2IPC : origin = 0x0005CE00, length = 0x00000026
+ SYSPERIPHAC : origin = 0x0005D500, length = 0x00000200
+ CPUTIMER0 : origin = 0x00000C00, length = 0x00000008
+ CPUTIMER1 : origin = 0x00000C08, length = 0x00000008
+ CPUTIMER2 : origin = 0x00000C10, length = 0x00000008
+ CPUSYS : origin = 0x0005D300, length = 0x000000A0
+ DACA : origin = 0x00005C00, length = 0x00000008
+ DACB : origin = 0x00005C10, length = 0x00000008
+ DACC : origin = 0x00005C20, length = 0x00000008
+ DCC0 : origin = 0x0005E700, length = 0x00000038
+ DCC1 : origin = 0x0005E740, length = 0x00000038
+ DCC2 : origin = 0x0005E780, length = 0x00000038
+ DCSMCOMMON : origin = 0x0005F0C0, length = 0x00000020
+ DCSMZ1OTP : origin = 0x00078000, length = 0x00000020
+ DCSMZ1 : origin = 0x0005F000, length = 0x0000003E
+ DCSMZ2OTP : origin = 0x00078200, length = 0x00000020
+ DCSMZ2 : origin = 0x0005F080, length = 0x0000003E
+ DEVCFG : origin = 0x0005D000, length = 0x000001A0
+ DMACLASRCSEL : origin = 0x00007980, length = 0x0000001A
+ DMA : origin = 0x00001000, length = 0x00000200
+ ECAP1 : origin = 0x00005200, length = 0x00000020
+ ECAP2 : origin = 0x00005240, length = 0x00000020
+ ECAP3 : origin = 0x00005280, length = 0x00000020
+ ECAP4 : origin = 0x000052C0, length = 0x00000020
+ ECAP5 : origin = 0x00005300, length = 0x00000020
+ ECAP6 : origin = 0x00005340, length = 0x00000020
+ ECAP7 : origin = 0x00005380, length = 0x00000020
+ EMIF1CONFIG : origin = 0x0005F4C0, length = 0x00000020
+ EMIF2CONFIG : origin = 0x0005F4E0, length = 0x00000020
+ EMIF1 : origin = 0x00047000, length = 0x00000070
+ EMIF2 : origin = 0x00047800, length = 0x00000070
+ EPWM1 : origin = 0x00004000, length = 0x00000100
+ EPWM2 : origin = 0x00004100, length = 0x00000100
+ EPWM3 : origin = 0x00004200, length = 0x00000100
+ EPWM4 : origin = 0x00004300, length = 0x00000100
+ EPWM5 : origin = 0x00004400, length = 0x00000100
+ EPWM6 : origin = 0x00004500, length = 0x00000100
+ EPWM7 : origin = 0x00004600, length = 0x00000100
+ EPWM8 : origin = 0x00004700, length = 0x00000100
+ EPWM9 : origin = 0x00004800, length = 0x00000100
+ EPWM10 : origin = 0x00004900, length = 0x00000100
+ EPWM11 : origin = 0x00004A00, length = 0x00000100
+ EPWM12 : origin = 0x00004B00, length = 0x00000100
+ EPWM13 : origin = 0x00004C00, length = 0x00000100
+ EPWM14 : origin = 0x00004D00, length = 0x00000100
+ EPWM15 : origin = 0x00004E00, length = 0x00000100
+ EPWM16 : origin = 0x00004F00, length = 0x00000100
+ EPWMXBAR : origin = 0x00007A00, length = 0x00000040
+ EQEP1 : origin = 0x00005100, length = 0x00000040
+ EQEP2 : origin = 0x00005140, length = 0x00000040
+ EQEP3 : origin = 0x00005180, length = 0x00000040
+ ERADCOUNTER1 : origin = 0x0005E980, length = 0x00000010
+ ERADCOUNTER2 : origin = 0x0005E990, length = 0x00000010
+ ERADCOUNTER3 : origin = 0x0005E9A0, length = 0x00000010
+ ERADCOUNTER4 : origin = 0x0005E9B0, length = 0x00000010
+ ERADCRCGLOBAL : origin = 0x0005EA00, length = 0x00000010
+ ERADCRC1 : origin = 0x0005EA10, length = 0x00000010
+ ERADCRC2 : origin = 0x0005EA20, length = 0x00000010
+ ERADCRC3 : origin = 0x0005EA30, length = 0x00000010
+ ERADCRC4 : origin = 0x0005EA40, length = 0x00000010
+ ERADCRC5 : origin = 0x0005EA50, length = 0x00000010
+ ERADCRC6 : origin = 0x0005EA60, length = 0x00000010
+ ERADCRC7 : origin = 0x0005EA70, length = 0x00000010
+ ERADCRC8 : origin = 0x0005EA80, length = 0x00000010
+ ERADGLOBAL : origin = 0x0005E800, length = 0x00000014
+ ERADHWBP1 : origin = 0x0005E900, length = 0x00000008
+ ERADHWBP2 : origin = 0x0005E908, length = 0x00000008
+ ERADHWBP3 : origin = 0x0005E910, length = 0x00000008
+ ERADHWBP4 : origin = 0x0005E918, length = 0x00000008
+ ERADHWBP5 : origin = 0x0005E920, length = 0x00000008
+ ERADHWBP6 : origin = 0x0005E928, length = 0x00000008
+ ERADHWBP7 : origin = 0x0005E930, length = 0x00000008
+ ERADHWBP8 : origin = 0x0005E938, length = 0x00000008
+ ESCSSCONFIG : origin = 0x00057F00, length = 0x00000016
+ ESCSS : origin = 0x00057E00, length = 0x00000024
+ FLASH0CTRL : origin = 0x0005F800, length = 0x00000182
+ FLASH0ECC : origin = 0x0005FB00, length = 0x00000028
+ FSIRXA : origin = 0x00006680, length = 0x00000050
+ FSIRXB : origin = 0x00006780, length = 0x00000050
+ FSIRXC : origin = 0x00006880, length = 0x00000050
+ FSIRXD : origin = 0x00006980, length = 0x00000050
+ FSIRXE : origin = 0x00006A80, length = 0x00000050
+ FSIRXF : origin = 0x00006B80, length = 0x00000050
+ FSIRXG : origin = 0x00006C80, length = 0x00000050
+ FSIRXH : origin = 0x00006D80, length = 0x00000050
+ FSITXA : origin = 0x00006600, length = 0x00000050
+ FSITXB : origin = 0x00006700, length = 0x00000050
+ GPIOCTRL : origin = 0x00007C00, length = 0x00000200
+ GPIODATAREAD : origin = 0x00007F80, length = 0x00000010
+ GPIODATA : origin = 0x00007F00, length = 0x00000040
+ HRCAP6 : origin = 0x00005360, length = 0x00000020
+ HRCAP7 : origin = 0x000053A0, length = 0x00000020
+ I2CA : origin = 0x00007300, length = 0x00000022
+ I2CB : origin = 0x00007340, length = 0x00000022
+ INPUTXBAR : origin = 0x00007900, length = 0x00000020
+ CLBINPUTXBAR : origin = 0x00007960, length = 0x00000020
+ MCANASS : origin = 0x0005C400, length = 0x0000002C
+ MCANAERR : origin = 0x0005C800, length = 0x00000210
+ MCANA : origin = 0x0005C600, length = 0x00000100
+ MEMORYERROR : origin = 0x0005F540, length = 0x00000040
+ MEMCFG : origin = 0x0005F400, length = 0x000000C0
+ MCBSPA : origin = 0x00006000, length = 0x00000024
+ MCBSPB : origin = 0x00006040, length = 0x00000024
+ NMIINTRUPT : origin = 0x00007060, length = 0x00000010
+ OUTPUTXBAR : origin = 0x00007A80, length = 0x00000040
+ CLBOUTPUTXBAR : origin = 0x00007BC0, length = 0x00000040
+ PIECTRL : origin = 0x00000CE0, length = 0x0000001A
+ PIEVECTTABLE : origin = 0x00000D00, length = 0x00000200
+ PMBUSA : origin = 0x00006400, length = 0x00000020
+ ROMPREFETCH : origin = 0x0005F588, length = 0x00000008
+ ROMWAITSTATE : origin = 0x0005F580, length = 0x00000008
+ SCIA : origin = 0x00007200, length = 0x00000010
+ SCIB : origin = 0x00007210, length = 0x00000010
+ SCIC : origin = 0x00007220, length = 0x00000010
+ SCID : origin = 0x00007230, length = 0x00000010
+ SDFM1 : origin = 0x00005E00, length = 0x00000080
+ SDFM2 : origin = 0x00005E80, length = 0x00000080
+ SPIA : origin = 0x00006100, length = 0x00000010
+ SPIB : origin = 0x00006110, length = 0x00000010
+ SPIC : origin = 0x00006120, length = 0x00000010
+ SPID : origin = 0x00006130, length = 0x00000010
+ SYNCSOC : origin = 0x00007940, length = 0x00000006
+ SYSSTATUS : origin = 0x0005D400, length = 0x00000100
+ TESTERROR : origin = 0x0005F590, length = 0x00000010
+ WD : origin = 0x00007000, length = 0x0000002C
+ XBAR : origin = 0x00007920, length = 0x00000020
+ XINT : origin = 0x00007070, length = 0x0000000C
+
+}
+
+
+SECTIONS
+{
+/*** PIE Vect Table and Boot ROM Variables Structures ***/
+UNION run = PIEVECTTABLE
+{
+ PieVectTableFile
+ GROUP
+ {
+ EmuKeyVar
+ EmuBModeVar
+ EmuBootPinsVar
+ FlashCallbackVar
+ FlashScalingVar
+ }
+}
+
+ AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT
+ AdcaRegsFile : > ADCA, type=NOINIT
+ AdcbRegsFile : > ADCB, type=NOINIT
+ AdccRegsFile : > ADCC, type=NOINIT
+ AdcdRegsFile : > ADCD, type=NOINIT
+ AdcaResultRegsFile : > ADCARESULT, type=NOINIT
+ AdcbResultRegsFile : > ADCBRESULT, type=NOINIT
+ AdccResultRegsFile : > ADCCRESULT, type=NOINIT
+ AdcdResultRegsFile : > ADCDRESULT, type=NOINIT
+ AnalogSubsysRegsFile : > ANALOGSUBSYS, type=NOINIT
+ BgcrcCpuRegsFile : > BGCRCCPU, type=NOINIT
+ BgcrcCla1RegsFile : > BGCRCCLA1, type=NOINIT
+ CanaRegsFile : > CANA, type=NOINIT
+ CanbRegsFile : > CANB, type=NOINIT
+ Cla1RegsFile : > CLA1, type=NOINIT
+ Clb1DataExchRegsFile : > CLB1DATAEXCH, type=NOINIT
+ Clb2DataExchRegsFile : > CLB2DATAEXCH, type=NOINIT
+ Clb3DataExchRegsFile : > CLB3DATAEXCH, type=NOINIT
+ Clb4DataExchRegsFile : > CLB4DATAEXCH, type=NOINIT
+ Clb5DataExchRegsFile : > CLB5DATAEXCH, type=NOINIT
+ Clb6DataExchRegsFile : > CLB6DATAEXCH, type=NOINIT
+ Clb7DataExchRegsFile : > CLB7DATAEXCH, type=NOINIT
+ Clb8DataExchRegsFile : > CLB8DATAEXCH, type=NOINIT
+ Clb1LogicCfgRegsFile : > CLB1LOGICCFG, type=NOINIT
+ Clb2LogicCfgRegsFile : > CLB2LOGICCFG, type=NOINIT
+ Clb3LogicCfgRegsFile : > CLB3LOGICCFG, type=NOINIT
+ Clb4LogicCfgRegsFile : > CLB4LOGICCFG, type=NOINIT
+ Clb5LogicCfgRegsFile : > CLB5LOGICCFG, type=NOINIT
+ Clb6LogicCfgRegsFile : > CLB6LOGICCFG, type=NOINIT
+ Clb7LogicCfgRegsFile : > CLB7LOGICCFG, type=NOINIT
+ Clb8LogicCfgRegsFile : > CLB8LOGICCFG, type=NOINIT
+ Clb1LogicCtrlRegsFile : > CLB1LOGICCTRL, type=NOINIT
+ Clb2LogicCtrlRegsFile : > CLB2LOGICCTRL, type=NOINIT
+ Clb3LogicCtrlRegsFile : > CLB3LOGICCTRL, type=NOINIT
+ Clb4LogicCtrlRegsFile : > CLB4LOGICCTRL, type=NOINIT
+ Clb5LogicCtrlRegsFile : > CLB5LOGICCTRL, type=NOINIT
+ Clb6LogicCtrlRegsFile : > CLB6LOGICCTRL, type=NOINIT
+ Clb7LogicCtrlRegsFile : > CLB7LOGICCTRL, type=NOINIT
+ Clb8LogicCtrlRegsFile : > CLB8LOGICCTRL, type=NOINIT
+ CLBXbarRegsFile : > CLBXBAR, type=NOINIT
+ ClkCfgRegsFile : > CLKCFG, type=NOINIT
+ Cmpss1RegsFile : > CMPSS1, type=NOINIT
+ Cmpss2RegsFile : > CMPSS2, type=NOINIT
+ Cmpss3RegsFile : > CMPSS3, type=NOINIT
+ Cmpss4RegsFile : > CMPSS4, type=NOINIT
+ Cmpss5RegsFile : > CMPSS5, type=NOINIT
+ Cmpss6RegsFile : > CMPSS6, type=NOINIT
+ Cmpss7RegsFile : > CMPSS7, type=NOINIT
+ Cmpss8RegsFile : > CMPSS8, type=NOINIT
+ CmConfRegsFile : > CMCONF, type=NOINIT
+ Cpu1toCmIpcRegsFile : > CPU1TOCMIPC, type=NOINIT
+ Cpu1toCpu2IpcRegsFile : > CPU1TOCPU2IPC, type=NOINIT
+ SysPeriphAcRegsFile : > SYSPERIPHAC, type=NOINIT
+ CpuTimer0RegsFile : > CPUTIMER0, type=NOINIT
+ CpuTimer1RegsFile : > CPUTIMER1, type=NOINIT
+ CpuTimer2RegsFile : > CPUTIMER2, type=NOINIT
+ CpuSysRegsFile : > CPUSYS, type=NOINIT
+ DacaRegsFile : > DACA, type=NOINIT
+ DacbRegsFile : > DACB, type=NOINIT
+ DaccRegsFile : > DACC, type=NOINIT
+ Dcc0RegsFile : > DCC0, type=NOINIT
+ Dcc1RegsFile : > DCC1, type=NOINIT
+ Dcc2RegsFile : > DCC2, type=NOINIT
+ DcsmCommonRegsFile : > DCSMCOMMON, type=NOINIT
+ DcsmZ1OtpRegsFile : > DCSMZ1OTP, type=NOINIT
+ DcsmZ1RegsFile : > DCSMZ1, type=NOINIT
+ DcsmZ2OtpRegsFile : > DCSMZ2OTP, type=NOINIT
+ DcsmZ2RegsFile : > DCSMZ2, type=NOINIT
+ DevCfgRegsFile : > DEVCFG, type=NOINIT
+ DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT
+ DmaRegsFile : > DMA, type=NOINIT
+ ECap1RegsFile : > ECAP1, type=NOINIT
+ ECap2RegsFile : > ECAP2, type=NOINIT
+ ECap3RegsFile : > ECAP3, type=NOINIT
+ ECap4RegsFile : > ECAP4, type=NOINIT
+ ECap5RegsFile : > ECAP5, type=NOINIT
+ ECap6RegsFile : > ECAP6, type=NOINIT
+ ECap7RegsFile : > ECAP7, type=NOINIT
+ Emif1ConfigRegsFile : > EMIF1CONFIG, type=NOINIT
+ Emif2ConfigRegsFile : > EMIF2CONFIG, type=NOINIT
+ Emif1RegsFile : > EMIF1, type=NOINIT
+ Emif2RegsFile : > EMIF2, type=NOINIT
+ EPwm1RegsFile : > EPWM1, type=NOINIT
+ EPwm2RegsFile : > EPWM2, type=NOINIT
+ EPwm3RegsFile : > EPWM3, type=NOINIT
+ EPwm4RegsFile : > EPWM4, type=NOINIT
+ EPwm5RegsFile : > EPWM5, type=NOINIT
+ EPwm6RegsFile : > EPWM6, type=NOINIT
+ EPwm7RegsFile : > EPWM7, type=NOINIT
+ EPwm8RegsFile : > EPWM8, type=NOINIT
+ EPwm9RegsFile : > EPWM9, type=NOINIT
+ EPwm10RegsFile : > EPWM10, type=NOINIT
+ EPwm11RegsFile : > EPWM11, type=NOINIT
+ EPwm12RegsFile : > EPWM12, type=NOINIT
+ EPwm13RegsFile : > EPWM13, type=NOINIT
+ EPwm14RegsFile : > EPWM14, type=NOINIT
+ EPwm15RegsFile : > EPWM15, type=NOINIT
+ EPwm16RegsFile : > EPWM16, type=NOINIT
+ EPwmXbarRegsFile : > EPWMXBAR, type=NOINIT
+ EQep1RegsFile : > EQEP1, type=NOINIT
+ EQep2RegsFile : > EQEP2, type=NOINIT
+ EQep3RegsFile : > EQEP3, type=NOINIT
+ EradCounter1RegsFile : > ERADCOUNTER1, type=NOINIT
+ EradCounter2RegsFile : > ERADCOUNTER2, type=NOINIT
+ EradCounter3RegsFile : > ERADCOUNTER3, type=NOINIT
+ EradCounter4RegsFile : > ERADCOUNTER4, type=NOINIT
+ EradCRCGlobalRegsFile : > ERADCRCGLOBAL, type=NOINIT
+ EradCRC1RegsFile : > ERADCRC1, type=NOINIT
+ EradCRC2RegsFile : > ERADCRC2, type=NOINIT
+ EradCRC3RegsFile : > ERADCRC3, type=NOINIT
+ EradCRC4RegsFile : > ERADCRC4, type=NOINIT
+ EradCRC5RegsFile : > ERADCRC5, type=NOINIT
+ EradCRC6RegsFile : > ERADCRC6, type=NOINIT
+ EradCRC7RegsFile : > ERADCRC7, type=NOINIT
+ EradCRC8RegsFile : > ERADCRC8, type=NOINIT
+ EradGlobalRegsFile : > ERADGLOBAL, type=NOINIT
+ EradHWBP1RegsFile : > ERADHWBP1, type=NOINIT
+ EradHWBP2RegsFile : > ERADHWBP2, type=NOINIT
+ EradHWBP3RegsFile : > ERADHWBP3, type=NOINIT
+ EradHWBP4RegsFile : > ERADHWBP4, type=NOINIT
+ EradHWBP5RegsFile : > ERADHWBP5, type=NOINIT
+ EradHWBP6RegsFile : > ERADHWBP6, type=NOINIT
+ EradHWBP7RegsFile : > ERADHWBP7, type=NOINIT
+ EradHWBP8RegsFile : > ERADHWBP8, type=NOINIT
+ EscssConfigRegsFile : > ESCSSCONFIG, type=NOINIT
+ EscssRegsFile : > ESCSS, type=NOINIT
+ Flash0CtrlRegsFile : > FLASH0CTRL, type=NOINIT
+ Flash0EccRegsFile : > FLASH0ECC, type=NOINIT
+ FsiRxaRegsFile : > FSIRXA, type=NOINIT
+ FsiRxbRegsFile : > FSIRXB, type=NOINIT
+ FsiRxcRegsFile : > FSIRXC, type=NOINIT
+ FsiRxdRegsFile : > FSIRXD, type=NOINIT
+ FsiRxeRegsFile : > FSIRXE, type=NOINIT
+ FsiRxfRegsFile : > FSIRXF, type=NOINIT
+ FsiRxgRegsFile : > FSIRXG, type=NOINIT
+ FsiRxhRegsFile : > FSIRXH, type=NOINIT
+ FsiTxaRegsFile : > FSITXA, type=NOINIT
+ FsiTxbRegsFile : > FSITXB, type=NOINIT
+ GpioCtrlRegsFile : > GPIOCTRL, type=NOINIT
+ GpioDataReadRegsFile : > GPIODATAREAD, type=NOINIT
+ GpioDataRegsFile : > GPIODATA, type=NOINIT
+ HRCap6RegsFile : > HRCAP6, type=NOINIT
+ HRCap7RegsFile : > HRCAP7, type=NOINIT
+ I2caRegsFile : > I2CA, type=NOINIT
+ I2cbRegsFile : > I2CB, type=NOINIT
+ InputXbarRegsFile : > INPUTXBAR, type=NOINIT
+ ClbInputXbarRegsFile : > CLBINPUTXBAR, type=NOINIT
+ McanaSsRegsFile : > MCANASS, type=NOINIT
+ McanaErrRegsFile : > MCANAERR, type=NOINIT
+ McanaRegsFile : > MCANA, type=NOINIT
+ MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT
+ MemCfgRegsFile : > MEMCFG, type=NOINIT
+ McbspaRegsFile : > MCBSPA, type=NOINIT
+ McbspbRegsFile : > MCBSPB, type=NOINIT
+ NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT
+ OutputXbarRegsFile : > OUTPUTXBAR, type=NOINIT
+ ClbOutputXbarRegsFile : > CLBOUTPUTXBAR, type=NOINIT
+ PieCtrlRegsFile : > PIECTRL, type=NOINIT
+ PieVectTableFile : > PIEVECTTABLE, type=NOINIT
+ PmbusaRegsFile : > PMBUSA, type=NOINIT
+ RomPrefetchRegsFile : > ROMPREFETCH, type=NOINIT
+ RomWaitStateRegsFile : > ROMWAITSTATE, type=NOINIT
+ SciaRegsFile : > SCIA, type=NOINIT
+ ScibRegsFile : > SCIB, type=NOINIT
+ ScicRegsFile : > SCIC, type=NOINIT
+ ScidRegsFile : > SCID, type=NOINIT
+ Sdfm1RegsFile : > SDFM1, type=NOINIT
+ Sdfm2RegsFile : > SDFM2, type=NOINIT
+ SpiaRegsFile : > SPIA, type=NOINIT
+ SpibRegsFile : > SPIB, type=NOINIT
+ SpicRegsFile : > SPIC, type=NOINIT
+ SpidRegsFile : > SPID, type=NOINIT
+ SyncSocRegsFile : > SYNCSOC, type=NOINIT
+ SysStatusRegsFile : > SYSSTATUS, type=NOINIT
+ TestErrorRegsFile : > TESTERROR, type=NOINIT
+ WdRegsFile : > WD, type=NOINIT
+ XbarRegsFile : > XBAR, type=NOINIT
+ XintRegsFile : > XINT, type=NOINIT
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
+
diff --git a/Projects/epwm_test/lib/f2838x_codestartbranch.asm b/Projects/epwm_test/lib/f2838x_codestartbranch.asm
new file mode 100644
index 0000000..df7a0e3
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_codestartbranch.asm
@@ -0,0 +1,112 @@
+;//###########################################################################
+;//
+;// FILE: f2838x_codestartbranch.asm
+;//
+;// TITLE: Branch for redirecting code execution after boot.
+;//
+;// For these examples, code_start is the first code that is executed after
+;// exiting the boot ROM code.
+;//
+;// The codestart section in the linker cmd file is used to physically place
+;// this code at the correct memory location. This section should be placed
+;// at the location the BOOT ROM will re-direct the code to. For example,
+;// for boot to FLASH this code will be located at 0x3f7ff6.
+;//
+;// In addition, the example F2838x projects are setup such that the codegen
+;// entry point is also set to the code_start label. This is done by linker
+;// option -e in the project build options. When the debugger loads the code,
+;// it will automatically set the PC to the "entry point" address indicated by
+;// the -e linker option. In this case the debugger is simply assigning the PC,
+;// it is not the same as a full reset of the device.
+;//
+;// The compiler may warn that the entry point for the project is other then
+;// _c_init00. _c_init00 is the C environment setup and is run before
+;// main() is entered. The code_start code will re-direct the execution
+;// to _c_init00 and thus there is no worry and this warning can be ignored.
+;//
+;//###########################################################################
+;//
+;//
+;// $Copyright:
+;// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+;//
+;// Redistribution and use in source and binary forms, with or without
+;// modification, are permitted provided that the following conditions
+;// are met:
+;//
+;// Redistributions of source code must retain the above copyright
+;// notice, this list of conditions and the following disclaimer.
+;//
+;// Redistributions in binary form must reproduce the above copyright
+;// notice, this list of conditions and the following disclaimer in the
+;// documentation and/or other materials provided with the
+;// distribution.
+;//
+;// Neither the name of Texas Instruments Incorporated nor the names of
+;// its contributors may be used to endorse or promote products derived
+;// from this software without specific prior written permission.
+;//
+;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;// $
+;//###########################################################################
+
+***********************************************************************
+
+WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0
+
+ .ref _c_int00
+ .global code_start
+
+***********************************************************************
+* Function: codestart section
+*
+* Description: Branch to code starting point
+***********************************************************************
+
+ .sect "codestart"
+ .retain
+
+code_start:
+ .if WD_DISABLE == 1
+ LB wd_disable ;Branch to watchdog disable code
+ .else
+ LB _c_int00 ;Branch to start of boot._asm in RTS library
+ .endif
+
+;end codestart section
+
+***********************************************************************
+* Function: wd_disable
+*
+* Description: Disables the watchdog timer
+***********************************************************************
+ .if WD_DISABLE == 1
+
+ .text
+wd_disable:
+ SETC OBJMODE ;Set OBJMODE for 28x object code
+ EALLOW ;Enable EALLOW protected register access
+ MOVZ DP, #7029h>>6 ;Set data page for WDCR register
+ MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
+ EDIS ;Disable EALLOW protected register access
+ LB _c_int00 ;Branch to start of boot._asm in RTS library
+
+ .endif
+
+;end wd_disable
+
+ .end
+
+;//
+;// End of file.
+;//
diff --git a/Projects/epwm_test/lib/f2838x_defaultisr.c b/Projects/epwm_test/lib/f2838x_defaultisr.c
new file mode 100644
index 0000000..0a9c44f
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_defaultisr.c
@@ -0,0 +1,4635 @@
+//###########################################################################
+//
+// FILE: f2838x_defaultisr.c
+//
+// TITLE: f2838x Device Default Interrupt Service Routines
+//
+//###########################################################################
+// $Copyright:
+// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "f2838x_device.h" // f2838x Header File Include File
+#include "f2838x_examples.h" // f2838x Examples Include File
+
+//
+// CPU Timer 1 Interrupt
+//
+interrupt void TIMER1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// CPU Timer 2 Interrupt
+//
+interrupt void TIMER2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// Datalogging Interrupt
+//
+interrupt void DATALOG_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// RTOS Interrupt
+//
+interrupt void RTOS_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// Emulation Interrupt
+//
+interrupt void EMU_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// Non-Maskable Interrupt
+//
+interrupt void NMI_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// Illegal Operation Trap
+//
+interrupt void ILLEGAL_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 1
+//
+interrupt void USER1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 2
+//
+interrupt void USER2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 3
+//
+interrupt void USER3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 4
+//
+interrupt void USER4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 5
+//
+interrupt void USER5_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 6
+//
+interrupt void USER6_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 7
+//
+interrupt void USER7_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 8
+//
+interrupt void USER8_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 9
+//
+interrupt void USER9_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 10
+//
+interrupt void USER10_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 11
+//
+interrupt void USER11_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// User Defined Trap 12
+//
+interrupt void USER12_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.1 - ADCA Interrupt 1
+//
+interrupt void ADCA1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.2 - ADCB Interrupt 1
+//
+interrupt void ADCB1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.3 - ADCC Interrupt 1
+//
+interrupt void ADCC1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.4 - XINT1 Interrupt
+//
+interrupt void XINT1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.5 - XINT2 Interrupt
+//
+interrupt void XINT2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.6 - ADCD Interrupt 1
+//
+interrupt void ADCD1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.7 - Timer 0 Interrupt
+//
+interrupt void TIMER0_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.8 - Standby and Halt Wakeup Interrupt
+//
+interrupt void WAKE_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.1 - ePWM1 Trip Zone Interrupt
+//
+interrupt void EPWM1_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.2 - ePWM2 Trip Zone Interrupt
+//
+interrupt void EPWM2_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.3 - ePWM3 Trip Zone Interrupt
+//
+interrupt void EPWM3_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.4 - ePWM4 Trip Zone Interrupt
+//
+interrupt void EPWM4_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.5 - ePWM5 Trip Zone Interrupt
+//
+interrupt void EPWM5_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.6 - ePWM6 Trip Zone Interrupt
+//
+interrupt void EPWM6_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.7 - ePWM7 Trip Zone Interrupt
+//
+interrupt void EPWM7_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.8 - ePWM8 Trip Zone Interrupt
+//
+interrupt void EPWM8_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.1 - ePWM1 Interrupt
+//
+interrupt void EPWM1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.2 - ePWM2 Interrupt
+//
+interrupt void EPWM2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.3 - ePWM3 Interrupt
+//
+interrupt void EPWM3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.4 - ePWM4 Interrupt
+//
+interrupt void EPWM4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.5 - ePWM5 Interrupt
+//
+interrupt void EPWM5_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.6 - ePWM6 Interrupt
+//
+interrupt void EPWM6_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.7 - ePWM7 Interrupt
+//
+interrupt void EPWM7_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.8 - ePWM8 Interrupt
+//
+interrupt void EPWM8_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.1 - eCAP1 Interrupt
+//
+interrupt void ECAP1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.2 - eCAP2 Interrupt
+//
+interrupt void ECAP2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.3 - eCAP3 Interrupt
+//
+interrupt void ECAP3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.4 - eCAP4 Interrupt
+//
+interrupt void ECAP4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.5 - eCAP5 Interrupt
+//
+interrupt void ECAP5_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.6 - eCAP6 Interrupt
+//
+interrupt void ECAP6_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.7 - eCAP7 Interrupt
+//
+interrupt void ECAP7_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.1 - eQEP1 Interrupt
+//
+interrupt void EQEP1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.2 - eQEP2 Interrupt
+//
+interrupt void EQEP2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.3 - eQEP3 Interrupt
+//
+interrupt void EQEP3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.5 - CLB1 (Reconfigurable Logic) Interrupt
+//
+interrupt void CLB1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.6 - CLB2 (Reconfigurable Logic) Interrupt
+//
+interrupt void CLB2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.7 - CLB3 (Reconfigurable Logic) Interrupt
+//
+interrupt void CLB3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.8 - CLB4 (Reconfigurable Logic) Interrupt
+//
+interrupt void CLB4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.1 - SPIA Receive Interrupt
+//
+interrupt void SPIA_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.2 - SPIA Transmit Interrupt
+//
+interrupt void SPIA_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.3 - SPIB Receive Interrupt
+//
+interrupt void SPIB_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.4 - SPIB Transmit Interrupt
+//
+interrupt void SPIB_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.5 - McBSPA Receive Interrupt
+//
+interrupt void MCBSPA_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.6 - McBSPA Transmit Interrupt
+//
+interrupt void MCBSPA_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.7 - McBSPB Receive Interrupt
+//
+interrupt void MCBSPB_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.8 - McBSPB Transmit Interrupt
+//
+interrupt void MCBSPB_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.1 - DMA Channel 1 Interrupt
+//
+interrupt void DMA_CH1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.2 - DMA Channel 2 Interrupt
+//
+interrupt void DMA_CH2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.3 - DMA Channel 3 Interrupt
+//
+interrupt void DMA_CH3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.4 - DMA Channel 4 Interrupt
+//
+interrupt void DMA_CH4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.5 - DMA Channel 5 Interrupt
+//
+interrupt void DMA_CH5_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.6 - DMA Channel 6 Interrupt
+//
+interrupt void DMA_CH6_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.1 - I2CA Interrupt 1
+//
+interrupt void I2CA_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.2 - I2CA Interrupt 2
+//
+interrupt void I2CA_FIFO_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.3 - I2CB Interrupt 1
+//
+interrupt void I2CB_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.4 - I2CB Interrupt 2
+//
+interrupt void I2CB_FIFO_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.5 - SCIC Receive Interrupt
+//
+interrupt void SCIC_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.6 - SCIC Transmit Interrupt
+//
+interrupt void SCIC_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.7 - SCID Receive Interrupt
+//
+interrupt void SCID_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.8 - SCID Transmit Interrupt
+//
+interrupt void SCID_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.1 - SCIA Receive Interrupt
+//
+interrupt void SCIA_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.2 - SCIA Transmit Interrupt
+//
+interrupt void SCIA_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.3 - SCIB Receive Interrupt
+//
+interrupt void SCIB_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.4 - SCIB Transmit Interrupt
+//
+interrupt void SCIB_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.5 - CANA Interrupt 0
+//
+interrupt void CANA0_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.6 - CANA Interrupt 1
+//
+interrupt void CANA1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.7 - CANB Interrupt 0
+//
+interrupt void CANB0_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.8 - CANB Interrupt 1
+//
+interrupt void CANB1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.1 - ADCA Event Interrupt
+//
+interrupt void ADCA_EVT_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.2 - ADCA Interrupt 2
+//
+interrupt void ADCA2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.3 - ADCA Interrupt 3
+//
+interrupt void ADCA3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.4 - ADCA Interrupt 4
+//
+interrupt void ADCA4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.5 - ADCB Event Interrupt
+//
+interrupt void ADCB_EVT_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.6 - ADCB Interrupt 2
+//
+interrupt void ADCB2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.7 - ADCB Interrupt 3
+//
+interrupt void ADCB3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.8 - ADCB Interrupt 4
+//
+interrupt void ADCB4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.1 - CLA1 Interrupt 1
+//
+interrupt void CLA1_1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.2 - CLA1 Interrupt 2
+//
+interrupt void CLA1_2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.3 - CLA1 Interrupt 3
+//
+interrupt void CLA1_3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.4 - CLA1 Interrupt 4
+//
+interrupt void CLA1_4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.5 - CLA1 Interrupt 5
+//
+interrupt void CLA1_5_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.6 - CLA1 Interrupt 6
+//
+interrupt void CLA1_6_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.7 - CLA1 Interrupt 7
+//
+interrupt void CLA1_7_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.8 - CLA1 Interrupt 8
+//
+interrupt void CLA1_8_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.1 - XINT3 Interrupt
+//
+interrupt void XINT3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.2 - XINT4 Interrupt
+//
+interrupt void XINT4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.3 - XINT5 Interrupt
+//
+interrupt void XINT5_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.4 - MPOST Interrupt
+//
+interrupt void MPOST_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.5 - Flash Wrapper Operation Done Interrupt
+//
+interrupt void FMC_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.7 - FPU Overflow Interrupt
+//
+interrupt void FPU_OFLOW_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.8 - FPU Underflow Interrupt
+//
+interrupt void FPU_UFLOW_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.9 - I2CA Interrupt high priority
+//
+interrupt void I2CA_HIGH_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.10 - System error interrupt
+//
+interrupt void SYS_ERR_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.11 - ETHERCAT SYNC0 interrupt
+//
+interrupt void ECATSYNC0_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.12 - ETHERCAT main interrupt
+//
+interrupt void ECAT_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.13 - C28x CPU IPC interrupt 1
+//
+interrupt void CIPC0_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.14 - C28x CPU IPC interrupt 2
+//
+interrupt void CIPC1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.15 - C28x CPU IPC interrupt 3
+//
+interrupt void CIPC2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 1.16 - C28x CPU IPC interrupt 4
+//
+interrupt void CIPC3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.9 - ePWM9 Trip Zone Interrupt
+//
+interrupt void EPWM9_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.10 - ePWM10 Trip Zone Interrupt
+//
+interrupt void EPWM10_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.11 - ePWM11 Trip Zone Interrupt
+//
+interrupt void EPWM11_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.12 - ePWM12 Trip Zone Interrupt
+//
+interrupt void EPWM12_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.13 - ePWM13 Trip Zone Interrupt
+//
+interrupt void EPWM13_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.14 - ePWM14 Trip Zone Interrupt
+//
+interrupt void EPWM14_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.15 - ePWM15 Trip Zone Interrupt
+//
+interrupt void EPWM15_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 2.16 - ePWM16 Trip Zone Interrupt
+//
+interrupt void EPWM16_TZ_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.9 - ePWM9 Interrupt
+//
+interrupt void EPWM9_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.10 - ePWM10 Interrupt
+//
+interrupt void EPWM10_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.11 - ePWM11 Interrupt
+//
+interrupt void EPWM11_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.12 - ePWM12 Interrupt
+//
+interrupt void EPWM12_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.13 - ePWM13 Interrupt
+//
+interrupt void EPWM13_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.14 - ePWM14 Interrupt
+//
+interrupt void EPWM14_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.15 - ePWM15 Interrupt
+//
+interrupt void EPWM15_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 3.16 - ePWM16 Interrupt
+//
+interrupt void EPWM16_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.9 - FSIA Transmit interrupt 1
+//
+interrupt void FSITXA1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.10 - FSIA Transmit interrupt 2
+//
+interrupt void FSITXA2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.11 - FSIB Transmit interrupt 1
+//
+interrupt void FSITXB1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.12 - FSIB Transmit interrupt 2
+//
+interrupt void FSITXB2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.13 - FSIA Receive interrupt 1
+//
+interrupt void FSIRXA1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.14 - FSIA Receive interrupt 2
+//
+interrupt void FSIRXA2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.15 - FSIB Receive interrupt 1
+//
+interrupt void FSIRXB1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 4.16 - FSIB Receive interrupt 2
+//
+interrupt void FSIRXB2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.9 - Sigma Delta Filter Module1 Interrupt
+//
+interrupt void SDFM1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.10 - Sigma Delta Filter Module2 Interrupt
+//
+interrupt void SDFM2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.11 - ETHERCAT Resetout Interrupt
+//
+interrupt void ECATRST_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.12 - ETHERCAT SYNC1 interrupt
+//
+interrupt void ECATSYNC1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.13 - Sigma Delta Filter Module1 Filter 1 Interrupt
+//
+interrupt void SDFM1DR1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.14 - Sigma Delta Filter Module1 Filter 2 Interrupt
+//
+interrupt void SDFM1DR2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.15 - Sigma Delta Filter Module1 Filter 3 Interrupt
+//
+interrupt void SDFM1DR3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 5.16 - Sigma Delta Filter Module1 Filter 4 Interrupt
+//
+interrupt void SDFM1DR4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.9 - SPIC Receive Interrupt
+//
+interrupt void SPIC_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.10 - SPIC Transmit Interrupt
+//
+interrupt void SPIC_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.11 - SPID Receive Interrupt
+//
+interrupt void SPID_RX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.12 - SPID Transmit Interrupt
+//
+interrupt void SPID_TX_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.13 - Sigma Delta Filter Module2 Filter 1 Interrupt
+//
+interrupt void SDFM2DR1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.14 - Sigma Delta Filter Module2 Filter 2 Interrupt
+//
+interrupt void SDFM2DR2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.15 - Sigma Delta Filter Module2 Filter 3 Interrupt
+//
+interrupt void SDFM2DR3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 6.16 - Sigma Delta Filter Module2 Filter 4 Interrupt
+//
+interrupt void SDFM2DR4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.9 - FSIC Receive interrupt 1
+//
+interrupt void FSIRXC1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.10 - FSIC Receive interrupt 2
+//
+interrupt void FSIRXC2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.11 - FSID Receive interrupt 1
+//
+interrupt void FSIRXD1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.12 - FSID Receive interrupt 2
+//
+interrupt void FSIRXD2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.13 - FSIE Receive interrupt 1
+//
+interrupt void FSIRXE1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.14 - FSIE Receive interrupt 2
+//
+interrupt void FSIRXE2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.15 - FSIF Receive interrupt 1
+//
+interrupt void FSIRXF1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 7.16 - FSIF Receive interrupt 2
+//
+interrupt void FSIRXF2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.9 - FSIG Receive interrupt 1
+//
+interrupt void FSIRXG1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.10 - FSIG Receive interrupt 2
+//
+interrupt void FSIRXG2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.11 - FSIH Receive interrupt 1
+//
+interrupt void FSIRXH1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.12 - FSIH Receive interrupt 2
+//
+interrupt void FSIRXH2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.13 - CLB5 Interrupt
+//
+interrupt void CLB5_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.14 - CLB6 Interrupt
+//
+interrupt void CLB6_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.15 - CLB7 Interrupt
+//
+interrupt void CLB7_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 8.16 - CLB8 Interrupt
+//
+interrupt void CLB8_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.9 - MCAN Sub-System Interrupt 0
+//
+interrupt void MCANA_0_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.10 - MCAN Sub-System Interrupt 1
+//
+interrupt void MCANA_1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.11 - MCAN Sub-System ECC error Interrupt
+//
+interrupt void MCANA_ECC_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.12 - MCAN Sub-System wakeup Interrupt
+//
+interrupt void MCANA_WAKE_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.13 - PMBUSA Interrupt
+//
+interrupt void PMBUSA_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.14 - CM Reset Status Interrupt
+//
+interrupt void CM_STATUS_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 9.15 - USBA Interrupt
+//
+interrupt void USBA_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.9 - ADCC Event Interrupt
+//
+interrupt void ADCC_EVT_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.10 - ADCC Interrupt 2
+//
+interrupt void ADCC2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.11 - ADCC Interrupt 3
+//
+interrupt void ADCC3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.12 - ADCC Interrupt 4
+//
+interrupt void ADCC4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.13 - ADCD Event Interrupt
+//
+interrupt void ADCD_EVT_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.14 - ADCD Interrupt 2
+//
+interrupt void ADCD2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.15 - ADCD Interrupt 3
+//
+interrupt void ADCD3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 10.16 - ADCD Interrupt 4
+//
+interrupt void ADCD4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.9 - CM to CPU IPC Interrupt 0
+//
+interrupt void CMTOCPUXIPC0_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.10 - CM to CPU IPC Interrupt 1
+//
+interrupt void CMTOCPUXIPC1_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.11 - CM to CPU IPC Interrupt 2
+//
+interrupt void CMTOCPUXIPC2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.12 - CM to CPU IPC Interrupt 3
+//
+interrupt void CMTOCPUXIPC3_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.13 - CM to CPU IPC Interrupt 4
+//
+interrupt void CMTOCPUXIPC4_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.14 - CM to CPU IPC Interrupt 5
+//
+interrupt void CMTOCPUXIPC5_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.15 - CM to CPU IPC Interrupt 6
+//
+interrupt void CMTOCPUXIPC6_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 11.16 - CM to CPU IPC Interrupt 7
+//
+interrupt void CMTOCPUXIPC7_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.10 - eCAP6 Interrupt 2
+//
+interrupt void ECAP6_2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.11 - eCAP7 Interrupt 2
+//
+interrupt void ECAP7_2_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.13 - CPU BGCRC module interrupt
+//
+interrupt void CPUCRC_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.14 - CLA1 BGCRC module interrupt
+//
+interrupt void CLA1CRC_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.15 - CLA Overflow Interrupt
+//
+interrupt void CLA_OVERFLOW_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// 12.16 - CLA Underflow Interrupt
+//
+interrupt void CLA_UNDERFLOW_ISR(void)
+{
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // To receive more interrupts from this PIE group,
+ // acknowledge this interrupt.
+ // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// Catch-all Default ISRs:
+//
+
+//
+// PIE_RESERVED_ISR - Reserved ISR
+//
+interrupt void PIE_RESERVED_ISR(void)
+{
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// EMPTY_ISR - Only does a return
+//
+interrupt void EMPTY_ISR(void)
+{
+
+}
+
+//
+// NOTUSED_ISR - Unused ISR
+//
+interrupt void NOTUSED_ISR(void)
+{
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// End of File
+//
+
diff --git a/Projects/epwm_test/lib/f2838x_epwm.c b/Projects/epwm_test/lib/f2838x_epwm.c
new file mode 100644
index 0000000..b1b422c
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_epwm.c
@@ -0,0 +1,642 @@
+//###########################################################################
+//
+// FILE: f2838x_epwm.c
+//
+// TITLE: F2838x EPwm Initialization & Support Functions.
+//
+//###########################################################################
+//
+//
+// $Copyright:
+// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "f2838x_device.h"
+#include "f2838x_examples.h"
+
+//
+// InitEPwmGpio - Initialize all EPWM modules' GPIOs
+//
+void InitEPwmGpio(void)
+{
+ InitEPwm1Gpio();
+ InitEPwm2Gpio();
+ InitEPwm3Gpio();
+ InitEPwm4Gpio();
+ InitEPwm5Gpio();
+ InitEPwm6Gpio();
+ InitEPwm7Gpio();
+ InitEPwm8Gpio();
+ InitEPwm9Gpio();
+ InitEPwm10Gpio();
+ InitEPwm11Gpio();
+ InitEPwm12Gpio();
+ InitEPwm13Gpio();
+ InitEPwm14Gpio();
+ InitEPwm15Gpio();
+ InitEPwm16Gpio();
+}
+
+//
+// InitEPwm1Gpio - Initialize EPWM1 GPIOs
+//
+void InitEPwm1Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B)
+// GpioCtrlRegs.GPEPUD.bit.GPIO145 = 1; // Disable pull-up on GPIO145 (EPWM1A)
+// GpioCtrlRegs.GPEPUD.bit.GPIO146 = 1; // Disable pull-up on GPIO146 (EPWM1B)
+
+ //
+ // Configure EPWM-1 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM1 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B
+// GpioCtrlRegs.GPEMUX2.bit.GPIO145 = 1; // Configure GPIO145 as EPWM1A
+// GpioCtrlRegs.GPEMUX2.bit.GPIO146 = 1; // Configure GPIO0146 as EPWM1B
+
+ EDIS;
+}
+
+//
+// InitEPwm2Gpio - Initialize EPWM2 GPIOs
+//
+void InitEPwm2Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B)
+// GpioCtrlRegs.GPEPUD.bit.GPIO147 = 1; // Disable pull-up on GPIO147 (EPWM2A)
+// GpioCtrlRegs.GPEPUD.bit.GPIO148 = 1; // Disable pull-up on GPIO148 (EPWM2B)
+
+ //
+ // Configure EPwm-2 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM2 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B
+// GpioCtrlRegs.GPEMUX2.bit.GPIO147 = 1; // Configure GPIO147 as EPWM2A
+// GpioCtrlRegs.GPEMUX2.bit.GPIO148 = 1; // Configure GPIO148 as EPWM2B
+
+ EDIS;
+}
+
+//
+// InitEPwm3Gpio - Initialize EPWM3 GPIOs
+//
+void InitEPwm3Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B)
+// GpioCtrlRegs.GPEPUD.bit.GPIO149 = 1; // Disable pull-up on GPIO149 (EPWM3A)
+// GpioCtrlRegs.GPEPUD.bit.GPIO150 = 1; // Disable pull-up on GPIO150 (EPWM3B)
+
+ //
+ // Configure EPwm-3 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM3 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B
+// GpioCtrlRegs.GPEMUX2.bit.GPIO149 = 1; // Configure GPIO149 as EPWM3A
+// GpioCtrlRegs.GPEMUX2.bit.GPIO150 = 1; // Configure GPIO150 as EPWM3B
+
+ EDIS;
+}
+
+//
+// InitEPwm4Gpio - Initialize EPWM4 GPIOs
+//
+void InitEPwm4Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B)
+// GpioCtrlRegs.GPEPUD.bit.GPIO151 = 1; // Disable pull-up on GPIO151 (EPWM4A)
+// GpioCtrlRegs.GPEPUD.bit.GPIO152 = 1; // Disable pull-up on GPIO152 (EPWM4B)
+
+ //
+ // Configure EPWM-4 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM4 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
+// GpioCtrlRegs.GPEMUX2.bit.GPIO151 = 1; // Configure GPIO151 as EPWM4A
+// GpioCtrlRegs.GPEMUX2.bit.GPIO152 = 1; // Configure GPIO152 as EPWM4B
+
+ EDIS;
+}
+
+//
+// InitEPwm5Gpio - Initialize EPWM5 GPIOs
+//
+void InitEPwm5Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EPWM5B)
+// GpioCtrlRegs.GPEPUD.bit.GPIO153 = 1; // Disable pull-up on GPIO153 (EPWM5A)
+// GpioCtrlRegs.GPEPUD.bit.GPIO154 = 1; // Disable pull-up on GPIO154 (EPWM5B)
+
+ //
+ // Configure EPWM-5 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM5 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
+// GpioCtrlRegs.GPEMUX2.bit.GPIO153 = 1; // Configure GPIO153 as EPWM5A
+// GpioCtrlRegs.GPEMUX2.bit.GPIO154 = 1; // Configure GPIO0154 as EPWM5B
+
+ EDIS;
+}
+
+//
+// InitEPwm6Gpio - Initialize EPWM6 GPIOs
+//
+void InitEPwm6Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EPWM6B)
+// GpioCtrlRegs.GPEPUD.bit.GPIO155 = 1; // Disable pull-up on GPIO155 (EPWM6A)
+// GpioCtrlRegs.GPEPUD.bit.GPIO156 = 1; // Disable pull-up on GPIO156 (EPWM6B)
+
+ //
+ // Configure EPWM-6 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM6 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B
+// GpioCtrlRegs.GPEMUX2.bit.GPIO155 = 1; // Configure GPIO155 as EPWM6A
+// GpioCtrlRegs.GPEMUX2.bit.GPIO156 = 1; // Configure GPIO156 as EPWM6B
+
+ EDIS;
+}
+
+//
+// InitEPwm7Gpio - Initialize EPWM7 GPIOs
+//
+void InitEPwm7Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EPWM7A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EPWM7B)
+// GpioCtrlRegs.GPEPUD.bit.GPIO157 = 1; // Disable pull-up on GPIO157 (EPWM7A)
+// GpioCtrlRegs.GPEPUD.bit.GPIO158 = 1; // Disable pull-up on GPIO158 (EPWM7B)
+
+ //
+ // Configure EPWM-7 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM7 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EPWM7A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EPWM7B
+// GpioCtrlRegs.GPEMUX2.bit.GPIO157 = 1; // Configure GPIO157 as EPWM7A
+// GpioCtrlRegs.GPEMUX2.bit.GPIO158 = 1; // Configure GPIO158 as EPWM7B
+
+ EDIS;
+}
+
+//
+// InitEPwm8Gpio - Initialize EPWM8 GPIOs
+//
+void InitEPwm8Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (EPWM8A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (EPWM8B)
+// GpioCtrlRegs.GPEPUD.bit.GPIO159 = 1; // Disable pull-up on GPIO159 (EPWM8A)
+// GpioCtrlRegs.GPFPUD.bit.GPIO160 = 1; // Disable pull-up on GPIO160 (EPWM8B)
+
+ //
+ // Configure EPWM-8 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM8 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as EPWM8A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as EPWM8B
+// GpioCtrlRegs.GPEMUX2.bit.GPIO159 = 1; // Configure GPIO159 as EPWM8A
+// GpioCtrlRegs.GPFMUX1.bit.GPIO160 = 1; // Configure GPIO160 as EPWM8B
+
+ EDIS;
+}
+
+//
+// InitEPwm9Gpio - Initialize EPWM9 GPIOs
+//
+void InitEPwm9Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPFPUD.bit.GPIO161 = 1; // Disable pull-up on GPIO161 (EPWM9A)
+ GpioCtrlRegs.GPFPUD.bit.GPIO162 = 1; // Disable pull-up on GPIO162 (EPWM9B)
+// GpioCtrlRegs.GPAPUD.bit.GPIO16 = 1; // Disable pull-up on GPIO16 (EPWM9A)
+// GpioCtrlRegs.GPAPUD.bit.GPIO17 = 1; // Disable pull-up on GPIO17 (EPWM9B)
+
+ //
+ // Configure EPWM-9 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM9 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPFMUX1.bit.GPIO161 = 1; // Configure GPIO161 as EPWM9A
+ GpioCtrlRegs.GPFMUX1.bit.GPIO162 = 1; // Configure GPIO162 as EPWM9B
+
+// //
+// // Alternate mapping for EPWM-9. Uncomment if required. Write 0 to
+// // GPAMUx register before configuring GPAGMux to avoid glitches.
+// //
+// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // Configure GPAMUX to 0 for GPIO16
+// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0; // Configure GPAMUX to 0 for GPIO17
+//
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO16 = 1; // Configure GPAGMUX for EPWM9A
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO17 = 1; // Configure GPAGMUX for EPWM9B
+//
+// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPAMUX for EPWM9A
+// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPAMUX for EPWM9B
+
+ EDIS;
+}
+
+//
+// InitEPwm10Gpio - Initialize EPWM10 GPIOs
+//
+void InitEPwm10Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPFPUD.bit.GPIO163 = 1; // Disable pull-up on GPIO163 (EPWM10A)
+ GpioCtrlRegs.GPFPUD.bit.GPIO164 = 1; // Disable pull-up on GPIO164 (EPWM10B)
+// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO18 (EPWM10A)
+// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 1; // Disable pull-up on GPIO19 (EPWM10B)
+
+ //
+ // Configure EPWM-10 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM10 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPFMUX1.bit.GPIO163 = 1; // Configure GPIO163 as EPWM10A
+ GpioCtrlRegs.GPFMUX1.bit.GPIO164 = 1; // Configure GPIO164 as EPWM10B
+
+// //
+// // Alternate mapping for EPWM-10. Uncomment if required. Write 0 to
+// // GPAMUx register before configuring GPAGMux to avoid glitches.
+// //
+// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; // Configure GPAMUX to 0 for GPIO18
+// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // Configure GPAMUX to 0 for GPIO19
+//
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 1; // Configure GPAGMUX for EPWM10A
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 1; // Configure GPAGMUX for EPWM10B
+//
+// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPAMUX for EPWM10A
+// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPAMUX for EPWM10B
+
+ EDIS;
+}
+
+//
+// InitEPwm11Gpio - Initialize EPWM11 GPIOs
+//
+void InitEPwm11Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPFPUD.bit.GPIO165 = 1; // Disable pull-up on GPIO165 (EPWM11A)
+ GpioCtrlRegs.GPFPUD.bit.GPIO166 = 1; // Disable pull-up on GPIO166 (EPWM11B)
+// GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (EPWM11A)
+// GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (EPWM11B)
+
+ //
+ // Configure EPWM-11 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM11 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPFMUX1.bit.GPIO165 = 1; // Configure GPIO165 as EPWM11A
+ GpioCtrlRegs.GPFMUX1.bit.GPIO166 = 1; // Configure GPIO166 as EPWM11B
+
+// //
+// // Alternate mapping for EPWM-11. Uncomment if required. Write 0 to
+// // GPAMUx register before configuring GPAGMux to avoid glitches.
+// //
+// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0; // Configure GPAMUX to 0 for GPIO20
+// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0; // Configure GPAMUX to 0 for GPIO21
+//
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 1; // Configure GPAGMUX for EPWM11A
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 1; // Configure GPAGMUX for EPWM11B
+//
+// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPAMUX for EPWM11A
+// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPAMUX for EPWM11B
+
+ EDIS;
+}
+
+//
+// InitEPwm12Gpio - Initialize EPWM12 GPIOs
+//
+void InitEPwm12Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPFPUD.bit.GPIO167 = 1; // Disable pull-up on GPIO167 (EPWM12A)
+ GpioCtrlRegs.GPFPUD.bit.GPIO168 = 1; // Disable pull-up on GPIO168 (EPWM12B)
+// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; // Disable pull-up on GPIO22 (EPWM12A)
+// GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; // Disable pull-up on GPIO23 (EPWM12B)
+
+ //
+ // Configure EPWM-12 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM12 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPFMUX1.bit.GPIO167 = 1; // Configure GPIO167 as EPWM12A
+ GpioCtrlRegs.GPFMUX1.bit.GPIO168 = 1; // Configure GPIO168 as EPWM12B
+
+// //
+// // Alternate mapping for EPWM-12. Uncomment if required. Write 0 to
+// // GPAMUx register before configuring GPAGMux to avoid glitches.
+// //
+// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; // Configure GPAMUX to 0 for GPIO22
+// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0; // Configure GPAMUX to 0 for GPIO23
+//
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO22 = 1; // Configure GPAGMUX for EPWM12A
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO23 = 1; // Configure GPAGMUX for EPWM12B
+//
+// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPAMUX for EPWM12A
+// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPAMUX for EPWM12B
+
+ EDIS;
+}
+
+//
+// InitEPwm13Gpio - Initialize EPWM13 GPIOs
+//
+void InitEPwm13Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPEPUD.bit.GPIO137 = 1; // Disable pull-up on GPIO137 (EPWM13A)
+ GpioCtrlRegs.GPEPUD.bit.GPIO138 = 1; // Disable pull-up on GPIO138 (EPWM13B)
+// GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EPWM13A)
+// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EPWM13B)
+
+ //
+ // Configure EPWM-13 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM13 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPEMUX1.bit.GPIO137 = 1; // Configure GPIO137 as EPWM13A
+ GpioCtrlRegs.GPEMUX1.bit.GPIO138 = 1; // Configure GPIO138 as EPWM13B
+
+// //
+// // Alternate mapping for EPWM-13. Uncomment if required. Write 0 to
+// // GPAMUx register before configuring GPAGMux to avoid glitches.
+// //
+// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 0; // Configure GPAMUX to 0 for GPIO24
+// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // Configure GPAMUX to 0 for GPIO25
+//
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO24 = 3; // Configure GPAGMUX for EPWM13A
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO25 = 3; // Configure GPAGMUX for EPWM13B
+//
+// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPAMUX for EPWM13A
+// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPAMUX for EPWM13B
+
+ EDIS;
+}
+
+//
+// InitEPwm14Gpio - Initialize EPWM14 GPIOs
+//
+void InitEPwm14Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPEPUD.bit.GPIO139 = 1; // Disable pull-up on GPIO139 (EPWM14A)
+ GpioCtrlRegs.GPEPUD.bit.GPIO140 = 1; // Disable pull-up on GPIO140 (EPWM14B)
+// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EPWM14A)
+// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EPWM14B)
+
+ //
+ // Configure EPWM-14 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM14 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPEMUX1.bit.GPIO139 = 1; // Configure GPIO139 as EPWM14A
+ GpioCtrlRegs.GPEMUX1.bit.GPIO140 = 1; // Configure GPIO140 as EPWM14B
+
+// //
+// // Alternate mapping for EPWM-14. Uncomment if required. Write 0 to
+// // GPAMUx register before configuring GPAGMux to avoid glitches.
+// //
+// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // Configure GPAMUX to 0 for GPIO26
+// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // Configure GPAMUX to 0 for GPIO27
+//
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO26 = 3; // Configure GPAGMUX for EPWM14A
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO27 = 3; // Configure GPAGMUX for EPWM14B
+//
+// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPAMUX for EPWM14A
+// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPAMUX for EPWM14B
+
+ EDIS;
+}
+
+//
+// InitEPwm15Gpio - Initialize EPWM15 GPIOs
+//
+void InitEPwm15Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPEPUD.bit.GPIO141 = 1; // Disable pull-up on GPIO141 (EPWM15A)
+ GpioCtrlRegs.GPEPUD.bit.GPIO142 = 1; // Disable pull-up on GPIO142 (EPWM15B)
+// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up on GPIO28 (EPWM15A)
+// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1; // Disable pull-up on GPIO29 (EPWM15B)
+
+ //
+ // Configure EPWM-15 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM15 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPEMUX1.bit.GPIO141 = 1; // Configure GPIO141 as EPWM15A
+ GpioCtrlRegs.GPEMUX1.bit.GPIO142 = 1; // Configure GPIO142 as EPWM15B
+
+// //
+// // Alternate mapping for EPWM-15. Uncomment if required. Write 0 to
+// // GPAMUx register before configuring GPAGMux to avoid glitches.
+// //
+// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 0; // Configure GPAMUX to 0 for GPIO28
+// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 0; // Configure GPAMUX to 0 for GPIO29
+//
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 3; // Configure GPAGMUX for EPWM15A
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 3; // Configure GPAGMUX for EPWM15B
+//
+// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPAMUX for EPWM15A
+// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPAMUX for EPWM15B
+
+ EDIS;
+}
+
+//
+// InitEPwm16Gpio - Initialize EPWM16 GPIOs
+//
+void InitEPwm16Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Disable internal pull-up for the selected output pins for reduced
+ // power consumption. Pull-ups can be enabled or disabled by the user.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPEPUD.bit.GPIO143 = 1; // Disable pull-up on GPIO141 (EPWM16A)
+ GpioCtrlRegs.GPEPUD.bit.GPIO144 = 1; // Disable pull-up on GPIO142 (EPWM16B)
+// GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Disable pull-up on GPIO28 (EPWM16A)
+// GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Disable pull-up on GPIO29 (EPWM16B)
+
+ //
+ // Configure EPWM-16 pins using GPIO regs. This specifies which of the
+ // possible GPIO pins will be EPWM16 functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPEMUX1.bit.GPIO143 = 1; // Configure GPIO141 as EPWM16A
+ GpioCtrlRegs.GPEMUX2.bit.GPIO144 = 1; // Configure GPIO142 as EPWM16B
+
+// //
+// // Alternate mapping for EPWM-16. Uncomment if required. Write 0 to
+// // GPAMUx register before configuring GPAGMux to avoid glitches in Mux.
+// //
+// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0; // Configure GPAMUX to 0 for GPIO30
+// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0; // Configure GPAMUX to 0 for GPIO31
+//
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO30 = 3; // Configure GPAGMUx for EPWM16A
+// GpioCtrlRegs.GPAGMUX2.bit.GPIO31 = 3; // Configure GPAGMux for EPWM16B
+//
+// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPAMUx for EPWM16A
+// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPAMux for EPWM16B
+
+ EDIS;
+}
+
+//
+// End of File
+//
diff --git a/Projects/epwm_test/lib/f2838x_globalvariabledefs.c b/Projects/epwm_test/lib/f2838x_globalvariabledefs.c
new file mode 100644
index 0000000..db5a2a5
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_globalvariabledefs.c
@@ -0,0 +1,1561 @@
+//###########################################################################
+//
+// FILE: f2838x_globalvariabledefs.c
+//
+// TITLE: f2838x Global Variables and Data Section Pragmas.
+//
+//###########################################################################
+// $Copyright:
+// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#include "f2838x_device.h" // f2838x Headerfile Include File
+
+//---------------------------------------------------------------------------
+// Define Global Peripheral Variables:
+//
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AccessProtectionRegsFile")
+#else
+#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile");
+#endif
+volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcaRegsFile")
+#else
+#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile");
+#endif
+volatile struct ADC_REGS AdcaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcbRegsFile")
+#else
+#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile");
+#endif
+volatile struct ADC_REGS AdcbRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdccRegsFile")
+#else
+#pragma DATA_SECTION(AdccRegs,"AdccRegsFile");
+#endif
+volatile struct ADC_REGS AdccRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcdRegsFile")
+#else
+#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile");
+#endif
+volatile struct ADC_REGS AdcdRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcaResultRegsFile")
+#else
+#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultRegsFile");
+#endif
+volatile struct ADC_RESULT_REGS AdcaResultRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcbResultRegsFile")
+#else
+#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultRegsFile");
+#endif
+volatile struct ADC_RESULT_REGS AdcbResultRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdccResultRegsFile")
+#else
+#pragma DATA_SECTION(AdccResultRegs,"AdccResultRegsFile");
+#endif
+volatile struct ADC_RESULT_REGS AdccResultRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcdResultRegsFile")
+#else
+#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultRegsFile");
+#endif
+volatile struct ADC_RESULT_REGS AdcdResultRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("AnalogSubsysRegsFile")
+#else
+#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile");
+#endif
+volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("BgcrcCpuRegsFile")
+#else
+#pragma DATA_SECTION(BgcrcCpuRegs,"BgcrcCpuRegsFile");
+#endif
+volatile struct BGCRC_REGS BgcrcCpuRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("BgcrcCla1RegsFile")
+#else
+#pragma DATA_SECTION(BgcrcCla1Regs,"BgcrcCla1RegsFile");
+#endif
+volatile struct BGCRC_REGS BgcrcCla1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CanaRegsFile")
+#else
+#pragma DATA_SECTION(CanaRegs,"CanaRegsFile");
+#endif
+volatile struct CAN_REGS CanaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CanbRegsFile")
+#else
+#pragma DATA_SECTION(CanbRegs,"CanbRegsFile");
+#endif
+volatile struct CAN_REGS CanbRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cla1RegsFile")
+#else
+#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile");
+#endif
+volatile struct CLA_REGS Cla1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb1DataExchRegsFile")
+#else
+#pragma DATA_SECTION(Clb1DataExchRegs,"Clb1DataExchRegsFile");
+#endif
+volatile struct CLB_DATA_EXCHANGE_REGS Clb1DataExchRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb2DataExchRegsFile")
+#else
+#pragma DATA_SECTION(Clb2DataExchRegs,"Clb2DataExchRegsFile");
+#endif
+volatile struct CLB_DATA_EXCHANGE_REGS Clb2DataExchRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb3DataExchRegsFile")
+#else
+#pragma DATA_SECTION(Clb3DataExchRegs,"Clb3DataExchRegsFile");
+#endif
+volatile struct CLB_DATA_EXCHANGE_REGS Clb3DataExchRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb4DataExchRegsFile")
+#else
+#pragma DATA_SECTION(Clb4DataExchRegs,"Clb4DataExchRegsFile");
+#endif
+volatile struct CLB_DATA_EXCHANGE_REGS Clb4DataExchRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb5DataExchRegsFile")
+#else
+#pragma DATA_SECTION(Clb5DataExchRegs,"Clb5DataExchRegsFile");
+#endif
+volatile struct CLB_DATA_EXCHANGE_REGS Clb5DataExchRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb6DataExchRegsFile")
+#else
+#pragma DATA_SECTION(Clb6DataExchRegs,"Clb6DataExchRegsFile");
+#endif
+volatile struct CLB_DATA_EXCHANGE_REGS Clb6DataExchRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb7DataExchRegsFile")
+#else
+#pragma DATA_SECTION(Clb7DataExchRegs,"Clb7DataExchRegsFile");
+#endif
+volatile struct CLB_DATA_EXCHANGE_REGS Clb7DataExchRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb8DataExchRegsFile")
+#else
+#pragma DATA_SECTION(Clb8DataExchRegs,"Clb8DataExchRegsFile");
+#endif
+volatile struct CLB_DATA_EXCHANGE_REGS Clb8DataExchRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb1LogicCfgRegsFile")
+#else
+#pragma DATA_SECTION(Clb1LogicCfgRegs,"Clb1LogicCfgRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONFIG_REGS Clb1LogicCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb2LogicCfgRegsFile")
+#else
+#pragma DATA_SECTION(Clb2LogicCfgRegs,"Clb2LogicCfgRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONFIG_REGS Clb2LogicCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb3LogicCfgRegsFile")
+#else
+#pragma DATA_SECTION(Clb3LogicCfgRegs,"Clb3LogicCfgRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONFIG_REGS Clb3LogicCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb4LogicCfgRegsFile")
+#else
+#pragma DATA_SECTION(Clb4LogicCfgRegs,"Clb4LogicCfgRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONFIG_REGS Clb4LogicCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb5LogicCfgRegsFile")
+#else
+#pragma DATA_SECTION(Clb5LogicCfgRegs,"Clb5LogicCfgRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONFIG_REGS Clb5LogicCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb6LogicCfgRegsFile")
+#else
+#pragma DATA_SECTION(Clb6LogicCfgRegs,"Clb6LogicCfgRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONFIG_REGS Clb6LogicCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb7LogicCfgRegsFile")
+#else
+#pragma DATA_SECTION(Clb7LogicCfgRegs,"Clb7LogicCfgRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONFIG_REGS Clb7LogicCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb8LogicCfgRegsFile")
+#else
+#pragma DATA_SECTION(Clb8LogicCfgRegs,"Clb8LogicCfgRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONFIG_REGS Clb8LogicCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb1LogicCtrlRegsFile")
+#else
+#pragma DATA_SECTION(Clb1LogicCtrlRegs,"Clb1LogicCtrlRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONTROL_REGS Clb1LogicCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb2LogicCtrlRegsFile")
+#else
+#pragma DATA_SECTION(Clb2LogicCtrlRegs,"Clb2LogicCtrlRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONTROL_REGS Clb2LogicCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb3LogicCtrlRegsFile")
+#else
+#pragma DATA_SECTION(Clb3LogicCtrlRegs,"Clb3LogicCtrlRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONTROL_REGS Clb3LogicCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb4LogicCtrlRegsFile")
+#else
+#pragma DATA_SECTION(Clb4LogicCtrlRegs,"Clb4LogicCtrlRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONTROL_REGS Clb4LogicCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb5LogicCtrlRegsFile")
+#else
+#pragma DATA_SECTION(Clb5LogicCtrlRegs,"Clb5LogicCtrlRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONTROL_REGS Clb5LogicCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb6LogicCtrlRegsFile")
+#else
+#pragma DATA_SECTION(Clb6LogicCtrlRegs,"Clb6LogicCtrlRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONTROL_REGS Clb6LogicCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb7LogicCtrlRegsFile")
+#else
+#pragma DATA_SECTION(Clb7LogicCtrlRegs,"Clb7LogicCtrlRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONTROL_REGS Clb7LogicCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Clb8LogicCtrlRegsFile")
+#else
+#pragma DATA_SECTION(Clb8LogicCtrlRegs,"Clb8LogicCtrlRegsFile");
+#endif
+volatile struct CLB_LOGIC_CONTROL_REGS Clb8LogicCtrlRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CLBXbarRegsFile")
+#else
+#pragma DATA_SECTION(CLBXbarRegs,"CLBXbarRegsFile");
+#endif
+volatile struct CLB_XBAR_REGS CLBXbarRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ClkCfgRegsFile")
+#else
+#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile");
+#endif
+volatile struct CLK_CFG_REGS ClkCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cmpss1RegsFile")
+#else
+#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile");
+#endif
+volatile struct CMPSS_REGS Cmpss1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cmpss2RegsFile")
+#else
+#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile");
+#endif
+volatile struct CMPSS_REGS Cmpss2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cmpss3RegsFile")
+#else
+#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile");
+#endif
+volatile struct CMPSS_REGS Cmpss3Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cmpss4RegsFile")
+#else
+#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile");
+#endif
+volatile struct CMPSS_REGS Cmpss4Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cmpss5RegsFile")
+#else
+#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile");
+#endif
+volatile struct CMPSS_REGS Cmpss5Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cmpss6RegsFile")
+#else
+#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile");
+#endif
+volatile struct CMPSS_REGS Cmpss6Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cmpss7RegsFile")
+#else
+#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile");
+#endif
+volatile struct CMPSS_REGS Cmpss7Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cmpss8RegsFile")
+#else
+#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile");
+#endif
+volatile struct CMPSS_REGS Cmpss8Regs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CmConfRegsFile")
+#else
+#pragma DATA_SECTION(CmConfRegs,"CmConfRegsFile");
+#endif
+volatile struct CM_CONF_REGS CmConfRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cpu1toCmIpcRegsFile")
+#else
+#pragma DATA_SECTION(Cpu1toCmIpcRegs,"Cpu1toCmIpcRegsFile");
+#endif
+volatile struct CPU1TOCM_IPC_REGS_CPU1VIEW Cpu1toCmIpcRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cpu1toCpu2IpcRegsFile")
+#else
+#pragma DATA_SECTION(Cpu1toCpu2IpcRegs,"Cpu1toCpu2IpcRegsFile");
+#endif
+volatile struct CPU1TOCPU2_IPC_REGS_CPU1VIEW Cpu1toCpu2IpcRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU2
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cpu2toCpu1IpcRegsFile")
+#else
+#pragma DATA_SECTION(Cpu2toCpu1IpcRegs,"Cpu2toCpu1IpcRegsFile");
+#endif
+volatile struct CPU1TOCPU2_IPC_REGS_CPU2VIEW Cpu2toCpu1IpcRegs;
+#endif // ifdef CPU2
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SysPeriphAcRegsFile")
+#else
+#pragma DATA_SECTION(SysPeriphAcRegs,"SysPeriphAcRegsFile");
+#endif
+volatile struct CPU1_PERIPH_AC_REGS SysPeriphAcRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU2
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Cpu2toCmIpcRegsFile")
+#else
+#pragma DATA_SECTION(Cpu2toCmIpcRegs,"Cpu2toCmIpcRegsFile");
+#endif
+volatile struct CPU2TOCM_IPC_REGS_CPU2VIEW Cpu2toCmIpcRegs;
+#endif // ifdef CPU2
+
+#ifdef CPU2
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SysPeriphAcRegsFile")
+#else
+#pragma DATA_SECTION(SysPeriphAcRegs,"SysPeriphAcRegsFile");
+#endif
+volatile struct CPU2_PERIPH_AC_REGS SysPeriphAcRegs;
+#endif // ifdef CPU2
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuTimer0RegsFile")
+#else
+#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile");
+#endif
+volatile struct CPUTIMER_REGS CpuTimer0Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuTimer1RegsFile")
+#else
+#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile");
+#endif
+volatile struct CPUTIMER_REGS CpuTimer1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuTimer2RegsFile")
+#else
+#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile");
+#endif
+volatile struct CPUTIMER_REGS CpuTimer2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuSysRegsFile")
+#else
+#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile");
+#endif
+volatile struct CPU_SYS_REGS CpuSysRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DacaRegsFile")
+#else
+#pragma DATA_SECTION(DacaRegs,"DacaRegsFile");
+#endif
+volatile struct DAC_REGS DacaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DacbRegsFile")
+#else
+#pragma DATA_SECTION(DacbRegs,"DacbRegsFile");
+#endif
+volatile struct DAC_REGS DacbRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DaccRegsFile")
+#else
+#pragma DATA_SECTION(DaccRegs,"DaccRegsFile");
+#endif
+volatile struct DAC_REGS DaccRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Dcc0RegsFile")
+#else
+#pragma DATA_SECTION(Dcc0Regs,"Dcc0RegsFile");
+#endif
+volatile struct DCC_REGS Dcc0Regs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Dcc1RegsFile")
+#else
+#pragma DATA_SECTION(Dcc1Regs,"Dcc1RegsFile");
+#endif
+volatile struct DCC_REGS Dcc1Regs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Dcc2RegsFile")
+#else
+#pragma DATA_SECTION(Dcc2Regs,"Dcc2RegsFile");
+#endif
+volatile struct DCC_REGS Dcc2Regs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DcsmCommonRegsFile")
+#else
+#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile");
+#endif
+volatile struct DCSM_COMMON_REGS DcsmCommonRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DcsmZ1OtpRegsFile")
+#else
+#pragma DATA_SECTION(DcsmZ1OtpRegs,"DcsmZ1OtpRegsFile");
+#endif
+volatile struct DCSM_Z1_OTP DcsmZ1OtpRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DcsmZ1RegsFile")
+#else
+#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile");
+#endif
+volatile struct DCSM_Z1_REGS DcsmZ1Regs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DcsmZ2OtpRegsFile")
+#else
+#pragma DATA_SECTION(DcsmZ2OtpRegs,"DcsmZ2OtpRegsFile");
+#endif
+volatile struct DCSM_Z2_OTP DcsmZ2OtpRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DcsmZ2RegsFile")
+#else
+#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile");
+#endif
+volatile struct DCSM_Z2_REGS DcsmZ2Regs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DevCfgRegsFile")
+#else
+#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile");
+#endif
+volatile struct DEV_CFG_REGS DevCfgRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DmaClaSrcSelRegsFile")
+#else
+#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile");
+#endif
+volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("DmaRegsFile")
+#else
+#pragma DATA_SECTION(DmaRegs,"DmaRegsFile");
+#endif
+volatile struct DMA_REGS DmaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap1RegsFile")
+#else
+#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile");
+#endif
+volatile struct ECAP_REGS ECap1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap2RegsFile")
+#else
+#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile");
+#endif
+volatile struct ECAP_REGS ECap2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap3RegsFile")
+#else
+#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile");
+#endif
+volatile struct ECAP_REGS ECap3Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap4RegsFile")
+#else
+#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile");
+#endif
+volatile struct ECAP_REGS ECap4Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap5RegsFile")
+#else
+#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile");
+#endif
+volatile struct ECAP_REGS ECap5Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap6RegsFile")
+#else
+#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile");
+#endif
+volatile struct ECAP_REGS ECap6Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap7RegsFile")
+#else
+#pragma DATA_SECTION(ECap7Regs,"ECap7RegsFile");
+#endif
+volatile struct ECAP_REGS ECap7Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Emif1ConfigRegsFile")
+#else
+#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile");
+#endif
+volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Emif2ConfigRegsFile")
+#else
+#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile");
+#endif
+volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Emif1RegsFile")
+#else
+#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile");
+#endif
+volatile struct EMIF_REGS Emif1Regs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Emif2RegsFile")
+#else
+#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile");
+#endif
+volatile struct EMIF_REGS Emif2Regs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm1RegsFile")
+#else
+#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm2RegsFile")
+#else
+#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm3RegsFile")
+#else
+#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm3Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm4RegsFile")
+#else
+#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm4Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm5RegsFile")
+#else
+#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm5Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm6RegsFile")
+#else
+#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm6Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm7RegsFile")
+#else
+#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm7Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm8RegsFile")
+#else
+#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm8Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm9RegsFile")
+#else
+#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm9Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm10RegsFile")
+#else
+#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm10Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm11RegsFile")
+#else
+#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm11Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm12RegsFile")
+#else
+#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm12Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm13RegsFile")
+#else
+#pragma DATA_SECTION(EPwm13Regs,"EPwm13RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm13Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm14RegsFile")
+#else
+#pragma DATA_SECTION(EPwm14Regs,"EPwm14RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm14Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm15RegsFile")
+#else
+#pragma DATA_SECTION(EPwm15Regs,"EPwm15RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm15Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm16RegsFile")
+#else
+#pragma DATA_SECTION(EPwm16Regs,"EPwm16RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm16Regs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwmXbarRegsFile")
+#else
+#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile");
+#endif
+volatile struct EPWM_XBAR_REGS EPwmXbarRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EQep1RegsFile")
+#else
+#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile");
+#endif
+volatile struct EQEP_REGS EQep1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EQep2RegsFile")
+#else
+#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile");
+#endif
+volatile struct EQEP_REGS EQep2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EQep3RegsFile")
+#else
+#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile");
+#endif
+volatile struct EQEP_REGS EQep3Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCounter1RegsFile")
+#else
+#pragma DATA_SECTION(EradCounter1Regs,"EradCounter1RegsFile");
+#endif
+volatile struct ERAD_COUNTER_REGS EradCounter1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCounter2RegsFile")
+#else
+#pragma DATA_SECTION(EradCounter2Regs,"EradCounter2RegsFile");
+#endif
+volatile struct ERAD_COUNTER_REGS EradCounter2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCounter3RegsFile")
+#else
+#pragma DATA_SECTION(EradCounter3Regs,"EradCounter3RegsFile");
+#endif
+volatile struct ERAD_COUNTER_REGS EradCounter3Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCounter4RegsFile")
+#else
+#pragma DATA_SECTION(EradCounter4Regs,"EradCounter4RegsFile");
+#endif
+volatile struct ERAD_COUNTER_REGS EradCounter4Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCRCGlobalRegsFile")
+#else
+#pragma DATA_SECTION(EradCRCGlobalRegs,"EradCRCGlobalRegsFile");
+#endif
+volatile struct ERAD_CRC_GLOBAL_REGS EradCRCGlobalRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCRC1RegsFile")
+#else
+#pragma DATA_SECTION(EradCRC1Regs,"EradCRC1RegsFile");
+#endif
+volatile struct ERAD_CRC_REGS EradCRC1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCRC2RegsFile")
+#else
+#pragma DATA_SECTION(EradCRC2Regs,"EradCRC2RegsFile");
+#endif
+volatile struct ERAD_CRC_REGS EradCRC2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCRC3RegsFile")
+#else
+#pragma DATA_SECTION(EradCRC3Regs,"EradCRC3RegsFile");
+#endif
+volatile struct ERAD_CRC_REGS EradCRC3Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCRC4RegsFile")
+#else
+#pragma DATA_SECTION(EradCRC4Regs,"EradCRC4RegsFile");
+#endif
+volatile struct ERAD_CRC_REGS EradCRC4Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCRC5RegsFile")
+#else
+#pragma DATA_SECTION(EradCRC5Regs,"EradCRC5RegsFile");
+#endif
+volatile struct ERAD_CRC_REGS EradCRC5Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCRC6RegsFile")
+#else
+#pragma DATA_SECTION(EradCRC6Regs,"EradCRC6RegsFile");
+#endif
+volatile struct ERAD_CRC_REGS EradCRC6Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCRC7RegsFile")
+#else
+#pragma DATA_SECTION(EradCRC7Regs,"EradCRC7RegsFile");
+#endif
+volatile struct ERAD_CRC_REGS EradCRC7Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradCRC8RegsFile")
+#else
+#pragma DATA_SECTION(EradCRC8Regs,"EradCRC8RegsFile");
+#endif
+volatile struct ERAD_CRC_REGS EradCRC8Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradGlobalRegsFile")
+#else
+#pragma DATA_SECTION(EradGlobalRegs,"EradGlobalRegsFile");
+#endif
+volatile struct ERAD_GLOBAL_REGS EradGlobalRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradHWBP1RegsFile")
+#else
+#pragma DATA_SECTION(EradHWBP1Regs,"EradHWBP1RegsFile");
+#endif
+volatile struct ERAD_HWBP_REGS EradHWBP1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradHWBP2RegsFile")
+#else
+#pragma DATA_SECTION(EradHWBP2Regs,"EradHWBP2RegsFile");
+#endif
+volatile struct ERAD_HWBP_REGS EradHWBP2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradHWBP3RegsFile")
+#else
+#pragma DATA_SECTION(EradHWBP3Regs,"EradHWBP3RegsFile");
+#endif
+volatile struct ERAD_HWBP_REGS EradHWBP3Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradHWBP4RegsFile")
+#else
+#pragma DATA_SECTION(EradHWBP4Regs,"EradHWBP4RegsFile");
+#endif
+volatile struct ERAD_HWBP_REGS EradHWBP4Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradHWBP5RegsFile")
+#else
+#pragma DATA_SECTION(EradHWBP5Regs,"EradHWBP5RegsFile");
+#endif
+volatile struct ERAD_HWBP_REGS EradHWBP5Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradHWBP6RegsFile")
+#else
+#pragma DATA_SECTION(EradHWBP6Regs,"EradHWBP6RegsFile");
+#endif
+volatile struct ERAD_HWBP_REGS EradHWBP6Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradHWBP7RegsFile")
+#else
+#pragma DATA_SECTION(EradHWBP7Regs,"EradHWBP7RegsFile");
+#endif
+volatile struct ERAD_HWBP_REGS EradHWBP7Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EradHWBP8RegsFile")
+#else
+#pragma DATA_SECTION(EradHWBP8Regs,"EradHWBP8RegsFile");
+#endif
+volatile struct ERAD_HWBP_REGS EradHWBP8Regs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EscssConfigRegsFile")
+#else
+#pragma DATA_SECTION(EscssConfigRegs,"EscssConfigRegsFile");
+#endif
+volatile struct ESCSS_CONFIG_REGS EscssConfigRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("EscssRegsFile")
+#else
+#pragma DATA_SECTION(EscssRegs,"EscssRegsFile");
+#endif
+volatile struct ESCSS_REGS EscssRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Flash0CtrlRegsFile")
+#else
+#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile");
+#endif
+volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Flash0EccRegsFile")
+#else
+#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile");
+#endif
+volatile struct FLASH_ECC_REGS Flash0EccRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiRxaRegsFile")
+#else
+#pragma DATA_SECTION(FsiRxaRegs,"FsiRxaRegsFile");
+#endif
+volatile struct FSI_RX_REGS FsiRxaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiRxbRegsFile")
+#else
+#pragma DATA_SECTION(FsiRxbRegs,"FsiRxbRegsFile");
+#endif
+volatile struct FSI_RX_REGS FsiRxbRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiRxcRegsFile")
+#else
+#pragma DATA_SECTION(FsiRxcRegs,"FsiRxcRegsFile");
+#endif
+volatile struct FSI_RX_REGS FsiRxcRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiRxdRegsFile")
+#else
+#pragma DATA_SECTION(FsiRxdRegs,"FsiRxdRegsFile");
+#endif
+volatile struct FSI_RX_REGS FsiRxdRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiRxeRegsFile")
+#else
+#pragma DATA_SECTION(FsiRxeRegs,"FsiRxeRegsFile");
+#endif
+volatile struct FSI_RX_REGS FsiRxeRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiRxfRegsFile")
+#else
+#pragma DATA_SECTION(FsiRxfRegs,"FsiRxfRegsFile");
+#endif
+volatile struct FSI_RX_REGS FsiRxfRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiRxgRegsFile")
+#else
+#pragma DATA_SECTION(FsiRxgRegs,"FsiRxgRegsFile");
+#endif
+volatile struct FSI_RX_REGS FsiRxgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiRxhRegsFile")
+#else
+#pragma DATA_SECTION(FsiRxhRegs,"FsiRxhRegsFile");
+#endif
+volatile struct FSI_RX_REGS FsiRxhRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiTxaRegsFile")
+#else
+#pragma DATA_SECTION(FsiTxaRegs,"FsiTxaRegsFile");
+#endif
+volatile struct FSI_TX_REGS FsiTxaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("FsiTxbRegsFile")
+#else
+#pragma DATA_SECTION(FsiTxbRegs,"FsiTxbRegsFile");
+#endif
+volatile struct FSI_TX_REGS FsiTxbRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("GpioCtrlRegsFile")
+#else
+#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
+#endif
+volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("GpioDataReadRegsFile")
+#else
+#pragma DATA_SECTION(GpioDataReadRegs,"GpioDataReadRegsFile");
+#endif
+volatile struct GPIO_DATA_READ_REGS GpioDataReadRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("GpioDataRegsFile")
+#else
+#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile");
+#endif
+volatile struct GPIO_DATA_REGS GpioDataRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("HRCap6RegsFile")
+#else
+#pragma DATA_SECTION(HRCap6Regs,"HRCap6RegsFile");
+#endif
+volatile struct HRCAP_REGS HRCap6Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("HRCap7RegsFile")
+#else
+#pragma DATA_SECTION(HRCap7Regs,"HRCap7RegsFile");
+#endif
+volatile struct HRCAP_REGS HRCap7Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("I2caRegsFile")
+#else
+#pragma DATA_SECTION(I2caRegs,"I2caRegsFile");
+#endif
+volatile struct I2C_REGS I2caRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("I2cbRegsFile")
+#else
+#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile");
+#endif
+volatile struct I2C_REGS I2cbRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("InputXbarRegsFile")
+#else
+#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile");
+#endif
+volatile struct INPUT_XBAR_REGS InputXbarRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ClbInputXbarRegsFile")
+#else
+#pragma DATA_SECTION(ClbInputXbarRegs,"ClbInputXbarRegsFile");
+#endif
+volatile struct INPUT_XBAR_REGS ClbInputXbarRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("McanaSsRegsFile")
+#else
+#pragma DATA_SECTION(McanaSsRegs,"McanaSsRegsFile");
+#endif
+volatile struct MCANSS_REGS McanaSsRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("McanaErrRegsFile")
+#else
+#pragma DATA_SECTION(McanaErrRegs,"McanaErrRegsFile");
+#endif
+volatile struct MCAN_ERROR_REGS McanaErrRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("McanaRegsFile")
+#else
+#pragma DATA_SECTION(McanaRegs,"McanaRegsFile");
+#endif
+volatile struct MCAN_REGS McanaRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("MemoryErrorRegsFile")
+#else
+#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile");
+#endif
+volatile struct MEMORY_ERROR_REGS MemoryErrorRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("MemCfgRegsFile")
+#else
+#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile");
+#endif
+volatile struct MEM_CFG_REGS MemCfgRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("McbspaRegsFile")
+#else
+#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile");
+#endif
+volatile struct McBSP_REGS McbspaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("McbspbRegsFile")
+#else
+#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile");
+#endif
+volatile struct McBSP_REGS McbspbRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("NmiIntruptRegsFile")
+#else
+#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile");
+#endif
+volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("OutputXbarRegsFile")
+#else
+#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile");
+#endif
+volatile struct OUTPUT_XBAR_REGS OutputXbarRegs;
+#endif // ifdef CPU1
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ClbOutputXbarRegsFile")
+#else
+#pragma DATA_SECTION(ClbOutputXbarRegs,"ClbOutputXbarRegsFile");
+#endif
+volatile struct OUTPUT_XBAR_REGS ClbOutputXbarRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("PieCtrlRegsFile")
+#else
+#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile");
+#endif
+volatile struct PIE_CTRL_REGS PieCtrlRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("PieVectTableFile")
+#else
+#pragma DATA_SECTION(PieVectTable,"PieVectTableFile");
+#endif
+volatile struct PIE_VECT_TABLE PieVectTable;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("PmbusaRegsFile")
+#else
+#pragma DATA_SECTION(PmbusaRegs,"PmbusaRegsFile");
+#endif
+volatile struct PMBUS_REGS PmbusaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("RomPrefetchRegsFile")
+#else
+#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile");
+#endif
+volatile struct ROM_PREFETCH_REGS RomPrefetchRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("RomWaitStateRegsFile")
+#else
+#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile");
+#endif
+volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SciaRegsFile")
+#else
+#pragma DATA_SECTION(SciaRegs,"SciaRegsFile");
+#endif
+volatile struct SCI_REGS SciaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ScibRegsFile")
+#else
+#pragma DATA_SECTION(ScibRegs,"ScibRegsFile");
+#endif
+volatile struct SCI_REGS ScibRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ScicRegsFile")
+#else
+#pragma DATA_SECTION(ScicRegs,"ScicRegsFile");
+#endif
+volatile struct SCI_REGS ScicRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("ScidRegsFile")
+#else
+#pragma DATA_SECTION(ScidRegs,"ScidRegsFile");
+#endif
+volatile struct SCI_REGS ScidRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Sdfm1RegsFile")
+#else
+#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile");
+#endif
+volatile struct SDFM_REGS Sdfm1Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("Sdfm2RegsFile")
+#else
+#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile");
+#endif
+volatile struct SDFM_REGS Sdfm2Regs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SpiaRegsFile")
+#else
+#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile");
+#endif
+volatile struct SPI_REGS SpiaRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SpibRegsFile")
+#else
+#pragma DATA_SECTION(SpibRegs,"SpibRegsFile");
+#endif
+volatile struct SPI_REGS SpibRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SpicRegsFile")
+#else
+#pragma DATA_SECTION(SpicRegs,"SpicRegsFile");
+#endif
+volatile struct SPI_REGS SpicRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SpidRegsFile")
+#else
+#pragma DATA_SECTION(SpidRegs,"SpidRegsFile");
+#endif
+volatile struct SPI_REGS SpidRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SyncSocRegsFile")
+#else
+#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile");
+#endif
+volatile struct SYNC_SOC_REGS SyncSocRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("SysStatusRegsFile")
+#else
+#pragma DATA_SECTION(SysStatusRegs,"SysStatusRegsFile");
+#endif
+volatile struct SYS_STATUS_REGS SysStatusRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("TestErrorRegsFile")
+#else
+#pragma DATA_SECTION(TestErrorRegs,"TestErrorRegsFile");
+#endif
+volatile struct TEST_ERROR_REGS TestErrorRegs;
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("WdRegsFile")
+#else
+#pragma DATA_SECTION(WdRegs,"WdRegsFile");
+#endif
+volatile struct WD_REGS WdRegs;
+
+#ifdef CPU1
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("XbarRegsFile")
+#else
+#pragma DATA_SECTION(XbarRegs,"XbarRegsFile");
+#endif
+volatile struct XBAR_REGS XbarRegs;
+#endif // ifdef CPU1
+
+//----------------------------------------
+#ifdef __cplusplus
+#pragma DATA_SECTION("XintRegsFile")
+#else
+#pragma DATA_SECTION(XintRegs,"XintRegsFile");
+#endif
+volatile struct XINT_REGS XintRegs;
+
+
+
+//===========================================================================
+// End of file.
+//===========================================================================
+
+
diff --git a/Projects/epwm_test/lib/f2838x_gpio.c b/Projects/epwm_test/lib/f2838x_gpio.c
new file mode 100644
index 0000000..aca3330
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_gpio.c
@@ -0,0 +1,472 @@
+//###########################################################################
+//
+// FILE: f2838x_gpio.c
+//
+// TITLE: GPIO module support functions
+//
+//###########################################################################
+//
+//
+// $Copyright:
+// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "f2838x_device.h"
+#include "f2838x_examples.h"
+
+//
+//Low-level functions for GPIO configuration (CPU1 only)
+//
+
+#ifdef CPU1
+ //
+ // InitGpio - Sets all pins to be muxed to GPIO in input mode.
+ // Also resets CPU control to CPU1 and disables open
+ // drain and polarity inversion and sets the qualification to
+ // synchronous. Also unlocks all GPIOs. Only one CPU should call
+ // this function.
+ //
+ void InitGpio()
+ {
+ volatile Uint32 *gpioBaseAddr;
+ Uint16 regOffset;
+
+ //
+ //Disable pin locks
+ //
+ EALLOW;
+ GpioCtrlRegs.GPALOCK.all = 0x00000000;
+ GpioCtrlRegs.GPBLOCK.all = 0x00000000;
+ GpioCtrlRegs.GPCLOCK.all = 0x00000000;
+ GpioCtrlRegs.GPDLOCK.all = 0x00000000;
+ GpioCtrlRegs.GPELOCK.all = 0x00000000;
+ GpioCtrlRegs.GPFLOCK.all = 0x00000000;
+
+ //
+ // Fill all registers with zeros. Writing to each register separately
+ // for six GPIO modules would make this function *very* long.
+ // Fortunately, we'd be writing them all with zeros anyway, so this
+ // saves a lot of space.
+ //
+ gpioBaseAddr = (Uint32 *)&GpioCtrlRegs;
+ for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++)
+ {
+ //
+ //Hack to avoid enabling pull-ups on all pins. GPyPUD is offset
+ //0x0C in each register group of 0x40 words. Since this is a
+ //32-bit pointer, the addresses must be divided by 2.
+ //
+ if (regOffset % (0x40/2) != (0x0C/2))
+ {
+ gpioBaseAddr[regOffset] = 0x00000000;
+ }
+ }
+
+ gpioBaseAddr = (Uint32 *)&GpioDataRegs;
+ for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++)
+ {
+ gpioBaseAddr[regOffset] = 0x00000000;
+ }
+
+ EDIS;
+ }
+
+ //
+ // GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The
+ // appropriate parameters can be found in the GPIO Muxed
+ // Pins table(4.4) in the datasheet. Use the GPIO index
+ // row (0 to 15) to select a muxing option for the GPIO.
+ //
+ void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition)
+ {
+ volatile Uint32 *gpioBaseAddr;
+ volatile Uint32 *mux, *gmux, *csel;
+ Uint16 pin32, pin16, pin8;
+
+ pin32 = gpioNumber % 32;
+ pin16 = gpioNumber % 16;
+ pin8 = gpioNumber % 8;
+ gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
+
+ //
+ //Sanity check for valid cpu and peripheral values
+ //
+ if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF)
+ return;
+
+ //
+ //Create pointers to the appropriate registers. This is a workaround
+ //for the way GPIO registers are defined. The standard definition
+ //in the header file makes it very easy to do named accesses of one
+ //register or bit, but hard to do arbitrary numerical accesses. It's
+ //easier to have an array of GPIO modules with identical registers,
+ //including arrays for multi-register groups like GPyCSEL1-4. But
+ //the header file doesn't define anything we can turn into an array,
+ //so manual pointer arithmetic is used instead.
+ //
+ mux = gpioBaseAddr + GPYMUX + pin32/16;
+ gmux = gpioBaseAddr + GPYGMUX + pin32/16;
+ csel = gpioBaseAddr + GPYCSEL + pin32/8;
+
+ //
+ //Now for the actual function
+ //
+ EALLOW;
+
+ //
+ //To change the muxing, set the peripheral mux to 0/GPIO first to avoid
+ //glitches, then change the group mux, then set the peripheral mux to
+ //its target value. Finally, set the CPU select. This procedure is
+ //described in the TRM. Unfortunately, since we don't know the pin in
+ //advance we can't hardcode a bitfield reference, so there's some
+ //tricky bit twiddling here.
+ //
+ *mux &= ~(0x3UL << (2*pin16));
+ *gmux &= ~(0x3UL << (2*pin16));
+ *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16);
+ *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16);
+
+ *csel &= ~(0x3L << (4*pin8));
+ *csel |= (Uint32)(cpu & 0x3L) << (4*pin8);
+
+ //
+ //WARNING: This code does not touch the analog mode select registers,
+ //which are needed to give the USB module control of its IOs.
+ //
+ EDIS;
+ }
+
+ //
+ // GPIO_SetupPinOptions - Setup up the GPIO input/output options for the
+ // specified pin.
+ //
+ //The flags are a 16-bit mask produced by ORing together options.
+ //For input pins, the valid flags are:
+ //GPIO_PULLUP Enable pull-up
+ //GPIO_INVERT Enable input polarity inversion
+ //GPIO_SYNC Synchronize the input latch to PLLSYSCLK
+ // (default -- you don't need to specify this)
+ //GPIO_QUAL3 Use 3-sample qualification
+ //GPIO_QUAL6 Use 6-sample qualification
+ //GPIO_ASYNC Do not use synchronization or qualification
+ //(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed)
+ //
+ //For output pins, the valid flags are:
+ //GPIO_OPENDRAIN Output in open drain mode
+ //GPIO_PULLUP If open drain enabled, also enable the pull-up
+ //and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above.
+ //
+ //With no flags, the default input state is synchronous with no
+ //pull-up or polarity inversion. The default output state is
+ //the standard digital output.
+ //
+ void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags)
+ {
+ volatile Uint32 *gpioBaseAddr;
+ volatile Uint32 *dir, *pud, *inv, *odr, *qsel;
+ Uint32 pin32, pin16, pinMask, qual;
+
+ pin32 = gpioNumber % 32;
+ pin16 = gpioNumber % 16;
+ pinMask = 1UL << pin32;
+ gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
+
+ //
+ //Create pointers to the appropriate registers. This is a workaround
+ //for the way GPIO registers are defined. The standard definition
+ //in the header file makes it very easy to do named accesses of one
+ //register or bit, but hard to do arbitrary numerical accesses. It's
+ //easier to have an array of GPIO modules with identical registers,
+ //including arrays for multi-register groups like GPyQSEL1-2. But
+ //the header file doesn't define anything we can turn into an array,
+ //so manual pointer arithmetic is used instead.
+ //
+ dir = gpioBaseAddr + GPYDIR;
+ pud = gpioBaseAddr + GPYPUD;
+ inv = gpioBaseAddr + GPYINV;
+ odr = gpioBaseAddr + GPYODR;
+ qsel = gpioBaseAddr + GPYQSEL + pin32/16;
+
+ EALLOW;
+
+ //
+ //Set the data direction
+ //
+ *dir &= ~pinMask;
+ if (output == 1)
+ {
+ //
+ //Output, with optional open drain mode and pull-up
+ //
+ *dir |= pinMask;
+
+ //
+ //Enable open drain if necessary
+ //
+ if (flags & GPIO_OPENDRAIN)
+ {
+ *odr |= pinMask;
+ }
+ else
+ {
+ *odr &= ~pinMask;
+ }
+
+ //
+ //Enable pull-up if necessary. Open drain mode must be active.
+ //
+ if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP))
+ {
+ *pud &= ~pinMask;
+ }
+ else
+ {
+ *pud |= pinMask;
+ }
+ }
+ else
+ {
+ //
+ //Input, with optional pull-up, qualification, and polarity
+ //inversion
+ //
+ *dir &= ~pinMask;
+
+ //
+ //Enable pull-up if necessary
+ //
+ if (flags & GPIO_PULLUP)
+ {
+ *pud &= ~pinMask;
+ }
+ else
+ {
+ *pud |= pinMask;
+ }
+
+ //
+ //Invert polarity if necessary
+ //
+ if (flags & GPIO_INVERT)
+ {
+ *inv |= pinMask;
+ }
+ else
+ {
+ *inv &= ~pinMask;
+ }
+ }
+
+ //
+ //Extract the qualification parameter and load it into the register.
+ //This is also needed for open drain outputs, so we might as well do it
+ //all the time.
+ //
+ qual = (flags & GPIO_ASYNC) / GPIO_QUAL3;
+ *qsel &= ~(0x3L << (2 * pin16));
+ if (qual != 0x0)
+ {
+ *qsel |= qual << (2 * pin16);
+ }
+
+ EDIS;
+ }
+
+ //
+ // GPIO_SetupLock - Enable or disable the GPIO register bit lock for the
+ // specified pin.
+ // The valid flags are:
+ // GPIO_UNLOCK - Unlock the pin setup register bits for
+ // the specified pin
+ // GPIO_LOCK - Lock the pin setup register bits for the
+ // specified pin
+ //
+ void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags)
+ {
+ volatile Uint32 *gpioBaseAddr;
+ volatile Uint32 *lock;
+ Uint32 pin32, pinMask;
+
+ pin32 = gpioNumber % 32;
+ pinMask = 1UL << pin32;
+ gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
+
+ //
+ //Create pointers to the appropriate registers. This is a workaround
+ //for the way GPIO registers are defined. The standard definition
+ //in the header file makes it very easy to do named accesses of one
+ //register or bit, but hard to do arbitrary numerical accesses. It's
+ //easier to have an array of GPIO modules with identical registers,
+ //including arrays for multi-register groups like GPyQSEL1-2. But
+ //the header file doesn't define anything we can turn into an array,
+ //so manual pointer arithmetic is used instead.
+ //
+ lock = gpioBaseAddr + GPYLOCK;
+
+ EALLOW;
+ if(flags)
+ {
+ //Lock the pin
+ *lock |= pinMask;
+ }
+ else
+ {
+ //Unlock the pin
+ *lock &= ~pinMask;
+ }
+ EDIS;
+ }
+
+ //
+ //External interrupt setup
+ //
+ void GPIO_SetupXINT1Gpio(Uint16 gpioNumber)
+ {
+ EALLOW;
+ InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin
+ EDIS;
+ }
+ void GPIO_SetupXINT2Gpio(Uint16 gpioNumber)
+ {
+ EALLOW;
+ InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin
+ EDIS;
+ }
+ void GPIO_SetupXINT3Gpio(Uint16 gpioNumber)
+ {
+ EALLOW;
+ InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin
+ EDIS;
+ }
+ void GPIO_SetupXINT4Gpio(Uint16 gpioNumber)
+ {
+ EALLOW;
+ InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin
+ EDIS;
+ }
+ void GPIO_SetupXINT5Gpio(Uint16 gpioNumber)
+ {
+ EALLOW;
+ InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin
+ EDIS;
+ }
+
+ //
+ //GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded
+ // GPIOs on the 176PTP package:
+ // GPIOs Grp Bits
+ // 95-132 C 31
+ // D 31:0
+ // E 4:0
+ // 134-168 E 31:6
+ // F 8:0
+ //
+ void GPIO_EnableUnbondedIOPullupsFor176Pin()
+ {
+ EALLOW;
+ GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95
+ GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127
+ GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133
+ GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168
+ EDIS;
+ }
+
+ //
+ // GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function
+ // this takes care of enabling IO pullups.
+ //
+ void GPIO_EnableUnbondedIOPullups()
+ {
+ //
+ //bits 8-10 have pin count
+ //
+ unsigned char pin_count = (DevCfgRegs.PARTIDL.bit.PIN_COUNT) ;
+
+ //
+ //6 = 176 pin
+ //7 = 337 pin
+ //
+ if (pin_count == 6)
+ {
+ GPIO_EnableUnbondedIOPullupsFor176Pin();
+ }
+ else
+ {
+ //do nothing - this is 337 pin package
+ }
+ }
+
+#endif //CPU1
+
+//
+// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that
+// this returns the actual state of the pin, not the state of
+// the output latch.
+//
+Uint16 GPIO_ReadPin(Uint16 gpioNumber)
+{
+ volatile Uint32 *gpioDataReg;
+ Uint16 pinVal;
+
+ gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET;
+ pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1;
+
+ return pinVal;
+}
+
+//
+// GPIO_WritePin - Set the GPyDAT register bit for the specified pin.
+//
+void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal)
+{
+ volatile Uint32 *gpioDataReg;
+ Uint32 pinMask;
+
+ gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET;
+ pinMask = 1UL << (gpioNumber % 32);
+
+ if (outVal == 0)
+ {
+ gpioDataReg[GPYCLEAR] = pinMask;
+ }
+ else
+ {
+ gpioDataReg[GPYSET] = pinMask;
+ }
+}
+
+//
+// End of file
+//
diff --git a/Projects/epwm_test/lib/f2838x_piectrl.c b/Projects/epwm_test/lib/f2838x_piectrl.c
new file mode 100644
index 0000000..3fbd8a5
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_piectrl.c
@@ -0,0 +1,121 @@
+//###########################################################################
+//
+// FILE: f2838x_piectrl.c
+//
+// TITLE: F2838x Device PIE Control Register Initialization Functions.
+//
+//###########################################################################
+//
+//
+// $Copyright:
+// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "f2838x_device.h" // F2838x Headerfile Include File
+#include "f2838x_examples.h" // F2838x Examples Include File
+
+//
+// InitPieCtrl - This function initializes the PIE control registers to a
+// known state.
+//
+void InitPieCtrl(void)
+{
+ //
+ // Disable Interrupts at the CPU level:
+ //
+ DINT;
+
+ //
+ // Disable the PIE
+ //
+ PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
+
+ //
+ // Clear all PIEIER registers:
+ //
+ PieCtrlRegs.PIEIER1.all = 0;
+ PieCtrlRegs.PIEIER2.all = 0;
+ PieCtrlRegs.PIEIER3.all = 0;
+ PieCtrlRegs.PIEIER4.all = 0;
+ PieCtrlRegs.PIEIER5.all = 0;
+ PieCtrlRegs.PIEIER6.all = 0;
+ PieCtrlRegs.PIEIER7.all = 0;
+ PieCtrlRegs.PIEIER8.all = 0;
+ PieCtrlRegs.PIEIER9.all = 0;
+ PieCtrlRegs.PIEIER10.all = 0;
+ PieCtrlRegs.PIEIER11.all = 0;
+ PieCtrlRegs.PIEIER12.all = 0;
+
+ //
+ // Clear all PIEIFR registers:
+ //
+ PieCtrlRegs.PIEIFR1.all = 0;
+ PieCtrlRegs.PIEIFR2.all = 0;
+ PieCtrlRegs.PIEIFR3.all = 0;
+ PieCtrlRegs.PIEIFR4.all = 0;
+ PieCtrlRegs.PIEIFR5.all = 0;
+ PieCtrlRegs.PIEIFR6.all = 0;
+ PieCtrlRegs.PIEIFR7.all = 0;
+ PieCtrlRegs.PIEIFR8.all = 0;
+ PieCtrlRegs.PIEIFR9.all = 0;
+ PieCtrlRegs.PIEIFR10.all = 0;
+ PieCtrlRegs.PIEIFR11.all = 0;
+ PieCtrlRegs.PIEIFR12.all = 0;
+}
+
+//
+// EnableInterrupts - This function enables the PIE module and CPU __interrupts
+//
+void EnableInterrupts()
+{
+ //
+ // Enable the PIE
+ //
+ PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
+
+ //
+ // Enables PIE to drive a pulse into the CPU
+ //
+ PieCtrlRegs.PIEACK.all = 0xFFFF;
+
+ //
+ // Enable Interrupts at the CPU level
+ //
+ EINT;
+}
+
+//
+// End of file
+//
diff --git a/Projects/epwm_test/lib/f2838x_pievect.c b/Projects/epwm_test/lib/f2838x_pievect.c
new file mode 100644
index 0000000..5f0d7cb
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_pievect.c
@@ -0,0 +1,309 @@
+//###########################################################################
+//
+// FILE: f2838x_pievect.c
+//
+// TITLE: f2838x Device PIE Vector Initialization Functions
+//
+//###########################################################################
+// $Copyright:
+// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "f2838x_device.h" // f2838x Header File Include File
+#include "f2838x_examples.h" // f2838x Examples Include File
+
+//
+// Globals
+//
+const struct PIE_VECT_TABLE PieVectTableInit = {
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ PIE_RESERVED_ISR, // Reserved
+ TIMER1_ISR, // CPU Timer 1 Interrupt
+ TIMER2_ISR, // CPU Timer 2 Interrupt
+ DATALOG_ISR, // Datalogging Interrupt
+ RTOS_ISR, // RTOS Interrupt
+ EMU_ISR, // Emulation Interrupt
+ NMI_ISR, // Non-Maskable Interrupt
+ ILLEGAL_ISR, // Illegal Operation Trap
+ USER1_ISR, // User Defined Trap 1
+ USER2_ISR, // User Defined Trap 2
+ USER3_ISR, // User Defined Trap 3
+ USER4_ISR, // User Defined Trap 4
+ USER5_ISR, // User Defined Trap 5
+ USER6_ISR, // User Defined Trap 6
+ USER7_ISR, // User Defined Trap 7
+ USER8_ISR, // User Defined Trap 8
+ USER9_ISR, // User Defined Trap 9
+ USER10_ISR, // User Defined Trap 10
+ USER11_ISR, // User Defined Trap 11
+ USER12_ISR, // User Defined Trap 12
+ ADCA1_ISR, // 1.1 - ADCA Interrupt 1
+ ADCB1_ISR, // 1.2 - ADCB Interrupt 1
+ ADCC1_ISR, // 1.3 - ADCC Interrupt 1
+ XINT1_ISR, // 1.4 - XINT1 Interrupt
+ XINT2_ISR, // 1.5 - XINT2 Interrupt
+ ADCD1_ISR, // 1.6 - ADCD Interrupt 1
+ TIMER0_ISR, // 1.7 - Timer 0 Interrupt
+ WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt
+ EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt
+ EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt
+ EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt
+ EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt
+ EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt
+ EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt
+ EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt
+ EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt
+ EPWM1_ISR, // 3.1 - ePWM1 Interrupt
+ EPWM2_ISR, // 3.2 - ePWM2 Interrupt
+ EPWM3_ISR, // 3.3 - ePWM3 Interrupt
+ EPWM4_ISR, // 3.4 - ePWM4 Interrupt
+ EPWM5_ISR, // 3.5 - ePWM5 Interrupt
+ EPWM6_ISR, // 3.6 - ePWM6 Interrupt
+ EPWM7_ISR, // 3.7 - ePWM7 Interrupt
+ EPWM8_ISR, // 3.8 - ePWM8 Interrupt
+ ECAP1_ISR, // 4.1 - eCAP1 Interrupt
+ ECAP2_ISR, // 4.2 - eCAP2 Interrupt
+ ECAP3_ISR, // 4.3 - eCAP3 Interrupt
+ ECAP4_ISR, // 4.4 - eCAP4 Interrupt
+ ECAP5_ISR, // 4.5 - eCAP5 Interrupt
+ ECAP6_ISR, // 4.6 - eCAP6 Interrupt
+ ECAP7_ISR, // 4.7 - eCAP7 Interrupt
+ PIE_RESERVED_ISR, // 4.8 - Reserved
+ EQEP1_ISR, // 5.1 - eQEP1 Interrupt
+ EQEP2_ISR, // 5.2 - eQEP2 Interrupt
+ EQEP3_ISR, // 5.3 - eQEP3 Interrupt
+ PIE_RESERVED_ISR, // 5.4 - Reserved
+ CLB1_ISR, // 5.5 - CLB1 (Reconfigurable Logic) Interrupt
+ CLB2_ISR, // 5.6 - CLB2 (Reconfigurable Logic) Interrupt
+ CLB3_ISR, // 5.7 - CLB3 (Reconfigurable Logic) Interrupt
+ CLB4_ISR, // 5.8 - CLB4 (Reconfigurable Logic) Interrupt
+ SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt
+ SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt
+ SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt
+ SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt
+ MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt
+ MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt
+ MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt
+ MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt
+ DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt
+ DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt
+ DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt
+ DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt
+ DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt
+ DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt
+ PIE_RESERVED_ISR, // 7.7 - Reserved
+ PIE_RESERVED_ISR, // 7.8 - Reserved
+ I2CA_ISR, // 8.1 - I2CA Interrupt 1
+ I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2
+ I2CB_ISR, // 8.3 - I2CB Interrupt 1
+ I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2
+ SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt
+ SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt
+ SCID_RX_ISR, // 8.7 - SCID Receive Interrupt
+ SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt
+ SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt
+ SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt
+ SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt
+ SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt
+ CANA0_ISR, // 9.5 - CANA Interrupt 0
+ CANA1_ISR, // 9.6 - CANA Interrupt 1
+ CANB0_ISR, // 9.7 - CANB Interrupt 0
+ CANB1_ISR, // 9.8 - CANB Interrupt 1
+ ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt
+ ADCA2_ISR, // 10.2 - ADCA Interrupt 2
+ ADCA3_ISR, // 10.3 - ADCA Interrupt 3
+ ADCA4_ISR, // 10.4 - ADCA Interrupt 4
+ ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt
+ ADCB2_ISR, // 10.6 - ADCB Interrupt 2
+ ADCB3_ISR, // 10.7 - ADCB Interrupt 3
+ ADCB4_ISR, // 10.8 - ADCB Interrupt 4
+ CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1
+ CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2
+ CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3
+ CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4
+ CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5
+ CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6
+ CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7
+ CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8
+ XINT3_ISR, // 12.1 - XINT3 Interrupt
+ XINT4_ISR, // 12.2 - XINT4 Interrupt
+ XINT5_ISR, // 12.3 - XINT5 Interrupt
+ MPOST_ISR, // 12.4 - MPOST Interrupt
+ FMC_ISR, // 12.5 - Flash Wrapper Operation Done Interrupt
+ PIE_RESERVED_ISR, // 12.6 - Reserved
+ FPU_OFLOW_ISR, // 12.7 - FPU Overflow Interrupt
+ FPU_UFLOW_ISR, // 12.8 - FPU Underflow Interrupt
+ I2CA_HIGH_ISR, // 1.9 - I2CA Interrupt high priority
+ SYS_ERR_ISR, // 1.10 - System error interrupt
+ ECATSYNC0_ISR, // 1.11 - ETHERCAT SYNC0 interrupt
+ ECAT_ISR, // 1.12 - ETHERCAT main interrupt
+ CIPC0_ISR, // 1.13 - C28x CPU IPC interrupt 1
+ CIPC1_ISR, // 1.14 - C28x CPU IPC interrupt 2
+ CIPC2_ISR, // 1.15 - C28x CPU IPC interrupt 3
+ CIPC3_ISR, // 1.16 - C28x CPU IPC interrupt 4
+ EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt
+ EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt
+ EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt
+ EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt
+ EPWM13_TZ_ISR, // 2.13 - ePWM13 Trip Zone Interrupt
+ EPWM14_TZ_ISR, // 2.14 - ePWM14 Trip Zone Interrupt
+ EPWM15_TZ_ISR, // 2.15 - ePWM15 Trip Zone Interrupt
+ EPWM16_TZ_ISR, // 2.16 - ePWM16 Trip Zone Interrupt
+ EPWM9_ISR, // 3.9 - ePWM9 Interrupt
+ EPWM10_ISR, // 3.10 - ePWM10 Interrupt
+ EPWM11_ISR, // 3.11 - ePWM11 Interrupt
+ EPWM12_ISR, // 3.12 - ePWM12 Interrupt
+ EPWM13_ISR, // 3.13 - ePWM13 Interrupt
+ EPWM14_ISR, // 3.14 - ePWM14 Interrupt
+ EPWM15_ISR, // 3.15 - ePWM15 Interrupt
+ EPWM16_ISR, // 3.16 - ePWM16 Interrupt
+ FSITXA1_ISR, // 4.9 - FSIA Transmit interrupt 1
+ FSITXA2_ISR, // 4.10 - FSIA Transmit interrupt 2
+ FSITXB1_ISR, // 4.11 - FSIB Transmit interrupt 1
+ FSITXB2_ISR, // 4.12 - FSIB Transmit interrupt 2
+ FSIRXA1_ISR, // 4.13 - FSIA Receive interrupt 1
+ FSIRXA2_ISR, // 4.14 - FSIA Receive interrupt 2
+ FSIRXB1_ISR, // 4.15 - FSIB Receive interrupt 1
+ FSIRXB2_ISR, // 4.16 - FSIB Receive interrupt 2
+ SDFM1_ISR, // 5.9 - Sigma Delta Filter Module1 Interrupt
+ SDFM2_ISR, // 5.10 - Sigma Delta Filter Module2 Interrupt
+ ECATRST_ISR, // 5.11 - ETHERCAT Resetout Interrupt
+ ECATSYNC1_ISR, // 5.12 - ETHERCAT SYNC1 interrupt
+ SDFM1DR1_ISR, // 5.13 - Sigma Delta Filter Module1 Filter 1 Interrupt
+ SDFM1DR2_ISR, // 5.14 - Sigma Delta Filter Module1 Filter 2 Interrupt
+ SDFM1DR3_ISR, // 5.15 - Sigma Delta Filter Module1 Filter 3 Interrupt
+ SDFM1DR4_ISR, // 5.16 - Sigma Delta Filter Module1 Filter 4 Interrupt
+ SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt
+ SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt
+ SPID_RX_ISR, // 6.11 - SPID Receive Interrupt
+ SPID_TX_ISR, // 6.12 - SPID Transmit Interrupt
+ SDFM2DR1_ISR, // 6.13 - Sigma Delta Filter Module2 Filter 1 Interrupt
+ SDFM2DR2_ISR, // 6.14 - Sigma Delta Filter Module2 Filter 2 Interrupt
+ SDFM2DR3_ISR, // 6.15 - Sigma Delta Filter Module2 Filter 3 Interrupt
+ SDFM2DR4_ISR, // 6.16 - Sigma Delta Filter Module2 Filter 4 Interrupt
+ FSIRXC1_ISR, // 7.9 - FSIC Receive interrupt 1
+ FSIRXC2_ISR, // 7.10 - FSIC Receive interrupt 2
+ FSIRXD1_ISR, // 7.11 - FSID Receive interrupt 1
+ FSIRXD2_ISR, // 7.12 - FSID Receive interrupt 2
+ FSIRXE1_ISR, // 7.13 - FSIE Receive interrupt 1
+ FSIRXE2_ISR, // 7.14 - FSIE Receive interrupt 2
+ FSIRXF1_ISR, // 7.15 - FSIF Receive interrupt 1
+ FSIRXF2_ISR, // 7.16 - FSIF Receive interrupt 2
+ FSIRXG1_ISR, // 8.9 - FSIG Receive interrupt 1
+ FSIRXG2_ISR, // 8.10 - FSIG Receive interrupt 2
+ FSIRXH1_ISR, // 8.11 - FSIH Receive interrupt 1
+ FSIRXH2_ISR, // 8.12 - FSIH Receive interrupt 2
+ CLB5_ISR, // 8.13 - CLB5 Interrupt
+ CLB6_ISR, // 8.14 - CLB6 Interrupt
+ CLB7_ISR, // 8.15 - CLB7 Interrupt
+ CLB8_ISR, // 8.16 - CLB8 Interrupt
+ MCANA_0_ISR, // 9.9 - MCAN Sub-System Interrupt 0
+ MCANA_1_ISR, // 9.10 - MCAN Sub-System Interrupt 1
+ MCANA_ECC_ISR, // 9.11 - MCAN Sub-System ECC error Interrupt
+ MCANA_WAKE_ISR, // 9.12 - MCAN Sub-System wakeup Interrupt
+ PMBUSA_ISR, // 9.13 - PMBUSA Interrupt
+ CM_STATUS_ISR, // 9.14 - CM Reset Status Interrupt
+ USBA_ISR, // 9.15 - USBA Interrupt
+ PIE_RESERVED_ISR, // 9.16 - Reserved
+ ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt
+ ADCC2_ISR, // 10.10 - ADCC Interrupt 2
+ ADCC3_ISR, // 10.11 - ADCC Interrupt 3
+ ADCC4_ISR, // 10.12 - ADCC Interrupt 4
+ ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt
+ ADCD2_ISR, // 10.14 - ADCD Interrupt 2
+ ADCD3_ISR, // 10.15 - ADCD Interrupt 3
+ ADCD4_ISR, // 10.16 - ADCD Interrupt 4
+ CMTOCPUXIPC0_ISR, // 11.9 - CM to CPU IPC Interrupt 0
+ CMTOCPUXIPC1_ISR, // 11.10 - CM to CPU IPC Interrupt 1
+ CMTOCPUXIPC2_ISR, // 11.11 - CM to CPU IPC Interrupt 2
+ CMTOCPUXIPC3_ISR, // 11.12 - CM to CPU IPC Interrupt 3
+ CMTOCPUXIPC4_ISR, // 11.13 - CM to CPU IPC Interrupt 4
+ CMTOCPUXIPC5_ISR, // 11.14 - CM to CPU IPC Interrupt 5
+ CMTOCPUXIPC6_ISR, // 11.15 - CM to CPU IPC Interrupt 6
+ CMTOCPUXIPC7_ISR, // 11.16 - CM to CPU IPC Interrupt 7
+ PIE_RESERVED_ISR, // 12.9 - Reserved
+ ECAP6_2_ISR, // 12.10 - eCAP6 Interrupt 2
+ ECAP7_2_ISR, // 12.11 - eCAP7 Interrupt 2
+ PIE_RESERVED_ISR, // 12.12 - Reserved
+ CPUCRC_ISR, // 12.13 - CPU BGCRC module interrupt
+ CLA1CRC_ISR, // 12.14 - CLA1 BGCRC module interrupt
+ CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt
+ CLA_UNDERFLOW_ISR, // 12.16 - CLA Underflow Interrupt
+};
+
+//
+// InitPieVectTable - This function initializes the PIE vector table to a
+// known state and must be executed after boot time.
+//
+void InitPieVectTable(void)
+{
+ Uint16 i;
+ Uint32 *Source = (void *) &PieVectTableInit;
+ Uint32 *Dest = (void *) &PieVectTable;
+
+ //
+ // Do not write over first 3 32-bit locations (these locations are
+ // initialized by Boot ROM with boot variables)
+ //
+ Source = Source + 3;
+ Dest = Dest + 3;
+
+ EALLOW;
+ for(i = 0; i < 221; i++)
+ {
+ *Dest++ = *Source++;
+ }
+ EDIS;
+
+ //
+ // Enable the PIE Vector Table
+ //
+ PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
+}
+
+//
+// End of file
+//
diff --git a/Projects/epwm_test/lib/f2838x_sdfm_drivers.c b/Projects/epwm_test/lib/f2838x_sdfm_drivers.c
new file mode 100644
index 0000000..540fe13
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_sdfm_drivers.c
@@ -0,0 +1,568 @@
+//###########################################################################
+//
+// FILE: f2838x_sdfm_drivers.c
+//
+// TITLE: SDFM Driver functions
+//
+//###########################################################################
+//
+//
+// $Copyright:
+// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "f28x_project.h"
+#include "f2838x_struct.h"
+#include "f2838x_sdfm_drivers.h"
+
+//
+// Sdfm_configureInputCtrl - This function configures SDFM Input control unit.
+// sdfmNumber - This parameter should be used to
+// select SDFM1 (or) SDFM2
+// filterNumber - This parameter is used to select
+// which filter (FILTER1,FILTER2,
+// FILTER3,FILTER4) needs to be
+// configured.
+// mode - This parameter is used to select
+// one of the modes mentioned above
+//
+// Input control unit can be configured in four different modes:
+// MODE_0 : Modulator clock rate = Modulator data rate
+// MODE_1 : Modulator clock rate = (Modulator data rate / 2)
+// MODE_2 : Manchester encoded data (Modulator clock is encoded into data)
+// MODE_3 : Modulator clock rate = (2 x Modulator data rate)
+//
+void Sdfm_configureInputCtrl(Uint16 sdfmNumber, Uint16 filterNumber,
+ Uint16 mode)
+{
+ EALLOW;
+
+ switch (filterNumber)
+ {
+ case FILTER1:
+ (*SDFM[sdfmNumber]).SDCTLPARM1.bit.MOD = mode;
+ break;
+
+ case FILTER2:
+ (*SDFM[sdfmNumber]).SDCTLPARM2.bit.MOD = mode;
+ break;
+
+ case FILTER3:
+ (*SDFM[sdfmNumber]).SDCTLPARM3.bit.MOD = mode;
+ break;
+
+ case FILTER4:
+ (*SDFM[sdfmNumber]).SDCTLPARM4.bit.MOD = mode;
+ break;
+ }
+
+ EDIS;
+}
+
+//
+// Sdfm_configureComparator - This function configures SDFM Comparator unit.
+// Comparator unit can be configured to monitor
+// input conditions with a fast settling time.
+// This module can be programmed to detect over and
+// under value conditions.
+//
+// sdfmNumber - This parameter should be used to
+// select SDFM1 (or) SDFM2
+// filterNumber - This parameter is used to select
+// which filter (FILTER1,FILTER2,
+// FILTER3,FILTER3)
+// filterType - This parameter is used to select
+// one of the filter type mentioned
+// above (SINC1,SINC2,SINC3,SINCFAST)
+// OSR - This parameter is used to
+// configure oversampling ratio for
+// comparator
+// HLT - This parameter is used to
+// configure to detect over value
+// condition. The upper 16-bits denote
+// high threshold 2 values while lower
+// 16-bits denote high threshold 1
+// values
+// LLT - This parameter is used to
+// configure to detect under value
+// condition.The upper 16-bits denote
+// low threshold 2 values while lower
+// 16-bits denote low threshold 1
+// values
+//
+void Sdfm_configureComparator(Uint16 sdfmNumber, Uint16 filterNumber,
+ Uint16 filterType, Uint16 OSR, Uint32 HLT,
+ Uint32 LLT)
+{
+ EALLOW;
+
+ switch (filterNumber)
+ {
+ case FILTER1: //Filter 1
+
+ //
+ // Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3
+ //
+ (*SDFM[sdfmNumber]).SDCPARM1.bit.CS1_CS0 = filterType;
+
+ //
+ // Configure OSR value
+ //
+ if(OSR<=COMPARATOR_MAX_OSR)
+ {
+ (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = OSR;
+ }
+ else
+ {
+ (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = COMPARATOR_MAX_OSR;
+ }
+
+ (*SDFM[sdfmNumber]).SDFLT1CMPH1.bit.HLT = (Uint16)HLT;
+ (*SDFM[sdfmNumber]).SDFLT1CMPL1.bit.LLT = (Uint16)LLT;
+ (*SDFM[sdfmNumber]).SDFLT1CMPH2.bit.HLT2 = (Uint16)(HLT >> 16U);
+ (*SDFM[sdfmNumber]).SDFLT1CMPL2.bit.LLT2 = (Uint16)(LLT >> 16U);
+ break;
+
+ case FILTER2: //Filter 2
+ //
+ // Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3
+ //
+ (*SDFM[sdfmNumber]).SDCPARM2.bit.CS1_CS0 = filterType;
+
+ //
+ // Configure OSR value
+ //
+ if(OSR<=COMPARATOR_MAX_OSR)
+ {
+ (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = OSR;
+ }
+ else
+ {
+ (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = COMPARATOR_MAX_OSR;
+ }
+
+ (*SDFM[sdfmNumber]).SDFLT2CMPH1.bit.HLT = (Uint16)HLT;
+ (*SDFM[sdfmNumber]).SDFLT2CMPL1.bit.LLT = (Uint16)LLT;
+ (*SDFM[sdfmNumber]).SDFLT2CMPH2.bit.HLT2 = (Uint16)(HLT >> 16U);
+ (*SDFM[sdfmNumber]).SDFLT2CMPL2.bit.LLT2 = (Uint16)(LLT >> 16U);
+ break;
+
+ case FILTER3: //Filter 3
+ //
+ // Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3
+ //
+ (*SDFM[sdfmNumber]).SDCPARM3.bit.CS1_CS0 = filterType;
+
+ //
+ // Configure OSR value
+ //
+ if(OSR<=COMPARATOR_MAX_OSR)
+ {
+ (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = OSR;
+ }
+ else
+ {
+ (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = COMPARATOR_MAX_OSR;
+ }
+
+ (*SDFM[sdfmNumber]).SDFLT3CMPH1.bit.HLT = (Uint16)HLT;
+ (*SDFM[sdfmNumber]).SDFLT3CMPL1.bit.LLT = (Uint16)LLT;
+ (*SDFM[sdfmNumber]).SDFLT3CMPH2.bit.HLT2 = (Uint16)(HLT >> 16U);
+ (*SDFM[sdfmNumber]).SDFLT3CMPL2.bit.LLT2 = (Uint16)(LLT >> 16U);
+ break;
+
+ case FILTER4: //Filter 4
+ //
+ // Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3
+ //
+ (*SDFM[sdfmNumber]).SDCPARM4.bit.CS1_CS0 = filterType;
+
+ //
+ // Configure Comparator OSR value
+ //
+ if(OSR<=COMPARATOR_MAX_OSR)
+ {
+ (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = OSR;
+ }
+ else
+ {
+ (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = COMPARATOR_MAX_OSR;
+ }
+
+ (*SDFM[sdfmNumber]).SDFLT4CMPH1.bit.HLT = (Uint16)HLT;
+ (*SDFM[sdfmNumber]).SDFLT4CMPL1.bit.LLT = (Uint16)LLT;
+ (*SDFM[sdfmNumber]).SDFLT4CMPH2.bit.HLT2 = (Uint16)(HLT >> 16U);
+ (*SDFM[sdfmNumber]).SDFLT4CMPL2.bit.LLT2 = (Uint16)(LLT >> 16U);
+ break;
+ }
+
+ EDIS;
+}
+
+
+//
+// SDFM_configureData_filter - This function configures SDFM Data filter unit
+//
+// SDFM Data filter unit can be configured in any
+// of four different Sinc filter types:
+// sdfmNumber - This parameter should be used to
+// select SDFM1 (or) SDFM2
+// filterNumber - This parameter is used to select
+// which filter(FILTER1,FILTER2,
+// FILTER3,FILTER3) needs to be
+// configured
+// Filter_switch - This parameter is used to
+// enable/disable a filter
+// filterType - This parameter is used to select
+// one of the filter type mentioned
+// above (SINC1 / SINC2 / SINC3 /
+// SINCFAST)
+// OSR - This parameter is used to
+// configure oversampling ratio
+// for Data filter (Upto OSR_256)
+// DR_switch - This parameter selects whether
+// data is represented in 16 (or)
+// 32 bits
+// shift_bits - When user chooses 16 bit
+// representation, this variable
+// allows to right shift by
+// specific number of bits
+//
+void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber,
+ Uint16 Filter_switch, Uint16 filterType,
+ Uint16 OSR, Uint16 DR_switch, Uint16 shift_bits)
+{
+ EALLOW;
+
+ switch(filterNumber)
+ {
+
+ case FILTER1: //Filter 1
+ (*SDFM[sdfmNumber]).SDDFPARM1.bit.FEN = Filter_switch;
+ (*SDFM[sdfmNumber]).SDDFPARM1.bit.SST = filterType;
+
+ //
+ // Configure Sinc filter OSR value
+ //
+ if(OSR<=DATA_FILTER_MAX_OSR)
+ {
+ (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = OSR;
+ }
+ else
+ {
+ (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = DATA_FILTER_MAX_OSR;
+ }
+
+ //
+ // Configure Data filter data representation
+ // DR_switch - Data Representation (0/1 = 16/32b 2's complement)
+ //
+ (*SDFM[sdfmNumber]).SDDPARM1.bit.DR = DR_switch;
+ if(DR_switch == 0)
+ {
+ (*SDFM[sdfmNumber]).SDDPARM1.bit.SH = shift_bits;
+ }
+
+ break;
+
+ case FILTER2: //Filter 2
+ (*SDFM[sdfmNumber]).SDDFPARM2.bit.FEN = Filter_switch;
+ (*SDFM[sdfmNumber]).SDDFPARM2.bit.SST = filterType;
+
+ //
+ // Configure Sinc filter OSR value
+ //
+ if(OSR<=DATA_FILTER_MAX_OSR)
+ {
+ (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = OSR;
+ }
+ else
+ {
+ (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = DATA_FILTER_MAX_OSR;
+ }
+
+ //
+ // Configure Data filter data representation
+ // DR_switch - Data Representation (0/1 = 16/32b 2's complement)
+ //
+ (*SDFM[sdfmNumber]).SDDPARM2.bit.DR = DR_switch;
+ if(DR_switch == 0)
+ {
+ (*SDFM[sdfmNumber]).SDDPARM2.bit.SH = shift_bits;
+ }
+
+ break;
+
+ case FILTER3: //Filter 3
+ (*SDFM[sdfmNumber]).SDDFPARM3.bit.FEN = Filter_switch;
+ (*SDFM[sdfmNumber]).SDDFPARM3.bit.SST = filterType;
+
+ //
+ // Configure Sinc filter OSR value
+ //
+ if(OSR<=DATA_FILTER_MAX_OSR)
+ {
+ (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = OSR;
+ }
+ else
+ {
+ (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = DATA_FILTER_MAX_OSR;
+ }
+
+ //
+ // Configure Data filter data representation
+ // DR_switch - Data Representation (0/1 = 16/32b 2's complement)
+ //
+ (*SDFM[sdfmNumber]).SDDPARM3.bit.DR = DR_switch;
+ if(DR_switch == 0)
+ {
+ (*SDFM[sdfmNumber]).SDDPARM3.bit.SH = shift_bits;
+ }
+
+ break;
+
+ case FILTER4: //Filter 4
+ (*SDFM[sdfmNumber]).SDDFPARM4.bit.FEN = Filter_switch;
+ (*SDFM[sdfmNumber]).SDDFPARM4.bit.SST = filterType;
+
+ //
+ // Configure Sinc filter OSR value
+ //
+ if(OSR<=DATA_FILTER_MAX_OSR)
+ {
+ (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = OSR;
+ }
+ else
+ {
+ (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = DATA_FILTER_MAX_OSR;
+ }
+
+ //
+ // Configure Data filter data representation
+ // DR_switch - Data Representation (0/1 = 16/32b 2's complement)
+ //
+ (*SDFM[sdfmNumber]).SDDPARM4.bit.DR = DR_switch;
+ if(DR_switch == 0)
+ {
+ (*SDFM[sdfmNumber]).SDDPARM4.bit.SH = shift_bits;
+ }
+
+ break;
+ }
+
+ EDIS;
+}
+
+//
+// Sdfm_configureInterrupt - This function configures SDFM Interrupt unit.
+// SDFM Interrupt unit can be configured to
+// enable/disable different sources of SDFM
+// interrupts which should trigger CPU interrupt.
+//
+// sdfmNumber - This parameter should be used to
+// select SDFM1 (or) SDFM2
+// filterNumber - This parameter is used to select
+// which filter(FILTER1,FILTER2,
+// FILTER3,FILTER3) needs to be
+// configured
+// IEH_Switch - This parameter allows over value
+// condition to trigger CPU interrupt
+// IEL_Switch - This parameter allows under value
+// condition to trigger CPU interrupt
+// MFIE_Switch - This parameter allows modulator
+// failure to trigger CPU interrupt
+// AE_Switch - This parameter allows new filter
+// data acknowledge interrupt signal
+// to trigger CPU interrupt
+//
+void Sdfm_configureInterrupt(Uint16 sdfmNumber, Uint16 filterNumber,
+ Uint16 IEH_Switch, Uint16 IEL_Switch,
+ Uint16 MFIE_Switch, Uint16 AE_Switch)
+{
+ EALLOW;
+
+ switch(filterNumber)
+ {
+ case FILTER1: //Filter 1
+ (*SDFM[sdfmNumber]).SDCPARM1.bit.EN_CEVT1 = IEH_Switch;
+ (*SDFM[sdfmNumber]).SDCPARM1.bit.EN_CEVT2 = IEL_Switch;
+ (*SDFM[sdfmNumber]).SDCPARM1.bit.MFIE = MFIE_Switch;
+ (*SDFM[sdfmNumber]).SDDFPARM1.bit.AE = AE_Switch;
+ break;
+
+ case FILTER2: //Filter 2
+ (*SDFM[sdfmNumber]).SDCPARM2.bit.EN_CEVT1 = IEH_Switch;
+ (*SDFM[sdfmNumber]).SDCPARM2.bit.EN_CEVT2 = IEL_Switch;
+ (*SDFM[sdfmNumber]).SDCPARM2.bit.MFIE = MFIE_Switch;
+ (*SDFM[sdfmNumber]).SDDFPARM2.bit.AE = AE_Switch;
+ break;
+
+ case FILTER3: //Filter 3
+ (*SDFM[sdfmNumber]).SDCPARM3.bit.EN_CEVT1 = IEH_Switch;
+ (*SDFM[sdfmNumber]).SDCPARM3.bit.EN_CEVT2 = IEL_Switch;
+ (*SDFM[sdfmNumber]).SDCPARM3.bit.MFIE = MFIE_Switch;
+ (*SDFM[sdfmNumber]).SDDFPARM3.bit.AE = AE_Switch;
+ break;
+
+ case FILTER4: //Filter 4
+ (*SDFM[sdfmNumber]).SDCPARM4.bit.EN_CEVT1 = IEH_Switch;
+ (*SDFM[sdfmNumber]).SDCPARM4.bit.EN_CEVT2 = IEL_Switch;
+ (*SDFM[sdfmNumber]).SDCPARM4.bit.MFIE = MFIE_Switch;
+ (*SDFM[sdfmNumber]).SDDFPARM4.bit.AE = AE_Switch;
+ break;
+ }
+
+ EDIS;
+}
+
+
+//
+// SDFM_configExternalreset - This function configures SDFM module to
+// enable/disable external filter reset from PWM
+//
+// sdfmNumber - This parameter should
+// be used to select
+// SDFM1 (or) SDFM2
+// filter1_Config_ext_reset - This parameter is used
+// to enable/disable
+// external PWM reset for
+// filter1
+// filter2_Config_ext_reset - This parameter is used
+// to enable/disable
+// external PWM reset for
+// filter2
+// filter3_Config_ext_reset - This parameter is used
+// to enable / disable
+// external PWM reset for
+// filter3
+// filter4_Config_ext_reset - This parameter is used
+// to enable / disable
+// external PWM reset for
+// filter4
+//
+void Sdfm_configureExternalreset(Uint16 sdfmNumber,
+ Uint16 filter1_Config_ext_reset,
+ Uint16 filter2_Config_ext_reset,
+ Uint16 filter3_Config_ext_reset,
+ Uint16 filter4_Config_ext_reset)
+{
+ EALLOW;
+ (*SDFM[sdfmNumber]).SDDFPARM1.bit.SDSYNCEN = filter1_Config_ext_reset;
+ (*SDFM[sdfmNumber]).SDDFPARM2.bit.SDSYNCEN = filter2_Config_ext_reset;
+ (*SDFM[sdfmNumber]).SDDFPARM3.bit.SDSYNCEN = filter3_Config_ext_reset;
+ (*SDFM[sdfmNumber]).SDDFPARM4.bit.SDSYNCEN = filter4_Config_ext_reset;
+ EDIS;
+}
+
+//
+// SDFM_enableMFE - This function enables Master filter bit of SDFM module
+//
+// sdfmNumber - This parameter should be used to select
+// SDFM1 (or) SDFM2
+//
+void Sdfm_enableMFE(Uint16 sdfmNumber)
+{
+ EALLOW;
+ (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 1; //Master Filter bit is enabled
+ EDIS;
+}
+
+//
+// SDFM_disableMFE - This function disable Master filter bit of SDFM module
+//
+// sdfmNumber - This parameter should be used to select
+// SDFM1 (or) SDFM2
+//
+void SDFM_disableMFE(Uint16 sdfmNumber)
+{
+ EALLOW;
+ (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 0; //Master Filter bit is disabled
+ EDIS;
+}
+
+//
+// SDFM_enableMIE - This function enable Master Interrupt bit of SDFM module
+//
+// sdfmNumber - This parameter should be used to select
+// SDFM1 (or) SDFM2
+//
+void Sdfm_enableMIE(Uint16 sdfmNumber)
+{
+ EALLOW;
+ //
+ //Enable MIE (Master Interrupt Enable) bit
+ //
+ (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 1;
+ EDIS;
+}
+
+//
+// Sdfm_disableMIE - This function disable Master Interrupt bit of SDFM module
+//
+// sdfmNumber - This parameter should be used to select
+// SDFM1 (or) SDFM2
+//
+void Sdfm_disableMIE(Uint16 sdfmNumber)
+{
+
+ EALLOW;
+ //
+ //Disable MIE (Master Interrupt Enable) bit
+ //
+ (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 0;
+ EDIS;
+}
+
+//
+// Sdfm_readFlagRegister - This function helps user read SDFM flag
+// register (SDIFLG)
+//
+Uint32 Sdfm_readFlagRegister(Uint16 sdfmNumber)
+{
+ return ((*SDFM[sdfmNumber]).SDIFLG.all);
+}
+
+//
+// Sdfm_clearFlagRegister - This function helps is used to clear
+// SDIFLG register
+//
+void Sdfm_clearFlagRegister(Uint16 sdfmNumber,Uint32 sdfmReadFlagRegister)
+{
+ (*SDFM[sdfmNumber]).SDIFLGCLR.all = sdfmReadFlagRegister;
+}
+
+//
+// End of file
+//
diff --git a/Projects/epwm_test/lib/f2838x_struct.c b/Projects/epwm_test/lib/f2838x_struct.c
new file mode 100644
index 0000000..37934ce
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_struct.c
@@ -0,0 +1,105 @@
+//###########################################################################
+//
+// FILE: f2838x_struct.c
+//
+// TITLE: F2838x SDFM structure
+//
+//###########################################################################
+//
+//
+// $Copyright:
+// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "f2838x_device.h"
+#include "f2838x_struct.h"
+
+//
+// Globals
+//
+#if defined(CPU1)
+volatile struct ADC_REGS *ADC[MAX_ADC] =
+{ 0, &AdcaRegs, &AdcbRegs,
+ &AdccRegs, &AdcdRegs };
+#endif
+
+volatile struct ECAP_REGS *ECAP[MAX_ECAP] =
+{ 0, &ECap1Regs, &ECap2Regs, &ECap3Regs,
+ &ECap4Regs, &ECap5Regs, &ECap6Regs,
+ &ECap7Regs };
+
+volatile struct EPWM_REGS *EPWM[MAX_EPWM] =
+{ 0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs,
+ &EPwm4Regs, &EPwm5Regs, &EPwm6Regs,
+ &EPwm7Regs, &EPwm8Regs, &EPwm9Regs,
+ &EPwm10Regs, &EPwm11Regs, &EPwm12Regs,
+ &EPwm13Regs, &EPwm14Regs, &EPwm15Regs,
+ &EPwm16Regs };
+
+volatile struct EQEP_REGS *EQEP[MAX_EQEP] =
+{ 0, &EQep1Regs, &EQep2Regs, &EQep3Regs };
+
+volatile struct I2C_REGS *I2C[MAX_I2C] =
+{ 0, &I2caRegs ,&I2cbRegs };
+
+volatile struct McBSP_REGS *MCBSP[MAX_MCBSP] =
+{ 0, &McbspaRegs ,&McbspbRegs };
+
+volatile struct SCI_REGS *SCI[MAX_SCI] =
+{ 0, &SciaRegs ,&ScibRegs ,&ScicRegs ,
+ &ScidRegs };
+
+volatile struct SPI_REGS *SPI[MAX_SPI] =
+{ 0, &SpibRegs, &SpibRegs, &SpicRegs,
+ &SpicRegs };
+
+volatile struct SDFM_REGS *SDFM[MAX_SDFM] =
+{ 0, &Sdfm1Regs, &Sdfm2Regs};
+
+#if defined(CPU1)
+volatile Uint16 *TRIP_SEL[MAX_TRIPSEL] =
+{ 0, &InputXbarRegs.INPUT1SELECT, &InputXbarRegs.INPUT2SELECT,
+ &InputXbarRegs.INPUT3SELECT, &InputXbarRegs.INPUT4SELECT,
+ &InputXbarRegs.INPUT5SELECT, &InputXbarRegs.INPUT6SELECT,
+ &InputXbarRegs.INPUT7SELECT, &InputXbarRegs.INPUT8SELECT,
+ &InputXbarRegs.INPUT9SELECT, &InputXbarRegs.INPUT10SELECT,
+ &InputXbarRegs.INPUT11SELECT, &InputXbarRegs.INPUT12SELECT,
+ &InputXbarRegs.INPUT13SELECT, &InputXbarRegs.INPUT14SELECT
+};
+#endif
+
+//
+// End of file
+//
diff --git a/Projects/epwm_test/lib/f2838x_sysctrl.c b/Projects/epwm_test/lib/f2838x_sysctrl.c
new file mode 100644
index 0000000..e6da39b
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_sysctrl.c
@@ -0,0 +1,1463 @@
+//###########################################################################
+//
+// FILE: f2838x_sysctrl.c
+//
+// TITLE: F2838x Device System Control Initialization & Support Functions.
+//
+// DESCRIPTION:
+//
+// Example initialization of system resources.
+//
+//###########################################################################
+//
+//
+// $Copyright:
+// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "f2838x_device.h"
+#include "f2838x_examples.h"
+#include "math.h"
+
+//
+// Functions that will be run from RAM need to be assigned to a different
+// section. This section will then be mapped to a load and run address using
+// the linker cmd file.
+//
+// *IMPORTANT*
+//
+// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM
+// FLASH TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM
+// THROWING AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE.
+//
+#pragma CODE_SECTION(InitFlash, ".TI.ramfunc");
+#pragma CODE_SECTION(FlashOff, ".TI.ramfunc");
+
+
+// The following values are used to validate PLL Frequency using DCC
+//
+#define DCC_COUNTER0_TOLERANCE 1
+
+#ifdef USE_20MHZ_XTAL
+
+#define OSC_FREQ 20
+
+//
+// Multipliers and dividers to configure 200MHz SYSPLL output from 20MHz XTAL
+//
+#define SYS_IMULT IMULT_40
+#define SYS_REFDIV REFDIV_2
+#define SYS_ODIV ODIV_2
+#define SYS_DIV PLLCLK_BY_1
+
+//
+// Multipliers and dividers to configure 125MHz AUXPLL output from 20MHz XTAL
+//
+#define AUX_IMULT IMULT_50
+#define AUX_REFDIV REFDIV_2
+#define AUX_ODIV ODIV_4
+#define AUX_DIV AUXPLLRAWCLK_BY_1
+
+
+#else // USE_25MHZ_XTAL
+
+#define OSC_FREQ 25
+
+//
+// Multipliers and dividers to configure 200MHz SYSPLL output from 25MHz XTAL
+//
+#define SYS_IMULT IMULT_32
+#define SYS_REFDIV REFDIV_2
+#define SYS_ODIV ODIV_2
+#define SYS_DIV PLLCLK_BY_1
+
+//
+// Multipliers and dividers to configure 125MHz AUXPLL output from 25MHz XTAL
+//
+#define AUX_IMULT IMULT_40
+#define AUX_REFDIV REFDIV_2
+#define AUX_ODIV ODIV_4
+#define AUX_DIV AUXPLLRAWCLK_BY_1
+
+#endif
+
+//
+// InitSysCtrl - Initialization of system resources.
+//
+void InitSysCtrl(void)
+{
+ //
+ // Disable the watchdog
+ //
+ DisableDog();
+
+#ifdef _FLASH
+ //
+ // Copy time critical code and Flash setup code to RAM. This includes the
+ // following functions: InitFlash()
+ //
+ // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart
+ // symbols are created by the linker. Refer to the device .cmd file.
+ //
+ memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
+
+ //
+ // Call Flash Initialization to setup flash waitstates. This function must
+ // reside in RAM.
+ //
+ InitFlash();
+#endif
+
+ //
+ // *IMPORTANT*
+ //
+ // The Device_cal function, which copies the ADC & oscillator calibration
+ // values from TI reserved OTP into the appropriate trim registers, occurs
+ // automatically in the Boot ROM. If the boot ROM code is bypassed during
+ // the debug process, the following function MUST be called for the ADC and
+ // oscillators to function according to specification. The clocks to the
+ // ADC MUST be enabled before calling this function.
+ //
+ // See the device data manual and/or the ADC Reference Manual for more
+ // information.
+ //
+#ifdef CPU1
+ //
+ // Enable pull-ups on unbonded IOs as soon as possible to reduce power
+ // consumption.
+ //
+ GPIO_EnableUnbondedIOPullups();
+
+ EALLOW;
+
+
+ CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
+ CpuSysRegs.PCLKCR13.bit.ADC_B = 1;
+ CpuSysRegs.PCLKCR13.bit.ADC_C = 1;
+ CpuSysRegs.PCLKCR13.bit.ADC_D = 1;
+
+ //
+ // Check if device is trimmed
+ //
+ if(*((Uint16 *)0x5D736) == 0x0000){
+ //
+ // Device is not trimmed--apply static calibration values
+ //
+ AnalogSubsysRegs.ANAREFTRIMA.all = 31709;
+ AnalogSubsysRegs.ANAREFTRIMB.all = 31709;
+ AnalogSubsysRegs.ANAREFTRIMC.all = 31709;
+ AnalogSubsysRegs.ANAREFTRIMD.all = 31709;
+ }
+
+ CpuSysRegs.PCLKCR13.bit.ADC_A = 0;
+ CpuSysRegs.PCLKCR13.bit.ADC_B = 0;
+ CpuSysRegs.PCLKCR13.bit.ADC_C = 0;
+ CpuSysRegs.PCLKCR13.bit.ADC_D = 0;
+ EDIS;
+
+ //
+ // Verify the crystal frequency.
+ // Note: This check can be removed if you are not using XTAL as the PLL
+ // source
+ //
+ if(!VerifyXTAL(OSC_FREQ))
+ {
+ //
+ // The actual XTAL frequency does not match OSC_FREQ!!
+ // Please check the XTAL frequency used.
+ //
+ // By default, the InitSysCtrl function assumes 25MHz XTAL.
+ // If a 20MHz crystal is used, please add a predefined symbol
+ // "USE_20MHZ_XTAL" in your CCS project.
+ // If a different XTAL is used, please update the PLL configuration
+ // below accordingly.
+ //
+ // Note that the latest F2838x controlCARDs (Rev.B and later) have been
+ // updated to use 25MHz XTAL by default. If you have an older 20MHz XTAL
+ // controlCARD (E1, E2, or Rev.A), refer to the controlCARD
+ // documentation on steps to reconfigure the controlCARD from 20MHz to
+ // 25MHz.
+ //
+ ESTOP0;
+ while(1);
+ }
+
+ //
+ // Initialize the SYSPLL control to generate a 200Mhz clock
+ //
+ // Defined options to be passed as arguments to this function are defined
+ // in f2838x_examples.h.
+ //
+ // Note: The internal oscillator CANNOT be used as the PLL source if the
+ // PLLSYSCLK is configured to frequencies above 194 MHz.
+ //
+ // PLLSYSCLK = (XTAL_OSC) * (IMULT) /(REFDIV) * (ODIV) * (PLLSYSCLKDIV)
+ //
+ InitSysPll(XTAL_OSC, SYS_IMULT, SYS_REFDIV, SYS_ODIV, SYS_DIV, SYSCTL_DCC_BASE0);
+
+ //
+ // Initialize the AUXPLL control to generate a 125Mhz clock:
+ //
+ // Defined options to be passed as arguments to this function are defined
+ // in f2838x_Examples.h.
+ //
+ // Note: The internal oscillator CANNOT be used as the PLL source if the
+ // AUXPLLCLK is configured to frequencies above 194 MHz.
+ //
+ // AUXPLLCLK = (XTAL_OSC) * (IMULT) /(REFDIV) * (ODIV) * (AUXPLLDIV)
+ //
+ InitAuxPll(XTAL_OSC, AUX_IMULT, AUX_REFDIV, AUX_ODIV, AUX_DIV, SYSCTL_DCC_BASE1);
+
+ //
+ // Set up CMCLK to use AUXPLL as the clock source and set the
+ // clock divider to 1.
+ //
+ EALLOW;
+ ClkCfgRegs.CMCLKCTL.bit.CMCLKDIV = 0; // 0 : Divide by 1
+ ClkCfgRegs.CMCLKCTL.bit.CMDIVSRCSEL = 0; // 0 : AuxPLL is the source for the CM clock divider.
+ EDIS;
+
+#ifndef _FLASH
+ //
+ // Call Device_cal function when run using debugger
+ // This function is called as part of the Boot code. The function is called
+ // in the InitSysCtrl function since during debug time resets, the boot code
+ // will not be executed and the gel script will reinitialize all the
+ // registers and the calibrated values will be lost.
+ //
+ Device_cal();
+#endif
+
+#endif // CPU1
+
+ //
+ // Turn on all peripherals
+ //
+ InitPeripheralClocks();
+}
+
+//
+//
+// Function to verify the XTAL frequency
+// freq is the XTAL frequency in MHz
+// The function return true if the the actual XTAL frequency matches with the
+// input value
+//
+//
+#ifdef CPU1
+bool VerifyXTAL(float freq)
+{
+ //
+ // Configures XTAL as CLKSRC0 and INTOSC2 as CLKSRC1.
+ // Fclk0 = XTAL frequency (input parameter)
+ // Fclk1 = INTOSC2 frequency = 10MHz
+ //
+ // Calculating Counter0 & Valid Seed Value with +/-1% tolerance
+ // INTOSC can have a variance in frequency of +/-10%
+ //
+ // Since Fclk1 < Fclk0, then Async. Error (In Clock0 cycles) =
+ // 2*(Fclk0/Fclk1) + 2*(Fsysclk/Fclk0)
+ // Digitization error = 8 Clock0 cycles
+ // DCC Error (in Cycles) = 2*(Fclk0/Fclk1) + 2*(Fsysclk/Fclk0) + 8
+ // Window (in Cycles) = (Total Error) / (0.01 * Tolerance)
+ // Error due to variance in frequency = Window * freqVariance
+ // Total error = DCC Error + Error due to variance in frequency
+ // Counter0 = Window - Total Error
+ // Valid0 = 2 * Total Error
+ // Counter1 = Window * (Fclk1/Fclk0)
+ //
+ // Note : Update the tolerance and INTOSC2 frequency variance as necessary.
+ //
+ uint32_t total_error = ceil((2.0F * freq/10.0F) + (2.0F * 10.0F/freq) + 8.0F);
+ uint32_t window = total_error / 0.01F;
+ total_error += window * 0.1F;
+
+ uint32_t count0 = window - total_error;
+ uint32_t valid = 2 * total_error;
+ uint32_t count1 = window * 10 / freq;
+
+ EALLOW;
+
+ //
+ // Enable DCC0 clock
+ //
+ CpuSysRegs.PCLKCR21.bit.DCC0 = 1;
+
+ //
+ // Insert atleast 5 cycles delay after enabling the peripheral clock
+ //
+ asm(" RPT #5 || NOP");
+
+ //
+ // Clear Error & Done Flag
+ //
+ Dcc0Regs.DCCSTATUS.bit.ERR = 1;
+ Dcc0Regs.DCCSTATUS.bit.DONE = 1;
+
+ //
+ // Disable DCC
+ //
+ Dcc0Regs.DCCGCTRL.bit.DCCENA = 0x5;
+
+ //
+ // Disable Error Signal
+ //
+ Dcc0Regs.DCCGCTRL.bit.ERRENA = 0x5;
+
+ //
+ // Disable Done Signal
+ //
+ Dcc0Regs.DCCGCTRL.bit.DONEENA = 0x5;
+
+ //
+ // Configure Clock Source0 to XTAL
+ //
+ Dcc0Regs.DCCCLKSRC0.all = (0xA << 12) | // bits 12..15 : Key
+ 0; // bits 0..4 : Source = XTAL(value 0)
+
+ //
+ // Configure Clock Source1 to INTOSC
+ //
+ Dcc0Regs.DCCCLKSRC1.all = (0xA << 12) | // bits 12..15 : Key
+ 3; // bits 0..4 : Source = INTOS2(value 3)
+
+ //
+ // Configure COUNTER-0, COUNTER-1 & Valid Window
+ //
+ Dcc0Regs.DCCCNTSEED0.all = count0;
+ Dcc0Regs.DCCCNTSEED1.all = count1;
+ Dcc0Regs.DCCVALIDSEED0.all = valid;
+
+ //
+ // Enable Single Shot mode
+ //
+ Dcc0Regs.DCCGCTRL.bit.SINGLESHOT = 0xA;
+
+ //
+ // Enable Error Signal
+ //
+ Dcc0Regs.DCCGCTRL.bit.ERRENA = 0xA;
+
+ //
+ // Enable Done Signal
+ //
+ Dcc0Regs.DCCGCTRL.bit.DONEENA = 0xA;
+
+ //
+ // Enable DCC to start counting
+ //
+ Dcc0Regs.DCCGCTRL.bit.DCCENA = 0xA;
+
+ EDIS;
+
+ //
+ // Wait until Error or Done Flag is generated
+ //
+ while((Dcc0Regs.DCCSTATUS.bit.DONE | Dcc0Regs.DCCSTATUS.bit.ERR) == 0);
+
+ //
+ // Returns true if DCC completes without error
+ //
+ if (Dcc0Regs.DCCSTATUS.bit.DONE == 1U)
+ {
+ return true;
+ }
+ else
+ {
+ return false;
+ }
+
+}
+#endif
+
+//
+// InitPeripheralClocks - Initializes the clocks for the peripherals.
+//
+// Note: In order to reduce power consumption, turn off the clocks to any
+// peripheral that is not specified for your part-number or is not used in the
+// application
+//
+void InitPeripheralClocks(void)
+{
+ EALLOW;
+
+ CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
+ CpuSysRegs.PCLKCR0.bit.DMA = 1;
+ CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
+ CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1;
+ CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1;
+ CpuSysRegs.PCLKCR0.bit.CPUBGCRC = 1;
+ CpuSysRegs.PCLKCR0.bit.CLA1BGCRC = 1;
+
+#ifdef CPU1
+ CpuSysRegs.PCLKCR0.bit.HRCAL = 1;
+#endif
+
+ CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
+ CpuSysRegs.PCLKCR0.bit.ERAD = 1;
+
+#ifdef CPU1
+ CpuSysRegs.PCLKCR1.bit.EMIF1 = 1;
+ CpuSysRegs.PCLKCR1.bit.EMIF2 = 1;
+#endif
+
+ CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM5 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM6 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM7 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM8 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM9 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM10 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM11 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM12 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM13 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM14 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM15 = 1;
+ CpuSysRegs.PCLKCR2.bit.EPWM16 = 1;
+
+ CpuSysRegs.PCLKCR3.bit.ECAP1 = 1;
+ CpuSysRegs.PCLKCR3.bit.ECAP2 = 1;
+ CpuSysRegs.PCLKCR3.bit.ECAP3 = 1;
+ CpuSysRegs.PCLKCR3.bit.ECAP4 = 1;
+ CpuSysRegs.PCLKCR3.bit.ECAP5 = 1;
+ CpuSysRegs.PCLKCR3.bit.ECAP6 = 1;
+ CpuSysRegs.PCLKCR3.bit.ECAP7 = 1;
+
+ CpuSysRegs.PCLKCR4.bit.EQEP1 = 1;
+ CpuSysRegs.PCLKCR4.bit.EQEP2 = 1;
+ CpuSysRegs.PCLKCR4.bit.EQEP3 = 1;
+
+ CpuSysRegs.PCLKCR6.bit.SD1 = 1;
+ CpuSysRegs.PCLKCR6.bit.SD2 = 1;
+
+ CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
+ CpuSysRegs.PCLKCR7.bit.SCI_B = 1;
+ CpuSysRegs.PCLKCR7.bit.SCI_C = 1;
+ CpuSysRegs.PCLKCR7.bit.SCI_D = 1;
+
+ CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
+ CpuSysRegs.PCLKCR8.bit.SPI_B = 1;
+ CpuSysRegs.PCLKCR8.bit.SPI_C = 1;
+ CpuSysRegs.PCLKCR8.bit.SPI_D = 1;
+
+ CpuSysRegs.PCLKCR9.bit.I2C_A = 1;
+ CpuSysRegs.PCLKCR9.bit.I2C_B = 1;
+
+ CpuSysRegs.PCLKCR10.bit.CAN_A = 1;
+ CpuSysRegs.PCLKCR10.bit.CAN_B = 1;
+
+ CpuSysRegs.PCLKCR11.bit.McBSP_A = 1;
+ CpuSysRegs.PCLKCR11.bit.McBSP_B = 1;
+
+#ifdef CPU1
+ CpuSysRegs.PCLKCR11.bit.USB_A = 1;
+#endif
+
+ CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
+ CpuSysRegs.PCLKCR13.bit.ADC_B = 1;
+ CpuSysRegs.PCLKCR13.bit.ADC_C = 1;
+ CpuSysRegs.PCLKCR13.bit.ADC_D = 1;
+
+ CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1;
+ CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1;
+ CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1;
+ CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1;
+ CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1;
+ CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1;
+ CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1;
+ CpuSysRegs.PCLKCR14.bit.CMPSS8 = 1;
+
+ CpuSysRegs.PCLKCR16.bit.DAC_A = 1;
+ CpuSysRegs.PCLKCR16.bit.DAC_B = 1;
+ CpuSysRegs.PCLKCR16.bit.DAC_C = 1;
+
+ CpuSysRegs.PCLKCR18.bit.FSITX_A = 1;
+ CpuSysRegs.PCLKCR18.bit.FSITX_B = 1;
+ CpuSysRegs.PCLKCR18.bit.FSIRX_A = 1;
+ CpuSysRegs.PCLKCR18.bit.FSIRX_B = 1;
+ CpuSysRegs.PCLKCR18.bit.FSIRX_C = 1;
+ CpuSysRegs.PCLKCR18.bit.FSIRX_D = 1;
+ CpuSysRegs.PCLKCR18.bit.FSIRX_E = 1;
+ CpuSysRegs.PCLKCR18.bit.FSIRX_F = 1;
+ CpuSysRegs.PCLKCR18.bit.FSIRX_G = 1;
+ CpuSysRegs.PCLKCR18.bit.FSIRX_H = 1;
+
+ CpuSysRegs.PCLKCR20.bit.PMBUS_A = 1;
+
+ CpuSysRegs.PCLKCR21.bit.DCC0 = 1;
+ CpuSysRegs.PCLKCR21.bit.DCC1 = 1;
+ CpuSysRegs.PCLKCR21.bit.DCC2 = 1;
+
+ CpuSysRegs.PCLKCR23.bit.ETHERCAT = 1;
+
+ EDIS;
+}
+
+//
+// DisablePeripheralClocks - Gates-off all peripheral clocks.
+//
+void DisablePeripheralClocks(void)
+{
+ EALLOW;
+
+ CpuSysRegs.PCLKCR0.all = 0;
+ CpuSysRegs.PCLKCR1.all = 0;
+ CpuSysRegs.PCLKCR2.all = 0;
+ CpuSysRegs.PCLKCR3.all = 0;
+ CpuSysRegs.PCLKCR4.all = 0;
+ CpuSysRegs.PCLKCR6.all = 0;
+ CpuSysRegs.PCLKCR7.all = 0;
+ CpuSysRegs.PCLKCR8.all = 0;
+ CpuSysRegs.PCLKCR9.all = 0;
+ CpuSysRegs.PCLKCR10.all = 0;
+ CpuSysRegs.PCLKCR11.all = 0;
+ CpuSysRegs.PCLKCR13.all = 0;
+ CpuSysRegs.PCLKCR14.all = 0;
+ CpuSysRegs.PCLKCR16.all = 0;
+ CpuSysRegs.PCLKCR18.all = 0;
+ CpuSysRegs.PCLKCR20.all = 0;
+ CpuSysRegs.PCLKCR21.all = 0;
+ CpuSysRegs.PCLKCR22.all = 0;
+ CpuSysRegs.PCLKCR23.all = 0;
+
+ EDIS;
+}
+
+//
+// InitFlash - This function initializes the Flash Control registers.
+//
+// *CAUTION*
+// This function MUST be executed out of RAM. Executing it out of OTP/Flash
+// will yield unpredictable results.
+//
+#ifdef __cplusplus
+#pragma CODE_SECTION(".TI.ramfunc");
+#endif
+void InitFlash(void)
+{
+ EALLOW;
+
+ //
+ // At reset bank and pump are in sleep. A Flash access will power up the
+ // bank and pump automatically.
+ //
+ // Power up Flash bank and pump. This also sets the fall back mode of
+ // flash and pump as active.
+ //
+ Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1;
+ Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3;
+
+ //
+ // Disable Cache and prefetch mechanism before changing wait states
+ //
+ Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0;
+ Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0;
+
+ //
+ // Set waitstates according to frequency
+ //
+ // *CAUTION*
+ // Minimum waitstates required for the flash operating at a given CPU rate
+ // must be characterized by TI. Refer to the datasheet for the latest
+ // information.
+ //
+ #if CPU_FRQ_200MHZ
+ Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3;
+ #endif
+
+ #if CPU_FRQ_150MHZ
+ Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
+ #endif
+
+ #if CPU_FRQ_120MHZ
+ Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
+ #endif
+
+ //
+ // Enable Cache and prefetch mechanism to improve performance of code
+ // executed from Flash.
+ //
+ Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1;
+ Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1;
+
+ //
+ // At reset, ECC is enabled. If it is disabled by application software and
+ // if application again wants to enable ECC.
+ //
+ Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
+
+ EDIS;
+
+ //
+ // Force a pipeline flush to ensure that the write to the last register
+ // configured occurs before returning.
+ //
+ __asm(" RPT #7 || NOP");
+}
+
+//
+// FlashOff - This function powers down the flash
+//
+// *CAUTION*
+// This function MUST be executed out of RAM. Executing it out of OTP/Flash
+// will yield unpredictable results. Also you must seize the flash pump in
+// order to power it down.
+//
+#ifdef __cplusplus
+#pragma CODE_SECTION(".TI.ramfunc");
+#endif
+void FlashOff(void)
+{
+ EALLOW;
+
+ //
+ // Power down bank
+ //
+ Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0;
+
+ //
+ // Power down pump
+ //
+ Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0;
+
+ EDIS;
+}
+
+
+//
+// ServiceDog - This function resets the watchdog timer.
+//
+// Enable this function for using ServiceDog in the application.
+//
+void ServiceDog(void)
+{
+ EALLOW;
+ WdRegs.WDKEY.bit.WDKEY = 0x0055;
+ WdRegs.WDKEY.bit.WDKEY = 0x00AA;
+ EDIS;
+}
+
+//
+// DisableDog - This function disables the watchdog timer.
+//
+void DisableDog(void)
+{
+ volatile Uint16 temp;
+
+ //
+ // Grab the clock config first so we don't clobber it
+ //
+ EALLOW;
+ temp = WdRegs.WDCR.all & 0x0007;
+ WdRegs.WDCR.all = 0x0068 | temp;
+ EDIS;
+}
+
+#ifdef CPU1
+//
+// InitPll - This function initializes the PLL registers.
+//
+// Note: This function uses the DCC to check that the PLLRAWCLK is running at
+// the expected rate. The desirable DCC can be provided as a parameter.
+//
+void InitSysPll(Uint16 clock_source, Uint16 imult, Uint32 refdiv, Uint32 odiv,
+ Uint16 divsel, Uint32 dccbase)
+{
+ Uint32 timeout,temp_syspllmult, pllLockStatus;
+ bool status;
+
+ if(((clock_source & 0x3) == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) &&
+ (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE) &&
+ (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) &&
+ (refdiv == ClkCfgRegs.SYSPLLMULT.bit.REFDIV) &&
+ (odiv == ClkCfgRegs.SYSPLLMULT.bit.ODIV) &&
+ (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV))
+ {
+ //
+ // Everything is set as required, so just return
+ //
+ return;
+ }
+
+ EALLOW;
+
+ //
+ // First modify the PLL multipliers if the multipliers need an update or PLL needs
+ // to be powered on / enabled
+ //
+ if((imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT) ||
+ (refdiv != ClkCfgRegs.SYSPLLMULT.bit.REFDIV)||
+ (odiv != ClkCfgRegs.SYSPLLMULT.bit.ODIV) ||
+ (1U != ClkCfgRegs.SYSPLLCTL1.bit.PLLEN))
+ {
+ //
+ // Bypass PLL and set dividers to /1
+ //
+ ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0;
+
+ //
+ // Delay of at least 120 OSCCLK cycles required post PLL bypass
+ //
+ asm(" RPT #120 || NOP");
+
+ //
+ // Evaluate PLL multipliers and dividers
+ //
+ temp_syspllmult = ((refdiv << 24U) | (odiv << 16U)| imult);
+
+ //
+ // Turnoff the PLL
+ //
+ ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0;
+ EDIS;
+
+ //
+ // Delay of at least 66 OSCCLK cycles
+ //
+ asm(" RPT #66 || NOP");
+
+ if(((clock_source & 0x3) != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) ||
+ (((clock_source & 0x4) >> 2) != ClkCfgRegs.XTALCR.bit.SE))
+ {
+ switch (clock_source)
+ {
+ case INT_OSC1:
+ SysIntOsc1Sel();
+ break;
+
+ case INT_OSC2:
+ SysIntOsc2Sel();
+ break;
+
+ case XTAL_OSC:
+ SysXtalOscSel();
+ break;
+
+ case XTAL_OSC_SE:
+ SysXtalOscSESel();
+ break;
+ }
+ }
+
+ //
+ // Delay of at least 60 OSCCLK cycles
+ //
+ asm(" RPT #60 || NOP");
+
+ EALLOW;
+
+ //
+ // Set dividers to /1 to ensure the fastest PLL configuration
+ //
+ ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0;
+
+ //
+ // Program PLL multipliers
+ //
+ ClkCfgRegs.SYSPLLMULT.all = temp_syspllmult;
+
+ //
+ // Enable SYSPLL
+ //
+ ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1;
+
+ //
+ // Lock time is 1024 OSCCLK * (REFDIV+1)
+ //
+ timeout = (1024U * (refdiv + 1U));
+ pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS;
+
+ //
+ // Wait for the SYSPLL lock
+ //
+ while((pllLockStatus != 1) && (timeout != 0U))
+ {
+ pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS;
+ timeout--;
+ }
+
+ EDIS;
+
+ //
+ // Check PLL Frequency using DCC
+ //
+ status = IsPLLValid(dccbase, clock_source, INT_PLL_SYSPLL,
+ imult, odiv , refdiv);
+
+ }
+ else
+ {
+ //
+ // Re-Lock of PLL not needed since the multipliers
+ // are not updated
+ //
+ status = true;
+ }
+
+ if(status)
+ {
+ EALLOW;
+ //
+ // Set divider to produce slower output frequency to limit current increase
+ //
+ if(divsel != PLLCLK_BY_126)
+ {
+ ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1;
+ }
+ else
+ {
+ ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;
+ }
+
+ //
+ // Enable PLLSYSCLK is fed from system PLL clock
+ //
+ ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;
+
+ //
+ // Small 100 cycle delay
+ //
+ asm(" RPT #100 || NOP");
+
+ //
+ // Set the divider to user value
+ //
+ ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;
+ EDIS;
+ }
+ else
+ ESTOP0; // If the frequency is out of range, stop here.
+
+}
+
+//
+// InitAuxPll - This function initializes the AUXPLL registers.
+//
+// Note: This function uses the DCC to check that the AUXPLLRAWCLK is running at
+// the expected rate. The desirable DCC can be provided as a parameter.
+//
+void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint32 refdiv, Uint32 odiv,
+ Uint16 divsel, Uint32 dccbase)
+{
+ Uint16 started = 0 , status = 0;
+
+ if((clock_source == ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL) &&
+ (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE) &&
+ (imult == ClkCfgRegs.AUXPLLMULT.bit.IMULT) &&
+ (refdiv == ClkCfgRegs.SYSPLLMULT.bit.REFDIV) &&
+ (odiv == ClkCfgRegs.SYSPLLMULT.bit.ODIV) &&
+ (divsel == ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV))
+ {
+ //
+ // Everything is set as required, so just return
+ //
+ return;
+ }
+
+ //
+ // First modify the PLL multipliers
+ //
+ if((imult != ClkCfgRegs.AUXPLLMULT.bit.IMULT) ||
+ (refdiv != ClkCfgRegs.AUXPLLMULT.bit.REFDIV)||
+ (odiv != ClkCfgRegs.AUXPLLMULT.bit.ODIV) ||
+ (1U != ClkCfgRegs.AUXPLLCTL1.bit.PLLEN))
+ {
+ EALLOW;
+
+ //
+ // Bypass PLL
+ //
+ ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0;
+
+ //
+ // Delay of at least 120 OSCCLK cycles required post PLL bypass
+ //
+ asm(" RPT #120 || NOP");
+
+ ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; // Turn off AUXPLL
+
+ //
+ // Delay of at least 66 OSCCLK cycles
+ //
+ asm(" RPT #66 || NOP");
+
+ //
+ // Configure oscillator source
+ //
+ switch (clock_source)
+ {
+ case INT_OSC2:
+ AuxIntOsc2Sel();
+ break;
+
+ case XTAL_OSC:
+ AuxXtalOscSel();
+ break;
+
+ case XTAL_OSC_SE:
+ AuxXtalOscSESel();
+ break;
+
+ case AUXCLKIN:
+ AuxAuxClkSel();
+ break;
+ }
+
+ //
+ // Delay of at least 60 OSCCLK cycles
+ //
+ asm(" RPT #60 || NOP");
+
+ EALLOW;
+ //
+ // Set integer multiplier and dividers, which automatically turns on
+ // the PLL
+ //
+ ClkCfgRegs.AUXPLLMULT.all = ((refdiv << 24U) | (odiv << 16U) | imult);
+
+ //
+ // Enable AUXPLL
+ //
+ ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1;
+ EDIS;
+
+ //
+ // Wait for the AUXPLL lock counter
+ //
+ while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1)
+ {
+ //
+ // Uncomment to service the watchdog
+ //
+ // ServiceDog();
+ }
+
+ status = IsPLLValid(dccbase, clock_source, INT_PLL_AUXPLL,
+ imult, odiv , refdiv);
+
+ //
+ // Check DCC Status
+ //
+ if(status)
+ {
+ started = 1;
+ }
+
+ //
+ // Enable AUXPLLCLK to be fed from AUX PLL
+ //
+ EALLOW;
+ ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1;
+ asm(" RPT #20 || NOP");
+
+ EDIS;
+
+ if(started == 0)
+ {
+ //
+ // AUX PLL may not have started. Reset multiplier to 0 (bypass PLL).
+ //
+ EALLOW;
+ ClkCfgRegs.AUXPLLMULT.all = 0;
+ EDIS;
+
+ //
+ // The user should put some handler code here based on how this
+ // condition should be handled in their application.
+ //
+ asm(" ESTOP0");
+ }
+ }
+
+ //
+ // Set divider to desired value
+ //
+ EALLOW;
+ ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = divsel;
+
+ EDIS;
+}
+#endif
+
+//
+// CsmUnlock - This function unlocks the CSM. User must replace the default
+// value with the current password for the DSP.
+//
+Uint16 CsmUnlock(void)
+{
+ volatile Uint16 temp;
+
+ //
+ // Load the key registers with the current password. These values are
+ // default passwords for the first ZSB. User should replace them with
+ // the correct password for the DSP.
+ //
+ EALLOW;
+ DcsmZ1Regs.Z1_CSMKEY0 = 0xFFFFFFFF;
+ DcsmZ1Regs.Z1_CSMKEY1 = 0x4D7FFFFF;
+ DcsmZ1Regs.Z1_CSMKEY2 = 0xFFFFFFFF;
+ DcsmZ1Regs.Z1_CSMKEY3 = 0xFFFFFFFF;
+
+ DcsmZ2Regs.Z2_CSMKEY0 = 0xFFFFFFFF;
+ DcsmZ2Regs.Z2_CSMKEY1 = 0x3FFFFFFF;
+ DcsmZ2Regs.Z2_CSMKEY2 = 0xFFFFFFFF;
+ DcsmZ2Regs.Z2_CSMKEY3 = 0xFFFFFFFF;
+ EDIS;
+
+ return(0);
+}
+
+//
+// SysIntOsc1Sel - This function switches to Internal Oscillator 1.
+//
+void SysIntOsc1Sel(void)
+{
+ EALLOW;
+ ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1
+ EDIS;
+}
+
+//
+// SysIntOsc2Sel - This function switches to Internal oscillator 2.
+//
+void SysIntOsc2Sel(void)
+{
+ EALLOW;
+ ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2
+ EDIS;
+}
+
+//
+// PollX1Counter - Clear the X1CNT counter and then wait for it to saturate
+// four times.
+//
+static void
+PollX1Counter(void)
+{
+ Uint16 loopCount = 0;
+
+ //
+ // Delay for 1 ms while the XTAL powers up
+ //
+ // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles
+ //
+ F28x_usDelay(2000);
+
+ //
+ // Clear and saturate X1CNT 4 times to guarantee operation
+ //
+ do
+ {
+ //
+ // Keep clearing the counter until it is no longer saturated
+ //
+ while(ClkCfgRegs.X1CNT.all > 0x1FF)
+ {
+ ClkCfgRegs.X1CNT.bit.CLR = 1;
+ ClkCfgRegs.X1CNT.bit.CLR = 0;
+ }
+
+ //
+ // Wait for the X1 clock to saturate
+ //
+ while(ClkCfgRegs.X1CNT.all != 0x3FFU)
+ {
+ ;
+ }
+
+ //
+ // Increment the counter
+ //
+ loopCount++;
+ }while(loopCount < 4);
+}
+// SysXtalOscSel - This function switches to External CRYSTAL oscillator.
+//
+void SysXtalOscSel(void)
+{
+ EALLOW;
+ ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC
+ ClkCfgRegs.XTALCR.bit.SE = 0; // Select crystal mode
+ EDIS;
+
+ //
+ // Wait for the X1 clock to saturate
+ //
+ PollX1Counter();
+
+ //
+ // Select XTAL as the oscillator source
+ //
+ EALLOW;
+ ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1;
+ EDIS;
+
+ //
+ // If a missing clock failure was detected, try waiting for the X1 counter
+ // to saturate again. Consider modifying this code to add a 10ms timeout.
+ //
+ while(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0)
+ {
+ EALLOW;
+ ClkCfgRegs.MCDCR.bit.MCLKCLR = 1;
+ EDIS;
+
+ //
+ // Wait for the X1 clock to saturate
+ //
+ PollX1Counter();
+
+ //
+ // Select XTAL as the oscillator source
+ //
+ EALLOW;
+ ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1;
+ EDIS;
+ }
+}
+//
+// SysXtalOscSESel - This function switches to external oscillator in
+// single-ended mode and turns off all other clock sources to minimize power
+// consumption. This option may not be available on all device packages
+//
+void
+SysXtalOscSESel (void)
+{
+ EALLOW;
+ ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC
+ ClkCfgRegs.XTALCR.bit.SE = 1; // Select single-ended mode
+ EDIS;
+
+ //
+ // Wait for the X1 clock to saturate
+ //
+ PollX1Counter();
+
+ //
+ // Select XTALOSC as the oscillator source
+ //
+ EALLOW;
+ ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1;
+ EDIS;
+
+ //
+ // If missing clock detected, there is something wrong with the oscillator
+ // module.
+ //
+ if(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0)
+ {
+ ESTOP0;
+ }
+}
+//
+// AuxIntOsc2Sel - This function switches to Internal oscillator 2.
+//
+void AuxIntOsc2Sel(void)
+{
+ EALLOW;
+ ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2
+ EDIS;
+}
+
+//
+// AuxXtalOscSel - This function switches to External CRYSTAL oscillator in
+// crystal mode.
+//
+void AuxXtalOscSel(void)
+{
+ EALLOW;
+ ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC
+ ClkCfgRegs.XTALCR.bit.SE = 0; // Select crystal mode
+ PollX1Counter(); // Wait for the X1 clock to saturate
+ ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL
+ EDIS;
+}
+
+//
+// AuxXtalOscSESel - This function switches to External CRYSTAL oscillator in
+// single-ended mode.
+//
+void AuxXtalOscSESel(void)
+{
+ EALLOW;
+ ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC
+ ClkCfgRegs.XTALCR.bit.SE = 1; // Select single-ended mode
+ PollX1Counter(); // Wait for the X1 clock to saturate
+ ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL
+ EDIS;
+}
+//
+// AuxAuxClkSel - This function switches to AUXCLKIN (from a GPIO).
+//
+void AuxAuxClkSel(void)
+{
+ EALLOW;
+ ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = XTAL
+ EDIS;
+}
+
+//
+// IDLE - Enter IDLE mode (single CPU).
+//
+void IDLE(void)
+{
+ EALLOW;
+ CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE;
+ EDIS;
+ asm(" IDLE");
+}
+
+//
+// STANDBY - Enter STANDBY mode (single CPU).
+//
+void STANDBY(void)
+{
+ EALLOW;
+ CpuSysRegs.LPMCR.bit.LPM = LPM_STANDBY;
+ EDIS;
+ asm(" IDLE");
+}
+
+#ifdef CPU1
+//
+// IsPLLValid - This function validates PLL Raw Clock Frequency
+//
+bool
+IsPLLValid(Uint32 base, Uint16 oscSource, Uint16 pllclk, Uint16 imult,
+ Uint16 odiv, Uint16 refdiv)
+{
+ float fclk1_0ratio;
+ volatile struct DCC_REGS *DccRegs;
+
+ EALLOW;
+
+ //
+ // Assigning DCC for PLL validation
+ // Enable Peripheral Clock Domain PCLKCR21 for DCC
+ //
+ if(base == SYSCTL_DCC_BASE0)
+ {
+ DccRegs = &Dcc0Regs;
+ CpuSysRegs.PCLKCR21.bit.DCC0 = 1;
+ }
+ else if(base == SYSCTL_DCC_BASE1)
+ {
+ DccRegs = &Dcc1Regs;
+ CpuSysRegs.PCLKCR21.bit.DCC1 = 1;
+ }
+ else if(base == SYSCTL_DCC_BASE2)
+ {
+ DccRegs = &Dcc2Regs;
+ CpuSysRegs.PCLKCR21.bit.DCC2 = 1;
+ }
+ else
+ ESTOP0; // Invalid DCC selected
+
+ //
+ // Clear Error & Done Flag
+ //
+ DccRegs->DCCSTATUS.bit.ERR = 1;
+ DccRegs->DCCSTATUS.bit.DONE = 1;
+
+ //
+ // Disable DCC
+ //
+ DccRegs->DCCGCTRL.bit.DCCENA = 0x5;
+
+ //
+ // Disable Error Signal
+ //
+ DccRegs->DCCGCTRL.bit.ERRENA = 0x5;
+
+ //
+ // Disable Done Signal
+ //
+ DccRegs->DCCGCTRL.bit.DONEENA = 0x5;
+
+ //
+ // Configure Clock Source1 to PLL
+ //
+ // Clk Src1 Key 0xA to enable clock source selection
+ //
+ switch(pllclk)
+ {
+ case INT_PLL_SYSPLL:
+ DccRegs->DCCCLKSRC1.all = 0xA000; // Clk Src1 = SYSPLL
+ break;
+
+ case INT_PLL_AUXPLL:
+ DccRegs->DCCCLKSRC1.all = 0xA001; // Clk Src1 = AUXPLL
+ break;
+
+ default:
+ //
+ // Code shouldn't reach here
+ //
+ break;
+ }
+
+ //
+ // Configure Clock Source0 to whatever is set as a reference
+ // clock source for PLL
+ //
+ // Clk Src0 Key 0xA to enable clock source selection
+ //
+ switch(oscSource)
+ {
+ case INT_OSC1:
+ DccRegs->DCCCLKSRC0.all = 0xA001; // Clk Src0 = INTOSC1
+ break;
+
+ case INT_OSC2:
+ DccRegs->DCCCLKSRC0.all = 0xA002; // Clk Src0 = INTOSC2
+ break;
+
+ case XTAL_OSC:
+ case XTAL_OSC_SE:
+ DccRegs->DCCCLKSRC0.all = 0xA000; // Clk Src0 = XTAL
+ break;
+
+ default:
+ //
+ // Code shouldn't reach here
+ //
+ break;
+ }
+
+ //
+ // Calculating frequency ratio of output clock(f1) vs reference clock(f0)
+ //
+ fclk1_0ratio = (float)imult / ((odiv + 1U) * (refdiv + 1));
+
+ //
+ // Computing and configuring Counter0 , Counter1 & Valid Seed Values
+ // with +/-1% tolerance for the desired DCC
+ //
+ ComputeCntrSeedValue(base, fclk1_0ratio, DCC_COUNTER0_TOLERANCE);
+
+ //
+ // Enable Single Shot Mode
+ //
+ DccRegs->DCCGCTRL.bit.SINGLESHOT = 0xA;
+
+ //
+ // Enable DCC to start counting
+ //
+ DccRegs->DCCGCTRL.bit.DCCENA = 0xA;
+ EDIS;
+
+ //
+ // Wait until Error or Done Flag is generated
+ //
+ while((DccRegs->DCCSTATUS.all & 3) == 0)
+ {
+ }
+
+ //
+ // Returns true if DCC completes without error
+ //
+ return((DccRegs->DCCSTATUS.all & 3) == 2);
+
+}
+
+//*****************************************************************************
+//
+// ComputeCntSeedValid - Compute Counter seed values based on the frequency ratio of output
+// clock vs reference clock & tolerance expected for the desired DCC
+//
+//*****************************************************************************
+void ComputeCntrSeedValue(Uint32 base, float fclk1_0ratio, Uint32 tolerance)
+{
+ Uint32 window, dccCounterSeed0, dccValidSeed0, dccCounterSeed1, total_error;
+ volatile struct DCC_REGS *DccRegs;
+
+ if(fclk1_0ratio >= 1U)
+ {
+ //
+ // Setting Counter0 & Valid Seed Value with expected tolerance
+ // Total error is 12
+ //
+ window = (12U * 100U) / tolerance;
+ dccCounterSeed0 = window - 12U;
+ dccValidSeed0 = 24U;
+
+ }
+ else
+ {
+ total_error = (((Uint32)2U / fclk1_0ratio) + (Uint32)10U);
+
+ window = ((total_error * 100U)/ tolerance);
+
+ //
+ // Setting Counter0 & Valid Seed Value with expected tolerance
+ //
+ dccCounterSeed0 = window - total_error;
+ dccValidSeed0 = (Uint32)2U * total_error;
+
+ }
+
+ //
+ // Multiplying Counter-0 window with PLL Integer Multiplier
+ //
+ dccCounterSeed1 = window * fclk1_0ratio;
+
+ //
+ // Assigning DCC for PLL validation
+ //
+ if(base == SYSCTL_DCC_BASE0)
+ DccRegs = &Dcc0Regs;
+ else if(base == SYSCTL_DCC_BASE1)
+ DccRegs = &Dcc1Regs;
+ else if(base == SYSCTL_DCC_BASE2)
+ DccRegs = &Dcc2Regs;
+ else
+ ESTOP0; // Invalid DCC selected
+
+ //
+ // Configure COUNTER-0, COUNTER-1 & Valid Window
+ //
+ DccRegs->DCCCNTSEED0.bit.COUNTSEED0 = dccCounterSeed0; // Loaded Counter0 Value
+ DccRegs->DCCVALIDSEED0.bit.VALIDSEED = dccValidSeed0; // Loaded Valid Value
+ DccRegs->DCCCNTSEED1.bit.COUNTSEED1 = dccCounterSeed1; // Loaded Counter1 Value
+}
+#endif
+
+//
+// End of File
+//
+
diff --git a/Projects/epwm_test/lib/f2838x_usdelay.asm b/Projects/epwm_test/lib/f2838x_usdelay.asm
new file mode 100644
index 0000000..a29cb5c
--- /dev/null
+++ b/Projects/epwm_test/lib/f2838x_usdelay.asm
@@ -0,0 +1,108 @@
+;//###########################################################################
+;//
+;// FILE: f2838x_usdelay.asm
+;//
+;// TITLE: Simple delay function
+;//
+;// DESCRIPTION:
+;// This is a simple delay function that can be used to insert a specified
+;// delay into code.
+;// This function is only accurate if executed from internal zero-waitstate
+;// SARAM. If it is executed from waitstate memory then the delay will be
+;// longer then specified.
+;// To use this function:
+;// 1 - update the CPU clock speed in the f2838x_examples.h
+;// file. For example:
+;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
+;// 2 - Call this function by using the DELAY_US(A) macro
+;// that is defined in the f2838x_device.h file. This macro
+;// will convert the number of microseconds specified
+;// into a loop count for use with this function.
+;// This count will be based on the CPU frequency you specify.
+;// 3 - For the most accurate delay
+;// - Execute this function in 0 waitstate RAM.
+;// - Disable interrupts before calling the function
+;// If you do not disable interrupts, then think of
+;// this as an "at least" delay function as the actual
+;// delay may be longer.
+;// The C assembly call from the DELAY_US(time) macro will
+;// look as follows:
+;// extern void Delay(long LoopCount);
+;// MOV AL,#LowLoopCount
+;// MOV AH,#HighLoopCount
+;// LCR _Delay
+;// Or as follows (if count is less then 16-bits):
+;// MOV ACC,#LoopCount
+;// LCR _Delay
+;//
+;//###########################################################################
+;//
+;//
+;// $Copyright:
+;// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
+;//
+;// Redistribution and use in source and binary forms, with or without
+;// modification, are permitted provided that the following conditions
+;// are met:
+;//
+;// Redistributions of source code must retain the above copyright
+;// notice, this list of conditions and the following disclaimer.
+;//
+;// Redistributions in binary form must reproduce the above copyright
+;// notice, this list of conditions and the following disclaimer in the
+;// documentation and/or other materials provided with the
+;// distribution.
+;//
+;// Neither the name of Texas Instruments Incorporated nor the names of
+;// its contributors may be used to endorse or promote products derived
+;// from this software without specific prior written permission.
+;//
+;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;// $
+;//###########################################################################
+
+ .if __TI_EABI__
+ .asg F28x_usDelay, _F28x_usDelay
+ .endif
+ .def _F28x_usDelay
+
+ .cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro
+ %{
+ %}
+
+ .if __TI_COMPILER_VERSION__
+ .if __TI_COMPILER_VERSION__ >= 15009000
+ .sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer
+ .else
+ .sect "ramfuncs" ;;Used with compilers older than v15.9.0
+ .endif
+ .endif
+
+ .global __F28x_usDelay
+_F28x_usDelay:
+ SUB ACC,#1
+ BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0
+ LRETR
+
+;There is a 9/10 cycle overhead and each loop
+;takes five cycles. The LoopCount is given by
+;the following formula:
+; DELAY_CPU_CYCLES = 9 + 5*LoopCount
+; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
+; The macro DELAY_US(A) performs this calculation for you
+;
+;
+
+;//
+;// End of file
+;//
diff --git a/Projects/epwm_test/src/ExternalEEPROM/BL25CM1A.c b/Projects/epwm_test/src/ExternalEEPROM/BL25CM1A.c
new file mode 100644
index 0000000..c621be5
--- /dev/null
+++ b/Projects/epwm_test/src/ExternalEEPROM/BL25CM1A.c
@@ -0,0 +1,61 @@
+/*
+ * BL25CM1A.c
+ *
+ * Created on: 7 сент. 2023 г.
+ * Author: seklyuts
+ */
+#include "f28x_project.h"
+#include "spi_init.h"
+
+#define WREN 0b00000110 //Enable Write Operations
+#define WRDI 0b00000100 //Disable Write Operations
+#define RDSR 0b00000101 //Read Status Register
+#define WRSR 0b00000001 //Write Status Register
+#define READ 0b00000011 //Read Data from Memory
+#define WRITE 0b00000010 //Write Data to Memory
+#define RDID 0b10000011 //Read identification page
+#define WRID 0b10000010 //Write identification page
+#define RDLS 0b10000011 //Reads the identification page lock status
+#define LID 0b10000010 //Locks the identification page in read-only mode
+
+
+uint16_t sdata2 = RDSR; // sent data
+uint16_t rdata2 = 0; // received data
+uint16_t error2 = 0;
+
+void Bl25cm1a_en(void)
+{
+ transmitBData(WREN);
+ while(SpibRegs.SPIFFRX.bit.RXFFST != 1)
+ {
+
+ }
+
+ rdata2 = SpibRegs.SPIRXBUF;
+}
+
+
+void Bl25cm1a_write(void)
+{
+ transmitBData(sdata2);
+
+ //
+ // Wait until data is received
+ //
+ while(SpibRegs.SPIFFRX.bit.RXFFST != 1)
+ {
+
+ }
+
+ rdata2 = SpibRegs.SPIRXBUF;
+
+
+}
+
+void Bl25cm1a_read(void)
+{
+
+
+
+
+}
diff --git a/Projects/epwm_test/src/ExternalEEPROM/BL25CM1A.h b/Projects/epwm_test/src/ExternalEEPROM/BL25CM1A.h
new file mode 100644
index 0000000..e42dc40
--- /dev/null
+++ b/Projects/epwm_test/src/ExternalEEPROM/BL25CM1A.h
@@ -0,0 +1,15 @@
+/*
+ * BL25CM1A.h
+ *
+ * Created on: 7 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_BL25CM1A_H_
+#define SRC_BL25CM1A_H_
+
+void Bl25cm1a_en(void);
+void Bl25cm1a_write(void);
+void Bl25cm1a_read(void);
+
+#endif /* SRC_BL25CM1A_H_ */
diff --git a/Projects/epwm_test/src/ExternalEEPROM/ExtEEPROM.c b/Projects/epwm_test/src/ExternalEEPROM/ExtEEPROM.c
new file mode 100644
index 0000000..ea47b03
--- /dev/null
+++ b/Projects/epwm_test/src/ExternalEEPROM/ExtEEPROM.c
@@ -0,0 +1,51 @@
+/*
+ * ExtEEPROM.c
+ *
+ * Created on: 14 сент. 2023 г.
+ * Author: seklyuts
+ */
+#include "f28x_project.h"
+#include "BL25CM1A.h"
+#include "GD25Q16ETIGR.h"
+#include "ZD24C02A.h"
+
+#define MAX_BUFFER_SIZE 0x10
+
+uint16_t sendNowI2C = 0, sendNowSPI = 0;
+uint16_t TestADR = 0;
+uint16_t NByte = 16;
+uint16_t WriteI2C = 0;
+uint16_t Adr = 0;
+
+uint16_t ArrayForTests[MAX_BUFFER_SIZE] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10};
+uint16_t ArrayMax[256];
+
+void ExtEEPROM_run(void)
+{
+ if(sendNowI2C)
+ {
+ if(WriteI2C)
+ {
+ ArrayForTests[0] = Adr;
+ ZD24C02A_write(NByte, ArrayForTests);
+ }
+ else
+ {
+ ArrayForTests[0] = Adr;
+ ZD24C02A_read(NByte, ArrayForTests);
+ }
+ sendNowI2C = 0;
+ }
+
+ if(sendNowSPI == 1)
+ {
+ GD25Q16ETIGR_write();
+ sendNowSPI = 0;
+ }
+
+ else if(sendNowSPI == 2)
+ {
+ Bl25cm1a_write();
+ sendNowSPI = 0;
+ }
+}
diff --git a/Projects/epwm_test/src/ExternalEEPROM/ExtEEPROM.h b/Projects/epwm_test/src/ExternalEEPROM/ExtEEPROM.h
new file mode 100644
index 0000000..532a59a
--- /dev/null
+++ b/Projects/epwm_test/src/ExternalEEPROM/ExtEEPROM.h
@@ -0,0 +1,13 @@
+/*
+ * ExtEEPROM.h
+ *
+ * Created on: 14 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_EXTEEPROM_H_
+#define SRC_EXTEEPROM_H_
+
+void ExtEEPROM_run(void);
+
+#endif /* SRC_EXTEEPROM_H_ */
diff --git a/Projects/epwm_test/src/ExternalEEPROM/GD25Q16ETIGR.c b/Projects/epwm_test/src/ExternalEEPROM/GD25Q16ETIGR.c
new file mode 100644
index 0000000..14e2a50
--- /dev/null
+++ b/Projects/epwm_test/src/ExternalEEPROM/GD25Q16ETIGR.c
@@ -0,0 +1,95 @@
+/*
+ * GD25Q16ETIGR.c
+ *
+ * Created on: 7 сент. 2023 г.
+ * Author: seklyuts
+ */
+#include "f28x_project.h"
+#include "spi_init.h"
+
+
+uint16_t sdata1 = 0x6; // sent data
+uint16_t rdata1[256]; // received data
+uint16_t error1 = 0;
+
+void GD25Q16ETIGR_en(void)
+{
+ transmitBData(sdata1);
+ while(SpibRegs.SPIFFRX.bit.RXFFST != 1)
+ {
+
+ }
+ rdata1[0] = SpibRegs.SPIRXBUF;
+}
+
+
+void GD25Q16ETIGR_write(void)
+{
+ uint16_t i;
+ for(i = 0; i<=255; i++)
+ {
+ transmitBData(i);
+
+ //
+ // Wait until data is received
+ //
+ while(SpibRegs.SPIFFRX.bit.RXFFST != 1)
+ {
+
+ }
+ rdata1[i] = SpibRegs.SPIRXBUF;
+ }
+/* transmitData(0x90);
+
+ //
+ // Wait until data is received
+ //
+ while(SpiaRegs.SPIFFRX.bit.RXFFST != 1)
+ {
+
+ }
+ rdata1 = SpiaRegs.SPIRXBUF;
+
+ transmitData(0xFF);
+
+ //
+ // Wait until data is received
+ //
+ while(SpiaRegs.SPIFFRX.bit.RXFFST != 1)
+ {
+
+ }
+ rdata1 = SpiaRegs.SPIRXBUF;
+
+ transmitData(0xFF);
+
+ //
+ // Wait until data is received
+ //
+ while(SpiaRegs.SPIFFRX.bit.RXFFST != 1)
+ {
+
+ }
+ rdata1 = SpiaRegs.SPIRXBUF;
+ transmitData(0xFF);
+
+ //
+ // Wait until data is received
+ //
+ while(SpiaRegs.SPIFFRX.bit.RXFFST != 1)
+ {
+
+ }
+ rdata1 = SpiaRegs.SPIRXBUF;
+ transmitData(0xFF);
+
+ //
+ // Wait until data is received
+ //
+ while(SpiaRegs.SPIFFRX.bit.RXFFST != 1)
+ {
+
+ }
+ rdata1 = SpiaRegs.SPIRXBUF;
+ */
+}
diff --git a/Projects/epwm_test/src/ExternalEEPROM/GD25Q16ETIGR.h b/Projects/epwm_test/src/ExternalEEPROM/GD25Q16ETIGR.h
new file mode 100644
index 0000000..77bbfcb
--- /dev/null
+++ b/Projects/epwm_test/src/ExternalEEPROM/GD25Q16ETIGR.h
@@ -0,0 +1,14 @@
+/*
+ * GD25Q16ETIGR.h
+ *
+ * Created on: 7 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_GD25Q16ETIGR_H_
+#define SRC_GD25Q16ETIGR_H_
+
+void GD25Q16ETIGR_en(void);
+void GD25Q16ETIGR_write(void);
+
+#endif /* SRC_GD25Q16ETIGR_H_ */
diff --git a/Projects/epwm_test/src/ExternalEEPROM/ZD24C02A.c b/Projects/epwm_test/src/ExternalEEPROM/ZD24C02A.c
new file mode 100644
index 0000000..8e54058
--- /dev/null
+++ b/Projects/epwm_test/src/ExternalEEPROM/ZD24C02A.c
@@ -0,0 +1,41 @@
+/*
+ * ZD24C02A.c
+ *
+ * Created on: 8 сент. 2023 г.
+ * Author: seklyuts
+ */
+#include "f28x_project.h"
+#include "i2c_init.h"
+#include "ZD24C02A.h"
+
+volatile uint16_t SlaveAdr = I2C_SLAVE_ADDRESS;
+
+void ZD24C02A_write(uint16_t byteCount, uint16_t * Array)
+{
+ I2CWrite(SlaveAdr, (byteCount + 1), true, Array);
+}
+
+void ZD24C02A_read(uint16_t byteCount, uint16_t * Array)
+{
+ I2CWrite(SlaveAdr, 1, false, Array);
+ I2CRead(SlaveAdr, byteCount, true, Array);
+// I2CWriteRead(I2C_SLAVE_ADDRESS, byteCount, true, Array);
+// I2CWriteReadOnes(I2C_SLAVE_ADDRESS);
+}
+
+void ZD24C02A_read_all(uint16_t byteCount, uint16_t * Array)
+{
+ I2CRead(SlaveAdr, byteCount, true, Array);
+// I2CWriteRead(I2C_SLAVE_ADDRESS, byteCount, true, Array);
+// I2CWriteReadOnes(I2C_SLAVE_ADDRESS);
+}
+
+
+void ZD24C02A_test(uint16_t * Array)
+{
+ uint16_t i=0;
+ for(i=0;i<=255;i+=15)
+ {
+ I2CWrite(SlaveAdr, 1, true, Array);
+ }
+}
diff --git a/Projects/epwm_test/src/ExternalEEPROM/ZD24C02A.h b/Projects/epwm_test/src/ExternalEEPROM/ZD24C02A.h
new file mode 100644
index 0000000..d9a36e4
--- /dev/null
+++ b/Projects/epwm_test/src/ExternalEEPROM/ZD24C02A.h
@@ -0,0 +1,20 @@
+/*
+ * ZD24C02A.h
+ *
+ * Created on: 8 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_ZD24C02A_H_
+#define SRC_ZD24C02A_H_
+
+#define I2C_SLAVE_ADDRESS 0x51U
+#define I2C_OWN_ADDRESS 0x30U
+
+
+void ZD24C02A_write(uint16_t byteCount, uint16_t * Array);
+void ZD24C02A_read(uint16_t byteCount, uint16_t * Array);
+void ZD24C02A_test(uint16_t * Array);
+void ZD24C02A_read_all(uint16_t byteCount, uint16_t * Array);
+
+#endif /* SRC_ZD24C02A_H_ */
diff --git a/Projects/epwm_test/src/Peripherals/gpio_init.c b/Projects/epwm_test/src/Peripherals/gpio_init.c
new file mode 100644
index 0000000..b0117c9
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/gpio_init.c
@@ -0,0 +1,41 @@
+/*
+ * gpio_init.c
+ *
+ * Created on: 4 сент. 2023 г.
+ * Author: seklyuts
+ */
+#include "f28x_project.h"
+
+void GpioInit(void)
+{
+ EALLOW;
+ GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0;
+ GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0;
+ GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 0;
+ GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 0;
+ GpioCtrlRegs.GPADIR.bit.GPIO20 = 1;
+ GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
+ GpioDataRegs.GPADAT.bit.GPIO20 = 0;
+ GpioDataRegs.GPADAT.bit.GPIO21 = 0;
+
+ GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0;
+ GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0;
+ GpioCtrlRegs.GPADIR.bit.GPIO18 = 0;
+
+ GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 0;
+ GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 0;
+ GpioCtrlRegs.GPADIR.bit.GPIO19 = 0;
+
+ EDIS;
+}
+
+void Gpio20out(uint16_t out_bit)
+{
+ GpioDataRegs.GPADAT.bit.GPIO20 = out_bit;
+}
+
+
+void Gpio21out(uint16_t out_bit)
+{
+ GpioDataRegs.GPADAT.bit.GPIO21 = out_bit;
+}
diff --git a/Projects/epwm_test/src/Peripherals/gpio_init.h b/Projects/epwm_test/src/Peripherals/gpio_init.h
new file mode 100644
index 0000000..bc634b2
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/gpio_init.h
@@ -0,0 +1,16 @@
+/*
+ * gpio_init.h
+ *
+ * Created on: 4 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_GPIO_INIT_H_
+#define SRC_GPIO_INIT_H_
+
+
+void GpioInit(void);
+void Gpio20out(uint16_t out_bit);
+void Gpio21out(uint16_t out_bit);
+
+#endif /* SRC_GPIO_INIT_H_ */
diff --git a/Projects/epwm_test/src/Peripherals/i2c_init.c b/Projects/epwm_test/src/Peripherals/i2c_init.c
new file mode 100644
index 0000000..5bdc4b6
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/i2c_init.c
@@ -0,0 +1,484 @@
+/*
+ * i2c_init.c
+ *
+ * Created on: 5 сент. 2023 г.
+ * Author: seklyuts
+ */
+#include "f28x_project.h"
+#include "i2c_init.h"
+//
+// Function to configure I2CA as Master Transmitter.
+//
+
+
+
+
+
+//
+// I2C GPIO pins
+//
+#define GPIO_PIN_SDAA 0U // GPIO number for I2C SDAA
+#define GPIO_PIN_SCLA 1U // GPIO number for I2C SCLA
+
+#define TIME_OVER 1000
+
+uint16_t TimerTimeouts = 0, ErrI2c = 0, ErrI2c1 = 0, ErrI2c2 = 0, ErrI2c3 = 0, Addr=0, Addr1[255];
+uint16_t RXdata, addrCount=0;
+
+void TimerBaseTimeoutInc(void)
+{
+ TimerTimeouts++;
+}
+
+
+void I2CMasterGpioInit(void)
+{
+ //
+ //Configure I2C pins
+ //
+ GPIO_SetupPinMux(GPIO_PIN_SDAA, GPIO_MUX_CPU1, 6);
+ GPIO_SetupPinOptions(GPIO_PIN_SDAA, GPIO_OUTPUT, GPIO_PULLUP);
+ GPIO_SetupPinMux(GPIO_PIN_SCLA, GPIO_MUX_CPU1, 6);
+ GPIO_SetupPinOptions(GPIO_PIN_SCLA, GPIO_OUTPUT, GPIO_PULLUP);
+}
+
+void I2CMasterInit(uint16_t I2C_OwnAddress, uint16_t I2CSlave_Address)
+{
+ EALLOW;
+ //
+ // Must put I2C into reset before configuring it
+ //
+ I2caRegs.I2CMDR.all &= ~(0x20U);
+
+ //
+ // I2C configuration. Use a 400kHz I2CCLK with a 50% duty cycle.
+ //
+ //I2C_initMaster(base, DEVICE_SYSCLK_FREQ, 400000, I2C_DUTYCYCLE_50); = 1000000 / (I2CPSC+1) / (I2CCLKL + I2CCLKH)
+ I2caRegs.I2CPSC.all = 49; // Prescaler - need 7-12 Mhz on module clk
+ I2caRegs.I2CCLKL = 12; // NOTE: must be non zero
+ I2caRegs.I2CCLKH = 12; // NOTE: must be non zero
+
+
+ //
+ // Configure Master as a Transmitter
+ //
+ I2caRegs.I2CMDR.bit.MST = 0x1;
+ I2caRegs.I2CMDR.bit.TRX = 0x1;
+
+ //
+ // Set data count
+ //
+// I2caRegs.I2CCNT = I2C_NUMBYTES;
+
+ //
+ // Set the bit count to 8 bits per data byte
+ //
+ I2caRegs.I2CMDR.bit.BC = 0x0U;
+
+ //
+ // Configure slave and own address
+ //
+ I2caRegs.I2COAR.all = I2C_OwnAddress; // Own address
+ I2caRegs.I2CSAR.all = I2CSlave_Address; // Slave address
+
+ //
+ // Set emulation mode to FREE
+ //
+ I2caRegs.I2CMDR.bit.FREE = 0x1;
+
+ //
+ //Clear all status
+ //
+ I2caRegs.I2CSTR.all = 0xFFFF;
+
+ //
+ // Enable I2C Interrupts- RRDY
+ //
+ I2caRegs.I2CIER.all = 0x08;
+
+ //
+ // Take I2C out of reset
+ //
+ I2caRegs.I2CMDR.all |= 0x0020;
+
+
+}
+
+uint16_t j = 0;
+//
+// Function to send data over I2C.
+//
+void I2CWrite(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition, uint16_t * I2C_TXdata)
+{
+
+ //
+ // Locals
+ //
+ uint16_t index = 0;
+
+ //
+ // Configure slave address
+ //
+ I2caRegs.I2CSAR.all = slaveAddr; // Slave address
+
+ //
+ // Configure I2C as Master Transmitter
+ //
+ I2caRegs.I2CMDR.bit.MST = 0x1;
+ I2caRegs.I2CMDR.bit.TRX = 0x1;
+
+ //
+ //Set Data Count
+ //
+ I2caRegs.I2CCNT = byteCount;
+
+ //
+ // send Start condition
+ //
+// I2caRegs.I2CMDR.bit.STP = 0x1;
+ I2caRegs.I2CMDR.bit.STT = 0x1;
+
+ //
+ //transmit the bytes
+ //
+ for(index=0; index < byteCount; index++)
+ {
+ I2caRegs.I2CDXR.all= I2C_TXdata[index];
+ //
+ //wait till byte is sent
+ //
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CSTR.bit.BYTESENT != 0x1)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c++;
+// else {Addr1[addrCount] = slaveAddr; addrCount++; if(addrCount > 255) addrCount = 0;}
+ //
+ //clear the byte sent
+ //
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+ }
+
+ //
+ // Send STOP condition if specified
+ //
+ if(sendStopCondition)
+ {
+ I2caRegs.I2CMDR.bit.STP = 0x1;
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CMDR.bit.STP != 0x0)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c1++;
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+ }
+}
+
+//
+// Function to read data over I2C. Returns the number of bytes read
+//
+uint16_t ttest=0;
+uint16_t I2CRead(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition, uint16_t * I2C_RXdata)
+{
+ I2caRegs.I2CMDR.bit.NACKMOD = 0x0;
+ //
+ // Configure slave address
+ //
+ I2caRegs.I2CSAR.all = slaveAddr;
+
+ //
+ // Configure I2C in Master Receiver mode
+ //
+ I2caRegs.I2CMDR.bit.MST = 0x1;
+ I2caRegs.I2CMDR.bit.TRX = 0x0;
+
+
+ uint16_t count = 0;
+
+ I2caRegs.I2CCNT = byteCount;
+
+ I2caRegs.I2CMDR.bit.STT = 0x1;
+
+ //
+ // Read the received data into RX buffer
+ //
+ TimerTimeouts = 0;
+ while((count < (byteCount))&&(TimerTimeouts < TIME_OVER))
+ {
+ if(I2caRegs.I2CSTR.bit.RRDY ==0x1)
+ {
+ RXdata = I2C_RXdata[count-1] = I2caRegs.I2CDRR.all;
+ count++;
+ }
+ }
+ if(TimerTimeouts >= TIME_OVER) ErrI2c2 += (byteCount - count);
+
+ //
+ // Send STOP condition
+ //
+ if(sendStopCondition)
+ {
+ I2caRegs.I2CMDR.bit.STP = 0x1;
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CMDR.bit.STP != 0x0)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c3++;
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+ }
+ return count;
+}
+
+
+uint16_t I2CWriteRead(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition, uint16_t * I2C_RXdata)
+{
+ //
+ // Locals
+ //
+
+ //
+ // Configure slave address
+ //
+ I2caRegs.I2CSAR.all = slaveAddr; // Slave address
+
+ //
+ // Configure I2C as Master Transmitter
+ //
+ I2caRegs.I2CMDR.bit.MST = 0x1;
+ I2caRegs.I2CMDR.bit.TRX = 0x1;
+
+ //
+ //Set Data Count
+ //
+ I2caRegs.I2CCNT = 1;
+
+ //
+ // send Start condition
+ //
+ I2caRegs.I2CMDR.bit.STT = 0x1;
+
+ //
+ //transmit the bytes
+ //
+
+ I2caRegs.I2CDXR.all= I2C_RXdata[0];
+ //
+ //wait till byte is sent
+ //
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CSTR.bit.BYTESENT != 0x1)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c++;
+ else Addr = slaveAddr;
+ //
+ //clear the byte sent
+ //
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+
+
+ //
+ // Configure slave address
+ //
+ I2caRegs.I2CSAR.all = slaveAddr;
+
+ //
+ // Configure I2C in Master Receiver mode
+ //
+ I2caRegs.I2CMDR.bit.MST = 0x1;
+ I2caRegs.I2CMDR.bit.TRX = 0x0;
+
+ //
+ //Set Data Count
+ //
+ I2caRegs.I2CCNT = byteCount;
+
+ //
+ // send Start condition
+ //
+ I2caRegs.I2CMDR.bit.STP = 0x1;
+ I2caRegs.I2CMDR.bit.STT = 0x1;
+
+ uint16_t count = 0;
+
+ //
+ // Read the received data into RX buffer
+ //
+ TimerTimeouts = 0;
+ while((count < byteCount)&&(TimerTimeouts < TIME_OVER))
+ {
+ if(count == (byteCount-1)) I2caRegs.I2CMDR.bit.NACKMOD = 0x1;
+ if(I2caRegs.I2CSTR.bit.RRDY ==0x1)
+ {
+ I2C_RXdata[count] = I2caRegs.I2CDRR.all;
+ count++;
+ }
+ }
+ if(TimerTimeouts >= TIME_OVER) ErrI2c2 += (byteCount - count);
+ I2caRegs.I2CMDR.bit.NACKMOD = 0x0;
+
+ //
+ // Send STOP condition
+ //
+ if(sendStopCondition)
+ {
+ I2caRegs.I2CMDR.bit.STP = 0x1;
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CMDR.bit.STP != 0x0)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c3++;
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+ }
+ return count;
+}
+
+
+void I2CWriteReadOnes(uint16_t slaveAddr)
+{
+ //
+ // Locals
+ //
+
+ //
+ // Configure slave address
+ //
+ I2caRegs.I2CSAR.all = slaveAddr; // Slave address
+
+ //
+ // Configure I2C as Master Transmitter
+ //
+ I2caRegs.I2CMDR.bit.MST = 0x1;
+ I2caRegs.I2CMDR.bit.TRX = 0x1;
+
+ //
+ //Set Data Count
+ //
+ I2caRegs.I2CCNT = 1;
+
+ //
+ // send Start condition
+ //
+ I2caRegs.I2CMDR.bit.STT = 0x1;
+
+ //
+ //transmit the bytes
+ //
+
+ I2caRegs.I2CDXR.all= 0x80;
+ //
+ //wait till byte is sent
+ //
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CSTR.bit.BYTESENT != 0x1)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c++;
+ else Addr = slaveAddr;
+ //
+ //clear the byte sent
+ //
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+
+
+ //
+ // Configure slave address
+ //
+ I2caRegs.I2CSAR.all = slaveAddr;
+
+ //
+ // Configure I2C in Master Receiver mode
+ //
+ I2caRegs.I2CMDR.bit.MST = 0x1;
+ I2caRegs.I2CMDR.bit.TRX = 0x0;
+
+ //
+ //Set Data Count
+ //
+ I2caRegs.I2CCNT = 0;
+
+ //
+ // send Start condition
+ //
+ I2caRegs.I2CMDR.bit.STT = 0x1;
+
+ //
+ // Read the received data into RX buffer
+ //
+ TimerTimeouts = 0;
+ I2caRegs.I2CMDR.bit.NACKMOD = 0x1;
+ while((I2caRegs.I2CSTR.bit.RRDY != 0x1)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c2++;
+ else RXdata = I2caRegs.I2CDRR.all;
+ I2caRegs.I2CMDR.bit.NACKMOD = 0x0;
+
+ //
+ // Send STOP condition
+ //
+
+ I2caRegs.I2CMDR.bit.STP = 0x1;
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CMDR.bit.STP != 0x0)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c3++;
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+
+
+}
+
+void I2CWriteOnse(uint16_t slaveAddr)
+{
+
+ //
+ // Locals
+ //
+ //uint16_t index = 0;
+
+ //
+ // Configure slave address
+ //
+ I2caRegs.I2CSAR.all = slaveAddr; // Slave address
+
+ //
+ // Configure I2C as Master Transmitter
+ //
+ I2caRegs.I2CMDR.bit.MST = 0x1;
+ I2caRegs.I2CMDR.bit.TRX = 0x1;
+
+ //
+ //Set Data Count
+ //
+ I2caRegs.I2CCNT = 2;
+
+ //
+ // send Start condition
+ //
+ I2caRegs.I2CMDR.bit.STT = 0x1;
+
+ //
+ //transmit the bytes
+ //
+
+ I2caRegs.I2CDXR.all= 0x80;
+ //
+ //wait till byte is sent
+ //
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CSTR.bit.BYTESENT != 0x1)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c++;
+ else Addr = slaveAddr;
+ //
+ //clear the byte sent
+ //
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+
+ I2caRegs.I2CDXR.all= RXdata;
+ //
+ //wait till byte is sent
+ //
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CSTR.bit.BYTESENT != 0x1)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c++;
+ else Addr = slaveAddr;
+ //
+ //clear the byte sent
+ //
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+ //
+ // Send STOP condition if specified
+ //
+
+ I2caRegs.I2CMDR.bit.STP = 0x1;
+ TimerTimeouts = 0;
+ while((I2caRegs.I2CMDR.bit.STP != 0x0)&&(TimerTimeouts < TIME_OVER));
+ if(TimerTimeouts >= TIME_OVER) ErrI2c1++;
+ I2caRegs.I2CSTR.bit.BYTESENT = 0x1;
+
+}
diff --git a/Projects/epwm_test/src/Peripherals/i2c_init.h b/Projects/epwm_test/src/Peripherals/i2c_init.h
new file mode 100644
index 0000000..7c455a0
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/i2c_init.h
@@ -0,0 +1,28 @@
+/*
+ * i2c_init.h
+ *
+ * Created on: 5 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_PERIPHERALS_I2C_INIT_H_
+#define SRC_PERIPHERALS_I2C_INIT_H_
+
+
+
+//
+// Function Prototypes
+//
+
+
+
+void I2CMasterInit(uint16_t I2CSlave_OwnAddress, uint16_t I2CSlave_Address);
+void I2CWrite(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition, uint16_t * I2C_TXdata);
+uint16_t I2CRead(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition, uint16_t * I2C_RXdata);
+uint16_t I2CWriteRead(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition, uint16_t * I2C_RXdata);
+void I2CMasterGpioInit(void);
+void TimerBaseTimeoutInc(void);
+void I2CWriteReadOnes(uint16_t slaveAddr);
+void I2CWriteOnse(uint16_t slaveAddr);
+
+#endif /* SRC_PERIPHERALS_I2C_INIT_H_ */
diff --git a/Projects/epwm_test/src/Peripherals/pwm_init.c b/Projects/epwm_test/src/Peripherals/pwm_init.c
new file mode 100644
index 0000000..6c28803
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/pwm_init.c
@@ -0,0 +1,197 @@
+/*
+ * init.c
+ *
+ * Created on: 21 авг. 2023 г.
+ * Author: seklyuts
+ */
+
+
+#include
+#include "f28x_project.h"
+#include "pwm_interrupts.h"
+#include "gpio_init.h"
+
+#define COUNT_UP 1
+#define COUNT_DOWN 0
+
+volatile struct EPWM_REGS * EPwmRegs[17] = {NULL, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, &EPwm7Regs, &EPwm8Regs, &EPwm9Regs, &EPwm10Regs, &EPwm11Regs, &EPwm12Regs, &EPwm13Regs, &EPwm14Regs, &EPwm15Regs, &EPwm16Regs};
+uint32_t EPwmTimerIntCount[17];
+uint16_t EPwm_DB_Direction[17];
+volatile uint16_t PwmBrake100 = PERIOD_BRAKE;
+volatile uint16_t PwmMotor100 = PERIOD_MOTOR;
+
+
+void pwm_AutoChange(uint16_t Num)
+{
+ if(EPwm_DB_Direction[Num] == COUNT_UP)
+ {
+ if(EPwmRegs[Num]->CMPA.bit.CMPA < PWM_MAX)
+ {
+ EPwmRegs[Num]->CMPA.bit.CMPA++;
+ }
+ else
+ {
+ EPwm_DB_Direction[Num] = COUNT_DOWN;
+ EPwmRegs[Num]->CMPA.bit.CMPA--;
+ }
+ }
+ else
+ {
+ if(EPwmRegs[Num]->CMPA.bit.CMPA <= PWM_MIN)
+ {
+ EPwm_DB_Direction[Num] = COUNT_UP;
+ EPwmRegs[Num]->CMPA.bit.CMPA++;
+ }
+ else
+ {
+ EPwmRegs[Num]->CMPA.bit.CMPA--;
+ }
+ }
+
+ EPwmTimerIntCount[Num]++;
+}
+
+
+void PWMAllInit(void)
+{
+//
+// Initialize the Device Peripherals:
+//
+ EALLOW;
+ CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
+ EDIS;
+
+
+ PwmBrake100 = PERIOD_BRAKE;
+ PwmMotor100 = PERIOD_MOTOR;
+
+ PWMInit(1, PwmMotor100, INDEPENDED);
+ PWMInit(2, PwmMotor100, COMPLIMENTARY);
+ PWMInit(3, PwmMotor100, COMPLIMENTARY);
+ PWMInit(4, PwmMotor100, COMPLIMENTARY);
+ PWMInit(5, PwmBrake100, INDEPENDED);
+ PWMInit(6, PwmBrake100, INDEPENDED);
+// PWMInit(11, PERIOD, INDEPENDED);
+
+ EALLOW;
+ CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
+ EDIS;
+}
+
+
+void PWMGpioInit(void)
+{
+ InitEPwm2Gpio();
+ InitEPwm3Gpio();
+ InitEPwm4Gpio();
+ InitEPwm5Gpio();
+ InitEPwm6Gpio();
+}
+
+void PWMInitEnable(void)
+{
+ CpuSysRegs.PCLKCR2.bit.EPWM1=1;
+ CpuSysRegs.PCLKCR2.bit.EPWM2=1;
+ CpuSysRegs.PCLKCR2.bit.EPWM3=1;
+ CpuSysRegs.PCLKCR2.bit.EPWM4=1;
+ CpuSysRegs.PCLKCR2.bit.EPWM5=1;
+ CpuSysRegs.PCLKCR2.bit.EPWM6=1;
+}
+
+void PWMInitInterruptEn(void)
+{
+ // Interrupts that are used in this example are re-mapped to
+ // ISR functions found within this file.
+ //
+ EALLOW; // This is needed to write to EALLOW protected registers
+ PieVectTable.EPWM1_INT = &epwm1_isr;
+ PieVectTable.EPWM2_INT = &epwm2_isr;
+ PieVectTable.EPWM3_INT = &epwm3_isr;
+ PieVectTable.EPWM4_INT = &epwm4_isr;
+ PieVectTable.EPWM5_INT = &epwm5_isr;
+ PieVectTable.EPWM6_INT = &epwm6_isr;
+ EDIS; // This is needed to disable write to EALLOW protected registers
+
+
+ // Enable CPU INT3 which is connected to EPWM1-3 INT:
+ //
+ IER |= M_INT3;
+
+ //
+ // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
+ //
+ PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
+ PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
+ PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
+ PieCtrlRegs.PIEIER3.bit.INTx4 = 1;
+ PieCtrlRegs.PIEIER3.bit.INTx5 = 1;
+ PieCtrlRegs.PIEIER3.bit.INTx6 = 1;
+
+}
+
+void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
+{
+
+ EPwmRegs[Num]->TBPRD = Period; // Set timer period
+ EPwmRegs[Num]->TBPHS.bit.TBPHS = 0x0000; // Phase is 0
+ EPwmRegs[Num]->TBCTR = 0x0000; // Clear counter
+
+ //
+ // Setup TBCLK
+ //
+ EPwmRegs[Num]->TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
+ EPwmRegs[Num]->TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
+ EPwmRegs[Num]->TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
+ EPwmRegs[Num]->TBCTL.bit.CLKDIV = TB_DIV1;
+
+ EPwmRegs[Num]->CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
+ EPwmRegs[Num]->CMPCTL.bit.SHDWBMODE = CC_SHADOW;
+ EPwmRegs[Num]->CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
+ EPwmRegs[Num]->CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
+
+ //
+ // Setup compare
+ //
+
+
+ //
+ // Set actions
+ //
+ EPwmRegs[Num]->AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
+ EPwmRegs[Num]->AQCTLA.bit.CAD = AQ_CLEAR;
+
+ EPwmRegs[Num]->AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
+ EPwmRegs[Num]->AQCTLB.bit.CAD = AQ_SET;
+
+ //
+ // Active Low PWMs - Setup Deadband
+ //
+ EPwmRegs[Num]->DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
+ if(Independed)
+ {
+ EPwmRegs[Num]->CMPA.bit.CMPA = Period;
+ EPwmRegs[Num]->DBCTL.bit.POLSEL = DB_ACTV_HI; //DB_ACTV_HI - independ
+ EPwmRegs[Num]->DBRED.bit.DBRED = 0;
+ EPwmRegs[Num]->DBFED.bit.DBFED = 0;
+ }
+ else
+ {
+ EPwmRegs[Num]->CMPA.bit.CMPA = Period/2;
+ EPwmRegs[Num]->DBCTL.bit.POLSEL = DB_ACTV_HIC;
+ EPwmRegs[Num]->DBRED.bit.DBRED = EPWM_DB;
+ EPwmRegs[Num]->DBFED.bit.DBFED = EPWM_DB;
+ }
+ EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL;
+
+// EPwm1_DB_Direction = COUNT_UP;
+
+ //
+ //
+ EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
+ EPwmRegs[Num]->ETSEL.bit.INTEN = 1; // Enable INT
+ EPwmRegs[Num]->ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1 event
+}
+
+
+
+
diff --git a/Projects/epwm_test/src/Peripherals/pwm_init.h b/Projects/epwm_test/src/Peripherals/pwm_init.h
new file mode 100644
index 0000000..0a69c9d
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/pwm_init.h
@@ -0,0 +1,47 @@
+/*
+ * init.h
+ *
+ * Created on: 21 авг. 2023 г.
+ * Author: seklyuts
+ */
+#include "f28x_project.h"
+
+#ifndef SRC_PWM_INIT_H_
+#define SRC_PWM_INIT_H_
+
+#define SYS_PWM_FREQUENCY 100000000.0 //Hz
+
+
+#define FREQUENCY_BRAKE 20000.0 //Hz
+#define FREQUENCY_MOTOR 10000.0 //Hz
+#define EPWM_DB_mkS 3.0 //mkS
+
+#define PERIOD_BRAKE (SYS_PWM_FREQUENCY/2/FREQUENCY_BRAKE) //Tic
+#define PERIOD_MOTOR (SYS_PWM_FREQUENCY/2/FREQUENCY_MOTOR) //Tic
+
+#define EPWM_DB (EPWM_DB_mkS*SYS_PWM_FREQUENCY/2/1000000)
+
+#define PERIOD_2 (PERIOD_MOTOR/2)
+#define PWM_MAX (PERIOD_MOTOR - EPWM_DB)
+#define PWM_MIN EPWM_DB
+#define INDEPENDED 1
+#define COMPLIMENTARY 0
+
+
+void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed);
+void PWMGpioInit(void);
+void PWMInitEnable(void);
+void PWMInitInterruptEn(void);
+void PWMAllInit(void);
+
+void InitEPwm1Example(void);
+void InitEPwm2Example(void);
+void InitEPwm3Example(void);
+void InitEPwm4Example(void);
+void InitEPwm5Example(void);
+void InitEPwm6Example(void);
+
+void pwm_AutoChange(uint16_t Num);
+
+
+#endif /* SRC_PWM_INIT_H_ */
diff --git a/Projects/epwm_test/src/Peripherals/pwm_interrupts.c b/Projects/epwm_test/src/Peripherals/pwm_interrupts.c
new file mode 100644
index 0000000..6fd4272
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/pwm_interrupts.c
@@ -0,0 +1,152 @@
+/*
+ * interrupts.c
+ *
+ * Created on: 21 авг. 2023 г.
+ * Author: seklyuts
+ */
+
+#include
+#include "f28x_project.h"
+#include"frm_uart.h"
+#include "gpio_init.h"
+#include "i2c_init.h"
+#include "timer_base.h"
+
+volatile uint16_t AutoChange = 0;
+volatile uint16_t PWM_out = 0;
+volatile uint16_t PWM_motor = PERIOD_2;
+uint16_t Fault = 0, Fault_fix = 0, Ready = 0;
+//
+// epwm1_isr - EPWM1 ISR
+//
+__interrupt void epwm1_isr(void)
+{
+// if(AutoChange) pwm_AutoChange(1);
+// else
+ EPwm1Regs.CMPA.bit.CMPA = PWM_out;
+
+ //
+ // Clear INT flag for this timer
+ //
+ EPwm1Regs.ETCLR.bit.INT = 1;
+ TimerBaseTimeoutInc();
+ MainTimerBaseTimeoutInc();
+
+ //
+ // Acknowledge this interrupt to receive more interrupts from group 3
+ //
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+}
+
+//
+// epwm2_isr - EPWM2 ISR
+//
+__interrupt void epwm2_isr(void)
+{
+ Gpio20out(1);
+// if(AutoChange) pwm_AutoChange(2);
+// else
+ EPwm2Regs.CMPA.bit.CMPA = PERIOD_MOTOR - PWM_motor;
+// GpioDataRegs.GPADAT.bit.GPIO0 = 1;
+ FMSTR_enable_set();
+ //
+ // Clear INT flag for this timer
+ //
+ EPwm2Regs.ETCLR.bit.INT = 1;
+ Gpio20out(0);
+ //
+ // Acknowledge this interrupt to receive more interrupts from group 3
+ //
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+// GpioDataRegs.GPADAT.bit.GPIO0 = 0;
+
+}
+
+//
+// epwm3_isr - EPWM3 ISR
+//
+__interrupt void epwm3_isr(void)
+{
+// if(AutoChange) pwm_AutoChange(3);
+// else
+ EPwm3Regs.CMPA.bit.CMPA = PERIOD_MOTOR - PWM_motor;
+
+ //
+ // Clear INT flag for this timer
+ //
+ EPwm3Regs.ETCLR.bit.INT = 1;
+
+ //
+ // Acknowledge this interrupt to receive more interrupts from group 3
+ //
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+
+}
+
+__interrupt void epwm4_isr(void)
+{
+// if(AutoChange) pwm_AutoChange(4);
+// else
+ EPwm4Regs.CMPA.bit.CMPA = PERIOD_MOTOR - PWM_motor;
+ //
+ // Clear INT flag for this timer
+ //
+ EPwm4Regs.ETCLR.bit.INT = 1;
+
+ //
+ // Acknowledge this interrupt to receive more interrupts from group 3
+ //
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+}
+
+__interrupt void epwm5_isr(void)
+{
+ Ready = GpioDataRegs.GPADAT.bit.GPIO19;
+ Fault = !GpioDataRegs.GPADAT.bit.GPIO18;
+ if(Fault || Fault_fix)
+ {
+ EPwm5Regs.CMPA.bit.CMPA = PERIOD_BRAKE;
+ PWM_out = 0;
+ if(Fault)Fault_fix = 1;
+ }
+ else
+ {
+// if(AutoChange) pwm_AutoChange(5);
+// else
+ EPwm5Regs.CMPA.bit.CMPA = PERIOD_BRAKE - PWM_out;
+ }
+
+ //
+ // Clear INT flag for this timer
+ //
+ EPwm5Regs.ETCLR.bit.INT = 1;
+
+ //
+ // Acknowledge this interrupt to receive more interrupts from group 3
+ //
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+}
+
+__interrupt void epwm6_isr(void)
+{
+
+// if(AutoChange) pwm_AutoChange(6);
+// else
+ EPwm6Regs.CMPA.bit.CMPA = PERIOD_BRAKE - PWM_out;
+ //
+ // Clear INT flag for this timer
+ //
+ EPwm6Regs.ETCLR.bit.INT = 1;
+
+ //
+ // Acknowledge this interrupt to receive more interrupts from group 3
+ //
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
+}
+
+
+
+
+//
+// InitEPwm1Example - Initialize EPWM1 configuration
+//
diff --git a/Projects/epwm_test/src/Peripherals/pwm_interrupts.h b/Projects/epwm_test/src/Peripherals/pwm_interrupts.h
new file mode 100644
index 0000000..fee4a18
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/pwm_interrupts.h
@@ -0,0 +1,20 @@
+/*
+ * pwm_interrupts.h
+ *
+ * Created on: 21 авг. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_PWM_INTERRUPTS_H_
+#define SRC_PWM_INTERRUPTS_H_
+
+
+__interrupt void epwm1_isr(void);
+__interrupt void epwm2_isr(void);
+__interrupt void epwm3_isr(void);
+__interrupt void epwm4_isr(void);
+__interrupt void epwm5_isr(void);
+__interrupt void epwm6_isr(void);
+
+
+#endif /* SRC_PWM_INTERRUPTS_H_ */
diff --git a/Projects/epwm_test/src/Peripherals/sdfm.c b/Projects/epwm_test/src/Peripherals/sdfm.c
new file mode 100644
index 0000000..aafc89f
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/sdfm.c
@@ -0,0 +1,215 @@
+/*
+ * sdfm.c
+ *
+ * Created on: 25 авг. 2023 г.
+ * Author: seklyuts
+ */
+
+#include "f28x_project.h"
+#include "f2838x_sdfm_drivers.h"
+#include "gpio_init.h"
+//
+// Defines
+//
+#define FILTER_BIT 10
+#define SKIP_FIRST 100
+#define MAX_SAMPLES (1<= (MAX_SAMPLES-1))
+ {
+ loopCounter1 = 0;
+ if(startInitCurrent < SKIP_FIRST) startInitCurrent++;
+ else if(!initDone)
+ {
+ for(i = 0; i <= (MAX_SAMPLES-1); i++)
+ {
+ OffsetCount += Filter1_Result[i];
+ }
+ sdfmOffset = OffsetCount>>FILTER_BIT;
+ initDone = 1;
+ }
+ }
+ Filter1_Result[loopCounter1++] = SDFM1_READ_FILTER1_DATA_16BIT;
+ ADC_ampere = Filter1_Result[loopCounter1-1] - sdfmOffset;
+ }
+
+ if(IntFlags & 0x100)
+ {
+ ADC_ampere = 0;
+ EALLOW;
+ Sdfm1Regs.SDCPARM1.bit.MFIE = 0;
+ EDIS;
+ }
+ else
+ {
+ EALLOW;
+ Sdfm1Regs.SDCPARM1.bit.MFIE = 1;
+ EDIS;
+ }
+
+ //
+ // Clear SDFM flag register
+ //
+ Sdfm_clearFlagRegister(gPeripheralNumber,IntFlags);
+
+ //
+ // Acknowledge this __interrupt to receive more __interrupts from group 5
+ //
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
+ Gpio21out(0);
+}
+
+//Sdfm_clearFlagRegister
+
+//Sdfm_readFlagRegister
+
diff --git a/Projects/epwm_test/src/Peripherals/sdfm.h b/Projects/epwm_test/src/Peripherals/sdfm.h
new file mode 100644
index 0000000..375dee1
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/sdfm.h
@@ -0,0 +1,19 @@
+/*
+ * sdfm.h
+ *
+ * Created on: 25 авг. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_SDFM_H_
+#define SRC_SDFM_H_
+
+void SdfmGpioInit(void);
+void SdfmInitEnable(void);
+void SdfmInitInterruptEn(void);
+void SdfmInit(uint16_t Num);
+
+
+
+
+#endif /* SRC_SDFM_H_ */
diff --git a/Projects/epwm_test/src/Peripherals/spi_init.c b/Projects/epwm_test/src/Peripherals/spi_init.c
new file mode 100644
index 0000000..849b31a
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/spi_init.c
@@ -0,0 +1,261 @@
+/*
+ * spi_init.c
+ *
+ * Created on: 5 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#include "f28x_project.h"
+
+__interrupt void spia_rx_isr(void);
+__interrupt void spia_tx_isr(void);
+
+__interrupt void spib_rx_isr(void);
+__interrupt void spib_tx_isr(void);
+
+
+
+void SpiAInit(void)
+{
+ //
+ // Initialize SPI-A
+ //
+ //
+ // Initialize SPI FIFO registers
+ //
+ CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
+
+ SpiaRegs.SPIFFTX.all = 0xE040;
+ SpiaRegs.SPIFFRX.all = 0x2044;
+ SpiaRegs.SPIFFCT.all = 0x0;
+
+ //
+ // Initialize core SPI registers
+ //
+ //
+ // Set reset low before configuration changes
+ // Clock polarity (0 == rising, 1 == falling)
+ // 16-bit character
+ // Enable loop-back
+ //
+ SpiaRegs.SPICCR.bit.SPISWRESET = 0;
+ SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
+ SpiaRegs.SPICCR.bit.SPICHAR = (8 - 1);
+ SpiaRegs.SPICCR.bit.SPILBK = 0;
+
+ //
+ // Enable master (0 == slave, 1 == master)
+ // Enable transmission (Talk)
+ // Clock phase (0 == normal, 1 == delayed)
+ // SPI interrupts are disabled
+ //
+ SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
+ SpiaRegs.SPICTL.bit.TALK = 1;
+ SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
+ SpiaRegs.SPICTL.bit.SPIINTENA = 0;
+
+ PieCtrlRegs.PIEIER6.bit.INTx1 = 0;
+ PieCtrlRegs.PIEIER6.bit.INTx2 = 0;
+
+ PieVectTable.SPIA_RX_INT = &spia_rx_isr;
+ PieVectTable.SPIA_TX_INT = &spia_tx_isr;
+ //
+ // Set the baud rate using a 1 MHz SPICLK
+ // BRR = (LSPCLK / SPICLK) - 1
+ //
+ SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = ((50000000 / 1000000) - 1);
+
+ // Set FREE bit
+ // Halting on a breakpoint will not halt the SPI
+ //
+ SpiaRegs.SPIPRI.bit.FREE = 1;
+
+ //
+ // Release the SPI from reset
+ //
+ SpiaRegs.SPICCR.bit.SPISWRESET = 1;
+}
+
+void SpiaAGpioInit(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ //
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ //
+ GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
+ GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
+ GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO18 (SPICLKA)
+ GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up on GPIO19 (SPISTEA)
+
+ //
+ // Set qualification for selected pins to asynch only
+ //
+ // This will select asynch (no qualification) for the selected pins.
+ //
+ GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO16 (SPISIMOA)
+ GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO17 (SPISOMIA)
+ GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3; // Asynch input GPIO18 (SPICLKA)
+ GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 3; // Asynch input GPIO19 (SPISTEA)
+
+ //
+ // Configure SPI-A pins
+ //
+ // This specifies which of the possible GPIO pins will be SPI functional
+ // pins.
+ //
+ GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 3; // Configure GPIO16 as SPISIMOA
+ GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 3; // Configure GPIO17 as SPISOMIA
+ GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // Configure GPIO18 as SPICLKA
+ GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO19 as SPISTEA
+
+ EDIS;
+}
+
+void transmitAData(uint16_t a)
+{
+ SpiaRegs.SPITXBUF = a<<8;
+}
+
+
+__interrupt void spia_rx_isr(void)
+{
+ uint16_t temp = SpiaRegs.SPISTS.all;
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+}
+
+
+__interrupt void spia_tx_isr(void)
+{
+ uint16_t temp = SpiaRegs.SPISTS.all;
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+}
+
+
+
+
+
+void SpiBInit(void)
+{
+
+ CpuSysRegs.PCLKCR8.bit.SPI_B = 1;
+
+ SpibRegs.SPIFFTX.all = 0xE040;
+ SpibRegs.SPIFFRX.all = 0x2044;
+ SpibRegs.SPIFFCT.all = 0x0;
+
+ //
+ // Initialize core SPI registers
+ //
+ //
+ // Set reset low before configuration changes
+ // Clock polarity (0 == rising, 1 == falling)
+ // 16-bit character
+ // Enable loop-back
+ //
+ SpibRegs.SPICCR.bit.SPISWRESET = 0;
+ SpibRegs.SPICCR.bit.CLKPOLARITY = 0;
+ SpibRegs.SPICCR.bit.SPICHAR = (8 - 1);
+ SpibRegs.SPICCR.bit.SPILBK = 0;
+
+ //
+ // Enable master (0 == slave, 1 == master)
+ // Enable transmission (Talk)
+ // Clock phase (0 == normal, 1 == delayed)
+ // SPI interrupts are disabled
+ //
+ SpibRegs.SPICTL.bit.MASTER_SLAVE = 1;
+ SpibRegs.SPICTL.bit.TALK = 1;
+ SpibRegs.SPICTL.bit.CLK_PHASE = 1;
+ SpibRegs.SPICTL.bit.SPIINTENA = 0;
+
+ PieCtrlRegs.PIEIER6.bit.INTx3 = 0; //3.4.5 PIE Channel Mapping str 150 of trm
+ PieCtrlRegs.PIEIER6.bit.INTx4 = 0;
+
+ PieVectTable.SPIB_RX_INT = &spib_rx_isr;
+ PieVectTable.SPIB_TX_INT = &spib_tx_isr;
+ //
+ // Set the baud rate using a 1 MHz SPICLK
+ // BRR = (LSPCLK / SPICLK) - 1
+ //
+ SpibRegs.SPIBRR.bit.SPI_BIT_RATE = 99;
+
+ // Set FREE bit
+ // Halting on a breakpoint will not halt the SPI
+ //
+ SpibRegs.SPIPRI.bit.FREE = 1;
+
+ //
+ // Release the SPI from reset
+ //
+ SpibRegs.SPICCR.bit.SPISWRESET = 1;
+}
+
+void SpiaBGpioInit(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ //
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO18 (SPICLKA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO19 (SPISTEA)
+
+ //
+ // Set qualification for selected pins to asynch only
+ //
+ // This will select asynch (no qualification) for the selected pins.
+ //
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 3; // Asynch input GPIO16 (SPISIMOA)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO17 (SPISOMIA)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO18 (SPICLKA)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO19 (SPISTEA)
+
+ //
+ // Configure SPI-A pins
+ //
+ // This specifies which of the possible GPIO pins will be SPI functional
+ // pins.
+ //
+ GPIO_SetupPinMux(24, 0, 6);
+ GPIO_SetupPinMux(25, 0, 6);
+ GPIO_SetupPinMux(26, 0, 6);
+ GPIO_SetupPinMux(27, 0, 6);
+
+// GpioCtrlRegs.GPAMUX1.bit.GPIO24 = 2; // Configure GPIO16 as SPISIMOA
+// GpioCtrlRegs.GPAMUX1.bit.GPIO25 = 2; // Configure GPIO17 as SPISOMIA
+// GpioCtrlRegs.GPAMUX1.bit.GPIO26 = 2; // Configure GPIO18 as SPICLKA
+// GpioCtrlRegs.GPAMUX1.bit.GPIO27 = 2; // Configure GPIO19 as SPISTEA
+// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO16 as SPISIMOA
+// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO17 as SPISOMIA
+// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO18 as SPICLKA
+// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO19 as SPISTEA
+ EDIS;
+}
+
+void transmitBData(uint16_t a)
+{
+ SpibRegs.SPITXBUF = a<<8;
+}
+
+
+__interrupt void spib_rx_isr(void)
+{
+ uint16_t temp = SpibRegs.SPISTS.all;
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+}
+
+
+__interrupt void spib_tx_isr(void)
+{
+ uint16_t temp = SpibRegs.SPISTS.all;
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
+}
diff --git a/Projects/epwm_test/src/Peripherals/spi_init.h b/Projects/epwm_test/src/Peripherals/spi_init.h
new file mode 100644
index 0000000..062ce7b
--- /dev/null
+++ b/Projects/epwm_test/src/Peripherals/spi_init.h
@@ -0,0 +1,18 @@
+/*
+ * spi_init.h
+ *
+ * Created on: 5 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_SPI_INIT_H_
+#define SRC_SPI_INIT_H_
+
+void SpiaAGpioInit(void);
+void SpiAInit(void);
+void transmitAData(uint16_t a);
+
+void SpiaBGpioInit(void);
+void SpiBInit(void);
+void transmitBData(uint16_t a);
+#endif /* SRC_SPI_INIT_H_ */
diff --git a/Projects/epwm_test/src/frm_uart.c b/Projects/epwm_test/src/frm_uart.c
new file mode 100644
index 0000000..516c658
--- /dev/null
+++ b/Projects/epwm_test/src/frm_uart.c
@@ -0,0 +1,123 @@
+/*
+ * frm_uart.c
+ *
+ * Created on: 21 авг. 2023 г.
+ * Author: seklyuts
+ */
+#include "f28x_project.h"
+//#include "f2838x_pinmux.h"
+#include "frm_uart.h"
+
+uint16_t frmEn = 0;
+
+
+uint16_t FMSTR_is_enable(void)
+{
+ return frmEn;
+}
+
+void FMSTR_enable_clr(void)
+{
+ frmEn = 0;
+}
+
+void FMSTR_enable_set(void)
+{
+ frmEn = 1;
+}
+
+void FRMUartInit(void)
+{
+ FMSTR_Init();
+ CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
+
+ // For this example, only init the pins for the SCI-A port.
+ // GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits
+ // GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS
+ // These functions are found in the f2838x_gpio.c file.
+ EALLOW;
+ GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up
+ GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;
+
+ GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; //
+ GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; //
+ EDIS;
+ // GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1);
+ // GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL);
+ // GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1);
+ GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
+ //
+ // Note: Clocks were turned on to the SCIA peripheral
+ // in the InitSysCtrl() function
+ //
+
+ SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
+ // No parity,8 char bits,
+ // async mode, idle-line protocol
+ SciaRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,
+ // Disable RX ERR, SLEEP, TXWAKE
+ SciaRegs.SCICTL2.all = 0x0003;
+ SciaRegs.SCICTL2.bit.TXINTENA = 0;
+ SciaRegs.SCICTL2.bit.RXBKINTENA = 0;
+
+ //
+ // SCIA at 9600 baud
+ // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B.
+ // @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.
+ //
+ SciaRegs.SCIHBAUD.all = 0x0002;
+ SciaRegs.SCILBAUD.all = 0x008B;
+
+ SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
+}
+
+
+
+
+void FMSTR_SCI_PUTCHAR(char _data)
+{
+ SciaRegs.SCITXBUF.all = _data;
+}
+
+char FMSTR_SCI_GETCHAR()
+{
+ return SciaRegs.SCIRXBUF.all; ;
+}
+
+void FMSTR_SCI_RE(void)
+{
+ SciaRegs.SCICTL1.bit.RXENA = 1;
+}
+
+void FMSTR_SCI_RD(void)
+{
+ SciaRegs.SCICTL1.bit.RXENA = 0;
+}
+
+void FMSTR_SCI_TE(void)
+{
+ SciaRegs.SCICTL1.bit.TXENA = 1;
+}
+
+void FMSTR_SCI_TD(void)
+{
+ SciaRegs.SCICTL1.bit.TXENA = 0;
+}
+
+
+FMSTR_SCISR FMSTR_SCI_RDCLRSR(void)
+{
+ FMSTR_SCISR SciSR = 0;
+
+ if (SciaRegs.SCIRXST.bit.RXRDY) // UART receive buffer full
+ {
+ SciSR = FMSTR_SCISR_RDRF;
+ }
+
+ if(SciaRegs.SCICTL2.bit.TXEMPTY) // UART is transmitting data or transmit register full (UART busy)
+ {
+ SciSR |= FMSTR_SCISR_TDRE;
+ }
+
+ return SciSR;
+}
diff --git a/Projects/epwm_test/src/frm_uart.h b/Projects/epwm_test/src/frm_uart.h
new file mode 100644
index 0000000..7ff51e8
--- /dev/null
+++ b/Projects/epwm_test/src/frm_uart.h
@@ -0,0 +1,31 @@
+/*
+ * frm_uart.h
+ *
+ * Created on: 21 авг. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_FRM_UART_H_
+#define SRC_FRM_UART_H_
+
+#include "PE_freemaster_56F8xxx.h"
+
+
+void uart_init_uart2(uint32_t Baudrate);
+void uart_init_uart1(uint32_t Baudrate);
+
+void FMSTR_SCI_PUTCHAR(char _data);
+char FMSTR_SCI_GETCHAR(void);
+void FMSTR_SCI_RE(void);
+void FMSTR_SCI_RD(void);
+void FMSTR_SCI_TE(void);
+void FMSTR_SCI_TD(void);
+FMSTR_SCISR FMSTR_SCI_RDCLRSR(void);
+//void FMSTR_InitSerial(void) ;
+void FRMUartInit(void);
+
+uint16_t FMSTR_is_enable(void);
+void FMSTR_enable_clr(void);
+void FMSTR_enable_set(void);
+
+#endif /* SRC_FRM_UART_H_ */
diff --git a/Projects/epwm_test/src/frmmstr_run.c b/Projects/epwm_test/src/frmmstr_run.c
new file mode 100644
index 0000000..8c71766
--- /dev/null
+++ b/Projects/epwm_test/src/frmmstr_run.c
@@ -0,0 +1,33 @@
+/*
+ * frmmstr_run.c
+ *
+ * Created on: 14 сент. 2023 г.
+ * Author: seklyuts
+ */
+#include "f28x_project.h"
+#include "init_perif.h"
+#include"frm_uart.h"
+
+volatile uint16_t counter=0 ;
+volatile uint16_t counter1=0 ;
+volatile uint16_t counter2=0 ;
+
+void frmmstr_run(void)
+{
+ if(FMSTR_is_enable()) {
+ if(counter < 100) counter++;
+ else
+ {
+ counter = 0;
+ if(counter1 < 100) counter1++;
+ else
+ {
+ counter1=0;
+ counter2++;
+ }
+ }
+ FMSTR_Poll();
+ FMSTR_Recorder();
+ FMSTR_enable_clr();
+ }
+}
diff --git a/Projects/epwm_test/src/frmmstr_run.h b/Projects/epwm_test/src/frmmstr_run.h
new file mode 100644
index 0000000..3aa3703
--- /dev/null
+++ b/Projects/epwm_test/src/frmmstr_run.h
@@ -0,0 +1,13 @@
+/*
+ * frmmstr_run.h
+ *
+ * Created on: 14 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_FRMMSTR_RUN_H_
+#define SRC_FRMMSTR_RUN_H_
+
+void frmmstr_run(void);
+
+#endif /* SRC_FRMMSTR_RUN_H_ */
diff --git a/Projects/epwm_test/src/init_perif.c b/Projects/epwm_test/src/init_perif.c
new file mode 100644
index 0000000..74e4ab2
--- /dev/null
+++ b/Projects/epwm_test/src/init_perif.c
@@ -0,0 +1,83 @@
+/*
+ * init_perif.c
+ *
+ * Created on: 21 авг. 2023 г.
+ * Author: seklyuts
+ */
+
+#include
+#include "f28x_project.h"
+#include "pwm_interrupts.h"
+#include "sdfm.h"
+#include "f2838x_sdfm_drivers.h"
+#include "gpio_init.h"
+#include "spi_init.h"
+#include "i2c_init.h"
+#include "frm_uart.h"
+#include "BL25CM1A.h"
+#include "GD25Q16ETIGR.h"
+#include "ZD24C02A.h"
+
+
+void InitPerif(void)
+{
+ InitSysCtrl();
+
+ PWMGpioInit();
+ PWMInitEnable();
+
+ SdfmGpioInit();
+ SdfmInitEnable();
+
+ SpiaBGpioInit();
+ I2CMasterGpioInit();
+
+
+// Clear all interrupts and initialize PIE vector table:
+// Disable CPU interrupts
+
+ DINT;
+
+//
+// Initialize the PIE control registers to their default state.
+// The default state is all PIE interrupts disabled and flags
+// are cleared.
+// This function is found in the f2838x_piectrl.c file.
+//
+ InitPieCtrl();
+
+//
+// Disable CPU interrupts and clear all CPU interrupt flags:
+//
+ IER = 0x0000;
+ IFR = 0x0000;
+
+//
+// Initialize the PIE vector table with pointers to the shell Interrupt
+// Service Routines (ISR).
+// This will populate the entire table, even if the interrupt
+// is not used in this example. This is useful for debug purposes.
+// The shell ISR routines are found in f2838x_defaultisr.c.
+// This function is found in f2838x_pievect.c.
+//
+ InitPieVectTable();
+
+//
+ GpioInit();
+ PWMInitInterruptEn();
+ PWMAllInit();
+ SdfmInitInterruptEn();
+ SdfmInit(SDFM1);
+ SpiBInit();
+ I2CMasterInit(I2C_OWN_ADDRESS,I2C_SLAVE_ADDRESS);
+//
+// Enable global Interrupts and higher priority real-time debug events:
+//
+ EINT; // Enable Global interrupt INTM
+ ERTM; // Enable Global realtime interrupt DBGM
+
+ FRMUartInit();
+ GD25Q16ETIGR_en();
+// Bl25cm1a_en();
+
+}
diff --git a/Projects/epwm_test/src/init_perif.h b/Projects/epwm_test/src/init_perif.h
new file mode 100644
index 0000000..b863057
--- /dev/null
+++ b/Projects/epwm_test/src/init_perif.h
@@ -0,0 +1,18 @@
+/*
+ * init_perif.h
+ *
+ * Created on: 21 авг. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_INIT_PERIF_H_
+#define SRC_INIT_PERIF_H_
+
+
+
+
+void InitPerif(void);
+
+
+
+#endif /* SRC_INIT_PERIF_H_ */
diff --git a/Projects/epwm_test/src/timer_base.c b/Projects/epwm_test/src/timer_base.c
new file mode 100644
index 0000000..d9c4ec4
--- /dev/null
+++ b/Projects/epwm_test/src/timer_base.c
@@ -0,0 +1,27 @@
+/*
+ * timer_base.c
+ *
+ * Created on: 11 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#include "f28x_project.h"
+
+
+uint16_t MainTimerTimeouts = 0;
+
+void MainTimerBaseTimeoutInc(void)
+{
+ MainTimerTimeouts++;
+}
+
+void MainTimerBaseTimeoutClr(void)
+{
+ MainTimerTimeouts = 0;
+}
+
+bool MainTimerBaseTimeoutCheck(uint16_t timeOff)
+{
+ if(MainTimerTimeouts >= timeOff) return true;
+ else return false;
+}
diff --git a/Projects/epwm_test/src/timer_base.h b/Projects/epwm_test/src/timer_base.h
new file mode 100644
index 0000000..749ed08
--- /dev/null
+++ b/Projects/epwm_test/src/timer_base.h
@@ -0,0 +1,15 @@
+/*
+ * timer_base.h
+ *
+ * Created on: 11 сент. 2023 г.
+ * Author: seklyuts
+ */
+
+#ifndef SRC_TIMER_BASE_H_
+#define SRC_TIMER_BASE_H_
+
+void MainTimerBaseTimeoutInc(void);
+void MainTimerBaseTimeoutClr(void);
+bool MainTimerBaseTimeoutCheck(uint16_t timeOff);
+
+#endif /* SRC_TIMER_BASE_H_ */
diff --git a/Projects/epwm_test/targetConfigs/TMS320F28388D.ccxml b/Projects/epwm_test/targetConfigs/TMS320F28388D.ccxml
new file mode 100644
index 0000000..e25cefb
--- /dev/null
+++ b/Projects/epwm_test/targetConfigs/TMS320F28388D.ccxml
@@ -0,0 +1,308 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Projects/epwm_test/Безымянный.png b/Projects/epwm_test/Безымянный.png
new file mode 100644
index 0000000..4da4846
Binary files /dev/null and b/Projects/epwm_test/Безымянный.png differ