seklyuts/MotorControlModuleSDFM_TMS320F28388D
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кое где добавлены EALLOW

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авторассчёт скорости uart
перед клоками:
    EALLOW;
    ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
    EDIS;
ибо сбрасывается при ресете хардварном  в 0
This commit is contained in:
seklyuts 2024-04-16 16:04:46 +03:00
parent 240ee72651
commit 224107e96d
14 changed files with 1118 additions and 37 deletions
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Projects/epwm_test/Start_rfm.pmp
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Projects/epwm_test/epwm_test.c
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@ -17,18 +17,18 @@
#include "f28x_project.h"
#include "init_perif.h"
#include "frmmstr_run.h"
#include "ExtEEPROM.h"
#include "adc_init.h"
#include "biss.h"
void main(void)
{
InitPerif();
for(;;)
{
// asm (" NOP");
frmmstr_run();
AdcRun();
// AdcRun();
BissClkgenRun();
}
}

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Projects/epwm_test/src/CLB/board.c Normal file
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/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "f28x_project.h"
#include "board.h"
#include "clb.h"
#include "xbar.h"
#include "xbar1.h"
//*****************************************************************************
//
// Board Configurations
// Initializes the rest of the modules.
// Call this function in your application if you wish to do all module
// initialization.
// If you wish to not use some of the initializations, instead of the
// Board_init use the individual Module_inits
//
//*****************************************************************************
void Board_init()
{
EALLOW;
//PinMux_init();
CLB_init();
CLB_OUTPUTXBAR_init();
EDIS;
}
//*****************************************************************************
//
// PINMUX Configurations
//
//*****************************************************************************
void PinMux_init()
{
//
// PinMux for modules assigned to CPU1
//
//
// CLB_OUTPUTXBAR6 -> CLB_OUTPUTXBAR_CLKGEN_CLK_M Pinmux
//
// GPIO_setPinConfig(CLB_OUTPUTXBAR_CLKGEN_CLK_M_CLBOUTPUTXBAR_PIN_CONFIG);
//
// CLB_OUTPUTXBAR7 -> CLB_OUTPUTXBAR_CLKGEN_CLK_S Pinmux
//
// GPIO_setPinConfig(CLB_OUTPUTXBAR_CLKGEN_CLK_S_CLBOUTPUTXBAR_PIN_CONFIG);
}
//*****************************************************************************
//
// CLB Configurations
//
//*****************************************************************************
void CLB_init(){
CLB_TILE_CLKGEN_M_init();
CLB_TILE_CLKGEN_S_init();
}
void CLB_TILE_CLKGEN_M_init(){
CLB_setOutputMask(CLB_TILE_CLKGEN_M_BASE,
(0UL << 0UL) |
(1UL << 17UL), true);
CLB_enableOutputMaskUpdates(CLB_TILE_CLKGEN_M_BASE);
//
// CLB_TILE_CLKGEN_M SPI Buffer Configuration
//
CLB_disableSPIBufferAccess(CLB_TILE_CLKGEN_M_BASE);
CLB_configSPIBufferLoadSignal(CLB_TILE_CLKGEN_M_BASE, 0);
CLB_configSPIBufferShift(CLB_TILE_CLKGEN_M_BASE, 0);
//
// CLB_TILE_CLKGEN_M CLB_IN0 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
CLB_configLocalInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configGlobalInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM1A);
CLB_configGPInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN0, CLB_GP_IN_MUX_GP_REG);
CLB_selectInputFilter(CLB_TILE_CLKGEN_M_BASE, CLB_IN0, CLB_FILTER_NONE);
CLB_disableInputPipelineMode(CLB_TILE_CLKGEN_M_BASE, CLB_IN0);
//
// CLB_TILE_CLKGEN_M CLB_IN1 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
CLB_configLocalInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configGlobalInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_EPWM1A);
CLB_configGPInputMux(CLB_TILE_CLKGEN_M_BASE, CLB_IN1, CLB_GP_IN_MUX_GP_REG);
CLB_selectInputFilter(CLB_TILE_CLKGEN_M_BASE, CLB_IN1, CLB_FILTER_NONE);
CLB_disableInputPipelineMode(CLB_TILE_CLKGEN_M_BASE, CLB_IN1);
CLB_setGPREG(CLB_TILE_CLKGEN_M_BASE,0);
initCLB_CLKGEN_M(CLB_TILE_CLKGEN_M_BASE);
CLB_enableCLB(CLB_TILE_CLKGEN_M_BASE);
}
void CLB_TILE_CLKGEN_S_init(){
CLB_setOutputMask(CLB_TILE_CLKGEN_S_BASE,
(0UL << 0UL), true);
CLB_enableOutputMaskUpdates(CLB_TILE_CLKGEN_S_BASE);
//
// CLB_TILE_CLKGEN_S SPI Buffer Configuration
//
CLB_disableSPIBufferAccess(CLB_TILE_CLKGEN_S_BASE);
CLB_configSPIBufferLoadSignal(CLB_TILE_CLKGEN_S_BASE, 0);
CLB_configSPIBufferShift(CLB_TILE_CLKGEN_S_BASE, 0);
//
// CLB_TILE_CLKGEN_S CLB_IN0 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
CLB_configLocalInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configGlobalInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM1A);
CLB_configGPInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN0, CLB_GP_IN_MUX_GP_REG);
CLB_selectInputFilter(CLB_TILE_CLKGEN_S_BASE, CLB_IN0, CLB_FILTER_NONE);
CLB_disableInputPipelineMode(CLB_TILE_CLKGEN_S_BASE, CLB_IN0);
//
// CLB_TILE_CLKGEN_S CLB_IN1 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
CLB_configLocalInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configGlobalInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_CLB1_OUT17);
CLB_configGPInputMux(CLB_TILE_CLKGEN_S_BASE, CLB_IN1, CLB_GP_IN_MUX_EXTERNAL);
CLB_selectInputFilter(CLB_TILE_CLKGEN_S_BASE, CLB_IN1, CLB_FILTER_NONE);
CLB_enableInputPipelineMode(CLB_TILE_CLKGEN_S_BASE, CLB_IN1);
CLB_setGPREG(CLB_TILE_CLKGEN_S_BASE,0);
initCLB_CLKGEN_S(CLB_TILE_CLKGEN_S_BASE);
CLB_enableCLB(CLB_TILE_CLKGEN_S_BASE);
}
//*****************************************************************************
//
// CLBOUTPUTXBAR Configurations
//
//*****************************************************************************
void CLB_OUTPUTXBAR_init(){
CLB_OUTPUTXBAR_CLKGEN_CLK_M_init();
CLB_OUTPUTXBAR_CLKGEN_CLK_S_init();
}
void CLB_OUTPUTXBAR_CLKGEN_CLK_M_init(){
XBAR_setOutputLatchMode(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_M, false);
XBAR_invertOutputSignal(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_M, false);
//
//Mux configuration
//
XBAR_setOutputMuxConfig(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_M, XBAR_OUT_MUX00_CLB1_OUT0);
XBAR_enableOutputMux(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_M, XBAR_MUX00);
}
void CLB_OUTPUTXBAR_CLKGEN_CLK_S_init(){
XBAR_setOutputLatchMode(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_S, false);
XBAR_invertOutputSignal(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_S, false);
//
//Mux configuration
//
XBAR_setOutputMuxConfig(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_S, XBAR_OUT_MUX08_CLB2_OUT0);
XBAR_enableOutputMux(CLBOUTPUTXBAR_BASE, CLB_OUTPUTXBAR_CLKGEN_CLK_S, XBAR_MUX08);
}

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Projects/epwm_test/src/CLB/board.h Normal file
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/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef BOARD_H
#define BOARD_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//
// Included Files
//
#include "f28x_project.h"
#include "clb.h"
//*****************************************************************************
//
// PinMux Configurations
//
//*****************************************************************************
//
// CLB_OUTPUTXBAR6 -> CLB_OUTPUTXBAR_CLKGEN_CLK_M Pinmux
//
//
// CLB_OUTPUTXBAR6 - GPIO Settings
//
#define GPIO_PIN_CLB_OUTPUTXBAR6 96
#define CLB_OUTPUTXBAR_CLKGEN_CLK_M_CLBOUTPUTXBAR_GPIO 96
#define CLB_OUTPUTXBAR_CLKGEN_CLK_M_CLBOUTPUTXBAR_PIN_CONFIG GPIO_96_CLB_OUTPUTXBAR6
//
// CLB_OUTPUTXBAR7 -> CLB_OUTPUTXBAR_CLKGEN_CLK_S Pinmux
//
//
// CLB_OUTPUTXBAR7 - GPIO Settings
//
#define GPIO_PIN_CLB_OUTPUTXBAR7 97
#define CLB_OUTPUTXBAR_CLKGEN_CLK_S_CLBOUTPUTXBAR_GPIO 97
#define CLB_OUTPUTXBAR_CLKGEN_CLK_S_CLBOUTPUTXBAR_PIN_CONFIG GPIO_97_CLB_OUTPUTXBAR7
//*****************************************************************************
//
// CLB Configurations
//
//*****************************************************************************
#define CLB_TILE_CLKGEN_M_BASE CLB1_BASE
void CLB_TILE_CLKGEN_M_init();
#define CLB_TILE_CLKGEN_S_BASE CLB2_BASE
void CLB_TILE_CLKGEN_S_init();
//
// Tile Configurations for all CLBs are in this file
//
#include "clb_config.h"
//*****************************************************************************
//
// CLBOUTPUTXBAR Configurations
//
//*****************************************************************************
void CLB_OUTPUTXBAR_CLKGEN_CLK_M_init();
#define CLB_OUTPUTXBAR_CLKGEN_CLK_M XBAR_OUTPUT6
#define CLB_OUTPUTXBAR_CLKGEN_CLK_M_ENABLED_MUXES (XBAR_MUX00)
void CLB_OUTPUTXBAR_CLKGEN_CLK_S_init();
#define CLB_OUTPUTXBAR_CLKGEN_CLK_S XBAR_OUTPUT7
#define CLB_OUTPUTXBAR_CLKGEN_CLK_S_ENABLED_MUXES (XBAR_MUX08)
//*****************************************************************************
//
// Board Configurations
//
//*****************************************************************************
void Board_init();
void CLB_init();
void CLB_OUTPUTXBAR_init();
void PinMux_init();
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // end of BOARD_H definition

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Projects/epwm_test/src/CLB/clb_config.c Normal file
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/*
* ======== clb.c ========
* DO NOT EDIT - This file is generated by the SysConfig tool.
*/
#include "f28x_project.h"
//#include "driverlib.h"
//#include "device.h"
#include "clb_config.h"
#include "clb.h"
const uint32_t CLB_CLKGEN_M_HLC_initFIFOData[4] = {CLB_CLKGEN_M_HLC_FIFO0_INIT, CLB_CLKGEN_M_HLC_FIFO1_INIT, CLB_CLKGEN_M_HLC_FIFO2_INIT, CLB_CLKGEN_M_HLC_FIFO3_INIT};
uint16_t CLB_CLKGEN_MHLCInstr[CLB_NUM_HLC_INSTR + 1] =
{
CLB_CLKGEN_M_HLCINSTR_0,
CLB_CLKGEN_M_HLCINSTR_1,
CLB_CLKGEN_M_HLCINSTR_2,
CLB_CLKGEN_M_HLCINSTR_3,
CLB_CLKGEN_M_HLCINSTR_4,
CLB_CLKGEN_M_HLCINSTR_5,
CLB_CLKGEN_M_HLCINSTR_6,
CLB_CLKGEN_M_HLCINSTR_7,
CLB_CLKGEN_M_HLCINSTR_8,
CLB_CLKGEN_M_HLCINSTR_9,
CLB_CLKGEN_M_HLCINSTR_10,
CLB_CLKGEN_M_HLCINSTR_11,
CLB_CLKGEN_M_HLCINSTR_12,
CLB_CLKGEN_M_HLCINSTR_13,
CLB_CLKGEN_M_HLCINSTR_14,
CLB_CLKGEN_M_HLCINSTR_15,
CLB_CLKGEN_M_HLCINSTR_16,
CLB_CLKGEN_M_HLCINSTR_17,
CLB_CLKGEN_M_HLCINSTR_18,
CLB_CLKGEN_M_HLCINSTR_19,
CLB_CLKGEN_M_HLCINSTR_20,
CLB_CLKGEN_M_HLCINSTR_21,
CLB_CLKGEN_M_HLCINSTR_22,
CLB_CLKGEN_M_HLCINSTR_23,
CLB_CLKGEN_M_HLCINSTR_24,
CLB_CLKGEN_M_HLCINSTR_25,
CLB_CLKGEN_M_HLCINSTR_26,
CLB_CLKGEN_M_HLCINSTR_27,
CLB_CLKGEN_M_HLCINSTR_28,
CLB_CLKGEN_M_HLCINSTR_29,
CLB_CLKGEN_M_HLCINSTR_30,
CLB_CLKGEN_M_HLCINSTR_31
};
const uint32_t CLB_CLKGEN_S_HLC_initFIFOData[4] = {CLB_CLKGEN_S_HLC_FIFO0_INIT, CLB_CLKGEN_S_HLC_FIFO1_INIT, CLB_CLKGEN_S_HLC_FIFO2_INIT, CLB_CLKGEN_S_HLC_FIFO3_INIT};
uint16_t CLB_CLKGEN_SHLCInstr[CLB_NUM_HLC_INSTR + 1] =
{
CLB_CLKGEN_S_HLCINSTR_0,
CLB_CLKGEN_S_HLCINSTR_1,
CLB_CLKGEN_S_HLCINSTR_2,
CLB_CLKGEN_S_HLCINSTR_3,
CLB_CLKGEN_S_HLCINSTR_4,
CLB_CLKGEN_S_HLCINSTR_5,
CLB_CLKGEN_S_HLCINSTR_6,
CLB_CLKGEN_S_HLCINSTR_7,
CLB_CLKGEN_S_HLCINSTR_8,
CLB_CLKGEN_S_HLCINSTR_9,
CLB_CLKGEN_S_HLCINSTR_10,
CLB_CLKGEN_S_HLCINSTR_11,
CLB_CLKGEN_S_HLCINSTR_12,
CLB_CLKGEN_S_HLCINSTR_13,
CLB_CLKGEN_S_HLCINSTR_14,
CLB_CLKGEN_S_HLCINSTR_15,
CLB_CLKGEN_S_HLCINSTR_16,
CLB_CLKGEN_S_HLCINSTR_17,
CLB_CLKGEN_S_HLCINSTR_18,
CLB_CLKGEN_S_HLCINSTR_19,
CLB_CLKGEN_S_HLCINSTR_20,
CLB_CLKGEN_S_HLCINSTR_21,
CLB_CLKGEN_S_HLCINSTR_22,
CLB_CLKGEN_S_HLCINSTR_23,
CLB_CLKGEN_S_HLCINSTR_24,
CLB_CLKGEN_S_HLCINSTR_25,
CLB_CLKGEN_S_HLCINSTR_26,
CLB_CLKGEN_S_HLCINSTR_27,
CLB_CLKGEN_S_HLCINSTR_28,
CLB_CLKGEN_S_HLCINSTR_29,
CLB_CLKGEN_S_HLCINSTR_30,
CLB_CLKGEN_S_HLCINSTR_31
};
void initCLB_CLKGEN_M(uint32_t base)
{
uint16_t i;
//
// Pipeline Mode
//
CLB_disablePipelineMode(base);
//
// Output LUT
//
//
// Equation for Output Look-Up Table Block 0 for CLB_CLKGEN_M: i0
//
// User Description for Output Look-Up Table 0 for CLB_CLKGEN_M
/*
CLK_M
*/
//
CLB_configOutputLUT(base, CLB_OUT0, CLB_CLKGEN_M_CFG_OUTLUT_0);
//
// Equation for Output Look-Up Table Block 1 for CLB_CLKGEN_M: i0 & i1
//
//
// User Description for Output Look-Up Table 1 for CLB_CLKGEN_M
/*
RUN_S
*/
//
CLB_configOutputLUT(base, CLB_OUT1, CLB_CLKGEN_M_CFG_OUTLUT_1);
CLB_configOutputLUT(base, CLB_OUT2, CLB_CLKGEN_M_CFG_OUTLUT_2);
CLB_configOutputLUT(base, CLB_OUT3, CLB_CLKGEN_M_CFG_OUTLUT_3);
CLB_configOutputLUT(base, CLB_OUT4, CLB_CLKGEN_M_CFG_OUTLUT_4);
CLB_configOutputLUT(base, CLB_OUT5, CLB_CLKGEN_M_CFG_OUTLUT_5);
CLB_configOutputLUT(base, CLB_OUT6, CLB_CLKGEN_M_CFG_OUTLUT_6);
CLB_configOutputLUT(base, CLB_OUT7, CLB_CLKGEN_M_CFG_OUTLUT_7);
//
// AOC
//
CLB_configAOC(base, CLB_AOC0, CLB_CLKGEN_M_OUTPUT_COND_CTR_0);
CLB_configAOC(base, CLB_AOC1, CLB_CLKGEN_M_OUTPUT_COND_CTR_1);
CLB_configAOC(base, CLB_AOC2, CLB_CLKGEN_M_OUTPUT_COND_CTR_2);
CLB_configAOC(base, CLB_AOC3, CLB_CLKGEN_M_OUTPUT_COND_CTR_3);
CLB_configAOC(base, CLB_AOC4, CLB_CLKGEN_M_OUTPUT_COND_CTR_4);
CLB_configAOC(base, CLB_AOC5, CLB_CLKGEN_M_OUTPUT_COND_CTR_5);
CLB_configAOC(base, CLB_AOC6, CLB_CLKGEN_M_OUTPUT_COND_CTR_6);
CLB_configAOC(base, CLB_AOC7, CLB_CLKGEN_M_OUTPUT_COND_CTR_7);
//
// LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
// CLB_selectLUT4Inputs and CLB_configLUT4Function
//
//
// Equation for Look-Up Table Block 0 for CLB_CLKGEN_M: i0 & !i1
// User Description for Look-Up Table Block 0 for CLB_CLKGEN_M
/*
LOAD
*/
//
// Equation for Look-Up Table Block 1 for CLB_CLKGEN_M: i0 & i1
// User Description for Look-Up Table Block 1 for CLB_CLKGEN_M
/*
DONE
*/
//
// Equation for Look-Up Table Block 2 for CLB_CLKGEN_M: i0 & i1
// User Description for Look-Up Table Block 2 for CLB_CLKGEN_M
/*
CLK_PULSE
*/
//
// LUT Configuration
//
CLB_selectLUT4Inputs(base, CLB_CLKGEN_M_CFG_LUT4_IN0, CLB_CLKGEN_M_CFG_LUT4_IN1, CLB_CLKGEN_M_CFG_LUT4_IN2, CLB_CLKGEN_M_CFG_LUT4_IN3);
CLB_configLUT4Function(base, CLB_CLKGEN_M_CFG_LUT4_FN10, CLB_CLKGEN_M_CFG_LUT4_FN2);
//
// FSM 0 - 2 are configured in <file>
//
// State 0 output equation for Finite State Machine 0 for CLB_CLKGEN_M: (e0 & !e1 & !s1 & !s0) | (!e0 & !e1 & !s1 & s0) | (e0 & !e1 & !s1 & s0)
// State 1 output equation for Finite State Machine 0 for CLB_CLKGEN_M: (e0 & e1 & !s1 & s0) | (e0 & !e1 & s1 & !s0) | (e0 & e1 & s1 & !s0)
//
// User Description for Finite State Machine 0 for CLB_CLKGEN_M
/*
ENABLE_PHASE_COUNTER
*/
// State 0 output equation for Finite State Machine 1 for CLB_CLKGEN_M: (e0 & !e1 & !s1 & !s0) | (!e0 & !e1 & !s1 & s0) | (e0 & !e1 & !s1 & s0)
// State 1 output equation for Finite State Machine 1 for CLB_CLKGEN_M: (e0 & e1 & !s1 & s0) | (e0 & !e1 & s1 & !s0) | (e0 & e1 & s1 & !s0)
//
// User Description for Finite State Machine 1 for CLB_CLKGEN_M
/*
ENABLE_CLK_PULSE_COUNTER
*/
// State 0 output equation for Finite State Machine 2 for CLB_CLKGEN_M: s0 ^ e0
// User Description for Finite State Machine 2 for CLB_CLKGEN_M
/*
CLK_OUTPUT
*/
//
// FSM
//
CLB_selectFSMInputs(base, CLB_CLKGEN_M_CFG_FSM_EXT_IN0, CLB_CLKGEN_M_CFG_FSM_EXT_IN1, CLB_CLKGEN_M_CFG_FSM_EXTRA_IN0, CLB_CLKGEN_M_CFG_FSM_EXTRA_IN1);
CLB_configFSMNextState(base, CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_0, CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_1, CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_2);
CLB_configFSMLUTFunction(base, CLB_CLKGEN_M_CFG_FSM_LUT_FN10, CLB_CLKGEN_M_CFG_FSM_LUT_FN2);
//
// Counter 0 - 2 are configured in <file>
//
// User Description for Counter 0 for CLB_CLKGEN_M
/*
CLK_PULSE_COUNTER
*/
// User Description for Counter 1 for CLB_CLKGEN_M
/*
CLK_BURST_COUNTER
*/
// User Description for Counter 2 for CLB_CLKGEN_M
/*
PHASE_COUNTER
*/
//
// Counters
//
CLB_selectCounterInputs(base, CLB_CLKGEN_M_CFG_COUNTER_RESET, CLB_CLKGEN_M_CFG_COUNTER_EVENT, CLB_CLKGEN_M_CFG_COUNTER_MODE_0, CLB_CLKGEN_M_CFG_COUNTER_MODE_1);
CLB_configMiscCtrlModes(base, CLB_CLKGEN_M_CFG_MISC_CONTROL);
CLB_configCounterLoadMatch(base, CLB_CTR0, CLB_CLKGEN_M_COUNTER_0_LOAD_VAL, CLB_CLKGEN_M_COUNTER_0_MATCH1_VAL, CLB_CLKGEN_M_COUNTER_0_MATCH2_VAL);
CLB_configCounterLoadMatch(base, CLB_CTR1, CLB_CLKGEN_M_COUNTER_1_LOAD_VAL, CLB_CLKGEN_M_COUNTER_1_MATCH1_VAL, CLB_CLKGEN_M_COUNTER_1_MATCH2_VAL);
CLB_configCounterLoadMatch(base, CLB_CTR2, CLB_CLKGEN_M_COUNTER_2_LOAD_VAL, CLB_CLKGEN_M_COUNTER_2_MATCH1_VAL, CLB_CLKGEN_M_COUNTER_2_MATCH2_VAL);
CLB_configCounterTapSelects(base, CLB_CLKGEN_M_CFG_TAP_SEL);
//
// HLC is configured in <file>
//
// User Description for the High Level Controller for CLB_CLKGEN_M
/*
*/
//
// HLC
//
CLB_configHLCEventSelect(base, CLB_CLKGEN_M_HLC_EVENT_SEL);
CLB_setHLCRegisters(base, CLB_CLKGEN_M_HLC_R0_INIT, CLB_CLKGEN_M_HLC_R1_INIT, CLB_CLKGEN_M_HLC_R2_INIT, CLB_CLKGEN_M_HLC_R3_INIT);
CLB_writeFIFOs(base, CLB_CLKGEN_M_HLC_initFIFOData);
for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
{
CLB_programHLCInstruction(base, i, CLB_CLKGEN_MHLCInstr[i]);
}
}
void initCLB_CLKGEN_S(uint32_t base)
{
uint16_t i;
//
// Pipeline Mode
//
CLB_disablePipelineMode(base);
//
// Output LUT
//
//
// Equation for Output Look-Up Table Block 0 for CLB_CLKGEN_S: i0
//
// User Description for Output Look-Up Table 0 for CLB_CLKGEN_S
/*
CLK_S
*/
//
CLB_configOutputLUT(base, CLB_OUT0, CLB_CLKGEN_S_CFG_OUTLUT_0);
CLB_configOutputLUT(base, CLB_OUT1, CLB_CLKGEN_S_CFG_OUTLUT_1);
CLB_configOutputLUT(base, CLB_OUT2, CLB_CLKGEN_S_CFG_OUTLUT_2);
CLB_configOutputLUT(base, CLB_OUT3, CLB_CLKGEN_S_CFG_OUTLUT_3);
CLB_configOutputLUT(base, CLB_OUT4, CLB_CLKGEN_S_CFG_OUTLUT_4);
CLB_configOutputLUT(base, CLB_OUT5, CLB_CLKGEN_S_CFG_OUTLUT_5);
CLB_configOutputLUT(base, CLB_OUT6, CLB_CLKGEN_S_CFG_OUTLUT_6);
CLB_configOutputLUT(base, CLB_OUT7, CLB_CLKGEN_S_CFG_OUTLUT_7);
//
// AOC
//
CLB_configAOC(base, CLB_AOC0, CLB_CLKGEN_S_OUTPUT_COND_CTR_0);
CLB_configAOC(base, CLB_AOC1, CLB_CLKGEN_S_OUTPUT_COND_CTR_1);
CLB_configAOC(base, CLB_AOC2, CLB_CLKGEN_S_OUTPUT_COND_CTR_2);
CLB_configAOC(base, CLB_AOC3, CLB_CLKGEN_S_OUTPUT_COND_CTR_3);
CLB_configAOC(base, CLB_AOC4, CLB_CLKGEN_S_OUTPUT_COND_CTR_4);
CLB_configAOC(base, CLB_AOC5, CLB_CLKGEN_S_OUTPUT_COND_CTR_5);
CLB_configAOC(base, CLB_AOC6, CLB_CLKGEN_S_OUTPUT_COND_CTR_6);
CLB_configAOC(base, CLB_AOC7, CLB_CLKGEN_S_OUTPUT_COND_CTR_7);
//
// LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
// CLB_selectLUT4Inputs and CLB_configLUT4Function
//
//
// Equation for Look-Up Table Block 0 for CLB_CLKGEN_S: i0 & !i1
// User Description for Look-Up Table Block 0 for CLB_CLKGEN_S
/*
LOAD
*/
//
// Equation for Look-Up Table Block 1 for CLB_CLKGEN_S: i0 & i1
// User Description for Look-Up Table Block 1 for CLB_CLKGEN_S
/*
DONE
*/
//
// Equation for Look-Up Table Block 2 for CLB_CLKGEN_S: i0 & i1
// User Description for Look-Up Table Block 2 for CLB_CLKGEN_S
/*
CLK_PULSE
*/
//
// LUT Configuration
//
CLB_selectLUT4Inputs(base, CLB_CLKGEN_S_CFG_LUT4_IN0, CLB_CLKGEN_S_CFG_LUT4_IN1, CLB_CLKGEN_S_CFG_LUT4_IN2, CLB_CLKGEN_S_CFG_LUT4_IN3);
CLB_configLUT4Function(base, CLB_CLKGEN_S_CFG_LUT4_FN10, CLB_CLKGEN_S_CFG_LUT4_FN2);
//
// FSM 0 - 2 are configured in <file>
//
// State 0 output equation for Finite State Machine 1 for CLB_CLKGEN_S: (e0 & !e1 & !s1 & !s0) | (!e0 & !e1 & !s1 & s0) | (e0 & !e1 & !s1 & s0)
// State 1 output equation for Finite State Machine 1 for CLB_CLKGEN_S: (e0 & e1 & !s1 & s0) | (e0 & !e1 & s1 & !s0) | (e0 & e1 & s1 & !s0)
//
// User Description for Finite State Machine 1 for CLB_CLKGEN_S
/*
ENABLE_CLK_PULSE_COUNTER
*/
// State 0 output equation for Finite State Machine 2 for CLB_CLKGEN_S: s0 ^ e0
// User Description for Finite State Machine 2 for CLB_CLKGEN_S
/*
CLK_OUTPUT
*/
//
// FSM
//
CLB_selectFSMInputs(base, CLB_CLKGEN_S_CFG_FSM_EXT_IN0, CLB_CLKGEN_S_CFG_FSM_EXT_IN1, CLB_CLKGEN_S_CFG_FSM_EXTRA_IN0, CLB_CLKGEN_S_CFG_FSM_EXTRA_IN1);
CLB_configFSMNextState(base, CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_0, CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_1, CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_2);
CLB_configFSMLUTFunction(base, CLB_CLKGEN_S_CFG_FSM_LUT_FN10, CLB_CLKGEN_S_CFG_FSM_LUT_FN2);
//
// Counter 0 - 2 are configured in <file>
//
// User Description for Counter 0 for CLB_CLKGEN_S
/*
CLK_PULSE_COUNTER
*/
// User Description for Counter 1 for CLB_CLKGEN_S
/*
CLK_BURST_COUNTER
*/
//
// Counters
//
CLB_selectCounterInputs(base, CLB_CLKGEN_S_CFG_COUNTER_RESET, CLB_CLKGEN_S_CFG_COUNTER_EVENT, CLB_CLKGEN_S_CFG_COUNTER_MODE_0, CLB_CLKGEN_S_CFG_COUNTER_MODE_1);
CLB_configMiscCtrlModes(base, CLB_CLKGEN_S_CFG_MISC_CONTROL);
CLB_configCounterLoadMatch(base, CLB_CTR0, CLB_CLKGEN_S_COUNTER_0_LOAD_VAL, CLB_CLKGEN_S_COUNTER_0_MATCH1_VAL, CLB_CLKGEN_S_COUNTER_0_MATCH2_VAL);
CLB_configCounterLoadMatch(base, CLB_CTR1, CLB_CLKGEN_S_COUNTER_1_LOAD_VAL, CLB_CLKGEN_S_COUNTER_1_MATCH1_VAL, CLB_CLKGEN_S_COUNTER_1_MATCH2_VAL);
CLB_configCounterLoadMatch(base, CLB_CTR2, CLB_CLKGEN_S_COUNTER_2_LOAD_VAL, CLB_CLKGEN_S_COUNTER_2_MATCH1_VAL, CLB_CLKGEN_S_COUNTER_2_MATCH2_VAL);
CLB_configCounterTapSelects(base, CLB_CLKGEN_S_CFG_TAP_SEL);
//
// HLC is configured in <file>
//
// User Description for the High Level Controller for CLB_CLKGEN_S
/*
*/
//
// HLC
//
CLB_configHLCEventSelect(base, CLB_CLKGEN_S_HLC_EVENT_SEL);
CLB_setHLCRegisters(base, CLB_CLKGEN_S_HLC_R0_INIT, CLB_CLKGEN_S_HLC_R1_INIT, CLB_CLKGEN_S_HLC_R2_INIT, CLB_CLKGEN_S_HLC_R3_INIT);
CLB_writeFIFOs(base, CLB_CLKGEN_S_HLC_initFIFOData);
for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
{
CLB_programHLCInstruction(base, i, CLB_CLKGEN_SHLCInstr[i]);
}
}

252
Projects/epwm_test/src/CLB/clb_config.h Normal file
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/*
* ======== clb.h ========
* DO NOT EDIT - This file is generated by the SysConfig tool.
*/
#ifndef ti_clb_h
#define ti_clb_h
#include <stdint.h>
#ifdef __cplusplus
extern "C" { // support C++ sources
#endif
// HLC Instruction Register Field definitions
#define HLC_OPCODE_R0 0x0
#define HLC_OPCODE_R1 0x1
#define HLC_OPCODE_R2 0x2
#define HLC_OPCODE_R3 0x3
#define HLC_OPCODE_C0 0x4
#define HLC_OPCODE_C1 0x5
#define HLC_OPCODE_C2 0x6
#define HLC_OPCODE_MOV 0x00
#define HLC_OPCODE_MOV_T1 0x01
#define HLC_OPCODE_MOV_T2 0x02
#define HLC_OPCODE_PUSH 0x03
#define HLC_OPCODE_PULL 0x04
#define HLC_OPCODE_ADD 0x05
#define HLC_OPCODE_SUB 0x06
#define HLC_OPCODE_INTR 0x07
//---------------------------------------------------------------------------
// CLB_CLKGEN_M
//---------------------------------------------------------------------------
#define CLB_CLKGEN_M_PIPELINE_MODE 0
#define CLB_CLKGEN_M_CFG_OUTLUT_0 0x550014
#define CLB_CLKGEN_M_CFG_OUTLUT_1 0x440093
#define CLB_CLKGEN_M_CFG_OUTLUT_2 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_3 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_4 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_5 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_6 0x0
#define CLB_CLKGEN_M_CFG_OUTLUT_7 0x0
#define CLB_CLKGEN_M_CFG_LUT4_IN0 0xc78
#define CLB_CLKGEN_M_CFG_LUT4_IN1 0x316c
#define CLB_CLKGEN_M_CFG_LUT4_IN2 0x0
#define CLB_CLKGEN_M_CFG_LUT4_IN3 0x0
#define CLB_CLKGEN_M_CFG_LUT4_FN10 ((0x88880000) | 0x2222)
#define CLB_CLKGEN_M_CFG_LUT4_FN2 0x8888
#define CLB_CLKGEN_M_CFG_FSM_EXT_IN0 0x5f39
#define CLB_CLKGEN_M_CFG_FSM_EXT_IN1 0x1f3
#define CLB_CLKGEN_M_CFG_FSM_EXTRA_IN0 0x0
#define CLB_CLKGEN_M_CFG_FSM_EXTRA_IN1 0x0
#define CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_0 ((0x60400000) | 0x32)
#define CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_1 ((0x60400000) | 0x32)
#define CLB_CLKGEN_M_CFG_FSM_NEXT_STATE_2 ((0x00000) | 0x5a5a)
#define CLB_CLKGEN_M_CFG_FSM_LUT_FN10 ((0x00000) | 0x0)
#define CLB_CLKGEN_M_CFG_FSM_LUT_FN2 0x0
#define CLB_CLKGEN_M_FSM_MISC_CONTROL 0x0
#define CLB_CLKGEN_M_CFG_COUNTER_RESET 0x4de3
#define CLB_CLKGEN_M_CFG_COUNTER_EVENT 0x60
#define CLB_CLKGEN_M_CFG_COUNTER_MODE_0 0x100c
#define CLB_CLKGEN_M_CFG_COUNTER_MODE_1 0x2008
#define CLB_CLKGEN_M_CFG_TAP_SEL 0x0
#define CLB_CLKGEN_M_CFG_MISC_CONTROL (0x38 | CLB_CLKGEN_M_FSM_MISC_CONTROL)
#define CLB_CLKGEN_M_COUNTER_0_MATCH1_VAL 0
#define CLB_CLKGEN_M_COUNTER_0_MATCH2_VAL 0
#define CLB_CLKGEN_M_COUNTER_0_LOAD_VAL 0
#define CLB_CLKGEN_M_COUNTER_1_MATCH1_VAL 0
#define CLB_CLKGEN_M_COUNTER_1_MATCH2_VAL 0
#define CLB_CLKGEN_M_COUNTER_1_LOAD_VAL 1
#define CLB_CLKGEN_M_COUNTER_2_MATCH1_VAL 0
#define CLB_CLKGEN_M_COUNTER_2_MATCH2_VAL 0
#define CLB_CLKGEN_M_COUNTER_2_LOAD_VAL 0
#define CLB_CLKGEN_M_SPI_EN 0
#define CLB_CLKGEN_M_HLC_EVENT_SEL 0x1e7
#define CLB_CLKGEN_M_HLC_R0_INIT 0
#define CLB_CLKGEN_M_HLC_R1_INIT 0
#define CLB_CLKGEN_M_HLC_R2_INIT 0
#define CLB_CLKGEN_M_HLC_R3_INIT 0
#define CLB_CLKGEN_M_HLC_FIFO0_INIT 0
#define CLB_CLKGEN_M_HLC_FIFO1_INIT 0
#define CLB_CLKGEN_M_HLC_FIFO2_INIT 0
#define CLB_CLKGEN_M_HLC_FIFO3_INIT 0
#define CLB_CLKGEN_M_HLCINSTR_0 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_M_HLCINSTR_1 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C0)
#define CLB_CLKGEN_M_HLCINSTR_2 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_M_HLCINSTR_3 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C1)
#define CLB_CLKGEN_M_HLCINSTR_4 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_M_HLCINSTR_5 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C2)
#define CLB_CLKGEN_M_HLCINSTR_6 (1 << 11 | HLC_OPCODE_PUSH << 6 | HLC_OPCODE_R0<<3)
#define CLB_CLKGEN_M_HLCINSTR_7 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_8 (1 << 11 | HLC_OPCODE_PUSH << 6 | HLC_OPCODE_R0<<3)
#define CLB_CLKGEN_M_HLCINSTR_9 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_10 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_11 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_12 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_13 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_14 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_15 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_16 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_17 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_18 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_19 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_20 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_21 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_22 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_23 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_24 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_25 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_26 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_27 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_28 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_29 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_30 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_HLCINSTR_31 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_0 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_1 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_2 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_3 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_4 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_5 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_6 0x0
#define CLB_CLKGEN_M_OUTPUT_COND_CTR_7 0x0
//---------------------------------------------------------------------------
// CLB_CLKGEN_S
//---------------------------------------------------------------------------
#define CLB_CLKGEN_S_PIPELINE_MODE 0
#define CLB_CLKGEN_S_CFG_OUTLUT_0 0x550014
#define CLB_CLKGEN_S_CFG_OUTLUT_1 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_2 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_3 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_4 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_5 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_6 0x0
#define CLB_CLKGEN_S_CFG_OUTLUT_7 0x0
#define CLB_CLKGEN_S_CFG_LUT4_IN0 0xc78
#define CLB_CLKGEN_S_CFG_LUT4_IN1 0x316c
#define CLB_CLKGEN_S_CFG_LUT4_IN2 0x0
#define CLB_CLKGEN_S_CFG_LUT4_IN3 0x0
#define CLB_CLKGEN_S_CFG_LUT4_FN10 ((0x88880000) | 0x2222)
#define CLB_CLKGEN_S_CFG_LUT4_FN2 0x8888
#define CLB_CLKGEN_S_CFG_FSM_EXT_IN0 0x5f20
#define CLB_CLKGEN_S_CFG_FSM_EXT_IN1 0x1e0
#define CLB_CLKGEN_S_CFG_FSM_EXTRA_IN0 0x0
#define CLB_CLKGEN_S_CFG_FSM_EXTRA_IN1 0x0
#define CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_0 ((0x00000) | 0x0)
#define CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_1 ((0x60400000) | 0x32)
#define CLB_CLKGEN_S_CFG_FSM_NEXT_STATE_2 ((0x00000) | 0x5a5a)
#define CLB_CLKGEN_S_CFG_FSM_LUT_FN10 ((0x00000) | 0x0)
#define CLB_CLKGEN_S_CFG_FSM_LUT_FN2 0x0
#define CLB_CLKGEN_S_FSM_MISC_CONTROL 0x0
#define CLB_CLKGEN_S_CFG_COUNTER_RESET 0x1e3
#define CLB_CLKGEN_S_CFG_COUNTER_EVENT 0x60
#define CLB_CLKGEN_S_CFG_COUNTER_MODE_0 0xc
#define CLB_CLKGEN_S_CFG_COUNTER_MODE_1 0x8
#define CLB_CLKGEN_S_CFG_TAP_SEL 0x0
#define CLB_CLKGEN_S_CFG_MISC_CONTROL (0x38 | CLB_CLKGEN_S_FSM_MISC_CONTROL)
#define CLB_CLKGEN_S_COUNTER_0_MATCH1_VAL 0
#define CLB_CLKGEN_S_COUNTER_0_MATCH2_VAL 0
#define CLB_CLKGEN_S_COUNTER_0_LOAD_VAL 0
#define CLB_CLKGEN_S_COUNTER_1_MATCH1_VAL 0
#define CLB_CLKGEN_S_COUNTER_1_MATCH2_VAL 0
#define CLB_CLKGEN_S_COUNTER_1_LOAD_VAL 1
#define CLB_CLKGEN_S_COUNTER_2_MATCH1_VAL 0
#define CLB_CLKGEN_S_COUNTER_2_MATCH2_VAL 0
#define CLB_CLKGEN_S_COUNTER_2_LOAD_VAL 0
#define CLB_CLKGEN_S_SPI_EN 0
#define CLB_CLKGEN_S_HLC_EVENT_SEL 0x1e7
#define CLB_CLKGEN_S_HLC_R0_INIT 0
#define CLB_CLKGEN_S_HLC_R1_INIT 0
#define CLB_CLKGEN_S_HLC_R2_INIT 0
#define CLB_CLKGEN_S_HLC_R3_INIT 0
#define CLB_CLKGEN_S_HLC_FIFO0_INIT 0
#define CLB_CLKGEN_S_HLC_FIFO1_INIT 0
#define CLB_CLKGEN_S_HLC_FIFO2_INIT 0
#define CLB_CLKGEN_S_HLC_FIFO3_INIT 0
#define CLB_CLKGEN_S_HLCINSTR_0 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_S_HLCINSTR_1 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C0)
#define CLB_CLKGEN_S_HLCINSTR_2 (0 << 11 | HLC_OPCODE_PULL << 6 | HLC_OPCODE_R1)
#define CLB_CLKGEN_S_HLCINSTR_3 (0 << 11 | HLC_OPCODE_MOV_T1 << 6 | HLC_OPCODE_R1<<3 | HLC_OPCODE_C1)
#define CLB_CLKGEN_S_HLCINSTR_4 (1 << 11 | HLC_OPCODE_PUSH << 6 | HLC_OPCODE_R0<<3)
#define CLB_CLKGEN_S_HLCINSTR_5 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_6 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_7 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_8 (1 << 11 | HLC_OPCODE_PUSH << 6 | HLC_OPCODE_R0<<3)
#define CLB_CLKGEN_S_HLCINSTR_9 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_10 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_11 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_12 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_13 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_14 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_15 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_16 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_17 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_18 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_19 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_20 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_21 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_22 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_23 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_24 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_25 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_26 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_27 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_28 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_29 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_30 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_HLCINSTR_31 (1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_0 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_1 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_2 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_3 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_4 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_5 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_6 0x0
#define CLB_CLKGEN_S_OUTPUT_COND_CTR_7 0x0
void initCLB_CLKGEN_M(uint32_t base);
void initCLB_CLKGEN_S(uint32_t base);
#ifdef __cplusplus
}
#endif
#endif // ti_clb_h

67
Projects/epwm_test/src/Peripherals/CLB_init.c Normal file
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@ -0,0 +1,67 @@
/*
* CLB_init.c
*
* Created on: 19 ôåâð. 2024 ã.
* Author: seklyuts
*/
#include "f28x_project.h"
#define CLB_FIFO_SIZE 4U
void CLB_clearFIFOs1(void)
{
uint16_t i;
for(i = 0U; i < CLB_FIFO_SIZE; i++)
{
Clb1DataExchRegs.CLB_PULL[i] = 0;
}
Clb1LogicCtrlRegs.CLB_BUF_PTR.all = 0;
}
void CLB_writeFIFOs1(const uint32_t pullData[])
{
//
// Clear the FIFO and pointer
//
CLB_clearFIFOs1();
//
// Write data into the FIFO.
//
Clb1DataExchRegs.CLB_PULL[0] = pullData[0U];
Clb1DataExchRegs.CLB_PULL[1] = pullData[1U];
Clb1DataExchRegs.CLB_PULL[2] = pullData[2U];
Clb1DataExchRegs.CLB_PULL[3] = pullData[3U];
}
void CLB_clearFIFOs2(void)
{
uint16_t i;
for(i = 0U; i < CLB_FIFO_SIZE; i++)
{
Clb1DataExchRegs.CLB_PULL[i] = 0;
}
Clb1LogicCtrlRegs.CLB_BUF_PTR.all = 0;
}
void CLB_writeFIFOs2(const uint32_t pullData[])
{
//
// Clear the FIFO and pointer
//
CLB_clearFIFOs2();
//
// Write data into the FIFO.
//
Clb2DataExchRegs.CLB_PULL[0] = pullData[0U];
Clb2DataExchRegs.CLB_PULL[1] = pullData[1U];
Clb2DataExchRegs.CLB_PULL[2] = pullData[2U];
Clb2DataExchRegs.CLB_PULL[3] = pullData[3U];
}

18
Projects/epwm_test/src/Peripherals/CLB_init.h Normal file
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@ -0,0 +1,18 @@
/*
* CLB_init.h
*
* Created on: 19 ôåâð. 2024 ã.
* Author: seklyuts
*/
#ifndef SRC_PERIPHERALS_CLB_INIT_H_
#define SRC_PERIPHERALS_CLB_INIT_H_
void CLB_clearFIFOs1(void);
void CLB_writeFIFOs1(const uint32_t pullData[]);
void CLB_clearFIFOs2(void);
void CLB_writeFIFOs2(const uint32_t pullData[]);
#endif /* SRC_PERIPHERALS_CLB_INIT_H_ */

27
Projects/epwm_test/src/Peripherals/pwm_init.c
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@ -136,22 +136,29 @@ void PWMInitInterruptEn(void)
PieVectTable.EPWM4_INT = &epwm4_isr;
PieVectTable.EPWM8_INT = &epwm8_isr;
PieVectTable.EPWM11_INT = &epwm11_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
EDIS;
// This is needed to disable write to EALLOW protected registers
EPwm1Regs.ETCLR.bit.INT = 1;
EPwm2Regs.ETCLR.bit.INT = 1;
EPwm8Regs.ETCLR.bit.INT = 1;
EPwm11Regs.ETCLR.bit.INT = 1;
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
IER |= M_INT3;
IER |= M_INT3;
//
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150)
//
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
PieCtrlRegs.PIEIER3.bit.INTx8 = 1;
PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
}
void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
@ -183,10 +190,8 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
EALLOW;
EPwmRegs[Num]->TZCTL.bit.TZA = 3;
EPwmRegs[Num]->TZCTL.bit.TZB = 3;
EPwmRegs[Num]->TZFRC.all = 4;
EDIS; //<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TZ-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
EDIS; //
//
// Set actions
//
@ -234,10 +239,6 @@ void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
}
EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL;
// EPwm1_DB_Direction = COUNT_UP;
//
//
if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA;

12
Projects/epwm_test/src/Peripherals/pwm_interrupts.c
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@ -1,7 +1,7 @@
/*
* interrupts.c
*
* Created on: 21 авг. 2023 г.
* Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts
*/
@ -25,7 +25,7 @@ volatile uint16_t PWM_out = 2500;
uint16_t Fault = 0, Fault_fix = 0, Ready = 0, Ready_Fix = 0;
uint16_t counter1s=0;
uint16_t FaultABC = 0, FaultABCFix = 0;
uint16_t PwmFlagStartADC = 0;
uint16_t PwmFlagStartCurrentMeashure = 0;
extern volatile struct EPWM_REGS * EPwmRegs[17];
typedef struct
@ -125,9 +125,9 @@ __interrupt void epwm2_isr(void)
//
EPwm2Regs.ETCLR.bit.INT = 1;
TimerBaseTimeoutInc();
if(PwmFlagStartADC) /// ацп не запустился, ток не был измерен
if(PwmFlagStartCurrentMeashure) /// Не были отработаны измерения тока в сигма-дельта и не было запущено векторное управление
{
PwmFlagStartADC = 0;
PwmFlagStartCurrentMeashure = 0;
FMSTREnableSet();
AdcStartSet();
BissStartSet();
@ -254,7 +254,7 @@ __interrupt void epwm11_isr(void)
if(TestStopSync != 3) sdfm_start_conversion_current();
PwmFlagStartADC = 1;
PwmFlagStartCurrentMeashure = 1;
EPwm11Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
// Gpio4out(0);
@ -263,7 +263,7 @@ __interrupt void epwm11_isr(void)
void pwm_clr_PwmFlagStartADC(void)
{
PwmFlagStartADC = 0;
PwmFlagStartCurrentMeashure = 0;
}
//

13
Projects/epwm_test/src/Peripherals/sdfm.c
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@ -94,6 +94,7 @@ int16_t sdfmAdcErr[8] = {0,0,0,0,0,0,0,0};
int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0};
uint16_t startInitCurrent = 0;
uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM};
uint16_t AllInitDone =0;
uint16_t sdfmIndex = 0;
int16_t Test_I[16];
uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0};
@ -179,8 +180,11 @@ void SdfmInitInterruptEn(void)
PieVectTable.SDFM1_INT = &Sdfm1_ISR;
PieVectTable.SDFM2_INT = &Sdfm2_ISR;
IER |= M_INT5;
Sdfm_clearFlagRegister(SDFM1,0xFFFFFFFF);
Sdfm_clearFlagRegister(SDFM2,0xFFFFFFFF);
PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 interrupt enabled
PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 interrupt enabled
PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
EDIS;
}
@ -359,7 +363,14 @@ void sdfm_check_all_current_measurements_was_done(void)
if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS)
{
sdfmIndex = 0;
vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]);
if(!AllInitDone)
{
if((initDone[SDFM_IA] == 0xFF)&&(initDone[SDFM_IB] == 0xFF)&&(initDone[SDFM_IC] == 0xFF)) AllInitDone = 1;
}
else
{
vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]);
}
}
}

16
Projects/epwm_test/src/frm_uart.c
View File

@ -8,6 +8,10 @@
//#include "f2838x_pinmux.h"
#include "frm_uart.h"
#define LSPCLK_HZ 50000000.0
#define BAUD 19200.0
#define BRR LSPCLK_HZ/(BAUD*8) + 1
uint16_t frmEn = 0;
@ -26,6 +30,8 @@ void FMSTREnableSet(void)
frmEn = 1;
}
void FRMUartInit(void)
{
FMSTR_Init();
@ -76,7 +82,7 @@ void FRMUartInit(void)
// Note: Clocks were turned on to the SCIA peripheral
// in the InitSysCtrl() function
//
EALLOW;
SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
@ -111,11 +117,13 @@ void FRMUartInit(void)
// SCIA at 115200 baud
// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0x35.
//
SciaRegs.SCIHBAUD.all = 0x0001;
SciaRegs.SCILBAUD.all = 0x0045;
uint16_t Brr = BRR;
SciaRegs.SCIHBAUD.all = 0xFF & (Brr>>8);//0x0002;
SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B;
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
EDIS;
FMSTREnableSet();
}

2
Projects/epwm_test/src/frmmstr_run.c
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@ -30,11 +30,13 @@ static uint16_t diod = 0;
diod++;
if(diod > 7) diod = 0;
Gpio_rainbow(diod);
//FMSTR_SCI_PUTCHAR(0xA5);
}
}
FMSTR_Poll();
FMSTR_Recorder();
FMSTREnableClr();
Gpio95out(Rele);
}
}

20
Projects/epwm_test/src/init_perif.c
View File

@ -1,7 +1,7 @@
/*
* init_perif.c
*
* Created on: 21 àâã. 2023 ã.
* Created on: 21 <EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts
*/
@ -30,6 +30,11 @@ void InitPerif(void)
GpioDiodInit();
GpioSetGreen();
EALLOW;
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
EDIS;
InitSysCtrl();
GpioSetBlue();
@ -65,12 +70,12 @@ void InitPerif(void)
InitPieVectTable();
GpioInit();
//
SdfmInitEnable();
SdfmInit();
SdfmGpioInit();
SdfmInitInterruptEn();
//
PWMInitEnable();
PWMAllInit();
PWMGpioInit();
@ -83,15 +88,8 @@ void InitPerif(void)
BissGpioInit();
BissInit();
// SpiGpioInit();
// SpiInit();
// I2CMasterGpioInit();
// I2CMasterInit(I2C_OWN_ADDRESS,I2C_SLAVE_ADDRESS);
FRMUartInit();
// vectorInitCurrLoop();
// ConfigureADC();
//