232 lines
11 KiB
C
232 lines
11 KiB
C
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//#############################################################################
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//
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// FILE: startup_cm.c
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//
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// TITLE: Cortex M4 Family Interrupt Vector Table for CGT.
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//
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//#############################################################################
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//
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//
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//#############################################################################
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#include <stdint.h>
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//
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// Forward declaration of the default fault handlers.
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//
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static void resetISR(void);
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static void nmiISR(void);
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static void faultISR(void);
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static void defaultISR(void);
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//
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// External declaration for the reset handler that is to be called when the
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// processor is started
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//
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extern void _c_int00(void);
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//
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// Linker variable that marks the top of the stack.
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//
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extern unsigned long __STACK_END;
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// External declarations for the interrupt handlers used by the application.
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// To be added by user
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//
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// Interrupt vector table. In the RAM variant, the vectorTableRAM is used and
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// in the Flash variant, the vectorTableFlash is used. The Flash variant can be
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// be used when memory is a concern and the RAM variant can be used when
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// speed is a concern.
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//
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#ifdef _FLASH
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#pragma RETAIN(vectorTableFlash)
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#pragma DATA_ALIGN(vectorTableFlash, 1024U)
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#pragma DATA_SECTION(vectorTableFlash, ".vftable")
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void (* const vectorTableFlash[])(void) =
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#else
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#pragma RETAIN(vectorTableRAM)
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#pragma DATA_ALIGN(vectorTableRAM, 1024U)
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#pragma DATA_SECTION(vectorTableRAM, ".vtable")
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void (* const vectorTableRAM[])(void) =
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#endif
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{
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(void (*)(void))((uint32_t)&__STACK_END),
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/* The initial stack pointer */
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resetISR, /* The reset handler */
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nmiISR, /* The NMI handler */
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faultISR, /* The hard fault handler */
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defaultISR, /* The MPU fault handler */
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defaultISR, /* The bus fault handler */
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defaultISR, /* The usage fault handler */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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defaultISR, /* SVCall handler */
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defaultISR, /* Debug monitor handler */
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0, /* Reserved */
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defaultISR, /* The PendSV handler */
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defaultISR, /* The SysTick handler */
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defaultISR, /* MCANSS_0 handler */
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defaultISR, /* MCANSS_1 handler */
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defaultISR, /* MCANSS_WAKE_AND_TS_PLS ISR*/
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defaultISR, /* MCANSS_ECC_CORR_PLS ISR */
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defaultISR, /* Reserved */
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defaultISR, /* ECAT ISR */
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defaultISR, /* ECAT_SYNC0 ISR */
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defaultISR, /* ECAT_SYNC1 ISR */
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defaultISR, /* ECAT_RST ISR ISR */
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defaultISR, /* CANA0 ISR */
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defaultISR, /* CANA1 ISR */
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defaultISR, /* CANB0 ISR */
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defaultISR, /* CANB1 ISR */
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defaultISR, /* EMAC ISR */
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defaultISR, /* EMAC_TX0 ISR */
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defaultISR, /* EMAC_TX1 ISR */
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defaultISR, /* EMAC_RX0 ISR */
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defaultISR, /* EMAC_RX1 ISR */
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defaultISR, /* UART0 ISR */
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defaultISR, /* Reserved */
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defaultISR, /* SSI0 ISR */
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defaultISR, /* Reserved */
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defaultISR, /* I2C0 ISR */
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defaultISR, /* Reserved */
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defaultISR, /* USB ISR */
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defaultISR, /* UDMA_SW ISR */
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defaultISR, /* UDMA_ERR ISR */
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defaultISR, /* Reserved */
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defaultISR, /* Reserved */
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defaultISR, /* CPU1TOCMIPC0 ISR */
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defaultISR, /* CPU1TOCMIPC1 ISR */
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defaultISR, /* CPU1TOCMIPC2 ISR */
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defaultISR, /* CPU1TOCMIPC3 ISR */
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defaultISR, /* CPU1TOCMIPC4 ISR */
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defaultISR, /* CPU1TOCMIPC5 ISR */
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defaultISR, /* CPU1TOCMIPC6 ISR */
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defaultISR, /* CPU1TOCMIPC7 ISR */
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defaultISR, /* CPU2TOCMIPC0 ISR */
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defaultISR, /* CPU2TOCMIPC1 ISR */
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defaultISR, /* CPU2TOCMIPC2 ISR */
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defaultISR, /* CPU2TOCMIPC3 ISR */
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defaultISR, /* CPU2TOCMIPC4 ISR */
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defaultISR, /* CPU2TOCMIPC5 ISR */
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defaultISR, /* CPU2TOCMIPC6 ISR */
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defaultISR, /* CPU2TOCMIPC7 ISR */
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defaultISR, /* FMC ISR */
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defaultISR, /* FMC_CORR_ERR ISR */
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defaultISR, /* AES Interrupt ISR */
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defaultISR, /* TIMER0 ISR */
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defaultISR, /* TIMER1 ISR */
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defaultISR, /* TIMER2 ISR */
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defaultISR, /* CMRAM_TESTERROR_LOG ISR */
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defaultISR, /* Reserved 52 */
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defaultISR, /* Reserved 53 */
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defaultISR, /* Reserved 54 */
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defaultISR, /* Reserved 55 */
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defaultISR, /* Reserved 56 */
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defaultISR, /* Reserved 57 */
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defaultISR, /* Reserved 58 */
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defaultISR, /* Reserved 59 */
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defaultISR, /* Reserved 60 */
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defaultISR, /* Reserved 61 */
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defaultISR, /* Reserved 62 */
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defaultISR /* Reserved 63 */
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};
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//
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// This is the code that gets called when the processor first starts execution
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// following a reset event.
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// Any actions (such as making decisions based on the reset cause register,
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// and resetting the bits in that register) are left solely in the hands of
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// the application.
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//
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#pragma RETAIN(resetISR)
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#pragma CODE_SECTION(resetISR, ".resetisr")
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void resetISR(void)
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{
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//
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// Jump to the CCS C Initialization Routine.
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//
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__asm(" .global _c_int00\n"
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" b.w _c_int00");
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}
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//
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// This is the code that gets called when the processor receives a NMI. This
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// simply enters an infinite loop, preserving the system state for examination
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// by a debugger.
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//
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static void nmiISR(void)
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{
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//
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// Enter an infinite loop.
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//
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while(1)
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{
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}
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}
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//
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// This is the code that gets called when the processor receives a fault
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// interrupt. This simply enters an infinite loop, preserving the system state
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// for examination by a debugger.
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//
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static void faultISR(void)
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{
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//
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// Enter an infinite loop.
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//
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while(1)
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{
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}
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}
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//
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// This is the code that gets called when the processor receives an unexpected
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// interrupt. This simply enters an infinite loop, preserving the system state
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// for examination by a debugger.
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//
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static void defaultISR(void)
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{
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//
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// Enter an infinite loop.
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//
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while(1)
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{
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}
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}
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