2023-09-14 14:39:29 +03:00
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/*
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* BL25CM1A.c
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*
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* Created on: 7 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
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* Author: seklyuts
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*/
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#include "f28x_project.h"
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#include "spi_init.h"
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#define WREN 0b00000110 //Enable Write Operations
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#define WRDI 0b00000100 //Disable Write Operations
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#define RDSR 0b00000101 //Read Status Register
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#define WRSR 0b00000001 //Write Status Register
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#define READ 0b00000011 //Read Data from Memory
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#define WRITE 0b00000010 //Write Data to Memory
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#define RDID 0b10000011 //Read identification page
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#define WRID 0b10000010 //Write identification page
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#define RDLS 0b10000011 //Reads the identification page lock status
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#define LID 0b10000010 //Locks the identification page in read-only mode
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uint16_t sdata2 = RDSR; // sent data
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2023-09-26 08:51:03 +03:00
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uint16_t rdata2[16] ; // received data
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//uint16_t error2 = 0;
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2023-09-14 14:39:29 +03:00
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void Bl25cm1a_en(void)
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{
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2023-09-26 08:51:03 +03:00
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volatile uint16_t empty;
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transmitData(WREN);
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while(SpiRegs.SPIFFRX.bit.RXFFST != 1)
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2023-09-14 14:39:29 +03:00
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{
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}
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2023-09-26 08:51:03 +03:00
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empty = SpiRegs.SPIRXBUF;
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2023-09-14 14:39:29 +03:00
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}
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void Bl25cm1a_write(void)
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{
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2023-09-26 08:51:03 +03:00
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transmitData(sdata2);
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transmitData(0xFF);
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while(SpiRegs.SPIFFRX.bit.RXFFST != 2)
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2023-09-14 14:39:29 +03:00
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{
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}
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2023-09-26 08:51:03 +03:00
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rdata2[0] = SpiRegs.SPIRXBUF;
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rdata2[1] = SpiRegs.SPIRXBUF;
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}
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2023-09-14 14:39:29 +03:00
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2023-09-26 08:51:03 +03:00
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#define quant 8
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2023-09-14 14:39:29 +03:00
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2023-09-26 08:51:03 +03:00
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void Bl25cm1a_read_data(uint32_t Addr)
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{
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volatile uint16_t empty, i, j;
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transmitData(READ);
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transmitData(Addr>>16);
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transmitData(Addr>>8);
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transmitData(Addr);
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for(i = 0; i<quant; i++) transmitData(0xFF);
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while(SpiRegs.SPIFFRX.bit.RXFFST != (quant+4))
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{
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2023-09-14 14:39:29 +03:00
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2023-09-26 08:51:03 +03:00
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}
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empty = SpiRegs.SPIRXBUF;
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empty = SpiRegs.SPIRXBUF;
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empty = SpiRegs.SPIRXBUF;
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empty = SpiRegs.SPIRXBUF;
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for(j = 0; j<quant; j++)
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{
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rdata2[j] = SpiRegs.SPIRXBUF;
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}
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2023-09-14 14:39:29 +03:00
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}
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2023-09-26 08:51:03 +03:00
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void Bl25cm1a_write_data(uint32_t Addr)
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2023-09-14 14:39:29 +03:00
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{
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2023-09-26 08:51:03 +03:00
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volatile uint16_t empty, i, j;
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transmitData(WRITE);
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transmitData(Addr>>16);
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transmitData(Addr>>8);
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transmitData(Addr);
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for(i = 0; i<quant; i++) transmitData(rdata2[i]);
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while(SpiRegs.SPIFFRX.bit.RXFFST != (quant+4))
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{
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2023-09-14 14:39:29 +03:00
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2023-09-26 08:51:03 +03:00
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}
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empty = SpiRegs.SPIRXBUF;
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empty = SpiRegs.SPIRXBUF;
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empty = SpiRegs.SPIRXBUF;
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empty = SpiRegs.SPIRXBUF;
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for(j = 0; j<quant; j++)
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{
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empty = SpiRegs.SPIRXBUF;
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}
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2023-09-14 14:39:29 +03:00
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}
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