451 lines
13 KiB
C
451 lines
13 KiB
C
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//###########################################################################
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//
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// FILE: fsi.c
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//
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// TITLE: C28x FSI driver.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#include "fsi.h"
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//*****************************************************************************
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//
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//! \internal
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//!
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//! Provides delay based on requested count. Needed while performing reset and
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//! flush sequence, sufficient delay ensures reliability in operation.
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//
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//*****************************************************************************
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static void FSI_delayWait(uint32_t n)
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{
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//
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// Taking local temp counter to avoid MISRAC:2012 rule 17.8 which states not
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// to modify parameter passed to a function call.
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//
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uint32_t temp;
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for(temp = n; temp > 0U; temp--)
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{
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}
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}
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//*****************************************************************************
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//
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// FSI_resetTxModule
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//
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//*****************************************************************************
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void
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FSI_resetTxModule(uint32_t base, FSI_TxSubmoduleInReset submodule)
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{
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//
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// Check the arguments.
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//
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ASSERT(FSI_isTxBaseValid(base));
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EALLOW;
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switch(submodule)
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{
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case FSI_TX_MAIN_CORE_RESET:
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HWREGH(base + FSI_O_TX_MAIN_CTRL) =
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((uint16_t)FSI_TX_MAIN_CTRL_CORE_RST |
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(FSI_CTRL_REG_KEY << FSI_TX_MAIN_CTRL_KEY_S));
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break;
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case FSI_TX_CLOCK_RESET:
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HWREGH(base + FSI_O_TX_CLK_CTRL) |= FSI_TX_CLK_CTRL_CLK_RST;
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break;
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case FSI_TX_PING_TIMEOUT_CNT_RESET:
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HWREGH(base + FSI_O_TX_PING_CTRL) |= FSI_TX_PING_CTRL_CNT_RST;
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break;
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default:
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//
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// Invalid submodule input
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//
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ASSERT(false);
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// FSI_clearTxModuleReset
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//
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//*****************************************************************************
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void
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FSI_clearTxModuleReset(uint32_t base, FSI_TxSubmoduleInReset submodule)
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{
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//
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// Check the arguments.
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//
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ASSERT(FSI_isTxBaseValid(base));
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EALLOW;
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switch(submodule)
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{
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//
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// Key value must be written into main control register and ensure
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// that FLUSH pattern is not sent while doing Tx core reset
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//
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case FSI_TX_MAIN_CORE_RESET:
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HWREGH(base + FSI_O_TX_MAIN_CTRL) =
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(HWREGH(base + FSI_O_TX_MAIN_CTRL) &
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(~FSI_TX_MAIN_CTRL_CORE_RST)) |
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(FSI_CTRL_REG_KEY << FSI_TX_MAIN_CTRL_KEY_S);
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break;
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case FSI_TX_CLOCK_RESET:
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HWREGH(base + FSI_O_TX_CLK_CTRL) &= ~FSI_TX_CLK_CTRL_CLK_RST;
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break;
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case FSI_TX_PING_TIMEOUT_CNT_RESET:
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HWREGH(base + FSI_O_TX_PING_CTRL) &= ~FSI_TX_PING_CTRL_CNT_RST;
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break;
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default:
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//
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// Invalid submodule input
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//
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ASSERT(false);
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// FSI_writeTxBuffer
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//
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//*****************************************************************************
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void
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FSI_writeTxBuffer(uint32_t base, const uint16_t array[], uint16_t length,
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uint16_t bufOffset)
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{
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//
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// Check the arguments.
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//
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ASSERT(FSI_isTxBaseValid(base));
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ASSERT((length - 1U) <= FSI_MAX_VALUE_BUF_PTR_OFF);
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ASSERT(bufOffset <= FSI_MAX_VALUE_BUF_PTR_OFF);
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uint16_t i = 0U, j, tempBufOffset = bufOffset;
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for(j = 0U; j < length; j++)
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{
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//
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// Check for wrap around in case more words to be written in buffer
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// when last write happened at maximum offset in Tx buffer
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//
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if((tempBufOffset + i) > FSI_MAX_VALUE_BUF_PTR_OFF)
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{
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tempBufOffset = 0U;
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i = 0U;
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}
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//
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// Write one 16 bit word, increment buffer pointer
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//
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HWREGH(base + FSI_O_TX_BUF_BASE(tempBufOffset) + i) = array[j];
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i++;
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}
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}
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//*****************************************************************************
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//
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// FSI_resetRxModule
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//
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//*****************************************************************************
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void
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FSI_resetRxModule(uint32_t base, FSI_RxSubmoduleInReset submodule)
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{
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//
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// Check the arguments.
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//
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ASSERT(FSI_isRxBaseValid(base));
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EALLOW;
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switch(submodule)
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{
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case FSI_RX_MAIN_CORE_RESET:
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HWREGH(base + FSI_O_RX_MAIN_CTRL) |=
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((uint16_t)FSI_RX_MAIN_CTRL_CORE_RST |
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(FSI_CTRL_REG_KEY << FSI_RX_MAIN_CTRL_KEY_S));
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break;
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case FSI_RX_FRAME_WD_CNT_RESET:
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HWREGH(base + FSI_O_RX_FRAME_WD_CTRL) |=
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FSI_RX_FRAME_WD_CTRL_FRAME_WD_CNT_RST;
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break;
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case FSI_RX_PING_WD_CNT_RESET:
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HWREGH(base + FSI_O_RX_PING_WD_CTRL) |=
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FSI_RX_PING_WD_CTRL_PING_WD_RST;
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break;
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default:
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//
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// Invalid submodule input
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//
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ASSERT(false);
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// FSI_clearRxModuleReset
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//
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//*****************************************************************************
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void
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FSI_clearRxModuleReset(uint32_t base, FSI_RxSubmoduleInReset submodule)
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{
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//
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// Check the arguments.
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//
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ASSERT(FSI_isRxBaseValid(base));
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EALLOW;
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switch(submodule)
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{
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case FSI_RX_MAIN_CORE_RESET:
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HWREGH(base + FSI_O_RX_MAIN_CTRL) =
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(HWREGH(base + FSI_O_RX_MAIN_CTRL) &
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(~FSI_RX_MAIN_CTRL_CORE_RST)) |
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(FSI_CTRL_REG_KEY << FSI_RX_MAIN_CTRL_KEY_S);
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break;
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case FSI_RX_FRAME_WD_CNT_RESET:
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HWREGH(base + FSI_O_RX_FRAME_WD_CTRL) &=
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~FSI_RX_FRAME_WD_CTRL_FRAME_WD_CNT_RST;
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break;
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case FSI_RX_PING_WD_CNT_RESET:
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HWREGH(base + FSI_O_RX_PING_WD_CTRL) &=
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~FSI_RX_PING_WD_CTRL_PING_WD_RST;
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break;
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default:
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//
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// Invalid submodule input
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//
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ASSERT(false);
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// FSI_readRxBuffer
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//
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//*****************************************************************************
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void
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FSI_readRxBuffer(uint32_t base, uint16_t array[], uint16_t length,
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uint16_t bufOffset)
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{
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//
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// Check the arguments.
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//
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ASSERT(FSI_isRxBaseValid(base));
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ASSERT((length - 1U) <= FSI_MAX_VALUE_BUF_PTR_OFF);
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ASSERT(bufOffset <= FSI_MAX_VALUE_BUF_PTR_OFF);
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uint16_t i = 0U, j, tempBufOffset = bufOffset;
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for(j = 0U; j < length; j++)
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{
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//
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// Check for wrap around in case more words to be read in buffer when
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// last read happened at maximum offset in Rx buffer
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//
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if((tempBufOffset + i) > FSI_MAX_VALUE_BUF_PTR_OFF)
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{
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tempBufOffset = 0U;
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i = 0U;
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}
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//
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// Read one 16 bit word, increment buffer pointer
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//
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array[j] = HWREGH(base + FSI_O_RX_BUF_BASE(tempBufOffset) + i);
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i++;
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}
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}
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//*****************************************************************************
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//
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// FSI_configRxDelayLine
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//
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//*****************************************************************************
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void
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FSI_configRxDelayLine(uint32_t base, FSI_RxDelayTapType delayTapType,
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uint16_t tapValue)
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{
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//
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// Check the arguments.
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//
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ASSERT(FSI_isRxBaseValid(base));
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ASSERT(tapValue <= FSI_RX_MAX_DELAY_LINE_VAL);
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EALLOW;
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switch(delayTapType)
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{
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case FSI_RX_DELAY_CLK:
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HWREGH(base + FSI_O_RX_DLYLINE_CTRL) =
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(HWREGH(base + FSI_O_RX_DLYLINE_CTRL) &
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(~FSI_RX_DLYLINE_CTRL_RXCLK_DLY_M)) |
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(tapValue << FSI_RX_DLYLINE_CTRL_RXCLK_DLY_S);
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break;
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case FSI_RX_DELAY_D0:
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HWREGH(base + FSI_O_RX_DLYLINE_CTRL) =
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(HWREGH(base + FSI_O_RX_DLYLINE_CTRL) &
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(~FSI_RX_DLYLINE_CTRL_RXD0_DLY_M)) |
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(tapValue << FSI_RX_DLYLINE_CTRL_RXD0_DLY_S);
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break;
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case FSI_RX_DELAY_D1:
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HWREGH(base + FSI_O_RX_DLYLINE_CTRL) =
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(HWREGH(base + FSI_O_RX_DLYLINE_CTRL) &
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(~FSI_RX_DLYLINE_CTRL_RXD1_DLY_M)) |
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(tapValue << FSI_RX_DLYLINE_CTRL_RXD1_DLY_S);
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break;
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default:
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//
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// Invalid tap selection input
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//
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ASSERT(false);
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// FSI_performTxInitialization
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//
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//*****************************************************************************
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void FSI_performTxInitialization(uint32_t base, uint16_t prescalar)
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{
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//
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// Check the arguments.
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//
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ASSERT(FSI_isTxBaseValid(base));
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ASSERT(prescalar <= 0xFFU );
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//
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// Reset the Tx core
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//
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FSI_resetTxModule(base, FSI_TX_MAIN_CORE_RESET);
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//
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// Select PLL clock as source for clock dividers
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//
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FSI_selectTxPLLClock(base);
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//
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// Sequence is :: Reset clock divider -> Set prescalar value
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// in reset -> Wait -> Enable clock -> Release reset
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//
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FSI_resetTxModule(base, FSI_TX_CLOCK_RESET);
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FSI_configPrescalar(base, prescalar);
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FSI_delayWait(1);
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FSI_enableTxClock(base);
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FSI_clearTxModuleReset(base, FSI_TX_CLOCK_RESET);
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//
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// Wait sufficient time before releasing reset of Tx core
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//
|
||
|
|
FSI_delayWait(prescalar);
|
||
|
|
FSI_clearTxEvents(base, FSI_TX_EVTMASK);
|
||
|
|
FSI_clearTxModuleReset(base, FSI_TX_MAIN_CORE_RESET);
|
||
|
|
FSI_delayWait(2U * prescalar);
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// FSI_performRxInitialization
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void FSI_performRxInitialization(uint32_t base)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT(FSI_isRxBaseValid(base));
|
||
|
|
|
||
|
|
FSI_resetRxModule(base, FSI_RX_MAIN_CORE_RESET);
|
||
|
|
|
||
|
|
FSI_clearRxEvents(base, FSI_RX_EVTMASK);
|
||
|
|
|
||
|
|
//
|
||
|
|
// It is important to ensure that there is no active clocks on RXCLK before
|
||
|
|
// releasing the reset. This can be accomplished by handshaking or by using
|
||
|
|
// the chip level connectivity options to ensure that no receive clocks are
|
||
|
|
// seen till the reset is released.
|
||
|
|
// FSI Rx module will come out of reset only when the receive clock is sent
|
||
|
|
// in or by sending a Flush pattern from FSI Tx.
|
||
|
|
//
|
||
|
|
FSI_delayWait(1);
|
||
|
|
FSI_clearRxModuleReset(base, FSI_RX_MAIN_CORE_RESET);
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// FSI_executeTxFlushSequence
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void FSI_executeTxFlushSequence(uint32_t base, uint16_t prescalar)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT(FSI_isTxBaseValid(base));
|
||
|
|
ASSERT(prescalar <= 0xFFU );
|
||
|
|
|
||
|
|
FSI_sendTxFlush(base);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Inserting delay as recommended in TRM, It ensures that the transmit
|
||
|
|
// module core sees sufficient TXCLK cycles before stopping FLUSH pattern.
|
||
|
|
//
|
||
|
|
FSI_delayWait(2U * prescalar);
|
||
|
|
|
||
|
|
FSI_stopTxFlush(base);
|
||
|
|
}
|