commit 4fdfe7547d752d75ecceb2ae69c9af6caf056389 Author: sedov Date: Thu Aug 29 10:09:49 2024 +0300 dev(UML-2579): Создан новый реазиторий добален тест иницилизации перефериии diff --git a/EFC_PlatformC28x/.ccsproject b/EFC_PlatformC28x/.ccsproject new file mode 100644 index 0000000..5fe545f --- /dev/null +++ b/EFC_PlatformC28x/.ccsproject @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/EFC_PlatformC28x/.cproject b/EFC_PlatformC28x/.cproject new file mode 100644 index 0000000..e96acf5 --- /dev/null +++ b/EFC_PlatformC28x/.cproject @@ -0,0 +1,146 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/EFC_PlatformC28x/.gitignore b/EFC_PlatformC28x/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/EFC_PlatformC28x/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/EFC_PlatformC28x/.project b/EFC_PlatformC28x/.project new file mode 100644 index 0000000..73897b2 --- /dev/null +++ b/EFC_PlatformC28x/.project @@ -0,0 +1,27 @@ + + + EFC_PlatformC28x + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/EFC_PlatformC28x/.settings/org.eclipse.cdt.codan.core.prefs b/EFC_PlatformC28x/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/EFC_PlatformC28x/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/EFC_PlatformC28x/.settings/org.eclipse.cdt.debug.core.prefs b/EFC_PlatformC28x/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000..2adc7b1 --- /dev/null +++ b/EFC_PlatformC28x/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/EFC_PlatformC28x/.settings/org.eclipse.core.resources.prefs b/EFC_PlatformC28x/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..175e60b --- /dev/null +++ b/EFC_PlatformC28x/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,10 @@ +eclipse.preferences.version=1 +encoding//Debug/VoltageMonitoring/subdir_rules.mk=UTF-8 +encoding//Debug/VoltageMonitoring/subdir_vars.mk=UTF-8 +encoding//Debug/lib/subdir_rules.mk=UTF-8 +encoding//Debug/lib/subdir_vars.mk=UTF-8 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/EFC_PlatformC28x/Atomic.cpp b/EFC_PlatformC28x/Atomic.cpp new file mode 100644 index 0000000..6bea5bf --- /dev/null +++ b/EFC_PlatformC28x/Atomic.cpp @@ -0,0 +1,61 @@ +/* + * \file Atomic.cpp + * \project EFC_PlatformC28x + * \date 23 мая 2024 г. + * \author leonidTitov + * + * \brief Создание флага atomic из одной ассемблерной операции (ну ладно, из трёх) + */ + +#include "Atomic.hpp" + +#ifndef ATOMIC_FLAGS_COUNT +#define ATOMIC_FLAGS_COUNT 32 +#endif + +extern "C" { + + extern uint16_t _test_and_set_bit_1( volatile uint16_t * p ); + extern void _clear_bit_1( volatile uint16_t * p ); + +} + +namespace { + + volatile uint16_t atomic_flags[ATOMIC_FLAGS_COUNT] = {}; + + volatile uint16_t * create_flag() { + + for( int i = 0; i < ATOMIC_FLAGS_COUNT; i++ ) + if( not( _test_and_set_bit_1( atomic_flags + i ) ) ) + return &atomic_flags[i]; + + while(true); + + } + + void delete_flag( volatile uint16_t * atomic_flag ) { + + _clear_bit_1( atomic_flag ); + + } + +} + +/** + * Create Flag + */ +umlib::imp::AtomicFlag::AtomicFlag() : flag( create_flag() ) { + + clear(); + +} + +/** + * Delete Flag + */ +umlib::imp::AtomicFlag::~AtomicFlag() { + + delete_flag( flag ); + +} diff --git a/EFC_PlatformC28x/Atomic.hpp b/EFC_PlatformC28x/Atomic.hpp new file mode 100644 index 0000000..07c3726 --- /dev/null +++ b/EFC_PlatformC28x/Atomic.hpp @@ -0,0 +1,75 @@ +/** + * \file Atomic.hpp + * \project EFC_PlatformC28x + * \date 10 мая 2024 г. + * \author leonidTitov + * + * \brief Проба пера использования ассемблерного кода для atomic + */ + +#ifndef ATOMIC_HPP_ +#define ATOMIC_HPP_ + +#include + +namespace umlib { namespace imp { + +class AtomicFlag { + + volatile uint16_t * flag; + +public: + + AtomicFlag(); + AtomicFlag(const AtomicFlag &) = delete; + + AtomicFlag & operator=(const AtomicFlag &) = delete; + AtomicFlag & operator=(const AtomicFlag &) volatile = delete; + + bool test_and_set() volatile; + bool test_and_set(); + + void clear() volatile; + void clear(); + + ~AtomicFlag(); + +}; + +}} + +extern "C" { + + extern uint16_t _test_and_set_bit( volatile uint16_t * p ); + extern void _clear_bit( volatile uint16_t * p ); + +} + +inline bool umlib::imp::AtomicFlag::test_and_set() volatile { + + return _test_and_set_bit( flag ); + +} + +inline bool umlib::imp::AtomicFlag::test_and_set() { + + return _test_and_set_bit( flag ); + +} + +inline void umlib::imp::AtomicFlag::clear() volatile { + + _clear_bit( flag ); + +} + +inline void umlib::imp::AtomicFlag::clear() { + + _clear_bit( flag ); + +} + +#endif /* ATOMIC_HPP_ */ + + +// end file Atomic.hpp diff --git a/EFC_PlatformC28x/Diakont-A.jpg b/EFC_PlatformC28x/Diakont-A.jpg new file mode 100644 index 0000000..2df3b85 Binary files /dev/null and b/EFC_PlatformC28x/Diakont-A.jpg differ diff --git a/EFC_PlatformC28x/F2838xD_ClearBit.asm b/EFC_PlatformC28x/F2838xD_ClearBit.asm new file mode 100644 index 0000000..e53da99 --- /dev/null +++ b/EFC_PlatformC28x/F2838xD_ClearBit.asm @@ -0,0 +1,33 @@ +;//########################################################################### +;// +;// FILE: F2838xD_TestAndSet.asm +;// +;// Titov L.A. +;// +;// +;//########################################################################### + +;D + + .text + .global _clear_bit + .global _clear_bit_1 + + +;Input: volatile uint16_t * - AR4 (on low 16 bit address space) +;Output: void + +_clear_bit: + TCLR *AR4,#0 ;Clear specified bit, read-modify-write operation. + LRETR + +;Input: volatile uint16_t * - AR4 (on low 16 bit address space) +;Output: void + +_clear_bit_1: + TCLR *AR4,#1 ;Clear specified bit, read-modify-write operation. + LRETR + +;// +;// End of file. +;// diff --git a/EFC_PlatformC28x/F2838xD_TestAndSet.asm b/EFC_PlatformC28x/F2838xD_TestAndSet.asm new file mode 100644 index 0000000..5600537 --- /dev/null +++ b/EFC_PlatformC28x/F2838xD_TestAndSet.asm @@ -0,0 +1,29 @@ +;//*########################################################################## +;// +;// \FILE F2838xD_TestAndSet.asm +;// \project EFC_PlatformC28x +;// \date 10 мая 2024 г. +;// \author Titov L.A. +;// +;// \breif Test of make-run-read-modify-write(bit) atomic operation +;// +;//########################################################################### + +;D + + .text + .global _test_and_set + + +;Input: volatile uint16_t * - AR4 (on low 16 bit address space) +;Output: uint16_t - AL (return value) + +_test_and_set: + TSET *AR4,#0 ;Test and set specified bit, read-modify-write operation. + MOVB AL,#0 + MOVB AL,#1,TC + LRETR + +;// +;// End of file. +;// diff --git a/EFC_PlatformC28x/F2838xD_TestAndSetBit.asm b/EFC_PlatformC28x/F2838xD_TestAndSetBit.asm new file mode 100644 index 0000000..f010e3e --- /dev/null +++ b/EFC_PlatformC28x/F2838xD_TestAndSetBit.asm @@ -0,0 +1,35 @@ +;//########################################################################### +;// +;// FILE: F2838xD_TestAndSet.asm +;// +;// Titov L.A. +;// +;// +;//########################################################################### + +;D + + .text + .global _test_and_set_bit + .global _test_and_set_bit_1 + + +;Input: volatile uint16_t * - AR4 (on low 16 bit address space) +;Output: uint16_t - AL (return value) + +_test_and_set_bit: + TSET *AR4,#0 ;Test and set specified bit, read-modify-write operation. + MOVB AL,#0 + MOVB AL,#1,TC + LRETR + + +_test_and_set_bit_1: + TSET *AR4,#1 ;Test and set specified bit, read-modify-write operation. + MOVB AL,#0 + MOVB AL,#1,TC + LRETR + +;// +;// End of file. +;// diff --git a/EFC_PlatformC28x/README.md b/EFC_PlatformC28x/README.md new file mode 100644 index 0000000..9457d76 --- /dev/null +++ b/EFC_PlatformC28x/README.md @@ -0,0 +1,42 @@ +# `Universal modulary Library ` +![](Diakont-A.jpg) +[![build](https://github.com/github/docs/actions/workflows/main.yml/badge.svg?branch=master)](http://sofdev:3000/Industrial/EFC_PlatformC28x.git/actions?workflow=build) +## `EFC_PlatformC28x` +# Проект на TMS320F28388D использование AtomicFlag в кроссплатформенной библиотеке UMLibrary +## Overview +Это исходный код на C++ проекта EFC_PlatformC28x для процессора TMS320F28388D. +Сам проект расположен [здесь](http://sofdev:3000/Industrial/EFC_PlatformC28x). +Фреймворк для его тестирования - [здесь](http://sofdev:3000/Industrial/EFC_PlatformC28xTest). + +## Версия +#### `Текущая версия: 1.0 ` + +### Технические детали +Проект использует ассемблерный (!!) код для реализации AtomicFlag. (**Остальное допишет Леонид**). +### Подключение +При включении его как библиотеки нужно любым образом определить следующие переменные: + + COMMON_FLAGS - для флагов компиляции + COMMON_INCLUDES - для дополнительных включений +### Документация +В папке /Docs пока ничего нет, как и папки. +Статья в Базе Знаний будет [здесь](http://sofdev:8081/articles/UML-A-438/Realizaciya-atomarnyh-operacij-v-UMLibrary). +### Исходные данные +Исходными данными для сборки служат: +- ничего? + +## Реализация +Табл.1 - Параметры, заданные при генерации исходных текстов. + + +## Usage +Проект предназначен для CCS (ver.>12.4). + + +## Building +Запустить проект, что для этого нужно: + запустить проект + +## Troubleshooting +— пока не найдены + diff --git a/EFC_PlatformC28x/VoltageMonitoring/SDFM.cpp b/EFC_PlatformC28x/VoltageMonitoring/SDFM.cpp new file mode 100644 index 0000000..e4fa5e7 --- /dev/null +++ b/EFC_PlatformC28x/VoltageMonitoring/SDFM.cpp @@ -0,0 +1,340 @@ +#include "SDFM.hpp" +#include "f2838x_pievect.h" + + + + + + + bool umlib::imp::Sdfm::initSdfm(){ + return testSdfmInit(); +} + + /** + * Create Flag + */ + umlib::imp::Sdfm::Sdfm() : flag( ) { + + instance = this; + + } + + /** + * Delete Flag + */ + umlib::imp::Sdfm::~Sdfm() { + + + + } + void umlib::imp::Sdfm::SdfmGpioInit(void) + { + EALLOW; + + GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(16,GPIO_MUX_CPU1,7); //SDFM-1 Channel 1 Data Input (Iu)a + GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(17,GPIO_MUX_CPU1,7); //SDFM-1 Channel 1 Clock Input + + GPIO_SetupPinOptions(22, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(22,GPIO_MUX_CPU1,7); //SDFM-1 Channel 4 Data Input (Iv)b + GPIO_SetupPinOptions(23, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(23,GPIO_MUX_CPU1,7); //SDFM-1 Channel 4 Clock Input + + GPIO_SetupPinOptions(24, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(24,GPIO_MUX_CPU1,7); //SDFM-2 Channel 1 Data Input (Iw)c + GPIO_SetupPinOptions(25, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(25,GPIO_MUX_CPU1,7); //SDFM-2 Channel 1 Clock Input + + GPIO_SetupPinOptions(58, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(58,GPIO_MUX_CPU1,7); //SDFM-2 Channel 2 Data Input (Udc) + GPIO_SetupPinOptions(59, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(59,GPIO_MUX_CPU1,7); //SDFM-2 Channel 2 Clock Input + + GPIO_SetupPinOptions(60, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(60,GPIO_MUX_CPU1,7); //SDFM-2 Channel 3 Data Input (brake) + GPIO_SetupPinOptions(61, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(61,GPIO_MUX_CPU1,7); //SDFM-2 Channel 3 Clock Input + + GPIO_SetupPinOptions(62, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(62,GPIO_MUX_CPU1,7); //SDFM-2 Channel 4 Data Input (sin) + GPIO_SetupPinOptions(63, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(63,GPIO_MUX_CPU1,7); //SDFM-2 Channel 4 Clock Input + + GPIO_SetupPinOptions(65, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(65,GPIO_MUX_CPU1,13); //SDFM-1 Channel 2 Data Input (cos) + GPIO_SetupPinOptions(66, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(66,GPIO_MUX_CPU1,13); //SDFM-1 Channel 2 Clock Input + + GPIO_SetupPinOptions(67, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(67,GPIO_MUX_CPU1,13); //SDFM-1 Channel 3 Data Input (ref) + GPIO_SetupPinOptions(68, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(68,GPIO_MUX_CPU1,13); //SDFM-1 Channel 3 Clock Input + + EDIS; + } + void umlib::imp::Sdfm::SdfmInitEnable(void) + { + EALLOW; + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; + CpuSysRegs.PCLKCR6.bit.SD1 = 1; + CpuSysRegs.PCLKCR6.bit.SD2 = 1; + EDIS; + } + void umlib::imp::Sdfm::sdfmErr(uint16_t N) + { + sdfmAdc[N] = 0; + EALLOW; + SDCPARM_Reg_arr[N]->bit.MFIE = 0; + EDIS; + sdfmAdcErr[N] = 1; + } + void umlib::imp::Sdfm::sdfmGetResult(uint16_t N) + { + uint16_t i = 0; + int32_t OffsetCount = 0; + + FilterResult[N][loopCounter[N]] = *SdfmReadData[N]; + sdfmAdc[N] = FilterResult[N][loopCounter[N]] - sdfmOffset[N]; + if(N != SDFM_U_DC) { + if(loopCounter[N] < MAX_SAMPLES) + loopCounter[N]++; + else + { + loopCounter[N] = 0; + if(!initDone[N]) + { + for(i = 0; i <= (MAX_SAMPLES-1); i++) OffsetCount += FilterResult[N][i]; + sdfmOffset[N] = OffsetCount>>FILTER_BIT; + initDone[N] = 0xFF; + } + else if(initDone[N] != 0xFF) initDone[N]--; + } + } + EALLOW; + SDCPARM_Reg_arr[N]->bit.MFIE = 1; + SDDFPARM_Reg_arr[N]->bit.AE = 0; + EDIS; + sdfmAdcErr[N] = 0; + + } + void umlib::imp::Sdfm::sdfmHandler1() + { + uint16_t i; + uint32_t IntFlags; + IntFlags = Sdfm_readFlagRegister(SDFM1); + sdfmIndex |= (IntFlags & 0xF000)>>12; + + for(i = 0; i < 4; i++) if((uint16_t)IntFlags & (0x1000 << i)) sdfmGetResult(i); + for(i = 0; i < 4; i++) if((uint16_t)IntFlags & (0x100 << i)) sdfmErr(i); + Sdfm_clearFlagRegister(SDFM1,IntFlags); + sdfm_check_all_current_measurements_was_done(); + PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + } + + void umlib::imp::Sdfm::sdfm_check_all_current_measurements_was_done(void) + { + if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS)//���� ��� SDFM ������ ������ � ���������� + { + sdfmIndex = 0; + if(!AllInitDone)// + { + if((initDone[SDFM_IA] == 0xFF)&&(initDone[SDFM_IB] == 0xFF)&&(initDone[SDFM_IC] == 0xFF)) AllInitDone = 1; + } + else + { + // vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]); ���������� + } + } + } + void umlib::imp::Sdfm::sdfmHandler2() + { + uint16_t i; + uint32_t IntFlags; + + IntFlags = Sdfm_readFlagRegister(SDFM2); + sdfmIndex |= (IntFlags & 0xF000)>>8; + + for(i = 0; i < 4; i++) if((uint16_t)IntFlags & (0x1000 << i)) sdfmGetResult(i+4); + for(i = 0; i < 4; i++) if((uint16_t)IntFlags & (0x100 << i)) sdfmErr(i+4); + + Sdfm_clearFlagRegister(SDFM2,IntFlags); + sdfm_check_all_current_measurements_was_done(); + PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + } + void umlib::imp::Sdfm::SdfmInitInterruptEn(void) + { + EALLOW; + PieVectTable.SDFM1_INT = &Sdfm1_ISR; + PieVectTable.SDFM2_INT = &Sdfm2_ISR; + IER |= M_INT5; + Sdfm_clearFlagRegister(SDFM1, 0xFFFFFFFF); + Sdfm_clearFlagRegister(SDFM2, 0xFFFFFFFF); + PieCtrlRegs.PIEIER5.bit.INTx9 = 1; + PieCtrlRegs.PIEIER5.bit.INTx10 = 1; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + EDIS; + } + void umlib::imp::Sdfm::SdfmInit(void) + { + uint16_t HLT, LLT; + Sdfm_configureInputCtrl(SDFM1, FILTER1, MODE_0); + Sdfm_configureInputCtrl(SDFM1, FILTER2, MODE_0); + Sdfm_configureInputCtrl(SDFM1, FILTER3, MODE_0); + Sdfm_configureInputCtrl(SDFM1, FILTER4, MODE_0); + Sdfm_configureInputCtrl(SDFM2, FILTER1, MODE_0); + Sdfm_configureInputCtrl(SDFM2, FILTER2, MODE_0); + Sdfm_configureInputCtrl(SDFM2, FILTER3, MODE_0); + Sdfm_configureInputCtrl(SDFM2, FILTER4, MODE_0); + HLT = 0x7FFF; + LLT = 0x0000; + Sdfm_configureComparator(SDFM1, FILTER1, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM1, FILTER2, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM1, FILTER3, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM1, FILTER4, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM2, FILTER1, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM2, FILTER2, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM2, FILTER3, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM2, FILTER4, SINC3, OSR_32, HLT, LLT); + + Sdfm_enableMFE(SDFM1); + Sdfm_enableMFE(SDFM2); + + Sdfm_configureData_filter(SDFM1, FILTER1, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM1, FILTER2, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM1, FILTER3, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM1, FILTER4, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM2, FILTER1, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM2, FILTER2, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM2, FILTER3, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM2, FILTER4, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + + EALLOW; + + // Sdfm1Regs.SDSYNC1.bit.SYNCSEL = 0x3F; + // Sdfm2Regs.SDSYNC1.bit.SYNCSEL = 0x3F; + // Sdfm1Regs.SDSYNC2.bit.SYNCSEL = 0x3F; + // Sdfm2Regs.SDSYNC2.bit.SYNCSEL = 0x3F; + // Sdfm1Regs.SDSYNC3.bit.SYNCSEL = 0x3F; + // Sdfm2Regs.SDSYNC3.bit.SYNCSEL = 0x3F; + // Sdfm1Regs.SDSYNC4.bit.SYNCSEL = 0x3F; + // Sdfm2Regs.SDSYNC4.bit.SYNCSEL = 0x3F; + + + Sdfm1Regs.SDDFPARM1.bit.SDSYNCEN = 0; + Sdfm2Regs.SDDFPARM1.bit.SDSYNCEN = 0; + Sdfm1Regs.SDDFPARM2.bit.SDSYNCEN = 0; + Sdfm2Regs.SDDFPARM2.bit.SDSYNCEN = 0; + Sdfm1Regs.SDDFPARM3.bit.SDSYNCEN = 0; + Sdfm2Regs.SDDFPARM3.bit.SDSYNCEN = 0; + Sdfm1Regs.SDDFPARM4.bit.SDSYNCEN = 0; + Sdfm2Regs.SDDFPARM4.bit.SDSYNCEN = 0; + EDIS; + + + // Sdfm_configureInterrupt(SDFM1, FILTER1, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); + // Sdfm_configureInterrupt(SDFM1, FILTER2, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); + // Sdfm_configureInterrupt(SDFM1, FILTER3, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); + // Sdfm_configureInterrupt(SDFM1, FILTER4, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); + //// + // Sdfm_configureInterrupt(SDFM2, FILTER1, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); + // Sdfm_configureInterrupt(SDFM2, FILTER2, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); + // Sdfm_configureInterrupt(SDFM2, FILTER3, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); + // Sdfm_configureInterrupt(SDFM2, FILTER4, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); + + + //Sdfm1Regs.SDCPARM4.bit.MFIE = 1; + //Sdfm1Regs.SDDFPARM4.bit.AE = 1; + Sdfm_enableMIE(SDFM1); + Sdfm_enableMIE(SDFM2); + + EALLOW; + Sdfm1Regs.SDDFPARM1.bit.FEN = 1; + Sdfm1Regs.SDDFPARM2.bit.FEN = 1; + Sdfm1Regs.SDDFPARM3.bit.FEN = 1; + Sdfm1Regs.SDDFPARM4.bit.FEN = 1; + Sdfm2Regs.SDDFPARM1.bit.FEN = 1; + Sdfm2Regs.SDDFPARM2.bit.FEN = 1; + Sdfm2Regs.SDDFPARM3.bit.FEN = 1; + Sdfm2Regs.SDDFPARM4.bit.FEN = 1; + EDIS; + } + int16_t umlib::imp::Sdfm::SdfmGetChannel(int16_t N) + { + return sdfmAdc[N]; + } + + + void umlib::imp::Sdfm::sdfm_start_conversion_current(void) + { + sdfmIndex = 0; + EALLOW; + Sdfm1Regs.SDIFLGCLR.all = 0xFFFFFFFF; + Sdfm2Regs.SDIFLGCLR.all = 0xFFFFFFFF; + SDCPARM_Reg_arr[SDFM_IA]->bit.MFIE = 1; + SDDFPARM_Reg_arr[SDFM_IA]->bit.AE = 1; + SDCPARM_Reg_arr[SDFM_IB]->bit.MFIE = 1; + SDDFPARM_Reg_arr[SDFM_IB]->bit.AE = 1; + SDCPARM_Reg_arr[SDFM_IC]->bit.MFIE = 1; + SDDFPARM_Reg_arr[SDFM_IC]->bit.AE = 1; + SDCPARM_Reg_arr[SDFM_U_DC]->bit.MFIE = 1; + SDDFPARM_Reg_arr[SDFM_U_DC]->bit.AE = 1; + EDIS; + } + int16_t umlib::imp::Sdfm::sdfm_get(int16_t N) + { + return sdfmAdc[N]; + } + bool umlib::imp::Sdfm::testSdfmInit(void) { + // + SdfmInitEnable(); + SdfmInit(); + SdfmInitInterruptEn(); + + // SdfmInitEnable + if (CpuSysRegs.PCLKCR0.bit.TBCLKSYNC != 1 || + CpuSysRegs.PCLKCR6.bit.SD1 != 1 || + CpuSysRegs.PCLKCR6.bit.SD2 != 1) { + return false; + } + // + if (Sdfm1Regs.SDDFPARM1.bit.FEN != 1 || + Sdfm1Regs.SDDFPARM2.bit.FEN != 1 || + Sdfm1Regs.SDDFPARM3.bit.FEN != 1 || + Sdfm1Regs.SDDFPARM4.bit.FEN != 1 || + Sdfm2Regs.SDDFPARM1.bit.FEN != 1 || + Sdfm2Regs.SDDFPARM2.bit.FEN != 1 || + Sdfm2Regs.SDDFPARM3.bit.FEN != 1 || + Sdfm2Regs.SDDFPARM4.bit.FEN != 1) { + return false; + } + + if (Sdfm1Regs.SDDFPARM1.bit.SDSYNCEN != 0 || + Sdfm1Regs.SDDFPARM2.bit.SDSYNCEN != 0 || + Sdfm1Regs.SDDFPARM3.bit.SDSYNCEN != 0 || + Sdfm1Regs.SDDFPARM4.bit.SDSYNCEN != 0 || + Sdfm2Regs.SDDFPARM1.bit.SDSYNCEN != 0 || + Sdfm2Regs.SDDFPARM2.bit.SDSYNCEN != 0 || + Sdfm2Regs.SDDFPARM3.bit.SDSYNCEN != 0 || + Sdfm2Regs.SDDFPARM4.bit.SDSYNCEN != 0) { + return false; + } + + if (PieVectTable.SDFM1_INT != &Sdfm1_ISR || + PieVectTable.SDFM2_INT != &Sdfm2_ISR) { + return false; + } + + if ((IER & M_INT5) != M_INT5) { + return false; + } + + if (PieCtrlRegs.PIEIER5.bit.INTx9 != 1 || + PieCtrlRegs.PIEIER5.bit.INTx10 != 1) { + return false; + } + + // true, + return true; + } + diff --git a/EFC_PlatformC28x/VoltageMonitoring/SDFM.hpp b/EFC_PlatformC28x/VoltageMonitoring/SDFM.hpp new file mode 100644 index 0000000..b0b648f --- /dev/null +++ b/EFC_PlatformC28x/VoltageMonitoring/SDFM.hpp @@ -0,0 +1,128 @@ +/* + * SDFM.h + * + * Created on: 27 авг. 2024 г. + * Author: sedov + */ + + +#ifndef VOLTAGEMONITORING_SDFM_HPP_ +#define VOLTAGEMONITORING_SDFM_HPP_ + +#include +#include "f28x_project.h" +#include "f2838x_struct.h" +#include "f2838x_sdfm_drivers.h" +#include "f2838x_gpio.h" +#include "f2838x_pievect.h" +#include "constantsSDFM.hpp" + +namespace umlib { namespace imp { + + + + +class Sdfm { + + volatile uint16_t * flag; + +public: + Sdfm(); + Sdfm(const Sdfm &) = delete; + Sdfm & operator=(const Sdfm &) = delete; + Sdfm & operator=(const Sdfm &) volatile = delete; + bool initSdfm(); + bool teast_SDFM1(); + void clear() volatile; + void clear(); + ~Sdfm(); + void sdfmHandler1(); + void sdfmHandler2(); + void sdfmErr(uint16_t N); + void sdfmGetResult(uint16_t N); + int16_t SdfmGetChannel(int16_t N); + void SdfmGpioInit(void); + void SdfmInitInterruptEn(void); + void SdfmInitEnable(void); + void sdfm_check_all_current_measurements_was_done(void); + void SdfmInit(void); + int16_t sdfm_get(int16_t N); + void sdfm_start_conversion_current(void); + bool testSdfmInit(void); + + static Sdfm* instance; +private: + //uint16_t gPWM_number = 1; // ePWM 1 for synchronizing SDFM1 filters + int16_t Filter0_Result[MAX_SAMPLES]; + int16_t Filter1_Result[MAX_SAMPLES]; + int16_t Filter2_Result[MAX_SAMPLES]; + int16_t Filter3_Result[MAX_SAMPLES]; + int16_t Filter4_Result[MAX_SAMPLES]; + int16_t Filter5_Result[MAX_SAMPLES]; + int16_t Filter6_Result[MAX_SAMPLES]; + int16_t Filter7_Result[MAX_SAMPLES]; + int16_t * FilterResult[8] = {Filter0_Result, Filter1_Result, Filter2_Result, Filter3_Result, Filter4_Result, Filter5_Result, Filter6_Result, Filter7_Result}; + union SDCPARM1_REG * SDCPARM_Reg_arr[8] = { + (union SDCPARM1_REG *)(&Sdfm1Regs.SDCPARM1), + (union SDCPARM1_REG *)(&Sdfm1Regs.SDCPARM2), + (union SDCPARM1_REG *)(&Sdfm1Regs.SDCPARM3), + (union SDCPARM1_REG *)(&Sdfm1Regs.SDCPARM4), + (union SDCPARM1_REG *)(&Sdfm2Regs.SDCPARM1), + (union SDCPARM1_REG *)(&Sdfm2Regs.SDCPARM2), + (union SDCPARM1_REG *)(&Sdfm2Regs.SDCPARM3), + (union SDCPARM1_REG *)(&Sdfm2Regs.SDCPARM4) + }; + union SDDFPARM1_REG * SDDFPARM_Reg_arr[8] = { + (union SDDFPARM1_REG *)(&Sdfm1Regs.SDDFPARM1), + (union SDDFPARM1_REG *)(&Sdfm1Regs.SDDFPARM2), + (union SDDFPARM1_REG *)(&Sdfm1Regs.SDDFPARM3), + (union SDDFPARM1_REG *)(&Sdfm1Regs.SDDFPARM4), + (union SDDFPARM1_REG *)(&Sdfm2Regs.SDDFPARM1), + (union SDDFPARM1_REG *)(&Sdfm2Regs.SDDFPARM2), + (union SDDFPARM1_REG *)(&Sdfm2Regs.SDDFPARM3), + (union SDDFPARM1_REG *)(&Sdfm2Regs.SDDFPARM4) + }; + volatile int16 * SdfmReadData[8] = { + (volatile int16 *)((Uint16)0x5E17), + (volatile int16 *)((Uint16)0x5E27), + (volatile int16 *)((Uint16)0x5E37), + (volatile int16 *)((Uint16)0x5E47), + (volatile int16 *)((Uint16)0x5E97), + (volatile int16 *)((Uint16)0x5EA7), + (volatile int16 *)((Uint16)0x5EB7), + (volatile int16 *)((Uint16)0x5EC7), + }; + int16_t sdfmAdc[8] = {0,0,0,0,0,0,0,0}; + int16_t sdfmAdcErr[8] = {0,0,0,0,0,0,0,0}; + int16_t sdfmOffset[8] = {0,0,0,0,0,-10,0,0}; + uint16_t startInitCurrent = 0; + uint16_t initDone[8] = {WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM,WAIT_STABILITY_SDFM}; + uint16_t AllInitDone =0; + uint16_t sdfmIndex = 0; + int16_t Test_I[16]; + uint16_t loopCounter[8] = {0,0,0,0,0,0,0,0}; +}; +// + inline bool Sdfm::teast_SDFM1() { + testSdfmInit(); + return true; +} + Sdfm* Sdfm::instance = NULL; + __interrupt void Sdfm1_ISR(void) { + // sdfmHandler1 + if (Sdfm::instance) { + Sdfm::instance->sdfmHandler1(); + } + } + __interrupt void Sdfm2_ISR(void) { + // sdfmHandler2 + if (Sdfm::instance) { + Sdfm::instance->sdfmHandler2(); + } + } +}} + + + + +#endif /* VOLTAGEMONITORING_SDFM_HPP_ */ diff --git a/EFC_PlatformC28x/VoltageMonitoring/SDFMController.cpp b/EFC_PlatformC28x/VoltageMonitoring/SDFMController.cpp new file mode 100644 index 0000000..dcd8ca2 --- /dev/null +++ b/EFC_PlatformC28x/VoltageMonitoring/SDFMController.cpp @@ -0,0 +1,312 @@ +/* + * SDFMController.cpp + * + * Created on: 26 ���. 2024 �. + * Author: sedov + */ + +#include "SDFMController.hpp" + + + +int16_t SdfmGetChannel(int16_t N) +{ + return sdfmAdc[N]; +} + + + +void SdfmGpioInit(void) +{ + EALLOW; + + GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(16,GPIO_MUX_CPU1,7); //SDFM-1 Channel 1 Data Input (Iu)a + GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(17,GPIO_MUX_CPU1,7); //SDFM-1 Channel 1 Clock Input + + GPIO_SetupPinOptions(22, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(22,GPIO_MUX_CPU1,7); //SDFM-1 Channel 4 Data Input (Iv)b + GPIO_SetupPinOptions(23, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(23,GPIO_MUX_CPU1,7); //SDFM-1 Channel 4 Clock Input + + GPIO_SetupPinOptions(24, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(24,GPIO_MUX_CPU1,7); //SDFM-2 Channel 1 Data Input (Iw)c + GPIO_SetupPinOptions(25, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(25,GPIO_MUX_CPU1,7); //SDFM-2 Channel 1 Clock Input + + GPIO_SetupPinOptions(58, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(58,GPIO_MUX_CPU1,7); //SDFM-2 Channel 2 Data Input (Udc) + GPIO_SetupPinOptions(59, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(59,GPIO_MUX_CPU1,7); //SDFM-2 Channel 2 Clock Input + + GPIO_SetupPinOptions(60, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(60,GPIO_MUX_CPU1,7); //SDFM-2 Channel 3 Data Input (brake) + GPIO_SetupPinOptions(61, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(61,GPIO_MUX_CPU1,7); //SDFM-2 Channel 3 Clock Input + + GPIO_SetupPinOptions(62, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(62,GPIO_MUX_CPU1,7); //SDFM-2 Channel 4 Data Input (sin) + GPIO_SetupPinOptions(63, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(63,GPIO_MUX_CPU1,7); //SDFM-2 Channel 4 Clock Input + + GPIO_SetupPinOptions(65, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(65,GPIO_MUX_CPU1,13); //SDFM-1 Channel 2 Data Input (cos) + GPIO_SetupPinOptions(66, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(66,GPIO_MUX_CPU1,13); //SDFM-1 Channel 2 Clock Input + + GPIO_SetupPinOptions(67, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(67,GPIO_MUX_CPU1,13); //SDFM-1 Channel 3 Data Input (ref) + GPIO_SetupPinOptions(68, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(68,GPIO_MUX_CPU1,13); //SDFM-1 Channel 3 Clock Input + + EDIS; +} +//��������� ������������ ������ SDFM +void SdfmInitEnable(void) +{ + EALLOW; + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; + CpuSysRegs.PCLKCR6.bit.SD1 = 1; + CpuSysRegs.PCLKCR6.bit.SD2 = 1; + EDIS; +} +void SdfmInitInterruptEn(void) +{ + EALLOW; + + PieVectTable.SDFM1_INT = &Sdfm1_ISR; // ���������� ���������� ������� ������ SDFM + PieVectTable.SDFM2_INT = &Sdfm2_ISR; // ���������� ���������� ������� ������ SDFM + // �������� ���������� ��� ������ 5 (������� SDFM1 � SDFM2) + IER |= M_INT5; + // �������� ����� ���������� ��� SDFM1 � SDFM2 + Sdfm_clearFlagRegister(SDFM1, 0xFFFFFFFF); + Sdfm_clearFlagRegister(SDFM2, 0xFFFFFFFF); + // �������� ���������� ��� SDFM1 � SDFM2 + PieCtrlRegs.PIEIER5.bit.INTx9 = 1; // SDFM1 ���������� �������� + PieCtrlRegs.PIEIER5.bit.INTx10 = 1; // SDFM2 ���������� �������� + PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + EDIS; +} + + +void SdfmInit(void) +{ + uint16_t HLT, LLT; + Sdfm_configureInputCtrl(SDFM1, FILTER1, MODE_0); + Sdfm_configureInputCtrl(SDFM1, FILTER2, MODE_0); + Sdfm_configureInputCtrl(SDFM1, FILTER3, MODE_0); + Sdfm_configureInputCtrl(SDFM1, FILTER4, MODE_0); + Sdfm_configureInputCtrl(SDFM2, FILTER1, MODE_0); + Sdfm_configureInputCtrl(SDFM2, FILTER2, MODE_0); + Sdfm_configureInputCtrl(SDFM2, FILTER3, MODE_0); + Sdfm_configureInputCtrl(SDFM2, FILTER4, MODE_0); + HLT = 0x7FFF; + LLT = 0x0000; + Sdfm_configureComparator(SDFM1, FILTER1, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM1, FILTER2, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM1, FILTER3, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM1, FILTER4, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM2, FILTER1, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM2, FILTER2, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM2, FILTER3, SINC3, OSR_32, HLT, LLT); + Sdfm_configureComparator(SDFM2, FILTER4, SINC3, OSR_32, HLT, LLT); + + Sdfm_enableMFE(SDFM1); + Sdfm_enableMFE(SDFM2); + + Sdfm_configureData_filter(SDFM1, FILTER1, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM1, FILTER2, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM1, FILTER3, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM1, FILTER4, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM2, FILTER1, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM2, FILTER2, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM2, FILTER3, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + Sdfm_configureData_filter(SDFM2, FILTER4, FILTER_DISABLE, SINC3, OSR_32, DATA_16_BIT, SHIFT_0_BITS); + + EALLOW; + +// Sdfm1Regs.SDSYNC1.bit.SYNCSEL = 0x3F; +// Sdfm2Regs.SDSYNC1.bit.SYNCSEL = 0x3F; +// Sdfm1Regs.SDSYNC2.bit.SYNCSEL = 0x3F; +// Sdfm2Regs.SDSYNC2.bit.SYNCSEL = 0x3F; +// Sdfm1Regs.SDSYNC3.bit.SYNCSEL = 0x3F; +// Sdfm2Regs.SDSYNC3.bit.SYNCSEL = 0x3F; +// Sdfm1Regs.SDSYNC4.bit.SYNCSEL = 0x3F; +// Sdfm2Regs.SDSYNC4.bit.SYNCSEL = 0x3F; + + + Sdfm1Regs.SDDFPARM1.bit.SDSYNCEN = 0; + Sdfm2Regs.SDDFPARM1.bit.SDSYNCEN = 0; + Sdfm1Regs.SDDFPARM2.bit.SDSYNCEN = 0; + Sdfm2Regs.SDDFPARM2.bit.SDSYNCEN = 0; + Sdfm1Regs.SDDFPARM3.bit.SDSYNCEN = 0; + Sdfm2Regs.SDDFPARM3.bit.SDSYNCEN = 0; + Sdfm1Regs.SDDFPARM4.bit.SDSYNCEN = 0; + Sdfm2Regs.SDDFPARM4.bit.SDSYNCEN = 0; + EDIS; + + +// Sdfm_configureInterrupt(SDFM1, FILTER1, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); +// Sdfm_configureInterrupt(SDFM1, FILTER2, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); +// Sdfm_configureInterrupt(SDFM1, FILTER3, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); +// Sdfm_configureInterrupt(SDFM1, FILTER4, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); +//// +// Sdfm_configureInterrupt(SDFM2, FILTER1, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); +// Sdfm_configureInterrupt(SDFM2, FILTER2, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); +// Sdfm_configureInterrupt(SDFM2, FILTER3, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); +// Sdfm_configureInterrupt(SDFM2, FILTER4, IEH_DISABLE, IEL_DISABLE, MFIE_ENABLE, AE_ENABLE); + + + //Sdfm1Regs.SDCPARM4.bit.MFIE = 1; + //Sdfm1Regs.SDDFPARM4.bit.AE = 1; + Sdfm_enableMIE(SDFM1); + Sdfm_enableMIE(SDFM2); + + EALLOW; + Sdfm1Regs.SDDFPARM1.bit.FEN = 1; + Sdfm1Regs.SDDFPARM2.bit.FEN = 1; + Sdfm1Regs.SDDFPARM3.bit.FEN = 1; + Sdfm1Regs.SDDFPARM4.bit.FEN = 1; + Sdfm2Regs.SDDFPARM1.bit.FEN = 1; + Sdfm2Regs.SDDFPARM2.bit.FEN = 1; + Sdfm2Regs.SDDFPARM3.bit.FEN = 1; + Sdfm2Regs.SDDFPARM4.bit.FEN = 1; + EDIS; +} + +void sdfmGetResult(uint16_t N) +{ + uint16_t i = 0; + int32_t OffsetCount = 0; + +// Gpio4out(1); + // ��������� ������ �� SDFM-������ � ��������� � ����� FilterResult + FilterResult[N][loopCounter[N]] = *SdfmReadData[N]; + // ��������� �������� ADC, ������� �������� + sdfmAdc[N] = FilterResult[N][loopCounter[N]] - sdfmOffset[N]; + if(N != SDFM_U_DC) {//���� ���������� + if(loopCounter[N] < MAX_SAMPLES) + loopCounter[N]++; + else + { + loopCounter[N] = 0; + if(!initDone[N])//���� �� ����������� ���������� ����� + { + // ��������� �������� ��� SDFM-������, �������� ���������� ���������� + for(i = 0; i <= (MAX_SAMPLES-1); i++) OffsetCount += FilterResult[N][i]; + sdfmOffset[N] = OffsetCount>>FILTER_BIT; + // ������������� ���� initDone[N] � 0xFF, ����� ��������������� �� ��������� ������������� ������ ����� + initDone[N] = 0xFF; + } + // ���� ���� initDone[N] �� ����� 0xFF, ��������� ��� �������� �� 1. + else if(initDone[N] != 0xFF) initDone[N]--; + } + } + EALLOW; + //���������� ���������� + SDCPARM_Reg_arr[N]->bit.MFIE = 1; + SDDFPARM_Reg_arr[N]->bit.AE = 0; + EDIS; + // �������� ������ SDFM + sdfmAdcErr[N] = 0; + +// Gpio4out(0); + +// if(N == SDFM_IA) Gpio54out(0); +// if(N == SDFM_IB) Gpio55out(0); +// if(N == SDFM_IC) Gpio56out(0); +} + +// ������� ������������� ������ �� ������ ������ SDFM +void sdfmErr(uint16_t N) +{ //���������� �������� � ADC SDFM + sdfmAdc[N] = 0; + EALLOW; + //��������� ���������� �� ������ SDFM + SDCPARM_Reg_arr[N]->bit.MFIE = 0; + EDIS; + // ������������� ���� ������ ��� ������ N + sdfmAdcErr[N] = 1; +} + +//������� ���������� �������� �������� �� ���� SDFM �������. +void sdfm_check_all_current_measurements_was_done(void) +{ + if((sdfmIndex & SDFM_ALL_CURRENTS) == SDFM_ALL_CURRENTS)//���� ��� SDFM ������ ������ � ���������� + { + sdfmIndex = 0; + if(!AllInitDone)// + { + if((initDone[SDFM_IA] == 0xFF)&&(initDone[SDFM_IB] == 0xFF)&&(initDone[SDFM_IC] == 0xFF)) AllInitDone = 1; + } + else + { + // vectorControl(sdfmAdc[SDFM_IA],sdfmAdc[SDFM_IB],sdfmAdc[SDFM_IC],sdfmAdc[SDFM_U_DC]); ���������� + } + } +} + +//������������ ���������� �� ������� ������ SDFM +__interrupt void Sdfm1_ISR(void) +{ + // ��������� ���������� ��� �������� ������� � ������ ���������� +uint16_t i; +uint32_t IntFlags; + // ��������� ����� ���������� �� ������ SDFM1 + IntFlags = Sdfm_readFlagRegister(SDFM1); + // ��������� ������ sdfmIndex, ��������� ����� ���������� + sdfmIndex |= (IntFlags & 0xF000)>>12; + + for(i = 0; i < 4; i++) if((uint16_t)IntFlags & (0x1000 << i)) sdfmGetResult(i);//������� ���������� ���� ���� ��������� ������ + for(i = 0; i < 4; i++) if((uint16_t)IntFlags & (0x100 << i)) sdfmErr(i);// ������������� ������� ���� ���� ��������� ������ + //���������� ����������. + Sdfm_clearFlagRegister(SDFM1,IntFlags); + // �������� ���������� �������� �������� �� ���� SDFM �������. + sdfm_check_all_current_measurements_was_done(); + // ������������ ���������� + PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; +} + + +//������������ ���������� �� ������� ������ SDFM +__interrupt void Sdfm2_ISR(void) +{ +uint16_t i; +uint32_t IntFlags; + + IntFlags = Sdfm_readFlagRegister(SDFM2); + sdfmIndex |= (IntFlags & 0xF000)>>8; + + for(i = 0; i < 4; i++) if((uint16_t)IntFlags & (0x1000 << i)) sdfmGetResult(i+4); + for(i = 0; i < 4; i++) if((uint16_t)IntFlags & (0x100 << i)) sdfmErr(i+4); + + Sdfm_clearFlagRegister(SDFM2,IntFlags); + sdfm_check_all_current_measurements_was_done(); + PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; +} + +void sdfm_start_conversion_current(void) +{ + sdfmIndex = 0; + + EALLOW; + // ������� ������ ���������� � ������� SDFM1 � SDFM2 + Sdfm1Regs.SDIFLGCLR.all = 0xFFFFFFFF; + Sdfm2Regs.SDIFLGCLR.all = 0xFFFFFFFF; + //��������� ����������� �� ������� sdfm + SDCPARM_Reg_arr[SDFM_IA]->bit.MFIE = 1; + SDDFPARM_Reg_arr[SDFM_IA]->bit.AE = 1; + SDCPARM_Reg_arr[SDFM_IB]->bit.MFIE = 1; + SDDFPARM_Reg_arr[SDFM_IB]->bit.AE = 1; + SDCPARM_Reg_arr[SDFM_IC]->bit.MFIE = 1; + SDDFPARM_Reg_arr[SDFM_IC]->bit.AE = 1; + SDCPARM_Reg_arr[SDFM_U_DC]->bit.MFIE = 1; + SDDFPARM_Reg_arr[SDFM_U_DC]->bit.AE = 1; + EDIS; +} +int16_t sdfm_get(int16_t N) +{ + return sdfmAdc[N]; +} + diff --git a/EFC_PlatformC28x/VoltageMonitoring/SDFMController.hpp b/EFC_PlatformC28x/VoltageMonitoring/SDFMController.hpp new file mode 100644 index 0000000..3a60b7d --- /dev/null +++ b/EFC_PlatformC28x/VoltageMonitoring/SDFMController.hpp @@ -0,0 +1,149 @@ +/* + * SDFMController.hpp + * + * Created on: 26 ���. 2024 �. + * Author: sedov + */ + +#ifndef VOLTAGEMONITORING_SDFMCONTROLLER_HPP_ +#define VOLTAGEMONITORING_SDFMCONTROLLER_HPP_ + + +#include +#include "f28x_project.h" +#include "f2838x_struct.h" +#include "f2838x_sdfm_drivers.h" + + + void SdfmGpioInit(); + + +#define SDFM_IA 0//16, 17 +#define SDFM_IB 3//22, 23 +#define SDFM_IC 4//24, 25 + +#define SDFM_BRAKE 6//60, 61 +#define SDFM_U_DC 5//58, 59 + +#define SDFM_SIN 7//62, 63 +#define SDFM_COS 1//65, 66 + +#define SDFM_REF 2//67, 68 + +#define SDFM_BIT_IA (1<> 8):(adcOffsetTrim & 0xFF); + } + else + { + adcOffsetTrim = 0; + } + + // + // Apply the resolution and signalmode to the specified ADC. + // Also apply the offset trim and, if needed, linearity trim correction. + // + switch(adc) + { + case ADC_ADCA: + { + AdcaRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + if(adcOffsetTrim > 0x0) + { + AdcaRegs.ADCOFFTRIM.all = adcOffsetTrim; + } +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcaRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + // 12-bit linearity trim workaround + // + AdcaRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcaRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCB: + { + AdcbRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + if(adcOffsetTrim > 0x0) + { + AdcbRegs.ADCOFFTRIM.all = adcOffsetTrim; + } +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcbRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + // 12-bit linearity trim workaround + // + AdcbRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcbRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCC: + { + AdccRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + if(adcOffsetTrim > 0x0) + { + AdccRegs.ADCOFFTRIM.all = adcOffsetTrim; + } +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdccRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + // 12-bit linearity trim workaround + // + AdccRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdccRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCD: + { + AdcdRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + if(adcOffsetTrim > 0x0) + { + AdcdRegs.ADCOFFTRIM.all = adcOffsetTrim; + } +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcdRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + // 12-bit linearity trim workaround + // + AdcdRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcdRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + } +} + +// +// CalAdcINL - Loads INL trim values from OTP into the trim registers of the +// specified ADC. Use only as part of AdcSetMode function, since +// linearity trim correction is needed for some modes. +// +void CalAdcINL(Uint16 adc) +{ + volatile Uint32 *inlRegBaseAddr, *inlOTPBaseAddr; + Uint32 i; + + switch(adc) + { + case ADC_ADCA: + // + // Pointer to ADCA trim address base + // + inlRegBaseAddr = &AdcaRegs.ADCINLTRIM1; + break; + case ADC_ADCB: + // + // Pointer to ADCB trim address + // + inlRegBaseAddr = &AdcbRegs.ADCINLTRIM1; + break; + case ADC_ADCC: + // + // Pointer to ADCC trim address + // + inlRegBaseAddr = &AdccRegs.ADCINLTRIM1; + break; + case ADC_ADCD: + // + // Pointer to ADCD trim address + // + inlRegBaseAddr = &AdcdRegs.ADCINLTRIM1; + break; + } + + // + // OTP trim location for ADC + // + inlOTPBaseAddr = GetAdcINLTrimOTPLoc(adc); + + // + // Populate INL Trim Codes 1 to 6 for respective ADC + // + if(TI_OTP_DEV_PRG_KEY_BF == TI_OTP_DEV_KEY_BF) + { + for(i = 0; i < 6; i++) + { + *inlRegBaseAddr++ = *inlOTPBaseAddr++; + } + } +} + +// +// End of file +// diff --git a/EFC_PlatformC28x/lib/f2838x_codestartbranch.asm b/EFC_PlatformC28x/lib/f2838x_codestartbranch.asm new file mode 100644 index 0000000..df7a0e3 --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_codestartbranch.asm @@ -0,0 +1,112 @@ +;//########################################################################### +;// +;// FILE: f2838x_codestartbranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example F2838x projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// +;// +;// $Copyright: +;// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + +*********************************************************************** + +WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + .retain + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot._asm in RTS library + .endif + +;end codestart section + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot._asm in RTS library + + .endif + +;end wd_disable + + .end + +;// +;// End of file. +;// diff --git a/EFC_PlatformC28x/lib/f2838x_defaultisr.c b/EFC_PlatformC28x/lib/f2838x_defaultisr.c new file mode 100644 index 0000000..0a9c44f --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_defaultisr.c @@ -0,0 +1,4635 @@ +//########################################################################### +// +// FILE: f2838x_defaultisr.c +// +// TITLE: f2838x Device Default Interrupt Service Routines +// +//########################################################################### +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" // f2838x Header File Include File +#include "f2838x_examples.h" // f2838x Examples Include File + +// +// CPU Timer 1 Interrupt +// +interrupt void TIMER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// CPU Timer 2 Interrupt +// +interrupt void TIMER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Datalogging Interrupt +// +interrupt void DATALOG_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// RTOS Interrupt +// +interrupt void RTOS_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Emulation Interrupt +// +interrupt void EMU_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Non-Maskable Interrupt +// +interrupt void NMI_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Illegal Operation Trap +// +interrupt void ILLEGAL_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 1 +// +interrupt void USER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 2 +// +interrupt void USER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 3 +// +interrupt void USER3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 4 +// +interrupt void USER4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 5 +// +interrupt void USER5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 6 +// +interrupt void USER6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 7 +// +interrupt void USER7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 8 +// +interrupt void USER8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 9 +// +interrupt void USER9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 10 +// +interrupt void USER10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 11 +// +interrupt void USER11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 12 +// +interrupt void USER12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.1 - ADCA Interrupt 1 +// +interrupt void ADCA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.2 - ADCB Interrupt 1 +// +interrupt void ADCB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.3 - ADCC Interrupt 1 +// +interrupt void ADCC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.4 - XINT1 Interrupt +// +interrupt void XINT1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.5 - XINT2 Interrupt +// +interrupt void XINT2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.6 - ADCD Interrupt 1 +// +interrupt void ADCD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.7 - Timer 0 Interrupt +// +interrupt void TIMER0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.8 - Standby and Halt Wakeup Interrupt +// +interrupt void WAKE_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.1 - ePWM1 Trip Zone Interrupt +// +interrupt void EPWM1_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.2 - ePWM2 Trip Zone Interrupt +// +interrupt void EPWM2_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.3 - ePWM3 Trip Zone Interrupt +// +interrupt void EPWM3_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.4 - ePWM4 Trip Zone Interrupt +// +interrupt void EPWM4_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.5 - ePWM5 Trip Zone Interrupt +// +interrupt void EPWM5_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.6 - ePWM6 Trip Zone Interrupt +// +interrupt void EPWM6_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.7 - ePWM7 Trip Zone Interrupt +// +interrupt void EPWM7_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.8 - ePWM8 Trip Zone Interrupt +// +interrupt void EPWM8_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.1 - ePWM1 Interrupt +// +interrupt void EPWM1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.2 - ePWM2 Interrupt +// +interrupt void EPWM2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.3 - ePWM3 Interrupt +// +interrupt void EPWM3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.4 - ePWM4 Interrupt +// +interrupt void EPWM4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.5 - ePWM5 Interrupt +// +interrupt void EPWM5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.6 - ePWM6 Interrupt +// +interrupt void EPWM6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.7 - ePWM7 Interrupt +// +interrupt void EPWM7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.8 - ePWM8 Interrupt +// +interrupt void EPWM8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.1 - eCAP1 Interrupt +// +interrupt void ECAP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.2 - eCAP2 Interrupt +// +interrupt void ECAP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.3 - eCAP3 Interrupt +// +interrupt void ECAP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.4 - eCAP4 Interrupt +// +interrupt void ECAP4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.5 - eCAP5 Interrupt +// +interrupt void ECAP5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.6 - eCAP6 Interrupt +// +interrupt void ECAP6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.7 - eCAP7 Interrupt +// +interrupt void ECAP7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.1 - eQEP1 Interrupt +// +interrupt void EQEP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.2 - eQEP2 Interrupt +// +interrupt void EQEP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.3 - eQEP3 Interrupt +// +interrupt void EQEP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.5 - CLB1 (Reconfigurable Logic) Interrupt +// +interrupt void CLB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.6 - CLB2 (Reconfigurable Logic) Interrupt +// +interrupt void CLB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.7 - CLB3 (Reconfigurable Logic) Interrupt +// +interrupt void CLB3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.8 - CLB4 (Reconfigurable Logic) Interrupt +// +interrupt void CLB4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.1 - SPIA Receive Interrupt +// +interrupt void SPIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.2 - SPIA Transmit Interrupt +// +interrupt void SPIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.3 - SPIB Receive Interrupt +// +interrupt void SPIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.4 - SPIB Transmit Interrupt +// +interrupt void SPIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.5 - McBSPA Receive Interrupt +// +interrupt void MCBSPA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.6 - McBSPA Transmit Interrupt +// +interrupt void MCBSPA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.7 - McBSPB Receive Interrupt +// +interrupt void MCBSPB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.8 - McBSPB Transmit Interrupt +// +interrupt void MCBSPB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.1 - DMA Channel 1 Interrupt +// +interrupt void DMA_CH1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.2 - DMA Channel 2 Interrupt +// +interrupt void DMA_CH2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.3 - DMA Channel 3 Interrupt +// +interrupt void DMA_CH3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.4 - DMA Channel 4 Interrupt +// +interrupt void DMA_CH4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.5 - DMA Channel 5 Interrupt +// +interrupt void DMA_CH5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.6 - DMA Channel 6 Interrupt +// +interrupt void DMA_CH6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.1 - I2CA Interrupt 1 +// +interrupt void I2CA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.2 - I2CA Interrupt 2 +// +interrupt void I2CA_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.3 - I2CB Interrupt 1 +// +interrupt void I2CB_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.4 - I2CB Interrupt 2 +// +interrupt void I2CB_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.5 - SCIC Receive Interrupt +// +interrupt void SCIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.6 - SCIC Transmit Interrupt +// +interrupt void SCIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.7 - SCID Receive Interrupt +// +interrupt void SCID_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.8 - SCID Transmit Interrupt +// +interrupt void SCID_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.1 - SCIA Receive Interrupt +// +interrupt void SCIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.2 - SCIA Transmit Interrupt +// +interrupt void SCIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.3 - SCIB Receive Interrupt +// +interrupt void SCIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.4 - SCIB Transmit Interrupt +// +interrupt void SCIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.5 - CANA Interrupt 0 +// +interrupt void CANA0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.6 - CANA Interrupt 1 +// +interrupt void CANA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.7 - CANB Interrupt 0 +// +interrupt void CANB0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.8 - CANB Interrupt 1 +// +interrupt void CANB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.1 - ADCA Event Interrupt +// +interrupt void ADCA_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.2 - ADCA Interrupt 2 +// +interrupt void ADCA2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.3 - ADCA Interrupt 3 +// +interrupt void ADCA3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.4 - ADCA Interrupt 4 +// +interrupt void ADCA4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.5 - ADCB Event Interrupt +// +interrupt void ADCB_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.6 - ADCB Interrupt 2 +// +interrupt void ADCB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.7 - ADCB Interrupt 3 +// +interrupt void ADCB3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.8 - ADCB Interrupt 4 +// +interrupt void ADCB4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.1 - CLA1 Interrupt 1 +// +interrupt void CLA1_1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.2 - CLA1 Interrupt 2 +// +interrupt void CLA1_2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.3 - CLA1 Interrupt 3 +// +interrupt void CLA1_3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.4 - CLA1 Interrupt 4 +// +interrupt void CLA1_4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.5 - CLA1 Interrupt 5 +// +interrupt void CLA1_5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.6 - CLA1 Interrupt 6 +// +interrupt void CLA1_6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.7 - CLA1 Interrupt 7 +// +interrupt void CLA1_7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.8 - CLA1 Interrupt 8 +// +interrupt void CLA1_8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.1 - XINT3 Interrupt +// +interrupt void XINT3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.2 - XINT4 Interrupt +// +interrupt void XINT4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.3 - XINT5 Interrupt +// +interrupt void XINT5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.4 - MPOST Interrupt +// +interrupt void MPOST_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.5 - Flash Wrapper Operation Done Interrupt +// +interrupt void FMC_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.7 - FPU Overflow Interrupt +// +interrupt void FPU_OFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.8 - FPU Underflow Interrupt +// +interrupt void FPU_UFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.9 - I2CA Interrupt high priority +// +interrupt void I2CA_HIGH_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.10 - System error interrupt +// +interrupt void SYS_ERR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.11 - ETHERCAT SYNC0 interrupt +// +interrupt void ECATSYNC0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.12 - ETHERCAT main interrupt +// +interrupt void ECAT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.13 - C28x CPU IPC interrupt 1 +// +interrupt void CIPC0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.14 - C28x CPU IPC interrupt 2 +// +interrupt void CIPC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.15 - C28x CPU IPC interrupt 3 +// +interrupt void CIPC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.16 - C28x CPU IPC interrupt 4 +// +interrupt void CIPC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.9 - ePWM9 Trip Zone Interrupt +// +interrupt void EPWM9_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.10 - ePWM10 Trip Zone Interrupt +// +interrupt void EPWM10_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.11 - ePWM11 Trip Zone Interrupt +// +interrupt void EPWM11_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.12 - ePWM12 Trip Zone Interrupt +// +interrupt void EPWM12_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.13 - ePWM13 Trip Zone Interrupt +// +interrupt void EPWM13_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.14 - ePWM14 Trip Zone Interrupt +// +interrupt void EPWM14_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.15 - ePWM15 Trip Zone Interrupt +// +interrupt void EPWM15_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.16 - ePWM16 Trip Zone Interrupt +// +interrupt void EPWM16_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.9 - ePWM9 Interrupt +// +interrupt void EPWM9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.10 - ePWM10 Interrupt +// +interrupt void EPWM10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.11 - ePWM11 Interrupt +// +interrupt void EPWM11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.12 - ePWM12 Interrupt +// +interrupt void EPWM12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.13 - ePWM13 Interrupt +// +interrupt void EPWM13_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.14 - ePWM14 Interrupt +// +interrupt void EPWM14_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.15 - ePWM15 Interrupt +// +interrupt void EPWM15_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.16 - ePWM16 Interrupt +// +interrupt void EPWM16_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.9 - FSIA Transmit interrupt 1 +// +interrupt void FSITXA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.10 - FSIA Transmit interrupt 2 +// +interrupt void FSITXA2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.11 - FSIB Transmit interrupt 1 +// +interrupt void FSITXB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.12 - FSIB Transmit interrupt 2 +// +interrupt void FSITXB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.13 - FSIA Receive interrupt 1 +// +interrupt void FSIRXA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.14 - FSIA Receive interrupt 2 +// +interrupt void FSIRXA2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.15 - FSIB Receive interrupt 1 +// +interrupt void FSIRXB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.16 - FSIB Receive interrupt 2 +// +interrupt void FSIRXB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.9 - Sigma Delta Filter Module1 Interrupt +// +interrupt void SDFM1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.10 - Sigma Delta Filter Module2 Interrupt +// +interrupt void SDFM2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.11 - ETHERCAT Resetout Interrupt +// +interrupt void ECATRST_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.12 - ETHERCAT SYNC1 interrupt +// +interrupt void ECATSYNC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.13 - Sigma Delta Filter Module1 Filter 1 Interrupt +// +interrupt void SDFM1DR1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.14 - Sigma Delta Filter Module1 Filter 2 Interrupt +// +interrupt void SDFM1DR2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.15 - Sigma Delta Filter Module1 Filter 3 Interrupt +// +interrupt void SDFM1DR3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.16 - Sigma Delta Filter Module1 Filter 4 Interrupt +// +interrupt void SDFM1DR4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.9 - SPIC Receive Interrupt +// +interrupt void SPIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.10 - SPIC Transmit Interrupt +// +interrupt void SPIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.11 - SPID Receive Interrupt +// +interrupt void SPID_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.12 - SPID Transmit Interrupt +// +interrupt void SPID_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.13 - Sigma Delta Filter Module2 Filter 1 Interrupt +// +interrupt void SDFM2DR1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.14 - Sigma Delta Filter Module2 Filter 2 Interrupt +// +interrupt void SDFM2DR2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.15 - Sigma Delta Filter Module2 Filter 3 Interrupt +// +interrupt void SDFM2DR3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.16 - Sigma Delta Filter Module2 Filter 4 Interrupt +// +interrupt void SDFM2DR4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.9 - FSIC Receive interrupt 1 +// +interrupt void FSIRXC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.10 - FSIC Receive interrupt 2 +// +interrupt void FSIRXC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.11 - FSID Receive interrupt 1 +// +interrupt void FSIRXD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.12 - FSID Receive interrupt 2 +// +interrupt void FSIRXD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.13 - FSIE Receive interrupt 1 +// +interrupt void FSIRXE1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.14 - FSIE Receive interrupt 2 +// +interrupt void FSIRXE2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.15 - FSIF Receive interrupt 1 +// +interrupt void FSIRXF1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.16 - FSIF Receive interrupt 2 +// +interrupt void FSIRXF2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.9 - FSIG Receive interrupt 1 +// +interrupt void FSIRXG1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.10 - FSIG Receive interrupt 2 +// +interrupt void FSIRXG2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.11 - FSIH Receive interrupt 1 +// +interrupt void FSIRXH1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.12 - FSIH Receive interrupt 2 +// +interrupt void FSIRXH2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.13 - CLB5 Interrupt +// +interrupt void CLB5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.14 - CLB6 Interrupt +// +interrupt void CLB6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.15 - CLB7 Interrupt +// +interrupt void CLB7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.16 - CLB8 Interrupt +// +interrupt void CLB8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.9 - MCAN Sub-System Interrupt 0 +// +interrupt void MCANA_0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.10 - MCAN Sub-System Interrupt 1 +// +interrupt void MCANA_1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.11 - MCAN Sub-System ECC error Interrupt +// +interrupt void MCANA_ECC_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.12 - MCAN Sub-System wakeup Interrupt +// +interrupt void MCANA_WAKE_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.13 - PMBUSA Interrupt +// +interrupt void PMBUSA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.14 - CM Reset Status Interrupt +// +interrupt void CM_STATUS_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.15 - USBA Interrupt +// +interrupt void USBA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.9 - ADCC Event Interrupt +// +interrupt void ADCC_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.10 - ADCC Interrupt 2 +// +interrupt void ADCC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.11 - ADCC Interrupt 3 +// +interrupt void ADCC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.12 - ADCC Interrupt 4 +// +interrupt void ADCC4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.13 - ADCD Event Interrupt +// +interrupt void ADCD_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.14 - ADCD Interrupt 2 +// +interrupt void ADCD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.15 - ADCD Interrupt 3 +// +interrupt void ADCD3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.16 - ADCD Interrupt 4 +// +interrupt void ADCD4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.9 - CM to CPU IPC Interrupt 0 +// +interrupt void CMTOCPUXIPC0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.10 - CM to CPU IPC Interrupt 1 +// +interrupt void CMTOCPUXIPC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.11 - CM to CPU IPC Interrupt 2 +// +interrupt void CMTOCPUXIPC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.12 - CM to CPU IPC Interrupt 3 +// +interrupt void CMTOCPUXIPC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.13 - CM to CPU IPC Interrupt 4 +// +interrupt void CMTOCPUXIPC4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.14 - CM to CPU IPC Interrupt 5 +// +interrupt void CMTOCPUXIPC5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.15 - CM to CPU IPC Interrupt 6 +// +interrupt void CMTOCPUXIPC6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.16 - CM to CPU IPC Interrupt 7 +// +interrupt void CMTOCPUXIPC7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.10 - eCAP6 Interrupt 2 +// +interrupt void ECAP6_2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.11 - eCAP7 Interrupt 2 +// +interrupt void ECAP7_2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.13 - CPU BGCRC module interrupt +// +interrupt void CPUCRC_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.14 - CLA1 BGCRC module interrupt +// +interrupt void CLA1CRC_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.15 - CLA Overflow Interrupt +// +interrupt void CLA_OVERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.16 - CLA Underflow Interrupt +// +interrupt void CLA_UNDERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Catch-all Default ISRs: +// + +// +// PIE_RESERVED_ISR - Reserved ISR +// +interrupt void PIE_RESERVED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// EMPTY_ISR - Only does a return +// +interrupt void EMPTY_ISR(void) +{ + +} + +// +// NOTUSED_ISR - Unused ISR +// +interrupt void NOTUSED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// End of File +// + diff --git a/EFC_PlatformC28x/lib/f2838x_epwm.c b/EFC_PlatformC28x/lib/f2838x_epwm.c new file mode 100644 index 0000000..596cc39 --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_epwm.c @@ -0,0 +1,666 @@ +//########################################################################### +// +// FILE: f2838x_epwm.c +// +// TITLE: F2838x EPwm Initialization & Support Functions. +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" +#include "f2838x_examples.h" + +// +// InitEPwmGpio - Initialize all EPWM modules' GPIOs +// +void InitEPwmGpio(void) +{ + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + InitEPwm5Gpio(); + InitEPwm6Gpio(); + InitEPwm7Gpio(); + InitEPwm8Gpio(); + InitEPwm9Gpio(); + InitEPwm10Gpio(); + InitEPwm11Gpio(); + InitEPwm12Gpio(); + InitEPwm13Gpio(); + InitEPwm14Gpio(); + InitEPwm15Gpio(); + InitEPwm16Gpio(); +} + +// +// InitEPwm1Gpio - Initialize EPWM1 GPIOs +// +void InitEPwm1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B) +// GpioCtrlRegs.GPEPUD.bit.GPIO145 = 1; // Disable pull-up on GPIO145 (EPWM1A) +// GpioCtrlRegs.GPEPUD.bit.GPIO146 = 1; // Disable pull-up on GPIO146 (EPWM1B) + + // + // Configure EPWM-1 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM1 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B +// GpioCtrlRegs.GPEMUX2.bit.GPIO145 = 1; // Configure GPIO145 as EPWM1A +// GpioCtrlRegs.GPEMUX2.bit.GPIO146 = 1; // Configure GPIO0146 as EPWM1B + + EDIS; +} + +// +// InitEPwm2Gpio - Initialize EPWM2 GPIOs +// +void InitEPwm2Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B) + +// GpioCtrlRegs.GPEPUD.bit.GPIO147 = 1; // Disable pull-up on GPIO147 (EPWM2A) +// GpioCtrlRegs.GPEPUD.bit.GPIO148 = 1; // Disable pull-up on GPIO148 (EPWM2B) + + // + // Configure EPwm-2 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM2 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B +// GpioCtrlRegs.GPEMUX2.bit.GPIO147 = 1; // Configure GPIO147 as EPWM2A +// GpioCtrlRegs.GPEMUX2.bit.GPIO148 = 1; // Configure GPIO148 as EPWM2B + + GpioCtrlRegs.GPACSEL1.bit.GPIO2 = 2;//to cpu2 + GpioCtrlRegs.GPACSEL1.bit.GPIO3 = 2; + + EDIS; +} + +// +// InitEPwm3Gpio - Initialize EPWM3 GPIOs +// +void InitEPwm3Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B) +// GpioCtrlRegs.GPEPUD.bit.GPIO149 = 1; // Disable pull-up on GPIO149 (EPWM3A) +// GpioCtrlRegs.GPEPUD.bit.GPIO150 = 1; // Disable pull-up on GPIO150 (EPWM3B) + + // + // Configure EPwm-3 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM3 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B +// GpioCtrlRegs.GPEMUX2.bit.GPIO149 = 1; // Configure GPIO149 as EPWM3A +// GpioCtrlRegs.GPEMUX2.bit.GPIO150 = 1; // Configure GPIO150 as EPWM3B + GpioCtrlRegs.GPACSEL1.bit.GPIO4 = 2;//to cpu2 + GpioCtrlRegs.GPACSEL1.bit.GPIO5 = 2; + + EDIS; +} + +// +// InitEPwm4Gpio - Initialize EPWM4 GPIOs +// +void InitEPwm4Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B) +// GpioCtrlRegs.GPEPUD.bit.GPIO151 = 1; // Disable pull-up on GPIO151 (EPWM4A) +// GpioCtrlRegs.GPEPUD.bit.GPIO152 = 1; // Disable pull-up on GPIO152 (EPWM4B) + + // + // Configure EPWM-4 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM4 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B +// GpioCtrlRegs.GPEMUX2.bit.GPIO151 = 1; // Configure GPIO151 as EPWM4A +// GpioCtrlRegs.GPEMUX2.bit.GPIO152 = 1; // Configure GPIO152 as EPWM4B + GpioCtrlRegs.GPACSEL1.bit.GPIO6 = 2;//to cpu2 + GpioCtrlRegs.GPACSEL1.bit.GPIO7 = 2; + + EDIS; +} + +// +// InitEPwm5Gpio - Initialize EPWM5 GPIOs +// +void InitEPwm5Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A) + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EPWM5B) +// GpioCtrlRegs.GPEPUD.bit.GPIO153 = 1; // Disable pull-up on GPIO153 (EPWM5A) +// GpioCtrlRegs.GPEPUD.bit.GPIO154 = 1; // Disable pull-up on GPIO154 (EPWM5B) + + // + // Configure EPWM-5 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM5 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B +// GpioCtrlRegs.GPEMUX2.bit.GPIO153 = 1; // Configure GPIO153 as EPWM5A +// GpioCtrlRegs.GPEMUX2.bit.GPIO154 = 1; // Configure GPIO0154 as EPWM5B + GpioCtrlRegs.GPACSEL2.bit.GPIO8 = 2;//to cpu2 + GpioCtrlRegs.GPACSEL2.bit.GPIO9 = 2; + + EDIS; +} + +// +// InitEPwm6Gpio - Initialize EPWM6 GPIOs +// +void InitEPwm6Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EPWM6B) +// GpioCtrlRegs.GPEPUD.bit.GPIO155 = 1; // Disable pull-up on GPIO155 (EPWM6A) +// GpioCtrlRegs.GPEPUD.bit.GPIO156 = 1; // Disable pull-up on GPIO156 (EPWM6B) + + // + // Configure EPWM-6 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM6 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B +// GpioCtrlRegs.GPEMUX2.bit.GPIO155 = 1; // Configure GPIO155 as EPWM6A +// GpioCtrlRegs.GPEMUX2.bit.GPIO156 = 1; // Configure GPIO156 as EPWM6B + GpioCtrlRegs.GPACSEL2.bit.GPIO10 = 2;//to cpu2 + GpioCtrlRegs.GPACSEL2.bit.GPIO11 = 2; + + EDIS; +} + +// +// InitEPwm7Gpio - Initialize EPWM7 GPIOs +// +void InitEPwm7Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EPWM7A) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EPWM7B) +// GpioCtrlRegs.GPEPUD.bit.GPIO157 = 1; // Disable pull-up on GPIO157 (EPWM7A) +// GpioCtrlRegs.GPEPUD.bit.GPIO158 = 1; // Disable pull-up on GPIO158 (EPWM7B) + + // + // Configure EPWM-7 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM7 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EPWM7A + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EPWM7B +// GpioCtrlRegs.GPEMUX2.bit.GPIO157 = 1; // Configure GPIO157 as EPWM7A +// GpioCtrlRegs.GPEMUX2.bit.GPIO158 = 1; // Configure GPIO158 as EPWM7B + GpioCtrlRegs.GPACSEL2.bit.GPIO12 = 2;//to cpu2 + GpioCtrlRegs.GPACSEL2.bit.GPIO13 = 2; + + EDIS; +} + +// +// InitEPwm8Gpio - Initialize EPWM8 GPIOs +// +void InitEPwm8Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (EPWM8A) +// GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (EPWM8B) +// GpioCtrlRegs.GPEPUD.bit.GPIO159 = 1; // Disable pull-up on GPIO159 (EPWM8A) +// GpioCtrlRegs.GPFPUD.bit.GPIO160 = 1; // Disable pull-up on GPIO160 (EPWM8B) + + // + // Configure EPWM-8 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM8 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as EPWM8A +// GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as EPWM8B +// GpioCtrlRegs.GPEMUX2.bit.GPIO159 = 1; // Configure GPIO159 as EPWM8A +// GpioCtrlRegs.GPFMUX1.bit.GPIO160 = 1; // Configure GPIO160 as EPWM8B + GpioCtrlRegs.GPACSEL2.bit.GPIO14 = 2;//to cpu2 + + + EDIS; +} + +// +// InitEPwm9Gpio - Initialize EPWM9 GPIOs +// +void InitEPwm9Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO161 = 1; // Disable pull-up on GPIO161 (EPWM9A) + GpioCtrlRegs.GPFPUD.bit.GPIO162 = 1; // Disable pull-up on GPIO162 (EPWM9B) +// GpioCtrlRegs.GPAPUD.bit.GPIO16 = 1; // Disable pull-up on GPIO16 (EPWM9A) +// GpioCtrlRegs.GPAPUD.bit.GPIO17 = 1; // Disable pull-up on GPIO17 (EPWM9B) + + // + // Configure EPWM-9 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM9 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO161 = 1; // Configure GPIO161 as EPWM9A + GpioCtrlRegs.GPFMUX1.bit.GPIO162 = 1; // Configure GPIO162 as EPWM9B + +// // +// // Alternate mapping for EPWM-9. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // Configure GPAMUX to 0 for GPIO16 +// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0; // Configure GPAMUX to 0 for GPIO17 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO16 = 1; // Configure GPAGMUX for EPWM9A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO17 = 1; // Configure GPAGMUX for EPWM9B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPAMUX for EPWM9A +// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPAMUX for EPWM9B + GpioCtrlRegs.GPBCSEL4.bit.GPIO61 = 2;//to cpu2 + GpioCtrlRegs.GPBCSEL4.bit.GPIO62 = 2; + + EDIS; +} + +// +// InitEPwm10Gpio - Initialize EPWM10 GPIOs +// +void InitEPwm10Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO163 = 1; // Disable pull-up on GPIO163 (EPWM10A) + GpioCtrlRegs.GPFPUD.bit.GPIO164 = 1; // Disable pull-up on GPIO164 (EPWM10B) +// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO18 (EPWM10A) +// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 1; // Disable pull-up on GPIO19 (EPWM10B) + + // + // Configure EPWM-10 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM10 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO163 = 1; // Configure GPIO163 as EPWM10A + GpioCtrlRegs.GPFMUX1.bit.GPIO164 = 1; // Configure GPIO164 as EPWM10B + +// // +// // Alternate mapping for EPWM-10. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; // Configure GPAMUX to 0 for GPIO18 +// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // Configure GPAMUX to 0 for GPIO19 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 1; // Configure GPAGMUX for EPWM10A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 1; // Configure GPAGMUX for EPWM10B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPAMUX for EPWM10A +// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPAMUX for EPWM10B + GpioCtrlRegs.GPBCSEL4.bit.GPIO63 = 2;//to cpu2 + GpioCtrlRegs.GPCCSEL1.bit.GPIO64 = 2; + + EDIS; +} + +// +// InitEPwm11Gpio - Initialize EPWM11 GPIOs +// +void InitEPwm11Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // +// GpioCtrlRegs.GPFPUD.bit.GPIO165 = 1; // Disable pull-up on GPIO165 (EPWM11A) +// GpioCtrlRegs.GPFPUD.bit.GPIO166 = 1; // Disable pull-up on GPIO166 (EPWM11B) + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (EPWM11A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (EPWM11B) + + // + // Configure EPWM-11 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM11 functional pins. + // Comment out other unwanted lines. + // +// GpioCtrlRegs.GPFMUX1.bit.GPIO165 = 1; // Configure GPIO165 as EPWM11A +// GpioCtrlRegs.GPFMUX1.bit.GPIO166 = 1; // Configure GPIO166 as EPWM11B + +// // +// // Alternate mapping for EPWM-11. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0; // Configure GPAMUX to 0 for GPIO20 + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0; // Configure GPAMUX to 0 for GPIO21 +// + GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 1; // Configure GPAGMUX for EPWM11A + GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 1; // Configure GPAGMUX for EPWM11B +// + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPAMUX for EPWM11A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPAMUX for EPWM11B + + GpioCtrlRegs.GPACSEL3.bit.GPIO20 = 2;//to cpu2 + GpioCtrlRegs.GPACSEL3.bit.GPIO21 = 2; + + EDIS; +} + +// +// InitEPwm12Gpio - Initialize EPWM12 GPIOs +// +void InitEPwm12Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO167 = 1; // Disable pull-up on GPIO167 (EPWM12A) + GpioCtrlRegs.GPFPUD.bit.GPIO168 = 1; // Disable pull-up on GPIO168 (EPWM12B) +// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; // Disable pull-up on GPIO22 (EPWM12A) +// GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; // Disable pull-up on GPIO23 (EPWM12B) + + // + // Configure EPWM-12 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM12 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO167 = 1; // Configure GPIO167 as EPWM12A + GpioCtrlRegs.GPFMUX1.bit.GPIO168 = 1; // Configure GPIO168 as EPWM12B + +// // +// // Alternate mapping for EPWM-12. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; // Configure GPAMUX to 0 for GPIO22 +// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0; // Configure GPAMUX to 0 for GPIO23 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO22 = 1; // Configure GPAGMUX for EPWM12A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO23 = 1; // Configure GPAGMUX for EPWM12B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPAMUX for EPWM12A +// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPAMUX for EPWM12B + + + EDIS; +} + +// +// InitEPwm13Gpio - Initialize EPWM13 GPIOs +// +void InitEPwm13Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEPUD.bit.GPIO137 = 1; // Disable pull-up on GPIO137 (EPWM13A) + GpioCtrlRegs.GPEPUD.bit.GPIO138 = 1; // Disable pull-up on GPIO138 (EPWM13B) +// GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EPWM13A) +// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EPWM13B) + + // + // Configure EPWM-13 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM13 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEMUX1.bit.GPIO137 = 1; // Configure GPIO137 as EPWM13A + GpioCtrlRegs.GPEMUX1.bit.GPIO138 = 1; // Configure GPIO138 as EPWM13B + +// // +// // Alternate mapping for EPWM-13. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 0; // Configure GPAMUX to 0 for GPIO24 +// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // Configure GPAMUX to 0 for GPIO25 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO24 = 3; // Configure GPAGMUX for EPWM13A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO25 = 3; // Configure GPAGMUX for EPWM13B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPAMUX for EPWM13A +// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPAMUX for EPWM13B + + EDIS; +} + +// +// InitEPwm14Gpio - Initialize EPWM14 GPIOs +// +void InitEPwm14Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEPUD.bit.GPIO139 = 1; // Disable pull-up on GPIO139 (EPWM14A) + GpioCtrlRegs.GPEPUD.bit.GPIO140 = 1; // Disable pull-up on GPIO140 (EPWM14B) +// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EPWM14A) +// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EPWM14B) + + // + // Configure EPWM-14 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM14 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEMUX1.bit.GPIO139 = 1; // Configure GPIO139 as EPWM14A + GpioCtrlRegs.GPEMUX1.bit.GPIO140 = 1; // Configure GPIO140 as EPWM14B + +// // +// // Alternate mapping for EPWM-14. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // Configure GPAMUX to 0 for GPIO26 +// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // Configure GPAMUX to 0 for GPIO27 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO26 = 3; // Configure GPAGMUX for EPWM14A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO27 = 3; // Configure GPAGMUX for EPWM14B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPAMUX for EPWM14A +// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPAMUX for EPWM14B + + EDIS; +} + +// +// InitEPwm15Gpio - Initialize EPWM15 GPIOs +// +void InitEPwm15Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEPUD.bit.GPIO141 = 1; // Disable pull-up on GPIO141 (EPWM15A) + GpioCtrlRegs.GPEPUD.bit.GPIO142 = 1; // Disable pull-up on GPIO142 (EPWM15B) +// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up on GPIO28 (EPWM15A) +// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1; // Disable pull-up on GPIO29 (EPWM15B) + + // + // Configure EPWM-15 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM15 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEMUX1.bit.GPIO141 = 1; // Configure GPIO141 as EPWM15A + GpioCtrlRegs.GPEMUX1.bit.GPIO142 = 1; // Configure GPIO142 as EPWM15B + +// // +// // Alternate mapping for EPWM-15. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 0; // Configure GPAMUX to 0 for GPIO28 +// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 0; // Configure GPAMUX to 0 for GPIO29 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 3; // Configure GPAGMUX for EPWM15A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 3; // Configure GPAGMUX for EPWM15B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPAMUX for EPWM15A +// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPAMUX for EPWM15B + + EDIS; +} + +// +// InitEPwm16Gpio - Initialize EPWM16 GPIOs +// +void InitEPwm16Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEPUD.bit.GPIO143 = 1; // Disable pull-up on GPIO141 (EPWM16A) + GpioCtrlRegs.GPEPUD.bit.GPIO144 = 1; // Disable pull-up on GPIO142 (EPWM16B) +// GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Disable pull-up on GPIO28 (EPWM16A) +// GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Disable pull-up on GPIO29 (EPWM16B) + + // + // Configure EPWM-16 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM16 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEMUX1.bit.GPIO143 = 1; // Configure GPIO141 as EPWM16A + GpioCtrlRegs.GPEMUX2.bit.GPIO144 = 1; // Configure GPIO142 as EPWM16B + +// // +// // Alternate mapping for EPWM-16. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches in Mux. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0; // Configure GPAMUX to 0 for GPIO30 +// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0; // Configure GPAMUX to 0 for GPIO31 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO30 = 3; // Configure GPAGMUx for EPWM16A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO31 = 3; // Configure GPAGMux for EPWM16B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPAMUx for EPWM16A +// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPAMux for EPWM16B + + EDIS; +} + +// +// End of File +// diff --git a/EFC_PlatformC28x/lib/f2838x_globalvariabledefs.c b/EFC_PlatformC28x/lib/f2838x_globalvariabledefs.c new file mode 100644 index 0000000..db5a2a5 --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_globalvariabledefs.c @@ -0,0 +1,1561 @@ +//########################################################################### +// +// FILE: f2838x_globalvariabledefs.c +// +// TITLE: f2838x Global Variables and Data Section Pragmas. +// +//########################################################################### +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "f2838x_device.h" // f2838x Headerfile Include File + +//--------------------------------------------------------------------------- +// Define Global Peripheral Variables: +// + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AccessProtectionRegsFile") +#else +#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile"); +#endif +volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaRegsFile") +#else +#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile"); +#endif +volatile struct ADC_REGS AdcaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbRegsFile") +#else +#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile"); +#endif +volatile struct ADC_REGS AdcbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdccRegsFile") +#else +#pragma DATA_SECTION(AdccRegs,"AdccRegsFile"); +#endif +volatile struct ADC_REGS AdccRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdRegsFile") +#else +#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile"); +#endif +volatile struct ADC_REGS AdcdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaResultRegsFile") +#else +#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultRegsFile"); +#endif +volatile struct ADC_RESULT_REGS AdcaResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbResultRegsFile") +#else +#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultRegsFile"); +#endif +volatile struct ADC_RESULT_REGS AdcbResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdccResultRegsFile") +#else +#pragma DATA_SECTION(AdccResultRegs,"AdccResultRegsFile"); +#endif +volatile struct ADC_RESULT_REGS AdccResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdResultRegsFile") +#else +#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultRegsFile"); +#endif +volatile struct ADC_RESULT_REGS AdcdResultRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AnalogSubsysRegsFile") +#else +#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile"); +#endif +volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("BgcrcCpuRegsFile") +#else +#pragma DATA_SECTION(BgcrcCpuRegs,"BgcrcCpuRegsFile"); +#endif +volatile struct BGCRC_REGS BgcrcCpuRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("BgcrcCla1RegsFile") +#else +#pragma DATA_SECTION(BgcrcCla1Regs,"BgcrcCla1RegsFile"); +#endif +volatile struct BGCRC_REGS BgcrcCla1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanaRegsFile") +#else +#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); +#endif +volatile struct CAN_REGS CanaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanbRegsFile") +#else +#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); +#endif +volatile struct CAN_REGS CanbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cla1RegsFile") +#else +#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); +#endif +volatile struct CLA_REGS Cla1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb1DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb1DataExchRegs,"Clb1DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb1DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb2DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb2DataExchRegs,"Clb2DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb2DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb3DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb3DataExchRegs,"Clb3DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb3DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb4DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb4DataExchRegs,"Clb4DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb4DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb5DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb5DataExchRegs,"Clb5DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb5DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb6DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb6DataExchRegs,"Clb6DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb6DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb7DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb7DataExchRegs,"Clb7DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb7DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb8DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb8DataExchRegs,"Clb8DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb8DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb1LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb1LogicCfgRegs,"Clb1LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb1LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb2LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb2LogicCfgRegs,"Clb2LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb2LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb3LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb3LogicCfgRegs,"Clb3LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb3LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb4LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb4LogicCfgRegs,"Clb4LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb4LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb5LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb5LogicCfgRegs,"Clb5LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb5LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb6LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb6LogicCfgRegs,"Clb6LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb6LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb7LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb7LogicCfgRegs,"Clb7LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb7LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb8LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb8LogicCfgRegs,"Clb8LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb8LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb1LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb1LogicCtrlRegs,"Clb1LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb1LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb2LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb2LogicCtrlRegs,"Clb2LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb2LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb3LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb3LogicCtrlRegs,"Clb3LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb3LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb4LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb4LogicCtrlRegs,"Clb4LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb4LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb5LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb5LogicCtrlRegs,"Clb5LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb5LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb6LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb6LogicCtrlRegs,"Clb6LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb6LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb7LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb7LogicCtrlRegs,"Clb7LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb7LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb8LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb8LogicCtrlRegs,"Clb8LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb8LogicCtrlRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CLBXbarRegsFile") +#else +#pragma DATA_SECTION(CLBXbarRegs,"CLBXbarRegsFile"); +#endif +volatile struct CLB_XBAR_REGS CLBXbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClkCfgRegsFile") +#else +#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); +#endif +volatile struct CLK_CFG_REGS ClkCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss1RegsFile") +#else +#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss2RegsFile") +#else +#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss3RegsFile") +#else +#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss4RegsFile") +#else +#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss5RegsFile") +#else +#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss6RegsFile") +#else +#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss7RegsFile") +#else +#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss8RegsFile") +#else +#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss8Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CmConfRegsFile") +#else +#pragma DATA_SECTION(CmConfRegs,"CmConfRegsFile"); +#endif +volatile struct CM_CONF_REGS CmConfRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cpu1toCmIpcRegsFile") +#else +#pragma DATA_SECTION(Cpu1toCmIpcRegs,"Cpu1toCmIpcRegsFile"); +#endif +volatile struct CPU1TOCM_IPC_REGS_CPU1VIEW Cpu1toCmIpcRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cpu1toCpu2IpcRegsFile") +#else +#pragma DATA_SECTION(Cpu1toCpu2IpcRegs,"Cpu1toCpu2IpcRegsFile"); +#endif +volatile struct CPU1TOCPU2_IPC_REGS_CPU1VIEW Cpu1toCpu2IpcRegs; +#endif // ifdef CPU1 + +#ifdef CPU2 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cpu2toCpu1IpcRegsFile") +#else +#pragma DATA_SECTION(Cpu2toCpu1IpcRegs,"Cpu2toCpu1IpcRegsFile"); +#endif +volatile struct CPU1TOCPU2_IPC_REGS_CPU2VIEW Cpu2toCpu1IpcRegs; +#endif // ifdef CPU2 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SysPeriphAcRegsFile") +#else +#pragma DATA_SECTION(SysPeriphAcRegs,"SysPeriphAcRegsFile"); +#endif +volatile struct CPU1_PERIPH_AC_REGS SysPeriphAcRegs; +#endif // ifdef CPU1 + +#ifdef CPU2 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cpu2toCmIpcRegsFile") +#else +#pragma DATA_SECTION(Cpu2toCmIpcRegs,"Cpu2toCmIpcRegsFile"); +#endif +volatile struct CPU2TOCM_IPC_REGS_CPU2VIEW Cpu2toCmIpcRegs; +#endif // ifdef CPU2 + +#ifdef CPU2 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SysPeriphAcRegsFile") +#else +#pragma DATA_SECTION(SysPeriphAcRegs,"SysPeriphAcRegsFile"); +#endif +volatile struct CPU2_PERIPH_AC_REGS SysPeriphAcRegs; +#endif // ifdef CPU2 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuSysRegsFile") +#else +#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); +#endif +volatile struct CPU_SYS_REGS CpuSysRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacaRegsFile") +#else +#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); +#endif +volatile struct DAC_REGS DacaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacbRegsFile") +#else +#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); +#endif +volatile struct DAC_REGS DacbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DaccRegsFile") +#else +#pragma DATA_SECTION(DaccRegs,"DaccRegsFile"); +#endif +volatile struct DAC_REGS DaccRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Dcc0RegsFile") +#else +#pragma DATA_SECTION(Dcc0Regs,"Dcc0RegsFile"); +#endif +volatile struct DCC_REGS Dcc0Regs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Dcc1RegsFile") +#else +#pragma DATA_SECTION(Dcc1Regs,"Dcc1RegsFile"); +#endif +volatile struct DCC_REGS Dcc1Regs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Dcc2RegsFile") +#else +#pragma DATA_SECTION(Dcc2Regs,"Dcc2RegsFile"); +#endif +volatile struct DCC_REGS Dcc2Regs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmCommonRegsFile") +#else +#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); +#endif +volatile struct DCSM_COMMON_REGS DcsmCommonRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ1OtpRegsFile") +#else +#pragma DATA_SECTION(DcsmZ1OtpRegs,"DcsmZ1OtpRegsFile"); +#endif +volatile struct DCSM_Z1_OTP DcsmZ1OtpRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ1RegsFile") +#else +#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile"); +#endif +volatile struct DCSM_Z1_REGS DcsmZ1Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ2OtpRegsFile") +#else +#pragma DATA_SECTION(DcsmZ2OtpRegs,"DcsmZ2OtpRegsFile"); +#endif +volatile struct DCSM_Z2_OTP DcsmZ2OtpRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ2RegsFile") +#else +#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile"); +#endif +volatile struct DCSM_Z2_REGS DcsmZ2Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DevCfgRegsFile") +#else +#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); +#endif +volatile struct DEV_CFG_REGS DevCfgRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaClaSrcSelRegsFile") +#else +#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); +#endif +volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap7RegsFile") +#else +#pragma DATA_SECTION(ECap7Regs,"ECap7RegsFile"); +#endif +volatile struct ECAP_REGS ECap7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile"); +#endif +volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile"); +#endif +volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1RegsFile") +#else +#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile"); +#endif +volatile struct EMIF_REGS Emif1Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2RegsFile") +#else +#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile"); +#endif +volatile struct EMIF_REGS Emif2Regs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm7RegsFile") +#else +#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); +#endif +volatile struct EPWM_REGS EPwm7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm8RegsFile") +#else +#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); +#endif +volatile struct EPWM_REGS EPwm8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm9RegsFile") +#else +#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile"); +#endif +volatile struct EPWM_REGS EPwm9Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm10RegsFile") +#else +#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile"); +#endif +volatile struct EPWM_REGS EPwm10Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm11RegsFile") +#else +#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile"); +#endif +volatile struct EPWM_REGS EPwm11Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm12RegsFile") +#else +#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile"); +#endif +volatile struct EPWM_REGS EPwm12Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm13RegsFile") +#else +#pragma DATA_SECTION(EPwm13Regs,"EPwm13RegsFile"); +#endif +volatile struct EPWM_REGS EPwm13Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm14RegsFile") +#else +#pragma DATA_SECTION(EPwm14Regs,"EPwm14RegsFile"); +#endif +volatile struct EPWM_REGS EPwm14Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm15RegsFile") +#else +#pragma DATA_SECTION(EPwm15Regs,"EPwm15RegsFile"); +#endif +volatile struct EPWM_REGS EPwm15Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm16RegsFile") +#else +#pragma DATA_SECTION(EPwm16Regs,"EPwm16RegsFile"); +#endif +volatile struct EPWM_REGS EPwm16Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwmXbarRegsFile") +#else +#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); +#endif +volatile struct EPWM_XBAR_REGS EPwmXbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep3RegsFile") +#else +#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile"); +#endif +volatile struct EQEP_REGS EQep3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCounter1RegsFile") +#else +#pragma DATA_SECTION(EradCounter1Regs,"EradCounter1RegsFile"); +#endif +volatile struct ERAD_COUNTER_REGS EradCounter1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCounter2RegsFile") +#else +#pragma DATA_SECTION(EradCounter2Regs,"EradCounter2RegsFile"); +#endif +volatile struct ERAD_COUNTER_REGS EradCounter2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCounter3RegsFile") +#else +#pragma DATA_SECTION(EradCounter3Regs,"EradCounter3RegsFile"); +#endif +volatile struct ERAD_COUNTER_REGS EradCounter3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCounter4RegsFile") +#else +#pragma DATA_SECTION(EradCounter4Regs,"EradCounter4RegsFile"); +#endif +volatile struct ERAD_COUNTER_REGS EradCounter4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRCGlobalRegsFile") +#else +#pragma DATA_SECTION(EradCRCGlobalRegs,"EradCRCGlobalRegsFile"); +#endif +volatile struct ERAD_CRC_GLOBAL_REGS EradCRCGlobalRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC1RegsFile") +#else +#pragma DATA_SECTION(EradCRC1Regs,"EradCRC1RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC2RegsFile") +#else +#pragma DATA_SECTION(EradCRC2Regs,"EradCRC2RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC3RegsFile") +#else +#pragma DATA_SECTION(EradCRC3Regs,"EradCRC3RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC4RegsFile") +#else +#pragma DATA_SECTION(EradCRC4Regs,"EradCRC4RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC5RegsFile") +#else +#pragma DATA_SECTION(EradCRC5Regs,"EradCRC5RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC6RegsFile") +#else +#pragma DATA_SECTION(EradCRC6Regs,"EradCRC6RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC7RegsFile") +#else +#pragma DATA_SECTION(EradCRC7Regs,"EradCRC7RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC8RegsFile") +#else +#pragma DATA_SECTION(EradCRC8Regs,"EradCRC8RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradGlobalRegsFile") +#else +#pragma DATA_SECTION(EradGlobalRegs,"EradGlobalRegsFile"); +#endif +volatile struct ERAD_GLOBAL_REGS EradGlobalRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP1RegsFile") +#else +#pragma DATA_SECTION(EradHWBP1Regs,"EradHWBP1RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP2RegsFile") +#else +#pragma DATA_SECTION(EradHWBP2Regs,"EradHWBP2RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP3RegsFile") +#else +#pragma DATA_SECTION(EradHWBP3Regs,"EradHWBP3RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP4RegsFile") +#else +#pragma DATA_SECTION(EradHWBP4Regs,"EradHWBP4RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP5RegsFile") +#else +#pragma DATA_SECTION(EradHWBP5Regs,"EradHWBP5RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP6RegsFile") +#else +#pragma DATA_SECTION(EradHWBP6Regs,"EradHWBP6RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP7RegsFile") +#else +#pragma DATA_SECTION(EradHWBP7Regs,"EradHWBP7RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP8RegsFile") +#else +#pragma DATA_SECTION(EradHWBP8Regs,"EradHWBP8RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP8Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EscssConfigRegsFile") +#else +#pragma DATA_SECTION(EscssConfigRegs,"EscssConfigRegsFile"); +#endif +volatile struct ESCSS_CONFIG_REGS EscssConfigRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EscssRegsFile") +#else +#pragma DATA_SECTION(EscssRegs,"EscssRegsFile"); +#endif +volatile struct ESCSS_REGS EscssRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0CtrlRegsFile") +#else +#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); +#endif +volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0EccRegsFile") +#else +#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); +#endif +volatile struct FLASH_ECC_REGS Flash0EccRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxaRegsFile") +#else +#pragma DATA_SECTION(FsiRxaRegs,"FsiRxaRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxbRegsFile") +#else +#pragma DATA_SECTION(FsiRxbRegs,"FsiRxbRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxcRegsFile") +#else +#pragma DATA_SECTION(FsiRxcRegs,"FsiRxcRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxcRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxdRegsFile") +#else +#pragma DATA_SECTION(FsiRxdRegs,"FsiRxdRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxeRegsFile") +#else +#pragma DATA_SECTION(FsiRxeRegs,"FsiRxeRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxeRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxfRegsFile") +#else +#pragma DATA_SECTION(FsiRxfRegs,"FsiRxfRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxfRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxgRegsFile") +#else +#pragma DATA_SECTION(FsiRxgRegs,"FsiRxgRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxhRegsFile") +#else +#pragma DATA_SECTION(FsiRxhRegs,"FsiRxhRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxhRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiTxaRegsFile") +#else +#pragma DATA_SECTION(FsiTxaRegs,"FsiTxaRegsFile"); +#endif +volatile struct FSI_TX_REGS FsiTxaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiTxbRegsFile") +#else +#pragma DATA_SECTION(FsiTxbRegs,"FsiTxbRegsFile"); +#endif +volatile struct FSI_TX_REGS FsiTxbRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataReadRegsFile") +#else +#pragma DATA_SECTION(GpioDataReadRegs,"GpioDataReadRegsFile"); +#endif +volatile struct GPIO_DATA_READ_REGS GpioDataReadRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("HRCap6RegsFile") +#else +#pragma DATA_SECTION(HRCap6Regs,"HRCap6RegsFile"); +#endif +volatile struct HRCAP_REGS HRCap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("HRCap7RegsFile") +#else +#pragma DATA_SECTION(HRCap7Regs,"HRCap7RegsFile"); +#endif +volatile struct HRCAP_REGS HRCap7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2cbRegsFile") +#else +#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile"); +#endif +volatile struct I2C_REGS I2cbRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("InputXbarRegsFile") +#else +#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); +#endif +volatile struct INPUT_XBAR_REGS InputXbarRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClbInputXbarRegsFile") +#else +#pragma DATA_SECTION(ClbInputXbarRegs,"ClbInputXbarRegsFile"); +#endif +volatile struct INPUT_XBAR_REGS ClbInputXbarRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McanaSsRegsFile") +#else +#pragma DATA_SECTION(McanaSsRegs,"McanaSsRegsFile"); +#endif +volatile struct MCANSS_REGS McanaSsRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McanaErrRegsFile") +#else +#pragma DATA_SECTION(McanaErrRegs,"McanaErrRegsFile"); +#endif +volatile struct MCAN_ERROR_REGS McanaErrRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McanaRegsFile") +#else +#pragma DATA_SECTION(McanaRegs,"McanaRegsFile"); +#endif +volatile struct MCAN_REGS McanaRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemoryErrorRegsFile") +#else +#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); +#endif +volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemCfgRegsFile") +#else +#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); +#endif +volatile struct MEM_CFG_REGS MemCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct McBSP_REGS McbspaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct McBSP_REGS McbspbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("NmiIntruptRegsFile") +#else +#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); +#endif +volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("OutputXbarRegsFile") +#else +#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); +#endif +volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClbOutputXbarRegsFile") +#else +#pragma DATA_SECTION(ClbOutputXbarRegs,"ClbOutputXbarRegsFile"); +#endif +volatile struct OUTPUT_XBAR_REGS ClbOutputXbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +volatile struct PIE_VECT_TABLE PieVectTable; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PmbusaRegsFile") +#else +#pragma DATA_SECTION(PmbusaRegs,"PmbusaRegsFile"); +#endif +volatile struct PMBUS_REGS PmbusaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("RomPrefetchRegsFile") +#else +#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile"); +#endif +volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("RomWaitStateRegsFile") +#else +#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile"); +#endif +volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScidRegsFile") +#else +#pragma DATA_SECTION(ScidRegs,"ScidRegsFile"); +#endif +volatile struct SCI_REGS ScidRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm1RegsFile") +#else +#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm2RegsFile") +#else +#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpibRegsFile") +#else +#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); +#endif +volatile struct SPI_REGS SpibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpicRegsFile") +#else +#pragma DATA_SECTION(SpicRegs,"SpicRegsFile"); +#endif +volatile struct SPI_REGS SpicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpidRegsFile") +#else +#pragma DATA_SECTION(SpidRegs,"SpidRegsFile"); +#endif +volatile struct SPI_REGS SpidRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SyncSocRegsFile") +#else +#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); +#endif +volatile struct SYNC_SOC_REGS SyncSocRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SysStatusRegsFile") +#else +#pragma DATA_SECTION(SysStatusRegs,"SysStatusRegsFile"); +#endif +volatile struct SYS_STATUS_REGS SysStatusRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("TestErrorRegsFile") +#else +#pragma DATA_SECTION(TestErrorRegs,"TestErrorRegsFile"); +#endif +volatile struct TEST_ERROR_REGS TestErrorRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("WdRegsFile") +#else +#pragma DATA_SECTION(WdRegs,"WdRegsFile"); +#endif +volatile struct WD_REGS WdRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XbarRegsFile") +#else +#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); +#endif +volatile struct XBAR_REGS XbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XintRegsFile") +#else +#pragma DATA_SECTION(XintRegs,"XintRegsFile"); +#endif +volatile struct XINT_REGS XintRegs; + + + +//=========================================================================== +// End of file. +//=========================================================================== + + diff --git a/EFC_PlatformC28x/lib/f2838x_gpio.c b/EFC_PlatformC28x/lib/f2838x_gpio.c new file mode 100644 index 0000000..aca3330 --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_gpio.c @@ -0,0 +1,472 @@ +//########################################################################### +// +// FILE: f2838x_gpio.c +// +// TITLE: GPIO module support functions +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" +#include "f2838x_examples.h" + +// +//Low-level functions for GPIO configuration (CPU1 only) +// + +#ifdef CPU1 + // + // InitGpio - Sets all pins to be muxed to GPIO in input mode. + // Also resets CPU control to CPU1 and disables open + // drain and polarity inversion and sets the qualification to + // synchronous. Also unlocks all GPIOs. Only one CPU should call + // this function. + // + void InitGpio() + { + volatile Uint32 *gpioBaseAddr; + Uint16 regOffset; + + // + //Disable pin locks + // + EALLOW; + GpioCtrlRegs.GPALOCK.all = 0x00000000; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPCLOCK.all = 0x00000000; + GpioCtrlRegs.GPDLOCK.all = 0x00000000; + GpioCtrlRegs.GPELOCK.all = 0x00000000; + GpioCtrlRegs.GPFLOCK.all = 0x00000000; + + // + // Fill all registers with zeros. Writing to each register separately + // for six GPIO modules would make this function *very* long. + // Fortunately, we'd be writing them all with zeros anyway, so this + // saves a lot of space. + // + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; + for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) + { + // + //Hack to avoid enabling pull-ups on all pins. GPyPUD is offset + //0x0C in each register group of 0x40 words. Since this is a + //32-bit pointer, the addresses must be divided by 2. + // + if (regOffset % (0x40/2) != (0x0C/2)) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + } + + gpioBaseAddr = (Uint32 *)&GpioDataRegs; + for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + + EDIS; + } + + // + // GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The + // appropriate parameters can be found in the GPIO Muxed + // Pins table(4.4) in the datasheet. Use the GPIO index + // row (0 to 15) to select a muxing option for the GPIO. + // + void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *mux, *gmux, *csel; + Uint16 pin32, pin16, pin8; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pin8 = gpioNumber % 8; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Sanity check for valid cpu and peripheral values + // + if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF) + return; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyCSEL1-4. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + mux = gpioBaseAddr + GPYMUX + pin32/16; + gmux = gpioBaseAddr + GPYGMUX + pin32/16; + csel = gpioBaseAddr + GPYCSEL + pin32/8; + + // + //Now for the actual function + // + EALLOW; + + // + //To change the muxing, set the peripheral mux to 0/GPIO first to avoid + //glitches, then change the group mux, then set the peripheral mux to + //its target value. Finally, set the CPU select. This procedure is + //described in the TRM. Unfortunately, since we don't know the pin in + //advance we can't hardcode a bitfield reference, so there's some + //tricky bit twiddling here. + // + *mux &= ~(0x3UL << (2*pin16)); + *gmux &= ~(0x3UL << (2*pin16)); + *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); + *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); + + *csel &= ~(0x3L << (4*pin8)); + *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); + + // + //WARNING: This code does not touch the analog mode select registers, + //which are needed to give the USB module control of its IOs. + // + EDIS; + } + + // + // GPIO_SetupPinOptions - Setup up the GPIO input/output options for the + // specified pin. + // + //The flags are a 16-bit mask produced by ORing together options. + //For input pins, the valid flags are: + //GPIO_PULLUP Enable pull-up + //GPIO_INVERT Enable input polarity inversion + //GPIO_SYNC Synchronize the input latch to PLLSYSCLK + // (default -- you don't need to specify this) + //GPIO_QUAL3 Use 3-sample qualification + //GPIO_QUAL6 Use 6-sample qualification + //GPIO_ASYNC Do not use synchronization or qualification + //(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) + // + //For output pins, the valid flags are: + //GPIO_OPENDRAIN Output in open drain mode + //GPIO_PULLUP If open drain enabled, also enable the pull-up + //and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. + // + //With no flags, the default input state is synchronous with no + //pull-up or polarity inversion. The default output state is + //the standard digital output. + // + void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *dir, *pud, *inv, *odr, *qsel; + Uint32 pin32, pin16, pinMask, qual; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + dir = gpioBaseAddr + GPYDIR; + pud = gpioBaseAddr + GPYPUD; + inv = gpioBaseAddr + GPYINV; + odr = gpioBaseAddr + GPYODR; + qsel = gpioBaseAddr + GPYQSEL + pin32/16; + + EALLOW; + + // + //Set the data direction + // + *dir &= ~pinMask; + if (output == 1) + { + // + //Output, with optional open drain mode and pull-up + // + *dir |= pinMask; + + // + //Enable open drain if necessary + // + if (flags & GPIO_OPENDRAIN) + { + *odr |= pinMask; + } + else + { + *odr &= ~pinMask; + } + + // + //Enable pull-up if necessary. Open drain mode must be active. + // + if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + } + else + { + // + //Input, with optional pull-up, qualification, and polarity + //inversion + // + *dir &= ~pinMask; + + // + //Enable pull-up if necessary + // + if (flags & GPIO_PULLUP) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + + // + //Invert polarity if necessary + // + if (flags & GPIO_INVERT) + { + *inv |= pinMask; + } + else + { + *inv &= ~pinMask; + } + } + + // + //Extract the qualification parameter and load it into the register. + //This is also needed for open drain outputs, so we might as well do it + //all the time. + // + qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; + *qsel &= ~(0x3L << (2 * pin16)); + if (qual != 0x0) + { + *qsel |= qual << (2 * pin16); + } + + EDIS; + } + + // + // GPIO_SetupLock - Enable or disable the GPIO register bit lock for the + // specified pin. + // The valid flags are: + // GPIO_UNLOCK - Unlock the pin setup register bits for + // the specified pin + // GPIO_LOCK - Lock the pin setup register bits for the + // specified pin + // + void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *lock; + Uint32 pin32, pinMask; + + pin32 = gpioNumber % 32; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + lock = gpioBaseAddr + GPYLOCK; + + EALLOW; + if(flags) + { + //Lock the pin + *lock |= pinMask; + } + else + { + //Unlock the pin + *lock &= ~pinMask; + } + EDIS; + } + + // + //External interrupt setup + // + void GPIO_SetupXINT1Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT2Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT3Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT4Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT5Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin + EDIS; + } + + // + //GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded + // GPIOs on the 176PTP package: + // GPIOs Grp Bits + // 95-132 C 31 + // D 31:0 + // E 4:0 + // 134-168 E 31:6 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor176Pin() + { + EALLOW; + GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function + // this takes care of enabling IO pullups. + // + void GPIO_EnableUnbondedIOPullups() + { + // + //bits 8-10 have pin count + // + unsigned char pin_count = (DevCfgRegs.PARTIDL.bit.PIN_COUNT) ; + + // + //6 = 176 pin + //7 = 337 pin + // + if (pin_count == 6) + { + GPIO_EnableUnbondedIOPullupsFor176Pin(); + } + else + { + //do nothing - this is 337 pin package + } + } + +#endif //CPU1 + +// +// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that +// this returns the actual state of the pin, not the state of +// the output latch. +// +Uint16 GPIO_ReadPin(Uint16 gpioNumber) +{ + volatile Uint32 *gpioDataReg; + Uint16 pinVal; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; + + return pinVal; +} + +// +// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. +// +void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) +{ + volatile Uint32 *gpioDataReg; + Uint32 pinMask; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinMask = 1UL << (gpioNumber % 32); + + if (outVal == 0) + { + gpioDataReg[GPYCLEAR] = pinMask; + } + else + { + gpioDataReg[GPYSET] = pinMask; + } +} + +// +// End of file +// diff --git a/EFC_PlatformC28x/lib/f2838x_piectrl.c b/EFC_PlatformC28x/lib/f2838x_piectrl.c new file mode 100644 index 0000000..3fbd8a5 --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_piectrl.c @@ -0,0 +1,121 @@ +//########################################################################### +// +// FILE: f2838x_piectrl.c +// +// TITLE: F2838x Device PIE Control Register Initialization Functions. +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" // F2838x Headerfile Include File +#include "f2838x_examples.h" // F2838x Examples Include File + +// +// InitPieCtrl - This function initializes the PIE control registers to a +// known state. +// +void InitPieCtrl(void) +{ + // + // Disable Interrupts at the CPU level: + // + DINT; + + // + // Disable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // + // Clear all PIEIER registers: + // + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // + // Clear all PIEIFR registers: + // + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; +} + +// +// EnableInterrupts - This function enables the PIE module and CPU __interrupts +// +void EnableInterrupts() +{ + // + // Enable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enables PIE to drive a pulse into the CPU + // + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // + // Enable Interrupts at the CPU level + // + EINT; +} + +// +// End of file +// diff --git a/EFC_PlatformC28x/lib/f2838x_pievect.c b/EFC_PlatformC28x/lib/f2838x_pievect.c new file mode 100644 index 0000000..5f0d7cb --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_pievect.c @@ -0,0 +1,309 @@ +//########################################################################### +// +// FILE: f2838x_pievect.c +// +// TITLE: f2838x Device PIE Vector Initialization Functions +// +//########################################################################### +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" // f2838x Header File Include File +#include "f2838x_examples.h" // f2838x Examples Include File + +// +// Globals +// +const struct PIE_VECT_TABLE PieVectTableInit = { + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + TIMER1_ISR, // CPU Timer 1 Interrupt + TIMER2_ISR, // CPU Timer 2 Interrupt + DATALOG_ISR, // Datalogging Interrupt + RTOS_ISR, // RTOS Interrupt + EMU_ISR, // Emulation Interrupt + NMI_ISR, // Non-Maskable Interrupt + ILLEGAL_ISR, // Illegal Operation Trap + USER1_ISR, // User Defined Trap 1 + USER2_ISR, // User Defined Trap 2 + USER3_ISR, // User Defined Trap 3 + USER4_ISR, // User Defined Trap 4 + USER5_ISR, // User Defined Trap 5 + USER6_ISR, // User Defined Trap 6 + USER7_ISR, // User Defined Trap 7 + USER8_ISR, // User Defined Trap 8 + USER9_ISR, // User Defined Trap 9 + USER10_ISR, // User Defined Trap 10 + USER11_ISR, // User Defined Trap 11 + USER12_ISR, // User Defined Trap 12 + ADCA1_ISR, // 1.1 - ADCA Interrupt 1 + ADCB1_ISR, // 1.2 - ADCB Interrupt 1 + ADCC1_ISR, // 1.3 - ADCC Interrupt 1 + XINT1_ISR, // 1.4 - XINT1 Interrupt + XINT2_ISR, // 1.5 - XINT2 Interrupt + ADCD1_ISR, // 1.6 - ADCD Interrupt 1 + TIMER0_ISR, // 1.7 - Timer 0 Interrupt + WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt + EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt + EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt + EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt + EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt + EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt + EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt + EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt + EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt + EPWM1_ISR, // 3.1 - ePWM1 Interrupt + EPWM2_ISR, // 3.2 - ePWM2 Interrupt + EPWM3_ISR, // 3.3 - ePWM3 Interrupt + EPWM4_ISR, // 3.4 - ePWM4 Interrupt + EPWM5_ISR, // 3.5 - ePWM5 Interrupt + EPWM6_ISR, // 3.6 - ePWM6 Interrupt + EPWM7_ISR, // 3.7 - ePWM7 Interrupt + EPWM8_ISR, // 3.8 - ePWM8 Interrupt + ECAP1_ISR, // 4.1 - eCAP1 Interrupt + ECAP2_ISR, // 4.2 - eCAP2 Interrupt + ECAP3_ISR, // 4.3 - eCAP3 Interrupt + ECAP4_ISR, // 4.4 - eCAP4 Interrupt + ECAP5_ISR, // 4.5 - eCAP5 Interrupt + ECAP6_ISR, // 4.6 - eCAP6 Interrupt + ECAP7_ISR, // 4.7 - eCAP7 Interrupt + PIE_RESERVED_ISR, // 4.8 - Reserved + EQEP1_ISR, // 5.1 - eQEP1 Interrupt + EQEP2_ISR, // 5.2 - eQEP2 Interrupt + EQEP3_ISR, // 5.3 - eQEP3 Interrupt + PIE_RESERVED_ISR, // 5.4 - Reserved + CLB1_ISR, // 5.5 - CLB1 (Reconfigurable Logic) Interrupt + CLB2_ISR, // 5.6 - CLB2 (Reconfigurable Logic) Interrupt + CLB3_ISR, // 5.7 - CLB3 (Reconfigurable Logic) Interrupt + CLB4_ISR, // 5.8 - CLB4 (Reconfigurable Logic) Interrupt + SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt + SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt + SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt + SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt + MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt + MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt + MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt + MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt + DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt + DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt + DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt + DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt + DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt + DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt + PIE_RESERVED_ISR, // 7.7 - Reserved + PIE_RESERVED_ISR, // 7.8 - Reserved + I2CA_ISR, // 8.1 - I2CA Interrupt 1 + I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 + I2CB_ISR, // 8.3 - I2CB Interrupt 1 + I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 + SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt + SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt + SCID_RX_ISR, // 8.7 - SCID Receive Interrupt + SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt + SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt + SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt + SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt + SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt + CANA0_ISR, // 9.5 - CANA Interrupt 0 + CANA1_ISR, // 9.6 - CANA Interrupt 1 + CANB0_ISR, // 9.7 - CANB Interrupt 0 + CANB1_ISR, // 9.8 - CANB Interrupt 1 + ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt + ADCA2_ISR, // 10.2 - ADCA Interrupt 2 + ADCA3_ISR, // 10.3 - ADCA Interrupt 3 + ADCA4_ISR, // 10.4 - ADCA Interrupt 4 + ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt + ADCB2_ISR, // 10.6 - ADCB Interrupt 2 + ADCB3_ISR, // 10.7 - ADCB Interrupt 3 + ADCB4_ISR, // 10.8 - ADCB Interrupt 4 + CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 + CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 + CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 + CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 + CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 + CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 + CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 + CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 + XINT3_ISR, // 12.1 - XINT3 Interrupt + XINT4_ISR, // 12.2 - XINT4 Interrupt + XINT5_ISR, // 12.3 - XINT5 Interrupt + MPOST_ISR, // 12.4 - MPOST Interrupt + FMC_ISR, // 12.5 - Flash Wrapper Operation Done Interrupt + PIE_RESERVED_ISR, // 12.6 - Reserved + FPU_OFLOW_ISR, // 12.7 - FPU Overflow Interrupt + FPU_UFLOW_ISR, // 12.8 - FPU Underflow Interrupt + I2CA_HIGH_ISR, // 1.9 - I2CA Interrupt high priority + SYS_ERR_ISR, // 1.10 - System error interrupt + ECATSYNC0_ISR, // 1.11 - ETHERCAT SYNC0 interrupt + ECAT_ISR, // 1.12 - ETHERCAT main interrupt + CIPC0_ISR, // 1.13 - C28x CPU IPC interrupt 1 + CIPC1_ISR, // 1.14 - C28x CPU IPC interrupt 2 + CIPC2_ISR, // 1.15 - C28x CPU IPC interrupt 3 + CIPC3_ISR, // 1.16 - C28x CPU IPC interrupt 4 + EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt + EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt + EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt + EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt + EPWM13_TZ_ISR, // 2.13 - ePWM13 Trip Zone Interrupt + EPWM14_TZ_ISR, // 2.14 - ePWM14 Trip Zone Interrupt + EPWM15_TZ_ISR, // 2.15 - ePWM15 Trip Zone Interrupt + EPWM16_TZ_ISR, // 2.16 - ePWM16 Trip Zone Interrupt + EPWM9_ISR, // 3.9 - ePWM9 Interrupt + EPWM10_ISR, // 3.10 - ePWM10 Interrupt + EPWM11_ISR, // 3.11 - ePWM11 Interrupt + EPWM12_ISR, // 3.12 - ePWM12 Interrupt + EPWM13_ISR, // 3.13 - ePWM13 Interrupt + EPWM14_ISR, // 3.14 - ePWM14 Interrupt + EPWM15_ISR, // 3.15 - ePWM15 Interrupt + EPWM16_ISR, // 3.16 - ePWM16 Interrupt + FSITXA1_ISR, // 4.9 - FSIA Transmit interrupt 1 + FSITXA2_ISR, // 4.10 - FSIA Transmit interrupt 2 + FSITXB1_ISR, // 4.11 - FSIB Transmit interrupt 1 + FSITXB2_ISR, // 4.12 - FSIB Transmit interrupt 2 + FSIRXA1_ISR, // 4.13 - FSIA Receive interrupt 1 + FSIRXA2_ISR, // 4.14 - FSIA Receive interrupt 2 + FSIRXB1_ISR, // 4.15 - FSIB Receive interrupt 1 + FSIRXB2_ISR, // 4.16 - FSIB Receive interrupt 2 + SDFM1_ISR, // 5.9 - Sigma Delta Filter Module1 Interrupt + SDFM2_ISR, // 5.10 - Sigma Delta Filter Module2 Interrupt + ECATRST_ISR, // 5.11 - ETHERCAT Resetout Interrupt + ECATSYNC1_ISR, // 5.12 - ETHERCAT SYNC1 interrupt + SDFM1DR1_ISR, // 5.13 - Sigma Delta Filter Module1 Filter 1 Interrupt + SDFM1DR2_ISR, // 5.14 - Sigma Delta Filter Module1 Filter 2 Interrupt + SDFM1DR3_ISR, // 5.15 - Sigma Delta Filter Module1 Filter 3 Interrupt + SDFM1DR4_ISR, // 5.16 - Sigma Delta Filter Module1 Filter 4 Interrupt + SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt + SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt + SPID_RX_ISR, // 6.11 - SPID Receive Interrupt + SPID_TX_ISR, // 6.12 - SPID Transmit Interrupt + SDFM2DR1_ISR, // 6.13 - Sigma Delta Filter Module2 Filter 1 Interrupt + SDFM2DR2_ISR, // 6.14 - Sigma Delta Filter Module2 Filter 2 Interrupt + SDFM2DR3_ISR, // 6.15 - Sigma Delta Filter Module2 Filter 3 Interrupt + SDFM2DR4_ISR, // 6.16 - Sigma Delta Filter Module2 Filter 4 Interrupt + FSIRXC1_ISR, // 7.9 - FSIC Receive interrupt 1 + FSIRXC2_ISR, // 7.10 - FSIC Receive interrupt 2 + FSIRXD1_ISR, // 7.11 - FSID Receive interrupt 1 + FSIRXD2_ISR, // 7.12 - FSID Receive interrupt 2 + FSIRXE1_ISR, // 7.13 - FSIE Receive interrupt 1 + FSIRXE2_ISR, // 7.14 - FSIE Receive interrupt 2 + FSIRXF1_ISR, // 7.15 - FSIF Receive interrupt 1 + FSIRXF2_ISR, // 7.16 - FSIF Receive interrupt 2 + FSIRXG1_ISR, // 8.9 - FSIG Receive interrupt 1 + FSIRXG2_ISR, // 8.10 - FSIG Receive interrupt 2 + FSIRXH1_ISR, // 8.11 - FSIH Receive interrupt 1 + FSIRXH2_ISR, // 8.12 - FSIH Receive interrupt 2 + CLB5_ISR, // 8.13 - CLB5 Interrupt + CLB6_ISR, // 8.14 - CLB6 Interrupt + CLB7_ISR, // 8.15 - CLB7 Interrupt + CLB8_ISR, // 8.16 - CLB8 Interrupt + MCANA_0_ISR, // 9.9 - MCAN Sub-System Interrupt 0 + MCANA_1_ISR, // 9.10 - MCAN Sub-System Interrupt 1 + MCANA_ECC_ISR, // 9.11 - MCAN Sub-System ECC error Interrupt + MCANA_WAKE_ISR, // 9.12 - MCAN Sub-System wakeup Interrupt + PMBUSA_ISR, // 9.13 - PMBUSA Interrupt + CM_STATUS_ISR, // 9.14 - CM Reset Status Interrupt + USBA_ISR, // 9.15 - USBA Interrupt + PIE_RESERVED_ISR, // 9.16 - Reserved + ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt + ADCC2_ISR, // 10.10 - ADCC Interrupt 2 + ADCC3_ISR, // 10.11 - ADCC Interrupt 3 + ADCC4_ISR, // 10.12 - ADCC Interrupt 4 + ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt + ADCD2_ISR, // 10.14 - ADCD Interrupt 2 + ADCD3_ISR, // 10.15 - ADCD Interrupt 3 + ADCD4_ISR, // 10.16 - ADCD Interrupt 4 + CMTOCPUXIPC0_ISR, // 11.9 - CM to CPU IPC Interrupt 0 + CMTOCPUXIPC1_ISR, // 11.10 - CM to CPU IPC Interrupt 1 + CMTOCPUXIPC2_ISR, // 11.11 - CM to CPU IPC Interrupt 2 + CMTOCPUXIPC3_ISR, // 11.12 - CM to CPU IPC Interrupt 3 + CMTOCPUXIPC4_ISR, // 11.13 - CM to CPU IPC Interrupt 4 + CMTOCPUXIPC5_ISR, // 11.14 - CM to CPU IPC Interrupt 5 + CMTOCPUXIPC6_ISR, // 11.15 - CM to CPU IPC Interrupt 6 + CMTOCPUXIPC7_ISR, // 11.16 - CM to CPU IPC Interrupt 7 + PIE_RESERVED_ISR, // 12.9 - Reserved + ECAP6_2_ISR, // 12.10 - eCAP6 Interrupt 2 + ECAP7_2_ISR, // 12.11 - eCAP7 Interrupt 2 + PIE_RESERVED_ISR, // 12.12 - Reserved + CPUCRC_ISR, // 12.13 - CPU BGCRC module interrupt + CLA1CRC_ISR, // 12.14 - CLA1 BGCRC module interrupt + CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt + CLA_UNDERFLOW_ISR, // 12.16 - CLA Underflow Interrupt +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a +// known state and must be executed after boot time. +// +void InitPieVectTable(void) +{ + Uint16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + // + // Do not write over first 3 32-bit locations (these locations are + // initialized by Boot ROM with boot variables) + // + Source = Source + 3; + Dest = Dest + 3; + + EALLOW; + for(i = 0; i < 221; i++) + { + *Dest++ = *Source++; + } + EDIS; + + // + // Enable the PIE Vector Table + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; +} + +// +// End of file +// diff --git a/EFC_PlatformC28x/lib/f2838x_sdfm_drivers.c b/EFC_PlatformC28x/lib/f2838x_sdfm_drivers.c new file mode 100644 index 0000000..540fe13 --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_sdfm_drivers.c @@ -0,0 +1,568 @@ +//########################################################################### +// +// FILE: f2838x_sdfm_drivers.c +// +// TITLE: SDFM Driver functions +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f28x_project.h" +#include "f2838x_struct.h" +#include "f2838x_sdfm_drivers.h" + +// +// Sdfm_configureInputCtrl - This function configures SDFM Input control unit. +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter (FILTER1,FILTER2, +// FILTER3,FILTER4) needs to be +// configured. +// mode - This parameter is used to select +// one of the modes mentioned above +// +// Input control unit can be configured in four different modes: +// MODE_0 : Modulator clock rate = Modulator data rate +// MODE_1 : Modulator clock rate = (Modulator data rate / 2) +// MODE_2 : Manchester encoded data (Modulator clock is encoded into data) +// MODE_3 : Modulator clock rate = (2 x Modulator data rate) +// +void Sdfm_configureInputCtrl(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 mode) +{ + EALLOW; + + switch (filterNumber) + { + case FILTER1: + (*SDFM[sdfmNumber]).SDCTLPARM1.bit.MOD = mode; + break; + + case FILTER2: + (*SDFM[sdfmNumber]).SDCTLPARM2.bit.MOD = mode; + break; + + case FILTER3: + (*SDFM[sdfmNumber]).SDCTLPARM3.bit.MOD = mode; + break; + + case FILTER4: + (*SDFM[sdfmNumber]).SDCTLPARM4.bit.MOD = mode; + break; + } + + EDIS; +} + +// +// Sdfm_configureComparator - This function configures SDFM Comparator unit. +// Comparator unit can be configured to monitor +// input conditions with a fast settling time. +// This module can be programmed to detect over and +// under value conditions. +// +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter (FILTER1,FILTER2, +// FILTER3,FILTER3) +// filterType - This parameter is used to select +// one of the filter type mentioned +// above (SINC1,SINC2,SINC3,SINCFAST) +// OSR - This parameter is used to +// configure oversampling ratio for +// comparator +// HLT - This parameter is used to +// configure to detect over value +// condition. The upper 16-bits denote +// high threshold 2 values while lower +// 16-bits denote high threshold 1 +// values +// LLT - This parameter is used to +// configure to detect under value +// condition.The upper 16-bits denote +// low threshold 2 values while lower +// 16-bits denote low threshold 1 +// values +// +void Sdfm_configureComparator(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 filterType, Uint16 OSR, Uint32 HLT, + Uint32 LLT) +{ + EALLOW; + + switch (filterNumber) + { + case FILTER1: //Filter 1 + + // + // Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM1.bit.CS1_CS0 = filterType; + + // + // Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDFLT1CMPH1.bit.HLT = (Uint16)HLT; + (*SDFM[sdfmNumber]).SDFLT1CMPL1.bit.LLT = (Uint16)LLT; + (*SDFM[sdfmNumber]).SDFLT1CMPH2.bit.HLT2 = (Uint16)(HLT >> 16U); + (*SDFM[sdfmNumber]).SDFLT1CMPL2.bit.LLT2 = (Uint16)(LLT >> 16U); + break; + + case FILTER2: //Filter 2 + // + // Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM2.bit.CS1_CS0 = filterType; + + // + // Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDFLT2CMPH1.bit.HLT = (Uint16)HLT; + (*SDFM[sdfmNumber]).SDFLT2CMPL1.bit.LLT = (Uint16)LLT; + (*SDFM[sdfmNumber]).SDFLT2CMPH2.bit.HLT2 = (Uint16)(HLT >> 16U); + (*SDFM[sdfmNumber]).SDFLT2CMPL2.bit.LLT2 = (Uint16)(LLT >> 16U); + break; + + case FILTER3: //Filter 3 + // + // Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM3.bit.CS1_CS0 = filterType; + + // + // Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDFLT3CMPH1.bit.HLT = (Uint16)HLT; + (*SDFM[sdfmNumber]).SDFLT3CMPL1.bit.LLT = (Uint16)LLT; + (*SDFM[sdfmNumber]).SDFLT3CMPH2.bit.HLT2 = (Uint16)(HLT >> 16U); + (*SDFM[sdfmNumber]).SDFLT3CMPL2.bit.LLT2 = (Uint16)(LLT >> 16U); + break; + + case FILTER4: //Filter 4 + // + // Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM4.bit.CS1_CS0 = filterType; + + // + // Configure Comparator OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDFLT4CMPH1.bit.HLT = (Uint16)HLT; + (*SDFM[sdfmNumber]).SDFLT4CMPL1.bit.LLT = (Uint16)LLT; + (*SDFM[sdfmNumber]).SDFLT4CMPH2.bit.HLT2 = (Uint16)(HLT >> 16U); + (*SDFM[sdfmNumber]).SDFLT4CMPL2.bit.LLT2 = (Uint16)(LLT >> 16U); + break; + } + + EDIS; +} + + +// +// SDFM_configureData_filter - This function configures SDFM Data filter unit +// +// SDFM Data filter unit can be configured in any +// of four different Sinc filter types: +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter(FILTER1,FILTER2, +// FILTER3,FILTER3) needs to be +// configured +// Filter_switch - This parameter is used to +// enable/disable a filter +// filterType - This parameter is used to select +// one of the filter type mentioned +// above (SINC1 / SINC2 / SINC3 / +// SINCFAST) +// OSR - This parameter is used to +// configure oversampling ratio +// for Data filter (Upto OSR_256) +// DR_switch - This parameter selects whether +// data is represented in 16 (or) +// 32 bits +// shift_bits - When user chooses 16 bit +// representation, this variable +// allows to right shift by +// specific number of bits +// +void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 Filter_switch, Uint16 filterType, + Uint16 OSR, Uint16 DR_switch, Uint16 shift_bits) +{ + EALLOW; + + switch(filterNumber) + { + + case FILTER1: //Filter 1 + (*SDFM[sdfmNumber]).SDDFPARM1.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.SST = filterType; + + // + // Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + // Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM1.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM1.bit.SH = shift_bits; + } + + break; + + case FILTER2: //Filter 2 + (*SDFM[sdfmNumber]).SDDFPARM2.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.SST = filterType; + + // + // Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + // Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM2.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM2.bit.SH = shift_bits; + } + + break; + + case FILTER3: //Filter 3 + (*SDFM[sdfmNumber]).SDDFPARM3.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.SST = filterType; + + // + // Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + // Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM3.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM3.bit.SH = shift_bits; + } + + break; + + case FILTER4: //Filter 4 + (*SDFM[sdfmNumber]).SDDFPARM4.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.SST = filterType; + + // + // Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + // Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM4.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM4.bit.SH = shift_bits; + } + + break; + } + + EDIS; +} + +// +// Sdfm_configureInterrupt - This function configures SDFM Interrupt unit. +// SDFM Interrupt unit can be configured to +// enable/disable different sources of SDFM +// interrupts which should trigger CPU interrupt. +// +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter(FILTER1,FILTER2, +// FILTER3,FILTER3) needs to be +// configured +// IEH_Switch - This parameter allows over value +// condition to trigger CPU interrupt +// IEL_Switch - This parameter allows under value +// condition to trigger CPU interrupt +// MFIE_Switch - This parameter allows modulator +// failure to trigger CPU interrupt +// AE_Switch - This parameter allows new filter +// data acknowledge interrupt signal +// to trigger CPU interrupt +// +void Sdfm_configureInterrupt(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 IEH_Switch, Uint16 IEL_Switch, + Uint16 MFIE_Switch, Uint16 AE_Switch) +{ + EALLOW; + + switch(filterNumber) + { + case FILTER1: //Filter 1 + (*SDFM[sdfmNumber]).SDCPARM1.bit.EN_CEVT1 = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM1.bit.EN_CEVT2 = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM1.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.AE = AE_Switch; + break; + + case FILTER2: //Filter 2 + (*SDFM[sdfmNumber]).SDCPARM2.bit.EN_CEVT1 = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM2.bit.EN_CEVT2 = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM2.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.AE = AE_Switch; + break; + + case FILTER3: //Filter 3 + (*SDFM[sdfmNumber]).SDCPARM3.bit.EN_CEVT1 = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM3.bit.EN_CEVT2 = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM3.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.AE = AE_Switch; + break; + + case FILTER4: //Filter 4 + (*SDFM[sdfmNumber]).SDCPARM4.bit.EN_CEVT1 = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM4.bit.EN_CEVT2 = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM4.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.AE = AE_Switch; + break; + } + + EDIS; +} + + +// +// SDFM_configExternalreset - This function configures SDFM module to +// enable/disable external filter reset from PWM +// +// sdfmNumber - This parameter should +// be used to select +// SDFM1 (or) SDFM2 +// filter1_Config_ext_reset - This parameter is used +// to enable/disable +// external PWM reset for +// filter1 +// filter2_Config_ext_reset - This parameter is used +// to enable/disable +// external PWM reset for +// filter2 +// filter3_Config_ext_reset - This parameter is used +// to enable / disable +// external PWM reset for +// filter3 +// filter4_Config_ext_reset - This parameter is used +// to enable / disable +// external PWM reset for +// filter4 +// +void Sdfm_configureExternalreset(Uint16 sdfmNumber, + Uint16 filter1_Config_ext_reset, + Uint16 filter2_Config_ext_reset, + Uint16 filter3_Config_ext_reset, + Uint16 filter4_Config_ext_reset) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.SDSYNCEN = filter1_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.SDSYNCEN = filter2_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.SDSYNCEN = filter3_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.SDSYNCEN = filter4_Config_ext_reset; + EDIS; +} + +// +// SDFM_enableMFE - This function enables Master filter bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_enableMFE(Uint16 sdfmNumber) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 1; //Master Filter bit is enabled + EDIS; +} + +// +// SDFM_disableMFE - This function disable Master filter bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void SDFM_disableMFE(Uint16 sdfmNumber) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 0; //Master Filter bit is disabled + EDIS; +} + +// +// SDFM_enableMIE - This function enable Master Interrupt bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_enableMIE(Uint16 sdfmNumber) +{ + EALLOW; + // + //Enable MIE (Master Interrupt Enable) bit + // + (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 1; + EDIS; +} + +// +// Sdfm_disableMIE - This function disable Master Interrupt bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_disableMIE(Uint16 sdfmNumber) +{ + + EALLOW; + // + //Disable MIE (Master Interrupt Enable) bit + // + (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 0; + EDIS; +} + +// +// Sdfm_readFlagRegister - This function helps user read SDFM flag +// register (SDIFLG) +// +Uint32 Sdfm_readFlagRegister(Uint16 sdfmNumber) +{ + return ((*SDFM[sdfmNumber]).SDIFLG.all); +} + +// +// Sdfm_clearFlagRegister - This function helps is used to clear +// SDIFLG register +// +void Sdfm_clearFlagRegister(Uint16 sdfmNumber,Uint32 sdfmReadFlagRegister) +{ + (*SDFM[sdfmNumber]).SDIFLGCLR.all = sdfmReadFlagRegister; +} + +// +// End of file +// diff --git a/EFC_PlatformC28x/lib/f2838x_struct.c b/EFC_PlatformC28x/lib/f2838x_struct.c new file mode 100644 index 0000000..37934ce --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_struct.c @@ -0,0 +1,105 @@ +//########################################################################### +// +// FILE: f2838x_struct.c +// +// TITLE: F2838x SDFM structure +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" +#include "f2838x_struct.h" + +// +// Globals +// +#if defined(CPU1) +volatile struct ADC_REGS *ADC[MAX_ADC] = +{ 0, &AdcaRegs, &AdcbRegs, + &AdccRegs, &AdcdRegs }; +#endif + +volatile struct ECAP_REGS *ECAP[MAX_ECAP] = +{ 0, &ECap1Regs, &ECap2Regs, &ECap3Regs, + &ECap4Regs, &ECap5Regs, &ECap6Regs, + &ECap7Regs }; + +volatile struct EPWM_REGS *EPWM[MAX_EPWM] = +{ 0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, + &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, + &EPwm7Regs, &EPwm8Regs, &EPwm9Regs, + &EPwm10Regs, &EPwm11Regs, &EPwm12Regs, + &EPwm13Regs, &EPwm14Regs, &EPwm15Regs, + &EPwm16Regs }; + +volatile struct EQEP_REGS *EQEP[MAX_EQEP] = +{ 0, &EQep1Regs, &EQep2Regs, &EQep3Regs }; + +volatile struct I2C_REGS *I2C[MAX_I2C] = +{ 0, &I2caRegs ,&I2cbRegs }; + +volatile struct McBSP_REGS *MCBSP[MAX_MCBSP] = +{ 0, &McbspaRegs ,&McbspbRegs }; + +volatile struct SCI_REGS *SCI[MAX_SCI] = +{ 0, &SciaRegs ,&ScibRegs ,&ScicRegs , + &ScidRegs }; + +volatile struct SPI_REGS *SPI[MAX_SPI] = +{ 0, &SpibRegs, &SpibRegs, &SpicRegs, + &SpicRegs }; + +volatile struct SDFM_REGS *SDFM[MAX_SDFM] = +{ 0, &Sdfm1Regs, &Sdfm2Regs}; + +#if defined(CPU1) +volatile Uint16 *TRIP_SEL[MAX_TRIPSEL] = +{ 0, &InputXbarRegs.INPUT1SELECT, &InputXbarRegs.INPUT2SELECT, + &InputXbarRegs.INPUT3SELECT, &InputXbarRegs.INPUT4SELECT, + &InputXbarRegs.INPUT5SELECT, &InputXbarRegs.INPUT6SELECT, + &InputXbarRegs.INPUT7SELECT, &InputXbarRegs.INPUT8SELECT, + &InputXbarRegs.INPUT9SELECT, &InputXbarRegs.INPUT10SELECT, + &InputXbarRegs.INPUT11SELECT, &InputXbarRegs.INPUT12SELECT, + &InputXbarRegs.INPUT13SELECT, &InputXbarRegs.INPUT14SELECT +}; +#endif + +// +// End of file +// diff --git a/EFC_PlatformC28x/lib/f2838x_sysctrl.c b/EFC_PlatformC28x/lib/f2838x_sysctrl.c new file mode 100644 index 0000000..a71322a --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_sysctrl.c @@ -0,0 +1,1519 @@ +//########################################################################### +// +// FILE: f2838x_sysctrl.c +// +// TITLE: F2838x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: +// +// Example initialization of system resources. +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" +#include "f2838x_examples.h" +#include "math.h" + +// +// Functions that will be run from RAM need to be assigned to a different +// section. This section will then be mapped to a load and run address using +// the linker cmd file. +// +// *IMPORTANT* +// +// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM +// FLASH TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM +// THROWING AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. +// +#pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); +#pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); + + +// The following values are used to validate PLL Frequency using DCC +// +#define DCC_COUNTER0_TOLERANCE 1 + + + +#ifdef USE_20MHZ_XTAL + +#define OSC_FREQ 20 + +// +// Multipliers and dividers to configure 200MHz SYSPLL output from 20MHz XTAL +// +#define SYS_IMULT IMULT_40 +#define SYS_REFDIV REFDIV_2 +#define SYS_ODIV ODIV_2 +#define SYS_DIV PLLCLK_BY_1 + +// +// Multipliers and dividers to configure 125MHz AUXPLL output from 20MHz XTAL +// +#define AUX_IMULT IMULT_50 +#define AUX_REFDIV REFDIV_2 +#define AUX_ODIV ODIV_4 +#define AUX_DIV AUXPLLRAWCLK_BY_1 + + +#else // USE_25MHZ_XTAL + +#define OSC_FREQ 25 + +// +// Multipliers and dividers to configure 200MHz SYSPLL output from 25MHz XTAL +// +#define SYS_IMULT IMULT_32 +#define SYS_REFDIV REFDIV_2 +#define SYS_ODIV ODIV_2 +#define SYS_DIV PLLCLK_BY_1 + +// +// Multipliers and dividers to configure 125MHz AUXPLL output from 25MHz XTAL +// +#define AUX_IMULT IMULT_40 +#define AUX_REFDIV REFDIV_2 +#define AUX_ODIV ODIV_4 +#define AUX_DIV AUXPLLRAWCLK_BY_1 + +#endif + +// +// InitSysCtrl - Initialization of system resources. +// +void InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + +#ifdef _FLASH + // + // Copy time critical code and Flash setup code to RAM. This includes the + // following functions: InitFlash() + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart + // symbols are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + InitFlash(); +#endif + + // + // *IMPORTANT* + // + // The Device_cal function, which copies the ADC & oscillator calibration + // values from TI reserved OTP into the appropriate trim registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC and + // oscillators to function according to specification. The clocks to the + // ADC MUST be enabled before calling this function. + // + // See the device data manual and/or the ADC Reference Manual for more + // information. + // +#ifdef CPU1 + // + // Enable pull-ups on unbonded IOs as soon as possible to reduce power + // consumption. + // + GPIO_EnableUnbondedIOPullups(); + + EALLOW; + + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + // + // Check if device is trimmed + // + if(*((Uint16 *)0x5D736) == 0x0000){ + // + // Device is not trimmed--apply static calibration values + // + AnalogSubsysRegs.ANAREFTRIMA.all = 31709; + AnalogSubsysRegs.ANAREFTRIMB.all = 31709; + AnalogSubsysRegs.ANAREFTRIMC.all = 31709; + AnalogSubsysRegs.ANAREFTRIMD.all = 31709; + } + + CpuSysRegs.PCLKCR13.bit.ADC_A = 0; + CpuSysRegs.PCLKCR13.bit.ADC_B = 0; + CpuSysRegs.PCLKCR13.bit.ADC_C = 0; + CpuSysRegs.PCLKCR13.bit.ADC_D = 0; + EDIS; + + // + // Verify the crystal frequency. + // Note: This check can be removed if you are not using XTAL as the PLL + // source + // + if(!VerifyXTAL(OSC_FREQ)) + { + // + // The actual XTAL frequency does not match OSC_FREQ!! + // Please check the XTAL frequency used. + // + // By default, the InitSysCtrl function assumes 25MHz XTAL. + // If a 20MHz crystal is used, please add a predefined symbol + // "USE_20MHZ_XTAL" in your CCS project. + // If a different XTAL is used, please update the PLL configuration + // below accordingly. + // + // Note that the latest F2838x controlCARDs (Rev.B and later) have been + // updated to use 25MHz XTAL by default. If you have an older 20MHz XTAL + // controlCARD (E1, E2, or Rev.A), refer to the controlCARD + // documentation on steps to reconfigure the controlCARD from 20MHz to + // 25MHz. + // +//��� ����� �� ������ + + ESTOP0; + while(1); + } + + // + // Initialize the SYSPLL control to generate a 200Mhz clock + // + // Defined options to be passed as arguments to this function are defined + // in f2838x_examples.h. + // + // Note: The internal oscillator CANNOT be used as the PLL source if the + // PLLSYSCLK is configured to frequencies above 194 MHz. + // + // PLLSYSCLK = (XTAL_OSC) * (IMULT) /(REFDIV) * (ODIV) * (PLLSYSCLKDIV) + // + InitSysPll(XTAL_OSC, SYS_IMULT, SYS_REFDIV, SYS_ODIV, SYS_DIV, SYSCTL_DCC_BASE0); + + // + // Initialize the AUXPLL control to generate a 125Mhz clock: + // + // Defined options to be passed as arguments to this function are defined + // in f2838x_Examples.h. + // + // Note: The internal oscillator CANNOT be used as the PLL source if the + // AUXPLLCLK is configured to frequencies above 194 MHz. + // + // AUXPLLCLK = (XTAL_OSC) * (IMULT) /(REFDIV) * (ODIV) * (AUXPLLDIV) + // + InitAuxPll(XTAL_OSC, AUX_IMULT, AUX_REFDIV, AUX_ODIV, AUX_DIV, SYSCTL_DCC_BASE1); + + // + // Set up CMCLK to use AUXPLL as the clock source and set the + // clock divider to 1. + // + EALLOW; + ClkCfgRegs.CMCLKCTL.bit.CMCLKDIV = 0; // 0 : Divide by 1 + ClkCfgRegs.CMCLKCTL.bit.CMDIVSRCSEL = 0; // 0 : AuxPLL is the source for the CM clock divider. + EDIS; + +#ifndef _FLASH + // + // Call Device_cal function when run using debugger + // This function is called as part of the Boot code. The function is called + // in the InitSysCtrl function since during debug time resets, the boot code + // will not be executed and the gel script will reinitialize all the + // registers and the calibrated values will be lost. + // + Device_cal(); +#endif + +#endif // CPU1 + + // + // Turn on all peripherals + // +// InitPeripheralClocks(); +} + +// +// +// Function to verify the XTAL frequency +// freq is the XTAL frequency in MHz +// The function return true if the the actual XTAL frequency matches with the +// input value +// +// +#ifdef CPU1 +bool VerifyXTAL(float freq) +{ + // + // Configures XTAL as CLKSRC0 and INTOSC2 as CLKSRC1. + // Fclk0 = XTAL frequency (input parameter) + // Fclk1 = INTOSC2 frequency = 10MHz + // + // Calculating Counter0 & Valid Seed Value with +/-1% tolerance + // INTOSC can have a variance in frequency of +/-10% + // + // Since Fclk1 < Fclk0, then Async. Error (In Clock0 cycles) = + // 2*(Fclk0/Fclk1) + 2*(Fsysclk/Fclk0) + // Digitization error = 8 Clock0 cycles + // DCC Error (in Cycles) = 2*(Fclk0/Fclk1) + 2*(Fsysclk/Fclk0) + 8 + // Window (in Cycles) = (Total Error) / (0.01 * Tolerance) + // Error due to variance in frequency = Window * freqVariance + // Total error = DCC Error + Error due to variance in frequency + // Counter0 = Window - Total Error + // Valid0 = 2 * Total Error + // Counter1 = Window * (Fclk1/Fclk0) + // + // Note : Update the tolerance and INTOSC2 frequency variance as necessary. + // + uint32_t total_error = ceil((2.0F * freq/10.0F) + (2.0F * 10.0F/freq) + 8.0F); + uint32_t window = total_error / 0.01F; + total_error += window * 0.1F; + + uint32_t count0 = window - total_error; + uint32_t valid = 2 * total_error; + uint32_t count1 = window * 10 / freq; + + EALLOW; + + // + // Enable DCC0 clock + // + CpuSysRegs.PCLKCR21.bit.DCC0 = 1; + + // + // Insert atleast 5 cycles delay after enabling the peripheral clock + // + asm(" RPT #5 || NOP"); + + // + // Clear Error & Done Flag + // + Dcc0Regs.DCCSTATUS.bit.ERR = 1; + Dcc0Regs.DCCSTATUS.bit.DONE = 1; + + // + // Disable DCC + // + Dcc0Regs.DCCGCTRL.bit.DCCENA = 0x5; + + // + // Disable Error Signal + // + Dcc0Regs.DCCGCTRL.bit.ERRENA = 0x5; + + // + // Disable Done Signal + // + Dcc0Regs.DCCGCTRL.bit.DONEENA = 0x5; + + // + // Configure Clock Source0 to XTAL + // + Dcc0Regs.DCCCLKSRC0.all = (0xA << 12) | // bits 12..15 : Key + 0; // bits 0..4 : Source = XTAL(value 0) + + // + // Configure Clock Source1 to INTOSC + // + Dcc0Regs.DCCCLKSRC1.all = (0xA << 12) | // bits 12..15 : Key + 3; // bits 0..4 : Source = INTOS2(value 3) + + // + // Configure COUNTER-0, COUNTER-1 & Valid Window + // + Dcc0Regs.DCCCNTSEED0.all = count0; + Dcc0Regs.DCCCNTSEED1.all = count1; + Dcc0Regs.DCCVALIDSEED0.all = valid; + + // + // Enable Single Shot mode + // + Dcc0Regs.DCCGCTRL.bit.SINGLESHOT = 0xA; + + // + // Enable Error Signal + // + Dcc0Regs.DCCGCTRL.bit.ERRENA = 0xA; + + // + // Enable Done Signal + // + Dcc0Regs.DCCGCTRL.bit.DONEENA = 0xA; + + // + // Enable DCC to start counting + // + Dcc0Regs.DCCGCTRL.bit.DCCENA = 0xA; + + EDIS; + + // + // Wait until Error or Done Flag is generated + // + while((Dcc0Regs.DCCSTATUS.bit.DONE | Dcc0Regs.DCCSTATUS.bit.ERR) == 0); + + // + // Returns true if DCC completes without error + // + if (Dcc0Regs.DCCSTATUS.bit.DONE == 1U) + { + return true; + } + else + { + return false; + } + +} +#endif + +// +// InitPeripheralClocks - Initializes the clocks for the peripherals. +// +// Note: In order to reduce power consumption, turn off the clocks to any +// peripheral that is not specified for your part-number or is not used in the +// application +// +void InitPeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.bit.CLA1 = 1; + CpuSysRegs.PCLKCR0.bit.DMA = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; + CpuSysRegs.PCLKCR0.bit.CPUBGCRC = 1; + CpuSysRegs.PCLKCR0.bit.CLA1BGCRC = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR0.bit.HRCAL = 1; +#endif + + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; + CpuSysRegs.PCLKCR0.bit.ERAD = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR1.bit.EMIF1 = 1; + CpuSysRegs.PCLKCR1.bit.EMIF2 = 1; +#endif + + CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM9 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM10 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM11 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM12 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM13 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM14 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM15 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM16 = 1; + + CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP7 = 1; + + CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP3 = 1; + + CpuSysRegs.PCLKCR6.bit.SD1 = 1; + CpuSysRegs.PCLKCR6.bit.SD2 = 1; + + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + CpuSysRegs.PCLKCR7.bit.SCI_B = 1; + CpuSysRegs.PCLKCR7.bit.SCI_C = 1; + CpuSysRegs.PCLKCR7.bit.SCI_D = 1; + + CpuSysRegs.PCLKCR8.bit.SPI_A = 1; + CpuSysRegs.PCLKCR8.bit.SPI_B = 1; + CpuSysRegs.PCLKCR8.bit.SPI_C = 1; + CpuSysRegs.PCLKCR8.bit.SPI_D = 1; + + CpuSysRegs.PCLKCR9.bit.I2C_A = 1; + CpuSysRegs.PCLKCR9.bit.I2C_B = 1; + + CpuSysRegs.PCLKCR10.bit.CAN_A = 1; + CpuSysRegs.PCLKCR10.bit.CAN_B = 1; + + CpuSysRegs.PCLKCR11.bit.McBSP_A = 1; + CpuSysRegs.PCLKCR11.bit.McBSP_B = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR11.bit.USB_A = 1; +#endif + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS8 = 1; + + CpuSysRegs.PCLKCR16.bit.DAC_A = 1; + CpuSysRegs.PCLKCR16.bit.DAC_B = 1; + CpuSysRegs.PCLKCR16.bit.DAC_C = 1; + + CpuSysRegs.PCLKCR18.bit.FSITX_A = 1; + CpuSysRegs.PCLKCR18.bit.FSITX_B = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_A = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_B = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_C = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_D = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_E = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_F = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_G = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_H = 1; + + CpuSysRegs.PCLKCR20.bit.PMBUS_A = 1; + + CpuSysRegs.PCLKCR21.bit.DCC0 = 1; + CpuSysRegs.PCLKCR21.bit.DCC1 = 1; + CpuSysRegs.PCLKCR21.bit.DCC2 = 1; + + CpuSysRegs.PCLKCR23.bit.ETHERCAT = 1; + + EDIS; +} + +// +// DisablePeripheralClocks - Gates-off all peripheral clocks. +// +void DisablePeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.all = 0; + CpuSysRegs.PCLKCR1.all = 0; + CpuSysRegs.PCLKCR2.all = 0; + CpuSysRegs.PCLKCR3.all = 0; + CpuSysRegs.PCLKCR4.all = 0; + CpuSysRegs.PCLKCR6.all = 0; + CpuSysRegs.PCLKCR7.all = 0; + CpuSysRegs.PCLKCR8.all = 0; + CpuSysRegs.PCLKCR9.all = 0; + CpuSysRegs.PCLKCR10.all = 0; + CpuSysRegs.PCLKCR11.all = 0; + CpuSysRegs.PCLKCR13.all = 0; + CpuSysRegs.PCLKCR14.all = 0; + CpuSysRegs.PCLKCR16.all = 0; + CpuSysRegs.PCLKCR18.all = 0; + CpuSysRegs.PCLKCR20.all = 0; + CpuSysRegs.PCLKCR21.all = 0; + CpuSysRegs.PCLKCR22.all = 0; + CpuSysRegs.PCLKCR23.all = 0; + + EDIS; +} + +// +// InitFlash - This function initializes the Flash Control registers. +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. +// +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void InitFlash(void) +{ + EALLOW; + + // + // At reset bank and pump are in sleep. A Flash access will power up the + // bank and pump automatically. + // + // Power up Flash bank and pump. This also sets the fall back mode of + // flash and pump as active. + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; + + // + // Disable Cache and prefetch mechanism before changing wait states + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; + + // + // Set waitstates according to frequency + // + // *CAUTION* + // Minimum waitstates required for the flash operating at a given CPU rate + // must be characterized by TI. Refer to the datasheet for the latest + // information. + // + #if CPU_FRQ_200MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3; + #endif + + #if CPU_FRQ_150MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + #if CPU_FRQ_120MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + // + // Enable Cache and prefetch mechanism to improve performance of code + // executed from Flash. + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; + + EDIS; + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + __asm(" RPT #7 || NOP"); +} + +// +// FlashOff - This function powers down the flash +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. Also you must seize the flash pump in +// order to power it down. +// +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void FlashOff(void) +{ + EALLOW; + + // + // Power down bank + // + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; + + // + // Power down pump + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; + + EDIS; +} + + +// +// ServiceDog - This function resets the watchdog timer. +// +// Enable this function for using ServiceDog in the application. +// +void ServiceDog(void) +{ + EALLOW; + WdRegs.WDKEY.bit.WDKEY = 0x0055; + WdRegs.WDKEY.bit.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void DisableDog(void) +{ + volatile Uint16 temp; + + // + // Grab the clock config first so we don't clobber it + // + EALLOW; + temp = WdRegs.WDCR.all & 0x0007; + WdRegs.WDCR.all = 0x0068 | temp; + EDIS; +} + +#ifdef CPU1 +// +// InitPll - This function initializes the PLL registers. +// +// Note: This function uses the DCC to check that the PLLRAWCLK is running at +// the expected rate. The desirable DCC can be provided as a parameter. +// +void InitSysPll(Uint16 clock_source, Uint16 imult, Uint32 refdiv, Uint32 odiv, + Uint16 divsel, Uint32 dccbase) +{ + Uint32 timeout,temp_syspllmult, pllLockStatus; + bool status; + + if(((clock_source & 0x3) == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && + (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE) && + (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && + (refdiv == ClkCfgRegs.SYSPLLMULT.bit.REFDIV) && + (odiv == ClkCfgRegs.SYSPLLMULT.bit.ODIV) && + (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + EALLOW; + + // + // First modify the PLL multipliers if the multipliers need an update or PLL needs + // to be powered on / enabled + // + if((imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT) || + (refdiv != ClkCfgRegs.SYSPLLMULT.bit.REFDIV)|| + (odiv != ClkCfgRegs.SYSPLLMULT.bit.ODIV) || + (1U != ClkCfgRegs.SYSPLLCTL1.bit.PLLEN)) + { + // + // Bypass PLL and set dividers to /1 + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + asm(" RPT #120 || NOP"); + + // + // Evaluate PLL multipliers and dividers + // + temp_syspllmult = ((refdiv << 24U) | (odiv << 16U)| imult); + + // + // Turnoff the PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + + // + // Delay of at least 66 OSCCLK cycles + // + asm(" RPT #66 || NOP"); + + if(((clock_source & 0x3) != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) || + (((clock_source & 0x4) >> 2) != ClkCfgRegs.XTALCR.bit.SE)) + { + switch (clock_source) + { + case INT_OSC1: + SysIntOsc1Sel(); + break; + + case INT_OSC2: + SysIntOsc2Sel(); + break; + + case XTAL_OSC: + SysXtalOscSel(); + break; + + case XTAL_OSC_SE: + SysXtalOscSESel(); + break; + } + } + + // + // Delay of at least 60 OSCCLK cycles + // + asm(" RPT #60 || NOP"); + + EALLOW; + + // + // Set dividers to /1 to ensure the fastest PLL configuration + // + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; + + // + // Program PLL multipliers + // + ClkCfgRegs.SYSPLLMULT.all = temp_syspllmult; + + // + // Enable SYSPLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; + + // + // Lock time is 1024 OSCCLK * (REFDIV+1) + // + timeout = (1024U * (refdiv + 1U)); + pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; + + // + // Wait for the SYSPLL lock + // + while((pllLockStatus != 1) && (timeout != 0U)) + { + pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; + timeout--; + } + + EDIS; + + // + // Check PLL Frequency using DCC + // + status = IsPLLValid(dccbase, clock_source, INT_PLL_SYSPLL, + imult, odiv , refdiv); + + } + else + { + // + // Re-Lock of PLL not needed since the multipliers + // are not updated + // + status = true; + } + + if(status) + { + EALLOW; + // + // Set divider to produce slower output frequency to limit current increase + // + if(divsel != PLLCLK_BY_126) + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; + } + else + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + } + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Small 100 cycle delay + // + asm(" RPT #100 || NOP"); + + // + // Set the divider to user value + // + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + EDIS; + } + else + { + EALLOW; + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; + GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; + GpioDataRegs.GPADAT.bit.GPIO6 = 0; + + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0; + GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO7 = 1; + GpioDataRegs.GPADAT.bit.GPIO7 = 1; + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; + GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO10 = 1; + GpioDataRegs.GPADAT.bit.GPIO10 = 1; + EDIS; + ESTOP0; // If the frequency is out of range, stop here. + } +} + +// +// InitAuxPll - This function initializes the AUXPLL registers. +// +// Note: This function uses the DCC to check that the AUXPLLRAWCLK is running at +// the expected rate. The desirable DCC can be provided as a parameter. +// +void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint32 refdiv, Uint32 odiv, + Uint16 divsel, Uint32 dccbase) +{ + Uint16 started = 0 , status = 0; + + if((clock_source == ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL) && + (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE) && + (imult == ClkCfgRegs.AUXPLLMULT.bit.IMULT) && + (refdiv == ClkCfgRegs.SYSPLLMULT.bit.REFDIV) && + (odiv == ClkCfgRegs.SYSPLLMULT.bit.ODIV) && + (divsel == ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + // + // First modify the PLL multipliers + // + if((imult != ClkCfgRegs.AUXPLLMULT.bit.IMULT) || + (refdiv != ClkCfgRegs.AUXPLLMULT.bit.REFDIV)|| + (odiv != ClkCfgRegs.AUXPLLMULT.bit.ODIV) || + (1U != ClkCfgRegs.AUXPLLCTL1.bit.PLLEN)) + { + EALLOW; + + // + // Bypass PLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + asm(" RPT #120 || NOP"); + + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; // Turn off AUXPLL + + // + // Delay of at least 66 OSCCLK cycles + // + asm(" RPT #66 || NOP"); + + // + // Configure oscillator source + // + switch (clock_source) + { + case INT_OSC2: + AuxIntOsc2Sel(); + break; + + case XTAL_OSC: + AuxXtalOscSel(); + break; + + case XTAL_OSC_SE: + AuxXtalOscSESel(); + break; + + case AUXCLKIN: + AuxAuxClkSel(); + break; + } + + // + // Delay of at least 60 OSCCLK cycles + // + asm(" RPT #60 || NOP"); + + EALLOW; + // + // Set integer multiplier and dividers, which automatically turns on + // the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((refdiv << 24U) | (odiv << 16U) | imult); + + // + // Enable AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + + status = IsPLLValid(dccbase, clock_source, INT_PLL_AUXPLL, + imult, odiv , refdiv); + + // + // Check DCC Status + // + if(status) + { + started = 1; + } + + // + // Enable AUXPLLCLK to be fed from AUX PLL + // + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + EDIS; + + if(started == 0) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass PLL). + // + EALLOW; + ClkCfgRegs.AUXPLLMULT.all = 0; + EDIS; + + // + // The user should put some handler code here based on how this + // condition should be handled in their application. + // + asm(" ESTOP0"); + } + } + + // + // Set divider to desired value + // + EALLOW; + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = divsel; + + EDIS; +} +#endif + +// +// CsmUnlock - This function unlocks the CSM. User must replace the default +// value with the current password for the DSP. +// +Uint16 CsmUnlock(void) +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. These values are + // default passwords for the first ZSB. User should replace them with + // the correct password for the DSP. + // + EALLOW; + DcsmZ1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY1 = 0x4D7FFFFF; + DcsmZ1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; + + DcsmZ2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY1 = 0x3FFFFFFF; + DcsmZ2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; + EDIS; + + return(0); +} + +// +// SysIntOsc1Sel - This function switches to Internal Oscillator 1. +// +void SysIntOsc1Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + EDIS; +} + +// +// SysIntOsc2Sel - This function switches to Internal oscillator 2. +// +void SysIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + EDIS; +} + +// +// PollX1Counter - Clear the X1CNT counter and then wait for it to saturate +// four times. +// +static void +PollX1Counter(void) +{ + Uint16 loopCount = 0; + + // + // Delay for 1 ms while the XTAL powers up + // + // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles + // + F28x_usDelay(2000); + + // + // Clear and saturate X1CNT 4 times to guarantee operation + // + do + { + // + // Keep clearing the counter until it is no longer saturated + // + while(ClkCfgRegs.X1CNT.all > 0x1FF) + { + ClkCfgRegs.X1CNT.bit.CLR = 1; + ClkCfgRegs.X1CNT.bit.CLR = 0; + } + + // + // Wait for the X1 clock to saturate + // + while(ClkCfgRegs.X1CNT.all != 0x3FFU) + { + ; + } + + // + // Increment the counter + // + loopCount++; + }while(loopCount < 4); +} +// SysXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void SysXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC + ClkCfgRegs.XTALCR.bit.SE = 0; // Select crystal mode + EDIS; + + // + // Wait for the X1 clock to saturate + // + PollX1Counter(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; + EDIS; + + // + // If a missing clock failure was detected, try waiting for the X1 counter + // to saturate again. Consider modifying this code to add a 10ms timeout. + // + while(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) + { + EALLOW; + ClkCfgRegs.MCDCR.bit.MCLKCLR = 1; + EDIS; + + // + // Wait for the X1 clock to saturate + // + PollX1Counter(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; + EDIS; + } +} +// +// SysXtalOscSESel - This function switches to external oscillator in +// single-ended mode and turns off all other clock sources to minimize power +// consumption. This option may not be available on all device packages +// +void +SysXtalOscSESel (void) +{ + EALLOW; + ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC + ClkCfgRegs.XTALCR.bit.SE = 1; // Select single-ended mode + EDIS; + + // + // Wait for the X1 clock to saturate + // + PollX1Counter(); + + // + // Select XTALOSC as the oscillator source + // + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; + EDIS; + + // + // If missing clock detected, there is something wrong with the oscillator + // module. + // + if(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) + { + + ESTOP0; + } +} +// +// AuxIntOsc2Sel - This function switches to Internal oscillator 2. +// +void AuxIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + EDIS; +} + +// +// AuxXtalOscSel - This function switches to External CRYSTAL oscillator in +// crystal mode. +// +void AuxXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.XTALCR.bit.SE = 0; // Select crystal mode + PollX1Counter(); // Wait for the X1 clock to saturate + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxXtalOscSESel - This function switches to External CRYSTAL oscillator in +// single-ended mode. +// +void AuxXtalOscSESel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.XTALCR.bit.SE = 1; // Select single-ended mode + PollX1Counter(); // Wait for the X1 clock to saturate + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} +// +// AuxAuxClkSel - This function switches to AUXCLKIN (from a GPIO). +// +void AuxAuxClkSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = XTAL + EDIS; +} + +// +// IDLE - Enter IDLE mode (single CPU). +// +void IDLE(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; + EDIS; + asm(" IDLE"); +} + +// +// STANDBY - Enter STANDBY mode (single CPU). +// +void STANDBY(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_STANDBY; + EDIS; + asm(" IDLE"); +} + +#ifdef CPU1 +// +// IsPLLValid - This function validates PLL Raw Clock Frequency +// +bool +IsPLLValid(Uint32 base, Uint16 oscSource, Uint16 pllclk, Uint16 imult, + Uint16 odiv, Uint16 refdiv) +{ + float fclk1_0ratio; + volatile struct DCC_REGS *DccRegs; + + EALLOW; + + // + // Assigning DCC for PLL validation + // Enable Peripheral Clock Domain PCLKCR21 for DCC + // + if(base == SYSCTL_DCC_BASE0) + { + DccRegs = &Dcc0Regs; + CpuSysRegs.PCLKCR21.bit.DCC0 = 1; + } + else if(base == SYSCTL_DCC_BASE1) + { + DccRegs = &Dcc1Regs; + CpuSysRegs.PCLKCR21.bit.DCC1 = 1; + } + else if(base == SYSCTL_DCC_BASE2) + { + DccRegs = &Dcc2Regs; + CpuSysRegs.PCLKCR21.bit.DCC2 = 1; + } + else + { + EALLOW; + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; + GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; + GpioDataRegs.GPADAT.bit.GPIO6 = 0; + + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0; + GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO7 = 1; + GpioDataRegs.GPADAT.bit.GPIO7 = 1; + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; + GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO10 = 1; + GpioDataRegs.GPADAT.bit.GPIO10 = 0; + EDIS; + ESTOP0; // Invalid DCC selected + } + // + // Clear Error & Done Flag + // + DccRegs->DCCSTATUS.bit.ERR = 1; + DccRegs->DCCSTATUS.bit.DONE = 1; + + // + // Disable DCC + // + DccRegs->DCCGCTRL.bit.DCCENA = 0x5; + + // + // Disable Error Signal + // + DccRegs->DCCGCTRL.bit.ERRENA = 0x5; + + // + // Disable Done Signal + // + DccRegs->DCCGCTRL.bit.DONEENA = 0x5; + + // + // Configure Clock Source1 to PLL + // + // Clk Src1 Key 0xA to enable clock source selection + // + switch(pllclk) + { + case INT_PLL_SYSPLL: + DccRegs->DCCCLKSRC1.all = 0xA000; // Clk Src1 = SYSPLL + break; + + case INT_PLL_AUXPLL: + DccRegs->DCCCLKSRC1.all = 0xA001; // Clk Src1 = AUXPLL + break; + + default: + // + // Code shouldn't reach here + // + break; + } + + // + // Configure Clock Source0 to whatever is set as a reference + // clock source for PLL + // + // Clk Src0 Key 0xA to enable clock source selection + // + switch(oscSource) + { + case INT_OSC1: + DccRegs->DCCCLKSRC0.all = 0xA001; // Clk Src0 = INTOSC1 + break; + + case INT_OSC2: + DccRegs->DCCCLKSRC0.all = 0xA002; // Clk Src0 = INTOSC2 + break; + + case XTAL_OSC: + case XTAL_OSC_SE: + DccRegs->DCCCLKSRC0.all = 0xA000; // Clk Src0 = XTAL + break; + + default: + // + // Code shouldn't reach here + // + break; + } + + // + // Calculating frequency ratio of output clock(f1) vs reference clock(f0) + // + fclk1_0ratio = (float)imult / ((odiv + 1U) * (refdiv + 1)); + + // + // Computing and configuring Counter0 , Counter1 & Valid Seed Values + // with +/-1% tolerance for the desired DCC + // + ComputeCntrSeedValue(base, fclk1_0ratio, DCC_COUNTER0_TOLERANCE); + + // + // Enable Single Shot Mode + // + DccRegs->DCCGCTRL.bit.SINGLESHOT = 0xA; + + // + // Enable DCC to start counting + // + DccRegs->DCCGCTRL.bit.DCCENA = 0xA; + EDIS; + + // + // Wait until Error or Done Flag is generated + // + while((DccRegs->DCCSTATUS.all & 3) == 0) + { + } + + // + // Returns true if DCC completes without error + // + return((DccRegs->DCCSTATUS.all & 3) == 2); + +} + +//***************************************************************************** +// +// ComputeCntSeedValid - Compute Counter seed values based on the frequency ratio of output +// clock vs reference clock & tolerance expected for the desired DCC +// +//***************************************************************************** +void ComputeCntrSeedValue(Uint32 base, float fclk1_0ratio, Uint32 tolerance) +{ + Uint32 window, dccCounterSeed0, dccValidSeed0, dccCounterSeed1, total_error; + volatile struct DCC_REGS *DccRegs; + + if(fclk1_0ratio >= 1U) + { + // + // Setting Counter0 & Valid Seed Value with expected tolerance + // Total error is 12 + // + window = (12U * 100U) / tolerance; + dccCounterSeed0 = window - 12U; + dccValidSeed0 = 24U; + + } + else + { + total_error = (((Uint32)2U / fclk1_0ratio) + (Uint32)10U); + + window = ((total_error * 100U)/ tolerance); + + // + // Setting Counter0 & Valid Seed Value with expected tolerance + // + dccCounterSeed0 = window - total_error; + dccValidSeed0 = (Uint32)2U * total_error; + + } + + // + // Multiplying Counter-0 window with PLL Integer Multiplier + // + dccCounterSeed1 = window * fclk1_0ratio; + + // + // Assigning DCC for PLL validation + // + if(base == SYSCTL_DCC_BASE0) + DccRegs = &Dcc0Regs; + else if(base == SYSCTL_DCC_BASE1) + DccRegs = &Dcc1Regs; + else if(base == SYSCTL_DCC_BASE2) + DccRegs = &Dcc2Regs; + else + { + EALLOW; + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; + GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; + GpioDataRegs.GPADAT.bit.GPIO6 = 1; + + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0; + GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO7 = 1; + GpioDataRegs.GPADAT.bit.GPIO7 = 1; + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; + GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO10 = 1; + GpioDataRegs.GPADAT.bit.GPIO10 = 1; + EDIS; + ESTOP0; // Invalid DCC selected + } + // + // Configure COUNTER-0, COUNTER-1 & Valid Window + // + DccRegs->DCCCNTSEED0.bit.COUNTSEED0 = dccCounterSeed0; // Loaded Counter0 Value + DccRegs->DCCVALIDSEED0.bit.VALIDSEED = dccValidSeed0; // Loaded Valid Value + DccRegs->DCCCNTSEED1.bit.COUNTSEED1 = dccCounterSeed1; // Loaded Counter1 Value +} +#endif + +// +// End of File +// + diff --git a/EFC_PlatformC28x/lib/f2838x_usdelay.asm b/EFC_PlatformC28x/lib/f2838x_usdelay.asm new file mode 100644 index 0000000..a29cb5c --- /dev/null +++ b/EFC_PlatformC28x/lib/f2838x_usdelay.asm @@ -0,0 +1,108 @@ +;//########################################################################### +;// +;// FILE: f2838x_usdelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// To use this function: +;// 1 - update the CPU clock speed in the f2838x_examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the f2838x_device.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// extern void Delay(long LoopCount); +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// Or as follows (if count is less then 16-bits): +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;//########################################################################### +;// +;// +;// $Copyright: +;// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + + .if __TI_EABI__ + .asg F28x_usDelay, _F28x_usDelay + .endif + .def _F28x_usDelay + + .cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro + %{ + %} + + .if __TI_COMPILER_VERSION__ + .if __TI_COMPILER_VERSION__ >= 15009000 + .sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer + .else + .sect "ramfuncs" ;;Used with compilers older than v15.9.0 + .endif + .endif + + .global __F28x_usDelay +_F28x_usDelay: + SUB ACC,#1 + BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +; + +;// +;// End of file +;// diff --git a/EFC_PlatformC28x_Test/.ccsproject b/EFC_PlatformC28x_Test/.ccsproject new file mode 100644 index 0000000..88e5593 --- /dev/null +++ b/EFC_PlatformC28x_Test/.ccsproject @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/EFC_PlatformC28x_Test/.cproject b/EFC_PlatformC28x_Test/.cproject new file mode 100644 index 0000000..dfa9992 --- /dev/null +++ b/EFC_PlatformC28x_Test/.cproject @@ -0,0 +1,383 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/EFC_PlatformC28x_Test/.gitignore b/EFC_PlatformC28x_Test/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/EFC_PlatformC28x_Test/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/EFC_PlatformC28x_Test/.launches/EFC_PlatformC28x_Test.launch b/EFC_PlatformC28x_Test/.launches/EFC_PlatformC28x_Test.launch new file mode 100644 index 0000000..0bf1bc7 --- /dev/null +++ b/EFC_PlatformC28x_Test/.launches/EFC_PlatformC28x_Test.launch @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EFC_PlatformC28x_Test/.project b/EFC_PlatformC28x_Test/.project new file mode 100644 index 0000000..1c0ce90 --- /dev/null +++ b/EFC_PlatformC28x_Test/.project @@ -0,0 +1,28 @@ + + + EFC_PlatformC28x_Test + + + EFC_PlatformC28x + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/EFC_PlatformC28x_Test/.settings/org.eclipse.cdt.codan.core.prefs b/EFC_PlatformC28x_Test/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/EFC_PlatformC28x_Test/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/EFC_PlatformC28x_Test/.settings/org.eclipse.cdt.debug.core.prefs b/EFC_PlatformC28x_Test/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000..2adc7b1 --- /dev/null +++ b/EFC_PlatformC28x_Test/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/EFC_PlatformC28x_Test/.settings/org.eclipse.core.resources.prefs b/EFC_PlatformC28x_Test/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..093dbb9 --- /dev/null +++ b/EFC_PlatformC28x_Test/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,6 @@ +eclipse.preferences.version=1 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/EFC_PlatformC28x_Test/2838x_ram_lnk_cpu1.cmd b/EFC_PlatformC28x_Test/2838x_ram_lnk_cpu1.cmd new file mode 100644 index 0000000..2880a19 --- /dev/null +++ b/EFC_PlatformC28x_Test/2838x_ram_lnk_cpu1.cmd @@ -0,0 +1,58 @@ +MEMORY +{ +PAGE 0: + BEGIN: origin = 0x000000, length = 0x000002 + BOOT_RSVD: origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */ + + RAM_M: origin = 0x0001B0, length = 0x000650 + RAM_D: origin = 0x00C000, length = 0x001000 + RAM_LS: origin = 0x008000, length = 0x004000 + + CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800 + CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800 + + CPUTOCMRAM : origin = 0x039000, length = 0x000800 + CMTOCPURAM : origin = 0x038000, length = 0x000800 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + +PAGE 1: + + RAM_GS: origin = 0x00D000, length = 0x010000 + +} + + +SECTIONS +{ + codestart : > BEGIN + + .text : > RAM_GS + + .cinit : > RAM_D + .switch : > RAM_D + + .reset : > BEGIN, TYPE = DSECT /* not used, */ + + .stack : > RAM_M + + .bss : > RAM_D + .bss:output : > RAM_D + .init_array : > RAM_D + .const : > RAM_D + .data : > RAM_D + .sysmem : > RAM_LS + + MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT + MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT + MSGRAM_CPU_TO_CM > CPUTOCMRAM, type=NOINIT + MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/EFC_PlatformC28x_Test/AsyncRunner.cpp b/EFC_PlatformC28x_Test/AsyncRunner.cpp new file mode 100644 index 0000000..18b0c54 --- /dev/null +++ b/EFC_PlatformC28x_Test/AsyncRunner.cpp @@ -0,0 +1,115 @@ +/** + * \file AsyncRunner.cpp + * \project EFC_PlatformC28x_Test + * + * Created on: 20 мая 2024 г. + * Author: leonid + */ + +#include "AsyncRunner.hh" + +#include +#include +#include + +void (*cputimer1_pfinthandler)(); +bool cputimer1_first_run; + +__interrupt void cputimer1_interrupt() { + + if( cputimer1_first_run ) + cputimer1_pfinthandler(); + + CPUTimer_stopTimer(CPUTIMER1_BASE); + + cputimer1_first_run = false; + +} + +void cputimer1_init( void (*interrupt_handler)() ) { + + cputimer1_pfinthandler = interrupt_handler; + + Interrupt_register( INT_TIMER1, &cputimer1_interrupt ); + Interrupt_enable(INT_TIMER1); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); + CPUTimer_stopTimer(CPUTIMER1_BASE); + CPUTimer_setPreScaler(CPUTIMER1_BASE, CPUTIMER_CLOCK_PRESCALER_1); + CPUTimer_enableInterrupt(CPUTIMER1_BASE); + +} + +//Запуск таймера +void cputimer1_run( uint32_t processor_tick ) { + + CPUTimer_setPeriod( CPUTIMER1_BASE, processor_tick + 1 ); + CPUTimer_reloadTimerCounter(CPUTIMER1_BASE); + CPUTimer_clearOverflowFlag( CPUTIMER1_BASE ); + + cputimer1_first_run = true; + + CPUTimer_startTimer(CPUTIMER1_BASE); + + //Задержка для гарантии входа в прерывание, исключения непокрытого + // кода после выполнения функции из-за отзывчивости прерываний. + for( volatile int i = 0; i < 4; i++ ); + +} + +void cputimer1_stop() { + + CPUTimer_stopTimer(CPUTIMER1_BASE); + +} + + +void platform::AsyncRunner::async_run() { + + platform::AsyncRunner::getInstance().run(); + +} + +platform::AsyncRunner::AsyncRunner() : task(0), ran(false) { + + cputimer1_init( &async_run ); + +} + +void platform::AsyncRunner::run_after( umlib::tests::TaskInterface * new_task, + uint32_t processor_tick ) { + + task = new_task; + ran = false; + + cputimer1_run(processor_tick); + +} + +void platform::AsyncRunner::cancel() { + + cputimer1_stop(); + +} + +bool platform::AsyncRunner::is_ran() { + + return ran; + +} + +void platform::AsyncRunner::run() { + + if( task ) { + task->do_task(); + ran = true; + } + +} + +platform::AsyncRunner & platform::AsyncRunner::getInstance() { + + static AsyncRunner instance; + return instance; + +} diff --git a/EFC_PlatformC28x_Test/AsyncRunner.hh b/EFC_PlatformC28x_Test/AsyncRunner.hh new file mode 100644 index 0000000..41ddb3e --- /dev/null +++ b/EFC_PlatformC28x_Test/AsyncRunner.hh @@ -0,0 +1,38 @@ +/* + * AsyncRunner.hh + * + * Created on: 19 мая 2024 г. + * Author: leonid + */ + +#ifndef ASYNCRUNNER_HH_ +#define ASYNCRUNNER_HH_ + +#include "AsyncRunnerInterface.hh" + +namespace platform { + +class AsyncRunner : public umlib::tests::AsyncRunnerInterface { + + AsyncRunner(); + + umlib::tests::TaskInterface * task; + bool ran; + + static void async_run(); + void run(); + +public: + void run_after( umlib::tests::TaskInterface * task, uint32_t processor_tick ); + void cancel(); + bool is_ran(); + + static AsyncRunner & getInstance(); + +}; + +} + + + +#endif /* ASYNCRUNNER_HH_ */ diff --git a/EFC_PlatformC28x_Test/AsyncRunnerInterface.hh b/EFC_PlatformC28x_Test/AsyncRunnerInterface.hh new file mode 100644 index 0000000..40ab571 --- /dev/null +++ b/EFC_PlatformC28x_Test/AsyncRunnerInterface.hh @@ -0,0 +1,31 @@ +/* + * AsyncRunnerInterface.hh + * + * Created on: 20 мая 2024 г. + * Author: leonid + */ + +#ifndef ASYNCRUNNERINTERFACE_HH_ +#define ASYNCRUNNERINTERFACE_HH_ + +#include + +namespace umlib { namespace tests { + +struct TaskInterface { + + virtual void do_task() = 0; + +}; + +struct AsyncRunnerInterface { + + virtual void run_after( TaskInterface * task, uint32_t processor_tick ) = 0; + virtual void cancel() = 0; + virtual bool is_ran() = 0; + +}; + +}} + +#endif /* ASYNCRUNNERINTERFACE_HH_ */ diff --git a/EFC_PlatformC28x_Test/AsyncRunnerTest.cpp b/EFC_PlatformC28x_Test/AsyncRunnerTest.cpp new file mode 100644 index 0000000..e11c6a6 --- /dev/null +++ b/EFC_PlatformC28x_Test/AsyncRunnerTest.cpp @@ -0,0 +1,92 @@ +/* + * \file AsyncRunnerTest.cpp + * \project EFC_PlatformC28x_Test + * + * \date 21 мая 2024 г. + * \author leonid + */ + +#include "AsyncRunnerTest.hh" + +void umlib::tests::AsyncRunnerTest::OnceCallTask::reset() { + + counter = 0; + +} + +void umlib::tests::AsyncRunnerTest::OnceCallTask::do_task() { + + ++counter; + +} + +umlib::tests::AsyncRunnerTest::AsyncRunnerTest( umlib::tests::AsyncRunnerInterface & async_runner ) : runner(async_runner) {} + +void umlib::tests::AsyncRunnerTest::run( TestResult & result ) { + + test_once_call_on_zero(result); + test_once_call_on_one(result); + test_ran_after_run(result); + test_cancel(result); + +} + +void umlib::tests::AsyncRunnerTest::test_once_call_on_zero( TestResult & result ) { + + OnceCallTask once_call_task; + + once_call_task.reset(); + + runner.run_after( &once_call_task, 0 ); + + for( volatile int i = 0; i < 1; i++ ); + + result.assert_true( once_call_task.counter == 1, "AsyncRunner call task once with 0"); + +} + +void umlib::tests::AsyncRunnerTest::test_once_call_on_one( + TestResult & result ) { + + OnceCallTask once_call_task; + + once_call_task.reset(); + + runner.run_after( &once_call_task, 1 ); + + for( volatile int i = 0; i < 2; i++ ); + + result.assert_true( once_call_task.counter == 1, "AsyncRunner call task once with 1"); + +} + +void umlib::tests::AsyncRunnerTest::test_ran_after_run( + TestResult & result ) { + + OnceCallTask once_call_task; + + once_call_task.reset(); + + runner.run_after( &once_call_task, 1 ); + + for( volatile int i = 0; i < 64; i++ ); + + result.assert_true( runner.is_ran(), "AsyncRunner ran after run"); + +} + +void umlib::tests::AsyncRunnerTest::test_cancel( TestResult & result ) { + + OnceCallTask once_call_task; + + once_call_task.reset(); + + runner.run_after( &once_call_task, 200 ); + runner.cancel(); + + for( volatile int i = 0; i < 200; i++ ); + + result.assert_false( runner.is_ran(), "AsyncRunner not ran after cancel"); + result.assert_true( once_call_task.counter == 0, "AsyncRunner not call task after cancel"); + +} diff --git a/EFC_PlatformC28x_Test/AsyncRunnerTest.hh b/EFC_PlatformC28x_Test/AsyncRunnerTest.hh new file mode 100644 index 0000000..4ed26cd --- /dev/null +++ b/EFC_PlatformC28x_Test/AsyncRunnerTest.hh @@ -0,0 +1,48 @@ +/* + * AsyncRunnerTest.hh + * + * Created on: 21 мая 2024 г. + * Author: leonid + */ + +#ifndef ASYNCRUNNERTEST_HH_ +#define ASYNCRUNNERTEST_HH_ + +#include "UnitTestInterface.hh" + +#include "AsyncRunnerInterface.hh" + +namespace umlib { namespace tests { + +class AsyncRunnerTest : public UnitTestInterface { + + AsyncRunnerInterface & runner; + + struct OnceCallTask : public TaskInterface { + + int counter; + + void reset(); + + void do_task(); + + }; + +public: + AsyncRunnerTest( AsyncRunnerInterface & runner ); + + void run( TestResult & result ); + + void test_once_call_on_zero( TestResult & result ); + void test_once_call_on_one( TestResult & result ); + void test_ran_after_run( TestResult & result ); + void test_cancel( TestResult & result ); + +}; + + +}} + + + +#endif /* ASYNCRUNNERTEST_HH_ */ diff --git a/EFC_PlatformC28x_Test/AtomicTest.hpp b/EFC_PlatformC28x_Test/AtomicTest.hpp new file mode 100644 index 0000000..c23a965 --- /dev/null +++ b/EFC_PlatformC28x_Test/AtomicTest.hpp @@ -0,0 +1,238 @@ +/* + * AtomicTest.hpp + * + * Created on: 25 сент. 2078 г. + * Author: leonid + */ + +#ifndef ATOMICTEST_HPP_ +#define ATOMICTEST_HPP_ + +#include "UnitTestInterface.hh" +#include "AsyncRunnerInterface.hh" + +namespace umlib { namespace tests { + +template +class AtomicFlagTest : public UnitTestInterface { + + typedef AtomicFlagImlementation AtomicFlagImpl; + +public: + AtomicFlagTest( AsyncRunnerInterface & runner ); + ~AtomicFlagTest(); + + void run( TestResult & test_result ); + +private: + AsyncRunnerInterface & runner; + + void test_create( TestResult & test_result ); + void test_create_volatile( TestResult & test_result ); + void test_set_after_test_and_set( TestResult & test_result ); + void test_set_after_test_and_set_volatile( TestResult & test_result ); + void test_clear_after_create( TestResult & test_result ); + void test_clear_after_create_volatile( TestResult & test_result ); + void test_clear( TestResult & test_result ); + void test_clear_volatile( TestResult & test_result ); + + void test_once_set( TestResult & test_result ); + void test_once_set_volatile( TestResult & test_result ); + + struct AtomicFlagTrySet : public TaskInterface { + + AtomicFlagImpl flag; + + volatile bool on_task = false; + volatile bool on_main = false; + + void reset() { + + on_task = false; + on_main = false; + + flag.clear(); + + } + + void do_task() { + + on_task = not flag.test_and_set(); + + } + + void do_main() { + + on_main = not flag.test_and_set(); + + } + + bool fault() { + + return (on_task and on_main) or + (not on_task and not on_main); + + } + + }; + +}; + +} +} + +template +inline umlib::tests::AtomicFlagTest::AtomicFlagTest( AsyncRunnerInterface & new_runner ) : runner(new_runner) {} + +template +inline umlib::tests::AtomicFlagTest::~AtomicFlagTest() {} + +template +inline void umlib::tests::AtomicFlagTest::run( TestResult & test_result ) { + + test_create( test_result ); + test_create_volatile( test_result ); + test_set_after_test_and_set( test_result ); + test_set_after_test_and_set_volatile( test_result ); + test_clear(test_result); + test_clear_volatile(test_result); + test_clear_after_create(test_result); + test_clear_after_create_volatile(test_result); + test_once_set(test_result); + +} + +template +inline void umlib::tests::AtomicFlagTest::test_create( + TestResult & test_result ) { + + AtomicFlagImpl flag; + + test_result.assert_false( flag.test_and_set(), "AtomicFlag is clear after create"); + +} + +template +inline void umlib::tests::AtomicFlagTest::test_create_volatile( + TestResult & test_result) { + + volatile AtomicFlagImpl flag; + + test_result.assert_false( flag.test_and_set(), "Volatile AtomicFlag is clear after create"); + +} + +template +inline void umlib::tests::AtomicFlagTest::test_set_after_test_and_set( + TestResult & test_result ) { + + AtomicFlagImpl flag; + + (void) flag.test_and_set(); + + test_result.assert_true( flag.test_and_set(), "AtomicFlag is set after *test_and_set*"); + +} + +template +inline void umlib::tests::AtomicFlagTest::test_set_after_test_and_set_volatile( + TestResult & test_result ) { + + volatile AtomicFlagImpl flag; + + (void) flag.test_and_set(); + + test_result.assert_true( flag.test_and_set(), "Volatile AtomicFlag is set after *test_and_set*"); + +} + +template +inline void umlib::tests::AtomicFlagTest::test_clear( + TestResult & test_result ) { + + AtomicFlagImpl flag; + + (void) flag.test_and_set(); + flag.clear(); + + test_result.assert_false( flag.test_and_set(), "AtomicFlag is clear after *clear*"); + +} + +template +inline void umlib::tests::AtomicFlagTest::test_clear_volatile( + TestResult & test_result ) { + + volatile AtomicFlagImpl flag; + + (void) flag.test_and_set(); + flag.clear(); + + test_result.assert_false( flag.test_and_set(), "AtomicFlag is clear after *clear*"); + +} + +template +inline void umlib::tests::AtomicFlagTest::test_clear_after_create( + TestResult & test_result ) { + + AtomicFlagImpl flag; + + flag.clear(); + + test_result.assert_false( flag.test_and_set(), "AtomicFlag is clear after create and *clear*"); + +} + +template +inline void umlib::tests::AtomicFlagTest::test_clear_after_create_volatile( + TestResult & test_result ) { + + volatile AtomicFlagImpl flag; + + flag.clear(); + + test_result.assert_false( flag.test_and_set(), "Volatile AtomicFlag is clear after create and *clear*"); + +} + +namespace umlib { namespace tests { namespace detail { + + + +}}} + +template +inline void umlib::tests::AtomicFlagTest::test_once_set( + TestResult & test_result ) { + + AtomicFlagTrySet flag_check; + + uint32_t tick = 0; + + bool fault = false; + + do { + flag_check.reset(); + + runner.run_after( &flag_check, tick++ ); + + flag_check.do_main(); + + runner.cancel(); + + fault = fault or flag_check.fault(); + + } while( runner.is_ran() ); //and not fault + + test_result.assert_false(fault, "AtomicFlag provide atomically test_and_set"); + +} + +template +inline void umlib::tests::AtomicFlagTest::test_once_set_volatile( + TestResult &test_result) +{ +} + +#endif /* ATOMICTEST_HPP_ */ diff --git a/EFC_PlatformC28x_Test/Diakont-A.jpg b/EFC_PlatformC28x_Test/Diakont-A.jpg new file mode 100644 index 0000000..2df3b85 Binary files /dev/null and b/EFC_PlatformC28x_Test/Diakont-A.jpg differ diff --git a/EFC_PlatformC28x_Test/README.md b/EFC_PlatformC28x_Test/README.md new file mode 100644 index 0000000..f4b31fe --- /dev/null +++ b/EFC_PlatformC28x_Test/README.md @@ -0,0 +1,31 @@ +# `Universal modulary Library ` +![](Diakont-A.jpg) +[![Build Status](https://github.com/OpenEtherCATsociety/SOEM/workflows/build/badge.svg?branch=master)](http://sofdev:3000/Industrial/UMLibrary.git/actions?workflow=build) +## `EFC_PlatformC28xTest` +# Тестовый фреймворк на TMS320F28388D для кроссплатформенной библиотеки UMLibrary +## Overview +Это исходный код на C++ проекта EFC_PlatformC28xTest для процессора TMS320F28388D. +Сам проект расположен [здесь](http://sofdev:3000/Industrial/EFC_PlatformC28xTest). +Проект предназначен для тестирования использования atomic +### Технические детали +Это супер проект!! Он предназначен для тестирования проекта [EFC_PlatformC28x](http://sofdev:3000/Industrial/EFC_PlatformC28x.git), в частности реализации (и работы) AtomicFlag. +### Подключение (но это не точно) +При включении его как библиотеки, нужно любым образом определить следующие переменные: + + COMMON_FLAGS - для флагов компиляции + COMMON_INCLUDES - для дополнительных включений +### Документация +Пока ничего не написано. + +# Версия +#### `Текущая версия: 1.0 ` + +## Usage +Проект предназначен для CCS (ver.>12.4). + +## Building +Запустить проект, что для этого нужно: + +## Troubleshooting +— пока не найдены + diff --git a/EFC_PlatformC28x_Test/SdfmTest.hpp b/EFC_PlatformC28x_Test/SdfmTest.hpp new file mode 100644 index 0000000..fdc081a --- /dev/null +++ b/EFC_PlatformC28x_Test/SdfmTest.hpp @@ -0,0 +1,53 @@ +/* + * SdfmTest.hpp + * + * Created on: 27 авг. 2024 г. + * Author: sedov + */ + +#ifndef SDFMTEST_HPP_ +#define SDFMTEST_HPP_ + +#include "UnitTestInterface.hh" +namespace umlib { namespace tests { +template +class SdfmTest : public UnitTestInterface { + typedef SdfmImplementation SdfmImpl; +public: + + SdfmTest(); + ~SdfmTest(); + void run( TestResult & test_result ); +private: + void test_create( TestResult & test_result ); + + + }; +// +template +inline umlib::tests::SdfmTest::SdfmTest() { + // +} + +template +inline umlib::tests::SdfmTest::~SdfmTest() { + // +} + +template +inline void umlib::tests::SdfmTest::run( TestResult & test_result ) { + test_create( test_result ); +} + +template +inline void umlib::tests::SdfmTest::test_create(TestResult & test_result ) { + + SdfmImpl flag; + + test_result.assert_true( flag.teast_SDFM1(), "SDFM Itterputs is instialize"); + +} + } + } + +#endif /* SDFMTEST_HPP_ */ diff --git a/EFC_PlatformC28x_Test/UnitTestInterface.hh b/EFC_PlatformC28x_Test/UnitTestInterface.hh new file mode 100644 index 0000000..3d12d3a --- /dev/null +++ b/EFC_PlatformC28x_Test/UnitTestInterface.hh @@ -0,0 +1,32 @@ +/* + * UnitTestInterface.hh + * + * Created on: 25 сент. 2078 г. + * Author: leonid + */ + +#ifndef UNITTESTINTERFACE_HH_ +#define UNITTESTINTERFACE_HH_ + +#include + +namespace umlib { namespace tests { + +struct TestResult { + + virtual void assert_false( bool, std::string description ) = 0; + virtual void assert_true( bool, std::string description ) = 0; + +}; + +struct UnitTestInterface { + + virtual void run( TestResult & test_result ) = 0; + +}; + +}} + + + +#endif /* UNITTESTINTERFACE_HH_ */ diff --git a/EFC_PlatformC28x_Test/f2838x_headers_nonBIOS_cpu1.cmd b/EFC_PlatformC28x_Test/f2838x_headers_nonBIOS_cpu1.cmd new file mode 100644 index 0000000..475a56a --- /dev/null +++ b/EFC_PlatformC28x_Test/f2838x_headers_nonBIOS_cpu1.cmd @@ -0,0 +1,388 @@ +MEMORY +{ + PAGE 0: /* Program Memory */ + PAGE 1: /* Data Memory */ + ACCESSPROTECTION : origin = 0x0005F500, length = 0x00000040 + ADCA : origin = 0x00007400, length = 0x00000080 + ADCB : origin = 0x00007480, length = 0x00000080 + ADCC : origin = 0x00007500, length = 0x00000080 + ADCD : origin = 0x00007580, length = 0x00000080 + ADCARESULT : origin = 0x00000B00, length = 0x00000018 + ADCBRESULT : origin = 0x00000B20, length = 0x00000018 + ADCCRESULT : origin = 0x00000B40, length = 0x00000018 + ADCDRESULT : origin = 0x00000B60, length = 0x00000018 + ANALOGSUBSYS : origin = 0x0005D700, length = 0x00000100 + BGCRCCPU : origin = 0x00006340, length = 0x00000040 + BGCRCCLA1 : origin = 0x00006380, length = 0x00000040 + CANA : origin = 0x00048000, length = 0x00000200 + CANB : origin = 0x0004A000, length = 0x00000200 + CLA1 : origin = 0x00001400, length = 0x00000080 + CLB1DATAEXCH : origin = 0x00003180, length = 0x00000080 + CLB2DATAEXCH : origin = 0x00003380, length = 0x00000080 + CLB3DATAEXCH : origin = 0x00003580, length = 0x00000080 + CLB4DATAEXCH : origin = 0x00003780, length = 0x00000080 + CLB5DATAEXCH : origin = 0x00003980, length = 0x00000080 + CLB6DATAEXCH : origin = 0x00003B80, length = 0x00000080 + CLB7DATAEXCH : origin = 0x00003D80, length = 0x00000080 + CLB8DATAEXCH : origin = 0x00003F80, length = 0x00000080 + CLB1LOGICCFG : origin = 0x00003000, length = 0x00000052 + CLB2LOGICCFG : origin = 0x00003200, length = 0x00000052 + CLB3LOGICCFG : origin = 0x00003400, length = 0x00000052 + CLB4LOGICCFG : origin = 0x00003600, length = 0x00000052 + CLB5LOGICCFG : origin = 0x00003800, length = 0x00000052 + CLB6LOGICCFG : origin = 0x00003A00, length = 0x00000052 + CLB7LOGICCFG : origin = 0x00003C00, length = 0x00000052 + CLB8LOGICCFG : origin = 0x00003E00, length = 0x00000052 + CLB1LOGICCTRL : origin = 0x00003100, length = 0x00000040 + CLB2LOGICCTRL : origin = 0x00003300, length = 0x00000040 + CLB3LOGICCTRL : origin = 0x00003500, length = 0x00000040 + CLB4LOGICCTRL : origin = 0x00003700, length = 0x00000040 + CLB5LOGICCTRL : origin = 0x00003900, length = 0x00000040 + CLB6LOGICCTRL : origin = 0x00003B00, length = 0x00000040 + CLB7LOGICCTRL : origin = 0x00003D00, length = 0x00000040 + CLB8LOGICCTRL : origin = 0x00003F00, length = 0x00000040 + CLBXBAR : origin = 0x00007A40, length = 0x00000040 + CLKCFG : origin = 0x0005D200, length = 0x00000100 + CMPSS1 : origin = 0x00005C80, length = 0x00000020 + CMPSS2 : origin = 0x00005CA0, length = 0x00000020 + CMPSS3 : origin = 0x00005CC0, length = 0x00000020 + CMPSS4 : origin = 0x00005CE0, length = 0x00000020 + CMPSS5 : origin = 0x00005D00, length = 0x00000020 + CMPSS6 : origin = 0x00005D20, length = 0x00000020 + CMPSS7 : origin = 0x00005D40, length = 0x00000020 + CMPSS8 : origin = 0x00005D60, length = 0x00000020 + CMCONF : origin = 0x0005DC00, length = 0x00000400 + CPU1TOCMIPC : origin = 0x0005CE40, length = 0x00000026 + CPU1TOCPU2IPC : origin = 0x0005CE00, length = 0x00000026 + SYSPERIPHAC : origin = 0x0005D500, length = 0x00000200 + CPUTIMER0 : origin = 0x00000C00, length = 0x00000008 + CPUTIMER1 : origin = 0x00000C08, length = 0x00000008 + CPUTIMER2 : origin = 0x00000C10, length = 0x00000008 + CPUSYS : origin = 0x0005D300, length = 0x000000A0 + DACA : origin = 0x00005C00, length = 0x00000008 + DACB : origin = 0x00005C10, length = 0x00000008 + DACC : origin = 0x00005C20, length = 0x00000008 + DCC0 : origin = 0x0005E700, length = 0x00000038 + DCC1 : origin = 0x0005E740, length = 0x00000038 + DCC2 : origin = 0x0005E780, length = 0x00000038 + DCSMCOMMON : origin = 0x0005F0C0, length = 0x00000020 + DCSMZ1OTP : origin = 0x00078000, length = 0x00000020 + DCSMZ1 : origin = 0x0005F000, length = 0x0000003E + DCSMZ2OTP : origin = 0x00078200, length = 0x00000020 + DCSMZ2 : origin = 0x0005F080, length = 0x0000003E + DEVCFG : origin = 0x0005D000, length = 0x000001A0 + DMACLASRCSEL : origin = 0x00007980, length = 0x0000001A + DMA : origin = 0x00001000, length = 0x00000200 + ECAP1 : origin = 0x00005200, length = 0x00000020 + ECAP2 : origin = 0x00005240, length = 0x00000020 + ECAP3 : origin = 0x00005280, length = 0x00000020 + ECAP4 : origin = 0x000052C0, length = 0x00000020 + ECAP5 : origin = 0x00005300, length = 0x00000020 + ECAP6 : origin = 0x00005340, length = 0x00000020 + ECAP7 : origin = 0x00005380, length = 0x00000020 + EMIF1CONFIG : origin = 0x0005F4C0, length = 0x00000020 + EMIF2CONFIG : origin = 0x0005F4E0, length = 0x00000020 + EMIF1 : origin = 0x00047000, length = 0x00000070 + EMIF2 : origin = 0x00047800, length = 0x00000070 + EPWM1 : origin = 0x00004000, length = 0x00000100 + EPWM2 : origin = 0x00004100, length = 0x00000100 + EPWM3 : origin = 0x00004200, length = 0x00000100 + EPWM4 : origin = 0x00004300, length = 0x00000100 + EPWM5 : origin = 0x00004400, length = 0x00000100 + EPWM6 : origin = 0x00004500, length = 0x00000100 + EPWM7 : origin = 0x00004600, length = 0x00000100 + EPWM8 : origin = 0x00004700, length = 0x00000100 + EPWM9 : origin = 0x00004800, length = 0x00000100 + EPWM10 : origin = 0x00004900, length = 0x00000100 + EPWM11 : origin = 0x00004A00, length = 0x00000100 + EPWM12 : origin = 0x00004B00, length = 0x00000100 + EPWM13 : origin = 0x00004C00, length = 0x00000100 + EPWM14 : origin = 0x00004D00, length = 0x00000100 + EPWM15 : origin = 0x00004E00, length = 0x00000100 + EPWM16 : origin = 0x00004F00, length = 0x00000100 + EPWMXBAR : origin = 0x00007A00, length = 0x00000040 + EQEP1 : origin = 0x00005100, length = 0x00000040 + EQEP2 : origin = 0x00005140, length = 0x00000040 + EQEP3 : origin = 0x00005180, length = 0x00000040 + ERADCOUNTER1 : origin = 0x0005E980, length = 0x00000010 + ERADCOUNTER2 : origin = 0x0005E990, length = 0x00000010 + ERADCOUNTER3 : origin = 0x0005E9A0, length = 0x00000010 + ERADCOUNTER4 : origin = 0x0005E9B0, length = 0x00000010 + ERADCRCGLOBAL : origin = 0x0005EA00, length = 0x00000010 + ERADCRC1 : origin = 0x0005EA10, length = 0x00000010 + ERADCRC2 : origin = 0x0005EA20, length = 0x00000010 + ERADCRC3 : origin = 0x0005EA30, length = 0x00000010 + ERADCRC4 : origin = 0x0005EA40, length = 0x00000010 + ERADCRC5 : origin = 0x0005EA50, length = 0x00000010 + ERADCRC6 : origin = 0x0005EA60, length = 0x00000010 + ERADCRC7 : origin = 0x0005EA70, length = 0x00000010 + ERADCRC8 : origin = 0x0005EA80, length = 0x00000010 + ERADGLOBAL : origin = 0x0005E800, length = 0x00000014 + ERADHWBP1 : origin = 0x0005E900, length = 0x00000008 + ERADHWBP2 : origin = 0x0005E908, length = 0x00000008 + ERADHWBP3 : origin = 0x0005E910, length = 0x00000008 + ERADHWBP4 : origin = 0x0005E918, length = 0x00000008 + ERADHWBP5 : origin = 0x0005E920, length = 0x00000008 + ERADHWBP6 : origin = 0x0005E928, length = 0x00000008 + ERADHWBP7 : origin = 0x0005E930, length = 0x00000008 + ERADHWBP8 : origin = 0x0005E938, length = 0x00000008 + ESCSSCONFIG : origin = 0x00057F00, length = 0x00000016 + ESCSS : origin = 0x00057E00, length = 0x00000024 + FLASH0CTRL : origin = 0x0005F800, length = 0x00000182 + FLASH0ECC : origin = 0x0005FB00, length = 0x00000028 + FSIRXA : origin = 0x00006680, length = 0x00000050 + FSIRXB : origin = 0x00006780, length = 0x00000050 + FSIRXC : origin = 0x00006880, length = 0x00000050 + FSIRXD : origin = 0x00006980, length = 0x00000050 + FSIRXE : origin = 0x00006A80, length = 0x00000050 + FSIRXF : origin = 0x00006B80, length = 0x00000050 + FSIRXG : origin = 0x00006C80, length = 0x00000050 + FSIRXH : origin = 0x00006D80, length = 0x00000050 + FSITXA : origin = 0x00006600, length = 0x00000050 + FSITXB : origin = 0x00006700, length = 0x00000050 + GPIOCTRL : origin = 0x00007C00, length = 0x00000200 + GPIODATAREAD : origin = 0x00007F80, length = 0x00000010 + GPIODATA : origin = 0x00007F00, length = 0x00000040 + HRCAP6 : origin = 0x00005360, length = 0x00000020 + HRCAP7 : origin = 0x000053A0, length = 0x00000020 + I2CA : origin = 0x00007300, length = 0x00000022 + I2CB : origin = 0x00007340, length = 0x00000022 + INPUTXBAR : origin = 0x00007900, length = 0x00000020 + CLBINPUTXBAR : origin = 0x00007960, length = 0x00000020 + MCANASS : origin = 0x0005C400, length = 0x0000002C + MCANAERR : origin = 0x0005C800, length = 0x00000210 + MCANA : origin = 0x0005C600, length = 0x00000100 + MEMORYERROR : origin = 0x0005F540, length = 0x00000040 + MEMCFG : origin = 0x0005F400, length = 0x000000C0 + MCBSPA : origin = 0x00006000, length = 0x00000024 + MCBSPB : origin = 0x00006040, length = 0x00000024 + NMIINTRUPT : origin = 0x00007060, length = 0x00000010 + OUTPUTXBAR : origin = 0x00007A80, length = 0x00000040 + CLBOUTPUTXBAR : origin = 0x00007BC0, length = 0x00000040 + PIECTRL : origin = 0x00000CE0, length = 0x0000001A + PIEVECTTABLE : origin = 0x00000D00, length = 0x00000200 + PMBUSA : origin = 0x00006400, length = 0x00000020 + ROMPREFETCH : origin = 0x0005F588, length = 0x00000008 + ROMWAITSTATE : origin = 0x0005F580, length = 0x00000008 + SCIA : origin = 0x00007200, length = 0x00000010 + SCIB : origin = 0x00007210, length = 0x00000010 + SCIC : origin = 0x00007220, length = 0x00000010 + SCID : origin = 0x00007230, length = 0x00000010 + SDFM1 : origin = 0x00005E00, length = 0x00000080 + SDFM2 : origin = 0x00005E80, length = 0x00000080 + SPIA : origin = 0x00006100, length = 0x00000010 + SPIB : origin = 0x00006110, length = 0x00000010 + SPIC : origin = 0x00006120, length = 0x00000010 + SPID : origin = 0x00006130, length = 0x00000010 + SYNCSOC : origin = 0x00007940, length = 0x00000006 + SYSSTATUS : origin = 0x0005D400, length = 0x00000100 + TESTERROR : origin = 0x0005F590, length = 0x00000010 + WD : origin = 0x00007000, length = 0x0000002C + XBAR : origin = 0x00007920, length = 0x00000020 + XINT : origin = 0x00007070, length = 0x0000000C + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ +UNION run = PIEVECTTABLE +{ + PieVectTableFile + GROUP + { + EmuKeyVar + EmuBModeVar + EmuBootPinsVar + FlashCallbackVar + FlashScalingVar + } +} + + AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT + AdcaRegsFile : > ADCA, type=NOINIT + AdcbRegsFile : > ADCB, type=NOINIT + AdccRegsFile : > ADCC, type=NOINIT + AdcdRegsFile : > ADCD, type=NOINIT + AdcaResultRegsFile : > ADCARESULT, type=NOINIT + AdcbResultRegsFile : > ADCBRESULT, type=NOINIT + AdccResultRegsFile : > ADCCRESULT, type=NOINIT + AdcdResultRegsFile : > ADCDRESULT, type=NOINIT + AnalogSubsysRegsFile : > ANALOGSUBSYS, type=NOINIT + BgcrcCpuRegsFile : > BGCRCCPU, type=NOINIT + BgcrcCla1RegsFile : > BGCRCCLA1, type=NOINIT + CanaRegsFile : > CANA, type=NOINIT + CanbRegsFile : > CANB, type=NOINIT + Cla1RegsFile : > CLA1, type=NOINIT + Clb1DataExchRegsFile : > CLB1DATAEXCH, type=NOINIT + Clb2DataExchRegsFile : > CLB2DATAEXCH, type=NOINIT + Clb3DataExchRegsFile : > CLB3DATAEXCH, type=NOINIT + Clb4DataExchRegsFile : > CLB4DATAEXCH, type=NOINIT + Clb5DataExchRegsFile : > CLB5DATAEXCH, type=NOINIT + Clb6DataExchRegsFile : > CLB6DATAEXCH, type=NOINIT + Clb7DataExchRegsFile : > CLB7DATAEXCH, type=NOINIT + Clb8DataExchRegsFile : > CLB8DATAEXCH, type=NOINIT + Clb1LogicCfgRegsFile : > CLB1LOGICCFG, type=NOINIT + Clb2LogicCfgRegsFile : > CLB2LOGICCFG, type=NOINIT + Clb3LogicCfgRegsFile : > CLB3LOGICCFG, type=NOINIT + Clb4LogicCfgRegsFile : > CLB4LOGICCFG, type=NOINIT + Clb5LogicCfgRegsFile : > CLB5LOGICCFG, type=NOINIT + Clb6LogicCfgRegsFile : > CLB6LOGICCFG, type=NOINIT + Clb7LogicCfgRegsFile : > CLB7LOGICCFG, type=NOINIT + Clb8LogicCfgRegsFile : > CLB8LOGICCFG, type=NOINIT + Clb1LogicCtrlRegsFile : > CLB1LOGICCTRL, type=NOINIT + Clb2LogicCtrlRegsFile : > CLB2LOGICCTRL, type=NOINIT + Clb3LogicCtrlRegsFile : > CLB3LOGICCTRL, type=NOINIT + Clb4LogicCtrlRegsFile : > CLB4LOGICCTRL, type=NOINIT + Clb5LogicCtrlRegsFile : > CLB5LOGICCTRL, type=NOINIT + Clb6LogicCtrlRegsFile : > CLB6LOGICCTRL, type=NOINIT + Clb7LogicCtrlRegsFile : > CLB7LOGICCTRL, type=NOINIT + Clb8LogicCtrlRegsFile : > CLB8LOGICCTRL, type=NOINIT + CLBXbarRegsFile : > CLBXBAR, type=NOINIT + ClkCfgRegsFile : > CLKCFG, type=NOINIT + Cmpss1RegsFile : > CMPSS1, type=NOINIT + Cmpss2RegsFile : > CMPSS2, type=NOINIT + Cmpss3RegsFile : > CMPSS3, type=NOINIT + Cmpss4RegsFile : > CMPSS4, type=NOINIT + Cmpss5RegsFile : > CMPSS5, type=NOINIT + Cmpss6RegsFile : > CMPSS6, type=NOINIT + Cmpss7RegsFile : > CMPSS7, type=NOINIT + Cmpss8RegsFile : > CMPSS8, type=NOINIT + CmConfRegsFile : > CMCONF, type=NOINIT + Cpu1toCmIpcRegsFile : > CPU1TOCMIPC, type=NOINIT + Cpu1toCpu2IpcRegsFile : > CPU1TOCPU2IPC, type=NOINIT + SysPeriphAcRegsFile : > SYSPERIPHAC, type=NOINIT + CpuTimer0RegsFile : > CPUTIMER0, type=NOINIT + CpuTimer1RegsFile : > CPUTIMER1, type=NOINIT + CpuTimer2RegsFile : > CPUTIMER2, type=NOINIT + CpuSysRegsFile : > CPUSYS, type=NOINIT + DacaRegsFile : > DACA, type=NOINIT + DacbRegsFile : > DACB, type=NOINIT + DaccRegsFile : > DACC, type=NOINIT + Dcc0RegsFile : > DCC0, type=NOINIT + Dcc1RegsFile : > DCC1, type=NOINIT + Dcc2RegsFile : > DCC2, type=NOINIT + DcsmCommonRegsFile : > DCSMCOMMON, type=NOINIT + DcsmZ1OtpRegsFile : > DCSMZ1OTP, type=NOINIT + DcsmZ1RegsFile : > DCSMZ1, type=NOINIT + DcsmZ2OtpRegsFile : > DCSMZ2OTP, type=NOINIT + DcsmZ2RegsFile : > DCSMZ2, type=NOINIT + DevCfgRegsFile : > DEVCFG, type=NOINIT + DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT + DmaRegsFile : > DMA, type=NOINIT + ECap1RegsFile : > ECAP1, type=NOINIT + ECap2RegsFile : > ECAP2, type=NOINIT + ECap3RegsFile : > ECAP3, type=NOINIT + ECap4RegsFile : > ECAP4, type=NOINIT + ECap5RegsFile : > ECAP5, type=NOINIT + ECap6RegsFile : > ECAP6, type=NOINIT + ECap7RegsFile : > ECAP7, type=NOINIT + Emif1ConfigRegsFile : > EMIF1CONFIG, type=NOINIT + Emif2ConfigRegsFile : > EMIF2CONFIG, type=NOINIT + Emif1RegsFile : > EMIF1, type=NOINIT + Emif2RegsFile : > EMIF2, type=NOINIT + EPwm1RegsFile : > EPWM1, type=NOINIT + EPwm2RegsFile : > EPWM2, type=NOINIT + EPwm3RegsFile : > EPWM3, type=NOINIT + EPwm4RegsFile : > EPWM4, type=NOINIT + EPwm5RegsFile : > EPWM5, type=NOINIT + EPwm6RegsFile : > EPWM6, type=NOINIT + EPwm7RegsFile : > EPWM7, type=NOINIT + EPwm8RegsFile : > EPWM8, type=NOINIT + EPwm9RegsFile : > EPWM9, type=NOINIT + EPwm10RegsFile : > EPWM10, type=NOINIT + EPwm11RegsFile : > EPWM11, type=NOINIT + EPwm12RegsFile : > EPWM12, type=NOINIT + EPwm13RegsFile : > EPWM13, type=NOINIT + EPwm14RegsFile : > EPWM14, type=NOINIT + EPwm15RegsFile : > EPWM15, type=NOINIT + EPwm16RegsFile : > EPWM16, type=NOINIT + EPwmXbarRegsFile : > EPWMXBAR, type=NOINIT + EQep1RegsFile : > EQEP1, type=NOINIT + EQep2RegsFile : > EQEP2, type=NOINIT + EQep3RegsFile : > EQEP3, type=NOINIT + EradCounter1RegsFile : > ERADCOUNTER1, type=NOINIT + EradCounter2RegsFile : > ERADCOUNTER2, type=NOINIT + EradCounter3RegsFile : > ERADCOUNTER3, type=NOINIT + EradCounter4RegsFile : > ERADCOUNTER4, type=NOINIT + EradCRCGlobalRegsFile : > ERADCRCGLOBAL, type=NOINIT + EradCRC1RegsFile : > ERADCRC1, type=NOINIT + EradCRC2RegsFile : > ERADCRC2, type=NOINIT + EradCRC3RegsFile : > ERADCRC3, type=NOINIT + EradCRC4RegsFile : > ERADCRC4, type=NOINIT + EradCRC5RegsFile : > ERADCRC5, type=NOINIT + EradCRC6RegsFile : > ERADCRC6, type=NOINIT + EradCRC7RegsFile : > ERADCRC7, type=NOINIT + EradCRC8RegsFile : > ERADCRC8, type=NOINIT + EradGlobalRegsFile : > ERADGLOBAL, type=NOINIT + EradHWBP1RegsFile : > ERADHWBP1, type=NOINIT + EradHWBP2RegsFile : > ERADHWBP2, type=NOINIT + EradHWBP3RegsFile : > ERADHWBP3, type=NOINIT + EradHWBP4RegsFile : > ERADHWBP4, type=NOINIT + EradHWBP5RegsFile : > ERADHWBP5, type=NOINIT + EradHWBP6RegsFile : > ERADHWBP6, type=NOINIT + EradHWBP7RegsFile : > ERADHWBP7, type=NOINIT + EradHWBP8RegsFile : > ERADHWBP8, type=NOINIT + EscssConfigRegsFile : > ESCSSCONFIG, type=NOINIT + EscssRegsFile : > ESCSS, type=NOINIT + Flash0CtrlRegsFile : > FLASH0CTRL, type=NOINIT + Flash0EccRegsFile : > FLASH0ECC, type=NOINIT + FsiRxaRegsFile : > FSIRXA, type=NOINIT + FsiRxbRegsFile : > FSIRXB, type=NOINIT + FsiRxcRegsFile : > FSIRXC, type=NOINIT + FsiRxdRegsFile : > FSIRXD, type=NOINIT + FsiRxeRegsFile : > FSIRXE, type=NOINIT + FsiRxfRegsFile : > FSIRXF, type=NOINIT + FsiRxgRegsFile : > FSIRXG, type=NOINIT + FsiRxhRegsFile : > FSIRXH, type=NOINIT + FsiTxaRegsFile : > FSITXA, type=NOINIT + FsiTxbRegsFile : > FSITXB, type=NOINIT + GpioCtrlRegsFile : > GPIOCTRL, type=NOINIT + GpioDataReadRegsFile : > GPIODATAREAD, type=NOINIT + GpioDataRegsFile : > GPIODATA, type=NOINIT + HRCap6RegsFile : > HRCAP6, type=NOINIT + HRCap7RegsFile : > HRCAP7, type=NOINIT + I2caRegsFile : > I2CA, type=NOINIT + I2cbRegsFile : > I2CB, type=NOINIT + InputXbarRegsFile : > INPUTXBAR, type=NOINIT + ClbInputXbarRegsFile : > CLBINPUTXBAR, type=NOINIT + McanaSsRegsFile : > MCANASS, type=NOINIT + McanaErrRegsFile : > MCANAERR, type=NOINIT + McanaRegsFile : > MCANA, type=NOINIT + MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT + MemCfgRegsFile : > MEMCFG, type=NOINIT + McbspaRegsFile : > MCBSPA, type=NOINIT + McbspbRegsFile : > MCBSPB, type=NOINIT + NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT + OutputXbarRegsFile : > OUTPUTXBAR, type=NOINIT + ClbOutputXbarRegsFile : > CLBOUTPUTXBAR, type=NOINIT + PieCtrlRegsFile : > PIECTRL, type=NOINIT + PieVectTableFile : > PIEVECTTABLE, type=NOINIT + PmbusaRegsFile : > PMBUSA, type=NOINIT + RomPrefetchRegsFile : > ROMPREFETCH, type=NOINIT + RomWaitStateRegsFile : > ROMWAITSTATE, type=NOINIT + SciaRegsFile : > SCIA, type=NOINIT + ScibRegsFile : > SCIB, type=NOINIT + ScicRegsFile : > SCIC, type=NOINIT + ScidRegsFile : > SCID, type=NOINIT + Sdfm1RegsFile : > SDFM1, type=NOINIT + Sdfm2RegsFile : > SDFM2, type=NOINIT + SpiaRegsFile : > SPIA, type=NOINIT + SpibRegsFile : > SPIB, type=NOINIT + SpicRegsFile : > SPIC, type=NOINIT + SpidRegsFile : > SPID, type=NOINIT + SyncSocRegsFile : > SYNCSOC, type=NOINIT + SysStatusRegsFile : > SYSSTATUS, type=NOINIT + TestErrorRegsFile : > TESTERROR, type=NOINIT + WdRegsFile : > WD, type=NOINIT + XbarRegsFile : > XBAR, type=NOINIT + XintRegsFile : > XINT, type=NOINIT +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/EFC_PlatformC28x_Test/main.cpp b/EFC_PlatformC28x_Test/main.cpp new file mode 100644 index 0000000..193afc8 --- /dev/null +++ b/EFC_PlatformC28x_Test/main.cpp @@ -0,0 +1,101 @@ +/** + * \file main.cpp + * \project EFC_PlatformC28x + * \Author leonidTitov + * \date 10 мая 2024 г. + * + */ +#define _DUAL_HEADERS // + +#include "UnitTestInterface.hh" +#include "AsyncRunnerInterface.hh" + +#include "AsyncRunner.hh" + +struct BaseResult : public umlib::tests::TestResult { + + void assert_false( bool, std::string description ); + void assert_true( bool, std::string description ); + +}; + +#include +#include + +void init() { + + Interrupt_disableGlobal(); + Interrupt_disablePIE(); + + Interrupt_initModule(); + Interrupt_initVectorTable(); + + Interrupt_enablePIE(); + Interrupt_enableGlobal(); + + EINT; + ERTM; + +} + +#include + +#include +#include + +#include // SDFM +#include // + + + +/** + * \function run() + */ +int run() +{ + + BaseResult result; + + umlib::tests::AsyncRunnerTest async_runner_test( platform::AsyncRunner::getInstance() ); + + async_runner_test.run(result); + + umlib::tests::AtomicFlagTest atomic_flag_tests( platform::AsyncRunner::getInstance() ); + + atomic_flag_tests.run(result); + + // Sdfm_tests + umlib::tests::SdfmTest Sdfm_tests; + Sdfm_tests.run(result); + return 0; + +} + +#include + +/*! + * \brief Вся инициализация должна быть произведена в скрипте отладчика. + * \function main() + * + */ +int main(int argc, char * argv[]) { + + printf("\n"); + printf("Run PlatformC28x Tests:\n"); + + init(); + + return run(); +} + +void BaseResult::assert_false( bool check, std::string description ) { + + printf("\"%s\": %s\n", description.c_str(), check ? "False" : "True"); + +} + +void BaseResult::assert_true( bool check, std::string description ) { + + printf("\"%s\": %s\n", description.c_str(), check ? "True" : "False"); + +} diff --git a/EFC_PlatformC28x_Test/targetConfigs/TMS320F28388D.ccxml b/EFC_PlatformC28x_Test/targetConfigs/TMS320F28388D.ccxml new file mode 100644 index 0000000..09ae94d --- /dev/null +++ b/EFC_PlatformC28x_Test/targetConfigs/TMS320F28388D.ccxml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EFC_PlatformC28x_Test/targetConfigs/readme.txt b/EFC_PlatformC28x_Test/targetConfigs/readme.txt new file mode 100644 index 0000000..d783fef --- /dev/null +++ b/EFC_PlatformC28x_Test/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/RemoteSystemsTempFiles/.project b/RemoteSystemsTempFiles/.project new file mode 100644 index 0000000..5447a64 --- /dev/null +++ b/RemoteSystemsTempFiles/.project @@ -0,0 +1,12 @@ + + + RemoteSystemsTempFiles + + + + + + + org.eclipse.rse.ui.remoteSystemsTempNature + +