From 4ec847ce58ca3af5f881ed4309ad9eb59f23f156 Mon Sep 17 00:00:00 2001 From: sedov Date: Fri, 9 Aug 2024 15:08:23 +0300 Subject: [PATCH] =?UTF-8?q?dev(UML-2538):=20=D0=9F=D1=80=D0=BE=D0=B5=D0=BA?= =?UTF-8?q?=D1=82=20=D0=B4=D0=BB=D1=8F=20=D1=82=D0=B5=D1=81=D1=82=D0=B8?= =?UTF-8?q?=D1=80=D0=BE=D0=B2=D0=B0=D0=BD=D0=B8=D1=8F=20=D0=B4=D0=B8=D1=81?= =?UTF-8?q?=D0=BF=D0=BB=D0=B5=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- RemoteSystemsTempFiles/.project | 12 + i2c_ex1_master/.ccsproject | 18 + i2c_ex1_master/.cproject | 209 + .../.launches/i2c_ex1_master.launch | 19 + i2c_ex1_master/.project | 37 + .../org.eclipse.cdt.codan.core.prefs | 3 + .../org.eclipse.cdt.debug.core.prefs | 2 + .../org.eclipse.core.resources.prefs | 6 + i2c_ex1_master/2838x_FLASH_lnk_cpu1.cmd | 137 + i2c_ex1_master/2838x_RAM_lnk_cpu1.cmd | 111 + i2c_ex1_master/CPU1_RAM/ccsObjs.opt | 17 + .../CPU1_RAM/f2838x_codestartbranch.obj | Bin 0 -> 3724 bytes i2c_ex1_master/CPU1_RAM/f2838x_cputimers.d | 231 + i2c_ex1_master/CPU1_RAM/f2838x_cputimers.obj | Bin 0 -> 10504 bytes i2c_ex1_master/CPU1_RAM/f2838x_defaultisr.d | 231 + i2c_ex1_master/CPU1_RAM/f2838x_defaultisr.obj | Bin 0 -> 289200 bytes i2c_ex1_master/CPU1_RAM/f2838x_dma.d | 231 + i2c_ex1_master/CPU1_RAM/f2838x_dma.obj | Bin 0 -> 99944 bytes i2c_ex1_master/CPU1_RAM/f2838x_epwm.d | 231 + i2c_ex1_master/CPU1_RAM/f2838x_epwm.obj | Bin 0 -> 101144 bytes .../CPU1_RAM/f2838x_globalvariabledefs.d | 180 + .../CPU1_RAM/f2838x_globalvariabledefs.obj | Bin 0 -> 786000 bytes i2c_ex1_master/CPU1_RAM/f2838x_gpio.d | 231 + i2c_ex1_master/CPU1_RAM/f2838x_gpio.obj | Bin 0 -> 144728 bytes i2c_ex1_master/CPU1_RAM/f2838x_piectrl.d | 231 + i2c_ex1_master/CPU1_RAM/f2838x_piectrl.obj | Bin 0 -> 21732 bytes i2c_ex1_master/CPU1_RAM/f2838x_pievect.d | 231 + i2c_ex1_master/CPU1_RAM/f2838x_pievect.obj | Bin 0 -> 42552 bytes i2c_ex1_master/CPU1_RAM/f2838x_sysctrl.d | 240 + i2c_ex1_master/CPU1_RAM/f2838x_sysctrl.obj | Bin 0 -> 144464 bytes i2c_ex1_master/CPU1_RAM/f2838x_usdelay.obj | Bin 0 -> 2480 bytes i2c_ex1_master/CPU1_RAM/fonts.d | 24 + i2c_ex1_master/CPU1_RAM/fonts.obj | Bin 0 -> 9888 bytes i2c_ex1_master/CPU1_RAM/i2c_ex1_master.d | 249 + i2c_ex1_master/CPU1_RAM/i2c_ex1_master.map | 1326 + i2c_ex1_master/CPU1_RAM/i2c_ex1_master.obj | Bin 0 -> 9716 bytes i2c_ex1_master/CPU1_RAM/i2c_ex1_master.out | Bin 0 -> 720060 bytes .../CPU1_RAM/i2c_ex1_master_linkInfo.xml | 22201 ++++++++++++++++ i2c_ex1_master/CPU1_RAM/i2c_oled.d | 249 + i2c_ex1_master/CPU1_RAM/i2c_oled.obj | Bin 0 -> 63280 bytes i2c_ex1_master/CPU1_RAM/makefile | 168 + i2c_ex1_master/CPU1_RAM/objects.mk | 8 + i2c_ex1_master/CPU1_RAM/sources.mk | 115 + i2c_ex1_master/CPU1_RAM/subdir_rules.mk | 22 + i2c_ex1_master/CPU1_RAM/subdir_vars.mk | 116 + i2c_ex1_master/f2838x_codestartbranch.asm | 112 + i2c_ex1_master/f2838x_cputimers.c | 181 + i2c_ex1_master/f2838x_defaultisr.c | 4635 ++++ i2c_ex1_master/f2838x_dma.c | 1100 + i2c_ex1_master/f2838x_epwm.c | 642 + i2c_ex1_master/f2838x_globalvariabledefs.c | 1561 ++ i2c_ex1_master/f2838x_gpio.c | 472 + .../f2838x_headers_nonBIOS_cpu1.cmd | 388 + i2c_ex1_master/f2838x_piectrl.c | 121 + i2c_ex1_master/f2838x_pievect.c | 309 + i2c_ex1_master/f2838x_sysctrl.c | 1463 + i2c_ex1_master/f2838x_usdelay.asm | 108 + i2c_ex1_master/fonts.c | 345 + i2c_ex1_master/fonts.h | 132 + i2c_ex1_master/i2c_ex1_master.c | 185 + i2c_ex1_master/i2c_oled.c | 669 + i2c_ex1_master/i2c_oled.h | 53 + .../targetConfigs/TMS320F28388D.ccxml | 55 + 63 files changed, 39617 insertions(+) create mode 100644 RemoteSystemsTempFiles/.project create mode 100644 i2c_ex1_master/.ccsproject create mode 100644 i2c_ex1_master/.cproject create mode 100644 i2c_ex1_master/.launches/i2c_ex1_master.launch create mode 100644 i2c_ex1_master/.project create mode 100644 i2c_ex1_master/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 i2c_ex1_master/.settings/org.eclipse.cdt.debug.core.prefs create mode 100644 i2c_ex1_master/.settings/org.eclipse.core.resources.prefs create mode 100644 i2c_ex1_master/2838x_FLASH_lnk_cpu1.cmd create mode 100644 i2c_ex1_master/2838x_RAM_lnk_cpu1.cmd create mode 100644 i2c_ex1_master/CPU1_RAM/ccsObjs.opt create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_codestartbranch.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_cputimers.d create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_cputimers.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_defaultisr.d create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_defaultisr.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_dma.d create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_dma.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_epwm.d create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_epwm.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_globalvariabledefs.d create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_globalvariabledefs.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_gpio.d create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_gpio.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_piectrl.d create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_piectrl.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_pievect.d create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_pievect.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_sysctrl.d create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_sysctrl.obj create mode 100644 i2c_ex1_master/CPU1_RAM/f2838x_usdelay.obj create mode 100644 i2c_ex1_master/CPU1_RAM/fonts.d create mode 100644 i2c_ex1_master/CPU1_RAM/fonts.obj create mode 100644 i2c_ex1_master/CPU1_RAM/i2c_ex1_master.d create mode 100644 i2c_ex1_master/CPU1_RAM/i2c_ex1_master.map create mode 100644 i2c_ex1_master/CPU1_RAM/i2c_ex1_master.obj create mode 100644 i2c_ex1_master/CPU1_RAM/i2c_ex1_master.out create mode 100644 i2c_ex1_master/CPU1_RAM/i2c_ex1_master_linkInfo.xml create mode 100644 i2c_ex1_master/CPU1_RAM/i2c_oled.d create mode 100644 i2c_ex1_master/CPU1_RAM/i2c_oled.obj create mode 100644 i2c_ex1_master/CPU1_RAM/makefile create mode 100644 i2c_ex1_master/CPU1_RAM/objects.mk create mode 100644 i2c_ex1_master/CPU1_RAM/sources.mk create mode 100644 i2c_ex1_master/CPU1_RAM/subdir_rules.mk create mode 100644 i2c_ex1_master/CPU1_RAM/subdir_vars.mk create mode 100644 i2c_ex1_master/f2838x_codestartbranch.asm create mode 100644 i2c_ex1_master/f2838x_cputimers.c create mode 100644 i2c_ex1_master/f2838x_defaultisr.c create mode 100644 i2c_ex1_master/f2838x_dma.c create mode 100644 i2c_ex1_master/f2838x_epwm.c create mode 100644 i2c_ex1_master/f2838x_globalvariabledefs.c create mode 100644 i2c_ex1_master/f2838x_gpio.c create mode 100644 i2c_ex1_master/f2838x_headers_nonBIOS_cpu1.cmd create mode 100644 i2c_ex1_master/f2838x_piectrl.c create mode 100644 i2c_ex1_master/f2838x_pievect.c create mode 100644 i2c_ex1_master/f2838x_sysctrl.c create mode 100644 i2c_ex1_master/f2838x_usdelay.asm create mode 100644 i2c_ex1_master/fonts.c create mode 100644 i2c_ex1_master/fonts.h create mode 100644 i2c_ex1_master/i2c_ex1_master.c create mode 100644 i2c_ex1_master/i2c_oled.c create mode 100644 i2c_ex1_master/i2c_oled.h create mode 100644 i2c_ex1_master/targetConfigs/TMS320F28388D.ccxml diff --git a/RemoteSystemsTempFiles/.project b/RemoteSystemsTempFiles/.project new file mode 100644 index 0000000..5447a64 --- /dev/null +++ b/RemoteSystemsTempFiles/.project @@ -0,0 +1,12 @@ + + + RemoteSystemsTempFiles + + + + + + + org.eclipse.rse.ui.remoteSystemsTempNature + + diff --git a/i2c_ex1_master/.ccsproject b/i2c_ex1_master/.ccsproject new file mode 100644 index 0000000..b8778e7 --- /dev/null +++ b/i2c_ex1_master/.ccsproject @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/i2c_ex1_master/.cproject b/i2c_ex1_master/.cproject new file mode 100644 index 0000000..c9fb160 --- /dev/null +++ b/i2c_ex1_master/.cproject @@ -0,0 +1,209 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/i2c_ex1_master/.launches/i2c_ex1_master.launch b/i2c_ex1_master/.launches/i2c_ex1_master.launch new file mode 100644 index 0000000..6205ce1 --- /dev/null +++ b/i2c_ex1_master/.launches/i2c_ex1_master.launch @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/i2c_ex1_master/.project b/i2c_ex1_master/.project new file mode 100644 index 0000000..f55009c --- /dev/null +++ b/i2c_ex1_master/.project @@ -0,0 +1,37 @@ + + + i2c_ex1_master + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + C2000WARE_COMMON_INCLUDE + $%7BCOM_TI_C2000WARE_SOFTWARE_PACKAGE_INSTALL_DIR%7D/device_support/f2838x/common/include + + + C2000WARE_HEADERS_INCLUDE + $%7BCOM_TI_C2000WARE_SOFTWARE_PACKAGE_INSTALL_DIR%7D/device_support/f2838x/headers/include + + + diff --git a/i2c_ex1_master/.settings/org.eclipse.cdt.codan.core.prefs b/i2c_ex1_master/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/i2c_ex1_master/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/i2c_ex1_master/.settings/org.eclipse.cdt.debug.core.prefs b/i2c_ex1_master/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000..2adc7b1 --- /dev/null +++ b/i2c_ex1_master/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/i2c_ex1_master/.settings/org.eclipse.core.resources.prefs b/i2c_ex1_master/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..56aa170 --- /dev/null +++ b/i2c_ex1_master/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,6 @@ +eclipse.preferences.version=1 +encoding//CPU1_RAM/makefile=UTF-8 +encoding//CPU1_RAM/objects.mk=UTF-8 +encoding//CPU1_RAM/sources.mk=UTF-8 +encoding//CPU1_RAM/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM/subdir_vars.mk=UTF-8 diff --git a/i2c_ex1_master/2838x_FLASH_lnk_cpu1.cmd b/i2c_ex1_master/2838x_FLASH_lnk_cpu1.cmd new file mode 100644 index 0000000..43f0b33 --- /dev/null +++ b/i2c_ex1_master/2838x_FLASH_lnk_cpu1.cmd @@ -0,0 +1,137 @@ + +MEMORY +{ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + BEGIN : origin = 0x080000, length = 0x000002 + BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x0001B1, length = 0x00024F + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD0 : origin = 0x00C000, length = 0x000800 + RAMD1 : origin = 0x00C800, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMLS5 : origin = 0x00A800, length = 0x000800 + RAMLS6 : origin = 0x00B000, length = 0x000800 + RAMLS7 : origin = 0x00B800, length = 0x000800 + RAMGS0 : origin = 0x00D000, length = 0x001000 + RAMGS1 : origin = 0x00E000, length = 0x001000 + RAMGS2 : origin = 0x00F000, length = 0x001000 + RAMGS3 : origin = 0x010000, length = 0x001000 + RAMGS4 : origin = 0x011000, length = 0x001000 + RAMGS5 : origin = 0x012000, length = 0x001000 + RAMGS6 : origin = 0x013000, length = 0x001000 + RAMGS7 : origin = 0x014000, length = 0x001000 + RAMGS8 : origin = 0x015000, length = 0x001000 + RAMGS9 : origin = 0x016000, length = 0x001000 + RAMGS10 : origin = 0x017000, length = 0x001000 + RAMGS11 : origin = 0x018000, length = 0x001000 + RAMGS12 : origin = 0x019000, length = 0x001000 + RAMGS13 : origin = 0x01A000, length = 0x001000 + RAMGS14 : origin = 0x01B000, length = 0x001000 + RAMGS15 : origin = 0x01C000, length = 0x000FF8 +// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + /* Flash sectors */ + FLASH0 : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASH13 : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ +// FLASH13_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800 + CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800 + CPUTOCMRAM : origin = 0x039000, length = 0x000800 + CMTOCPURAM : origin = 0x038000, length = 0x000800 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + RESET : origin = 0x3FFFC0, length = 0x000002 +} + +SECTIONS +{ + codestart : > BEGIN, ALIGN(8) + .text : >> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(8) + .cinit : > FLASH4, ALIGN(8) + .switch : > FLASH1, ALIGN(8) + .reset : > RESET, TYPE = DSECT /* not used, */ + .stack : > RAMM1 + +#if defined(__TI_EABI__) + .init_array : > FLASH1, ALIGN(8) + .bss : > RAMLS5 + .bss:output : > RAMLS3 + .bss:cio : > RAMLS5 + .data : > RAMLS5 + .sysmem : > RAMLS5 + /* Initalized sections go in Flash */ + .const : > FLASH5, ALIGN(8) +#else + .pinit : > FLASH1, ALIGN(8) + .ebss : > RAMLS5 + .esysmem : > RAMLS5 + .cio : > RAMLS5 + /* Initalized sections go in Flash */ + .econst : >> FLASH4 | FLASH5, ALIGN(8) +#endif + + ramgs0 : > RAMGS0, type=NOINIT + ramgs1 : > RAMGS1, type=NOINIT + + MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT + MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT + MSGRAM_CPU_TO_CM : > CPUTOCMRAM, type=NOINIT + MSGRAM_CM_TO_CPU : > CMTOCPURAM, type=NOINIT + + /* The following section definition are for SDFM examples */ + Filter_RegsFile : > RAMGS0 + Filter1_RegsFile : > RAMGS1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, fill=0x2222 + Filter3_RegsFile : > RAMGS3, fill=0x3333 + Filter4_RegsFile : > RAMGS4, fill=0x4444 + Difference_RegsFile : >RAMGS5, fill=0x3333 + + #if defined(__TI_EABI__) + .TI.ramfunc : {} LOAD = FLASH3, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(RamfuncsLoadStart), + LOAD_SIZE(RamfuncsLoadSize), + LOAD_END(RamfuncsLoadEnd), + RUN_START(RamfuncsRunStart), + RUN_SIZE(RamfuncsRunSize), + RUN_END(RamfuncsRunEnd), + ALIGN(8) + #else + .TI.ramfunc : {} LOAD = FLASH3, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + ALIGN(8) + #endif + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/i2c_ex1_master/2838x_RAM_lnk_cpu1.cmd b/i2c_ex1_master/2838x_RAM_lnk_cpu1.cmd new file mode 100644 index 0000000..3182312 --- /dev/null +++ b/i2c_ex1_master/2838x_RAM_lnk_cpu1.cmd @@ -0,0 +1,111 @@ +MEMORY +{ + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + BEGIN : origin = 0x000000, length = 0x000002 + BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x0001B1, length = 0x00024F + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD0 : origin = 0x00C000, length = 0x000800 + RAMD1 : origin = 0x00C800, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMLS5 : origin = 0x00A800, length = 0x000800 + RAMLS6 : origin = 0x00B000, length = 0x000800 + RAMLS7 : origin = 0x00B800, length = 0x000800 + RAMGS0 : origin = 0x00D000, length = 0x001000 + RAMGS1 : origin = 0x00E000, length = 0x001000 + RAMGS2 : origin = 0x00F000, length = 0x001000 + RAMGS3 : origin = 0x010000, length = 0x001000 + RAMGS4 : origin = 0x011000, length = 0x001000 + RAMGS5 : origin = 0x012000, length = 0x001000 + RAMGS6 : origin = 0x013000, length = 0x001000 + RAMGS7 : origin = 0x014000, length = 0x001000 + RAMGS8 : origin = 0x015000, length = 0x001000 + RAMGS9 : origin = 0x016000, length = 0x001000 + RAMGS10 : origin = 0x017000, length = 0x001000 + RAMGS11 : origin = 0x018000, length = 0x001000 + RAMGS12 : origin = 0x019000, length = 0x001000 + RAMGS13 : origin = 0x01A000, length = 0x001000 + RAMGS14 : origin = 0x01B000, length = 0x001000 + RAMGS15 : origin = 0x01C000, length = 0x000FF8 +// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + /* Flash sectors */ + FLASH0 : origin = 0x080000, length = 0x002000 /* on-chip Flash */ + FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800 + CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800 + + CPUTOCMRAM : origin = 0x039000, length = 0x000800 + CMTOCPURAM : origin = 0x038000, length = 0x000800 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 +} + + +SECTIONS +{ + codestart : > BEGIN + .text : >> RAMD0 | RAMD1 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 + .cinit : > RAMM0 + .switch : > RAMM0 + .reset : > RESET, TYPE = DSECT /* not used, */ + + .stack : > RAMM1 +#if defined(__TI_EABI__) + .bss : > RAMLS5 + .bss:output : > RAMLS3 + .init_array : > RAMM0 + .const : > RAMLS5 | RAMLS6 + .data : > RAMLS5 + .sysmem : > RAMLS4 +#else + .pinit : > RAMM0 + .ebss : >> RAMLS5 | RAMLS6 + .econst : > RAMLS5 + .esysmem : > RAMLS5 +#endif + + ramgs0 : > RAMGS0, type=NOINIT + ramgs1 : > RAMGS1, type=NOINIT + + MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT + MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT + MSGRAM_CPU_TO_CM > CPUTOCMRAM, type=NOINIT + MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT + + /* The following section definition are for SDFM examples */ + Filter_RegsFile : > RAMGS0 + Filter1_RegsFile : > RAMGS1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, fill=0x2222 + Filter3_RegsFile : > RAMGS3, fill=0x3333 + Filter4_RegsFile : > RAMGS4, fill=0x4444 + Difference_RegsFile : >RAMGS5, fill=0x3333 + + .TI.ramfunc : {} > RAMM0 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/i2c_ex1_master/CPU1_RAM/ccsObjs.opt b/i2c_ex1_master/CPU1_RAM/ccsObjs.opt new file mode 100644 index 0000000..47d6856 --- /dev/null +++ b/i2c_ex1_master/CPU1_RAM/ccsObjs.opt @@ -0,0 +1,17 @@ +"./f2838x_codestartbranch.obj" +"./f2838x_cputimers.obj" +"./f2838x_defaultisr.obj" +"./f2838x_dma.obj" +"./f2838x_epwm.obj" +"./f2838x_globalvariabledefs.obj" +"./f2838x_gpio.obj" +"./f2838x_piectrl.obj" +"./f2838x_pievect.obj" +"./f2838x_sysctrl.obj" +"./f2838x_usdelay.obj" +"./fonts.obj" +"./i2c_ex1_master.obj" +"./i2c_oled.obj" +"../2838x_RAM_lnk_cpu1.cmd" +"../f2838x_headers_nonBIOS_cpu1.cmd" +-llibc.a diff --git a/i2c_ex1_master/CPU1_RAM/f2838x_codestartbranch.obj b/i2c_ex1_master/CPU1_RAM/f2838x_codestartbranch.obj new file mode 100644 index 0000000000000000000000000000000000000000..4c5531e9bc5171850d435350206e28f96bf5c874 GIT binary patch literal 3724 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C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_device.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/assert.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_ti_config.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/linkage.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdarg.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_types.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/cdefs.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_types.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdbool.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stddef.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdint.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_stdint40.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/stdint.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_stdint.h +f2838x_dma.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_stdint.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_adc.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_analogsubsys.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_bgcrc.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cla.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clb.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clbxbar.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cmpss.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cputimer.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dac.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcsm.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dma.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecap.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecat_ss.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_emif.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwm.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwmxbar.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_eqep.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_erad.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_flash.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_fsi.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_gpio.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_hwbist.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_i2c.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_inputxbar.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ipc.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcbsp.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_memconfig.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_nmiintrupt.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_outputxbar.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pbist.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_piectrl.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pievect.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pmbus.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sci.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sdfm.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_spi.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sysctrl.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_wwd.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_xbar.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_xint.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_can.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcc.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcan.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_examples.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_globalprototypes.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_cputimervars.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_cla_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_can_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_dac_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_memctrl_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_epwm_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_adc_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_emif_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_gpio_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_ipc_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_pie_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_dma_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_sdfm_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_sysctrl_defines.h +f2838x_dma.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_defaultisr.h + +../f2838x_dma.c: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_device.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/assert.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_ti_config.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/linkage.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdarg.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_types.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/cdefs.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_types.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdbool.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stddef.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdint.h: + 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+f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_ti_config.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/linkage.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdarg.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_types.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/cdefs.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_types.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdbool.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stddef.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdint.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_stdint40.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/stdint.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_stdint.h +f2838x_globalvariabledefs.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_stdint.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_adc.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_analogsubsys.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_bgcrc.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cla.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clb.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clbxbar.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cmpss.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cputimer.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dac.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcsm.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dma.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecap.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecat_ss.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_emif.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwm.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwmxbar.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_eqep.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_erad.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_flash.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_fsi.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_gpio.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_hwbist.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_i2c.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_inputxbar.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ipc.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcbsp.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_memconfig.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_nmiintrupt.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_outputxbar.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pbist.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_piectrl.h +f2838x_globalvariabledefs.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pievect.h +f2838x_globalvariabledefs.obj: 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b/i2c_ex1_master/CPU1_RAM/f2838x_gpio.d @@ -0,0 +1,231 @@ +# FIXED + +f2838x_gpio.obj: ../f2838x_gpio.c +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_device.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/assert.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_ti_config.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/linkage.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdarg.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_types.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/cdefs.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_types.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdbool.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stddef.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdint.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_stdint40.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/stdint.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_stdint.h +f2838x_gpio.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_stdint.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_adc.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_analogsubsys.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_bgcrc.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cla.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clb.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clbxbar.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cmpss.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cputimer.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dac.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcsm.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dma.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecap.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecat_ss.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_emif.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwm.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwmxbar.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_eqep.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_erad.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_flash.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_fsi.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_gpio.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_hwbist.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_i2c.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_inputxbar.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ipc.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcbsp.h +f2838x_gpio.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_memconfig.h +f2838x_gpio.obj: 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C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_device.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/assert.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_ti_config.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/linkage.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdarg.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_types.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/cdefs.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_types.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdbool.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stddef.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdint.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_stdint40.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/stdint.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_stdint.h +f2838x_piectrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_stdint.h +f2838x_piectrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_adc.h +f2838x_piectrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_analogsubsys.h +f2838x_piectrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_bgcrc.h +f2838x_piectrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cla.h +f2838x_piectrl.obj: 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C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdarg.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_types.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/cdefs.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_types.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdbool.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stddef.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdint.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_stdint40.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/stdint.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_stdint.h +f2838x_pievect.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_stdint.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_adc.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_analogsubsys.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_bgcrc.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cla.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clb.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clbxbar.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cmpss.h +f2838x_pievect.obj: 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C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwmxbar.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_eqep.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_erad.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_flash.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_fsi.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_gpio.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_hwbist.h +f2838x_pievect.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_i2c.h +f2838x_pievect.obj: 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C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_device.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/assert.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_ti_config.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/linkage.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdarg.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_types.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/cdefs.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_types.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdbool.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stddef.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdint.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_stdint40.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/stdint.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_stdint.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_stdint.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_adc.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_analogsubsys.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_bgcrc.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cla.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clb.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clbxbar.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cmpss.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cputimer.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dac.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcsm.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dma.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecap.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecat_ss.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_emif.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwm.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwmxbar.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_eqep.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_erad.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_flash.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_fsi.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_gpio.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_hwbist.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_i2c.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_inputxbar.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ipc.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcbsp.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_memconfig.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_nmiintrupt.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_outputxbar.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pbist.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_piectrl.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pievect.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pmbus.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sci.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sdfm.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_spi.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sysctrl.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_wwd.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_xbar.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_xint.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_can.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcc.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcan.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_examples.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_globalprototypes.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_cputimervars.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_cla_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_can_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_dac_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_memctrl_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_epwm_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_adc_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_emif_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_gpio_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_ipc_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_pie_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_dma_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_sdfm_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_sysctrl_defines.h +f2838x_sysctrl.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_defaultisr.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/math.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_defs.h +f2838x_sysctrl.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_limits.h + +../f2838x_sysctrl.c: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_device.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/assert.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_ti_config.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/linkage.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdarg.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_types.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/cdefs.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_types.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdbool.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stddef.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdint.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_stdint40.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/stdint.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_stdint.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_stdint.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_adc.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_analogsubsys.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_bgcrc.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cla.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clb.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clbxbar.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cmpss.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cputimer.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dac.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcsm.h: + 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+C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_fsi.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_gpio.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_hwbist.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_i2c.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_inputxbar.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ipc.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcbsp.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_memconfig.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_nmiintrupt.h: + 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+C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clbxbar.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cmpss.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cputimer.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dac.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcsm.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dma.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecap.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecat_ss.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_emif.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwm.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwmxbar.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_eqep.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_erad.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_flash.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_fsi.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_gpio.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_hwbist.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_i2c.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_inputxbar.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ipc.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcbsp.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_memconfig.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_nmiintrupt.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_outputxbar.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pbist.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_piectrl.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pievect.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pmbus.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sci.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sdfm.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_spi.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sysctrl.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_wwd.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_xbar.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_xint.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_can.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcc.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcan.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_examples.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_globalprototypes.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_cputimervars.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_cla_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_can_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_dac_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_memctrl_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_epwm_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_adc_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_emif_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_gpio_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_ipc_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_pie_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_dma_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_sdfm_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_sysctrl_defines.h: + +C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_defaultisr.h: + +../i2c_oled.h: + +../fonts.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/string.h: + +C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/xlocale/_string.h: + diff --git a/i2c_ex1_master/CPU1_RAM/i2c_ex1_master.map b/i2c_ex1_master/CPU1_RAM/i2c_ex1_master.map new file mode 100644 index 0000000..7be7815 --- /dev/null +++ b/i2c_ex1_master/CPU1_RAM/i2c_ex1_master.map @@ -0,0 +1,1326 @@ +****************************************************************************** + TMS320C2000 Linker PC v22.6.0 +****************************************************************************** +>> Linked Fri Aug 9 12:18:59 2024 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "code_start" address: 00000000 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- +PAGE 0: + BEGIN 00000000 00000002 00000002 00000000 RWIX + BOOT_RSVD 00000002 000001af 00000000 000001af RWIX + RAMM0 000001b1 0000024f 00000028 00000227 RWIX + RAMM1 00000400 000003f8 00000100 000002f8 RWIX + RAMLS0 00008000 00000800 0000059c 00000264 RWIX + RAMLS1 00008800 00000800 00000000 00000800 RWIX + RAMLS2 00009000 00000800 00000000 00000800 RWIX + RAMLS3 00009800 00000800 00000000 00000800 RWIX + RAMLS4 0000a000 00000800 00000000 00000800 RWIX + RAMLS5 0000a800 00000800 0000042e 000003d2 RWIX + RAMLS6 0000b000 00000800 00000500 00000300 RWIX + RAMLS7 0000b800 00000800 00000000 00000800 RWIX + RAMD0 0000c000 00000800 00000800 00000000 RWIX + RAMD1 0000c800 00000800 00000800 00000000 RWIX + RAMGS0 0000d000 00001000 00000000 00001000 RWIX + RAMGS1 0000e000 00001000 00000000 00001000 RWIX + RAMGS2 0000f000 00001000 00000000 00001000 RWIX + RAMGS3 00010000 00001000 00000000 00001000 RWIX + RAMGS4 00011000 00001000 00000000 00001000 RWIX + RAMGS5 00012000 00001000 00000000 00001000 RWIX + RAMGS6 00013000 00001000 00000000 00001000 RWIX + RAMGS7 00014000 00001000 00000000 00001000 RWIX + RAMGS8 00015000 00001000 00000000 00001000 RWIX + RAMGS9 00016000 00001000 00000000 00001000 RWIX + RAMGS10 00017000 00001000 00000000 00001000 RWIX + RAMGS11 00018000 00001000 00000000 00001000 RWIX + RAMGS12 00019000 00001000 00000000 00001000 RWIX + RAMGS13 0001a000 00001000 00000000 00001000 RWIX + RAMGS14 0001b000 00001000 00000000 00001000 RWIX + RAMGS15 0001c000 00000ff8 00000000 00000ff8 RWIX + CMTOCPURAM 00038000 00000800 00000000 00000800 RWIX + CPUTOCMRAM 00039000 00000800 00000000 00000800 RWIX + CPU1TOCPU2RAM 0003a000 00000800 00000000 00000800 RWIX + CPU2TOCPU1RAM 0003b000 00000800 00000000 00000800 RWIX + CANA_MSG_RAM 00049000 00000800 00000000 00000800 RWIX + CANB_MSG_RAM 0004b000 00000800 00000000 00000800 RWIX + FLASH0 00080000 00002000 00000000 00002000 RWIX + FLASH1 00082000 00002000 00000000 00002000 RWIX + FLASH2 00084000 00002000 00000000 00002000 RWIX + FLASH3 00086000 00002000 00000000 00002000 RWIX + FLASH4 00088000 00008000 00000000 00008000 RWIX + FLASH5 00090000 00008000 00000000 00008000 RWIX + FLASH6 00098000 00008000 00000000 00008000 RWIX + FLASH7 000a0000 00008000 00000000 00008000 RWIX + FLASH8 000a8000 00008000 00000000 00008000 RWIX + FLASH9 000b0000 00008000 00000000 00008000 RWIX + FLASH10 000b8000 00002000 00000000 00002000 RWIX + FLASH11 000ba000 00002000 00000000 00002000 RWIX + FLASH12 000bc000 00002000 00000000 00002000 RWIX + FLASH13 000be000 00002000 00000000 00002000 RWIX + RESET 003fffc0 00000002 00000000 00000002 RWIX + +PAGE 1: + ADCARESULT 00000b00 00000018 00000000 00000018 RWIX + ADCBRESULT 00000b20 00000018 00000000 00000018 RWIX + ADCCRESULT 00000b40 00000018 00000000 00000018 RWIX + ADCDRESULT 00000b60 00000018 00000000 00000018 RWIX + CPUTIMER0 00000c00 00000008 00000000 00000008 RWIX + CPUTIMER1 00000c08 00000008 00000000 00000008 RWIX + CPUTIMER2 00000c10 00000008 00000000 00000008 RWIX + PIECTRL 00000ce0 0000001a 0000001a 00000000 RWIX + PIEVECTTABLE 00000d00 00000200 000001c0 00000040 RWIX + DMA 00001000 00000200 00000000 00000200 RWIX + CLA1 00001400 00000080 00000000 00000080 RWIX + CLB1LOGICCFG 00003000 00000052 00000000 00000052 RWIX + CLB1LOGICCTRL 00003100 00000040 00000000 00000040 RWIX + CLB1DATAEXCH 00003180 00000080 00000000 00000080 RWIX + CLB2LOGICCFG 00003200 00000052 00000000 00000052 RWIX + CLB2LOGICCTRL 00003300 00000040 00000000 00000040 RWIX + CLB2DATAEXCH 00003380 00000080 00000000 00000080 RWIX + CLB3LOGICCFG 00003400 00000052 00000000 00000052 RWIX + CLB3LOGICCTRL 00003500 00000040 00000000 00000040 RWIX + CLB3DATAEXCH 00003580 00000080 00000000 00000080 RWIX + CLB4LOGICCFG 00003600 00000052 00000000 00000052 RWIX + CLB4LOGICCTRL 00003700 00000040 00000000 00000040 RWIX + CLB4DATAEXCH 00003780 00000080 00000000 00000080 RWIX + CLB5LOGICCFG 00003800 00000052 00000000 00000052 RWIX + CLB5LOGICCTRL 00003900 00000040 00000000 00000040 RWIX + CLB5DATAEXCH 00003980 00000080 00000000 00000080 RWIX + CLB6LOGICCFG 00003a00 00000052 00000000 00000052 RWIX + CLB6LOGICCTRL 00003b00 00000040 00000000 00000040 RWIX + CLB6DATAEXCH 00003b80 00000080 00000000 00000080 RWIX + CLB7LOGICCFG 00003c00 00000052 00000000 00000052 RWIX + CLB7LOGICCTRL 00003d00 00000040 00000000 00000040 RWIX + CLB7DATAEXCH 00003d80 00000080 00000000 00000080 RWIX + CLB8LOGICCFG 00003e00 00000052 00000000 00000052 RWIX + CLB8LOGICCTRL 00003f00 00000040 00000000 00000040 RWIX + CLB8DATAEXCH 00003f80 00000080 00000000 00000080 RWIX + EPWM1 00004000 00000100 00000000 00000100 RWIX + EPWM2 00004100 00000100 00000000 00000100 RWIX + EPWM3 00004200 00000100 00000000 00000100 RWIX + EPWM4 00004300 00000100 00000000 00000100 RWIX + EPWM5 00004400 00000100 00000000 00000100 RWIX + EPWM6 00004500 00000100 00000000 00000100 RWIX + EPWM7 00004600 00000100 00000000 00000100 RWIX + EPWM8 00004700 00000100 00000000 00000100 RWIX + EPWM9 00004800 00000100 00000000 00000100 RWIX + EPWM10 00004900 00000100 00000000 00000100 RWIX + EPWM11 00004a00 00000100 00000000 00000100 RWIX + EPWM12 00004b00 00000100 00000000 00000100 RWIX + EPWM13 00004c00 00000100 00000000 00000100 RWIX + EPWM14 00004d00 00000100 00000000 00000100 RWIX + EPWM15 00004e00 00000100 00000000 00000100 RWIX + EPWM16 00004f00 00000100 00000000 00000100 RWIX + EQEP1 00005100 00000040 00000000 00000040 RWIX + EQEP2 00005140 00000040 00000000 00000040 RWIX + EQEP3 00005180 00000040 00000000 00000040 RWIX + ECAP1 00005200 00000020 00000000 00000020 RWIX + ECAP2 00005240 00000020 00000000 00000020 RWIX + ECAP3 00005280 00000020 00000000 00000020 RWIX + ECAP4 000052c0 00000020 00000000 00000020 RWIX + ECAP5 00005300 00000020 00000000 00000020 RWIX + ECAP6 00005340 00000020 00000000 00000020 RWIX + HRCAP6 00005360 00000020 00000000 00000020 RWIX + ECAP7 00005380 00000020 00000000 00000020 RWIX + HRCAP7 000053a0 00000020 00000000 00000020 RWIX + DACA 00005c00 00000008 00000000 00000008 RWIX + DACB 00005c10 00000008 00000000 00000008 RWIX + DACC 00005c20 00000008 00000000 00000008 RWIX + CMPSS1 00005c80 00000020 00000000 00000020 RWIX + CMPSS2 00005ca0 00000020 00000000 00000020 RWIX + CMPSS3 00005cc0 00000020 00000000 00000020 RWIX + CMPSS4 00005ce0 00000020 00000000 00000020 RWIX + CMPSS5 00005d00 00000020 00000000 00000020 RWIX + CMPSS6 00005d20 00000020 00000000 00000020 RWIX + CMPSS7 00005d40 00000020 00000000 00000020 RWIX + CMPSS8 00005d60 00000020 00000000 00000020 RWIX + SDFM1 00005e00 00000080 00000000 00000080 RWIX + SDFM2 00005e80 00000080 00000000 00000080 RWIX + MCBSPA 00006000 00000024 00000000 00000024 RWIX + MCBSPB 00006040 00000024 00000000 00000024 RWIX + SPIA 00006100 00000010 00000000 00000010 RWIX + SPIB 00006110 00000010 00000000 00000010 RWIX + SPIC 00006120 00000010 00000000 00000010 RWIX + SPID 00006130 00000010 00000000 00000010 RWIX + BGCRCCPU 00006340 00000040 00000000 00000040 RWIX + BGCRCCLA1 00006380 00000040 00000000 00000040 RWIX + PMBUSA 00006400 00000020 00000000 00000020 RWIX + FSITXA 00006600 00000050 00000000 00000050 RWIX + FSIRXA 00006680 00000050 00000000 00000050 RWIX + FSITXB 00006700 00000050 00000000 00000050 RWIX + FSIRXB 00006780 00000050 00000000 00000050 RWIX + FSIRXC 00006880 00000050 00000000 00000050 RWIX + FSIRXD 00006980 00000050 00000000 00000050 RWIX + FSIRXE 00006a80 00000050 00000000 00000050 RWIX + FSIRXF 00006b80 00000050 00000000 00000050 RWIX + FSIRXG 00006c80 00000050 00000000 00000050 RWIX + FSIRXH 00006d80 00000050 00000000 00000050 RWIX + WD 00007000 0000002c 0000002b 00000001 RWIX + NMIINTRUPT 00007060 00000010 00000000 00000010 RWIX + XINT 00007070 0000000c 00000000 0000000c RWIX + SCIA 00007200 00000010 00000000 00000010 RWIX + SCIB 00007210 00000010 00000000 00000010 RWIX + SCIC 00007220 00000010 00000000 00000010 RWIX + SCID 00007230 00000010 00000000 00000010 RWIX + I2CA 00007300 00000022 00000022 00000000 RWIX + I2CB 00007340 00000022 00000000 00000022 RWIX + ADCA 00007400 00000080 00000000 00000080 RWIX + ADCB 00007480 00000080 00000000 00000080 RWIX + ADCC 00007500 00000080 00000000 00000080 RWIX + ADCD 00007580 00000080 00000000 00000080 RWIX + INPUTXBAR 00007900 00000020 00000000 00000020 RWIX + XBAR 00007920 00000020 00000000 00000020 RWIX + SYNCSOC 00007940 00000006 00000000 00000006 RWIX + CLBINPUTXBAR 00007960 00000020 00000000 00000020 RWIX + DMACLASRCSEL 00007980 0000001a 00000000 0000001a RWIX + EPWMXBAR 00007a00 00000040 00000000 00000040 RWIX + CLBXBAR 00007a40 00000040 00000000 00000040 RWIX + OUTPUTXBAR 00007a80 00000040 00000000 00000040 RWIX + CLBOUTPUTXBAR 00007bc0 00000040 00000000 00000040 RWIX + GPIOCTRL 00007c00 00000200 00000180 00000080 RWIX + GPIODATA 00007f00 00000040 00000030 00000010 RWIX + GPIODATAREAD 00007f80 00000010 00000000 00000010 RWIX + EMIF1 00047000 00000070 00000000 00000070 RWIX + EMIF2 00047800 00000070 00000000 00000070 RWIX + CANA 00048000 00000200 00000000 00000200 RWIX + CANB 0004a000 00000200 00000000 00000200 RWIX + ESCSS 00057e00 00000024 00000000 00000024 RWIX + ESCSSCONFIG 00057f00 00000016 00000000 00000016 RWIX + MCANASS 0005c400 0000002c 00000000 0000002c RWIX + MCANA 0005c600 00000100 00000000 00000100 RWIX + MCANAERR 0005c800 00000210 00000000 00000210 RWIX + CPU1TOCPU2IPC 0005ce00 00000026 00000000 00000026 RWIX + CPU1TOCMIPC 0005ce40 00000026 00000000 00000026 RWIX + DEVCFG 0005d000 000001a0 000001a0 00000000 RWIX + CLKCFG 0005d200 00000100 0000003a 000000c6 RWIX + CPUSYS 0005d300 000000a0 0000009c 00000004 RWIX + SYSSTATUS 0005d400 00000100 00000000 00000100 RWIX + SYSPERIPHAC 0005d500 00000200 00000000 00000200 RWIX + ANALOGSUBSYS 0005d700 00000100 0000003e 000000c2 RWIX + CMCONF 0005dc00 00000400 00000000 00000400 RWIX + DCC0 0005e700 00000038 0000002c 0000000c RWIX + DCC1 0005e740 00000038 0000002c 0000000c RWIX + DCC2 0005e780 00000038 0000002c 0000000c RWIX + ERADGLOBAL 0005e800 00000014 00000000 00000014 RWIX + ERADHWBP1 0005e900 00000008 00000000 00000008 RWIX + ERADHWBP2 0005e908 00000008 00000000 00000008 RWIX + ERADHWBP3 0005e910 00000008 00000000 00000008 RWIX + ERADHWBP4 0005e918 00000008 00000000 00000008 RWIX + ERADHWBP5 0005e920 00000008 00000000 00000008 RWIX + ERADHWBP6 0005e928 00000008 00000000 00000008 RWIX + ERADHWBP7 0005e930 00000008 00000000 00000008 RWIX + ERADHWBP8 0005e938 00000008 00000000 00000008 RWIX + ERADCOUNTER1 0005e980 00000010 00000000 00000010 RWIX + ERADCOUNTER2 0005e990 00000010 00000000 00000010 RWIX + ERADCOUNTER3 0005e9a0 00000010 00000000 00000010 RWIX + ERADCOUNTER4 0005e9b0 00000010 00000000 00000010 RWIX + ERADCRCGLOBAL 0005ea00 00000010 00000000 00000010 RWIX + ERADCRC1 0005ea10 00000010 00000000 00000010 RWIX + ERADCRC2 0005ea20 00000010 00000000 00000010 RWIX + ERADCRC3 0005ea30 00000010 00000000 00000010 RWIX + ERADCRC4 0005ea40 00000010 00000000 00000010 RWIX + ERADCRC5 0005ea50 00000010 00000000 00000010 RWIX + ERADCRC6 0005ea60 00000010 00000000 00000010 RWIX + ERADCRC7 0005ea70 00000010 00000000 00000010 RWIX + ERADCRC8 0005ea80 00000010 00000000 00000010 RWIX + DCSMZ1 0005f000 0000003e 00000000 0000003e RWIX + DCSMZ2 0005f080 0000003e 00000000 0000003e RWIX + DCSMCOMMON 0005f0c0 00000020 00000000 00000020 RWIX + MEMCFG 0005f400 000000c0 00000000 000000c0 RWIX + EMIF1CONFIG 0005f4c0 00000020 00000000 00000020 RWIX + EMIF2CONFIG 0005f4e0 00000020 00000000 00000020 RWIX + ACCESSPROTECTION 0005f500 00000040 00000000 00000040 RWIX + MEMORYERROR 0005f540 00000040 00000000 00000040 RWIX + ROMWAITSTATE 0005f580 00000008 00000000 00000008 RWIX + ROMPREFETCH 0005f588 00000008 00000000 00000008 RWIX + TESTERROR 0005f590 00000010 00000000 00000010 RWIX + FLASH0CTRL 0005f800 00000182 00000000 00000182 RWIX + FLASH0ECC 0005fb00 00000028 00000000 00000028 RWIX + DCSMZ1OTP 00078000 00000020 00000000 00000020 RWIX + DCSMZ2OTP 00078200 00000020 00000000 00000020 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +codestart +* 0 00000000 00000002 + 00000000 00000002 f2838x_codestartbranch.obj (codestart) + +.cinit 0 000001b8 00000024 + 000001b8 00000008 (.cinit..data.load) [load image, compression = lzss] + 000001c0 00000006 (__TI_handler_table) + 000001c6 00000004 (.cinit..bss.load) [load image, compression = zero_init] + 000001ca 00000004 (.cinit.PieVectTableFile.load) [load image, compression = zero_init] + 000001ce 00000002 --HOLE-- [fill = 0] + 000001d0 0000000c (__TI_cinit_table) + +.reset 0 003fffc0 00000000 DSECT + +.stack 0 00000400 00000100 UNINITIALIZED + 00000400 00000100 --HOLE-- + +.bss 0 0000a800 00000424 UNINITIALIZED + 0000a800 00000400 i2c_oled.obj (.bss:SSD1306_Buffer) + 0000ac00 00000010 i2c_oled.obj (.bss:I2C_RXdata) + 0000ac10 00000010 i2c_oled.obj (.bss:I2C_TXdata) + 0000ac20 00000004 i2c_oled.obj (.bss) + +.init_array +* 0 000001b1 00000000 UNINITIALIZED + +.data 0 0000ac24 0000000a UNINITIALIZED + 0000ac24 00000006 rts2800_fpu64_eabi.lib : exit.c.obj (.data) + 0000ac2a 00000002 : _lock.c.obj (.data:_lock) + 0000ac2c 00000002 : _lock.c.obj (.data:_unlock) + +.const 0 0000b000 00000500 + 0000b000 00000340 i2c_ex1_master.obj (.const:.string:$P$T0$1) + 0000b340 000001c0 f2838x_pievect.obj (.const) + +.TI.ramfunc +* 0 000001b1 00000004 + 000001b1 00000004 f2838x_usdelay.obj (.TI.ramfunc) + +PieVectTableFile +* 1 00000d00 000001c0 UNINITIALIZED + 00000d00 000001c0 f2838x_globalvariabledefs.obj (PieVectTableFile) + +EmuKeyVar +* 1 00000d00 00000000 UNINITIALIZED + +EmuBModeVar +* 1 00000d00 00000000 UNINITIALIZED + +EmuBootPinsVar +* 1 00000d00 00000000 UNINITIALIZED + +FlashCallbackVar +* 1 00000d00 00000000 UNINITIALIZED + +FlashScalingVar +* 1 00000d00 00000000 UNINITIALIZED + +AnalogSubsysRegsFile +* 1 0005d700 0000003e UNINITIALIZED + 0005d700 0000003e f2838x_globalvariabledefs.obj (AnalogSubsysRegsFile) + +ClkCfgRegsFile +* 1 0005d200 0000003a UNINITIALIZED + 0005d200 0000003a f2838x_globalvariabledefs.obj (ClkCfgRegsFile) + +CpuSysRegsFile +* 1 0005d300 0000009c UNINITIALIZED + 0005d300 0000009c f2838x_globalvariabledefs.obj (CpuSysRegsFile) + +Dcc0RegsFile +* 1 0005e700 0000002c UNINITIALIZED + 0005e700 0000002c f2838x_globalvariabledefs.obj (Dcc0RegsFile) + +Dcc1RegsFile +* 1 0005e740 0000002c UNINITIALIZED + 0005e740 0000002c f2838x_globalvariabledefs.obj (Dcc1RegsFile) + +Dcc2RegsFile +* 1 0005e780 0000002c UNINITIALIZED + 0005e780 0000002c f2838x_globalvariabledefs.obj (Dcc2RegsFile) + +DevCfgRegsFile +* 1 0005d000 000001a0 UNINITIALIZED + 0005d000 000001a0 f2838x_globalvariabledefs.obj (DevCfgRegsFile) + +GpioCtrlRegsFile +* 1 00007c00 00000180 UNINITIALIZED + 00007c00 00000180 f2838x_globalvariabledefs.obj (GpioCtrlRegsFile) + +GpioDataRegsFile +* 1 00007f00 00000030 UNINITIALIZED + 00007f00 00000030 f2838x_globalvariabledefs.obj (GpioDataRegsFile) + +I2caRegsFile +* 1 00007300 00000022 UNINITIALIZED + 00007300 00000022 f2838x_globalvariabledefs.obj (I2caRegsFile) + +PieCtrlRegsFile +* 1 00000ce0 0000001a UNINITIALIZED + 00000ce0 0000001a f2838x_globalvariabledefs.obj (PieCtrlRegsFile) + +WdRegsFile +* 1 00007000 0000002b UNINITIALIZED + 00007000 0000002b f2838x_globalvariabledefs.obj (WdRegsFile) + +.text.1 0 00008000 0000059c + 00008000 0000000a f2838x_defaultisr.obj (.text:ECAP6_2_ISR) + 0000800a 0000000a f2838x_defaultisr.obj (.text:ECAP6_ISR) + 00008014 0000000a f2838x_defaultisr.obj (.text:ECAP7_2_ISR) + 0000801e 0000000a f2838x_defaultisr.obj (.text:ECAP7_ISR) + 00008028 0000000a f2838x_defaultisr.obj (.text:ECATRST_ISR) + 00008032 0000000a f2838x_defaultisr.obj (.text:ECATSYNC0_ISR) + 0000803c 0000000a f2838x_defaultisr.obj (.text:ECATSYNC1_ISR) + 00008046 0000000a f2838x_defaultisr.obj (.text:ECAT_ISR) + 00008050 0000000a f2838x_defaultisr.obj (.text:EMU_ISR) + 0000805a 0000000a f2838x_defaultisr.obj (.text:EPWM10_ISR) + 00008064 0000000a f2838x_defaultisr.obj (.text:EPWM10_TZ_ISR) + 0000806e 0000000a f2838x_defaultisr.obj (.text:EPWM11_ISR) + 00008078 0000000a f2838x_defaultisr.obj (.text:EPWM11_TZ_ISR) + 00008082 0000000a f2838x_defaultisr.obj (.text:EPWM12_ISR) + 0000808c 0000000a f2838x_defaultisr.obj (.text:EPWM12_TZ_ISR) + 00008096 0000000a f2838x_defaultisr.obj (.text:EPWM13_ISR) + 000080a0 0000000a f2838x_defaultisr.obj (.text:EPWM13_TZ_ISR) + 000080aa 0000000a f2838x_defaultisr.obj (.text:EPWM14_ISR) + 000080b4 0000000a f2838x_defaultisr.obj (.text:EPWM14_TZ_ISR) + 000080be 0000000a f2838x_defaultisr.obj (.text:EPWM15_ISR) + 000080c8 0000000a f2838x_defaultisr.obj (.text:EPWM15_TZ_ISR) + 000080d2 0000000a f2838x_defaultisr.obj (.text:EPWM16_ISR) + 000080dc 0000000a f2838x_defaultisr.obj (.text:EPWM16_TZ_ISR) + 000080e6 0000000a f2838x_defaultisr.obj (.text:EPWM1_ISR) + 000080f0 0000000a f2838x_defaultisr.obj (.text:EPWM1_TZ_ISR) + 000080fa 0000000a f2838x_defaultisr.obj (.text:EPWM2_ISR) + 00008104 0000000a f2838x_defaultisr.obj (.text:EPWM2_TZ_ISR) + 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f2838x_defaultisr.obj (.text:ECAP2_ISR) + 0000cfe1 0000000a f2838x_defaultisr.obj (.text:ECAP3_ISR) + 0000cfeb 0000000a f2838x_defaultisr.obj (.text:ECAP4_ISR) + 0000cff5 0000000a f2838x_defaultisr.obj (.text:ECAP5_ISR) + 0000cfff 00000001 rts2800_fpu64_eabi.lib : startup.c.obj (.text) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + f2838x_defaultisr.obj 2063 0 0 + f2838x_globalvariabledefs.obj 0 0 1807 + i2c_oled.obj 735 0 1060 + f2838x_sysctrl.obj 1343 0 0 + i2c_ex1_master.obj 97 832 0 + f2838x_gpio.obj 612 0 0 + f2838x_pievect.obj 38 448 0 + f2838x_piectrl.obj 31 0 0 + f2838x_codestartbranch.obj 10 0 0 + f2838x_usdelay.obj 4 0 0 + +--+-------------------------------+------+---------+---------+ + Total: 4933 1280 2867 + + C:\ti\ccs1240\ccs\tools\compiler\ti-cgt-c2000_22.6.0.LTS\lib\rts2800_fpu64_eabi.lib + s_ceil.c.obj 216 0 0 + fs_div28.asm.obj 136 0 0 + exit.c.obj 41 0 6 + copy_decompress_lzss.c.obj 46 0 0 + autoinit.c.obj 43 0 0 + memcpy.c.obj 29 0 0 + boot28.asm.obj 25 0 0 + ll_aox28.asm.obj 24 0 0 + _lock.c.obj 9 0 4 + args_main.c.obj 12 0 0 + copy_decompress_none.c.obj 8 0 0 + memset.c.obj 7 0 0 + copy_zero_init.c.obj 6 0 0 + pre_init.c.obj 2 0 0 + startup.c.obj 1 0 0 + +--+-------------------------------+------+---------+---------+ + Total: 605 0 10 + + Stack: 0 0 256 + Linker Generated: 0 34 0 + +--+-------------------------------+------+---------+---------+ + Grand Total: 5538 1314 3133 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 000001d0 records: 3, size/record: 4, table size: 12 + .data: load addr=000001b8, load size=00000008 bytes, run addr=0000ac24, run size=0000000a bytes, compression=lzss + .bss: load addr=000001c6, load size=00000004 bytes, run addr=0000a800, run size=00000424 bytes, compression=zero_init + PieVectTableFile: load addr=000001ca, load size=00000004 bytes, run addr=00000d00, run size=000001c0 bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 000001c0 records: 3, size/record: 2, table size: 6 + index: 0, handler: __TI_zero_init + index: 1, handler: __TI_decompress_lzss + index: 2, handler: __TI_decompress_none + + +GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE + +address data page name +-------- ---------------- ---- +00000400 10 (00000400) __stack + +00000ce0 33 (00000cc0) PieCtrlRegs + +00000d00 34 (00000d00) PieVectTable + +00007000 1c0 (00007000) WdRegs + +00007300 1cc (00007300) I2caRegs + +00007c00 1f0 (00007c00) GpioCtrlRegs + +00007f00 1fc (00007f00) GpioDataRegs + +0000ac00 2b0 (0000ac00) I2C_RXdata +0000ac10 2b0 (0000ac00) I2C_TXdata +0000ac24 2b0 (0000ac00) __TI_enable_exit_profile_output +0000ac26 2b0 (0000ac00) __TI_cleanup_ptr +0000ac28 2b0 (0000ac00) __TI_dtors_ptr +0000ac2a 2b0 (0000ac00) _lock +0000ac2c 2b0 (0000ac00) _unlock + +0000b340 2cd (0000b340) PieVectTableInit + +0005d000 1740 (0005d000) DevCfgRegs + +0005d200 1748 (0005d200) ClkCfgRegs + +0005d300 174c (0005d300) CpuSysRegs + +0005d700 175c (0005d700) AnalogSubsysRegs + +0005e700 179c (0005e700) Dcc0Regs + +0005e740 179d (0005e740) Dcc1Regs + +0005e780 179e (0005e780) Dcc2Regs + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +page address name +---- ------- ---- +0 0000cd43 ADCA1_ISR +0 0000cd4d ADCA2_ISR +0 0000cd57 ADCA3_ISR +0 0000cd61 ADCA4_ISR +0 0000cd6b ADCA_EVT_ISR +0 0000cd75 ADCB1_ISR +0 0000cd7f ADCB2_ISR +0 0000cd89 ADCB3_ISR +0 0000cd93 ADCB4_ISR +0 0000cd9d ADCB_EVT_ISR +0 0000cda7 ADCC1_ISR +0 0000cdb1 ADCC2_ISR +0 0000cdbb ADCC3_ISR +0 0000cdc5 ADCC4_ISR +0 0000cdcf ADCC_EVT_ISR +0 0000cdd9 ADCD1_ISR +0 0000cde3 ADCD2_ISR +0 0000cded ADCD3_ISR +0 0000cdf7 ADCD4_ISR +0 0000ce01 ADCD_EVT_ISR +1 0005d700 AnalogSubsysRegs +0 0000ce0b AuxAuxClkSel +0 0000856d AuxIntOsc2Sel +0 0000ccec AuxXtalOscSESel +0 0000ccfd AuxXtalOscSel +0 0000cb79 C$$EXIT +0 0000ce15 CANA0_ISR +0 0000ce1f CANA1_ISR +0 0000ce29 CANB0_ISR +0 0000ce33 CANB1_ISR +0 0000ce3d CIPC0_ISR +0 0000ce47 CIPC1_ISR +0 0000ce51 CIPC2_ISR +0 0000ce5b CIPC3_ISR +0 0000ce65 CLA1CRC_ISR +0 0000ce6f CLA1_1_ISR +0 0000ce79 CLA1_2_ISR +0 0000ce83 CLA1_3_ISR +0 0000ce8d CLA1_4_ISR +0 0000ce97 CLA1_5_ISR +0 0000cea1 CLA1_6_ISR +0 0000ceab CLA1_7_ISR +0 0000ceb5 CLA1_8_ISR +0 0000cebf CLA_OVERFLOW_ISR +0 0000cec9 CLA_UNDERFLOW_ISR +0 0000ced3 CLB1_ISR +0 0000cedd CLB2_ISR +0 0000cee7 CLB3_ISR +0 0000cef1 CLB4_ISR +0 0000cefb CLB5_ISR +0 0000cf05 CLB6_ISR +0 0000cf0f CLB7_ISR +0 0000cf19 CLB8_ISR +0 0000cf23 CMTOCPUXIPC0_ISR +0 0000cf2d CMTOCPUXIPC1_ISR +0 0000cf37 CMTOCPUXIPC2_ISR +0 0000cf41 CMTOCPUXIPC3_ISR +0 0000cf4b CMTOCPUXIPC4_ISR +0 0000cf55 CMTOCPUXIPC5_ISR +0 0000cf5f CMTOCPUXIPC6_ISR +0 0000cf69 CMTOCPUXIPC7_ISR +0 0000cf73 CM_STATUS_ISR +0 0000cf7d CPUCRC_ISR +1 0005d200 ClkCfgRegs +0 0000c800 ComputeCntrSeedValue +1 0005d300 CpuSysRegs +0 0000cf87 DATALOG_ISR +0 0000cf91 DMA_CH1_ISR +0 0000cf9b DMA_CH2_ISR +0 0000cfa5 DMA_CH3_ISR +0 0000cfaf DMA_CH4_ISR +0 0000cfb9 DMA_CH5_ISR +0 0000cfc3 DMA_CH6_ISR +1 0005e700 Dcc0Regs +1 0005e740 Dcc1Regs +1 0005e780 Dcc2Regs +1 0005d000 DevCfgRegs +0 0000cd0e DisableDog +0 0000cfcd ECAP1_ISR +0 0000cfd7 ECAP2_ISR +0 0000cfe1 ECAP3_ISR +0 0000cfeb ECAP4_ISR +0 0000cff5 ECAP5_ISR +0 00008000 ECAP6_2_ISR +0 0000800a ECAP6_ISR +0 00008014 ECAP7_2_ISR +0 0000801e ECAP7_ISR +0 00008028 ECATRST_ISR +0 00008032 ECATSYNC0_ISR +0 0000803c ECATSYNC1_ISR +0 00008046 ECAT_ISR +0 0000cd2a EMPTY_ISR +0 00008050 EMU_ISR +0 0000805a EPWM10_ISR +0 00008064 EPWM10_TZ_ISR +0 0000806e EPWM11_ISR +0 00008078 EPWM11_TZ_ISR +0 00008082 EPWM12_ISR +0 0000808c EPWM12_TZ_ISR +0 00008096 EPWM13_ISR +0 000080a0 EPWM13_TZ_ISR +0 000080aa EPWM14_ISR +0 000080b4 EPWM14_TZ_ISR +0 000080be EPWM15_ISR +0 000080c8 EPWM15_TZ_ISR +0 000080d2 EPWM16_ISR +0 000080dc EPWM16_TZ_ISR +0 000080e6 EPWM1_ISR +0 000080f0 EPWM1_TZ_ISR +0 000080fa EPWM2_ISR +0 00008104 EPWM2_TZ_ISR +0 0000810e EPWM3_ISR +0 00008118 EPWM3_TZ_ISR +0 00008122 EPWM4_ISR +0 0000812c EPWM4_TZ_ISR +0 00008136 EPWM5_ISR +0 00008140 EPWM5_TZ_ISR +0 0000814a EPWM6_ISR +0 00008154 EPWM6_TZ_ISR +0 0000815e EPWM7_ISR +0 00008168 EPWM7_TZ_ISR +0 00008172 EPWM8_ISR +0 0000817c EPWM8_TZ_ISR +0 00008186 EPWM9_ISR +0 00008190 EPWM9_TZ_ISR +0 0000819a EQEP1_ISR +0 000081a4 EQEP2_ISR +0 000081ae EQEP3_ISR +0 000001b1 F28x_usDelay +0 000081b8 FMC_ISR +0 000081c2 FPU_OFLOW_ISR +0 000081cc FPU_UFLOW_ISR +0 000081d6 FSIRXA1_ISR +0 000081e0 FSIRXA2_ISR +0 000081ea FSIRXB1_ISR +0 000081f4 FSIRXB2_ISR +0 000081fe FSIRXC1_ISR +0 00008208 FSIRXC2_ISR +0 00008212 FSIRXD1_ISR +0 0000821c FSIRXD2_ISR +0 00008226 FSIRXE1_ISR +0 00008230 FSIRXE2_ISR +0 0000823a FSIRXF1_ISR +0 00008244 FSIRXF2_ISR +0 0000824e FSIRXG1_ISR +0 00008258 FSIRXG2_ISR +0 00008262 FSIRXH1_ISR +0 0000826c FSIRXH2_ISR +0 00008276 FSITXA1_ISR +0 00008280 FSITXA2_ISR +0 0000828a FSITXB1_ISR +0 00008294 FSITXB2_ISR +0 0000cd1c GPIO_EnableUnbondedIOPullups +0 0000cc8c GPIO_EnableUnbondedIOPullupsFor176Pin +0 0000c14f GPIO_SetupPinMux +0 0000c24e GPIO_SetupPinOptions +1 00007c00 GpioCtrlRegs +1 00007f00 GpioDataRegs +0 0000829e I2CA_FIFO_ISR +0 000082a8 I2CA_HIGH_ISR +0 000082b2 I2CA_ISR +0 000082bc I2CB_FIFO_ISR +0 000082c6 I2CB_ISR +0 0000cbee I2CMaster_Init +0 0000c7c3 I2CWrite +0 0000ac00 I2C_RXdata +0 0000ac10 I2C_TXdata +1 00007300 I2caRegs +0 000082d0 ILLEGAL_ISR +0 0000c717 InitAuxPll +0 0000ca8b InitGpio +0 0000c665 InitPeripheralClocks +0 0000cc35 InitPieCtrl +0 0000cba2 InitPieVectTable +0 0000ca39 InitSysCtrl +0 0000c33b InitSysPll +0 0000c5b0 IsPLLValid +0 000082da MCANA_0_ISR +0 000082e4 MCANA_1_ISR +0 000082ee MCANA_ECC_ISR +0 000082f8 MCANA_WAKE_ISR +0 00008302 MCBSPA_RX_ISR +0 0000830c MCBSPA_TX_ISR +0 00008316 MCBSPB_RX_ISR +0 00008320 MCBSPB_TX_ISR +0 0000832a MPOST_ISR +0 00008334 NMI_ISR +0 0000833e NOTUSED_ISR +0 00008348 PIE_RESERVED_ISR +0 00008352 PMBUSA_ISR +1 00000ce0 PieCtrlRegs +1 00000d00 PieVectTable +0 0000b340 PieVectTableInit +0 0000835c RTOS_ISR +0 00008366 SCIA_RX_ISR +0 00008370 SCIA_TX_ISR +0 0000837a SCIB_RX_ISR +0 00008384 SCIB_TX_ISR +0 0000838e SCIC_RX_ISR +0 00008398 SCIC_TX_ISR +0 000083a2 SCID_RX_ISR +0 000083ac SCID_TX_ISR +0 000083b6 SDFM1DR1_ISR +0 000083c0 SDFM1DR2_ISR +0 000083ca SDFM1DR3_ISR +0 000083d4 SDFM1DR4_ISR +0 000083de SDFM1_ISR +0 000083e8 SDFM2DR1_ISR +0 000083f2 SDFM2DR2_ISR +0 000083fc SDFM2DR3_ISR +0 00008406 SDFM2DR4_ISR +0 00008410 SDFM2_ISR +0 0000841a SPIA_RX_ISR +0 00008424 SPIA_TX_ISR +0 0000842e SPIB_RX_ISR +0 00008438 SPIB_TX_ISR +0 00008442 SPIC_RX_ISR +0 0000844c SPIC_TX_ISR +0 00008456 SPID_RX_ISR +0 00008460 SPID_TX_ISR +0 0000c9df SSD1306_DrawPixel +0 0000c7f1 SSD1306_Fill +0 0000846a SSD1306_GotoXY +0 0000c000 SSD1306_Init +0 0000cadc SSD1306_UpdateScreen +0 0000cbc8 SSD1306_setPosition +0 00008474 SYS_ERR_ISR +0 0000847e SysIntOsc1Sel +0 00008575 SysIntOsc2Sel +0 0000ccd6 SysXtalOscSESel +0 0000cc12 SysXtalOscSel +0 00008488 TIMER0_ISR +0 00008492 TIMER1_ISR +0 0000849c TIMER2_ISR +0 000084a6 USBA_ISR +0 000084b0 USER10_ISR +0 000084ba USER11_ISR +0 000084c4 USER12_ISR +0 000084ce USER1_ISR +0 000084d8 USER2_ISR +0 000084e2 USER3_ISR +0 000084ec USER4_ISR +0 000084f6 USER5_ISR +0 00008500 USER6_ISR +0 0000850a USER7_ISR +0 00008514 USER8_ISR +0 0000851e USER9_ISR +0 0000c4f9 VerifyXTAL +0 00008528 WAKE_ISR +1 00007000 WdRegs +0 00008532 XINT1_ISR +0 0000853c XINT2_ISR +0 00008546 XINT3_ISR +0 00008550 XINT4_ISR +0 0000855a XINT5_ISR +0 000001d0 __TI_CINIT_Base +0 000001dc __TI_CINIT_Limit +0 000001dc __TI_CINIT_Warm +0 000001c0 __TI_Handler_Table_Base +0 000001c6 __TI_Handler_Table_Limit +0 00000500 __TI_STACK_END +abs 00000100 __TI_STACK_SIZE +0 0000cb4e __TI_auto_init_nobinit_nopinit +0 0000ac26 __TI_cleanup_ptr +0 0000cb20 __TI_decompress_lzss +0 0000857d __TI_decompress_none +0 0000ac28 __TI_dtors_ptr +0 0000ac24 __TI_enable_exit_profile_output +abs ffffffff __TI_pprof_out_hndl +abs ffffffff __TI_prof_data_size +abs ffffffff __TI_prof_data_start +0 00008594 __TI_zero_init +0 0000ccbe __c28xabi_andll +0 0000c895 __c28xabi_divf +0 0000ccc6 __c28xabi_orll +0 0000ccce __c28xabi_xorll +n/a UNDEFED __c_args__ +0 00000400 __stack +0 0000cd37 _args_main +0 0000cca5 _c_int00 +0 0000ac2a _lock +0 0000856c _nop +0 00008568 _register_lock +0 00008564 _register_unlock +0 0000cfff _system_post_cinit +0 0000859a _system_pre_init +0 0000ac2c _unlock +0 0000cb79 abort +0 0000c421 ceil +0 0000c421 ceill +0 00000000 code_start +0 0000cb7b exit +0 0000c91d main +0 0000cc54 memcpy +0 0000858d memset +0 0000c97e ssd1306_DrawBitmap + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +page address name +---- ------- ---- +0 00000000 code_start +0 000001b1 F28x_usDelay +0 000001c0 __TI_Handler_Table_Base +0 000001c6 __TI_Handler_Table_Limit +0 000001d0 __TI_CINIT_Base +0 000001dc __TI_CINIT_Limit +0 000001dc __TI_CINIT_Warm +0 00000400 __stack +0 00000500 __TI_STACK_END +0 00008000 ECAP6_2_ISR +0 0000800a ECAP6_ISR +0 00008014 ECAP7_2_ISR +0 0000801e ECAP7_ISR +0 00008028 ECATRST_ISR +0 00008032 ECATSYNC0_ISR +0 0000803c ECATSYNC1_ISR +0 00008046 ECAT_ISR +0 00008050 EMU_ISR +0 0000805a EPWM10_ISR +0 00008064 EPWM10_TZ_ISR +0 0000806e EPWM11_ISR +0 00008078 EPWM11_TZ_ISR +0 00008082 EPWM12_ISR +0 0000808c EPWM12_TZ_ISR +0 00008096 EPWM13_ISR +0 000080a0 EPWM13_TZ_ISR +0 000080aa EPWM14_ISR +0 000080b4 EPWM14_TZ_ISR +0 000080be EPWM15_ISR +0 000080c8 EPWM15_TZ_ISR +0 000080d2 EPWM16_ISR +0 000080dc EPWM16_TZ_ISR +0 000080e6 EPWM1_ISR +0 000080f0 EPWM1_TZ_ISR +0 000080fa EPWM2_ISR +0 00008104 EPWM2_TZ_ISR +0 0000810e EPWM3_ISR +0 00008118 EPWM3_TZ_ISR +0 00008122 EPWM4_ISR +0 0000812c EPWM4_TZ_ISR +0 00008136 EPWM5_ISR +0 00008140 EPWM5_TZ_ISR +0 0000814a EPWM6_ISR +0 00008154 EPWM6_TZ_ISR +0 0000815e EPWM7_ISR +0 00008168 EPWM7_TZ_ISR +0 00008172 EPWM8_ISR +0 0000817c EPWM8_TZ_ISR +0 00008186 EPWM9_ISR +0 00008190 EPWM9_TZ_ISR +0 0000819a EQEP1_ISR +0 000081a4 EQEP2_ISR +0 000081ae EQEP3_ISR +0 000081b8 FMC_ISR +0 000081c2 FPU_OFLOW_ISR +0 000081cc FPU_UFLOW_ISR +0 000081d6 FSIRXA1_ISR +0 000081e0 FSIRXA2_ISR +0 000081ea FSIRXB1_ISR +0 000081f4 FSIRXB2_ISR +0 000081fe FSIRXC1_ISR +0 00008208 FSIRXC2_ISR +0 00008212 FSIRXD1_ISR +0 0000821c FSIRXD2_ISR +0 00008226 FSIRXE1_ISR +0 00008230 FSIRXE2_ISR +0 0000823a FSIRXF1_ISR +0 00008244 FSIRXF2_ISR +0 0000824e FSIRXG1_ISR +0 00008258 FSIRXG2_ISR +0 00008262 FSIRXH1_ISR +0 0000826c FSIRXH2_ISR +0 00008276 FSITXA1_ISR +0 00008280 FSITXA2_ISR +0 0000828a FSITXB1_ISR +0 00008294 FSITXB2_ISR +0 0000829e I2CA_FIFO_ISR +0 000082a8 I2CA_HIGH_ISR +0 000082b2 I2CA_ISR +0 000082bc I2CB_FIFO_ISR +0 000082c6 I2CB_ISR +0 000082d0 ILLEGAL_ISR +0 000082da MCANA_0_ISR +0 000082e4 MCANA_1_ISR +0 000082ee MCANA_ECC_ISR +0 000082f8 MCANA_WAKE_ISR +0 00008302 MCBSPA_RX_ISR +0 0000830c MCBSPA_TX_ISR +0 00008316 MCBSPB_RX_ISR +0 00008320 MCBSPB_TX_ISR +0 0000832a MPOST_ISR +0 00008334 NMI_ISR +0 0000833e NOTUSED_ISR +0 00008348 PIE_RESERVED_ISR +0 00008352 PMBUSA_ISR +0 0000835c RTOS_ISR +0 00008366 SCIA_RX_ISR +0 00008370 SCIA_TX_ISR +0 0000837a SCIB_RX_ISR +0 00008384 SCIB_TX_ISR +0 0000838e SCIC_RX_ISR +0 00008398 SCIC_TX_ISR +0 000083a2 SCID_RX_ISR +0 000083ac SCID_TX_ISR +0 000083b6 SDFM1DR1_ISR +0 000083c0 SDFM1DR2_ISR +0 000083ca SDFM1DR3_ISR +0 000083d4 SDFM1DR4_ISR +0 000083de SDFM1_ISR +0 000083e8 SDFM2DR1_ISR +0 000083f2 SDFM2DR2_ISR +0 000083fc SDFM2DR3_ISR +0 00008406 SDFM2DR4_ISR +0 00008410 SDFM2_ISR +0 0000841a SPIA_RX_ISR +0 00008424 SPIA_TX_ISR +0 0000842e SPIB_RX_ISR +0 00008438 SPIB_TX_ISR +0 00008442 SPIC_RX_ISR +0 0000844c SPIC_TX_ISR +0 00008456 SPID_RX_ISR +0 00008460 SPID_TX_ISR +0 0000846a SSD1306_GotoXY +0 00008474 SYS_ERR_ISR +0 0000847e SysIntOsc1Sel +0 00008488 TIMER0_ISR +0 00008492 TIMER1_ISR +0 0000849c TIMER2_ISR +0 000084a6 USBA_ISR +0 000084b0 USER10_ISR +0 000084ba USER11_ISR +0 000084c4 USER12_ISR +0 000084ce USER1_ISR +0 000084d8 USER2_ISR +0 000084e2 USER3_ISR +0 000084ec USER4_ISR +0 000084f6 USER5_ISR +0 00008500 USER6_ISR +0 0000850a USER7_ISR +0 00008514 USER8_ISR +0 0000851e USER9_ISR +0 00008528 WAKE_ISR +0 00008532 XINT1_ISR +0 0000853c XINT2_ISR +0 00008546 XINT3_ISR +0 00008550 XINT4_ISR +0 0000855a XINT5_ISR +0 00008564 _register_unlock +0 00008568 _register_lock +0 0000856c _nop +0 0000856d AuxIntOsc2Sel +0 00008575 SysIntOsc2Sel +0 0000857d __TI_decompress_none +0 0000858d memset +0 00008594 __TI_zero_init +0 0000859a _system_pre_init +0 0000ac00 I2C_RXdata +0 0000ac10 I2C_TXdata +0 0000ac24 __TI_enable_exit_profile_output +0 0000ac26 __TI_cleanup_ptr +0 0000ac28 __TI_dtors_ptr +0 0000ac2a _lock +0 0000ac2c _unlock +0 0000b340 PieVectTableInit +0 0000c000 SSD1306_Init +0 0000c14f GPIO_SetupPinMux +0 0000c24e GPIO_SetupPinOptions +0 0000c33b InitSysPll +0 0000c421 ceil +0 0000c421 ceill +0 0000c4f9 VerifyXTAL +0 0000c5b0 IsPLLValid +0 0000c665 InitPeripheralClocks +0 0000c717 InitAuxPll +0 0000c7c3 I2CWrite +0 0000c7f1 SSD1306_Fill +0 0000c800 ComputeCntrSeedValue +0 0000c895 __c28xabi_divf +0 0000c91d main +0 0000c97e ssd1306_DrawBitmap +0 0000c9df SSD1306_DrawPixel +0 0000ca39 InitSysCtrl +0 0000ca8b InitGpio +0 0000cadc SSD1306_UpdateScreen +0 0000cb20 __TI_decompress_lzss +0 0000cb4e __TI_auto_init_nobinit_nopinit +0 0000cb79 C$$EXIT +0 0000cb79 abort +0 0000cb7b exit +0 0000cba2 InitPieVectTable +0 0000cbc8 SSD1306_setPosition +0 0000cbee I2CMaster_Init +0 0000cc12 SysXtalOscSel +0 0000cc35 InitPieCtrl +0 0000cc54 memcpy +0 0000cc8c GPIO_EnableUnbondedIOPullupsFor176Pin +0 0000cca5 _c_int00 +0 0000ccbe __c28xabi_andll +0 0000ccc6 __c28xabi_orll +0 0000ccce __c28xabi_xorll +0 0000ccd6 SysXtalOscSESel +0 0000ccec AuxXtalOscSESel +0 0000ccfd AuxXtalOscSel +0 0000cd0e DisableDog +0 0000cd1c GPIO_EnableUnbondedIOPullups +0 0000cd2a EMPTY_ISR +0 0000cd37 _args_main +0 0000cd43 ADCA1_ISR +0 0000cd4d ADCA2_ISR +0 0000cd57 ADCA3_ISR +0 0000cd61 ADCA4_ISR +0 0000cd6b ADCA_EVT_ISR +0 0000cd75 ADCB1_ISR +0 0000cd7f ADCB2_ISR +0 0000cd89 ADCB3_ISR +0 0000cd93 ADCB4_ISR +0 0000cd9d ADCB_EVT_ISR +0 0000cda7 ADCC1_ISR +0 0000cdb1 ADCC2_ISR +0 0000cdbb ADCC3_ISR +0 0000cdc5 ADCC4_ISR +0 0000cdcf ADCC_EVT_ISR +0 0000cdd9 ADCD1_ISR +0 0000cde3 ADCD2_ISR +0 0000cded ADCD3_ISR +0 0000cdf7 ADCD4_ISR +0 0000ce01 ADCD_EVT_ISR +0 0000ce0b AuxAuxClkSel +0 0000ce15 CANA0_ISR +0 0000ce1f CANA1_ISR +0 0000ce29 CANB0_ISR +0 0000ce33 CANB1_ISR +0 0000ce3d CIPC0_ISR +0 0000ce47 CIPC1_ISR +0 0000ce51 CIPC2_ISR +0 0000ce5b CIPC3_ISR +0 0000ce65 CLA1CRC_ISR +0 0000ce6f CLA1_1_ISR +0 0000ce79 CLA1_2_ISR +0 0000ce83 CLA1_3_ISR +0 0000ce8d CLA1_4_ISR +0 0000ce97 CLA1_5_ISR +0 0000cea1 CLA1_6_ISR +0 0000ceab CLA1_7_ISR +0 0000ceb5 CLA1_8_ISR +0 0000cebf CLA_OVERFLOW_ISR +0 0000cec9 CLA_UNDERFLOW_ISR +0 0000ced3 CLB1_ISR +0 0000cedd CLB2_ISR +0 0000cee7 CLB3_ISR +0 0000cef1 CLB4_ISR +0 0000cefb CLB5_ISR +0 0000cf05 CLB6_ISR +0 0000cf0f CLB7_ISR +0 0000cf19 CLB8_ISR +0 0000cf23 CMTOCPUXIPC0_ISR +0 0000cf2d CMTOCPUXIPC1_ISR +0 0000cf37 CMTOCPUXIPC2_ISR +0 0000cf41 CMTOCPUXIPC3_ISR +0 0000cf4b CMTOCPUXIPC4_ISR +0 0000cf55 CMTOCPUXIPC5_ISR +0 0000cf5f CMTOCPUXIPC6_ISR +0 0000cf69 CMTOCPUXIPC7_ISR +0 0000cf73 CM_STATUS_ISR +0 0000cf7d CPUCRC_ISR +0 0000cf87 DATALOG_ISR +0 0000cf91 DMA_CH1_ISR +0 0000cf9b DMA_CH2_ISR +0 0000cfa5 DMA_CH3_ISR +0 0000cfaf DMA_CH4_ISR +0 0000cfb9 DMA_CH5_ISR +0 0000cfc3 DMA_CH6_ISR +0 0000cfcd ECAP1_ISR +0 0000cfd7 ECAP2_ISR +0 0000cfe1 ECAP3_ISR +0 0000cfeb ECAP4_ISR +0 0000cff5 ECAP5_ISR +0 0000cfff _system_post_cinit +1 00000ce0 PieCtrlRegs +1 00000d00 PieVectTable +1 00007000 WdRegs +1 00007300 I2caRegs +1 00007c00 GpioCtrlRegs +1 00007f00 GpioDataRegs +1 0005d000 DevCfgRegs +1 0005d200 ClkCfgRegs +1 0005d300 CpuSysRegs +1 0005d700 AnalogSubsysRegs +1 0005e700 Dcc0Regs +1 0005e740 Dcc1Regs +1 0005e780 Dcc2Regs +abs 00000100 __TI_STACK_SIZE +abs ffffffff __TI_pprof_out_hndl +abs ffffffff __TI_prof_data_size +abs ffffffff __TI_prof_data_start +n/a UNDEFED __c_args__ + +[296 symbols] diff --git a/i2c_ex1_master/CPU1_RAM/i2c_ex1_master.obj b/i2c_ex1_master/CPU1_RAM/i2c_ex1_master.obj new file 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0xceb5 + + + + USER6_ISR + 0x8500 + + + + CLA1_2_ISR + 0xce79 + + + + ECAT_ISR + 0x8046 + + + + USER8_ISR + 0x8514 + + + + CM_STATUS_ISR + 0xcf73 + + + + MCBSPB_RX_ISR + 0x8316 + + + + MCBSPB_TX_ISR + 0x8320 + + + + CLB4_ISR + 0xcef1 + + + + SPIB_RX_ISR + 0x842e + + + + SPIB_TX_ISR + 0x8438 + + + + ECAP3_ISR + 0xcfe1 + + + + EPWM16_TZ_ISR + 0x80dc + + + + EPWM13_TZ_ISR + 0x80a0 + + + + EPWM1_ISR + 0x80e6 + + + + CIPC3_ISR + 0xce5b + + + + DMA_CH2_ISR + 0xcf9b + + + + USER12_ISR + 0x84c4 + + + + CMTOCPUXIPC0_ISR + 0xcf23 + + + + EPWM16_ISR + 0x80d2 + + + + XINT3_ISR + 0x8546 + + + + USER1_ISR + 0x84ce + + + + CLA1_3_ISR + 0xce83 + + + + I2CA_ISR + 0x82b2 + + + + CANA0_ISR + 0xce15 + + + + CANB0_ISR + 0xce29 + + + + CLB5_ISR + 0xcefb + + + + ECAP7_2_ISR + 0x8014 + + + + FSIRXA1_ISR + 0x81d6 + + + + EPWM1_TZ_ISR + 0x80f0 + + + + FSIRXB1_ISR + 0x81ea + + + + FSIRXC1_ISR + 0x81fe + + + + FSIRXD1_ISR + 0x8212 + + + + I2CA_FIFO_ISR + 0x829e + + + + FSIRXE1_ISR + 0x8226 + + + + FSIRXF1_ISR + 0x823a + + + + FSIRXG1_ISR + 0x824e + + + + FSIRXH1_ISR + 0x8262 + + + + EPWM2_ISR + 0x80fa + + + + USBA_ISR + 0x84a6 + + + + SDFM1DR4_ISR + 0x83d4 + + + + ADCD_EVT_ISR + 0xce01 + + + + DMA_CH3_ISR + 0xcfa5 + + + + FMC_ISR + 0x81b8 + + + + ADCC_EVT_ISR + 0xcdcf + + + + EPWM11_ISR + 0x806e + + + + DATALOG_ISR + 0xcf87 + + + + XINT2_ISR + 0x853c + + + + MCANA_0_ISR + 0x82da + + + + PIE_RESERVED_ISR + 0x8348 + + + + SCIB_RX_ISR + 0x837a + + + + SCIB_TX_ISR + 0x8384 + + + + I2CB_ISR + 0x82c6 + + + + CANA1_ISR + 0xce1f + + + + SPIC_RX_ISR + 0x8442 + + + + CANB1_ISR + 0xce33 + + + + CPUCRC_ISR + 0xcf7d + + + + CLB6_ISR + 0xcf05 + + + + SPIC_TX_ISR + 0x844c + + + + EPWM15_TZ_ISR + 0x80c8 + + + + FSIRXA2_ISR + 0x81e0 + + + + FSIRXB2_ISR + 0x81f4 + + + + EPWM12_TZ_ISR + 0x808c + + + + FSIRXC2_ISR + 0x8208 + + + + ILLEGAL_ISR + 0x82d0 + + + + FSIRXD2_ISR + 0x821c + + + + FSIRXE2_ISR + 0x8230 + + + + FSIRXF2_ISR + 0x8244 + + + + FSIRXG2_ISR + 0x8258 + + + + FSIRXH2_ISR + 0x826c + + + + EPWM3_ISR + 0x810e + + + + I2CA_HIGH_ISR + 0x82a8 + + + + FPU_UFLOW_ISR + 0x81cc + + + + TIMER0_ISR + 0x8488 + + + + EPWM10_ISR + 0x805a + + + + USER3_ISR + 0x84e2 + + + + MCANA_1_ISR + 0x82e4 + + + + ClkCfgRegs + 0x5d200 + + + + PieVectTable + 0xd00 + + + + GpioCtrlRegs + 0x7c00 + + + + Dcc0Regs + 0x5e700 + + + + CpuSysRegs + 0x5d300 + + + + I2caRegs + 0x7300 + + + + Dcc1Regs + 0x5e740 + + + + Dcc2Regs + 0x5e780 + + + + DevCfgRegs + 0x5d000 + + + + PieCtrlRegs + 0xce0 + + + + WdRegs + 0x7000 + + + + GpioDataRegs + 0x7f00 + + + + AnalogSubsysRegs + 0x5d700 + + + + GPIO_SetupPinMux + 0xc14f + + + + GPIO_EnableUnbondedIOPullupsFor176Pin + 0xcc8c + + + + GPIO_EnableUnbondedIOPullups + 0xcd1c + + + + GPIO_SetupPinOptions + 0xc24e + + + + InitGpio + 0xca8b + + + + InitPieCtrl + 0xcc35 + + + + InitPieVectTable + 0xcba2 + + + + PieVectTableInit + 0xb340 + + + + ComputeCntrSeedValue + 0xc800 + + + + VerifyXTAL + 0xc4f9 + + + + IsPLLValid + 0xc5b0 + + + + InitPeripheralClocks + 0xc665 + + + + SysIntOsc1Sel + 0x847e + + + + SysXtalOscSel + 0xcc12 + + + + SysXtalOscSESel + 0xccd6 + + + + AuxIntOsc2Sel + 0x856d + + + + InitSysCtrl + 0xca39 + + + + InitAuxPll + 0xc717 + + + + DisableDog + 0xcd0e + + + + AuxAuxClkSel + 0xce0b + + + + AuxXtalOscSESel + 0xccec + + + + AuxXtalOscSel + 0xccfd + + + + InitSysPll + 0xc33b + + + + SysIntOsc2Sel + 0x8575 + + + + F28x_usDelay + 0x1b1 + + + + main + 0xc91d + + + + I2CWrite + 0xc7c3 + + + + SSD1306_setPosition + 0xcbc8 + + + + I2C_TXdata + 0xac10 + + + + I2C_RXdata + 0xac00 + + + + SSD1306_GotoXY + 0x846a + + + + SSD1306_DrawPixel + 0xc9df + + + + I2CMaster_Init + 0xcbee + + + + SSD1306_Init + 0xc000 + + + + ssd1306_DrawBitmap + 0xc97e + + + + SSD1306_Fill + 0xc7f1 + + + + SSD1306_UpdateScreen + 0xcadc + + + + ceil + 0xc421 + + + + ceill + 0xc421 + + + + _c_int00 + 0xcca5 + + + + __stack + 0x400 + + + + __c28xabi_divf + 0xc895 + + + + __c28xabi_orll + 0xccc6 + + + + __c28xabi_xorll + 0xccce + + + + __c28xabi_andll + 0xccbe + + + + _system_pre_init + 0x859a + + + + __TI_auto_init_nobinit_nopinit + 0xcb4e + + + + __TI_zero_init + 0x8594 + + + + __TI_decompress_none + 0x857d + + + + __TI_decompress_lzss + 0xcb20 + + + + C$$EXIT + 0xcb79 + + + + abort + 0xcb79 + + + + exit + 0xcb7b + + + + __TI_dtors_ptr + 0xac28 + + + + __TI_cleanup_ptr + 0xac26 + + + + __TI_enable_exit_profile_output + 0xac24 + + + + _nop + 0x856c + + + + _lock + 0xac2a + + + + _unlock + 0xac2c + + + + _register_lock + 0x8568 + + + + _register_unlock + 0x8564 + + + + _args_main + 0xcd37 + + + + memset + 0x858d + + + + memcpy + 0xcc54 + + + + _system_post_cinit + 0xcfff + + + + __c_args__ + 0x0 + + + Link successful + diff --git a/i2c_ex1_master/CPU1_RAM/i2c_oled.d b/i2c_ex1_master/CPU1_RAM/i2c_oled.d new file mode 100644 index 0000000..40bbb55 --- /dev/null +++ b/i2c_ex1_master/CPU1_RAM/i2c_oled.d @@ -0,0 +1,249 @@ +# FIXED + +i2c_oled.obj: ../i2c_oled.c +i2c_oled.obj: ../i2c_oled.h +i2c_oled.obj: ../fonts.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/string.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_ti_config.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/linkage.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/cdefs.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/xlocale/_string.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f28x_project.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_cla_typedefs.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_device.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/assert.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdarg.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_types.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_types.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdbool.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stddef.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/stdint.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/_stdint40.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/stdint.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/machine/_stdint.h +i2c_oled.obj: C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include/sys/_stdint.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_adc.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_analogsubsys.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_bgcrc.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cla.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clb.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_clbxbar.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cmpss.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_cputimer.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dac.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dcsm.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_dma.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecap.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ecat_ss.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_emif.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwm.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_epwmxbar.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_eqep.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_erad.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_flash.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_fsi.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_gpio.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_hwbist.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_i2c.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_inputxbar.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_ipc.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_mcbsp.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_memconfig.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_nmiintrupt.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_outputxbar.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pbist.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_piectrl.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pievect.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_pmbus.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sci.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sdfm.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_spi.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_sysctrl.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_wwd.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_xbar.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_xint.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include/f2838x_can.h +i2c_oled.obj: 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C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_memctrl_defines.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_epwm_defines.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_adc_defines.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_emif_defines.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_gpio_defines.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_ipc_defines.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_pie_defines.h +i2c_oled.obj: C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include/f2838x_dma_defines.h +i2c_oled.obj: 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Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./f2838x_codestartbranch.obj" \ +"./f2838x_cputimers.obj" \ +"./f2838x_defaultisr.obj" \ +"./f2838x_dma.obj" \ +"./f2838x_epwm.obj" \ +"./f2838x_globalvariabledefs.obj" \ +"./f2838x_gpio.obj" \ +"./f2838x_piectrl.obj" \ +"./f2838x_pievect.obj" \ +"./f2838x_sysctrl.obj" \ +"./f2838x_usdelay.obj" \ +"./fonts.obj" \ +"./i2c_ex1_master.obj" \ +"./i2c_oled.obj" \ +"../2838x_RAM_lnk_cpu1.cmd" \ +"../f2838x_headers_nonBIOS_cpu1.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +i2c_ex1_master.out \ + +EXE_OUTPUTS__QUOTED += \ +"i2c_ex1_master.out" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "i2c_ex1_master.out" + +# Tool invocations +i2c_ex1_master.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: C2000 Linker' + "C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --idiv_support=idiv0 --tmu_support=tmu0 --vcu_support=vcrc -Ooff --advice:performance=all --define=DEBUG --define=CPU1 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi --cla_background_task=on -z -m"i2c_ex1_master.map" --stack_size=0x100 --warn_sections -i"C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/lib" -i"C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include" --reread_libs --diag_wrap=off --display_error_number --xml_link_info="i2c_ex1_master_linkInfo.xml" --entry_point=code_start --rom_model -o "i2c_ex1_master.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(EXE_OUTPUTS__QUOTED) + -$(RM) "f2838x_codestartbranch.obj" "f2838x_cputimers.obj" "f2838x_defaultisr.obj" "f2838x_dma.obj" "f2838x_epwm.obj" "f2838x_globalvariabledefs.obj" "f2838x_gpio.obj" "f2838x_piectrl.obj" "f2838x_pievect.obj" "f2838x_sysctrl.obj" "f2838x_usdelay.obj" "fonts.obj" "i2c_ex1_master.obj" "i2c_oled.obj" + -$(RM) "f2838x_cputimers.d" "f2838x_defaultisr.d" "f2838x_dma.d" "f2838x_epwm.d" "f2838x_globalvariabledefs.d" "f2838x_gpio.d" "f2838x_piectrl.d" "f2838x_pievect.d" "f2838x_sysctrl.d" "fonts.d" "i2c_ex1_master.d" "i2c_oled.d" + -$(RM) "f2838x_codestartbranch.d" "f2838x_usdelay.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/i2c_ex1_master/CPU1_RAM/objects.mk b/i2c_ex1_master/CPU1_RAM/objects.mk new file mode 100644 index 0000000..ad64ce9 --- /dev/null +++ b/i2c_ex1_master/CPU1_RAM/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/i2c_ex1_master/CPU1_RAM/sources.mk b/i2c_ex1_master/CPU1_RAM/sources.mk new file mode 100644 index 0000000..57d4267 --- /dev/null +++ b/i2c_ex1_master/CPU1_RAM/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/i2c_ex1_master/CPU1_RAM/subdir_rules.mk b/i2c_ex1_master/CPU1_RAM/subdir_rules.mk new file mode 100644 index 0000000..dccbebf --- /dev/null +++ b/i2c_ex1_master/CPU1_RAM/subdir_rules.mk @@ -0,0 +1,22 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: C2000 Compiler' + "C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --idiv_support=idiv0 --tmu_support=tmu0 --vcu_support=vcrc -Ooff --include_path="C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/i2c_ex1_master" --include_path="C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/common/include" --include_path="C:/Users/sedov/Desktop/Work/C2000Ware_5_00_00_00/device_support/f2838x/headers/include" --include_path="C:/ti/ccs1240/ccs/tools/compiler/ti-cgt-c2000_22.6.0.LTS/include" --advice:performance=all --define=DEBUG --define=CPU1 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi --cla_background_task=on --preproc_with_compile --preproc_dependency="$(basename $(>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot._asm in RTS library + + .endif + +;end wd_disable + + .end + +;// +;// End of file. +;// diff --git a/i2c_ex1_master/f2838x_cputimers.c b/i2c_ex1_master/f2838x_cputimers.c new file mode 100644 index 0000000..ed6db21 --- /dev/null +++ b/i2c_ex1_master/f2838x_cputimers.c @@ -0,0 +1,181 @@ +//########################################################################### +// +// FILE: f2838x_cputimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" +#include "f2838x_examples.h" + +// +// Globals +// +struct CPUTIMER_VARS CpuTimer0; +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +// +// InitCpuTimers - This function initializes all three CPU timers to a known +// state. +// +void InitCpuTimers(void) +{ + // + // CPU Timer 0 + // Initialize address pointers to respective timer registers: + // + CpuTimer0.RegsAddr = &CpuTimer0Regs; + + // + // Initialize timer period to maximum: + // + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + // + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + + // + // Make sure timer is stopped: + // + CpuTimer0Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value: + // + CpuTimer0Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters: + // + CpuTimer0.InterruptCount = 0; + + // + // Initialize address pointers to respective timer registers: + // + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + + // + // Initialize timer period to maximum: + // + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + // + CpuTimer1Regs.TPR.all = 0; + CpuTimer1Regs.TPRH.all = 0; + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + + // + // Make sure timers are stopped: + // + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value: + // + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters: + // + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; +} + +// +// ConfigCpuTimer - This function initializes the selected timer to the period +// specified by the "Freq" and "Period" parameters. The "Freq" +// is entered as "MHz" and the period in "uSeconds". The timer +// is held in the stopped state after configuration. +// +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // + // Initialize timer period: + // + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + + // + // Counter decrements PRD+1 times each period + // + Timer->RegsAddr->PRD.all = temp - 1; + + // + // Set pre-scale counter to divide by 1 (SYSCLKOUT): + // + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // + // Initialize timer control register: + // + Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart + // Timer + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 0; + Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled + Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer + // Interrupt + + // + // Reset interrupt counter: + // + Timer->InterruptCount = 0; +} + + +// +// End of file +// diff --git a/i2c_ex1_master/f2838x_defaultisr.c b/i2c_ex1_master/f2838x_defaultisr.c new file mode 100644 index 0000000..0a9c44f --- /dev/null +++ b/i2c_ex1_master/f2838x_defaultisr.c @@ -0,0 +1,4635 @@ +//########################################################################### +// +// FILE: f2838x_defaultisr.c +// +// TITLE: f2838x Device Default Interrupt Service Routines +// +//########################################################################### +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" // f2838x Header File Include File +#include "f2838x_examples.h" // f2838x Examples Include File + +// +// CPU Timer 1 Interrupt +// +interrupt void TIMER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// CPU Timer 2 Interrupt +// +interrupt void TIMER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Datalogging Interrupt +// +interrupt void DATALOG_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// RTOS Interrupt +// +interrupt void RTOS_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Emulation Interrupt +// +interrupt void EMU_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Non-Maskable Interrupt +// +interrupt void NMI_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Illegal Operation Trap +// +interrupt void ILLEGAL_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 1 +// +interrupt void USER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 2 +// +interrupt void USER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 3 +// +interrupt void USER3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 4 +// +interrupt void USER4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 5 +// +interrupt void USER5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 6 +// +interrupt void USER6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 7 +// +interrupt void USER7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 8 +// +interrupt void USER8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 9 +// +interrupt void USER9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 10 +// +interrupt void USER10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 11 +// +interrupt void USER11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 12 +// +interrupt void USER12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.1 - ADCA Interrupt 1 +// +interrupt void ADCA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.2 - ADCB Interrupt 1 +// +interrupt void ADCB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.3 - ADCC Interrupt 1 +// +interrupt void ADCC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.4 - XINT1 Interrupt +// +interrupt void XINT1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.5 - XINT2 Interrupt +// +interrupt void XINT2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.6 - ADCD Interrupt 1 +// +interrupt void ADCD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.7 - Timer 0 Interrupt +// +interrupt void TIMER0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.8 - Standby and Halt Wakeup Interrupt +// +interrupt void WAKE_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.1 - ePWM1 Trip Zone Interrupt +// +interrupt void EPWM1_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.2 - ePWM2 Trip Zone Interrupt +// +interrupt void EPWM2_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.3 - ePWM3 Trip Zone Interrupt +// +interrupt void EPWM3_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.4 - ePWM4 Trip Zone Interrupt +// +interrupt void EPWM4_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.5 - ePWM5 Trip Zone Interrupt +// +interrupt void EPWM5_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.6 - ePWM6 Trip Zone Interrupt +// +interrupt void EPWM6_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.7 - ePWM7 Trip Zone Interrupt +// +interrupt void EPWM7_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.8 - ePWM8 Trip Zone Interrupt +// +interrupt void EPWM8_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.1 - ePWM1 Interrupt +// +interrupt void EPWM1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.2 - ePWM2 Interrupt +// +interrupt void EPWM2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.3 - ePWM3 Interrupt +// +interrupt void EPWM3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.4 - ePWM4 Interrupt +// +interrupt void EPWM4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.5 - ePWM5 Interrupt +// +interrupt void EPWM5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.6 - ePWM6 Interrupt +// +interrupt void EPWM6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.7 - ePWM7 Interrupt +// +interrupt void EPWM7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.8 - ePWM8 Interrupt +// +interrupt void EPWM8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.1 - eCAP1 Interrupt +// +interrupt void ECAP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.2 - eCAP2 Interrupt +// +interrupt void ECAP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.3 - eCAP3 Interrupt +// +interrupt void ECAP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.4 - eCAP4 Interrupt +// +interrupt void ECAP4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.5 - eCAP5 Interrupt +// +interrupt void ECAP5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.6 - eCAP6 Interrupt +// +interrupt void ECAP6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.7 - eCAP7 Interrupt +// +interrupt void ECAP7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.1 - eQEP1 Interrupt +// +interrupt void EQEP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.2 - eQEP2 Interrupt +// +interrupt void EQEP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.3 - eQEP3 Interrupt +// +interrupt void EQEP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.5 - CLB1 (Reconfigurable Logic) Interrupt +// +interrupt void CLB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.6 - CLB2 (Reconfigurable Logic) Interrupt +// +interrupt void CLB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.7 - CLB3 (Reconfigurable Logic) Interrupt +// +interrupt void CLB3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.8 - CLB4 (Reconfigurable Logic) Interrupt +// +interrupt void CLB4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.1 - SPIA Receive Interrupt +// +interrupt void SPIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.2 - SPIA Transmit Interrupt +// +interrupt void SPIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.3 - SPIB Receive Interrupt +// +interrupt void SPIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.4 - SPIB Transmit Interrupt +// +interrupt void SPIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.5 - McBSPA Receive Interrupt +// +interrupt void MCBSPA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.6 - McBSPA Transmit Interrupt +// +interrupt void MCBSPA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.7 - McBSPB Receive Interrupt +// +interrupt void MCBSPB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.8 - McBSPB Transmit Interrupt +// +interrupt void MCBSPB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.1 - DMA Channel 1 Interrupt +// +interrupt void DMA_CH1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.2 - DMA Channel 2 Interrupt +// +interrupt void DMA_CH2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.3 - DMA Channel 3 Interrupt +// +interrupt void DMA_CH3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.4 - DMA Channel 4 Interrupt +// +interrupt void DMA_CH4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.5 - DMA Channel 5 Interrupt +// +interrupt void DMA_CH5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.6 - DMA Channel 6 Interrupt +// +interrupt void DMA_CH6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.1 - I2CA Interrupt 1 +// +interrupt void I2CA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.2 - I2CA Interrupt 2 +// +interrupt void I2CA_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.3 - I2CB Interrupt 1 +// +interrupt void I2CB_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.4 - I2CB Interrupt 2 +// +interrupt void I2CB_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.5 - SCIC Receive Interrupt +// +interrupt void SCIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.6 - SCIC Transmit Interrupt +// +interrupt void SCIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.7 - SCID Receive Interrupt +// +interrupt void SCID_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.8 - SCID Transmit Interrupt +// +interrupt void SCID_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.1 - SCIA Receive Interrupt +// +interrupt void SCIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.2 - SCIA Transmit Interrupt +// +interrupt void SCIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.3 - SCIB Receive Interrupt +// +interrupt void SCIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.4 - SCIB Transmit Interrupt +// +interrupt void SCIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.5 - CANA Interrupt 0 +// +interrupt void CANA0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.6 - CANA Interrupt 1 +// +interrupt void CANA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.7 - CANB Interrupt 0 +// +interrupt void CANB0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.8 - CANB Interrupt 1 +// +interrupt void CANB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.1 - ADCA Event Interrupt +// +interrupt void ADCA_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.2 - ADCA Interrupt 2 +// +interrupt void ADCA2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.3 - ADCA Interrupt 3 +// +interrupt void ADCA3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.4 - ADCA Interrupt 4 +// +interrupt void ADCA4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.5 - ADCB Event Interrupt +// +interrupt void ADCB_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.6 - ADCB Interrupt 2 +// +interrupt void ADCB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.7 - ADCB Interrupt 3 +// +interrupt void ADCB3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.8 - ADCB Interrupt 4 +// +interrupt void ADCB4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.1 - CLA1 Interrupt 1 +// +interrupt void CLA1_1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.2 - CLA1 Interrupt 2 +// +interrupt void CLA1_2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.3 - CLA1 Interrupt 3 +// +interrupt void CLA1_3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.4 - CLA1 Interrupt 4 +// +interrupt void CLA1_4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.5 - CLA1 Interrupt 5 +// +interrupt void CLA1_5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.6 - CLA1 Interrupt 6 +// +interrupt void CLA1_6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.7 - CLA1 Interrupt 7 +// +interrupt void CLA1_7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.8 - CLA1 Interrupt 8 +// +interrupt void CLA1_8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.1 - XINT3 Interrupt +// +interrupt void XINT3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.2 - XINT4 Interrupt +// +interrupt void XINT4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.3 - XINT5 Interrupt +// +interrupt void XINT5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.4 - MPOST Interrupt +// +interrupt void MPOST_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.5 - Flash Wrapper Operation Done Interrupt +// +interrupt void FMC_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.7 - FPU Overflow Interrupt +// +interrupt void FPU_OFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.8 - FPU Underflow Interrupt +// +interrupt void FPU_UFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.9 - I2CA Interrupt high priority +// +interrupt void I2CA_HIGH_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.10 - System error interrupt +// +interrupt void SYS_ERR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.11 - ETHERCAT SYNC0 interrupt +// +interrupt void ECATSYNC0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.12 - ETHERCAT main interrupt +// +interrupt void ECAT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.13 - C28x CPU IPC interrupt 1 +// +interrupt void CIPC0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.14 - C28x CPU IPC interrupt 2 +// +interrupt void CIPC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.15 - C28x CPU IPC interrupt 3 +// +interrupt void CIPC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.16 - C28x CPU IPC interrupt 4 +// +interrupt void CIPC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.9 - ePWM9 Trip Zone Interrupt +// +interrupt void EPWM9_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.10 - ePWM10 Trip Zone Interrupt +// +interrupt void EPWM10_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.11 - ePWM11 Trip Zone Interrupt +// +interrupt void EPWM11_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.12 - ePWM12 Trip Zone Interrupt +// +interrupt void EPWM12_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.13 - ePWM13 Trip Zone Interrupt +// +interrupt void EPWM13_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.14 - ePWM14 Trip Zone Interrupt +// +interrupt void EPWM14_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.15 - ePWM15 Trip Zone Interrupt +// +interrupt void EPWM15_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.16 - ePWM16 Trip Zone Interrupt +// +interrupt void EPWM16_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.9 - ePWM9 Interrupt +// +interrupt void EPWM9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.10 - ePWM10 Interrupt +// +interrupt void EPWM10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.11 - ePWM11 Interrupt +// +interrupt void EPWM11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.12 - ePWM12 Interrupt +// +interrupt void EPWM12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.13 - ePWM13 Interrupt +// +interrupt void EPWM13_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.14 - ePWM14 Interrupt +// +interrupt void EPWM14_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.15 - ePWM15 Interrupt +// +interrupt void EPWM15_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.16 - ePWM16 Interrupt +// +interrupt void EPWM16_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.9 - FSIA Transmit interrupt 1 +// +interrupt void FSITXA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.10 - FSIA Transmit interrupt 2 +// +interrupt void FSITXA2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.11 - FSIB Transmit interrupt 1 +// +interrupt void FSITXB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.12 - FSIB Transmit interrupt 2 +// +interrupt void FSITXB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.13 - FSIA Receive interrupt 1 +// +interrupt void FSIRXA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.14 - FSIA Receive interrupt 2 +// +interrupt void FSIRXA2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.15 - FSIB Receive interrupt 1 +// +interrupt void FSIRXB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.16 - FSIB Receive interrupt 2 +// +interrupt void FSIRXB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.9 - Sigma Delta Filter Module1 Interrupt +// +interrupt void SDFM1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.10 - Sigma Delta Filter Module2 Interrupt +// +interrupt void SDFM2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.11 - ETHERCAT Resetout Interrupt +// +interrupt void ECATRST_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.12 - ETHERCAT SYNC1 interrupt +// +interrupt void ECATSYNC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.13 - Sigma Delta Filter Module1 Filter 1 Interrupt +// +interrupt void SDFM1DR1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.14 - Sigma Delta Filter Module1 Filter 2 Interrupt +// +interrupt void SDFM1DR2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.15 - Sigma Delta Filter Module1 Filter 3 Interrupt +// +interrupt void SDFM1DR3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.16 - Sigma Delta Filter Module1 Filter 4 Interrupt +// +interrupt void SDFM1DR4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.9 - SPIC Receive Interrupt +// +interrupt void SPIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.10 - SPIC Transmit Interrupt +// +interrupt void SPIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.11 - SPID Receive Interrupt +// +interrupt void SPID_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.12 - SPID Transmit Interrupt +// +interrupt void SPID_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.13 - Sigma Delta Filter Module2 Filter 1 Interrupt +// +interrupt void SDFM2DR1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.14 - Sigma Delta Filter Module2 Filter 2 Interrupt +// +interrupt void SDFM2DR2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.15 - Sigma Delta Filter Module2 Filter 3 Interrupt +// +interrupt void SDFM2DR3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.16 - Sigma Delta Filter Module2 Filter 4 Interrupt +// +interrupt void SDFM2DR4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.9 - FSIC Receive interrupt 1 +// +interrupt void FSIRXC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.10 - FSIC Receive interrupt 2 +// +interrupt void FSIRXC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.11 - FSID Receive interrupt 1 +// +interrupt void FSIRXD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.12 - FSID Receive interrupt 2 +// +interrupt void FSIRXD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.13 - FSIE Receive interrupt 1 +// +interrupt void FSIRXE1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.14 - FSIE Receive interrupt 2 +// +interrupt void FSIRXE2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.15 - FSIF Receive interrupt 1 +// +interrupt void FSIRXF1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.16 - FSIF Receive interrupt 2 +// +interrupt void FSIRXF2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.9 - FSIG Receive interrupt 1 +// +interrupt void FSIRXG1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.10 - FSIG Receive interrupt 2 +// +interrupt void FSIRXG2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.11 - FSIH Receive interrupt 1 +// +interrupt void FSIRXH1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.12 - FSIH Receive interrupt 2 +// +interrupt void FSIRXH2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.13 - CLB5 Interrupt +// +interrupt void CLB5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.14 - CLB6 Interrupt +// +interrupt void CLB6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.15 - CLB7 Interrupt +// +interrupt void CLB7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.16 - CLB8 Interrupt +// +interrupt void CLB8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.9 - MCAN Sub-System Interrupt 0 +// +interrupt void MCANA_0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.10 - MCAN Sub-System Interrupt 1 +// +interrupt void MCANA_1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.11 - MCAN Sub-System ECC error Interrupt +// +interrupt void MCANA_ECC_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.12 - MCAN Sub-System wakeup Interrupt +// +interrupt void MCANA_WAKE_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.13 - PMBUSA Interrupt +// +interrupt void PMBUSA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.14 - CM Reset Status Interrupt +// +interrupt void CM_STATUS_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.15 - USBA Interrupt +// +interrupt void USBA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.9 - ADCC Event Interrupt +// +interrupt void ADCC_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.10 - ADCC Interrupt 2 +// +interrupt void ADCC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.11 - ADCC Interrupt 3 +// +interrupt void ADCC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.12 - ADCC Interrupt 4 +// +interrupt void ADCC4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.13 - ADCD Event Interrupt +// +interrupt void ADCD_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.14 - ADCD Interrupt 2 +// +interrupt void ADCD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.15 - ADCD Interrupt 3 +// +interrupt void ADCD3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.16 - ADCD Interrupt 4 +// +interrupt void ADCD4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.9 - CM to CPU IPC Interrupt 0 +// +interrupt void CMTOCPUXIPC0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.10 - CM to CPU IPC Interrupt 1 +// +interrupt void CMTOCPUXIPC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.11 - CM to CPU IPC Interrupt 2 +// +interrupt void CMTOCPUXIPC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.12 - CM to CPU IPC Interrupt 3 +// +interrupt void CMTOCPUXIPC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.13 - CM to CPU IPC Interrupt 4 +// +interrupt void CMTOCPUXIPC4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.14 - CM to CPU IPC Interrupt 5 +// +interrupt void CMTOCPUXIPC5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.15 - CM to CPU IPC Interrupt 6 +// +interrupt void CMTOCPUXIPC6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.16 - CM to CPU IPC Interrupt 7 +// +interrupt void CMTOCPUXIPC7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.10 - eCAP6 Interrupt 2 +// +interrupt void ECAP6_2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.11 - eCAP7 Interrupt 2 +// +interrupt void ECAP7_2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.13 - CPU BGCRC module interrupt +// +interrupt void CPUCRC_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.14 - CLA1 BGCRC module interrupt +// +interrupt void CLA1CRC_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.15 - CLA Overflow Interrupt +// +interrupt void CLA_OVERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.16 - CLA Underflow Interrupt +// +interrupt void CLA_UNDERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Catch-all Default ISRs: +// + +// +// PIE_RESERVED_ISR - Reserved ISR +// +interrupt void PIE_RESERVED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// EMPTY_ISR - Only does a return +// +interrupt void EMPTY_ISR(void) +{ + +} + +// +// NOTUSED_ISR - Unused ISR +// +interrupt void NOTUSED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// End of File +// + diff --git a/i2c_ex1_master/f2838x_dma.c b/i2c_ex1_master/f2838x_dma.c new file mode 100644 index 0000000..dc4a8dc --- /dev/null +++ b/i2c_ex1_master/f2838x_dma.c @@ -0,0 +1,1100 @@ +//########################################################################### +// +// FILE: f2838x_dma.c +// +// TITLE: F2838x Device DMA Initialization & Support Functions. +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" +#include "f2838x_examples.h" + +// +// DMAInitialize - This function initializes the DMA to a known state. +// +void DMAInitialize(void) +{ + EALLOW; + + // + // Perform a hard reset on DMA + // + DmaRegs.DMACTRL.bit.HARDRESET = 1; + __asm (" nop"); // one NOP required after HARDRESET + + // + // Allow DMA to run free on emulation suspend + // + DmaRegs.DEBUGCTRL.bit.FREE = 1; + + EDIS; +} + +// +// DMACH1AddrConfig - DMA Channel 1 Address Configuration +// +void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to + // beginning of + // source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to + // beginning of + // destination buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH1BurstConfig - DMA Channel 1 Burst size configuration +// +void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) + // x-ferred in a burst. + DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between + // each word x-ferred. + + EDIS; +} + +// +// DMACH1TransferConfig - DMA Channel 1 Transfer size configuration +// +void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored + // when WRAP occurs. + DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored + // when WRAP occurs. + + EDIS; +} + +// +// DMACH1WrapConfig - DMA Channel 1 Wrap size configuration +// +void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH1ModeConfig - DMA Channel 1 Mode configuration +// +void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel; + DmaRegs.CH1.MODE.bit.PERINTSEL = 1; + DmaRegs.CH1.MODE.bit.PERINTE = perinte; + DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH1.MODE.bit.DATASIZE = datasize; + DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH1.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: interrupt and sync error flags + // + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH1 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; + + EDIS; +} + +// +// StartDMACH1 - This function starts DMA Channel 1. +// +void StartDMACH1(void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH2AddrConfig - DMA Channel 2 Address Configuration +// +void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to + // beginning of + // source buffer. + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2BurstConfig - DMA Channel 2 Burst size configuration +// +void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration +// +void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH2WrapConfig - DMA Channel 2 Wrap size configuration +// +void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH2ModeConfig - DMA Channel 2 Mode configuration +// +void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel; + DmaRegs.CH2.MODE.bit.PERINTSEL = 2; + DmaRegs.CH2.MODE.bit.PERINTE = perinte; + DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH2.MODE.bit.DATASIZE = datasize; + DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH2.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH2 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; + + EDIS; +} + +// +// StartDMACH2 - This function starts DMA Channel 2. +// +void StartDMACH2(void) +{ + EALLOW; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH3AddrConfig - DMA Channel 3 Address configuration +// +void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3BurstConfig - DMA Channel 3 burst size configuration +// +void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH3TransferConfig - DMA channel 3 transfer size configuration +// +void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH3WrapConfig - DMA Channel 3 wrap size configuration +// +void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N + // bursts. + DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH3ModeConfig - DMA Channel 3 mode configuration +// +void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel; + DmaRegs.CH3.MODE.bit.PERINTSEL = 3; + DmaRegs.CH3.MODE.bit.PERINTE = perinte; + DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH3.MODE.bit.DATASIZE = datasize; + DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH3.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: interrupt flags and sync error flags + // + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH3 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx3 = 1; + + EDIS; +} + +// +// StartDMACH3 - This function starts DMA Channel 3. +// +void StartDMACH3(void) +{ + EALLOW; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH4AddrConfig - DMA Channel 4 address configuration +// +void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4BurstConfig - DMA Channel 4 burst size configuration +// +void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH4TransferConfig - DMA channel 4 transfer size configuration +// +void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH4WrapConfig - DMA channel 4 wrap size configuration +// +void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH4ModeConfig - DMA Channel 4 mode configuration +// +void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel; + DmaRegs.CH4.MODE.bit.PERINTSEL = 4; + DmaRegs.CH4.MODE.bit.PERINTE = perinte; + DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH4.MODE.bit.DATASIZE = datasize; + DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH4.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH4 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx4 = 1; + + EDIS; +} + +// +// StartDMACH4 - This function starts DMA Channel 4. +// +void StartDMACH4(void) +{ + EALLOW; + DmaRegs.CH4.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH5AddrConfig - DMA channel 5 address configuration +// +void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5BurstConfig - DMA Channel 5 burst size configuration +// +void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH5TransferConfig - DMA channel 5 transfer size configuration +// +void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH5WrapConfig - DMA Channel 5 wrap size configuration +// +void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH5ModeConfig - DMA Channel 5 mode configuration +// +void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel; + DmaRegs.CH5.MODE.bit.PERINTSEL = 5; + DmaRegs.CH5.MODE.bit.PERINTE = perinte; + DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH5.MODE.bit.DATASIZE = datasize; + DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH5.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH5 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx5 = 1; + + EDIS; +} + +// +// StartDMACH5 - This function starts DMA Channel 5. +// +void StartDMACH5(void) +{ + EALLOW; + DmaRegs.CH5.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH6AddrConfig - DMA Channel 6 address configuration +// +void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6BurstConfig - DMA Channel 6 burst size configuration +// +void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH6TransferConfig - DMA channel 6 transfer size configuration +// +void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH6WrapConfig - DMA Channel 6 wrap size configuration +// +void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N + // bursts. + DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH6ModeConfig - DMA Channel 6 mode configuration +// +void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel; + DmaRegs.CH6.MODE.bit.PERINTSEL = 6; + DmaRegs.CH6.MODE.bit.PERINTE = perinte; + DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH6.MODE.bit.DATASIZE = datasize; + DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH6.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH6 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx6 = 1; + + EDIS; +} + +// +// StartDMACH6 - This function starts DMA Channel 6. +// +void StartDMACH6(void) +{ + EALLOW; + DmaRegs.CH6.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// NOTE: +// Following functions are required for EMIF as the address is out of +// 22bit range +// + +// +// DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit +// +void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit +// +void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit +// +void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit +// +void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit +// +void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit +// +void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// End of file +// diff --git a/i2c_ex1_master/f2838x_epwm.c b/i2c_ex1_master/f2838x_epwm.c new file mode 100644 index 0000000..b1b422c --- /dev/null +++ b/i2c_ex1_master/f2838x_epwm.c @@ -0,0 +1,642 @@ +//########################################################################### +// +// FILE: f2838x_epwm.c +// +// TITLE: F2838x EPwm Initialization & Support Functions. +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" +#include "f2838x_examples.h" + +// +// InitEPwmGpio - Initialize all EPWM modules' GPIOs +// +void InitEPwmGpio(void) +{ + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + InitEPwm5Gpio(); + InitEPwm6Gpio(); + InitEPwm7Gpio(); + InitEPwm8Gpio(); + InitEPwm9Gpio(); + InitEPwm10Gpio(); + InitEPwm11Gpio(); + InitEPwm12Gpio(); + InitEPwm13Gpio(); + InitEPwm14Gpio(); + InitEPwm15Gpio(); + InitEPwm16Gpio(); +} + +// +// InitEPwm1Gpio - Initialize EPWM1 GPIOs +// +void InitEPwm1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B) +// GpioCtrlRegs.GPEPUD.bit.GPIO145 = 1; // Disable pull-up on GPIO145 (EPWM1A) +// GpioCtrlRegs.GPEPUD.bit.GPIO146 = 1; // Disable pull-up on GPIO146 (EPWM1B) + + // + // Configure EPWM-1 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM1 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B +// GpioCtrlRegs.GPEMUX2.bit.GPIO145 = 1; // Configure GPIO145 as EPWM1A +// GpioCtrlRegs.GPEMUX2.bit.GPIO146 = 1; // Configure GPIO0146 as EPWM1B + + EDIS; +} + +// +// InitEPwm2Gpio - Initialize EPWM2 GPIOs +// +void InitEPwm2Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B) +// GpioCtrlRegs.GPEPUD.bit.GPIO147 = 1; // Disable pull-up on GPIO147 (EPWM2A) +// GpioCtrlRegs.GPEPUD.bit.GPIO148 = 1; // Disable pull-up on GPIO148 (EPWM2B) + + // + // Configure EPwm-2 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM2 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B +// GpioCtrlRegs.GPEMUX2.bit.GPIO147 = 1; // Configure GPIO147 as EPWM2A +// GpioCtrlRegs.GPEMUX2.bit.GPIO148 = 1; // Configure GPIO148 as EPWM2B + + EDIS; +} + +// +// InitEPwm3Gpio - Initialize EPWM3 GPIOs +// +void InitEPwm3Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B) +// GpioCtrlRegs.GPEPUD.bit.GPIO149 = 1; // Disable pull-up on GPIO149 (EPWM3A) +// GpioCtrlRegs.GPEPUD.bit.GPIO150 = 1; // Disable pull-up on GPIO150 (EPWM3B) + + // + // Configure EPwm-3 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM3 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B +// GpioCtrlRegs.GPEMUX2.bit.GPIO149 = 1; // Configure GPIO149 as EPWM3A +// GpioCtrlRegs.GPEMUX2.bit.GPIO150 = 1; // Configure GPIO150 as EPWM3B + + EDIS; +} + +// +// InitEPwm4Gpio - Initialize EPWM4 GPIOs +// +void InitEPwm4Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B) +// GpioCtrlRegs.GPEPUD.bit.GPIO151 = 1; // Disable pull-up on GPIO151 (EPWM4A) +// GpioCtrlRegs.GPEPUD.bit.GPIO152 = 1; // Disable pull-up on GPIO152 (EPWM4B) + + // + // Configure EPWM-4 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM4 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B +// GpioCtrlRegs.GPEMUX2.bit.GPIO151 = 1; // Configure GPIO151 as EPWM4A +// GpioCtrlRegs.GPEMUX2.bit.GPIO152 = 1; // Configure GPIO152 as EPWM4B + + EDIS; +} + +// +// InitEPwm5Gpio - Initialize EPWM5 GPIOs +// +void InitEPwm5Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A) + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EPWM5B) +// GpioCtrlRegs.GPEPUD.bit.GPIO153 = 1; // Disable pull-up on GPIO153 (EPWM5A) +// GpioCtrlRegs.GPEPUD.bit.GPIO154 = 1; // Disable pull-up on GPIO154 (EPWM5B) + + // + // Configure EPWM-5 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM5 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B +// GpioCtrlRegs.GPEMUX2.bit.GPIO153 = 1; // Configure GPIO153 as EPWM5A +// GpioCtrlRegs.GPEMUX2.bit.GPIO154 = 1; // Configure GPIO0154 as EPWM5B + + EDIS; +} + +// +// InitEPwm6Gpio - Initialize EPWM6 GPIOs +// +void InitEPwm6Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EPWM6B) +// GpioCtrlRegs.GPEPUD.bit.GPIO155 = 1; // Disable pull-up on GPIO155 (EPWM6A) +// GpioCtrlRegs.GPEPUD.bit.GPIO156 = 1; // Disable pull-up on GPIO156 (EPWM6B) + + // + // Configure EPWM-6 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM6 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B +// GpioCtrlRegs.GPEMUX2.bit.GPIO155 = 1; // Configure GPIO155 as EPWM6A +// GpioCtrlRegs.GPEMUX2.bit.GPIO156 = 1; // Configure GPIO156 as EPWM6B + + EDIS; +} + +// +// InitEPwm7Gpio - Initialize EPWM7 GPIOs +// +void InitEPwm7Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EPWM7A) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EPWM7B) +// GpioCtrlRegs.GPEPUD.bit.GPIO157 = 1; // Disable pull-up on GPIO157 (EPWM7A) +// GpioCtrlRegs.GPEPUD.bit.GPIO158 = 1; // Disable pull-up on GPIO158 (EPWM7B) + + // + // Configure EPWM-7 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM7 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EPWM7A + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EPWM7B +// GpioCtrlRegs.GPEMUX2.bit.GPIO157 = 1; // Configure GPIO157 as EPWM7A +// GpioCtrlRegs.GPEMUX2.bit.GPIO158 = 1; // Configure GPIO158 as EPWM7B + + EDIS; +} + +// +// InitEPwm8Gpio - Initialize EPWM8 GPIOs +// +void InitEPwm8Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (EPWM8A) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (EPWM8B) +// GpioCtrlRegs.GPEPUD.bit.GPIO159 = 1; // Disable pull-up on GPIO159 (EPWM8A) +// GpioCtrlRegs.GPFPUD.bit.GPIO160 = 1; // Disable pull-up on GPIO160 (EPWM8B) + + // + // Configure EPWM-8 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM8 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as EPWM8A + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as EPWM8B +// GpioCtrlRegs.GPEMUX2.bit.GPIO159 = 1; // Configure GPIO159 as EPWM8A +// GpioCtrlRegs.GPFMUX1.bit.GPIO160 = 1; // Configure GPIO160 as EPWM8B + + EDIS; +} + +// +// InitEPwm9Gpio - Initialize EPWM9 GPIOs +// +void InitEPwm9Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO161 = 1; // Disable pull-up on GPIO161 (EPWM9A) + GpioCtrlRegs.GPFPUD.bit.GPIO162 = 1; // Disable pull-up on GPIO162 (EPWM9B) +// GpioCtrlRegs.GPAPUD.bit.GPIO16 = 1; // Disable pull-up on GPIO16 (EPWM9A) +// GpioCtrlRegs.GPAPUD.bit.GPIO17 = 1; // Disable pull-up on GPIO17 (EPWM9B) + + // + // Configure EPWM-9 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM9 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO161 = 1; // Configure GPIO161 as EPWM9A + GpioCtrlRegs.GPFMUX1.bit.GPIO162 = 1; // Configure GPIO162 as EPWM9B + +// // +// // Alternate mapping for EPWM-9. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // Configure GPAMUX to 0 for GPIO16 +// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0; // Configure GPAMUX to 0 for GPIO17 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO16 = 1; // Configure GPAGMUX for EPWM9A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO17 = 1; // Configure GPAGMUX for EPWM9B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPAMUX for EPWM9A +// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPAMUX for EPWM9B + + EDIS; +} + +// +// InitEPwm10Gpio - Initialize EPWM10 GPIOs +// +void InitEPwm10Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO163 = 1; // Disable pull-up on GPIO163 (EPWM10A) + GpioCtrlRegs.GPFPUD.bit.GPIO164 = 1; // Disable pull-up on GPIO164 (EPWM10B) +// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO18 (EPWM10A) +// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 1; // Disable pull-up on GPIO19 (EPWM10B) + + // + // Configure EPWM-10 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM10 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO163 = 1; // Configure GPIO163 as EPWM10A + GpioCtrlRegs.GPFMUX1.bit.GPIO164 = 1; // Configure GPIO164 as EPWM10B + +// // +// // Alternate mapping for EPWM-10. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; // Configure GPAMUX to 0 for GPIO18 +// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // Configure GPAMUX to 0 for GPIO19 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 1; // Configure GPAGMUX for EPWM10A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 1; // Configure GPAGMUX for EPWM10B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPAMUX for EPWM10A +// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPAMUX for EPWM10B + + EDIS; +} + +// +// InitEPwm11Gpio - Initialize EPWM11 GPIOs +// +void InitEPwm11Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO165 = 1; // Disable pull-up on GPIO165 (EPWM11A) + GpioCtrlRegs.GPFPUD.bit.GPIO166 = 1; // Disable pull-up on GPIO166 (EPWM11B) +// GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (EPWM11A) +// GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (EPWM11B) + + // + // Configure EPWM-11 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM11 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO165 = 1; // Configure GPIO165 as EPWM11A + GpioCtrlRegs.GPFMUX1.bit.GPIO166 = 1; // Configure GPIO166 as EPWM11B + +// // +// // Alternate mapping for EPWM-11. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0; // Configure GPAMUX to 0 for GPIO20 +// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0; // Configure GPAMUX to 0 for GPIO21 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 1; // Configure GPAGMUX for EPWM11A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 1; // Configure GPAGMUX for EPWM11B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPAMUX for EPWM11A +// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPAMUX for EPWM11B + + EDIS; +} + +// +// InitEPwm12Gpio - Initialize EPWM12 GPIOs +// +void InitEPwm12Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO167 = 1; // Disable pull-up on GPIO167 (EPWM12A) + GpioCtrlRegs.GPFPUD.bit.GPIO168 = 1; // Disable pull-up on GPIO168 (EPWM12B) +// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; // Disable pull-up on GPIO22 (EPWM12A) +// GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; // Disable pull-up on GPIO23 (EPWM12B) + + // + // Configure EPWM-12 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM12 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO167 = 1; // Configure GPIO167 as EPWM12A + GpioCtrlRegs.GPFMUX1.bit.GPIO168 = 1; // Configure GPIO168 as EPWM12B + +// // +// // Alternate mapping for EPWM-12. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; // Configure GPAMUX to 0 for GPIO22 +// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0; // Configure GPAMUX to 0 for GPIO23 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO22 = 1; // Configure GPAGMUX for EPWM12A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO23 = 1; // Configure GPAGMUX for EPWM12B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPAMUX for EPWM12A +// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPAMUX for EPWM12B + + EDIS; +} + +// +// InitEPwm13Gpio - Initialize EPWM13 GPIOs +// +void InitEPwm13Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEPUD.bit.GPIO137 = 1; // Disable pull-up on GPIO137 (EPWM13A) + GpioCtrlRegs.GPEPUD.bit.GPIO138 = 1; // Disable pull-up on GPIO138 (EPWM13B) +// GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EPWM13A) +// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EPWM13B) + + // + // Configure EPWM-13 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM13 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEMUX1.bit.GPIO137 = 1; // Configure GPIO137 as EPWM13A + GpioCtrlRegs.GPEMUX1.bit.GPIO138 = 1; // Configure GPIO138 as EPWM13B + +// // +// // Alternate mapping for EPWM-13. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 0; // Configure GPAMUX to 0 for GPIO24 +// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // Configure GPAMUX to 0 for GPIO25 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO24 = 3; // Configure GPAGMUX for EPWM13A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO25 = 3; // Configure GPAGMUX for EPWM13B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPAMUX for EPWM13A +// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPAMUX for EPWM13B + + EDIS; +} + +// +// InitEPwm14Gpio - Initialize EPWM14 GPIOs +// +void InitEPwm14Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEPUD.bit.GPIO139 = 1; // Disable pull-up on GPIO139 (EPWM14A) + GpioCtrlRegs.GPEPUD.bit.GPIO140 = 1; // Disable pull-up on GPIO140 (EPWM14B) +// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EPWM14A) +// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EPWM14B) + + // + // Configure EPWM-14 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM14 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEMUX1.bit.GPIO139 = 1; // Configure GPIO139 as EPWM14A + GpioCtrlRegs.GPEMUX1.bit.GPIO140 = 1; // Configure GPIO140 as EPWM14B + +// // +// // Alternate mapping for EPWM-14. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // Configure GPAMUX to 0 for GPIO26 +// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // Configure GPAMUX to 0 for GPIO27 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO26 = 3; // Configure GPAGMUX for EPWM14A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO27 = 3; // Configure GPAGMUX for EPWM14B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPAMUX for EPWM14A +// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPAMUX for EPWM14B + + EDIS; +} + +// +// InitEPwm15Gpio - Initialize EPWM15 GPIOs +// +void InitEPwm15Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEPUD.bit.GPIO141 = 1; // Disable pull-up on GPIO141 (EPWM15A) + GpioCtrlRegs.GPEPUD.bit.GPIO142 = 1; // Disable pull-up on GPIO142 (EPWM15B) +// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up on GPIO28 (EPWM15A) +// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1; // Disable pull-up on GPIO29 (EPWM15B) + + // + // Configure EPWM-15 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM15 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEMUX1.bit.GPIO141 = 1; // Configure GPIO141 as EPWM15A + GpioCtrlRegs.GPEMUX1.bit.GPIO142 = 1; // Configure GPIO142 as EPWM15B + +// // +// // Alternate mapping for EPWM-15. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 0; // Configure GPAMUX to 0 for GPIO28 +// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 0; // Configure GPAMUX to 0 for GPIO29 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 3; // Configure GPAGMUX for EPWM15A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 3; // Configure GPAGMUX for EPWM15B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPAMUX for EPWM15A +// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPAMUX for EPWM15B + + EDIS; +} + +// +// InitEPwm16Gpio - Initialize EPWM16 GPIOs +// +void InitEPwm16Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins for reduced + // power consumption. Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEPUD.bit.GPIO143 = 1; // Disable pull-up on GPIO141 (EPWM16A) + GpioCtrlRegs.GPEPUD.bit.GPIO144 = 1; // Disable pull-up on GPIO142 (EPWM16B) +// GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Disable pull-up on GPIO28 (EPWM16A) +// GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Disable pull-up on GPIO29 (EPWM16B) + + // + // Configure EPWM-16 pins using GPIO regs. This specifies which of the + // possible GPIO pins will be EPWM16 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPEMUX1.bit.GPIO143 = 1; // Configure GPIO141 as EPWM16A + GpioCtrlRegs.GPEMUX2.bit.GPIO144 = 1; // Configure GPIO142 as EPWM16B + +// // +// // Alternate mapping for EPWM-16. Uncomment if required. Write 0 to +// // GPAMUx register before configuring GPAGMux to avoid glitches in Mux. +// // +// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0; // Configure GPAMUX to 0 for GPIO30 +// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0; // Configure GPAMUX to 0 for GPIO31 +// +// GpioCtrlRegs.GPAGMUX2.bit.GPIO30 = 3; // Configure GPAGMUx for EPWM16A +// GpioCtrlRegs.GPAGMUX2.bit.GPIO31 = 3; // Configure GPAGMux for EPWM16B +// +// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPAMUx for EPWM16A +// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPAMux for EPWM16B + + EDIS; +} + +// +// End of File +// diff --git a/i2c_ex1_master/f2838x_globalvariabledefs.c b/i2c_ex1_master/f2838x_globalvariabledefs.c new file mode 100644 index 0000000..db5a2a5 --- /dev/null +++ b/i2c_ex1_master/f2838x_globalvariabledefs.c @@ -0,0 +1,1561 @@ +//########################################################################### +// +// FILE: f2838x_globalvariabledefs.c +// +// TITLE: f2838x Global Variables and Data Section Pragmas. +// +//########################################################################### +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "f2838x_device.h" // f2838x Headerfile Include File + +//--------------------------------------------------------------------------- +// Define Global Peripheral Variables: +// + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AccessProtectionRegsFile") +#else +#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile"); +#endif +volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaRegsFile") +#else +#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile"); +#endif +volatile struct ADC_REGS AdcaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbRegsFile") +#else +#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile"); +#endif +volatile struct ADC_REGS AdcbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdccRegsFile") +#else +#pragma DATA_SECTION(AdccRegs,"AdccRegsFile"); +#endif +volatile struct ADC_REGS AdccRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdRegsFile") +#else +#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile"); +#endif +volatile struct ADC_REGS AdcdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaResultRegsFile") +#else +#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultRegsFile"); +#endif +volatile struct ADC_RESULT_REGS AdcaResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbResultRegsFile") +#else +#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultRegsFile"); +#endif +volatile struct ADC_RESULT_REGS AdcbResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdccResultRegsFile") +#else +#pragma DATA_SECTION(AdccResultRegs,"AdccResultRegsFile"); +#endif +volatile struct ADC_RESULT_REGS AdccResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdResultRegsFile") +#else +#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultRegsFile"); +#endif +volatile struct ADC_RESULT_REGS AdcdResultRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AnalogSubsysRegsFile") +#else +#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile"); +#endif +volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("BgcrcCpuRegsFile") +#else +#pragma DATA_SECTION(BgcrcCpuRegs,"BgcrcCpuRegsFile"); +#endif +volatile struct BGCRC_REGS BgcrcCpuRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("BgcrcCla1RegsFile") +#else +#pragma DATA_SECTION(BgcrcCla1Regs,"BgcrcCla1RegsFile"); +#endif +volatile struct BGCRC_REGS BgcrcCla1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanaRegsFile") +#else +#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); +#endif +volatile struct CAN_REGS CanaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanbRegsFile") +#else +#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); +#endif +volatile struct CAN_REGS CanbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cla1RegsFile") +#else +#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); +#endif +volatile struct CLA_REGS Cla1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb1DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb1DataExchRegs,"Clb1DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb1DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb2DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb2DataExchRegs,"Clb2DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb2DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb3DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb3DataExchRegs,"Clb3DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb3DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb4DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb4DataExchRegs,"Clb4DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb4DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb5DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb5DataExchRegs,"Clb5DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb5DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb6DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb6DataExchRegs,"Clb6DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb6DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb7DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb7DataExchRegs,"Clb7DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb7DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb8DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb8DataExchRegs,"Clb8DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb8DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb1LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb1LogicCfgRegs,"Clb1LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb1LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb2LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb2LogicCfgRegs,"Clb2LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb2LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb3LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb3LogicCfgRegs,"Clb3LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb3LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb4LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb4LogicCfgRegs,"Clb4LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb4LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb5LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb5LogicCfgRegs,"Clb5LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb5LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb6LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb6LogicCfgRegs,"Clb6LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb6LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb7LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb7LogicCfgRegs,"Clb7LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb7LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb8LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb8LogicCfgRegs,"Clb8LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb8LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb1LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb1LogicCtrlRegs,"Clb1LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb1LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb2LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb2LogicCtrlRegs,"Clb2LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb2LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb3LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb3LogicCtrlRegs,"Clb3LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb3LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb4LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb4LogicCtrlRegs,"Clb4LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb4LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb5LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb5LogicCtrlRegs,"Clb5LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb5LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb6LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb6LogicCtrlRegs,"Clb6LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb6LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb7LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb7LogicCtrlRegs,"Clb7LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb7LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb8LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb8LogicCtrlRegs,"Clb8LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb8LogicCtrlRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CLBXbarRegsFile") +#else +#pragma DATA_SECTION(CLBXbarRegs,"CLBXbarRegsFile"); +#endif +volatile struct CLB_XBAR_REGS CLBXbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClkCfgRegsFile") +#else +#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); +#endif +volatile struct CLK_CFG_REGS ClkCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss1RegsFile") +#else +#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss2RegsFile") +#else +#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss3RegsFile") +#else +#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss4RegsFile") +#else +#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss5RegsFile") +#else +#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss6RegsFile") +#else +#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss7RegsFile") +#else +#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss8RegsFile") +#else +#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss8Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CmConfRegsFile") +#else +#pragma DATA_SECTION(CmConfRegs,"CmConfRegsFile"); +#endif +volatile struct CM_CONF_REGS CmConfRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cpu1toCmIpcRegsFile") +#else +#pragma DATA_SECTION(Cpu1toCmIpcRegs,"Cpu1toCmIpcRegsFile"); +#endif +volatile struct CPU1TOCM_IPC_REGS_CPU1VIEW Cpu1toCmIpcRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cpu1toCpu2IpcRegsFile") +#else +#pragma DATA_SECTION(Cpu1toCpu2IpcRegs,"Cpu1toCpu2IpcRegsFile"); +#endif +volatile struct CPU1TOCPU2_IPC_REGS_CPU1VIEW Cpu1toCpu2IpcRegs; +#endif // ifdef CPU1 + +#ifdef CPU2 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cpu2toCpu1IpcRegsFile") +#else +#pragma DATA_SECTION(Cpu2toCpu1IpcRegs,"Cpu2toCpu1IpcRegsFile"); +#endif +volatile struct CPU1TOCPU2_IPC_REGS_CPU2VIEW Cpu2toCpu1IpcRegs; +#endif // ifdef CPU2 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SysPeriphAcRegsFile") +#else +#pragma DATA_SECTION(SysPeriphAcRegs,"SysPeriphAcRegsFile"); +#endif +volatile struct CPU1_PERIPH_AC_REGS SysPeriphAcRegs; +#endif // ifdef CPU1 + +#ifdef CPU2 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cpu2toCmIpcRegsFile") +#else +#pragma DATA_SECTION(Cpu2toCmIpcRegs,"Cpu2toCmIpcRegsFile"); +#endif +volatile struct CPU2TOCM_IPC_REGS_CPU2VIEW Cpu2toCmIpcRegs; +#endif // ifdef CPU2 + +#ifdef CPU2 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SysPeriphAcRegsFile") +#else +#pragma DATA_SECTION(SysPeriphAcRegs,"SysPeriphAcRegsFile"); +#endif +volatile struct CPU2_PERIPH_AC_REGS SysPeriphAcRegs; +#endif // ifdef CPU2 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuSysRegsFile") +#else +#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); +#endif +volatile struct CPU_SYS_REGS CpuSysRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacaRegsFile") +#else +#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); +#endif +volatile struct DAC_REGS DacaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacbRegsFile") +#else +#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); +#endif +volatile struct DAC_REGS DacbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DaccRegsFile") +#else +#pragma DATA_SECTION(DaccRegs,"DaccRegsFile"); +#endif +volatile struct DAC_REGS DaccRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Dcc0RegsFile") +#else +#pragma DATA_SECTION(Dcc0Regs,"Dcc0RegsFile"); +#endif +volatile struct DCC_REGS Dcc0Regs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Dcc1RegsFile") +#else +#pragma DATA_SECTION(Dcc1Regs,"Dcc1RegsFile"); +#endif +volatile struct DCC_REGS Dcc1Regs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Dcc2RegsFile") +#else +#pragma DATA_SECTION(Dcc2Regs,"Dcc2RegsFile"); +#endif +volatile struct DCC_REGS Dcc2Regs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmCommonRegsFile") +#else +#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); +#endif +volatile struct DCSM_COMMON_REGS DcsmCommonRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ1OtpRegsFile") +#else +#pragma DATA_SECTION(DcsmZ1OtpRegs,"DcsmZ1OtpRegsFile"); +#endif +volatile struct DCSM_Z1_OTP DcsmZ1OtpRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ1RegsFile") +#else +#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile"); +#endif +volatile struct DCSM_Z1_REGS DcsmZ1Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ2OtpRegsFile") +#else +#pragma DATA_SECTION(DcsmZ2OtpRegs,"DcsmZ2OtpRegsFile"); +#endif +volatile struct DCSM_Z2_OTP DcsmZ2OtpRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ2RegsFile") +#else +#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile"); +#endif +volatile struct DCSM_Z2_REGS DcsmZ2Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DevCfgRegsFile") +#else +#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); +#endif +volatile struct DEV_CFG_REGS DevCfgRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaClaSrcSelRegsFile") +#else +#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); +#endif +volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap7RegsFile") +#else +#pragma DATA_SECTION(ECap7Regs,"ECap7RegsFile"); +#endif +volatile struct ECAP_REGS ECap7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile"); +#endif +volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile"); +#endif +volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1RegsFile") +#else +#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile"); +#endif +volatile struct EMIF_REGS Emif1Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2RegsFile") +#else +#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile"); +#endif +volatile struct EMIF_REGS Emif2Regs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm7RegsFile") +#else +#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); +#endif +volatile struct EPWM_REGS EPwm7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm8RegsFile") +#else +#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); +#endif +volatile struct EPWM_REGS EPwm8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm9RegsFile") +#else +#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile"); +#endif +volatile struct EPWM_REGS EPwm9Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm10RegsFile") +#else +#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile"); +#endif +volatile struct EPWM_REGS EPwm10Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm11RegsFile") +#else +#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile"); +#endif +volatile struct EPWM_REGS EPwm11Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm12RegsFile") +#else +#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile"); +#endif +volatile struct EPWM_REGS EPwm12Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm13RegsFile") +#else +#pragma DATA_SECTION(EPwm13Regs,"EPwm13RegsFile"); +#endif +volatile struct EPWM_REGS EPwm13Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm14RegsFile") +#else +#pragma DATA_SECTION(EPwm14Regs,"EPwm14RegsFile"); +#endif +volatile struct EPWM_REGS EPwm14Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm15RegsFile") +#else +#pragma DATA_SECTION(EPwm15Regs,"EPwm15RegsFile"); +#endif +volatile struct EPWM_REGS EPwm15Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm16RegsFile") +#else +#pragma DATA_SECTION(EPwm16Regs,"EPwm16RegsFile"); +#endif +volatile struct EPWM_REGS EPwm16Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwmXbarRegsFile") +#else +#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); +#endif +volatile struct EPWM_XBAR_REGS EPwmXbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep3RegsFile") +#else +#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile"); +#endif +volatile struct EQEP_REGS EQep3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCounter1RegsFile") +#else +#pragma DATA_SECTION(EradCounter1Regs,"EradCounter1RegsFile"); +#endif +volatile struct ERAD_COUNTER_REGS EradCounter1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCounter2RegsFile") +#else +#pragma DATA_SECTION(EradCounter2Regs,"EradCounter2RegsFile"); +#endif +volatile struct ERAD_COUNTER_REGS EradCounter2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCounter3RegsFile") +#else +#pragma DATA_SECTION(EradCounter3Regs,"EradCounter3RegsFile"); +#endif +volatile struct ERAD_COUNTER_REGS EradCounter3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCounter4RegsFile") +#else +#pragma DATA_SECTION(EradCounter4Regs,"EradCounter4RegsFile"); +#endif +volatile struct ERAD_COUNTER_REGS EradCounter4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRCGlobalRegsFile") +#else +#pragma DATA_SECTION(EradCRCGlobalRegs,"EradCRCGlobalRegsFile"); +#endif +volatile struct ERAD_CRC_GLOBAL_REGS EradCRCGlobalRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC1RegsFile") +#else +#pragma DATA_SECTION(EradCRC1Regs,"EradCRC1RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC2RegsFile") +#else +#pragma DATA_SECTION(EradCRC2Regs,"EradCRC2RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC3RegsFile") +#else +#pragma DATA_SECTION(EradCRC3Regs,"EradCRC3RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC4RegsFile") +#else +#pragma DATA_SECTION(EradCRC4Regs,"EradCRC4RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC5RegsFile") +#else +#pragma DATA_SECTION(EradCRC5Regs,"EradCRC5RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC6RegsFile") +#else +#pragma DATA_SECTION(EradCRC6Regs,"EradCRC6RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC7RegsFile") +#else +#pragma DATA_SECTION(EradCRC7Regs,"EradCRC7RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradCRC8RegsFile") +#else +#pragma DATA_SECTION(EradCRC8Regs,"EradCRC8RegsFile"); +#endif +volatile struct ERAD_CRC_REGS EradCRC8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradGlobalRegsFile") +#else +#pragma DATA_SECTION(EradGlobalRegs,"EradGlobalRegsFile"); +#endif +volatile struct ERAD_GLOBAL_REGS EradGlobalRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP1RegsFile") +#else +#pragma DATA_SECTION(EradHWBP1Regs,"EradHWBP1RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP2RegsFile") +#else +#pragma DATA_SECTION(EradHWBP2Regs,"EradHWBP2RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP3RegsFile") +#else +#pragma DATA_SECTION(EradHWBP3Regs,"EradHWBP3RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP4RegsFile") +#else +#pragma DATA_SECTION(EradHWBP4Regs,"EradHWBP4RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP5RegsFile") +#else +#pragma DATA_SECTION(EradHWBP5Regs,"EradHWBP5RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP6RegsFile") +#else +#pragma DATA_SECTION(EradHWBP6Regs,"EradHWBP6RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP7RegsFile") +#else +#pragma DATA_SECTION(EradHWBP7Regs,"EradHWBP7RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EradHWBP8RegsFile") +#else +#pragma DATA_SECTION(EradHWBP8Regs,"EradHWBP8RegsFile"); +#endif +volatile struct ERAD_HWBP_REGS EradHWBP8Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EscssConfigRegsFile") +#else +#pragma DATA_SECTION(EscssConfigRegs,"EscssConfigRegsFile"); +#endif +volatile struct ESCSS_CONFIG_REGS EscssConfigRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EscssRegsFile") +#else +#pragma DATA_SECTION(EscssRegs,"EscssRegsFile"); +#endif +volatile struct ESCSS_REGS EscssRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0CtrlRegsFile") +#else +#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); +#endif +volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0EccRegsFile") +#else +#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); +#endif +volatile struct FLASH_ECC_REGS Flash0EccRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxaRegsFile") +#else +#pragma DATA_SECTION(FsiRxaRegs,"FsiRxaRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxbRegsFile") +#else +#pragma DATA_SECTION(FsiRxbRegs,"FsiRxbRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxcRegsFile") +#else +#pragma DATA_SECTION(FsiRxcRegs,"FsiRxcRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxcRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxdRegsFile") +#else +#pragma DATA_SECTION(FsiRxdRegs,"FsiRxdRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxeRegsFile") +#else +#pragma DATA_SECTION(FsiRxeRegs,"FsiRxeRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxeRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxfRegsFile") +#else +#pragma DATA_SECTION(FsiRxfRegs,"FsiRxfRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxfRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxgRegsFile") +#else +#pragma DATA_SECTION(FsiRxgRegs,"FsiRxgRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiRxhRegsFile") +#else +#pragma DATA_SECTION(FsiRxhRegs,"FsiRxhRegsFile"); +#endif +volatile struct FSI_RX_REGS FsiRxhRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiTxaRegsFile") +#else +#pragma DATA_SECTION(FsiTxaRegs,"FsiTxaRegsFile"); +#endif +volatile struct FSI_TX_REGS FsiTxaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FsiTxbRegsFile") +#else +#pragma DATA_SECTION(FsiTxbRegs,"FsiTxbRegsFile"); +#endif +volatile struct FSI_TX_REGS FsiTxbRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataReadRegsFile") +#else +#pragma DATA_SECTION(GpioDataReadRegs,"GpioDataReadRegsFile"); +#endif +volatile struct GPIO_DATA_READ_REGS GpioDataReadRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("HRCap6RegsFile") +#else +#pragma DATA_SECTION(HRCap6Regs,"HRCap6RegsFile"); +#endif +volatile struct HRCAP_REGS HRCap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("HRCap7RegsFile") +#else +#pragma DATA_SECTION(HRCap7Regs,"HRCap7RegsFile"); +#endif +volatile struct HRCAP_REGS HRCap7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2cbRegsFile") +#else +#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile"); +#endif +volatile struct I2C_REGS I2cbRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("InputXbarRegsFile") +#else +#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); +#endif +volatile struct INPUT_XBAR_REGS InputXbarRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClbInputXbarRegsFile") +#else +#pragma DATA_SECTION(ClbInputXbarRegs,"ClbInputXbarRegsFile"); +#endif +volatile struct INPUT_XBAR_REGS ClbInputXbarRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McanaSsRegsFile") +#else +#pragma DATA_SECTION(McanaSsRegs,"McanaSsRegsFile"); +#endif +volatile struct MCANSS_REGS McanaSsRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McanaErrRegsFile") +#else +#pragma DATA_SECTION(McanaErrRegs,"McanaErrRegsFile"); +#endif +volatile struct MCAN_ERROR_REGS McanaErrRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McanaRegsFile") +#else +#pragma DATA_SECTION(McanaRegs,"McanaRegsFile"); +#endif +volatile struct MCAN_REGS McanaRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemoryErrorRegsFile") +#else +#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); +#endif +volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemCfgRegsFile") +#else +#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); +#endif +volatile struct MEM_CFG_REGS MemCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct McBSP_REGS McbspaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct McBSP_REGS McbspbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("NmiIntruptRegsFile") +#else +#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); +#endif +volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("OutputXbarRegsFile") +#else +#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); +#endif +volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClbOutputXbarRegsFile") +#else +#pragma DATA_SECTION(ClbOutputXbarRegs,"ClbOutputXbarRegsFile"); +#endif +volatile struct OUTPUT_XBAR_REGS ClbOutputXbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +volatile struct PIE_VECT_TABLE PieVectTable; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PmbusaRegsFile") +#else +#pragma DATA_SECTION(PmbusaRegs,"PmbusaRegsFile"); +#endif +volatile struct PMBUS_REGS PmbusaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("RomPrefetchRegsFile") +#else +#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile"); +#endif +volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("RomWaitStateRegsFile") +#else +#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile"); +#endif +volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScidRegsFile") +#else +#pragma DATA_SECTION(ScidRegs,"ScidRegsFile"); +#endif +volatile struct SCI_REGS ScidRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm1RegsFile") +#else +#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm2RegsFile") +#else +#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpibRegsFile") +#else +#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); +#endif +volatile struct SPI_REGS SpibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpicRegsFile") +#else +#pragma DATA_SECTION(SpicRegs,"SpicRegsFile"); +#endif +volatile struct SPI_REGS SpicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpidRegsFile") +#else +#pragma DATA_SECTION(SpidRegs,"SpidRegsFile"); +#endif +volatile struct SPI_REGS SpidRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SyncSocRegsFile") +#else +#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); +#endif +volatile struct SYNC_SOC_REGS SyncSocRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SysStatusRegsFile") +#else +#pragma DATA_SECTION(SysStatusRegs,"SysStatusRegsFile"); +#endif +volatile struct SYS_STATUS_REGS SysStatusRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("TestErrorRegsFile") +#else +#pragma DATA_SECTION(TestErrorRegs,"TestErrorRegsFile"); +#endif +volatile struct TEST_ERROR_REGS TestErrorRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("WdRegsFile") +#else +#pragma DATA_SECTION(WdRegs,"WdRegsFile"); +#endif +volatile struct WD_REGS WdRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XbarRegsFile") +#else +#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); +#endif +volatile struct XBAR_REGS XbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XintRegsFile") +#else +#pragma DATA_SECTION(XintRegs,"XintRegsFile"); +#endif +volatile struct XINT_REGS XintRegs; + + + +//=========================================================================== +// End of file. +//=========================================================================== + + diff --git a/i2c_ex1_master/f2838x_gpio.c b/i2c_ex1_master/f2838x_gpio.c new file mode 100644 index 0000000..aca3330 --- /dev/null +++ b/i2c_ex1_master/f2838x_gpio.c @@ -0,0 +1,472 @@ +//########################################################################### +// +// FILE: f2838x_gpio.c +// +// TITLE: GPIO module support functions +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" +#include "f2838x_examples.h" + +// +//Low-level functions for GPIO configuration (CPU1 only) +// + +#ifdef CPU1 + // + // InitGpio - Sets all pins to be muxed to GPIO in input mode. + // Also resets CPU control to CPU1 and disables open + // drain and polarity inversion and sets the qualification to + // synchronous. Also unlocks all GPIOs. Only one CPU should call + // this function. + // + void InitGpio() + { + volatile Uint32 *gpioBaseAddr; + Uint16 regOffset; + + // + //Disable pin locks + // + EALLOW; + GpioCtrlRegs.GPALOCK.all = 0x00000000; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPCLOCK.all = 0x00000000; + GpioCtrlRegs.GPDLOCK.all = 0x00000000; + GpioCtrlRegs.GPELOCK.all = 0x00000000; + GpioCtrlRegs.GPFLOCK.all = 0x00000000; + + // + // Fill all registers with zeros. Writing to each register separately + // for six GPIO modules would make this function *very* long. + // Fortunately, we'd be writing them all with zeros anyway, so this + // saves a lot of space. + // + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; + for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) + { + // + //Hack to avoid enabling pull-ups on all pins. GPyPUD is offset + //0x0C in each register group of 0x40 words. Since this is a + //32-bit pointer, the addresses must be divided by 2. + // + if (regOffset % (0x40/2) != (0x0C/2)) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + } + + gpioBaseAddr = (Uint32 *)&GpioDataRegs; + for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + + EDIS; + } + + // + // GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The + // appropriate parameters can be found in the GPIO Muxed + // Pins table(4.4) in the datasheet. Use the GPIO index + // row (0 to 15) to select a muxing option for the GPIO. + // + void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *mux, *gmux, *csel; + Uint16 pin32, pin16, pin8; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pin8 = gpioNumber % 8; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Sanity check for valid cpu and peripheral values + // + if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF) + return; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyCSEL1-4. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + mux = gpioBaseAddr + GPYMUX + pin32/16; + gmux = gpioBaseAddr + GPYGMUX + pin32/16; + csel = gpioBaseAddr + GPYCSEL + pin32/8; + + // + //Now for the actual function + // + EALLOW; + + // + //To change the muxing, set the peripheral mux to 0/GPIO first to avoid + //glitches, then change the group mux, then set the peripheral mux to + //its target value. Finally, set the CPU select. This procedure is + //described in the TRM. Unfortunately, since we don't know the pin in + //advance we can't hardcode a bitfield reference, so there's some + //tricky bit twiddling here. + // + *mux &= ~(0x3UL << (2*pin16)); + *gmux &= ~(0x3UL << (2*pin16)); + *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); + *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); + + *csel &= ~(0x3L << (4*pin8)); + *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); + + // + //WARNING: This code does not touch the analog mode select registers, + //which are needed to give the USB module control of its IOs. + // + EDIS; + } + + // + // GPIO_SetupPinOptions - Setup up the GPIO input/output options for the + // specified pin. + // + //The flags are a 16-bit mask produced by ORing together options. + //For input pins, the valid flags are: + //GPIO_PULLUP Enable pull-up + //GPIO_INVERT Enable input polarity inversion + //GPIO_SYNC Synchronize the input latch to PLLSYSCLK + // (default -- you don't need to specify this) + //GPIO_QUAL3 Use 3-sample qualification + //GPIO_QUAL6 Use 6-sample qualification + //GPIO_ASYNC Do not use synchronization or qualification + //(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) + // + //For output pins, the valid flags are: + //GPIO_OPENDRAIN Output in open drain mode + //GPIO_PULLUP If open drain enabled, also enable the pull-up + //and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. + // + //With no flags, the default input state is synchronous with no + //pull-up or polarity inversion. The default output state is + //the standard digital output. + // + void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *dir, *pud, *inv, *odr, *qsel; + Uint32 pin32, pin16, pinMask, qual; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + dir = gpioBaseAddr + GPYDIR; + pud = gpioBaseAddr + GPYPUD; + inv = gpioBaseAddr + GPYINV; + odr = gpioBaseAddr + GPYODR; + qsel = gpioBaseAddr + GPYQSEL + pin32/16; + + EALLOW; + + // + //Set the data direction + // + *dir &= ~pinMask; + if (output == 1) + { + // + //Output, with optional open drain mode and pull-up + // + *dir |= pinMask; + + // + //Enable open drain if necessary + // + if (flags & GPIO_OPENDRAIN) + { + *odr |= pinMask; + } + else + { + *odr &= ~pinMask; + } + + // + //Enable pull-up if necessary. Open drain mode must be active. + // + if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + } + else + { + // + //Input, with optional pull-up, qualification, and polarity + //inversion + // + *dir &= ~pinMask; + + // + //Enable pull-up if necessary + // + if (flags & GPIO_PULLUP) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + + // + //Invert polarity if necessary + // + if (flags & GPIO_INVERT) + { + *inv |= pinMask; + } + else + { + *inv &= ~pinMask; + } + } + + // + //Extract the qualification parameter and load it into the register. + //This is also needed for open drain outputs, so we might as well do it + //all the time. + // + qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; + *qsel &= ~(0x3L << (2 * pin16)); + if (qual != 0x0) + { + *qsel |= qual << (2 * pin16); + } + + EDIS; + } + + // + // GPIO_SetupLock - Enable or disable the GPIO register bit lock for the + // specified pin. + // The valid flags are: + // GPIO_UNLOCK - Unlock the pin setup register bits for + // the specified pin + // GPIO_LOCK - Lock the pin setup register bits for the + // specified pin + // + void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *lock; + Uint32 pin32, pinMask; + + pin32 = gpioNumber % 32; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + lock = gpioBaseAddr + GPYLOCK; + + EALLOW; + if(flags) + { + //Lock the pin + *lock |= pinMask; + } + else + { + //Unlock the pin + *lock &= ~pinMask; + } + EDIS; + } + + // + //External interrupt setup + // + void GPIO_SetupXINT1Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT2Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT3Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT4Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT5Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin + EDIS; + } + + // + //GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded + // GPIOs on the 176PTP package: + // GPIOs Grp Bits + // 95-132 C 31 + // D 31:0 + // E 4:0 + // 134-168 E 31:6 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor176Pin() + { + EALLOW; + GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function + // this takes care of enabling IO pullups. + // + void GPIO_EnableUnbondedIOPullups() + { + // + //bits 8-10 have pin count + // + unsigned char pin_count = (DevCfgRegs.PARTIDL.bit.PIN_COUNT) ; + + // + //6 = 176 pin + //7 = 337 pin + // + if (pin_count == 6) + { + GPIO_EnableUnbondedIOPullupsFor176Pin(); + } + else + { + //do nothing - this is 337 pin package + } + } + +#endif //CPU1 + +// +// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that +// this returns the actual state of the pin, not the state of +// the output latch. +// +Uint16 GPIO_ReadPin(Uint16 gpioNumber) +{ + volatile Uint32 *gpioDataReg; + Uint16 pinVal; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; + + return pinVal; +} + +// +// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. +// +void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) +{ + volatile Uint32 *gpioDataReg; + Uint32 pinMask; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinMask = 1UL << (gpioNumber % 32); + + if (outVal == 0) + { + gpioDataReg[GPYCLEAR] = pinMask; + } + else + { + gpioDataReg[GPYSET] = pinMask; + } +} + +// +// End of file +// diff --git a/i2c_ex1_master/f2838x_headers_nonBIOS_cpu1.cmd b/i2c_ex1_master/f2838x_headers_nonBIOS_cpu1.cmd new file mode 100644 index 0000000..475a56a --- /dev/null +++ b/i2c_ex1_master/f2838x_headers_nonBIOS_cpu1.cmd @@ -0,0 +1,388 @@ +MEMORY +{ + PAGE 0: /* Program Memory */ + PAGE 1: /* Data Memory */ + ACCESSPROTECTION : origin = 0x0005F500, length = 0x00000040 + ADCA : origin = 0x00007400, length = 0x00000080 + ADCB : origin = 0x00007480, length = 0x00000080 + ADCC : origin = 0x00007500, length = 0x00000080 + ADCD : origin = 0x00007580, length = 0x00000080 + ADCARESULT : origin = 0x00000B00, length = 0x00000018 + ADCBRESULT : origin = 0x00000B20, length = 0x00000018 + ADCCRESULT : origin = 0x00000B40, length = 0x00000018 + ADCDRESULT : origin = 0x00000B60, length = 0x00000018 + ANALOGSUBSYS : origin = 0x0005D700, length = 0x00000100 + BGCRCCPU : origin = 0x00006340, length = 0x00000040 + BGCRCCLA1 : origin = 0x00006380, length = 0x00000040 + CANA : origin = 0x00048000, length = 0x00000200 + CANB : origin = 0x0004A000, length = 0x00000200 + CLA1 : origin = 0x00001400, length = 0x00000080 + CLB1DATAEXCH : origin = 0x00003180, length = 0x00000080 + CLB2DATAEXCH : origin = 0x00003380, length = 0x00000080 + CLB3DATAEXCH : origin = 0x00003580, length = 0x00000080 + CLB4DATAEXCH : origin = 0x00003780, length = 0x00000080 + CLB5DATAEXCH : origin = 0x00003980, length = 0x00000080 + CLB6DATAEXCH : origin = 0x00003B80, length = 0x00000080 + CLB7DATAEXCH : origin = 0x00003D80, length = 0x00000080 + CLB8DATAEXCH : origin = 0x00003F80, length = 0x00000080 + CLB1LOGICCFG : origin = 0x00003000, length = 0x00000052 + CLB2LOGICCFG : origin = 0x00003200, length = 0x00000052 + CLB3LOGICCFG : origin = 0x00003400, length = 0x00000052 + CLB4LOGICCFG : origin = 0x00003600, length = 0x00000052 + CLB5LOGICCFG : origin = 0x00003800, length = 0x00000052 + CLB6LOGICCFG : origin = 0x00003A00, length = 0x00000052 + CLB7LOGICCFG : origin = 0x00003C00, length = 0x00000052 + CLB8LOGICCFG : origin = 0x00003E00, length = 0x00000052 + CLB1LOGICCTRL : origin = 0x00003100, length = 0x00000040 + CLB2LOGICCTRL : origin = 0x00003300, length = 0x00000040 + CLB3LOGICCTRL : origin = 0x00003500, length = 0x00000040 + CLB4LOGICCTRL : origin = 0x00003700, length = 0x00000040 + CLB5LOGICCTRL : origin = 0x00003900, length = 0x00000040 + CLB6LOGICCTRL : origin = 0x00003B00, length = 0x00000040 + CLB7LOGICCTRL : origin = 0x00003D00, length = 0x00000040 + CLB8LOGICCTRL : origin = 0x00003F00, length = 0x00000040 + CLBXBAR : origin = 0x00007A40, length = 0x00000040 + CLKCFG : origin = 0x0005D200, length = 0x00000100 + CMPSS1 : origin = 0x00005C80, length = 0x00000020 + CMPSS2 : origin = 0x00005CA0, length = 0x00000020 + CMPSS3 : origin = 0x00005CC0, length = 0x00000020 + CMPSS4 : origin = 0x00005CE0, length = 0x00000020 + CMPSS5 : origin = 0x00005D00, length = 0x00000020 + CMPSS6 : origin = 0x00005D20, length = 0x00000020 + CMPSS7 : origin = 0x00005D40, length = 0x00000020 + CMPSS8 : origin = 0x00005D60, length = 0x00000020 + CMCONF : origin = 0x0005DC00, length = 0x00000400 + CPU1TOCMIPC : origin = 0x0005CE40, length = 0x00000026 + CPU1TOCPU2IPC : origin = 0x0005CE00, length = 0x00000026 + SYSPERIPHAC : origin = 0x0005D500, length = 0x00000200 + CPUTIMER0 : origin = 0x00000C00, length = 0x00000008 + CPUTIMER1 : origin = 0x00000C08, length = 0x00000008 + CPUTIMER2 : origin = 0x00000C10, length = 0x00000008 + CPUSYS : origin = 0x0005D300, length = 0x000000A0 + DACA : origin = 0x00005C00, length = 0x00000008 + DACB : origin = 0x00005C10, length = 0x00000008 + DACC : origin = 0x00005C20, length = 0x00000008 + DCC0 : origin = 0x0005E700, length = 0x00000038 + DCC1 : origin = 0x0005E740, length = 0x00000038 + DCC2 : origin = 0x0005E780, length = 0x00000038 + DCSMCOMMON : origin = 0x0005F0C0, length = 0x00000020 + DCSMZ1OTP : origin = 0x00078000, length = 0x00000020 + DCSMZ1 : origin = 0x0005F000, length = 0x0000003E + DCSMZ2OTP : origin = 0x00078200, length = 0x00000020 + DCSMZ2 : origin = 0x0005F080, length = 0x0000003E + DEVCFG : origin = 0x0005D000, length = 0x000001A0 + DMACLASRCSEL : origin = 0x00007980, length = 0x0000001A + DMA : origin = 0x00001000, length = 0x00000200 + ECAP1 : origin = 0x00005200, length = 0x00000020 + ECAP2 : origin = 0x00005240, length = 0x00000020 + ECAP3 : origin = 0x00005280, length = 0x00000020 + ECAP4 : origin = 0x000052C0, length = 0x00000020 + ECAP5 : origin = 0x00005300, length = 0x00000020 + ECAP6 : origin = 0x00005340, length = 0x00000020 + ECAP7 : origin = 0x00005380, length = 0x00000020 + EMIF1CONFIG : origin = 0x0005F4C0, length = 0x00000020 + EMIF2CONFIG : origin = 0x0005F4E0, length = 0x00000020 + EMIF1 : origin = 0x00047000, length = 0x00000070 + EMIF2 : origin = 0x00047800, length = 0x00000070 + EPWM1 : origin = 0x00004000, length = 0x00000100 + EPWM2 : origin = 0x00004100, length = 0x00000100 + EPWM3 : origin = 0x00004200, length = 0x00000100 + EPWM4 : origin = 0x00004300, length = 0x00000100 + EPWM5 : origin = 0x00004400, length = 0x00000100 + EPWM6 : origin = 0x00004500, length = 0x00000100 + EPWM7 : origin = 0x00004600, length = 0x00000100 + EPWM8 : origin = 0x00004700, length = 0x00000100 + EPWM9 : origin = 0x00004800, length = 0x00000100 + EPWM10 : origin = 0x00004900, length = 0x00000100 + EPWM11 : origin = 0x00004A00, length = 0x00000100 + EPWM12 : origin = 0x00004B00, length = 0x00000100 + EPWM13 : origin = 0x00004C00, length = 0x00000100 + EPWM14 : origin = 0x00004D00, length = 0x00000100 + EPWM15 : origin = 0x00004E00, length = 0x00000100 + EPWM16 : origin = 0x00004F00, length = 0x00000100 + EPWMXBAR : origin = 0x00007A00, length = 0x00000040 + EQEP1 : origin = 0x00005100, length = 0x00000040 + EQEP2 : origin = 0x00005140, length = 0x00000040 + EQEP3 : origin = 0x00005180, length = 0x00000040 + ERADCOUNTER1 : origin = 0x0005E980, length = 0x00000010 + ERADCOUNTER2 : origin = 0x0005E990, length = 0x00000010 + ERADCOUNTER3 : origin = 0x0005E9A0, length = 0x00000010 + ERADCOUNTER4 : origin = 0x0005E9B0, length = 0x00000010 + ERADCRCGLOBAL : origin = 0x0005EA00, length = 0x00000010 + ERADCRC1 : origin = 0x0005EA10, length = 0x00000010 + ERADCRC2 : origin = 0x0005EA20, length = 0x00000010 + ERADCRC3 : origin = 0x0005EA30, length = 0x00000010 + ERADCRC4 : origin = 0x0005EA40, length = 0x00000010 + ERADCRC5 : origin = 0x0005EA50, length = 0x00000010 + ERADCRC6 : origin = 0x0005EA60, length = 0x00000010 + ERADCRC7 : origin = 0x0005EA70, length = 0x00000010 + ERADCRC8 : origin = 0x0005EA80, length = 0x00000010 + ERADGLOBAL : origin = 0x0005E800, length = 0x00000014 + ERADHWBP1 : origin = 0x0005E900, length = 0x00000008 + ERADHWBP2 : origin = 0x0005E908, length = 0x00000008 + ERADHWBP3 : origin = 0x0005E910, length = 0x00000008 + ERADHWBP4 : origin = 0x0005E918, length = 0x00000008 + ERADHWBP5 : origin = 0x0005E920, length = 0x00000008 + ERADHWBP6 : origin = 0x0005E928, length = 0x00000008 + ERADHWBP7 : origin = 0x0005E930, length = 0x00000008 + ERADHWBP8 : origin = 0x0005E938, length = 0x00000008 + ESCSSCONFIG : origin = 0x00057F00, length = 0x00000016 + ESCSS : origin = 0x00057E00, length = 0x00000024 + FLASH0CTRL : origin = 0x0005F800, length = 0x00000182 + FLASH0ECC : origin = 0x0005FB00, length = 0x00000028 + FSIRXA : origin = 0x00006680, length = 0x00000050 + FSIRXB : origin = 0x00006780, length = 0x00000050 + FSIRXC : origin = 0x00006880, length = 0x00000050 + FSIRXD : origin = 0x00006980, length = 0x00000050 + FSIRXE : origin = 0x00006A80, length = 0x00000050 + FSIRXF : origin = 0x00006B80, length = 0x00000050 + FSIRXG : origin = 0x00006C80, length = 0x00000050 + FSIRXH : origin = 0x00006D80, length = 0x00000050 + FSITXA : origin = 0x00006600, length = 0x00000050 + FSITXB : origin = 0x00006700, length = 0x00000050 + GPIOCTRL : origin = 0x00007C00, length = 0x00000200 + GPIODATAREAD : origin = 0x00007F80, length = 0x00000010 + GPIODATA : origin = 0x00007F00, length = 0x00000040 + HRCAP6 : origin = 0x00005360, length = 0x00000020 + HRCAP7 : origin = 0x000053A0, length = 0x00000020 + I2CA : origin = 0x00007300, length = 0x00000022 + I2CB : origin = 0x00007340, length = 0x00000022 + INPUTXBAR : origin = 0x00007900, length = 0x00000020 + CLBINPUTXBAR : origin = 0x00007960, length = 0x00000020 + MCANASS : origin = 0x0005C400, length = 0x0000002C + MCANAERR : origin = 0x0005C800, length = 0x00000210 + MCANA : origin = 0x0005C600, length = 0x00000100 + MEMORYERROR : origin = 0x0005F540, length = 0x00000040 + MEMCFG : origin = 0x0005F400, length = 0x000000C0 + MCBSPA : origin = 0x00006000, length = 0x00000024 + MCBSPB : origin = 0x00006040, length = 0x00000024 + NMIINTRUPT : origin = 0x00007060, length = 0x00000010 + OUTPUTXBAR : origin = 0x00007A80, length = 0x00000040 + CLBOUTPUTXBAR : origin = 0x00007BC0, length = 0x00000040 + PIECTRL : origin = 0x00000CE0, length = 0x0000001A + PIEVECTTABLE : origin = 0x00000D00, length = 0x00000200 + PMBUSA : origin = 0x00006400, length = 0x00000020 + ROMPREFETCH : origin = 0x0005F588, length = 0x00000008 + ROMWAITSTATE : origin = 0x0005F580, length = 0x00000008 + SCIA : origin = 0x00007200, length = 0x00000010 + SCIB : origin = 0x00007210, length = 0x00000010 + SCIC : origin = 0x00007220, length = 0x00000010 + SCID : origin = 0x00007230, length = 0x00000010 + SDFM1 : origin = 0x00005E00, length = 0x00000080 + SDFM2 : origin = 0x00005E80, length = 0x00000080 + SPIA : origin = 0x00006100, length = 0x00000010 + SPIB : origin = 0x00006110, length = 0x00000010 + SPIC : origin = 0x00006120, length = 0x00000010 + SPID : origin = 0x00006130, length = 0x00000010 + SYNCSOC : origin = 0x00007940, length = 0x00000006 + SYSSTATUS : origin = 0x0005D400, length = 0x00000100 + TESTERROR : origin = 0x0005F590, length = 0x00000010 + WD : origin = 0x00007000, length = 0x0000002C + XBAR : origin = 0x00007920, length = 0x00000020 + XINT : origin = 0x00007070, length = 0x0000000C + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ +UNION run = PIEVECTTABLE +{ + PieVectTableFile + GROUP + { + EmuKeyVar + EmuBModeVar + EmuBootPinsVar + FlashCallbackVar + FlashScalingVar + } +} + + AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT + AdcaRegsFile : > ADCA, type=NOINIT + AdcbRegsFile : > ADCB, type=NOINIT + AdccRegsFile : > ADCC, type=NOINIT + AdcdRegsFile : > ADCD, type=NOINIT + AdcaResultRegsFile : > ADCARESULT, type=NOINIT + AdcbResultRegsFile : > ADCBRESULT, type=NOINIT + AdccResultRegsFile : > ADCCRESULT, type=NOINIT + AdcdResultRegsFile : > ADCDRESULT, type=NOINIT + AnalogSubsysRegsFile : > ANALOGSUBSYS, type=NOINIT + BgcrcCpuRegsFile : > BGCRCCPU, type=NOINIT + BgcrcCla1RegsFile : > BGCRCCLA1, type=NOINIT + CanaRegsFile : > CANA, type=NOINIT + CanbRegsFile : > CANB, type=NOINIT + Cla1RegsFile : > CLA1, type=NOINIT + Clb1DataExchRegsFile : > CLB1DATAEXCH, type=NOINIT + Clb2DataExchRegsFile : > CLB2DATAEXCH, type=NOINIT + Clb3DataExchRegsFile : > CLB3DATAEXCH, type=NOINIT + Clb4DataExchRegsFile : > CLB4DATAEXCH, type=NOINIT + Clb5DataExchRegsFile : > CLB5DATAEXCH, type=NOINIT + Clb6DataExchRegsFile : > CLB6DATAEXCH, type=NOINIT + Clb7DataExchRegsFile : > CLB7DATAEXCH, type=NOINIT + Clb8DataExchRegsFile : > CLB8DATAEXCH, type=NOINIT + Clb1LogicCfgRegsFile : > CLB1LOGICCFG, type=NOINIT + Clb2LogicCfgRegsFile : > CLB2LOGICCFG, type=NOINIT + Clb3LogicCfgRegsFile : > CLB3LOGICCFG, type=NOINIT + Clb4LogicCfgRegsFile : > CLB4LOGICCFG, type=NOINIT + Clb5LogicCfgRegsFile : > CLB5LOGICCFG, type=NOINIT + Clb6LogicCfgRegsFile : > CLB6LOGICCFG, type=NOINIT + Clb7LogicCfgRegsFile : > CLB7LOGICCFG, type=NOINIT + Clb8LogicCfgRegsFile : > CLB8LOGICCFG, type=NOINIT + Clb1LogicCtrlRegsFile : > CLB1LOGICCTRL, type=NOINIT + Clb2LogicCtrlRegsFile : > CLB2LOGICCTRL, type=NOINIT + Clb3LogicCtrlRegsFile : > CLB3LOGICCTRL, type=NOINIT + Clb4LogicCtrlRegsFile : > CLB4LOGICCTRL, type=NOINIT + Clb5LogicCtrlRegsFile : > CLB5LOGICCTRL, type=NOINIT + Clb6LogicCtrlRegsFile : > CLB6LOGICCTRL, type=NOINIT + Clb7LogicCtrlRegsFile : > CLB7LOGICCTRL, type=NOINIT + Clb8LogicCtrlRegsFile : > CLB8LOGICCTRL, type=NOINIT + CLBXbarRegsFile : > CLBXBAR, type=NOINIT + ClkCfgRegsFile : > CLKCFG, type=NOINIT + Cmpss1RegsFile : > CMPSS1, type=NOINIT + Cmpss2RegsFile : > CMPSS2, type=NOINIT + Cmpss3RegsFile : > CMPSS3, type=NOINIT + Cmpss4RegsFile : > CMPSS4, type=NOINIT + Cmpss5RegsFile : > CMPSS5, type=NOINIT + Cmpss6RegsFile : > CMPSS6, type=NOINIT + Cmpss7RegsFile : > CMPSS7, type=NOINIT + Cmpss8RegsFile : > CMPSS8, type=NOINIT + CmConfRegsFile : > CMCONF, type=NOINIT + Cpu1toCmIpcRegsFile : > CPU1TOCMIPC, type=NOINIT + Cpu1toCpu2IpcRegsFile : > CPU1TOCPU2IPC, type=NOINIT + SysPeriphAcRegsFile : > SYSPERIPHAC, type=NOINIT + CpuTimer0RegsFile : > CPUTIMER0, type=NOINIT + CpuTimer1RegsFile : > CPUTIMER1, type=NOINIT + CpuTimer2RegsFile : > CPUTIMER2, type=NOINIT + CpuSysRegsFile : > CPUSYS, type=NOINIT + DacaRegsFile : > DACA, type=NOINIT + DacbRegsFile : > DACB, type=NOINIT + DaccRegsFile : > DACC, type=NOINIT + Dcc0RegsFile : > DCC0, type=NOINIT + Dcc1RegsFile : > DCC1, type=NOINIT + Dcc2RegsFile : > DCC2, type=NOINIT + DcsmCommonRegsFile : > DCSMCOMMON, type=NOINIT + DcsmZ1OtpRegsFile : > DCSMZ1OTP, type=NOINIT + DcsmZ1RegsFile : > DCSMZ1, type=NOINIT + DcsmZ2OtpRegsFile : > DCSMZ2OTP, type=NOINIT + DcsmZ2RegsFile : > DCSMZ2, type=NOINIT + DevCfgRegsFile : > DEVCFG, type=NOINIT + DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT + DmaRegsFile : > DMA, type=NOINIT + ECap1RegsFile : > ECAP1, type=NOINIT + ECap2RegsFile : > ECAP2, type=NOINIT + ECap3RegsFile : > ECAP3, type=NOINIT + ECap4RegsFile : > ECAP4, type=NOINIT + ECap5RegsFile : > ECAP5, type=NOINIT + ECap6RegsFile : > ECAP6, type=NOINIT + ECap7RegsFile : > ECAP7, type=NOINIT + Emif1ConfigRegsFile : > EMIF1CONFIG, type=NOINIT + Emif2ConfigRegsFile : > EMIF2CONFIG, type=NOINIT + Emif1RegsFile : > EMIF1, type=NOINIT + Emif2RegsFile : > EMIF2, type=NOINIT + EPwm1RegsFile : > EPWM1, type=NOINIT + EPwm2RegsFile : > EPWM2, type=NOINIT + EPwm3RegsFile : > EPWM3, type=NOINIT + EPwm4RegsFile : > EPWM4, type=NOINIT + EPwm5RegsFile : > EPWM5, type=NOINIT + EPwm6RegsFile : > EPWM6, type=NOINIT + EPwm7RegsFile : > EPWM7, type=NOINIT + EPwm8RegsFile : > EPWM8, type=NOINIT + EPwm9RegsFile : > EPWM9, type=NOINIT + EPwm10RegsFile : > EPWM10, type=NOINIT + EPwm11RegsFile : > EPWM11, type=NOINIT + EPwm12RegsFile : > EPWM12, type=NOINIT + EPwm13RegsFile : > EPWM13, type=NOINIT + EPwm14RegsFile : > EPWM14, type=NOINIT + EPwm15RegsFile : > EPWM15, type=NOINIT + EPwm16RegsFile : > EPWM16, type=NOINIT + EPwmXbarRegsFile : > EPWMXBAR, type=NOINIT + EQep1RegsFile : > EQEP1, type=NOINIT + EQep2RegsFile : > EQEP2, type=NOINIT + EQep3RegsFile : > EQEP3, type=NOINIT + EradCounter1RegsFile : > ERADCOUNTER1, type=NOINIT + EradCounter2RegsFile : > ERADCOUNTER2, type=NOINIT + EradCounter3RegsFile : > ERADCOUNTER3, type=NOINIT + EradCounter4RegsFile : > ERADCOUNTER4, type=NOINIT + EradCRCGlobalRegsFile : > ERADCRCGLOBAL, type=NOINIT + EradCRC1RegsFile : > ERADCRC1, type=NOINIT + EradCRC2RegsFile : > ERADCRC2, type=NOINIT + EradCRC3RegsFile : > ERADCRC3, type=NOINIT + EradCRC4RegsFile : > ERADCRC4, type=NOINIT + EradCRC5RegsFile : > ERADCRC5, type=NOINIT + EradCRC6RegsFile : > ERADCRC6, type=NOINIT + EradCRC7RegsFile : > ERADCRC7, type=NOINIT + EradCRC8RegsFile : > ERADCRC8, type=NOINIT + EradGlobalRegsFile : > ERADGLOBAL, type=NOINIT + EradHWBP1RegsFile : > ERADHWBP1, type=NOINIT + EradHWBP2RegsFile : > ERADHWBP2, type=NOINIT + EradHWBP3RegsFile : > ERADHWBP3, type=NOINIT + EradHWBP4RegsFile : > ERADHWBP4, type=NOINIT + EradHWBP5RegsFile : > ERADHWBP5, type=NOINIT + EradHWBP6RegsFile : > ERADHWBP6, type=NOINIT + EradHWBP7RegsFile : > ERADHWBP7, type=NOINIT + EradHWBP8RegsFile : > ERADHWBP8, type=NOINIT + EscssConfigRegsFile : > ESCSSCONFIG, type=NOINIT + EscssRegsFile : > ESCSS, type=NOINIT + Flash0CtrlRegsFile : > FLASH0CTRL, type=NOINIT + Flash0EccRegsFile : > FLASH0ECC, type=NOINIT + FsiRxaRegsFile : > FSIRXA, type=NOINIT + FsiRxbRegsFile : > FSIRXB, type=NOINIT + FsiRxcRegsFile : > FSIRXC, type=NOINIT + FsiRxdRegsFile : > FSIRXD, type=NOINIT + FsiRxeRegsFile : > FSIRXE, type=NOINIT + FsiRxfRegsFile : > FSIRXF, type=NOINIT + FsiRxgRegsFile : > FSIRXG, type=NOINIT + FsiRxhRegsFile : > FSIRXH, type=NOINIT + FsiTxaRegsFile : > FSITXA, type=NOINIT + FsiTxbRegsFile : > FSITXB, type=NOINIT + GpioCtrlRegsFile : > GPIOCTRL, type=NOINIT + GpioDataReadRegsFile : > GPIODATAREAD, type=NOINIT + GpioDataRegsFile : > GPIODATA, type=NOINIT + HRCap6RegsFile : > HRCAP6, type=NOINIT + HRCap7RegsFile : > HRCAP7, type=NOINIT + I2caRegsFile : > I2CA, type=NOINIT + I2cbRegsFile : > I2CB, type=NOINIT + InputXbarRegsFile : > INPUTXBAR, type=NOINIT + ClbInputXbarRegsFile : > CLBINPUTXBAR, type=NOINIT + McanaSsRegsFile : > MCANASS, type=NOINIT + McanaErrRegsFile : > MCANAERR, type=NOINIT + McanaRegsFile : > MCANA, type=NOINIT + MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT + MemCfgRegsFile : > MEMCFG, type=NOINIT + McbspaRegsFile : > MCBSPA, type=NOINIT + McbspbRegsFile : > MCBSPB, type=NOINIT + NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT + OutputXbarRegsFile : > OUTPUTXBAR, type=NOINIT + ClbOutputXbarRegsFile : > CLBOUTPUTXBAR, type=NOINIT + PieCtrlRegsFile : > PIECTRL, type=NOINIT + PieVectTableFile : > PIEVECTTABLE, type=NOINIT + PmbusaRegsFile : > PMBUSA, type=NOINIT + RomPrefetchRegsFile : > ROMPREFETCH, type=NOINIT + RomWaitStateRegsFile : > ROMWAITSTATE, type=NOINIT + SciaRegsFile : > SCIA, type=NOINIT + ScibRegsFile : > SCIB, type=NOINIT + ScicRegsFile : > SCIC, type=NOINIT + ScidRegsFile : > SCID, type=NOINIT + Sdfm1RegsFile : > SDFM1, type=NOINIT + Sdfm2RegsFile : > SDFM2, type=NOINIT + SpiaRegsFile : > SPIA, type=NOINIT + SpibRegsFile : > SPIB, type=NOINIT + SpicRegsFile : > SPIC, type=NOINIT + SpidRegsFile : > SPID, type=NOINIT + SyncSocRegsFile : > SYNCSOC, type=NOINIT + SysStatusRegsFile : > SYSSTATUS, type=NOINIT + TestErrorRegsFile : > TESTERROR, type=NOINIT + WdRegsFile : > WD, type=NOINIT + XbarRegsFile : > XBAR, type=NOINIT + XintRegsFile : > XINT, type=NOINIT +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/i2c_ex1_master/f2838x_piectrl.c b/i2c_ex1_master/f2838x_piectrl.c new file mode 100644 index 0000000..3fbd8a5 --- /dev/null +++ b/i2c_ex1_master/f2838x_piectrl.c @@ -0,0 +1,121 @@ +//########################################################################### +// +// FILE: f2838x_piectrl.c +// +// TITLE: F2838x Device PIE Control Register Initialization Functions. +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" // F2838x Headerfile Include File +#include "f2838x_examples.h" // F2838x Examples Include File + +// +// InitPieCtrl - This function initializes the PIE control registers to a +// known state. +// +void InitPieCtrl(void) +{ + // + // Disable Interrupts at the CPU level: + // + DINT; + + // + // Disable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // + // Clear all PIEIER registers: + // + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // + // Clear all PIEIFR registers: + // + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; +} + +// +// EnableInterrupts - This function enables the PIE module and CPU __interrupts +// +void EnableInterrupts() +{ + // + // Enable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enables PIE to drive a pulse into the CPU + // + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // + // Enable Interrupts at the CPU level + // + EINT; +} + +// +// End of file +// diff --git a/i2c_ex1_master/f2838x_pievect.c b/i2c_ex1_master/f2838x_pievect.c new file mode 100644 index 0000000..5f0d7cb --- /dev/null +++ b/i2c_ex1_master/f2838x_pievect.c @@ -0,0 +1,309 @@ +//########################################################################### +// +// FILE: f2838x_pievect.c +// +// TITLE: f2838x Device PIE Vector Initialization Functions +// +//########################################################################### +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" // f2838x Header File Include File +#include "f2838x_examples.h" // f2838x Examples Include File + +// +// Globals +// +const struct PIE_VECT_TABLE PieVectTableInit = { + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + TIMER1_ISR, // CPU Timer 1 Interrupt + TIMER2_ISR, // CPU Timer 2 Interrupt + DATALOG_ISR, // Datalogging Interrupt + RTOS_ISR, // RTOS Interrupt + EMU_ISR, // Emulation Interrupt + NMI_ISR, // Non-Maskable Interrupt + ILLEGAL_ISR, // Illegal Operation Trap + USER1_ISR, // User Defined Trap 1 + USER2_ISR, // User Defined Trap 2 + USER3_ISR, // User Defined Trap 3 + USER4_ISR, // User Defined Trap 4 + USER5_ISR, // User Defined Trap 5 + USER6_ISR, // User Defined Trap 6 + USER7_ISR, // User Defined Trap 7 + USER8_ISR, // User Defined Trap 8 + USER9_ISR, // User Defined Trap 9 + USER10_ISR, // User Defined Trap 10 + USER11_ISR, // User Defined Trap 11 + USER12_ISR, // User Defined Trap 12 + ADCA1_ISR, // 1.1 - ADCA Interrupt 1 + ADCB1_ISR, // 1.2 - ADCB Interrupt 1 + ADCC1_ISR, // 1.3 - ADCC Interrupt 1 + XINT1_ISR, // 1.4 - XINT1 Interrupt + XINT2_ISR, // 1.5 - XINT2 Interrupt + ADCD1_ISR, // 1.6 - ADCD Interrupt 1 + TIMER0_ISR, // 1.7 - Timer 0 Interrupt + WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt + EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt + EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt + EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt + EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt + EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt + EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt + EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt + EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt + EPWM1_ISR, // 3.1 - ePWM1 Interrupt + EPWM2_ISR, // 3.2 - ePWM2 Interrupt + EPWM3_ISR, // 3.3 - ePWM3 Interrupt + EPWM4_ISR, // 3.4 - ePWM4 Interrupt + EPWM5_ISR, // 3.5 - ePWM5 Interrupt + EPWM6_ISR, // 3.6 - ePWM6 Interrupt + EPWM7_ISR, // 3.7 - ePWM7 Interrupt + EPWM8_ISR, // 3.8 - ePWM8 Interrupt + ECAP1_ISR, // 4.1 - eCAP1 Interrupt + ECAP2_ISR, // 4.2 - eCAP2 Interrupt + ECAP3_ISR, // 4.3 - eCAP3 Interrupt + ECAP4_ISR, // 4.4 - eCAP4 Interrupt + ECAP5_ISR, // 4.5 - eCAP5 Interrupt + ECAP6_ISR, // 4.6 - eCAP6 Interrupt + ECAP7_ISR, // 4.7 - eCAP7 Interrupt + PIE_RESERVED_ISR, // 4.8 - Reserved + EQEP1_ISR, // 5.1 - eQEP1 Interrupt + EQEP2_ISR, // 5.2 - eQEP2 Interrupt + EQEP3_ISR, // 5.3 - eQEP3 Interrupt + PIE_RESERVED_ISR, // 5.4 - Reserved + CLB1_ISR, // 5.5 - CLB1 (Reconfigurable Logic) Interrupt + CLB2_ISR, // 5.6 - CLB2 (Reconfigurable Logic) Interrupt + CLB3_ISR, // 5.7 - CLB3 (Reconfigurable Logic) Interrupt + CLB4_ISR, // 5.8 - CLB4 (Reconfigurable Logic) Interrupt + SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt + SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt + SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt + SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt + MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt + MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt + MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt + MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt + DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt + DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt + DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt + DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt + DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt + DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt + PIE_RESERVED_ISR, // 7.7 - Reserved + PIE_RESERVED_ISR, // 7.8 - Reserved + I2CA_ISR, // 8.1 - I2CA Interrupt 1 + I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 + I2CB_ISR, // 8.3 - I2CB Interrupt 1 + I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 + SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt + SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt + SCID_RX_ISR, // 8.7 - SCID Receive Interrupt + SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt + SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt + SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt + SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt + SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt + CANA0_ISR, // 9.5 - CANA Interrupt 0 + CANA1_ISR, // 9.6 - CANA Interrupt 1 + CANB0_ISR, // 9.7 - CANB Interrupt 0 + CANB1_ISR, // 9.8 - CANB Interrupt 1 + ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt + ADCA2_ISR, // 10.2 - ADCA Interrupt 2 + ADCA3_ISR, // 10.3 - ADCA Interrupt 3 + ADCA4_ISR, // 10.4 - ADCA Interrupt 4 + ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt + ADCB2_ISR, // 10.6 - ADCB Interrupt 2 + ADCB3_ISR, // 10.7 - ADCB Interrupt 3 + ADCB4_ISR, // 10.8 - ADCB Interrupt 4 + CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 + CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 + CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 + CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 + CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 + CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 + CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 + CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 + XINT3_ISR, // 12.1 - XINT3 Interrupt + XINT4_ISR, // 12.2 - XINT4 Interrupt + XINT5_ISR, // 12.3 - XINT5 Interrupt + MPOST_ISR, // 12.4 - MPOST Interrupt + FMC_ISR, // 12.5 - Flash Wrapper Operation Done Interrupt + PIE_RESERVED_ISR, // 12.6 - Reserved + FPU_OFLOW_ISR, // 12.7 - FPU Overflow Interrupt + FPU_UFLOW_ISR, // 12.8 - FPU Underflow Interrupt + I2CA_HIGH_ISR, // 1.9 - I2CA Interrupt high priority + SYS_ERR_ISR, // 1.10 - System error interrupt + ECATSYNC0_ISR, // 1.11 - ETHERCAT SYNC0 interrupt + ECAT_ISR, // 1.12 - ETHERCAT main interrupt + CIPC0_ISR, // 1.13 - C28x CPU IPC interrupt 1 + CIPC1_ISR, // 1.14 - C28x CPU IPC interrupt 2 + CIPC2_ISR, // 1.15 - C28x CPU IPC interrupt 3 + CIPC3_ISR, // 1.16 - C28x CPU IPC interrupt 4 + EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt + EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt + EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt + EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt + EPWM13_TZ_ISR, // 2.13 - ePWM13 Trip Zone Interrupt + EPWM14_TZ_ISR, // 2.14 - ePWM14 Trip Zone Interrupt + EPWM15_TZ_ISR, // 2.15 - ePWM15 Trip Zone Interrupt + EPWM16_TZ_ISR, // 2.16 - ePWM16 Trip Zone Interrupt + EPWM9_ISR, // 3.9 - ePWM9 Interrupt + EPWM10_ISR, // 3.10 - ePWM10 Interrupt + EPWM11_ISR, // 3.11 - ePWM11 Interrupt + EPWM12_ISR, // 3.12 - ePWM12 Interrupt + EPWM13_ISR, // 3.13 - ePWM13 Interrupt + EPWM14_ISR, // 3.14 - ePWM14 Interrupt + EPWM15_ISR, // 3.15 - ePWM15 Interrupt + EPWM16_ISR, // 3.16 - ePWM16 Interrupt + FSITXA1_ISR, // 4.9 - FSIA Transmit interrupt 1 + FSITXA2_ISR, // 4.10 - FSIA Transmit interrupt 2 + FSITXB1_ISR, // 4.11 - FSIB Transmit interrupt 1 + FSITXB2_ISR, // 4.12 - FSIB Transmit interrupt 2 + FSIRXA1_ISR, // 4.13 - FSIA Receive interrupt 1 + FSIRXA2_ISR, // 4.14 - FSIA Receive interrupt 2 + FSIRXB1_ISR, // 4.15 - FSIB Receive interrupt 1 + FSIRXB2_ISR, // 4.16 - FSIB Receive interrupt 2 + SDFM1_ISR, // 5.9 - Sigma Delta Filter Module1 Interrupt + SDFM2_ISR, // 5.10 - Sigma Delta Filter Module2 Interrupt + ECATRST_ISR, // 5.11 - ETHERCAT Resetout Interrupt + ECATSYNC1_ISR, // 5.12 - ETHERCAT SYNC1 interrupt + SDFM1DR1_ISR, // 5.13 - Sigma Delta Filter Module1 Filter 1 Interrupt + SDFM1DR2_ISR, // 5.14 - Sigma Delta Filter Module1 Filter 2 Interrupt + SDFM1DR3_ISR, // 5.15 - Sigma Delta Filter Module1 Filter 3 Interrupt + SDFM1DR4_ISR, // 5.16 - Sigma Delta Filter Module1 Filter 4 Interrupt + SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt + SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt + SPID_RX_ISR, // 6.11 - SPID Receive Interrupt + SPID_TX_ISR, // 6.12 - SPID Transmit Interrupt + SDFM2DR1_ISR, // 6.13 - Sigma Delta Filter Module2 Filter 1 Interrupt + SDFM2DR2_ISR, // 6.14 - Sigma Delta Filter Module2 Filter 2 Interrupt + SDFM2DR3_ISR, // 6.15 - Sigma Delta Filter Module2 Filter 3 Interrupt + SDFM2DR4_ISR, // 6.16 - Sigma Delta Filter Module2 Filter 4 Interrupt + FSIRXC1_ISR, // 7.9 - FSIC Receive interrupt 1 + FSIRXC2_ISR, // 7.10 - FSIC Receive interrupt 2 + FSIRXD1_ISR, // 7.11 - FSID Receive interrupt 1 + FSIRXD2_ISR, // 7.12 - FSID Receive interrupt 2 + FSIRXE1_ISR, // 7.13 - FSIE Receive interrupt 1 + FSIRXE2_ISR, // 7.14 - FSIE Receive interrupt 2 + FSIRXF1_ISR, // 7.15 - FSIF Receive interrupt 1 + FSIRXF2_ISR, // 7.16 - FSIF Receive interrupt 2 + FSIRXG1_ISR, // 8.9 - FSIG Receive interrupt 1 + FSIRXG2_ISR, // 8.10 - FSIG Receive interrupt 2 + FSIRXH1_ISR, // 8.11 - FSIH Receive interrupt 1 + FSIRXH2_ISR, // 8.12 - FSIH Receive interrupt 2 + CLB5_ISR, // 8.13 - CLB5 Interrupt + CLB6_ISR, // 8.14 - CLB6 Interrupt + CLB7_ISR, // 8.15 - CLB7 Interrupt + CLB8_ISR, // 8.16 - CLB8 Interrupt + MCANA_0_ISR, // 9.9 - MCAN Sub-System Interrupt 0 + MCANA_1_ISR, // 9.10 - MCAN Sub-System Interrupt 1 + MCANA_ECC_ISR, // 9.11 - MCAN Sub-System ECC error Interrupt + MCANA_WAKE_ISR, // 9.12 - MCAN Sub-System wakeup Interrupt + PMBUSA_ISR, // 9.13 - PMBUSA Interrupt + CM_STATUS_ISR, // 9.14 - CM Reset Status Interrupt + USBA_ISR, // 9.15 - USBA Interrupt + PIE_RESERVED_ISR, // 9.16 - Reserved + ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt + ADCC2_ISR, // 10.10 - ADCC Interrupt 2 + ADCC3_ISR, // 10.11 - ADCC Interrupt 3 + ADCC4_ISR, // 10.12 - ADCC Interrupt 4 + ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt + ADCD2_ISR, // 10.14 - ADCD Interrupt 2 + ADCD3_ISR, // 10.15 - ADCD Interrupt 3 + ADCD4_ISR, // 10.16 - ADCD Interrupt 4 + CMTOCPUXIPC0_ISR, // 11.9 - CM to CPU IPC Interrupt 0 + CMTOCPUXIPC1_ISR, // 11.10 - CM to CPU IPC Interrupt 1 + CMTOCPUXIPC2_ISR, // 11.11 - CM to CPU IPC Interrupt 2 + CMTOCPUXIPC3_ISR, // 11.12 - CM to CPU IPC Interrupt 3 + CMTOCPUXIPC4_ISR, // 11.13 - CM to CPU IPC Interrupt 4 + CMTOCPUXIPC5_ISR, // 11.14 - CM to CPU IPC Interrupt 5 + CMTOCPUXIPC6_ISR, // 11.15 - CM to CPU IPC Interrupt 6 + CMTOCPUXIPC7_ISR, // 11.16 - CM to CPU IPC Interrupt 7 + PIE_RESERVED_ISR, // 12.9 - Reserved + ECAP6_2_ISR, // 12.10 - eCAP6 Interrupt 2 + ECAP7_2_ISR, // 12.11 - eCAP7 Interrupt 2 + PIE_RESERVED_ISR, // 12.12 - Reserved + CPUCRC_ISR, // 12.13 - CPU BGCRC module interrupt + CLA1CRC_ISR, // 12.14 - CLA1 BGCRC module interrupt + CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt + CLA_UNDERFLOW_ISR, // 12.16 - CLA Underflow Interrupt +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a +// known state and must be executed after boot time. +// +void InitPieVectTable(void) +{ + Uint16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + // + // Do not write over first 3 32-bit locations (these locations are + // initialized by Boot ROM with boot variables) + // + Source = Source + 3; + Dest = Dest + 3; + + EALLOW; + for(i = 0; i < 221; i++) + { + *Dest++ = *Source++; + } + EDIS; + + // + // Enable the PIE Vector Table + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; +} + +// +// End of file +// diff --git a/i2c_ex1_master/f2838x_sysctrl.c b/i2c_ex1_master/f2838x_sysctrl.c new file mode 100644 index 0000000..e6da39b --- /dev/null +++ b/i2c_ex1_master/f2838x_sysctrl.c @@ -0,0 +1,1463 @@ +//########################################################################### +// +// FILE: f2838x_sysctrl.c +// +// TITLE: F2838x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: +// +// Example initialization of system resources. +// +//########################################################################### +// +// +// $Copyright: +// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "f2838x_device.h" +#include "f2838x_examples.h" +#include "math.h" + +// +// Functions that will be run from RAM need to be assigned to a different +// section. This section will then be mapped to a load and run address using +// the linker cmd file. +// +// *IMPORTANT* +// +// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM +// FLASH TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM +// THROWING AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. +// +#pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); +#pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); + + +// The following values are used to validate PLL Frequency using DCC +// +#define DCC_COUNTER0_TOLERANCE 1 + +#ifdef USE_20MHZ_XTAL + +#define OSC_FREQ 20 + +// +// Multipliers and dividers to configure 200MHz SYSPLL output from 20MHz XTAL +// +#define SYS_IMULT IMULT_40 +#define SYS_REFDIV REFDIV_2 +#define SYS_ODIV ODIV_2 +#define SYS_DIV PLLCLK_BY_1 + +// +// Multipliers and dividers to configure 125MHz AUXPLL output from 20MHz XTAL +// +#define AUX_IMULT IMULT_50 +#define AUX_REFDIV REFDIV_2 +#define AUX_ODIV ODIV_4 +#define AUX_DIV AUXPLLRAWCLK_BY_1 + + +#else // USE_25MHZ_XTAL + +#define OSC_FREQ 25 + +// +// Multipliers and dividers to configure 200MHz SYSPLL output from 25MHz XTAL +// +#define SYS_IMULT IMULT_32 +#define SYS_REFDIV REFDIV_2 +#define SYS_ODIV ODIV_2 +#define SYS_DIV PLLCLK_BY_1 + +// +// Multipliers and dividers to configure 125MHz AUXPLL output from 25MHz XTAL +// +#define AUX_IMULT IMULT_40 +#define AUX_REFDIV REFDIV_2 +#define AUX_ODIV ODIV_4 +#define AUX_DIV AUXPLLRAWCLK_BY_1 + +#endif + +// +// InitSysCtrl - Initialization of system resources. +// +void InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + +#ifdef _FLASH + // + // Copy time critical code and Flash setup code to RAM. This includes the + // following functions: InitFlash() + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart + // symbols are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + InitFlash(); +#endif + + // + // *IMPORTANT* + // + // The Device_cal function, which copies the ADC & oscillator calibration + // values from TI reserved OTP into the appropriate trim registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC and + // oscillators to function according to specification. The clocks to the + // ADC MUST be enabled before calling this function. + // + // See the device data manual and/or the ADC Reference Manual for more + // information. + // +#ifdef CPU1 + // + // Enable pull-ups on unbonded IOs as soon as possible to reduce power + // consumption. + // + GPIO_EnableUnbondedIOPullups(); + + EALLOW; + + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + // + // Check if device is trimmed + // + if(*((Uint16 *)0x5D736) == 0x0000){ + // + // Device is not trimmed--apply static calibration values + // + AnalogSubsysRegs.ANAREFTRIMA.all = 31709; + AnalogSubsysRegs.ANAREFTRIMB.all = 31709; + AnalogSubsysRegs.ANAREFTRIMC.all = 31709; + AnalogSubsysRegs.ANAREFTRIMD.all = 31709; + } + + CpuSysRegs.PCLKCR13.bit.ADC_A = 0; + CpuSysRegs.PCLKCR13.bit.ADC_B = 0; + CpuSysRegs.PCLKCR13.bit.ADC_C = 0; + CpuSysRegs.PCLKCR13.bit.ADC_D = 0; + EDIS; + + // + // Verify the crystal frequency. + // Note: This check can be removed if you are not using XTAL as the PLL + // source + // + if(!VerifyXTAL(OSC_FREQ)) + { + // + // The actual XTAL frequency does not match OSC_FREQ!! + // Please check the XTAL frequency used. + // + // By default, the InitSysCtrl function assumes 25MHz XTAL. + // If a 20MHz crystal is used, please add a predefined symbol + // "USE_20MHZ_XTAL" in your CCS project. + // If a different XTAL is used, please update the PLL configuration + // below accordingly. + // + // Note that the latest F2838x controlCARDs (Rev.B and later) have been + // updated to use 25MHz XTAL by default. If you have an older 20MHz XTAL + // controlCARD (E1, E2, or Rev.A), refer to the controlCARD + // documentation on steps to reconfigure the controlCARD from 20MHz to + // 25MHz. + // + ESTOP0; + while(1); + } + + // + // Initialize the SYSPLL control to generate a 200Mhz clock + // + // Defined options to be passed as arguments to this function are defined + // in f2838x_examples.h. + // + // Note: The internal oscillator CANNOT be used as the PLL source if the + // PLLSYSCLK is configured to frequencies above 194 MHz. + // + // PLLSYSCLK = (XTAL_OSC) * (IMULT) /(REFDIV) * (ODIV) * (PLLSYSCLKDIV) + // + InitSysPll(XTAL_OSC, SYS_IMULT, SYS_REFDIV, SYS_ODIV, SYS_DIV, SYSCTL_DCC_BASE0); + + // + // Initialize the AUXPLL control to generate a 125Mhz clock: + // + // Defined options to be passed as arguments to this function are defined + // in f2838x_Examples.h. + // + // Note: The internal oscillator CANNOT be used as the PLL source if the + // AUXPLLCLK is configured to frequencies above 194 MHz. + // + // AUXPLLCLK = (XTAL_OSC) * (IMULT) /(REFDIV) * (ODIV) * (AUXPLLDIV) + // + InitAuxPll(XTAL_OSC, AUX_IMULT, AUX_REFDIV, AUX_ODIV, AUX_DIV, SYSCTL_DCC_BASE1); + + // + // Set up CMCLK to use AUXPLL as the clock source and set the + // clock divider to 1. + // + EALLOW; + ClkCfgRegs.CMCLKCTL.bit.CMCLKDIV = 0; // 0 : Divide by 1 + ClkCfgRegs.CMCLKCTL.bit.CMDIVSRCSEL = 0; // 0 : AuxPLL is the source for the CM clock divider. + EDIS; + +#ifndef _FLASH + // + // Call Device_cal function when run using debugger + // This function is called as part of the Boot code. The function is called + // in the InitSysCtrl function since during debug time resets, the boot code + // will not be executed and the gel script will reinitialize all the + // registers and the calibrated values will be lost. + // + Device_cal(); +#endif + +#endif // CPU1 + + // + // Turn on all peripherals + // + InitPeripheralClocks(); +} + +// +// +// Function to verify the XTAL frequency +// freq is the XTAL frequency in MHz +// The function return true if the the actual XTAL frequency matches with the +// input value +// +// +#ifdef CPU1 +bool VerifyXTAL(float freq) +{ + // + // Configures XTAL as CLKSRC0 and INTOSC2 as CLKSRC1. + // Fclk0 = XTAL frequency (input parameter) + // Fclk1 = INTOSC2 frequency = 10MHz + // + // Calculating Counter0 & Valid Seed Value with +/-1% tolerance + // INTOSC can have a variance in frequency of +/-10% + // + // Since Fclk1 < Fclk0, then Async. Error (In Clock0 cycles) = + // 2*(Fclk0/Fclk1) + 2*(Fsysclk/Fclk0) + // Digitization error = 8 Clock0 cycles + // DCC Error (in Cycles) = 2*(Fclk0/Fclk1) + 2*(Fsysclk/Fclk0) + 8 + // Window (in Cycles) = (Total Error) / (0.01 * Tolerance) + // Error due to variance in frequency = Window * freqVariance + // Total error = DCC Error + Error due to variance in frequency + // Counter0 = Window - Total Error + // Valid0 = 2 * Total Error + // Counter1 = Window * (Fclk1/Fclk0) + // + // Note : Update the tolerance and INTOSC2 frequency variance as necessary. + // + uint32_t total_error = ceil((2.0F * freq/10.0F) + (2.0F * 10.0F/freq) + 8.0F); + uint32_t window = total_error / 0.01F; + total_error += window * 0.1F; + + uint32_t count0 = window - total_error; + uint32_t valid = 2 * total_error; + uint32_t count1 = window * 10 / freq; + + EALLOW; + + // + // Enable DCC0 clock + // + CpuSysRegs.PCLKCR21.bit.DCC0 = 1; + + // + // Insert atleast 5 cycles delay after enabling the peripheral clock + // + asm(" RPT #5 || NOP"); + + // + // Clear Error & Done Flag + // + Dcc0Regs.DCCSTATUS.bit.ERR = 1; + Dcc0Regs.DCCSTATUS.bit.DONE = 1; + + // + // Disable DCC + // + Dcc0Regs.DCCGCTRL.bit.DCCENA = 0x5; + + // + // Disable Error Signal + // + Dcc0Regs.DCCGCTRL.bit.ERRENA = 0x5; + + // + // Disable Done Signal + // + Dcc0Regs.DCCGCTRL.bit.DONEENA = 0x5; + + // + // Configure Clock Source0 to XTAL + // + Dcc0Regs.DCCCLKSRC0.all = (0xA << 12) | // bits 12..15 : Key + 0; // bits 0..4 : Source = XTAL(value 0) + + // + // Configure Clock Source1 to INTOSC + // + Dcc0Regs.DCCCLKSRC1.all = (0xA << 12) | // bits 12..15 : Key + 3; // bits 0..4 : Source = INTOS2(value 3) + + // + // Configure COUNTER-0, COUNTER-1 & Valid Window + // + Dcc0Regs.DCCCNTSEED0.all = count0; + Dcc0Regs.DCCCNTSEED1.all = count1; + Dcc0Regs.DCCVALIDSEED0.all = valid; + + // + // Enable Single Shot mode + // + Dcc0Regs.DCCGCTRL.bit.SINGLESHOT = 0xA; + + // + // Enable Error Signal + // + Dcc0Regs.DCCGCTRL.bit.ERRENA = 0xA; + + // + // Enable Done Signal + // + Dcc0Regs.DCCGCTRL.bit.DONEENA = 0xA; + + // + // Enable DCC to start counting + // + Dcc0Regs.DCCGCTRL.bit.DCCENA = 0xA; + + EDIS; + + // + // Wait until Error or Done Flag is generated + // + while((Dcc0Regs.DCCSTATUS.bit.DONE | Dcc0Regs.DCCSTATUS.bit.ERR) == 0); + + // + // Returns true if DCC completes without error + // + if (Dcc0Regs.DCCSTATUS.bit.DONE == 1U) + { + return true; + } + else + { + return false; + } + +} +#endif + +// +// InitPeripheralClocks - Initializes the clocks for the peripherals. +// +// Note: In order to reduce power consumption, turn off the clocks to any +// peripheral that is not specified for your part-number or is not used in the +// application +// +void InitPeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.bit.CLA1 = 1; + CpuSysRegs.PCLKCR0.bit.DMA = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; + CpuSysRegs.PCLKCR0.bit.CPUBGCRC = 1; + CpuSysRegs.PCLKCR0.bit.CLA1BGCRC = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR0.bit.HRCAL = 1; +#endif + + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; + CpuSysRegs.PCLKCR0.bit.ERAD = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR1.bit.EMIF1 = 1; + CpuSysRegs.PCLKCR1.bit.EMIF2 = 1; +#endif + + CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM9 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM10 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM11 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM12 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM13 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM14 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM15 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM16 = 1; + + CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP7 = 1; + + CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP3 = 1; + + CpuSysRegs.PCLKCR6.bit.SD1 = 1; + CpuSysRegs.PCLKCR6.bit.SD2 = 1; + + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + CpuSysRegs.PCLKCR7.bit.SCI_B = 1; + CpuSysRegs.PCLKCR7.bit.SCI_C = 1; + CpuSysRegs.PCLKCR7.bit.SCI_D = 1; + + CpuSysRegs.PCLKCR8.bit.SPI_A = 1; + CpuSysRegs.PCLKCR8.bit.SPI_B = 1; + CpuSysRegs.PCLKCR8.bit.SPI_C = 1; + CpuSysRegs.PCLKCR8.bit.SPI_D = 1; + + CpuSysRegs.PCLKCR9.bit.I2C_A = 1; + CpuSysRegs.PCLKCR9.bit.I2C_B = 1; + + CpuSysRegs.PCLKCR10.bit.CAN_A = 1; + CpuSysRegs.PCLKCR10.bit.CAN_B = 1; + + CpuSysRegs.PCLKCR11.bit.McBSP_A = 1; + CpuSysRegs.PCLKCR11.bit.McBSP_B = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR11.bit.USB_A = 1; +#endif + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS8 = 1; + + CpuSysRegs.PCLKCR16.bit.DAC_A = 1; + CpuSysRegs.PCLKCR16.bit.DAC_B = 1; + CpuSysRegs.PCLKCR16.bit.DAC_C = 1; + + CpuSysRegs.PCLKCR18.bit.FSITX_A = 1; + CpuSysRegs.PCLKCR18.bit.FSITX_B = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_A = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_B = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_C = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_D = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_E = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_F = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_G = 1; + CpuSysRegs.PCLKCR18.bit.FSIRX_H = 1; + + CpuSysRegs.PCLKCR20.bit.PMBUS_A = 1; + + CpuSysRegs.PCLKCR21.bit.DCC0 = 1; + CpuSysRegs.PCLKCR21.bit.DCC1 = 1; + CpuSysRegs.PCLKCR21.bit.DCC2 = 1; + + CpuSysRegs.PCLKCR23.bit.ETHERCAT = 1; + + EDIS; +} + +// +// DisablePeripheralClocks - Gates-off all peripheral clocks. +// +void DisablePeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.all = 0; + CpuSysRegs.PCLKCR1.all = 0; + CpuSysRegs.PCLKCR2.all = 0; + CpuSysRegs.PCLKCR3.all = 0; + CpuSysRegs.PCLKCR4.all = 0; + CpuSysRegs.PCLKCR6.all = 0; + CpuSysRegs.PCLKCR7.all = 0; + CpuSysRegs.PCLKCR8.all = 0; + CpuSysRegs.PCLKCR9.all = 0; + CpuSysRegs.PCLKCR10.all = 0; + CpuSysRegs.PCLKCR11.all = 0; + CpuSysRegs.PCLKCR13.all = 0; + CpuSysRegs.PCLKCR14.all = 0; + CpuSysRegs.PCLKCR16.all = 0; + CpuSysRegs.PCLKCR18.all = 0; + CpuSysRegs.PCLKCR20.all = 0; + CpuSysRegs.PCLKCR21.all = 0; + CpuSysRegs.PCLKCR22.all = 0; + CpuSysRegs.PCLKCR23.all = 0; + + EDIS; +} + +// +// InitFlash - This function initializes the Flash Control registers. +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. +// +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void InitFlash(void) +{ + EALLOW; + + // + // At reset bank and pump are in sleep. A Flash access will power up the + // bank and pump automatically. + // + // Power up Flash bank and pump. This also sets the fall back mode of + // flash and pump as active. + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; + + // + // Disable Cache and prefetch mechanism before changing wait states + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; + + // + // Set waitstates according to frequency + // + // *CAUTION* + // Minimum waitstates required for the flash operating at a given CPU rate + // must be characterized by TI. Refer to the datasheet for the latest + // information. + // + #if CPU_FRQ_200MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3; + #endif + + #if CPU_FRQ_150MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + #if CPU_FRQ_120MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + // + // Enable Cache and prefetch mechanism to improve performance of code + // executed from Flash. + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; + + EDIS; + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + __asm(" RPT #7 || NOP"); +} + +// +// FlashOff - This function powers down the flash +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. Also you must seize the flash pump in +// order to power it down. +// +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void FlashOff(void) +{ + EALLOW; + + // + // Power down bank + // + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; + + // + // Power down pump + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; + + EDIS; +} + + +// +// ServiceDog - This function resets the watchdog timer. +// +// Enable this function for using ServiceDog in the application. +// +void ServiceDog(void) +{ + EALLOW; + WdRegs.WDKEY.bit.WDKEY = 0x0055; + WdRegs.WDKEY.bit.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void DisableDog(void) +{ + volatile Uint16 temp; + + // + // Grab the clock config first so we don't clobber it + // + EALLOW; + temp = WdRegs.WDCR.all & 0x0007; + WdRegs.WDCR.all = 0x0068 | temp; + EDIS; +} + +#ifdef CPU1 +// +// InitPll - This function initializes the PLL registers. +// +// Note: This function uses the DCC to check that the PLLRAWCLK is running at +// the expected rate. The desirable DCC can be provided as a parameter. +// +void InitSysPll(Uint16 clock_source, Uint16 imult, Uint32 refdiv, Uint32 odiv, + Uint16 divsel, Uint32 dccbase) +{ + Uint32 timeout,temp_syspllmult, pllLockStatus; + bool status; + + if(((clock_source & 0x3) == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && + (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE) && + (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && + (refdiv == ClkCfgRegs.SYSPLLMULT.bit.REFDIV) && + (odiv == ClkCfgRegs.SYSPLLMULT.bit.ODIV) && + (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + EALLOW; + + // + // First modify the PLL multipliers if the multipliers need an update or PLL needs + // to be powered on / enabled + // + if((imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT) || + (refdiv != ClkCfgRegs.SYSPLLMULT.bit.REFDIV)|| + (odiv != ClkCfgRegs.SYSPLLMULT.bit.ODIV) || + (1U != ClkCfgRegs.SYSPLLCTL1.bit.PLLEN)) + { + // + // Bypass PLL and set dividers to /1 + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + asm(" RPT #120 || NOP"); + + // + // Evaluate PLL multipliers and dividers + // + temp_syspllmult = ((refdiv << 24U) | (odiv << 16U)| imult); + + // + // Turnoff the PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + + // + // Delay of at least 66 OSCCLK cycles + // + asm(" RPT #66 || NOP"); + + if(((clock_source & 0x3) != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) || + (((clock_source & 0x4) >> 2) != ClkCfgRegs.XTALCR.bit.SE)) + { + switch (clock_source) + { + case INT_OSC1: + SysIntOsc1Sel(); + break; + + case INT_OSC2: + SysIntOsc2Sel(); + break; + + case XTAL_OSC: + SysXtalOscSel(); + break; + + case XTAL_OSC_SE: + SysXtalOscSESel(); + break; + } + } + + // + // Delay of at least 60 OSCCLK cycles + // + asm(" RPT #60 || NOP"); + + EALLOW; + + // + // Set dividers to /1 to ensure the fastest PLL configuration + // + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; + + // + // Program PLL multipliers + // + ClkCfgRegs.SYSPLLMULT.all = temp_syspllmult; + + // + // Enable SYSPLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; + + // + // Lock time is 1024 OSCCLK * (REFDIV+1) + // + timeout = (1024U * (refdiv + 1U)); + pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; + + // + // Wait for the SYSPLL lock + // + while((pllLockStatus != 1) && (timeout != 0U)) + { + pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; + timeout--; + } + + EDIS; + + // + // Check PLL Frequency using DCC + // + status = IsPLLValid(dccbase, clock_source, INT_PLL_SYSPLL, + imult, odiv , refdiv); + + } + else + { + // + // Re-Lock of PLL not needed since the multipliers + // are not updated + // + status = true; + } + + if(status) + { + EALLOW; + // + // Set divider to produce slower output frequency to limit current increase + // + if(divsel != PLLCLK_BY_126) + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; + } + else + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + } + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Small 100 cycle delay + // + asm(" RPT #100 || NOP"); + + // + // Set the divider to user value + // + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + EDIS; + } + else + ESTOP0; // If the frequency is out of range, stop here. + +} + +// +// InitAuxPll - This function initializes the AUXPLL registers. +// +// Note: This function uses the DCC to check that the AUXPLLRAWCLK is running at +// the expected rate. The desirable DCC can be provided as a parameter. +// +void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint32 refdiv, Uint32 odiv, + Uint16 divsel, Uint32 dccbase) +{ + Uint16 started = 0 , status = 0; + + if((clock_source == ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL) && + (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE) && + (imult == ClkCfgRegs.AUXPLLMULT.bit.IMULT) && + (refdiv == ClkCfgRegs.SYSPLLMULT.bit.REFDIV) && + (odiv == ClkCfgRegs.SYSPLLMULT.bit.ODIV) && + (divsel == ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + // + // First modify the PLL multipliers + // + if((imult != ClkCfgRegs.AUXPLLMULT.bit.IMULT) || + (refdiv != ClkCfgRegs.AUXPLLMULT.bit.REFDIV)|| + (odiv != ClkCfgRegs.AUXPLLMULT.bit.ODIV) || + (1U != ClkCfgRegs.AUXPLLCTL1.bit.PLLEN)) + { + EALLOW; + + // + // Bypass PLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + asm(" RPT #120 || NOP"); + + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; // Turn off AUXPLL + + // + // Delay of at least 66 OSCCLK cycles + // + asm(" RPT #66 || NOP"); + + // + // Configure oscillator source + // + switch (clock_source) + { + case INT_OSC2: + AuxIntOsc2Sel(); + break; + + case XTAL_OSC: + AuxXtalOscSel(); + break; + + case XTAL_OSC_SE: + AuxXtalOscSESel(); + break; + + case AUXCLKIN: + AuxAuxClkSel(); + break; + } + + // + // Delay of at least 60 OSCCLK cycles + // + asm(" RPT #60 || NOP"); + + EALLOW; + // + // Set integer multiplier and dividers, which automatically turns on + // the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((refdiv << 24U) | (odiv << 16U) | imult); + + // + // Enable AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + + status = IsPLLValid(dccbase, clock_source, INT_PLL_AUXPLL, + imult, odiv , refdiv); + + // + // Check DCC Status + // + if(status) + { + started = 1; + } + + // + // Enable AUXPLLCLK to be fed from AUX PLL + // + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + EDIS; + + if(started == 0) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass PLL). + // + EALLOW; + ClkCfgRegs.AUXPLLMULT.all = 0; + EDIS; + + // + // The user should put some handler code here based on how this + // condition should be handled in their application. + // + asm(" ESTOP0"); + } + } + + // + // Set divider to desired value + // + EALLOW; + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = divsel; + + EDIS; +} +#endif + +// +// CsmUnlock - This function unlocks the CSM. User must replace the default +// value with the current password for the DSP. +// +Uint16 CsmUnlock(void) +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. These values are + // default passwords for the first ZSB. User should replace them with + // the correct password for the DSP. + // + EALLOW; + DcsmZ1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY1 = 0x4D7FFFFF; + DcsmZ1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; + + DcsmZ2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY1 = 0x3FFFFFFF; + DcsmZ2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; + EDIS; + + return(0); +} + +// +// SysIntOsc1Sel - This function switches to Internal Oscillator 1. +// +void SysIntOsc1Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + EDIS; +} + +// +// SysIntOsc2Sel - This function switches to Internal oscillator 2. +// +void SysIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + EDIS; +} + +// +// PollX1Counter - Clear the X1CNT counter and then wait for it to saturate +// four times. +// +static void +PollX1Counter(void) +{ + Uint16 loopCount = 0; + + // + // Delay for 1 ms while the XTAL powers up + // + // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles + // + F28x_usDelay(2000); + + // + // Clear and saturate X1CNT 4 times to guarantee operation + // + do + { + // + // Keep clearing the counter until it is no longer saturated + // + while(ClkCfgRegs.X1CNT.all > 0x1FF) + { + ClkCfgRegs.X1CNT.bit.CLR = 1; + ClkCfgRegs.X1CNT.bit.CLR = 0; + } + + // + // Wait for the X1 clock to saturate + // + while(ClkCfgRegs.X1CNT.all != 0x3FFU) + { + ; + } + + // + // Increment the counter + // + loopCount++; + }while(loopCount < 4); +} +// SysXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void SysXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC + ClkCfgRegs.XTALCR.bit.SE = 0; // Select crystal mode + EDIS; + + // + // Wait for the X1 clock to saturate + // + PollX1Counter(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; + EDIS; + + // + // If a missing clock failure was detected, try waiting for the X1 counter + // to saturate again. Consider modifying this code to add a 10ms timeout. + // + while(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) + { + EALLOW; + ClkCfgRegs.MCDCR.bit.MCLKCLR = 1; + EDIS; + + // + // Wait for the X1 clock to saturate + // + PollX1Counter(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; + EDIS; + } +} +// +// SysXtalOscSESel - This function switches to external oscillator in +// single-ended mode and turns off all other clock sources to minimize power +// consumption. This option may not be available on all device packages +// +void +SysXtalOscSESel (void) +{ + EALLOW; + ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC + ClkCfgRegs.XTALCR.bit.SE = 1; // Select single-ended mode + EDIS; + + // + // Wait for the X1 clock to saturate + // + PollX1Counter(); + + // + // Select XTALOSC as the oscillator source + // + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; + EDIS; + + // + // If missing clock detected, there is something wrong with the oscillator + // module. + // + if(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) + { + ESTOP0; + } +} +// +// AuxIntOsc2Sel - This function switches to Internal oscillator 2. +// +void AuxIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + EDIS; +} + +// +// AuxXtalOscSel - This function switches to External CRYSTAL oscillator in +// crystal mode. +// +void AuxXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.XTALCR.bit.SE = 0; // Select crystal mode + PollX1Counter(); // Wait for the X1 clock to saturate + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxXtalOscSESel - This function switches to External CRYSTAL oscillator in +// single-ended mode. +// +void AuxXtalOscSESel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.XTALCR.bit.SE = 1; // Select single-ended mode + PollX1Counter(); // Wait for the X1 clock to saturate + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} +// +// AuxAuxClkSel - This function switches to AUXCLKIN (from a GPIO). +// +void AuxAuxClkSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = XTAL + EDIS; +} + +// +// IDLE - Enter IDLE mode (single CPU). +// +void IDLE(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; + EDIS; + asm(" IDLE"); +} + +// +// STANDBY - Enter STANDBY mode (single CPU). +// +void STANDBY(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_STANDBY; + EDIS; + asm(" IDLE"); +} + +#ifdef CPU1 +// +// IsPLLValid - This function validates PLL Raw Clock Frequency +// +bool +IsPLLValid(Uint32 base, Uint16 oscSource, Uint16 pllclk, Uint16 imult, + Uint16 odiv, Uint16 refdiv) +{ + float fclk1_0ratio; + volatile struct DCC_REGS *DccRegs; + + EALLOW; + + // + // Assigning DCC for PLL validation + // Enable Peripheral Clock Domain PCLKCR21 for DCC + // + if(base == SYSCTL_DCC_BASE0) + { + DccRegs = &Dcc0Regs; + CpuSysRegs.PCLKCR21.bit.DCC0 = 1; + } + else if(base == SYSCTL_DCC_BASE1) + { + DccRegs = &Dcc1Regs; + CpuSysRegs.PCLKCR21.bit.DCC1 = 1; + } + else if(base == SYSCTL_DCC_BASE2) + { + DccRegs = &Dcc2Regs; + CpuSysRegs.PCLKCR21.bit.DCC2 = 1; + } + else + ESTOP0; // Invalid DCC selected + + // + // Clear Error & Done Flag + // + DccRegs->DCCSTATUS.bit.ERR = 1; + DccRegs->DCCSTATUS.bit.DONE = 1; + + // + // Disable DCC + // + DccRegs->DCCGCTRL.bit.DCCENA = 0x5; + + // + // Disable Error Signal + // + DccRegs->DCCGCTRL.bit.ERRENA = 0x5; + + // + // Disable Done Signal + // + DccRegs->DCCGCTRL.bit.DONEENA = 0x5; + + // + // Configure Clock Source1 to PLL + // + // Clk Src1 Key 0xA to enable clock source selection + // + switch(pllclk) + { + case INT_PLL_SYSPLL: + DccRegs->DCCCLKSRC1.all = 0xA000; // Clk Src1 = SYSPLL + break; + + case INT_PLL_AUXPLL: + DccRegs->DCCCLKSRC1.all = 0xA001; // Clk Src1 = AUXPLL + break; + + default: + // + // Code shouldn't reach here + // + break; + } + + // + // Configure Clock Source0 to whatever is set as a reference + // clock source for PLL + // + // Clk Src0 Key 0xA to enable clock source selection + // + switch(oscSource) + { + case INT_OSC1: + DccRegs->DCCCLKSRC0.all = 0xA001; // Clk Src0 = INTOSC1 + break; + + case INT_OSC2: + DccRegs->DCCCLKSRC0.all = 0xA002; // Clk Src0 = INTOSC2 + break; + + case XTAL_OSC: + case XTAL_OSC_SE: + DccRegs->DCCCLKSRC0.all = 0xA000; // Clk Src0 = XTAL + break; + + default: + // + // Code shouldn't reach here + // + break; + } + + // + // Calculating frequency ratio of output clock(f1) vs reference clock(f0) + // + fclk1_0ratio = (float)imult / ((odiv + 1U) * (refdiv + 1)); + + // + // Computing and configuring Counter0 , Counter1 & Valid Seed Values + // with +/-1% tolerance for the desired DCC + // + ComputeCntrSeedValue(base, fclk1_0ratio, DCC_COUNTER0_TOLERANCE); + + // + // Enable Single Shot Mode + // + DccRegs->DCCGCTRL.bit.SINGLESHOT = 0xA; + + // + // Enable DCC to start counting + // + DccRegs->DCCGCTRL.bit.DCCENA = 0xA; + EDIS; + + // + // Wait until Error or Done Flag is generated + // + while((DccRegs->DCCSTATUS.all & 3) == 0) + { + } + + // + // Returns true if DCC completes without error + // + return((DccRegs->DCCSTATUS.all & 3) == 2); + +} + +//***************************************************************************** +// +// ComputeCntSeedValid - Compute Counter seed values based on the frequency ratio of output +// clock vs reference clock & tolerance expected for the desired DCC +// +//***************************************************************************** +void ComputeCntrSeedValue(Uint32 base, float fclk1_0ratio, Uint32 tolerance) +{ + Uint32 window, dccCounterSeed0, dccValidSeed0, dccCounterSeed1, total_error; + volatile struct DCC_REGS *DccRegs; + + if(fclk1_0ratio >= 1U) + { + // + // Setting Counter0 & Valid Seed Value with expected tolerance + // Total error is 12 + // + window = (12U * 100U) / tolerance; + dccCounterSeed0 = window - 12U; + dccValidSeed0 = 24U; + + } + else + { + total_error = (((Uint32)2U / fclk1_0ratio) + (Uint32)10U); + + window = ((total_error * 100U)/ tolerance); + + // + // Setting Counter0 & Valid Seed Value with expected tolerance + // + dccCounterSeed0 = window - total_error; + dccValidSeed0 = (Uint32)2U * total_error; + + } + + // + // Multiplying Counter-0 window with PLL Integer Multiplier + // + dccCounterSeed1 = window * fclk1_0ratio; + + // + // Assigning DCC for PLL validation + // + if(base == SYSCTL_DCC_BASE0) + DccRegs = &Dcc0Regs; + else if(base == SYSCTL_DCC_BASE1) + DccRegs = &Dcc1Regs; + else if(base == SYSCTL_DCC_BASE2) + DccRegs = &Dcc2Regs; + else + ESTOP0; // Invalid DCC selected + + // + // Configure COUNTER-0, COUNTER-1 & Valid Window + // + DccRegs->DCCCNTSEED0.bit.COUNTSEED0 = dccCounterSeed0; // Loaded Counter0 Value + DccRegs->DCCVALIDSEED0.bit.VALIDSEED = dccValidSeed0; // Loaded Valid Value + DccRegs->DCCCNTSEED1.bit.COUNTSEED1 = dccCounterSeed1; // Loaded Counter1 Value +} +#endif + +// +// End of File +// + diff --git a/i2c_ex1_master/f2838x_usdelay.asm b/i2c_ex1_master/f2838x_usdelay.asm new file mode 100644 index 0000000..a29cb5c --- /dev/null +++ b/i2c_ex1_master/f2838x_usdelay.asm @@ -0,0 +1,108 @@ +;//########################################################################### +;// +;// FILE: f2838x_usdelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// To use this function: +;// 1 - update the CPU clock speed in the f2838x_examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the f2838x_device.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// extern void Delay(long LoopCount); +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// Or as follows (if count is less then 16-bits): +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;//########################################################################### +;// +;// +;// $Copyright: +;// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + + .if __TI_EABI__ + .asg F28x_usDelay, _F28x_usDelay + .endif + .def _F28x_usDelay + + .cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro + %{ + %} + + .if __TI_COMPILER_VERSION__ + .if __TI_COMPILER_VERSION__ >= 15009000 + .sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer + .else + .sect "ramfuncs" ;;Used with compilers older than v15.9.0 + .endif + .endif + + .global __F28x_usDelay +_F28x_usDelay: + SUB ACC,#1 + BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +; + +;// +;// End of file +;// diff --git a/i2c_ex1_master/fonts.c b/i2c_ex1_master/fonts.c new file mode 100644 index 0000000..78b2b66 --- /dev/null +++ b/i2c_ex1_master/fonts.c @@ -0,0 +1,345 @@ +/** + * original author: Tilen Majerle + * modification for STM32f10x: Alexander Lutsai + + ---------------------------------------------------------------------- + Copyright (C) Alexander Lutsai, 2016 + Copyright (C) Tilen Majerle, 2015 + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + ---------------------------------------------------------------------- + */ +#include "fonts.h" + +const uint16_t Font7x10 [] = { +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // sp +0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x0000, 0x0000, // ! +0x2800, 0x2800, 0x2800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // " +0x2400, 0x2400, 0x7C00, 0x2400, 0x4800, 0x7C00, 0x4800, 0x4800, 0x0000, 0x0000, // # +0x3800, 0x5400, 0x5000, 0x3800, 0x1400, 0x5400, 0x5400, 0x3800, 0x1000, 0x0000, // $ +0x2000, 0x5400, 0x5800, 0x3000, 0x2800, 0x5400, 0x1400, 0x0800, 0x0000, 0x0000, // % +0x1000, 0x2800, 0x2800, 0x1000, 0x3400, 0x4800, 0x4800, 0x3400, 0x0000, 0x0000, // & +0x1000, 0x1000, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ' +0x0800, 0x1000, 0x2000, 0x2000, 0x2000, 0x2000, 0x2000, 0x2000, 0x1000, 0x0800, // ( +0x2000, 0x1000, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x1000, 0x2000, // ) +0x1000, 0x3800, 0x1000, 0x2800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // * +0x0000, 0x0000, 0x1000, 0x1000, 0x7C00, 0x1000, 0x1000, 0x0000, 0x0000, 0x0000, // + +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1000, 0x1000, 0x1000, // , +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3800, 0x0000, 0x0000, 0x0000, 0x0000, // - +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, // . +0x0800, 0x0800, 0x1000, 0x1000, 0x1000, 0x1000, 0x2000, 0x2000, 0x0000, 0x0000, // / +0x3800, 0x4400, 0x4400, 0x5400, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // 0 +0x1000, 0x3000, 0x5000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // 1 +0x3800, 0x4400, 0x4400, 0x0400, 0x0800, 0x1000, 0x2000, 0x7C00, 0x0000, 0x0000, // 2 +0x3800, 0x4400, 0x0400, 0x1800, 0x0400, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // 3 +0x0800, 0x1800, 0x2800, 0x2800, 0x4800, 0x7C00, 0x0800, 0x0800, 0x0000, 0x0000, // 4 +0x7C00, 0x4000, 0x4000, 0x7800, 0x0400, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // 5 +0x3800, 0x4400, 0x4000, 0x7800, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // 6 +0x7C00, 0x0400, 0x0800, 0x1000, 0x1000, 0x2000, 0x2000, 0x2000, 0x0000, 0x0000, // 7 +0x3800, 0x4400, 0x4400, 0x3800, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // 8 +0x3800, 0x4400, 0x4400, 0x4400, 0x3C00, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // 9 +0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, // : +0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, 0x1000, 0x1000, 0x1000, // ; +0x0000, 0x0000, 0x0C00, 0x3000, 0x4000, 0x3000, 0x0C00, 0x0000, 0x0000, 0x0000, // < +0x0000, 0x0000, 0x0000, 0x7C00, 0x0000, 0x7C00, 0x0000, 0x0000, 0x0000, 0x0000, // = +0x0000, 0x0000, 0x6000, 0x1800, 0x0400, 0x1800, 0x6000, 0x0000, 0x0000, 0x0000, // > +0x3800, 0x4400, 0x0400, 0x0800, 0x1000, 0x1000, 0x0000, 0x1000, 0x0000, 0x0000, // ? +0x3800, 0x4400, 0x4C00, 0x5400, 0x5C00, 0x4000, 0x4000, 0x3800, 0x0000, 0x0000, // @ +0x1000, 0x2800, 0x2800, 0x2800, 0x2800, 0x7C00, 0x4400, 0x4400, 0x0000, 0x0000, // A +0x7800, 0x4400, 0x4400, 0x7800, 0x4400, 0x4400, 0x4400, 0x7800, 0x0000, 0x0000, // B +0x3800, 0x4400, 0x4000, 0x4000, 0x4000, 0x4000, 0x4400, 0x3800, 0x0000, 0x0000, // C +0x7000, 0x4800, 0x4400, 0x4400, 0x4400, 0x4400, 0x4800, 0x7000, 0x0000, 0x0000, // D +0x7C00, 0x4000, 0x4000, 0x7C00, 0x4000, 0x4000, 0x4000, 0x7C00, 0x0000, 0x0000, // E +0x7C00, 0x4000, 0x4000, 0x7800, 0x4000, 0x4000, 0x4000, 0x4000, 0x0000, 0x0000, // F +0x3800, 0x4400, 0x4000, 0x4000, 0x5C00, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // G +0x4400, 0x4400, 0x4400, 0x7C00, 0x4400, 0x4400, 0x4400, 0x4400, 0x0000, 0x0000, // H +0x3800, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x3800, 0x0000, 0x0000, // I +0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // J +0x4400, 0x4800, 0x5000, 0x6000, 0x5000, 0x4800, 0x4800, 0x4400, 0x0000, 0x0000, // K +0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x7C00, 0x0000, 0x0000, // L +0x4400, 0x6C00, 0x6C00, 0x5400, 0x4400, 0x4400, 0x4400, 0x4400, 0x0000, 0x0000, // M +0x4400, 0x6400, 0x6400, 0x5400, 0x5400, 0x4C00, 0x4C00, 0x4400, 0x0000, 0x0000, // N +0x3800, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // O +0x7800, 0x4400, 0x4400, 0x4400, 0x7800, 0x4000, 0x4000, 0x4000, 0x0000, 0x0000, // P +0x3800, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x5400, 0x3800, 0x0400, 0x0000, // Q +0x7800, 0x4400, 0x4400, 0x4400, 0x7800, 0x4800, 0x4800, 0x4400, 0x0000, 0x0000, // R +0x3800, 0x4400, 0x4000, 0x3000, 0x0800, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // S +0x7C00, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // T +0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // U +0x4400, 0x4400, 0x4400, 0x2800, 0x2800, 0x2800, 0x1000, 0x1000, 0x0000, 0x0000, // V +0x4400, 0x4400, 0x5400, 0x5400, 0x5400, 0x6C00, 0x2800, 0x2800, 0x0000, 0x0000, // W +0x4400, 0x2800, 0x2800, 0x1000, 0x1000, 0x2800, 0x2800, 0x4400, 0x0000, 0x0000, // X +0x4400, 0x4400, 0x2800, 0x2800, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // Y +0x7C00, 0x0400, 0x0800, 0x1000, 0x1000, 0x2000, 0x4000, 0x7C00, 0x0000, 0x0000, // Z +0x1800, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1800, // [ +0x2000, 0x2000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0800, 0x0800, 0x0000, 0x0000, /* \ */ +0x3000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x3000, // ] +0x1000, 0x2800, 0x2800, 0x4400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ^ +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xFE00, // _ +0x2000, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ` +0x0000, 0x0000, 0x3800, 0x4400, 0x3C00, 0x4400, 0x4C00, 0x3400, 0x0000, 0x0000, // a +0x4000, 0x4000, 0x5800, 0x6400, 0x4400, 0x4400, 0x6400, 0x5800, 0x0000, 0x0000, // b +0x0000, 0x0000, 0x3800, 0x4400, 0x4000, 0x4000, 0x4400, 0x3800, 0x0000, 0x0000, // c +0x0400, 0x0400, 0x3400, 0x4C00, 0x4400, 0x4400, 0x4C00, 0x3400, 0x0000, 0x0000, // d +0x0000, 0x0000, 0x3800, 0x4400, 0x7C00, 0x4000, 0x4400, 0x3800, 0x0000, 0x0000, // e +0x0C00, 0x1000, 0x7C00, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // f +0x0000, 0x0000, 0x3400, 0x4C00, 0x4400, 0x4400, 0x4C00, 0x3400, 0x0400, 0x7800, // g +0x4000, 0x4000, 0x5800, 0x6400, 0x4400, 0x4400, 0x4400, 0x4400, 0x0000, 0x0000, // h +0x1000, 0x0000, 0x7000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // i +0x1000, 0x0000, 0x7000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0xE000, // j +0x4000, 0x4000, 0x4800, 0x5000, 0x6000, 0x5000, 0x4800, 0x4400, 0x0000, 0x0000, // k +0x7000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // l +0x0000, 0x0000, 0x7800, 0x5400, 0x5400, 0x5400, 0x5400, 0x5400, 0x0000, 0x0000, // m +0x0000, 0x0000, 0x5800, 0x6400, 0x4400, 0x4400, 0x4400, 0x4400, 0x0000, 0x0000, // n +0x0000, 0x0000, 0x3800, 0x4400, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // o +0x0000, 0x0000, 0x5800, 0x6400, 0x4400, 0x4400, 0x6400, 0x5800, 0x4000, 0x4000, // p +0x0000, 0x0000, 0x3400, 0x4C00, 0x4400, 0x4400, 0x4C00, 0x3400, 0x0400, 0x0400, // q +0x0000, 0x0000, 0x5800, 0x6400, 0x4000, 0x4000, 0x4000, 0x4000, 0x0000, 0x0000, // r +0x0000, 0x0000, 0x3800, 0x4400, 0x3000, 0x0800, 0x4400, 0x3800, 0x0000, 0x0000, // s +0x2000, 0x2000, 0x7800, 0x2000, 0x2000, 0x2000, 0x2000, 0x1800, 0x0000, 0x0000, // t +0x0000, 0x0000, 0x4400, 0x4400, 0x4400, 0x4400, 0x4C00, 0x3400, 0x0000, 0x0000, // u +0x0000, 0x0000, 0x4400, 0x4400, 0x2800, 0x2800, 0x2800, 0x1000, 0x0000, 0x0000, // v +0x0000, 0x0000, 0x5400, 0x5400, 0x5400, 0x6C00, 0x2800, 0x2800, 0x0000, 0x0000, // w +0x0000, 0x0000, 0x4400, 0x2800, 0x1000, 0x1000, 0x2800, 0x4400, 0x0000, 0x0000, // x +0x0000, 0x0000, 0x4400, 0x4400, 0x2800, 0x2800, 0x1000, 0x1000, 0x1000, 0x6000, // y +0x0000, 0x0000, 0x7C00, 0x0800, 0x1000, 0x2000, 0x4000, 0x7C00, 0x0000, 0x0000, // z +0x1800, 0x1000, 0x1000, 0x1000, 0x2000, 0x2000, 0x1000, 0x1000, 0x1000, 0x1800, // { +0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, // | +0x3000, 0x1000, 0x1000, 0x1000, 0x0800, 0x0800, 0x1000, 0x1000, 0x1000, 0x3000, // } +0x0000, 0x0000, 0x0000, 0x7400, 0x4C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ~ +}; +/* +const uint16_t Font11x18 [] = { +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // sp +0x0000, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // ! +0x0000, 0x1B00, 0x1B00, 0x1B00, 0x1B00, 0x1B00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // " +0x0000, 0x1980, 0x1980, 0x1980, 0x1980, 0x7FC0, 0x7FC0, 0x1980, 0x3300, 0x7FC0, 0x7FC0, 0x3300, 0x3300, 0x3300, 0x3300, 0x0000, 0x0000, 0x0000, // # +0x0000, 0x1E00, 0x3F00, 0x7580, 0x6580, 0x7400, 0x3C00, 0x1E00, 0x0700, 0x0580, 0x6580, 0x6580, 0x7580, 0x3F00, 0x1E00, 0x0400, 0x0400, 0x0000, // $ +0x0000, 0x7000, 0xD800, 0xD840, 0xD8C0, 0xD980, 0x7300, 0x0600, 0x0C00, 0x1B80, 0x36C0, 0x66C0, 0x46C0, 0x06C0, 0x0380, 0x0000, 0x0000, 0x0000, // % +0x0000, 0x1E00, 0x3F00, 0x3300, 0x3300, 0x3300, 0x1E00, 0x0C00, 0x3CC0, 0x66C0, 0x6380, 0x6180, 0x6380, 0x3EC0, 0x1C80, 0x0000, 0x0000, 0x0000, // & +0x0000, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ' +0x0080, 0x0100, 0x0300, 0x0600, 0x0600, 0x0400, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0400, 0x0600, 0x0600, 0x0300, 0x0100, 0x0080, // ( +0x2000, 0x1000, 0x1800, 0x0C00, 0x0C00, 0x0400, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0400, 0x0C00, 0x0C00, 0x1800, 0x1000, 0x2000, // ) +0x0000, 0x0C00, 0x2D00, 0x3F00, 0x1E00, 0x3300, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // * +0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0xFFC0, 0xFFC0, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // + +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0400, 0x0400, 0x0800, // , +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x1E00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // - +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // . +0x0000, 0x0300, 0x0300, 0x0300, 0x0600, 0x0600, 0x0600, 0x0600, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x1800, 0x1800, 0x1800, 0x0000, 0x0000, 0x0000, // / +0x0000, 0x1E00, 0x3F00, 0x3300, 0x6180, 0x6180, 0x6180, 0x6D80, 0x6D80, 0x6180, 0x6180, 0x6180, 0x3300, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 0 +0x0000, 0x0600, 0x0E00, 0x1E00, 0x3600, 0x2600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, // 1 +0x0000, 0x1E00, 0x3F00, 0x7380, 0x6180, 0x6180, 0x0180, 0x0300, 0x0600, 0x0C00, 0x1800, 0x3000, 0x6000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, // 2 +0x0000, 0x1C00, 0x3E00, 0x6300, 0x6300, 0x0300, 0x0E00, 0x0E00, 0x0300, 0x0180, 0x0180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 3 +0x0000, 0x0600, 0x0E00, 0x0E00, 0x1E00, 0x1E00, 0x1600, 0x3600, 0x3600, 0x6600, 0x7F80, 0x7F80, 0x0600, 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, // 4 +0x0000, 0x7F00, 0x7F00, 0x6000, 0x6000, 0x6000, 0x6E00, 0x7F00, 0x6380, 0x0180, 0x0180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 5 +0x0000, 0x1E00, 0x3F00, 0x3380, 0x6180, 0x6000, 0x6E00, 0x7F00, 0x7380, 0x6180, 0x6180, 0x6180, 0x3380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 6 +0x0000, 0x7F80, 0x7F80, 0x0180, 0x0300, 0x0300, 0x0600, 0x0600, 0x0C00, 0x0C00, 0x0C00, 0x0800, 0x1800, 0x1800, 0x1800, 0x0000, 0x0000, 0x0000, // 7 +0x0000, 0x1E00, 0x3F00, 0x6380, 0x6180, 0x6180, 0x2100, 0x1E00, 0x3F00, 0x6180, 0x6180, 0x6180, 0x6180, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 8 +0x0000, 0x1E00, 0x3F00, 0x7300, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F80, 0x1D80, 0x0180, 0x6180, 0x7300, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 9 +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // : +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0400, 0x0400, 0x0800, // ; +0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0380, 0x0E00, 0x3800, 0x6000, 0x3800, 0x0E00, 0x0380, 0x0080, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // < +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // = +0x0000, 0x0000, 0x0000, 0x0000, 0x4000, 0x7000, 0x1C00, 0x0700, 0x0180, 0x0700, 0x1C00, 0x7000, 0x4000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // > +0x0000, 0x1F00, 0x3F80, 0x71C0, 0x60C0, 0x00C0, 0x01C0, 0x0380, 0x0700, 0x0E00, 0x0C00, 0x0C00, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // ? +0x0000, 0x1E00, 0x3F00, 0x3180, 0x7180, 0x6380, 0x6F80, 0x6D80, 0x6D80, 0x6F80, 0x6780, 0x6000, 0x3200, 0x3E00, 0x1C00, 0x0000, 0x0000, 0x0000, // @ +0x0000, 0x0E00, 0x0E00, 0x1B00, 0x1B00, 0x1B00, 0x1B00, 0x3180, 0x3180, 0x3F80, 0x3F80, 0x3180, 0x60C0, 0x60C0, 0x60C0, 0x0000, 0x0000, 0x0000, // A +0x0000, 0x7C00, 0x7E00, 0x6300, 0x6300, 0x6300, 0x6300, 0x7E00, 0x7E00, 0x6300, 0x6180, 0x6180, 0x6380, 0x7F00, 0x7E00, 0x0000, 0x0000, 0x0000, // B +0x0000, 0x1E00, 0x3F00, 0x3180, 0x6180, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6180, 0x3180, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // C +0x0000, 0x7C00, 0x7F00, 0x6300, 0x6380, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6300, 0x6300, 0x7E00, 0x7C00, 0x0000, 0x0000, 0x0000, // D +0x0000, 0x7F80, 0x7F80, 0x6000, 0x6000, 0x6000, 0x6000, 0x7F00, 0x7F00, 0x6000, 0x6000, 0x6000, 0x6000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, // E +0x0000, 0x7F80, 0x7F80, 0x6000, 0x6000, 0x6000, 0x6000, 0x7F00, 0x7F00, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x0000, 0x0000, 0x0000, // F +0x0000, 0x1E00, 0x3F00, 0x3180, 0x6180, 0x6000, 0x6000, 0x6000, 0x6380, 0x6380, 0x6180, 0x6180, 0x3180, 0x3F80, 0x1E00, 0x0000, 0x0000, 0x0000, // G +0x0000, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x7F80, 0x7F80, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, // H +0x0000, 0x3F00, 0x3F00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x3F00, 0x3F00, 0x0000, 0x0000, 0x0000, // I +0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x6180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // J +0x0000, 0x60C0, 0x6180, 0x6300, 0x6600, 0x6600, 0x6C00, 0x7800, 0x7C00, 0x6600, 0x6600, 0x6300, 0x6180, 0x6180, 0x60C0, 0x0000, 0x0000, 0x0000, // K +0x0000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, // L +0x0000, 0x71C0, 0x71C0, 0x7BC0, 0x7AC0, 0x6AC0, 0x6AC0, 0x6EC0, 0x64C0, 0x60C0, 0x60C0, 0x60C0, 0x60C0, 0x60C0, 0x60C0, 0x0000, 0x0000, 0x0000, // M +0x0000, 0x7180, 0x7180, 0x7980, 0x7980, 0x7980, 0x6D80, 0x6D80, 0x6D80, 0x6580, 0x6780, 0x6780, 0x6780, 0x6380, 0x6380, 0x0000, 0x0000, 0x0000, // N +0x0000, 0x1E00, 0x3F00, 0x3300, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x3300, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // O +0x0000, 0x7E00, 0x7F00, 0x6380, 0x6180, 0x6180, 0x6180, 0x6380, 0x7F00, 0x7E00, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x0000, 0x0000, 0x0000, // P +0x0000, 0x1E00, 0x3F00, 0x3300, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6580, 0x6780, 0x3300, 0x3F80, 0x1E40, 0x0000, 0x0000, 0x0000, // Q +0x0000, 0x7E00, 0x7F00, 0x6380, 0x6180, 0x6180, 0x6380, 0x7F00, 0x7E00, 0x6600, 0x6300, 0x6300, 0x6180, 0x6180, 0x60C0, 0x0000, 0x0000, 0x0000, // R +0x0000, 0x0E00, 0x1F00, 0x3180, 0x3180, 0x3000, 0x3800, 0x1E00, 0x0700, 0x0380, 0x6180, 0x6180, 0x3180, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // S +0x0000, 0xFFC0, 0xFFC0, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // T +0x0000, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // U +0x0000, 0x60C0, 0x60C0, 0x60C0, 0x3180, 0x3180, 0x3180, 0x1B00, 0x1B00, 0x1B00, 0x1B00, 0x0E00, 0x0E00, 0x0E00, 0x0400, 0x0000, 0x0000, 0x0000, // V +0x0000, 0xC0C0, 0xC0C0, 0xC0C0, 0xC0C0, 0xC0C0, 0xCCC0, 0x4C80, 0x4C80, 0x5E80, 0x5280, 0x5280, 0x7380, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, // W +0x0000, 0xC0C0, 0x6080, 0x6180, 0x3300, 0x3B00, 0x1E00, 0x0C00, 0x0C00, 0x1E00, 0x1F00, 0x3B00, 0x7180, 0x6180, 0xC0C0, 0x0000, 0x0000, 0x0000, // X +0x0000, 0xC0C0, 0x6180, 0x6180, 0x3300, 0x3300, 0x1E00, 0x1E00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // Y +0x0000, 0x3F80, 0x3F80, 0x0180, 0x0300, 0x0300, 0x0600, 0x0C00, 0x0C00, 0x1800, 0x1800, 0x3000, 0x6000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, // Z +0x0F00, 0x0F00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0F00, 0x0F00, // [ +0x0000, 0x1800, 0x1800, 0x1800, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, 0x0300, 0x0000, 0x0000, 0x0000, /* \ +0x1E00, 0x1E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x1E00, 0x1E00, // ] +0x0000, 0x0C00, 0x0C00, 0x1E00, 0x1200, 0x3300, 0x3300, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ^ +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xFFE0, 0x0000, // _ +0x0000, 0x3800, 0x1800, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ` +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1F00, 0x3F80, 0x6180, 0x0180, 0x1F80, 0x3F80, 0x6180, 0x6380, 0x7F80, 0x38C0, 0x0000, 0x0000, 0x0000, // a +0x0000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6E00, 0x7F00, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x7F00, 0x6E00, 0x0000, 0x0000, 0x0000, // b +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x3F00, 0x7380, 0x6180, 0x6000, 0x6000, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // c +0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x1D80, 0x3F80, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F80, 0x1D80, 0x0000, 0x0000, 0x0000, // d +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x3F00, 0x7300, 0x6180, 0x7F80, 0x7F80, 0x6000, 0x7180, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // e +0x0000, 0x07C0, 0x0FC0, 0x0C00, 0x0C00, 0x7F80, 0x7F80, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // f +0x0000, 0x0000, 0x0000, 0x0000, 0x1D80, 0x3F80, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F80, 0x1D80, 0x0180, 0x6380, 0x7F00, 0x3E00, // g +0x0000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6F00, 0x7F80, 0x7180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, // h +0x0000, 0x0600, 0x0600, 0x0000, 0x0000, 0x3E00, 0x3E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, // i +0x0600, 0x0600, 0x0000, 0x0000, 0x3E00, 0x3E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x4600, 0x7E00, 0x3C00, // j +0x0000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6180, 0x6300, 0x6600, 0x6C00, 0x7C00, 0x7600, 0x6300, 0x6300, 0x6180, 0x60C0, 0x0000, 0x0000, 0x0000, // k +0x0000, 0x3E00, 0x3E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, // l +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xDD80, 0xFFC0, 0xCEC0, 0xCCC0, 0xCCC0, 0xCCC0, 0xCCC0, 0xCCC0, 0xCCC0, 0xCCC0, 0x0000, 0x0000, 0x0000, // m +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6F00, 0x7F80, 0x7180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, // n +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x3F00, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // o +0x0000, 0x0000, 0x0000, 0x0000, 0x6E00, 0x7F00, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x7F00, 0x6E00, 0x6000, 0x6000, 0x6000, 0x6000, // p +0x0000, 0x0000, 0x0000, 0x0000, 0x1D80, 0x3F80, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F80, 0x1D80, 0x0180, 0x0180, 0x0180, 0x0180, // q +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6700, 0x3F80, 0x3900, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x0000, 0x0000, 0x0000, // r +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x3F80, 0x6180, 0x6000, 0x7F00, 0x3F80, 0x0180, 0x6180, 0x7F00, 0x1E00, 0x0000, 0x0000, 0x0000, // s +0x0000, 0x0000, 0x0800, 0x1800, 0x1800, 0x7F00, 0x7F00, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1F80, 0x0F80, 0x0000, 0x0000, 0x0000, // t +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6380, 0x7F80, 0x3D80, 0x0000, 0x0000, 0x0000, // u +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x60C0, 0x3180, 0x3180, 0x3180, 0x1B00, 0x1B00, 0x1B00, 0x0E00, 0x0E00, 0x0600, 0x0000, 0x0000, 0x0000, // v +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xDD80, 0xDD80, 0xDD80, 0x5500, 0x5500, 0x5500, 0x7700, 0x7700, 0x2200, 0x2200, 0x0000, 0x0000, 0x0000, // w +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6180, 0x3300, 0x3300, 0x1E00, 0x0C00, 0x0C00, 0x1E00, 0x3300, 0x3300, 0x6180, 0x0000, 0x0000, 0x0000, // x +0x0000, 0x0000, 0x0000, 0x0000, 0x6180, 0x6180, 0x3180, 0x3300, 0x3300, 0x1B00, 0x1B00, 0x1B00, 0x0E00, 0x0E00, 0x0E00, 0x1C00, 0x7C00, 0x7000, // y +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x7FC0, 0x7FC0, 0x0180, 0x0300, 0x0600, 0x0C00, 0x1800, 0x3000, 0x7FC0, 0x7FC0, 0x0000, 0x0000, 0x0000, // z +0x0380, 0x0780, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0E00, 0x1C00, 0x1C00, 0x0E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0780, 0x0380, // { +0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, // | +0x3800, 0x3C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0E00, 0x0700, 0x0700, 0x0E00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x3C00, 0x3800, // } +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3880, 0x7F80, 0x4700, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ~ +}; + +const uint16_t Font16x26 [] = { +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [ ] +0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03C0,0x03C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [!] +0x1E3C,0x1E3C,0x1E3C,0x1E3C,0x1E3C,0x1E3C,0x1E3C,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = ["] +0x01CE,0x03CE,0x03DE,0x039E,0x039C,0x079C,0x3FFF,0x7FFF,0x0738,0x0F38,0x0F78,0x0F78,0x0E78,0xFFFF,0xFFFF,0x1EF0,0x1CF0,0x1CE0,0x3CE0,0x3DE0,0x39E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [#] +0x03FC,0x0FFE,0x1FEE,0x1EE0,0x1EE0,0x1EE0,0x1EE0,0x1FE0,0x0FE0,0x07E0,0x03F0,0x01FC,0x01FE,0x01FE,0x01FE,0x01FE,0x01FE,0x01FE,0x3DFE,0x3FFC,0x0FF0,0x01E0,0x01E0,0x0000,0x0000,0x0000, // Ascii = [$] +0x3E03,0xF707,0xE78F,0xE78E,0xE39E,0xE3BC,0xE7B8,0xE7F8,0xF7F0,0x3FE0,0x01C0,0x03FF,0x07FF,0x07F3,0x0FF3,0x1EF3,0x3CF3,0x38F3,0x78F3,0xF07F,0xE03F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [%] +0x07E0,0x0FF8,0x0F78,0x1F78,0x1F78,0x1F78,0x0F78,0x0FF0,0x0FE0,0x1F80,0x7FC3,0xFBC3,0xF3E7,0xF1F7,0xF0F7,0xF0FF,0xF07F,0xF83E,0x7C7F,0x3FFF,0x1FEF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [&] +0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03C0,0x01C0,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = ['] +0x003F,0x007C,0x01F0,0x01E0,0x03C0,0x07C0,0x0780,0x0780,0x0F80,0x0F00,0x0F00,0x0F00,0x0F00,0x0F00,0x0F00,0x0F80,0x0780,0x0780,0x07C0,0x03C0,0x01E0,0x01F0,0x007C,0x003F,0x000F,0x0000, // Ascii = [(] +0x7E00,0x1F00,0x07C0,0x03C0,0x01E0,0x01F0,0x00F0,0x00F0,0x00F8,0x0078,0x0078,0x0078,0x0078,0x0078,0x0078,0x00F8,0x00F0,0x00F0,0x01F0,0x01E0,0x03C0,0x07C0,0x1F00,0x7E00,0x7800,0x0000, // Ascii = [)] +0x03E0,0x03C0,0x01C0,0x39CE,0x3FFF,0x3F7F,0x0320,0x0370,0x07F8,0x0F78,0x1F3C,0x0638,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [*] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0xFFFF,0xFFFF,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [+] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x01E0,0x01E0,0x01E0,0x01C0,0x0380, // Ascii = [,] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3FFE,0x3FFE,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [-] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [.] +0x000F,0x000F,0x001E,0x001E,0x003C,0x003C,0x0078,0x0078,0x00F0,0x00F0,0x01E0,0x01E0,0x03C0,0x03C0,0x0780,0x0780,0x0F00,0x0F00,0x1E00,0x1E00,0x3C00,0x3C00,0x7800,0x7800,0xF000,0x0000, // Ascii = [/] +0x07F0,0x0FF8,0x1F7C,0x3E3E,0x3C1E,0x7C1F,0x7C1F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x7C1F,0x7C1F,0x3C1E,0x3E3E,0x1F7C,0x0FF8,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [0] +0x00F0,0x07F0,0x3FF0,0x3FF0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x3FFF,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [1] +0x0FE0,0x3FF8,0x3C7C,0x003C,0x003E,0x003E,0x003E,0x003C,0x003C,0x007C,0x00F8,0x01F0,0x03E0,0x07C0,0x0780,0x0F00,0x1E00,0x3E00,0x3C00,0x3FFE,0x3FFE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [2] +0x0FF0,0x1FF8,0x1C7C,0x003E,0x003E,0x003E,0x003C,0x003C,0x00F8,0x0FF0,0x0FF8,0x007C,0x003E,0x001E,0x001E,0x001E,0x001E,0x003E,0x1C7C,0x1FF8,0x1FE0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [3] +0x0078,0x00F8,0x00F8,0x01F8,0x03F8,0x07F8,0x07F8,0x0F78,0x1E78,0x1E78,0x3C78,0x7878,0x7878,0xFFFF,0xFFFF,0x0078,0x0078,0x0078,0x0078,0x0078,0x0078,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [4] +0x1FFC,0x1FFC,0x1FFC,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1FE0,0x1FF8,0x00FC,0x007C,0x003E,0x003E,0x001E,0x003E,0x003E,0x003C,0x1C7C,0x1FF8,0x1FE0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [5] +0x01FC,0x07FE,0x0F8E,0x1F00,0x1E00,0x3E00,0x3C00,0x3C00,0x3DF8,0x3FFC,0x7F3E,0x7E1F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3E0F,0x1E1F,0x1F3E,0x0FFC,0x03F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [6] +0x3FFF,0x3FFF,0x3FFF,0x000F,0x001E,0x001E,0x003C,0x0038,0x0078,0x00F0,0x00F0,0x01E0,0x01E0,0x03C0,0x03C0,0x0780,0x0F80,0x0F80,0x0F00,0x1F00,0x1F00,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [7] +0x07F8,0x0FFC,0x1F3E,0x1E1E,0x3E1E,0x3E1E,0x1E1E,0x1F3C,0x0FF8,0x07F0,0x0FF8,0x1EFC,0x3E3E,0x3C1F,0x7C1F,0x7C0F,0x7C0F,0x3C1F,0x3F3E,0x1FFC,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [8] +0x07F0,0x0FF8,0x1E7C,0x3C3E,0x3C1E,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x3C1F,0x3E3F,0x1FFF,0x07EF,0x001F,0x001E,0x001E,0x003E,0x003C,0x38F8,0x3FF0,0x1FE0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [9] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [:] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x01E0,0x01E0,0x01E0,0x03C0,0x0380, // Ascii = [;] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0003,0x000F,0x003F,0x00FC,0x03F0,0x0FC0,0x3F00,0xFE00,0x3F00,0x0FC0,0x03F0,0x00FC,0x003F,0x000F,0x0003,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [<] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xFFFF,0xFFFF,0x0000,0x0000,0x0000,0xFFFF,0xFFFF,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [=] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xE000,0xF800,0x7E00,0x1F80,0x07E0,0x01F8,0x007E,0x001F,0x007E,0x01F8,0x07E0,0x1F80,0x7E00,0xF800,0xE000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [>] +0x1FF0,0x3FFC,0x383E,0x381F,0x381F,0x001E,0x001E,0x003C,0x0078,0x00F0,0x01E0,0x03C0,0x03C0,0x07C0,0x07C0,0x0000,0x0000,0x0000,0x07C0,0x07C0,0x07C0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [?] +0x03F8,0x0FFE,0x1F1E,0x3E0F,0x3C7F,0x78FF,0x79EF,0x73C7,0xF3C7,0xF38F,0xF38F,0xF38F,0xF39F,0xF39F,0x73FF,0x7BFF,0x79F7,0x3C00,0x1F1C,0x0FFC,0x03F8,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [@] +0x0000,0x0000,0x0000,0x03E0,0x03E0,0x07F0,0x07F0,0x07F0,0x0F78,0x0F78,0x0E7C,0x1E3C,0x1E3C,0x3C3E,0x3FFE,0x3FFF,0x781F,0x780F,0xF00F,0xF007,0xF007,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [A] +0x0000,0x0000,0x0000,0x3FF8,0x3FFC,0x3C3E,0x3C1E,0x3C1E,0x3C1E,0x3C3E,0x3C7C,0x3FF0,0x3FF8,0x3C7E,0x3C1F,0x3C1F,0x3C0F,0x3C0F,0x3C1F,0x3FFE,0x3FF8,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [B] +0x0000,0x0000,0x0000,0x01FF,0x07FF,0x1F87,0x3E00,0x3C00,0x7C00,0x7800,0x7800,0x7800,0x7800,0x7800,0x7C00,0x7C00,0x3E00,0x3F00,0x1F83,0x07FF,0x01FF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [C] +0x0000,0x0000,0x0000,0x7FF0,0x7FFC,0x787E,0x781F,0x781F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x781F,0x781E,0x787E,0x7FF8,0x7FE0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [D] +0x0000,0x0000,0x0000,0x3FFF,0x3FFF,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3FFE,0x3FFE,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3FFF,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [E] +0x0000,0x0000,0x0000,0x1FFF,0x1FFF,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1FFF,0x1FFF,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [F] +0x0000,0x0000,0x0000,0x03FE,0x0FFF,0x1F87,0x3E00,0x7C00,0x7C00,0x7800,0xF800,0xF800,0xF87F,0xF87F,0x780F,0x7C0F,0x7C0F,0x3E0F,0x1F8F,0x0FFF,0x03FE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [G] +0x0000,0x0000,0x0000,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7FFF,0x7FFF,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [H] +0x0000,0x0000,0x0000,0x3FFF,0x3FFF,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x3FFF,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [I] +0x0000,0x0000,0x0000,0x1FFC,0x1FFC,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x0078,0x0078,0x38F8,0x3FF0,0x3FC0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [J] +0x0000,0x0000,0x0000,0x3C1F,0x3C1E,0x3C3C,0x3C78,0x3CF0,0x3DE0,0x3FE0,0x3FC0,0x3F80,0x3FC0,0x3FE0,0x3DF0,0x3CF0,0x3C78,0x3C7C,0x3C3E,0x3C1F,0x3C0F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [K] +0x0000,0x0000,0x0000,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3FFF,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [L] +0x0000,0x0000,0x0000,0xF81F,0xFC1F,0xFC1F,0xFE3F,0xFE3F,0xFE3F,0xFF7F,0xFF77,0xFF77,0xF7F7,0xF7E7,0xF3E7,0xF3E7,0xF3C7,0xF007,0xF007,0xF007,0xF007,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [M] +0x0000,0x0000,0x0000,0x7C0F,0x7C0F,0x7E0F,0x7F0F,0x7F0F,0x7F8F,0x7F8F,0x7FCF,0x7BEF,0x79EF,0x79FF,0x78FF,0x78FF,0x787F,0x783F,0x783F,0x781F,0x781F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [N] +0x0000,0x0000,0x0000,0x07F0,0x1FFC,0x3E3E,0x7C1F,0x780F,0x780F,0xF80F,0xF80F,0xF80F,0xF80F,0xF80F,0xF80F,0x780F,0x780F,0x7C1F,0x3E3E,0x1FFC,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [O] +0x0000,0x0000,0x0000,0x3FFC,0x3FFF,0x3E1F,0x3E0F,0x3E0F,0x3E0F,0x3E0F,0x3E1F,0x3E3F,0x3FFC,0x3FF0,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [P] +0x0000,0x0000,0x0000,0x07F0,0x1FFC,0x3E3E,0x7C1F,0x780F,0x780F,0xF80F,0xF80F,0xF80F,0xF80F,0xF80F,0xF80F,0x780F,0x780F,0x7C1F,0x3E3E,0x1FFC,0x07F8,0x007C,0x003F,0x000F,0x0003,0x0000, // Ascii = [Q] +0x0000,0x0000,0x0000,0x3FF0,0x3FFC,0x3C7E,0x3C3E,0x3C1E,0x3C1E,0x3C3E,0x3C3C,0x3CFC,0x3FF0,0x3FE0,0x3DF0,0x3CF8,0x3C7C,0x3C3E,0x3C1E,0x3C1F,0x3C0F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [R] +0x0000,0x0000,0x0000,0x07FC,0x1FFE,0x3E0E,0x3C00,0x3C00,0x3C00,0x3E00,0x1FC0,0x0FF8,0x03FE,0x007F,0x001F,0x000F,0x000F,0x201F,0x3C3E,0x3FFC,0x1FF0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [S] +0x0000,0x0000,0x0000,0xFFFF,0xFFFF,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [T] +0x0000,0x0000,0x0000,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x3C1E,0x3C1E,0x3E3E,0x1FFC,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [U] +0x0000,0x0000,0x0000,0xF007,0xF007,0xF807,0x780F,0x7C0F,0x3C1E,0x3C1E,0x3E1E,0x1E3C,0x1F3C,0x1F78,0x0F78,0x0FF8,0x07F0,0x07F0,0x07F0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [V] +0x0000,0x0000,0x0000,0xE003,0xF003,0xF003,0xF007,0xF3E7,0xF3E7,0xF3E7,0x73E7,0x7BF7,0x7FF7,0x7FFF,0x7F7F,0x7F7F,0x7F7E,0x3F7E,0x3E3E,0x3E3E,0x3E3E,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [W] +0x0000,0x0000,0x0000,0xF807,0x7C0F,0x3E1E,0x3E3E,0x1F3C,0x0FF8,0x07F0,0x07E0,0x03E0,0x03E0,0x07F0,0x0FF8,0x0F7C,0x1E7C,0x3C3E,0x781F,0x780F,0xF00F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [X] +0x0000,0x0000,0x0000,0xF807,0x7807,0x7C0F,0x3C1E,0x3E1E,0x1F3C,0x0F78,0x0FF8,0x07F0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [Y] +0x0000,0x0000,0x0000,0x7FFF,0x7FFF,0x000F,0x001F,0x003E,0x007C,0x00F8,0x00F0,0x01E0,0x03E0,0x07C0,0x0F80,0x0F00,0x1E00,0x3E00,0x7C00,0x7FFF,0x7FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [Z] +0x07FF,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x07FF,0x07FF,0x0000, // Ascii = [[] +0x7800,0x7800,0x3C00,0x3C00,0x1E00,0x1E00,0x0F00,0x0F00,0x0780,0x0780,0x03C0,0x03C0,0x01E0,0x01E0,0x00F0,0x00F0,0x0078,0x0078,0x003C,0x003C,0x001E,0x001E,0x000F,0x000F,0x0007,0x0000, // Ascii = [\] +0x7FF0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x7FF0,0x7FF0,0x0000, // Ascii = []] +0x00C0,0x01C0,0x01C0,0x03E0,0x03E0,0x07F0,0x07F0,0x0778,0x0F78,0x0F38,0x1E3C,0x1E3C,0x3C1E,0x3C1E,0x380F,0x780F,0x7807,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [^] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xFFFF,0xFFFF,0x0000,0x0000,0x0000, // Ascii = [_] +0x00F0,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [`] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0FF8,0x3FFC,0x3C7C,0x003E,0x003E,0x003E,0x07FE,0x1FFE,0x3E3E,0x7C3E,0x783E,0x7C3E,0x7C7E,0x3FFF,0x1FCF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [a] +0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3DF8,0x3FFE,0x3F3E,0x3E1F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C1F,0x3C1E,0x3F3E,0x3FFC,0x3BF0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [b] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03FE,0x0FFF,0x1F87,0x3E00,0x3E00,0x3C00,0x7C00,0x7C00,0x7C00,0x3C00,0x3E00,0x3E00,0x1F87,0x0FFF,0x03FE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [c] +0x001F,0x001F,0x001F,0x001F,0x001F,0x001F,0x07FF,0x1FFF,0x3E3F,0x3C1F,0x7C1F,0x7C1F,0x7C1F,0x781F,0x781F,0x7C1F,0x7C1F,0x3C3F,0x3E7F,0x1FFF,0x0FDF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [d] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03F8,0x0FFC,0x1F3E,0x3E1E,0x3C1F,0x7C1F,0x7FFF,0x7FFF,0x7C00,0x7C00,0x3C00,0x3E00,0x1F07,0x0FFF,0x03FE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [e] +0x01FF,0x03E1,0x03C0,0x07C0,0x07C0,0x07C0,0x7FFF,0x7FFF,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [f] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x07EF,0x1FFF,0x3E7F,0x3C1F,0x7C1F,0x7C1F,0x781F,0x781F,0x781F,0x7C1F,0x7C1F,0x3C3F,0x3E7F,0x1FFF,0x0FDF,0x001E,0x001E,0x001E,0x387C,0x3FF8, // Ascii = [g] +0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3DFC,0x3FFE,0x3F9E,0x3F1F,0x3E1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [h] +0x01F0,0x01F0,0x0000,0x0000,0x0000,0x0000,0x7FE0,0x7FE0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [i] +0x00F8,0x00F8,0x0000,0x0000,0x0000,0x0000,0x3FF8,0x3FF8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F0,0x71F0,0x7FE0, // Ascii = [j] +0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3C1F,0x3C3E,0x3C7C,0x3CF8,0x3DF0,0x3DE0,0x3FC0,0x3FC0,0x3FE0,0x3DF0,0x3CF8,0x3C7C,0x3C3E,0x3C1F,0x3C1F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [k] +0x7FF0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [l] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xF79E,0xFFFF,0xFFFF,0xFFFF,0xFBE7,0xF9E7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [m] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3DFC,0x3FFE,0x3F9E,0x3F1F,0x3E1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [n] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x07F0,0x1FFC,0x3E3E,0x3C1F,0x7C1F,0x780F,0x780F,0x780F,0x780F,0x780F,0x7C1F,0x3C1F,0x3E3E,0x1FFC,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [o] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3DF8,0x3FFE,0x3F3E,0x3E1F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C1F,0x3E1E,0x3F3E,0x3FFC,0x3FF8,0x3C00,0x3C00,0x3C00,0x3C00,0x3C00, // Ascii = [p] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x07EE,0x1FFE,0x3E7E,0x3C1E,0x7C1E,0x781E,0x781E,0x781E,0x781E,0x781E,0x7C1E,0x7C3E,0x3E7E,0x1FFE,0x0FDE,0x001E,0x001E,0x001E,0x001E,0x001E, // Ascii = [q] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x1F7F,0x1FFF,0x1FE7,0x1FC7,0x1F87,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [r] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x07FC,0x1FFE,0x1E0E,0x3E00,0x3E00,0x3F00,0x1FE0,0x07FC,0x00FE,0x003E,0x001E,0x001E,0x3C3E,0x3FFC,0x1FF0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [s] +0x0000,0x0000,0x0000,0x0780,0x0780,0x0780,0x7FFF,0x7FFF,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x07C0,0x03FF,0x01FF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [t] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C3E,0x3C7E,0x3EFE,0x1FFE,0x0FDE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [u] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xF007,0x780F,0x780F,0x3C1E,0x3C1E,0x3E1E,0x1E3C,0x1E3C,0x0F78,0x0F78,0x0FF0,0x07F0,0x07F0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [v] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xF003,0xF1E3,0xF3E3,0xF3E7,0xF3F7,0xF3F7,0x7FF7,0x7F77,0x7F7F,0x7F7F,0x7F7F,0x3E3E,0x3E3E,0x3E3E,0x3E3E,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [w] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7C0F,0x3E1E,0x3E3C,0x1F3C,0x0FF8,0x07F0,0x07F0,0x03E0,0x07F0,0x07F8,0x0FF8,0x1E7C,0x3E3E,0x3C1F,0x781F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [x] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xF807,0x780F,0x7C0F,0x3C1E,0x3C1E,0x1E3C,0x1E3C,0x1F3C,0x0F78,0x0FF8,0x07F0,0x07F0,0x03E0,0x03E0,0x03C0,0x03C0,0x03C0,0x0780,0x0F80,0x7F00, // Ascii = [y] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3FFF,0x3FFF,0x001F,0x003E,0x007C,0x00F8,0x01F0,0x03E0,0x07C0,0x0F80,0x1F00,0x1E00,0x3C00,0x7FFF,0x7FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [z] +0x01FE,0x03E0,0x03C0,0x03C0,0x03C0,0x03C0,0x01E0,0x01E0,0x01E0,0x01C0,0x03C0,0x3F80,0x3F80,0x03C0,0x01C0,0x01E0,0x01E0,0x01E0,0x03C0,0x03C0,0x03C0,0x03C0,0x03E0,0x01FE,0x007E,0x0000, // Ascii = [{] +0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x0000, // Ascii = [|] +0x3FC0,0x03E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01C0,0x03C0,0x03C0,0x01C0,0x01E0,0x00FE,0x00FE,0x01E0,0x01C0,0x03C0,0x03C0,0x01C0,0x01E0,0x01E0,0x01E0,0x01E0,0x03E0,0x3FC0,0x3F00,0x0000, // Ascii = [}] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3F07,0x7FC7,0x73E7,0xF1FF,0xF07E,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [~] +}; +*/ + +FontDef_t Font_7x10 = { + 7, + 10, + Font7x10 +}; +/* +FontDef_t Font_11x18 = { + 11, + 18, + Font11x18 +}; + +FontDef_t Font_16x26 = { + 16, + 26, + Font16x26 +};*/ + +char* FONTS_GetStringSize(char* str, FONTS_SIZE_t* SizeStruct, FontDef_t* Font) { + /* Fill settings */ + SizeStruct->Height = Font->FontHeight; + SizeStruct->Length = Font->FontWidth * strlen(str); + + /* Return pointer */ + return str; +} diff --git a/i2c_ex1_master/fonts.h b/i2c_ex1_master/fonts.h new file mode 100644 index 0000000..b8aa071 --- /dev/null +++ b/i2c_ex1_master/fonts.h @@ -0,0 +1,132 @@ +/** + * original author: Tilen Majerle + * modification for STM32f10x: Alexander Lutsai + + ---------------------------------------------------------------------- + Copyright (C) Alexander Lutsai, 2016 + Copyright (C) Tilen Majerle, 2015 + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + ---------------------------------------------------------------------- + */ +#ifndef FONTS_H +#define FONTS_H 120 +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +/* C++ detection */ +#ifdef __cplusplus +extern C { +#endif + +/** + * + * Default fonts library. It is used in all LCD based libraries. + * + * \par Supported fonts + * + * Currently, these fonts are supported: + * - 7 x 10 pixels + * - 11 x 18 pixels + * - 16 x 26 pixels + + */ +#include "string.h" + +/** + * @defgroup LIB_Typedefs + * @brief Library Typedefs + * @{ + */ + +/** + * @brief Font structure used on my LCD libraries + */ +typedef struct { + uint8_t FontWidth; /*!< Font width in pixels */ + uint8_t FontHeight; /*!< Font height in pixels */ + const uint16_t *data; /*!< Pointer to data font data array */ +} FontDef_t; + +/** + * @brief String length and height + */ +typedef struct { + uint16_t Length; /*!< String length in units of pixels */ + uint16_t Height; /*!< String height in units of pixels */ +} FONTS_SIZE_t; + +/** + * @} + */ + +/** + * @defgroup FONTS_FontVariables + * @brief Library font variables + * @{ + */ + +/** + * @brief 7 x 10 pixels font size structure + */ +extern FontDef_t Font_7x10; + +/** + * @brief 11 x 18 pixels font size structure + */ +extern FontDef_t Font_11x18; + +/** + * @brief 16 x 26 pixels font size structure + */ +extern FontDef_t Font_16x26; + +/** + * @} + */ + +/** + * @defgroup FONTS_Functions + * @brief Library functions + * @{ + */ + +/** + * @brief Calculates string length and height in units of pixels depending on string and font used + * @param *str: String to be checked for length and height + * @param *SizeStruct: Pointer to empty @ref FONTS_SIZE_t structure where informations will be saved + * @param *Font: Pointer to @ref FontDef_t font used for calculations + * @retval Pointer to string used for length and height + */ +char* FONTS_GetStringSize(char* str, FONTS_SIZE_t* SizeStruct, FontDef_t* Font); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* C++ detection */ +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/i2c_ex1_master/i2c_ex1_master.c b/i2c_ex1_master/i2c_ex1_master.c new file mode 100644 index 0000000..ef2092a --- /dev/null +++ b/i2c_ex1_master/i2c_ex1_master.c @@ -0,0 +1,185 @@ +//############################################################################# +// +// FILE: i2c_ex1_master.c +// +// TITLE: I2C Example Master. +// +//############################################################################# +// +// Included Files +// +#include "f28x_project.h" +#include "i2c_oled.h" +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +extern uint16_t I2C_TXdata[]; +extern uint16_t I2C_RXdata[]; +//////////////////////////////////////////////////////////// +// +// Main +// + +void main(void) +{ + // + // Locals + // + uint16_t index = 0U; + uint16_t count = 0U; + + // + // Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // + InitSysCtrl(); + + // + // Initialize GPIO + // + InitGpio(); + + // + //Configure I2C pins + // + GPIO_SetupPinMux(GPIO_PIN_SDAA, GPIO_MUX_CPU1, 6); + GPIO_SetupPinOptions(GPIO_PIN_SDAA, GPIO_OUTPUT, GPIO_PULLUP); + GPIO_SetupPinMux(GPIO_PIN_SCLA, GPIO_MUX_CPU1, 6); + GPIO_SetupPinOptions(GPIO_PIN_SCLA, GPIO_OUTPUT, GPIO_PULLUP); + + + // + // Initialize the PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // + InitPieCtrl(); + + // + // Disable CPU interrupts and clear all CPU interrupt flags + // + IER = 0x0000; + IFR = 0x0000; + + // + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR) + // + InitPieVectTable(); + + // + // Set the buffer to some default non-zero value + // + for (index=0; index 0 ? (x) : -(x)) + +/* SSD1306 data buffer */ +static uint8_t SSD1306_Buffer[SSD1306_WIDTH * SSD1306_HEIGHT / 8]; + +uint16_t I2C_TXdata[16]; +uint16_t I2C_RXdata[16]; +/* Private SSD1306 structure */ +typedef struct { + uint16_t CurrentX; + uint16_t CurrentY; + uint8_t Inverted; + uint8_t Initialized; +} SSD1306_t; + +/* Private variable */ +static SSD1306_t SSD1306; +/* Функция инициализации дисплея подает управялющие комманды на микросхему управления sh1106 */ +uint8_t SSD1306_Init(void) { + + /* A little delay */ + uint32_t p = 2500; + while(p>0) + p--; + + /* Init LCD */ + SSD1306_WRITECOMMAND(0xAE); //display off + + SSD1306_WRITECOMMAND(0xB0); //Set Page Address + SSD1306_WRITECOMMAND(0x40); //---set high column address + SSD1306_WRITECOMMAND(0x00); //---set low column address + + SSD1306_WRITECOMMAND(0xA4); //---set high column address + + SSD1306_WRITECOMMAND(0xD5); //--set start line address + SSD1306_WRITECOMMAND(0x50); //--set contrast control register + + SSD1306_WRITECOMMAND(0xA8); + SSD1306_WRITECOMMAND(0x3F); //--set segment re-map 0 to 127 + + SSD1306_WRITECOMMAND(0xD3); //--set normal display + SSD1306_WRITECOMMAND(0x00); //--set multiplex ratio(1 to 64) + + SSD1306_WRITECOMMAND(0x40); // + + SSD1306_WRITECOMMAND(0xAD); //0xa4,Output follows RAM content;0xa5,Output ignores RAM content + SSD1306_WRITECOMMAND(0x8A); //-set display offset + + SSD1306_WRITECOMMAND(0xA1); //-not offset + + SSD1306_WRITECOMMAND(0xC8); //--set display clock divide ratio/oscillator frequency + + SSD1306_WRITECOMMAND(0xDA); //--set divide ratio + SSD1306_WRITECOMMAND(0x12); //--set pre-charge period + + SSD1306_WRITECOMMAND(0x81); // + SSD1306_WRITECOMMAND(0xFF); //--set com pins hardware configuration + + SSD1306_WRITECOMMAND(0xD9); + SSD1306_WRITECOMMAND(0x11); //--set vcomh + + SSD1306_WRITECOMMAND(0xDB); //0x20,0.77xVcc + SSD1306_WRITECOMMAND(0x35); //--set DC-DC enable + + SSD1306_WRITECOMMAND(0xA6); // + + SSD1306_WRITECOMMAND(0xAF); //--turn on SSD1306 panel + + /* Clear screen */ + SSD1306_Fill(SSD1306_COLOR_BLACK); + + /* Update screen */ + SSD1306_UpdateScreen(); + /* Set default values */ + SSD1306.CurrentX = 0; + SSD1306.CurrentY = 0; + + /* Initialized OK */ + SSD1306.Initialized = 1; + + /* Return OK */ + return 1; +} + +//Начальные адресса колонки и странцы +#define SSD1306_COLUMNADDR 0x21 +#define SSD1306_PAGEADDR 0xB0 + +//Функция перемещения на начльную позцию +void SSD1306_setPosition(uint8_t column, uint8_t page) { + if (column > SSD1306_WIDTH - 1) { + column = 0; // Ограничение столбца + } + if (page > 7) { + page = 0; // Ограничение страницы + } + + SSD1306_WRITECOMMAND(0x20+column); // Начальный адрес столбца + SSD1306_WRITECOMMAND(SSD1306_PAGEADDR+page); // Начальный адрес страницы + // SSD1306_WRITECOMMAND(7); // Конечный адрес страницы +} + +//Функция отображения картинки из буффера +void SSD1306_UpdateScreen(void) { + + uint8_t page; + uint8_t column; + uint8_t data_bytes = SSD1306_WIDTH / 8; + int i; + for (page = 0; page < 8; page++) { + SSD1306_WRITECOMMAND(0x10); + SSD1306_WRITECOMMAND(0x00); + for (column = 0; column < SSD1306_WIDTH; column++) { // + SSD1306_setPosition(column, page); // Начало столбца - 0, страница - m + + // Запись данных в буфер дисплея + I2C_TXdata[0] = 0x40; // Байт управления: данные + // Заполнить буфер I2C данными из буфера дисплея + I2C_TXdata[0] = 0x40; // Команда записи данных + I2C_TXdata[1] = SSD1306_Buffer[SSD1306_WIDTH*page + column]; + I2CWrite(I2C_SLAVE_ADDRESS, 2, true); + } + } +} +//Функция инвертирования бфуффера. +void SSD1306_ToggleInvert(void) { + uint16_t i; + + /* Toggle invert */ + SSD1306.Inverted = !SSD1306.Inverted; + + /* Do memory toggle */ + for (i = 0; i < sizeof(SSD1306_Buffer); i++) { + SSD1306_Buffer[i] = ~SSD1306_Buffer[i]; + } +} +// Функция заливки (стирания) +void SSD1306_Fill(SSD1306_COLOR_t color) { + /* Set memory */ + memset(SSD1306_Buffer, (color == SSD1306_COLOR_BLACK) ? 0x00 : 0xFF, sizeof(SSD1306_Buffer)); +} +void SSD1306_DrawPixel(uint16_t x, uint16_t y, SSD1306_COLOR_t color) { + if (x >= SSD1306_WIDTH || y >= SSD1306_HEIGHT) { + return; + } + + if (SSD1306.Inverted) { + color = (SSD1306_COLOR_t)!color; + } + + // Правильно вычисляем индекс байта в буфере + uint16_t byteIndex = x + (y / 8) * SSD1306_WIDTH; + // Правильно вычисляем индекс бита в байт + uint8_t bitIndex = y % 8; + + if (color == SSD1306_COLOR_WHITE) { + SSD1306_Buffer[byteIndex] |= (1 << bitIndex); + } else { + SSD1306_Buffer[byteIndex] &= ~(1 << bitIndex); + } +} + +/* Функция отображения растрового изображения */ +void ssd1306_DrawBitmap(uint8_t x, uint8_t y, const unsigned char* bitmap, uint8_t w, uint8_t h, SSD1306_COLOR_t color) { + int16_t byteWidth = (w + 7) / 8; // Bitmap scanline pad = whole byte + uint8_t byte = 0; + uint8_t i,j; + if (x >= SSD1306_WIDTH || y >= SSD1306_HEIGHT) { + return; + } + + for ( j = 0; j < h; j++, y++) { + for ( i = 0; i < w; i++) { + if (i & 7) { + byte <<= 1; + } else { + byte = (*(const unsigned char *)(&bitmap[j * byteWidth + i / 8])); + } + + if (byte & 0x80) { + SSD1306_DrawPixel(x + i, y, color); + } + } + } + return; +} + +// функция позцианирования каретки по изображению +void SSD1306_GotoXY(uint16_t x, uint16_t y) { + /* Set write pointers */ + SSD1306.CurrentX = x; + SSD1306.CurrentY = y; +} +// функция отображения символов +char SSD1306_Putc(char ch, FontDef_t* Font, SSD1306_COLOR_t color) { + uint32_t i, b, j; + + /* Check available space in LCD */ + if ( + SSD1306_WIDTH <= (SSD1306.CurrentX + Font->FontWidth) || + SSD1306_HEIGHT <= (SSD1306.CurrentY + Font->FontHeight) + ) { + /* Error */ + return 0; + } + + /* Go through font */ + for (i = 0; i < Font->FontHeight; i++) { + b = Font->data[(ch - 32) * Font->FontHeight + i]; + for (j = 0; j < Font->FontWidth; j++) { + if ((b << j) & 0x8000) { + SSD1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR_t) color); + } else { + SSD1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR_t)!color); + } + } + } + + /* Increase pointer */ + SSD1306.CurrentX += Font->FontWidth; + + /* Return character written */ + return ch; +} +//Диспетчер отображения строк. +char SSD1306_Puts(char* str, FontDef_t* Font, SSD1306_COLOR_t color) { + /* Write characters */ + // reverseString(str); + while (*str) { + /* Write character by character */ + if (SSD1306_Putc(*str, Font, color) != *str) { + /* Return error */ + return *str; + } + + /* Increase string pointer */ + str++; + } + + /* Everything OK, zero should be returned */ + return *str; +} + +//Функция построения прямых линий по алгоритму брезинхема +void SSD1306_DrawLine(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1, SSD1306_COLOR_t c) { + int16_t dx, dy, sx, sy, err, e2, i, tmp; + + /* Check for overflow */ + if (x0 >= SSD1306_WIDTH) { + x0 = SSD1306_WIDTH - 1; + } + if (x1 >= SSD1306_WIDTH) { + x1 = SSD1306_WIDTH - 1; + } + if (y0 >= SSD1306_HEIGHT) { + y0 = SSD1306_HEIGHT - 1; + } + if (y1 >= SSD1306_HEIGHT) { + y1 = SSD1306_HEIGHT - 1; + } + + dx = (x0 < x1) ? (x1 - x0) : (x0 - x1); + dy = (y0 < y1) ? (y1 - y0) : (y0 - y1); + sx = (x0 < x1) ? 1 : -1; + sy = (y0 < y1) ? 1 : -1; + err = ((dx > dy) ? dx : -dy) / 2; + + if (dx == 0) { + if (y1 < y0) { + tmp = y1; + y1 = y0; + y0 = tmp; + } + + if (x1 < x0) { + tmp = x1; + x1 = x0; + x0 = tmp; + } + + /* Vertical line */ + for (i = y0; i <= y1; i++) { + SSD1306_DrawPixel(x0, i, c); + } + + /* Return from function */ + return; + } + + if (dy == 0) { + if (y1 < y0) { + tmp = y1; + y1 = y0; + y0 = tmp; + } + + if (x1 < x0) { + tmp = x1; + x1 = x0; + x0 = tmp; + } + + /* Horizontal line */ + for (i = x0; i <= x1; i++) { + SSD1306_DrawPixel(i, y0, c); + } + + /* Return from function */ + return; + } + + while (1) { + SSD1306_DrawPixel(x0, y0, c); + if (x0 == x1 && y0 == y1) { + break; + } + e2 = err; + if (e2 > -dx) { + err -= dy; + x0 += sx; + } + if (e2 < dy) { + err += dx; + y0 += sy; + } + } +} +//функция построения прямоугольников +void SSD1306_DrawRectangle(uint16_t x, uint16_t y, uint16_t w, uint16_t h, SSD1306_COLOR_t c) { + /* Check input parameters */ + if ( + x >= SSD1306_WIDTH || + y >= SSD1306_HEIGHT + ) { + /* Return error */ + return; + } + + /* Check width and height */ + if ((x + w) >= SSD1306_WIDTH) { + w = SSD1306_WIDTH - x; + } + if ((y + h) >= SSD1306_HEIGHT) { + h = SSD1306_HEIGHT - y; + } + + /* Draw 4 lines */ + SSD1306_DrawLine(x, y, x + w, y, c); /* Top line */ + SSD1306_DrawLine(x, y + h, x + w, y + h, c); /* Bottom line */ + SSD1306_DrawLine(x, y, x, y + h, c); /* Left line */ + SSD1306_DrawLine(x + w, y, x + w, y + h, c); /* Right line */ +} +//Функция построения прямоугольников закрашенных прямоугольников +void SSD1306_DrawFilledRectangle(uint16_t x, uint16_t y, uint16_t w, uint16_t h, SSD1306_COLOR_t c) { + uint8_t i; + + /* Check input parameters */ + if ( + x >= SSD1306_WIDTH || + y >= SSD1306_HEIGHT + ) { + /* Return error */ + return; + } + + /* Check width and height */ + if ((x + w) >= SSD1306_WIDTH) { + w = SSD1306_WIDTH - x; + } + if ((y + h) >= SSD1306_HEIGHT) { + h = SSD1306_HEIGHT - y; + } + + /* Draw lines */ + for (i = 0; i <= h; i++) { + /* Draw lines */ + SSD1306_DrawLine(x, y + i, x + w, y + i, c); + } +} +//Фунция построения треугольников +void SSD1306_DrawTriangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t x3, uint16_t y3, SSD1306_COLOR_t color) { + /* Draw lines */ + SSD1306_DrawLine(x1, y1, x2, y2, color); + SSD1306_DrawLine(x2, y2, x3, y3, color); + SSD1306_DrawLine(x3, y3, x1, y1, color); +} + +//Фунция построения закрашенных треугольников +void SSD1306_DrawFilledTriangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t x3, uint16_t y3, SSD1306_COLOR_t color) { + int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, + yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, + curpixel = 0; + + deltax = ABS(x2 - x1); + deltay = ABS(y2 - y1); + x = x1; + y = y1; + + if (x2 >= x1) { + xinc1 = 1; + xinc2 = 1; + } else { + xinc1 = -1; + xinc2 = -1; + } + + if (y2 >= y1) { + yinc1 = 1; + yinc2 = 1; + } else { + yinc1 = -1; + yinc2 = -1; + } + + if (deltax >= deltay){ + xinc1 = 0; + yinc2 = 0; + den = deltax; + num = deltax / 2; + numadd = deltay; + numpixels = deltax; + } else { + xinc2 = 0; + yinc1 = 0; + den = deltay; + num = deltay / 2; + numadd = deltax; + numpixels = deltay; + } + + for (curpixel = 0; curpixel <= numpixels; curpixel++) { + SSD1306_DrawLine(x, y, x3, y3, color); + + num += numadd; + if (num >= den) { + num -= den; + x += xinc1; + y += yinc1; + } + x += xinc2; + y += yinc2; + } +} +//Функция построения окружностей +void SSD1306_DrawCircle(int16_t x0, int16_t y0, int16_t r, SSD1306_COLOR_t c) { + int16_t f = 1 - r; + int16_t ddF_x = 1; + int16_t ddF_y = -2 * r; + int16_t x = 0; + int16_t y = r; + + SSD1306_DrawPixel(x0, y0 + r, c); + SSD1306_DrawPixel(x0, y0 - r, c); + SSD1306_DrawPixel(x0 + r, y0, c); + SSD1306_DrawPixel(x0 - r, y0, c); + + while (x < y) { + if (f >= 0) { + y--; + ddF_y += 2; + f += ddF_y; + } + x++; + ddF_x += 2; + f += ddF_x; + + SSD1306_DrawPixel(x0 + x, y0 + y, c); + SSD1306_DrawPixel(x0 - x, y0 + y, c); + SSD1306_DrawPixel(x0 + x, y0 - y, c); + SSD1306_DrawPixel(x0 - x, y0 - y, c); + + SSD1306_DrawPixel(x0 + y, y0 + x, c); + SSD1306_DrawPixel(x0 - y, y0 + x, c); + SSD1306_DrawPixel(x0 + y, y0 - x, c); + SSD1306_DrawPixel(x0 - y, y0 - x, c); + } +} +//Функция построения закрашенных окружностей +void SSD1306_DrawFilledCircle(int16_t x0, int16_t y0, int16_t r, SSD1306_COLOR_t c) { + int16_t f = 1 - r; + int16_t ddF_x = 1; + int16_t ddF_y = -2 * r; + int16_t x = 0; + int16_t y = r; + + SSD1306_DrawPixel(x0, y0 + r, c); + SSD1306_DrawPixel(x0, y0 - r, c); + SSD1306_DrawPixel(x0 + r, y0, c); + SSD1306_DrawPixel(x0 - r, y0, c); + SSD1306_DrawLine(x0 - r, y0, x0 + r, y0, c); + + while (x < y) { + if (f >= 0) { + y--; + ddF_y += 2; + f += ddF_y; + } + x++; + ddF_x += 2; + f += ddF_x; + + SSD1306_DrawLine(x0 - x, y0 + y, x0 + x, y0 + y, c); + SSD1306_DrawLine(x0 + x, y0 - y, x0 - x, y0 - y, c); + + SSD1306_DrawLine(x0 + y, y0 + x, x0 - y, y0 + x, c); + SSD1306_DrawLine(x0 + y, y0 - x, x0 - y, y0 - x, c); + } +} +//Функция включения дисплея +void SSD1306_ON(void) { + SSD1306_WRITECOMMAND(0x8D); + SSD1306_WRITECOMMAND(0x14); + SSD1306_WRITECOMMAND(0xAF); +} +//Функция выключения дисплея +void SSD1306_OFF(void) { + SSD1306_WRITECOMMAND(0x8D); + SSD1306_WRITECOMMAND(0x10); + SSD1306_WRITECOMMAND(0xAE); +} + +// +// Функция инцииализации I2C как мастера. +// +void I2CMaster_Init(uint16_t I2C_OwnAddress, uint16_t I2CSlave_Address) +{ + EALLOW; + // + // Must put I2C into reset before configuring it + // + I2caRegs.I2CMDR.all &= ~(0x20U); + + // + // I2C configuration. Use a 400kHz I2CCLK with a 50% duty cycle. + // + //I2C_initMaster(base, DEVICE_SYSCLK_FREQ, 400000, I2C_DUTYCYCLE_50); + I2caRegs.I2CPSC.all = 0xB; // Prescaler - need 7-12 Mhz on module clk + I2caRegs.I2CCLKL = 0x7; // NOTE: must be non zero + I2caRegs.I2CCLKH = 0x8; // NOTE: must be non zero + + + // + // Configure Master as a Transmitter + // + I2caRegs.I2CMDR.bit.MST = 0x1; + I2caRegs.I2CMDR.bit.TRX = 0x1; + + // + // Set data count + // + I2caRegs.I2CCNT = I2C_NUMBYTES; + + // + // Set the bit count to 8 bits per data byte + // + I2caRegs.I2CMDR.bit.BC = 0x0U; + + // + // Configure slave and own address + // + I2caRegs.I2COAR.all = I2C_OwnAddress; // Own address + I2caRegs.I2CSAR.all = I2CSlave_Address; // Slave address + + // + // Set emulation mode to FREE + // + I2caRegs.I2CMDR.bit.FREE = 0x1; + + // + //Clear all status + // + I2caRegs.I2CSTR.all = 0xFFFF; + + // + // Enable I2C Interrupts- RRDY + // + I2caRegs.I2CIER.all = 0x08; + + // + // Take I2C out of reset + // + I2caRegs.I2CMDR.all |= 0x0020; + + +} + +// +// Функция передачи сообщений по I2C на слэйва. +// +void I2CWrite(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition) { + int i ; + I2caRegs.I2CSAR.all = slaveAddr; + I2caRegs.I2CMDR.bit.MST = 0x1; + I2caRegs.I2CMDR.bit.TRX = 0x1; + I2caRegs.I2CCNT = byteCount; + I2caRegs.I2CMDR.bit.STT = 0x1; + + for ( i = 0; i < byteCount; i++) { + I2caRegs.I2CDXR.all = I2C_TXdata[i]; + while (I2caRegs.I2CSTR.bit.BYTESENT != 0x1); + I2caRegs.I2CSTR.bit.BYTESENT = 0x1; + } + + if (sendStopCondition) { + I2caRegs.I2CMDR.bit.STP = 0x1; + while (I2caRegs.I2CMDR.bit.STP != 0x0); + I2caRegs.I2CSTR.bit.BYTESENT = 0x1; + } + } +// +// Функция чтения сообщений по I2C слэйва. +// +uint16_t I2CRead(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition) +{ + // + // Configure slave address + // + I2caRegs.I2CSAR.all = slaveAddr; + + // + // Configure I2C in Master Receiver mode + // + I2caRegs.I2CMDR.bit.MST = 0x1; + I2caRegs.I2CMDR.bit.TRX = 0x0; + + // + //Set Data Count + // + //I2caRegs.I2CCNT = byteCount; + + // + // send Start condition + // + I2caRegs.I2CMDR.bit.STT = 0x1; + + uint16_t count = 0; + + // + // Read the received data into RX buffer + // + while(count < I2C_NUMBYTES) + { + if(I2caRegs.I2CSTR.bit.RRDY ==0x1) + { + I2C_RXdata[count] = I2caRegs.I2CDRR.all; + count++; + } + } + + // + // Send STOP condition + // + if(sendStopCondition) + { + I2caRegs.I2CMDR.bit.STP = 0x1; + while(I2caRegs.I2CMDR.bit.STP != 0x0); + + I2caRegs.I2CSTR.bit.BYTESENT = 0x1; + + } + return count; +} + + + diff --git a/i2c_ex1_master/i2c_oled.h b/i2c_ex1_master/i2c_oled.h new file mode 100644 index 0000000..e0d4059 --- /dev/null +++ b/i2c_ex1_master/i2c_oled.h @@ -0,0 +1,53 @@ +#include "fonts.h" +#include "f28x_project.h" +// +// Defines +// +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +#define I2C_SLAVE_ADDRESS 0x3C +#define I2C_OWN_ADDRESS 0x30 +#define MAX_BUFFER_SIZE 0x10 +#define I2C_NUMBYTES 0x2U + +// +// I2C GPIO pins +// +#define GPIO_PIN_SDAA 0 // GPIO number for I2C SDAA +#define GPIO_PIN_SCLA 1 // GPIO number for I2C SCLA + + +// OLED- + #define SSD1306_WRITECOMMAND(cmd) \ + do { \ + I2C_TXdata[0] = 0x00; \ + I2C_TXdata[1] = cmd; \ + I2CWrite(I2C_SLAVE_ADDRESS, 2, true); \ + } while (0) + + +/* SSD1306 settings */ +/* SSD1306 width in pixels */ +#ifndef SSD1306_WIDTH +#define SSD1306_WIDTH 128 +#endif +/* SSD1306 LCD height in pixels */ +#ifndef SSD1306_HEIGHT +#define SSD1306_HEIGHT 64 +#endif + +/** + * @brief SSD1306 color enumeration + */ +typedef enum { + SSD1306_COLOR_BLACK = 0x00, /*!< Black color, no pixel */ + SSD1306_COLOR_WHITE = 0x01 /*!< Pixel is set. Color depends on LCD */ +} SSD1306_COLOR_t; + + +// +// Function Prototypes +// +void I2CMaster_Init(uint16_t I2CSlave_OwnAddress, uint16_t I2CSlave_Address); +void I2CWrite(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition); +uint16_t I2CRead(uint16_t slaveAddr, uint16_t byteCount, bool sendStopCondition); diff --git a/i2c_ex1_master/targetConfigs/TMS320F28388D.ccxml b/i2c_ex1_master/targetConfigs/TMS320F28388D.ccxml new file mode 100644 index 0000000..07dfdb0 --- /dev/null +++ b/i2c_ex1_master/targetConfigs/TMS320F28388D.ccxml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

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