351 lines
10 KiB
C++
351 lines
10 KiB
C++
/*
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* eth_ecat.cpp
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*
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* Created on: 16 <20><><EFBFBD>. 2023 <20>.
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* Author: sychev
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*/
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#include "free_rtos/ethernet_industry/eth_ecat.hpp"
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#include <cstring>
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#include <kernel/dpl/ClockP.h>
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namespace free_rtos {
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EthEcat::EthEcat(Eth& eth)
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: eth_{eth}
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, tx_flow_{*eth.getTxFlowPtr()}
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, telegram_{eth}
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, eeprom_{telegram_} { }
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void EthEcat::Init(TEthMacPorts port_id, uint32_t period_microsec = 250) {
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port_id_ = port_id;
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telegram_.init(port_id);
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Timer::Settings ecat_tmr_sett = {
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.input_clk_Hz = 25000000, // 25MHz
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.base_address = 0x2400000u, // memory mapping,
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.clock_src_mux_addr = 0x430081B0u, // sysconfig
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.int_num = 152u, // sysconfig
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.int_priority = 4, // sysconfig
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.period_us = period_microsec /// microsec
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};
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ecat_timer_.Init(ecat_tmr_sett);
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ecat_timer_.Stop();
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}
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bool EthEcat::set_slaves_to_default() {
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const datagram::TEcatWkc expected_wkc = 1;
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address::Broadcast broadcast{0x0000};
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bool status;
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/* deact loop manual */
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uint8_t a_data_out{0x00};
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datagram::EcatDatagram<command::BWR, uint8_t> a{ {{broadcast, ECT_REG_DLPORT}}, expected_wkc, a_data_out };
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/* set IRQ mask */
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uint16_t b_data_out{0x0C04};
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datagram::EcatDatagram<command::BWR, uint16_t> b{ {{broadcast, ECT_REG_IRQMASK}}, expected_wkc, b_data_out };
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/* reset CRC counters */
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std::array<uint8_t, 8> c_data_out;
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c_data_out.fill(0x00);
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datagram::EcatDatagram<command::BWR, std::array<uint8_t, 8>> c{ {{broadcast, ECT_REG_RXERR}}, expected_wkc, c_data_out };
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/* reset FMMU's */
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std::array<uint8_t, 16*3> d_data_out;
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d_data_out.fill(0x00);
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datagram::EcatDatagram<command::BWR, std::array<uint8_t, 16*3>> d{ {{broadcast, ECT_REG_FMMU0}}, expected_wkc, d_data_out };
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/* reset SyncM */
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std::array<uint8_t, 8*4> e_data_out;
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e_data_out.fill(0x00);
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datagram::EcatDatagram<command::BWR, std::array<uint8_t, 8*4>> e{ {{broadcast, ECT_REG_SM0}}, expected_wkc, e_data_out };
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/* reset activation register */
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uint8_t f_data_out{0x00};
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datagram::EcatDatagram<command::BWR, uint8_t> f{ {{broadcast, ECT_REG_DCSYNCACT}}, expected_wkc, f_data_out };
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/* reset system time+ofs */
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std::array<uint8_t, 4> g_data_out;
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g_data_out.fill(0x00);
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datagram::EcatDatagram<command::BWR, std::array<uint8_t, 4>> g{ {{broadcast, ECT_REG_DCSYSTIME}}, expected_wkc, g_data_out };
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/* DC speedstart */
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uint16_t h_data_out{0x1000};
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datagram::EcatDatagram<command::BWR, uint16_t> h{ {{broadcast, ECT_REG_DCSPEEDCNT}}, expected_wkc, h_data_out };
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/* DC filt expr */
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uint16_t i_data_out{0x0C00};
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datagram::EcatDatagram<command::BWR, uint16_t> i{ {{broadcast, ECT_REG_DCTIMEFILT}}, expected_wkc, i_data_out };
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/* Ignore Alias register */
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uint8_t j_data_out{0x00};
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datagram::EcatDatagram<command::BWR, uint8_t> j{ {{broadcast, ECT_REG_DLALIAS}}, expected_wkc, j_data_out };
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/* Reset all slaves to Init */
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uint16_t k_data_out{EC_STATE_INIT|EC_STATE_ACK};
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datagram::EcatDatagram<command::BWR, uint16_t> k{ {{broadcast, ECT_REG_ALCTL}}, expected_wkc, k_data_out };
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/* force Eeprom from PDI */
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uint8_t l_data_out{0x02};
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datagram::EcatDatagram<command::BWR, uint8_t> l{ {{broadcast, ECT_REG_EEPCFG}}, expected_wkc, l_data_out };
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/* set Eeprom to master */
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uint8_t m_data_out{0x00};
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datagram::EcatDatagram<command::BWR, uint8_t> m{ {{broadcast, ECT_REG_EEPCFG}}, expected_wkc, m_data_out };
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auto queue = a + b + c + d + e + f + g + h + i + j + k + l + m;
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status = telegram_.transfer(queue);
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//telegram_.transfer(b);
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//telegram_.transfer(c);
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//telegram_.transfer(d);
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//telegram_.transfer(e);
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//telegram_.transfer(f);
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//telegram_.transfer(g);
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//telegram_.transfer(h);
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//telegram_.transfer(i);
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//telegram_.transfer(j);
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//telegram_.transfer(k);
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//telegram_.transfer(l);
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//telegram_.transfer(m);
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DebugP_log((char*)"Deact loop manual wkc = %d\r\n", a.get_wkc());
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DebugP_log((char*)"Set IRQ mask wkc = %d\r\n", b.get_wkc());
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DebugP_log((char*)"Reset CRC counters wkc = %d\r\n", c.get_wkc());
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DebugP_log((char*)"Reset FMMU's wkc = %d\r\n", d.get_wkc());
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DebugP_log((char*)"Reset SyncM wkc = %d\r\n", e.get_wkc());
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DebugP_log((char*)"Reset activation register wkc = %d\r\n", f.get_wkc());
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DebugP_log((char*)"Reset system time+ofs wkc = %d\r\n", g.get_wkc());
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DebugP_log((char*)"DC speedstart wkc = %d\r\n", h.get_wkc());
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DebugP_log((char*)"DC filt expr wkc = %d\r\n", i.get_wkc());
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DebugP_log((char*)"Ignore Alias register wkc = %d\r\n", j.get_wkc());
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DebugP_log((char*)"Reset all slaves to Init wkc = %d\r\n", k.get_wkc());
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DebugP_log((char*)"Force Eeprom from PDI wkc = %d\r\n", l.get_wkc());
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DebugP_log((char*)"Set Eeprom to master wkc = %d\r\n", m.get_wkc());
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return status;
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}
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uint16_t EthEcat::slaves_detecting() {
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address::Broadcast broadcast{0x0000};
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uint16_t data{0x0000};
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datagram::EcatDatagram<command::BRD, uint16_t> datagram{ {{broadcast, ECT_REG_TYPE}}, 1, data };
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telegram_.transfer(datagram);
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return datagram.get_wkc();
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}
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// Setting Station address (FP) of slave via Position addressing (AP)
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// Station address is datagram data
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bool EthEcat::set_addresses_of_slaves(uint16_t number_of_slaves, uint16_t address_base) {
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using TDatagram = datagram::EcatDatagram<command::APWR, address::Station>;
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const datagram::TEcatWkc expected_wkc = 1;
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std::vector<TDatagram> datagrams;
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bool status;
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slaves_.reserve(number_of_slaves);
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datagrams.reserve(number_of_slaves);
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for(uint16_t i = 0; i < number_of_slaves; i++) {
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address::Position position{static_cast<int16_t>(-i)};
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address::Station station{static_cast<uint16_t>(address_base + i)};
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address::SlaveAddresses slave_addresses{position, 0x0000, station, 0x00000000};
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slaves_.emplace_back(EcatSlave{std::move(slave_addresses)});
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datagrams.emplace_back(TDatagram{ {{position, ECT_REG_STADR}}, expected_wkc, slaves_.back().get_slave_address<command::FP>() });
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}
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queue::Queue<datagram::IEcatDatagram> queue;
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for(uint16_t i = 0; i < number_of_slaves; i++) {
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queue + datagrams[i];
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}
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status = telegram_.transfer(queue);
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if(status != true) {
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DebugP_log((char*)"Slave addresses not set\r\n");
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return status;
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}
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DebugP_log((char*)"Slave addresses set\r\n");
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return status;
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}
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bool EthEcat::get_addresses_of_slaves() {
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using TDatagram = datagram::EcatDatagram<command::APRD, address::Station>;
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const datagram::TEcatWkc expected_wkc = 1;
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std::vector<TDatagram> datagrams;
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uint16_t number_of_slaves = slaves_.size();
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queue::Queue<datagram::IEcatDatagram> queue;
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bool status;
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datagrams.reserve(number_of_slaves);
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for(EcatSlave& slave : slaves_) {
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datagrams.emplace_back(TDatagram{ {{slave.get_slave_address<command::AP>(), ECT_REG_STADR}}, expected_wkc, slave.get_slave_address<command::FP>() });
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}
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for(uint16_t i = 0; i < number_of_slaves; i++) {
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queue + datagrams[i];
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}
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status = telegram_.transfer(queue);
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if(status != true) {
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DebugP_log((char*)"Slave addresses not read\r\n");
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return status;
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}
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for(EcatSlave& slave : slaves_) {
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DebugP_log((char*)"Slave %d address = %d\r\n", -slave.get_slave_address<command::AP>(), slave.get_slave_address<command::FP>());
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}
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return status;
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}
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bool EthEcat::config_init(uint16_t address_base) {
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uint16_t number_of_slaves;
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bool status;
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DebugP_log((char*)"EthercatMaster starting. Initializing slaves...\r\n");
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status = set_slaves_to_default();
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if(status != true) {
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return status;
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}
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number_of_slaves = slaves_detecting();
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DebugP_log((char*)"number_of_slaves = %d\r\n", number_of_slaves);
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status = (number_of_slaves > 0);
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if(status != true) {
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return status;
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}
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status = set_addresses_of_slaves(number_of_slaves, address_base);
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if(status != true) {
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return status;
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}
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status = get_addresses_of_slaves();
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if(status != true) {
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return status;
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}
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return status;
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}
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bool EthEcat::enable_PDI() {
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const datagram::TEcatWkc expected_wkc = 1;
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bool status = true;
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for(EcatSlave& slave : slaves_) {
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status = (status && slave.enable_PDI<command::FP>(telegram_, expected_wkc));
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}
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return status;
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}
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bool EthEcat::init_to_preop() {
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const datagram::TEcatWkc expected_wkc = 1;
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bool success = true;
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for(EcatSlave& slave : slaves_) {
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success = (success && slave.init_to_preop<command::FP>(telegram_, expected_wkc));
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}
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DebugP_log((char*)"success = %d\r\n", success);
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return success;
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}
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bool EthEcat::preop_to_safeop() {
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const datagram::TEcatWkc expected_wkc = 1;
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bool success = true;
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for(EcatSlave& slave : slaves_) {
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success = (success && slave.preop_to_safeop<command::FP>(telegram_, expected_wkc));
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}
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DebugP_log((char*)"success = %d\r\n", success);
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return success;
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}
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bool EthEcat::safeop_to_op() {
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const datagram::TEcatWkc expected_wkc = slaves_.size();
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address::Broadcast broadcast{0x0000};
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ALSTAT stat{0x0000, 0x0000};
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uint16_t zero{0x00000000};
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bool status;
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ecat_timer_.Start();
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process_sem_.post();
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if(init_sem_.pend(process_timeout_ticks_) != SystemP_SUCCESS) {
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DebugP_log((char*)"Process task timeout !\r\n");
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return false;
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}
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{
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uint16_t data{EC_STATE_OPERATIONAL};
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datagram::EcatDatagram<command::BWR, uint16_t> datagram{ {{broadcast, ECT_REG_ALCTL}}, expected_wkc, data };
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status = telegram_.transfer(datagram);
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if(status != true) {
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return status;
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}
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}
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process_sem_.post();
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if(init_sem_.pend(process_timeout_ticks_) != SystemP_SUCCESS) {
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DebugP_log((char*)"Process task timeout !\r\n");
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return false;
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}
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{
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datagram::EcatDatagram<command::BRD, ALSTAT, uint16_t> datagram{ {{broadcast, ECT_REG_ALSTAT}}, expected_wkc, stat, zero };
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status = telegram_.transfer(datagram);
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if(status != true) {
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return status;
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}
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}
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status = (stat.state == EC_STATE_OPERATIONAL) && (stat.fault == 0);
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if(status != true) {
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DebugP_log((char*)"stat.state = %d, stat.fault = %d\r\n", stat.state, stat.fault);
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return status;
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}
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//DebugP_log((char*)"success = %d\r\n", success);
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process_sem_.post();
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return status;
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}
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}
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