fix(UML-1780): Перемещена перезарядка DMA в прерывание

This commit is contained in:
algin 2023-09-26 10:09:59 +03:00
parent 1a4929e96b
commit 8f643cd992
2 changed files with 24 additions and 12 deletions

View File

@ -28,7 +28,25 @@ using namespace free_rtos;
void free_rtos::rxIsrHandler(void *appData) void free_rtos::rxIsrHandler(void *appData)
{ {
EthRxFlow * rx_flow = (EthRxFlow *)appData; EthRxFlow * rx_flow = (EthRxFlow *)appData;
EnetDma_PktQ rxReadyQ;
uint32_t readyQCount;
int32_t status;
if (rx_flow != nullptr) { if (rx_flow != nullptr) {
status = EnetDma_retrieveRxPktQ(rx_flow->dma_handle_, &rxReadyQ);
EnetAppUtils_assert(status == ENET_SOK);
readyQCount = EnetQueue_getQCount(&rxReadyQ);
if(readyQCount == 0) {
return;
}
// Reload DMA with a new rx free queue as fast as possible
rx_flow->reloadDmaRxPktQ(readyQCount);
EnetQueue_append(&rx_flow->rx_ready_pktq_, &rxReadyQ);
rx_flow->sem_[EthRxFlow::e_signalRxPkt].post(); rx_flow->sem_[EthRxFlow::e_signalRxPkt].post();
} }
} }
@ -47,6 +65,7 @@ free_rtos::EthRxFlow::EthRxFlow(TEthFrameMacAddr& mac_addr, EthStackIface& eth_s
passive_mode_{false} passive_mode_{false}
{ {
EnetQueue_initQ(&rx_free_pktq_); EnetQueue_initQ(&rx_free_pktq_);
EnetQueue_initQ(&rx_ready_pktq_);
} }
void free_rtos::EthRxFlow::initRxFreePktQ(uint32_t qCount, void * appPriv) void free_rtos::EthRxFlow::initRxFreePktQ(uint32_t qCount, void * appPriv)
@ -118,7 +137,6 @@ void free_rtos::EthRxFlow::reloadDmaRxPktQ(uint32_t qCount)
void free_rtos::EthRxFlow::rxProcessPktTask() void free_rtos::EthRxFlow::rxProcessPktTask()
{ {
EnetDma_PktQ rxReadyQ; /// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
EnetDma_Pkt* rxPktInfo; /// <20><><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> EnetDma_Pkt* rxPktInfo; /// <20><><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
int32_t status; int32_t status;
@ -128,19 +146,12 @@ void free_rtos::EthRxFlow::rxProcessPktTask()
status = sem_[e_signalRxPkt].pend(e_signalRxPkt_timeout_ticks_); status = sem_[e_signalRxPkt].pend(e_signalRxPkt_timeout_ticks_);
if(status != SystemP_SUCCESS) { if(status != SystemP_SUCCESS) {
EnetAppUtils_print("rx_flow %u: Warning ! No rx packets timeout.\r\n", id_); //EnetAppUtils_print("rx_flow %u: Warning ! No rx packets timeout.\r\n", id_);
continue; continue;
} }
/// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> rxReadyQ rxPktInfo = (EnetDma_Pkt *)EnetQueue_deq(&rx_ready_pktq_);
status = EnetDma_retrieveRxPktQ(dma_handle_, &rxReadyQ);
EnetAppUtils_assert(status == ENET_SOK);
// Reload DMA with a new rx free queue as fast as possible
reloadDmaRxPktQ(EnetQueue_getQCount(&rxReadyQ));
rxPktInfo = (EnetDma_Pkt *)EnetQueue_deq(&rxReadyQ);
while(rxPktInfo != nullptr) while(rxPktInfo != nullptr)
{ {
@ -164,7 +175,7 @@ void free_rtos::EthRxFlow::rxProcessPktTask()
EnetQueue_enq(&rx_free_pktq_, &rxPktInfo->node); EnetQueue_enq(&rx_free_pktq_, &rxPktInfo->node);
/// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> /// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
rxPktInfo = (EnetDma_Pkt *)EnetQueue_deq(&rxReadyQ); rxPktInfo = (EnetDma_Pkt *)EnetQueue_deq(&rx_ready_pktq_);
/// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> /// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
++rx_pkt_counter_; ++rx_pkt_counter_;

View File

@ -50,7 +50,7 @@ private:
e_signalTotal e_signalTotal
}; };
static constexpr e_signalRxPkt_timeout_ticks_ = 1500; static constexpr uint32_t e_signalRxPkt_timeout_ticks_ = SystemP_WAIT_FOREVER;
uint32_t id_; /// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> uint32_t id_; /// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
bool open_; /// <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><><EFBFBD> dma <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> bool open_; /// <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><><EFBFBD> dma <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
@ -70,6 +70,7 @@ private:
uint32_t rx_flow_idx_; uint32_t rx_flow_idx_;
EnetDma_RxChHandle dma_handle_; EnetDma_RxChHandle dma_handle_;
EnetDma_PktQ rx_free_pktq_; EnetDma_PktQ rx_free_pktq_;
EnetDma_PktQ rx_ready_pktq_;
bool passive_mode_; /// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> bool passive_mode_; /// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}; };