am64x/am243x: SDFM: Enable shifting between time-trigger point

-Enable shifting between time-trigger point for 2-axis

Fixes: PINDSW-7136

Signed-off-by: Achala Ram <a-ram@ti.com>

examples/current_sense/icss_sdfm_nine_channel_load_share_mode/sdfm.c

@@ -296,24 +296,24 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI
         return SDFM_ERR_INIT_SDFM;
     }
 
-    hSdfm->iep_clock = pSdfmPrms->iep_clock; 
+    hSdfm->iepClock = pSdfmPrms->iepClock; 
-    hSdfm->sdfm_clock = pSdfmPrms->sd_clock; 
+    hSdfm->sdfmClock = pSdfmPrms->sdClock; 
     hSdfm->sampleOutputInterface = (SDFM_SampleOutInterface *)(pSdfmPrms->samplesBaseAddress);
     uint32_t sampleOutputInterfaceGlobalAddr = CPU0_BTCM_SOCVIEW(pSdfmPrms->samplesBaseAddress);
     hSdfm->p_sdfm_interface->sampleBufferBaseAdd = sampleOutputInterfaceGlobalAddr;
-    hSdfm->iep_inc = 1; /* Default IEP increment 1 */
+    hSdfm->iepInc = 1; /* Default IEP increment 1 */
     
     uint8_t acc_filter = 0; //SINC3 filter
     uint8_t ecap_divider = 0x0F; //IEP at 300MHz: SD clock = 300/15=20Mhz
 
     /*configure IEP count for one epwm period*/
-    SDFM_configIepCount(hSdfm, pSdfmPrms->epwm_out_freq);
+    SDFM_configIepCount(hSdfm, pSdfmPrms->epwmOutFreq);
 
     /*configure ecap as PWM code for generate 20 MHz sdfm clock*/
     SDFM_configEcap(hSdfm, ecap_divider);
 
     /*set Noraml current OSR */
-    SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->FilterOsr);
+    SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->filterOsr);
      
 
     /*below configuration for all three channel*/
@@ -321,7 +321,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI
     {
 
         /*set comparator osr or Over current osr*/
-        SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->ComFilterOsr);
+        SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->comFilterOsr);
 
         /*set ACC source or filter type*/
         SDFM_configDataFilter(hSdfm, SDFM_CH, acc_filter);
@@ -330,13 +330,13 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI
         SDFM_selectClockSource(hSdfm, SDFM_CH, pSdfmPrms->clkPrms[SDFM_CH]);
 
         /*set threshold values */
-        SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->threshold_parms[SDFM_CH]);
+        SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->thresholdParms[SDFM_CH]);
-        if(pSdfmPrms->en_fd)
+        if(pSdfmPrms->enFastDetect)
         {
             /*Fast detect configuration */
             SDFM_configFastDetect(hSdfm, SDFM_CH, pSdfmPrms->fastDetect[SDFM_CH]);
         }
-        if(pSdfmPrms->en_com)
+        if(pSdfmPrms->enComparator )
         {
             SDFM_enableComparator(hSdfm, SDFM_CH);       
         }
@@ -346,7 +346,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI
         }
         
         /*enabling Zero cross only for first channel of axis*/
-        if(pSdfmPrms->en_zc && SDFM_CH == 2)
+        if(pSdfmPrms->enZeroCross && SDFM_CH == 2)
         {
             SDFM_enableZeroCrossDetection(hSdfm, SDFM_CH, pSdfmPrms->zcThr[SDFM_CH]);
         }
@@ -357,7 +357,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI
     SDFM_configGpioPins(hSdfm, pSdfmPrms->loadShare, pSdfmPrms->pruInsId);
 
     SDFM_setSampleTriggerTime(hSdfm, pSdfmPrms->firstSampTrigTime);
-    if(pSdfmPrms->en_second_update)
+    if(pSdfmPrms->enSecondUpdate)
     {
         SDFM_enableDoubleSampling(hSdfm, pSdfmPrms->secondSampTrigTime);
     }

examples/current_sense/icss_sdfm_nine_channel_load_share_mode/sdfm.h

@@ -143,35 +143,35 @@ typedef struct SdfmPrms_s
     /**<ICSSG pru Slice ID*/
     uint8_t icssgSliceId;
     /**< IEP clock value */
-    uint32_t iep_clock;
+    uint32_t iepClock;
     /**< Sigma delta input clock value  */
-    uint32_t sd_clock;
+    uint32_t sdClock;
     /**< double update enable field  */
-    uint8_t en_second_update;
+    uint8_t enSecondUpdate;
     /**< First normal current sample trigger time  */
     float firstSampTrigTime;
     /**< First normal current sample trigger time  */
     float secondSampTrigTime;
     /**< output freq. of EPWM0  */
-    uint32_t epwm_out_freq;
+    uint32_t epwmOutFreq;
     /**< Over current threshold parameters  */
-    SDFM_ThresholdParms   threshold_parms[NUM_CH_SUPPORTED_PER_AXIS];
+    SDFM_ThresholdParms   thresholdParms[NUM_CH_SUPPORTED_PER_AXIS];
     /**< SD clock source and clock inversion  */
     SDFM_ClkSourceParms   clkPrms[3];
     /**< Over current OSR  */
-    uint16_t ComFilterOsr;
+    uint16_t comFilterOsr;
     /**< Normal current OSR  */
-    uint16_t FilterOsr;
+    uint16_t filterOsr;
     /**< over current enable field */
-    uint8_t en_com;
+    uint8_t enComparator ;
     /**< output samples base address*/
     uint32_t samplesBaseAddress;
     /**<enable fast detect*/
-    uint8_t en_fd;
+    uint8_t enFastDetect;
     /**<Fast detect configuration field*/
     uint8_t fastDetect[NUM_SD_CH][NUM_FD_FIELD];
     /**<Zero Cross enable field*/
-    uint8_t en_zc;
+    uint8_t enZeroCross;
     /**<Zero cross threshold*/
     uint32_t zcThr[NUM_CH_SUPPORTED_PER_AXIS];
 } SdfmPrms;

examples/current_sense/icss_sdfm_three_channel_single_pru_mode/sdfm.c

@@ -178,24 +178,24 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
         return SDFM_ERR_INIT_SDFM;
     }
 
-    hSdfm->iep_clock = pSdfmPrms->iep_clock; 
+    hSdfm->iepClock = pSdfmPrms->iepClock; 
-    hSdfm->sdfm_clock = pSdfmPrms->sd_clock; 
+    hSdfm->sdfmClock = pSdfmPrms->sdClock; 
     hSdfm->sampleOutputInterface = (SDFM_SampleOutInterface *)(pSdfmPrms->samplesBaseAddress);
     uint32_t sampleOutputInterfaceGlobalAddr = CPU0_BTCM_SOCVIEW(pSdfmPrms->samplesBaseAddress);
     hSdfm->p_sdfm_interface->sampleBufferBaseAdd = sampleOutputInterfaceGlobalAddr;
-    hSdfm->iep_inc = 1; /* Default IEP increment 1 */
+    hSdfm->iepInc = 1; /* Default IEP increment 1 */
     
     uint8_t acc_filter = 0; //SINC3 filter
     uint8_t ecap_divider = 0x0F; //IEP at 300MHz: SD clock = 300/15=20Mhz
 
     /*configure IEP count for one epwm period*/
-    SDFM_configIepCount(hSdfm, pSdfmPrms->epwm_out_freq);
+    SDFM_configIepCount(hSdfm, pSdfmPrms->epwmOutFreq);
 
     /*configure ecap as PWM code for generate 20 MHz sdfm clock*/
     SDFM_configEcap(hSdfm, ecap_divider);
 
     /*set Noraml current OSR */
-    SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->FilterOsr);
+    SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->filterOsr);
      
     /*below configuration for all three channel*/
     for(SDFM_CH = 0; SDFM_CH < NUM_CH_SUPPORTED; SDFM_CH++)
@@ -203,7 +203,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
         SDFM_setEnableChannel(hSdfm, SDFM_CH);
 
         /*set comparator osr or Over current osr*/
-        SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->ComFilterOsr);
+        SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->comFilterOsr);
 
         /*set ACC source or filter type*/
         SDFM_configDataFilter(hSdfm, SDFM_CH, acc_filter);
@@ -212,13 +212,13 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
         SDFM_selectClockSource(hSdfm, SDFM_CH, pSdfmPrms->clkPrms[SDFM_CH]);
 
         /*set threshold values */
-        SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->threshold_parms[SDFM_CH]);
+        SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->thresholdParms[SDFM_CH]);
-        if(pSdfmPrms->en_fd)
+        if(pSdfmPrms->enFastDetect)
         {
             /*Fast detect configuration */
             SDFM_configFastDetect(hSdfm, SDFM_CH, pSdfmPrms->fastDetect[SDFM_CH]);
         }
-        if(pSdfmPrms->en_com)
+        if(pSdfmPrms->enComparator )
         {
             SDFM_enableComparator(hSdfm, SDFM_CH);       
         }
@@ -227,7 +227,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
             SDFM_disableComparator(hSdfm, SDFM_CH);
         }
 
-        if(pSdfmPrms->en_zc)
+        if(pSdfmPrms->enZeroCross)
         {
             SDFM_enableZeroCrossDetection(hSdfm, SDFM_CH, pSdfmPrms->zcThr[SDFM_CH]);
         }
@@ -238,7 +238,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
     SDFM_configGpioPins(hSdfm);
 
     SDFM_setSampleTriggerTime(hSdfm, pSdfmPrms->firstSampTrigTime);
-    if(pSdfmPrms->en_second_update)
+    if(pSdfmPrms->enSecondUpdate)
     {
         SDFM_enableDoubleSampling(hSdfm, pSdfmPrms->secondSampTrigTime);
     }

examples/current_sense/icss_sdfm_three_channel_single_pru_mode/sdfm.h

@@ -142,35 +142,35 @@ typedef struct SdfmPrms_s
     /**<ICSSG pru Slice ID*/
     uint8_t icssgSliceId;
     /**< IEP clock value */
-    uint32_t iep_clock;
+    uint32_t iepClock;
     /**< Sigma delta input clock value  */
-    uint32_t sd_clock;
+    uint32_t sdClock;
     /**< double update enable field  */
-    uint8_t en_second_update;
+    uint8_t enSecondUpdate;
     /**< First normal current sample trigger time  */
     float firstSampTrigTime;
     /**< First normal current sample trigger time  */
     float secondSampTrigTime;
     /**< output freq. of EPWM0  */
-    uint32_t epwm_out_freq;
+    uint32_t epwmOutFreq;
     /**< Over current threshold parameters  */
-    SDFM_ThresholdParms   threshold_parms[NUM_CH_SUPPORTED];
+    SDFM_ThresholdParms   thresholdParms[NUM_CH_SUPPORTED];
     /**< SD clock source and clock inversion  */
     SDFM_ClkSourceParms   clkPrms[3];
     /**< Over current OSR  */
-    uint16_t ComFilterOsr;
+    uint16_t comFilterOsr;
     /**< Normal current OSR  */
-    uint16_t FilterOsr;
+    uint16_t filterOsr;
     /**< over current enable field */
-    uint8_t en_com;
+    uint8_t enComparator;
     /**< output samples base address*/
     uint32_t samplesBaseAddress;
     /**<enable fast detect*/
-    uint8_t en_fd;
+    uint8_t enFastDetect;
     /**<Fast detect configuration field*/
     uint8_t fastDetect[NUM_SD_CH][NUM_FD_FIELD];
     /**<Zero Cross enable field*/
-    uint8_t en_zc;
+    uint8_t enZeroCross;
     /**<Zero cross threshold*/
     uint32_t zcThr[NUM_CH_SUPPORTED];
 } SdfmPrms;

examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/app_sdfm.c

@@ -338,7 +338,7 @@ void sdfm_main(void *args)
     DebugP_log("EPWM Configured!\r\n");
      
     /*Configure IEP for SD clock when phase delay calculaton is enabled*/
-    if(gTestSdfmPrms.phase_delay)
+    if(gTestSdfmPrms.phaseDelay)
     {
         /*config ICSSG1 IEP0 */
         init_IEP0_SYNC();

examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.c

@@ -189,31 +189,31 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
         return SDFM_ERR_INIT_SDFM;
     }
 
-    hSdfm->pru_core_clk = pSdfmPrms->pru_clock;
+    hSdfm->pruCoreClk = pSdfmPrms->pruClock;
-    hSdfm->iep_clock = pSdfmPrms->G0iep_clock; 
+    hSdfm->iepClock = pSdfmPrms->g0IepClock; 
-    hSdfm->sdfm_clock = pSdfmPrms->sd_clock; 
+    hSdfm->sdfmClock = pSdfmPrms->sdClock; 
     hSdfm->sampleOutputInterface = (SDFM_SampleOutInterface *)(pSdfmPrms->samplesBaseAddress);
     uint32_t sampleOutputInterfaceGlobalAddr = CPU0_BTCM_SOCVIEW(pSdfmPrms->samplesBaseAddress);
     hSdfm->p_sdfm_interface->sampleBufferBaseAdd = sampleOutputInterfaceGlobalAddr;
-    hSdfm->iep_inc = 1; /* Default IEP increment 1 */
+    hSdfm->iepInc = 1; /* Default IEP increment 1 */
 
     uint8_t acc_filter = 0; //SINC3 filter
     uint8_t ecap_divider = 0x0F; //IEP at 300MHz: SD clock = 300/15=20Mhz
     
-    if(pSdfmPrms->phase_delay)
+    if(pSdfmPrms->phaseDelay)
     {
-        SDFM_measurePhaseCompensation(hSdfm, pSdfmPrms->G1iep_clock);
+        SDFM_measurePhaseCompensation(hSdfm, pSdfmPrms->g1IepClock);
     }
     
 
     /*configure IEP count for one epwm period*/
-    SDFM_configIepCount(hSdfm, pSdfmPrms->epwm_out_freq);
+    SDFM_configIepCount(hSdfm, pSdfmPrms->epwmOutFreq);
 
     /*configure ecap as PWM code for generate 20 MHz sdfm clock*/
     SDFM_configEcap(hSdfm, ecap_divider);
 
     /*set Noraml current OSR */
-    SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->FilterOsr);
+    SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->filterOsr);
      
 
     /*below configuration for all three channel*/
@@ -222,7 +222,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
         SDFM_setEnableChannel(hSdfm, SDFM_CH);
 
         /*set comparator osr or Over current osr*/
-        SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->ComFilterOsr);
+        SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->comFilterOsr);
 
         /*set ACC source or filter type*/
         SDFM_configDataFilter(hSdfm, SDFM_CH, acc_filter);
@@ -231,13 +231,13 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
         SDFM_selectClockSource(hSdfm, SDFM_CH, pSdfmPrms->clkPrms[SDFM_CH]);
 
         /*set threshold values */
-        SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->threshold_parms[SDFM_CH]);
+        SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->thresholdParms[SDFM_CH]);
-        if(pSdfmPrms->en_fd)
+        if(pSdfmPrms->enFastDetect)
         {
             /*Fast detect configuration */
             SDFM_configFastDetect(hSdfm, SDFM_CH, pSdfmPrms->fastDetect[SDFM_CH]);
         }
-        if(pSdfmPrms->en_com)
+        if(pSdfmPrms->enComparator)
         {
             SDFM_enableComparator(hSdfm, SDFM_CH);       
         }
@@ -246,7 +246,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
             SDFM_disableComparator(hSdfm, SDFM_CH);
         }
 
-        if(pSdfmPrms->en_zc)
+        if(pSdfmPrms->enZeroCross)
         {
             SDFM_enableZeroCrossDetection(hSdfm, SDFM_CH, pSdfmPrms->zcThr[SDFM_CH]);
         }
@@ -257,7 +257,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm,  PRU
     SDFM_configGpioPins(hSdfm);
 
     SDFM_setSampleTriggerTime(hSdfm, pSdfmPrms->firstSampTrigTime);
-    if(pSdfmPrms->en_second_update)
+    if(pSdfmPrms->enSecondUpdate)
     {
         SDFM_enableDoubleSampling(hSdfm, pSdfmPrms->secondSampTrigTime);
     }

examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.h

@@ -141,41 +141,41 @@ typedef struct SdfmPrms_s
     /**<ICSSG pru Slice ID*/
     uint8_t icssgSliceId;
     /**< PRU_CORE_CLOCK*/
-    uint32_t pru_clock;
+    uint32_t pruClock;
     /**< IEP clock value */
-    uint32_t G0iep_clock;
+    uint32_t g0IepClock;
     /**< IEP clock value */
-    uint32_t G1iep_clock;
+    uint32_t g1IepClock;
     /**< Sigma delta input clock value  */
-    uint32_t sd_clock;
+    uint32_t sdClock;
     /**< double update enable field  */
-    uint8_t en_second_update;
+    uint8_t enSecondUpdate;
     /**< First normal current sample trigger time  */
     float firstSampTrigTime;
     /**< First normal current sample trigger time  */
     float secondSampTrigTime;
     /**< output freq. of EPWM0  */
-    uint32_t epwm_out_freq;
+    uint32_t epwmOutFreq;
     /**< Over current threshold parameters  */
-    SDFM_ThresholdParms   threshold_parms[NUM_CH_SUPPORTED];
+    SDFM_ThresholdParms   thresholdParms[NUM_CH_SUPPORTED];
     /**< SD clock source and clock inversion  */
     SDFM_ClkSourceParms   clkPrms[3];
     /**< Over current OSR  */
-    uint16_t ComFilterOsr;
+    uint16_t comFilterOsr;
     /**< Normal current OSR  */
-    uint16_t FilterOsr;
+    uint16_t filterOsr;
     /**< over current enable field */
-    uint8_t en_com;
+    uint8_t enComparator ;
     /**< output samples base address*/
     uint32_t samplesBaseAddress;
     /**<enable fast detect*/
-    uint8_t en_fd;
+    uint8_t enFastDetect;
     /**<Fast detect configuration field*/
     uint8_t fastDetect[NUM_SD_CH][NUM_FD_FIELD];
     /**<Phase delay enbale */
-    uint8_t phase_delay;
+    uint8_t phaseDelay;
     /**<Zero Cross enable field*/
-    uint8_t en_zc;
+    uint8_t enZeroCross;
     /**<Zero cross threshold*/
     uint32_t zcThr[NUM_CH_SUPPORTED];
 } SdfmPrms;

source/current_sense/sdfm/driver/sdfm_drv.c

@@ -116,7 +116,7 @@ sdfm_handle SDFM_init(uint8_t pru_id, uint8_t coreId)
 void SDFM_configIepCount(sdfm_handle h_sdfm, uint32_t epwm_out_freq)
 {
     /*; IEP0 default increment=1*/
-    h_sdfm->p_sdfm_interface->sdfm_cfg_iep_ptr.iep_inc_value = h_sdfm->iep_inc;
+    h_sdfm->p_sdfm_interface->sdfm_cfg_iep_ptr.iep_inc_value = h_sdfm->iepInc;
     /*
      IEP0 CMP0 count to simulate EPWM (FOC loop) period:
      - IEP frequency = 300 MHz
@@ -124,7 +124,7 @@ void SDFM_configIepCount(sdfm_handle h_sdfm, uint32_t epwm_out_freq)
      - Simulated EPWM frequency = 8e3
      CMP0 = 300e6/1/8e3 = 37500 = 0x927C
     */
-    uint32_t cnt_epwm_prd = h_sdfm->iep_clock/epwm_out_freq;
+    uint32_t cnt_epwm_prd = h_sdfm->iepClock/epwm_out_freq;
     h_sdfm->p_sdfm_interface->sdfm_cfg_iep_ptr.cnt_epwm_prd = cnt_epwm_prd;
 
 }
@@ -158,7 +158,7 @@ void SDFM_setCompFilterThresholds(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_Thresh
 void SDFM_setSampleTriggerTime(sdfm_handle h_sdfm, float samp_trig_time)
 {   /*convert sample time into IEP count*/
     /*samp time in us */
-    int32_t count = (h_sdfm->iep_clock /1000000)*((float)samp_trig_time);
+    int32_t count = (h_sdfm->iepClock /1000000)*((float)samp_trig_time);
     h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.first_samp_trig_time = count;
 
 
@@ -170,7 +170,7 @@ void SDFM_enableDoubleSampling(sdfm_handle h_sdfm, float samp_trig_time)
     /*Enable double normal current sampling*/
     h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.en_double_nc_sampling = 1;
     /*Second sample point*/
-    int32_t count = (h_sdfm->iep_clock /1000000)*((float)samp_trig_time);
+    int32_t count = (h_sdfm->iepClock /1000000)*((float)samp_trig_time);
     h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.second_samp_trig_time = count;
 }
 
@@ -253,8 +253,8 @@ void SDFM_setFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t nc_osr)
     
     /*IEP0 counts in normal current sampling period*/
     uint16_t count;
-    uint32_t iep_freq = h_sdfm->iep_clock;
+    uint32_t iep_freq = h_sdfm->iepClock;
-    uint32_t sd_clock = h_sdfm->sdfm_clock;
+    uint32_t sd_clock = h_sdfm->sdfmClock;
     count = (int)((float)nc_osr*((float)iep_freq/(float)sd_clock));
     h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.nc_prd_iep_cnt = count;
 }
@@ -421,18 +421,18 @@ float SDFM_measureClockPhaseDelay(sdfm_handle h_sdfm, uint16_t clkEdg)
    if(nEdge == clkEdg)
    {
       /*PRU cycles for half SD clock period*/
-      uint32_t pruCycles = ceil(((float)h_sdfm->pru_core_clk)/(2*h_sdfm->sdfm_clock));
+      uint32_t pruCycles = ceil(((float)h_sdfm->pruCoreClk)/(2*h_sdfm->sdfmClock));
       h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay = pruCycles - temp;
    }
    else
    {
       /*PRU cycles for one SD clock period*/
-      uint32_t pruCycles = ceil((float)(h_sdfm->pru_core_clk/(h_sdfm->sdfm_clock)));
+      uint32_t pruCycles = ceil((float)(h_sdfm->pruCoreClk/(h_sdfm->sdfmClock)));
       h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay = pruCycles - temp;
 
    }
     /*conversion from PRU cycle to ns */
-    float phaseDelay =  ((float)h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay * 1000000000)/h_sdfm->pru_core_clk;
+    float phaseDelay =  ((float)h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay * 1000000000)/h_sdfm->pruCoreClk;
     return phaseDelay;
 }
 uint8_t SDFM_getHighThresholdStatus(sdfm_handle h_sdfm, uint8_t chNum)

source/current_sense/sdfm/firmware/firmware_version.h

@@ -62,7 +62,7 @@ FIRMWARE_VERSION_REVISION	.set		0x01
 ;  bit23..16		major number
 FIRMWARE_VERSION_MAJOR	.set			0x01
 ;  bit15..0		minor number
-FIRMWARE_VERSION_MINOR	.set			0x0000
+FIRMWARE_VERSION_MINOR	.set			0x0001
 
 ICSS_FIRMWARE_RELEASE_1	.set	((FIRMWARE_DEVICE_AM64x_AM243x << 8) | (FIRMWARE_PROTOCOL_TYPE_SDFM << 0))
 ICSS_FIRMWARE_RELEASE_2	.set ((FIRMWARE_VERSION_RELEASE << 31) | (FIRMWARE_VERSION_REVISION << 24) | (FIRMWARE_VERSION_MAJOR << 16) | (FIRMWARE_VERSION_MINOR << 0))

source/current_sense/sdfm/firmware/sdfm.asm

@@ -152,15 +152,6 @@ CHECK_SDFM_EN:
 ; Perform initialization
 ;
 INIT_SDFM:
-    ; Enable XIN/XOUT shifting.
-    ; Used for context & SD state save/restore in TM tasks.
-    LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_CFG, ICSSG_CFG_SPPC, 1
-    .if $isdefed("SDFM_PRU_CORE")
-    SET     TEMP_REG0, TEMP_REG0, XFR_SHIFT_EN_BN   ; ICSSG_SPP_REG:XFR_SHIFT_EN=1
-    .elseif $isdefed("SDFM_RTU_CORE")
-    SET     TEMP_REG0, TEMP_REG0, RTU_XFR_SHIFT_EN   ; ICSSG_SPP_REG:RTU_XFR_SHIFT_EN=1
-    .endif
-    SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_CFG, ICSSG_CFG_SPPC, 1  
 
     ;Initialize Task Manager
     JAL     RET_ADDR_REG, FN_TM_INIT 
@@ -168,10 +159,8 @@ INIT_SDFM:
     ;Enable Task Manager
     M_PRU_TM_ENABLE  
 
-    .if $isdefed("SDFM_PRU_CORE") 
     ;Initialize IEP0
     JAL     RET_ADDR_REG, FN_IEP0_INIT
-    .endif
    
     .if $isdefed("SDFM_PRU_CORE")
     ;Initialize SD mode
@@ -794,11 +783,22 @@ FN_NC_LOOP_TASK:
     MOV     R18.b0, R30.b3                  ; save T0 SD channel select
     xchg    BANK_CTXT_NC, &R1, 4*18     
 
-    .if $isdefed("SDFM_PRU_CORE") ; no IEP config on RTU
+    .if $isdefed("SDFM_RTU_CORE")
-    ; Clear IEP0 CMP4 event
+    ; Clear IEP0 CMP7 event
-    LDI		TEMP_REG0.b0, 0x10
+    LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    SET		TEMP_REG0.t7
     SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
-    .endif 
+    .elseif $isdefed("SDFM_PRU_CORE")
+    ; Clear IEP0 CMP4 event
+    LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    SET		TEMP_REG0.t4
+    SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    ; Clear IEP0 CMP8 event
+    LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    SET		TEMP_REG0.t8
+    SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    .endif ; SDFM_TXPRU_CORE
     
     .if $isdefed("DEBUG_CODE")
     ;Debug code  :GPIO HIGH
@@ -876,38 +876,69 @@ WAIT_SAMPLE_COUNT_INCR:
     ;continuous mode check
     QBBC    TRIGGER_MODE, EN_DOUBLE_UPDATE, 1
 
-    .if $isdefed("SDFM_PRU_CORE")
+    ;update IEP0 CMP
-    ;update IEP0 CMP4
     LBBO    &TEMP_REG0, SDFM_CFG_BASE_PTR_REG, SDFM_CFG_NC_PRD_IEP_CNT_OFFSET, 4
-    LBCO    &TEMP_REG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4 ;
+    .if $isdefed("SDFM_RTU_CORE")
+    ;update IEP0 CMP7
+    LBCO    &TEMP_REG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP7_REG0, 4 
+    .elseif $isdefed("SDFM_PRU_CORE")
+    ;update IEP0 CMP4
+    LBCO    &TEMP_REG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4 
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    ;update IEP0 CMP4
+    LBCO    &TEMP_REG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP8_REG0, 4   
+    .endif ; SDFM_TXPRU_CORE
     ADD     TEMP_REG0, TEMP_REG1, TEMP_REG0
     ;read iep counter maximum value
     LDI     TEMP_REG1, 0
     LBBO    &TEMP_REG1, SDFM_CFG_BASE_PTR_REG, SDFM_CFG_IEP_CFG_SIM_EPWM_PRD_OFFSET, 4
     QBLE    UPDATE_CMP_FOR_IEP_RESET,  TEMP_REG0, TEMP_REG1
-    ;update Cmp4 with old value + next sample time value
-    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4
     JMP     END_CMP_UPDATE
 UPDATE_CMP_FOR_IEP_RESET:
     ;Update cmp4 according to iep reset
     SUB      TEMP_REG0, TEMP_REG0, TEMP_REG1
-    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4
 END_CMP_UPDATE:
-    .endif
+    .if $isdefed("SDFM_RTU_CORE")
+    ;update Cmp7 with old value + next sample time value
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP7_REG0, 4
+    .elseif $isdefed("SDFM_PRU_CORE")
+    ;update Cmp4 with old value + next sample time value
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    ;update Cmp8 with old value + next sample time value
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP8_REG0, 4
+    .endif ; SDFM_TXPRU_CORE
+    
     JMP  END_RESET_NC_FRAME
 
 TRIGGER_MODE:
     ;Check NC sample count
     QBLE    RESET_NC_FRAME, SAMP_CNT_REG, NC_SAMP_CNT-1
-    .if $isdefed("SDFM_PRU_CORE") ; no IEP config on RTU
     ; NC sample count < NC_SAMP_CNT-1
     ; Add configured IEP count for NC OSR
     ; IEP0 CMP4_reg = cmp4_reg + NC_OSR*IEP_CLOCK* SD_cycle
     LBBO    &TEMP_REG0, SDFM_CFG_BASE_PTR_REG,  SDFM_CFG_NC_PRD_IEP_CNT_OFFSET,  4
-    LBCO    &TEMP_REG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4 ;
+    .if $isdefed("SDFM_RTU_CORE")
+    ;update IEP0 CMP7
+    LBCO    &TEMP_REG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP7_REG0, 4 
+    .elseif $isdefed("SDFM_PRU_CORE")
+    ;update IEP0 CMP4
+    LBCO    &TEMP_REG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4 
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    ;update IEP0 CMP4
+    LBCO    &TEMP_REG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP8_REG0, 4   
+    .endif ; SDFM_TXPRU_CORE
     ADD     TEMP_REG0, TEMP_REG1, TEMP_REG0
+    .if $isdefed("SDFM_RTU_CORE")
+    ;update Cmp7 with old value + next sample time value
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP7_REG0, 4
+    .elseif $isdefed("SDFM_PRU_CORE")
+    ;update Cmp4 with old value + next sample time value
     SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4
-    .endif    
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    ;update Cmp8 with old value + next sample time value
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP8_REG0, 4
+    .endif ; SDFM_TXPRU_CORE    
     ADD     SAMP_CNT_REG, SAMP_CNT_REG, 1   ; increment NC sample count    
     QBA     NRESET_NC_FRAME
      
@@ -915,19 +946,33 @@ RESET_NC_FRAME:
     ; Set IEP CMP$ value: IEP_CMP4_REG1:REG0 = 0:TRIG_SAMPLE_TIME
     QBBS    FIRST_NC_SAMPLE, SAMP_NAME, 0
     QBBC    FIRST_NC_SAMPLE, EN_DOUBLE_UPDATE, 0 ;check double update is enable
-    .if $isdefed("SDFM_PRU_CORE") ; no IEP config on RTU
     LBBO    &TEMP_REG0, SDFM_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_SECOND_TRIG_SAMPLE_TIME, 4
     SUB     TEMP_REG0, TEMP_REG0, IEP_DEFAULT_INC ; subtract IEP default increment since IEP counts 0...CMP4
+    .if $isdefed("SDFM_RTU_CORE")
+    ;update Cmp7 with old value + next sample time value
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP7_REG0, 4
+    .elseif $isdefed("SDFM_PRU_CORE")
+    ;update Cmp4 with old value + next sample time value
     SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4
-    .endif
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    ;update Cmp8 with old value + next sample time value
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP8_REG0, 4
+    .endif ; SDFM_TXPRU_CORE   
     LDI    SAMP_NAME, 1 ;clear sample name for first sample
     QBA     END_RESET_NC_FRAME
 FIRST_NC_SAMPLE:
-    .if $isdefed("SDFM_PRU_CORE") ; no IEP config on RTU
     LBBO    &TEMP_REG0, SDFM_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_FIRST_TRIG_SAMPLE_TIME, 4
     SUB     TEMP_REG0, TEMP_REG0, IEP_DEFAULT_INC ; subtract IEP default increment since IEP counts 0...CMP4
+    .if $isdefed("SDFM_RTU_CORE")
+    ;update Cmp7 with old value + next sample time value
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP7_REG0, 4
+    .elseif $isdefed("SDFM_PRU_CORE")
+    ;update Cmp4 with old value + next sample time value
     SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4
-    .endif
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    ;update Cmp8 with old value + next sample time value
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP8_REG0, 4
+    .endif ; SDFM_TXPRU_CORE   
     LDI    SAMP_NAME, 0 ; update for Second sample
 END_RESET_NC_FRAME:
     LDI     SAMP_CNT_REG, 0 ; reset NC sample count
@@ -972,8 +1017,15 @@ FN_TM_INIT:
     .endif
 
     ; Set Task triggers
-    ; set T1_S1 trigger to IEP0 CMP4 event = 20
+    ; set T1_S1 trigger to IEP0 CMP4 event = 20, CMP7 = 23, CMP8 = 24
-    LDI     TEMP_REG0.w0, (COMP4_EVENT_NUMBER<<COMP_EVENT_FOUR_SIFT)
+    .if $isdefed("SDFM_RTU_CORE")
+    LDI     TEMP_REG0.w0, (CMP7_EVENT_NUMBER<<CMP_EVENT_BIT_SHIFT)
+    .elseif $isdefed("SDFM_PRU_CORE")
+    LDI     TEMP_REG0.w0, (CMP4_EVENT_NUMBER<<CMP_EVENT_BIT_SHIFT)
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    LDI     TEMP_REG0.w0, (CMP8_EVENT_NUMBER<<CMP_EVENT_BIT_SHIFT)
+    .endif ; SDFM_TXPRU_CORE   
+    
     .if $isdefed("SDFM_TXPRU_CORE")
     SBCO    &TEMP_REG0.w0, C28, TASKS_MGR_TS1_GEN_CFG1, 2
     .else
@@ -986,6 +1038,8 @@ FN_TM_INIT:
 ; Initialize IEP0.
 ;
 FN_IEP0_INIT:
+    
+    .if $isdefed("SDFM_PRU_CORE")
     ; Disable IEP0 counter
     LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1
     AND     TEMP_REG0.b0, TEMP_REG0.b0, 0xFE
@@ -994,9 +1048,26 @@ FN_IEP0_INIT:
     LDI     TEMP_REG0, 0
     SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_COUNT_REG1, 4
     SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_COUNT_REG0, 4  
-    ; Clear IEP0  CMP4 events
+    .endif
-    LDI		TEMP_REG0.b0, 0x10
+
+    .if $isdefed("SDFM_RTU_CORE")
+    ; Clear IEP0 CMP7 event
+    LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    SET		TEMP_REG0.t7
     SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    .elseif $isdefed("SDFM_PRU_CORE")
+    ; Clear IEP0 CMP4 event
+    LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    SET		TEMP_REG0.t4
+    SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    ; Clear IEP0 CMP8 event
+    LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    SET		TEMP_REG0.t8
+    SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
+    .endif ; SDFM_TXPRU_CORE 
+    
+    .if $isdefed("SDFM_PRU_CORE")
     ; Write IEP0 default increment
     LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1
     AND     TEMP_REG0.b0, TEMP_REG0.b0, 0x0F
@@ -1006,7 +1077,25 @@ FN_IEP0_INIT:
     LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0_0x100, ICSSG_IEP_PWM_REG, 1
     SET     TEMP_REG0.b0.t0 ; IEP_PWM_REG:PWM0_RST_CNT_EN = 1, enable IEP0 counter reset on EPWM0 SYNCO event
     SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0_0x100, ICSSG_IEP_PWM_REG, 1    
-    ; Initialize Trigger sample time for OC
+    .endif
+
+    
+    .if $isdefed("SDFM_RTU_CORE")
+    ; Initialize Trigger sample time for NC
+    ; Set IEP0 CMP7 value: IEP0_CMP7_REG1:REG0 = 0:TRIG_SAMPLE_TIME
+    LDI     TEMP_REG0, 0
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP7_REG1, 4
+    LBBO    &TEMP_REG0, SDFM_CFG_BASE_PTR_REG,  FW_REG_SDFM_CFG_FIRST_TRIG_SAMPLE_TIME,  4
+    LDI     TEMP_REG1, SDFM_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_MASK
+    AND     TEMP_REG0, TEMP_REG1, TEMP_REG0
+    SUB     TEMP_REG0, TEMP_REG0, IEP_DEFAULT_INC ; subtract IEP default increment since IEP counts 0...CMP0
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP7_REG0, 4
+    ;Enable IEP0 CMP7
+    LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_CFG_REG, 2  ; TR0 <- Byte0 ICSSG_CMP_CFG_REG
+    SET     TEMP_REG0.t8    ; CMP_EN[8]=1 => CMP7 enabled
+    SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_CFG_REG, 2  ; TR0 -> ICSSG_CMP_CFG_REG Byte0 
+    .elseif $isdefed("SDFM_PRU_CORE")
+    ; Initialize Trigger sample time for NC
     ; Set IEP0 CMP4 value: IEP0_CMP4_REG1:REG0 = 0:TRIG_SAMPLE_TIME
     LDI     TEMP_REG0, 0
     SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG1, 4
@@ -1019,6 +1108,21 @@ FN_IEP0_INIT:
     LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_CFG_REG, 1  ; TR0 <- Byte0 ICSSG_CMP_CFG_REG
     SET     TEMP_REG0.t5    ; CMP_EN[5]=1 => CMP4 enabled
     SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_CFG_REG, 1  ; TR0 -> ICSSG_CMP_CFG_REG Byte0  
+    .elseif $isdefed("SDFM_TXPRU_CORE")
+    ; Initialize Trigger sample time for NC
+    ; Set IEP0 CMP8 value: IEP0_CMP8_REG1:REG0 = 0:TRIG_SAMPLE_TIME
+    LDI     TEMP_REG0, 0
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP8_REG1, 4
+    LBBO    &TEMP_REG0, SDFM_CFG_BASE_PTR_REG,  FW_REG_SDFM_CFG_FIRST_TRIG_SAMPLE_TIME,  4
+    LDI     TEMP_REG1, SDFM_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_MASK
+    AND     TEMP_REG0, TEMP_REG1, TEMP_REG0
+    SUB     TEMP_REG0, TEMP_REG0, IEP_DEFAULT_INC ; subtract IEP default increment since IEP counts 0...CMP0
+    SBCO    &TEMP_REG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP8_REG0, 4
+    ; Enable IEP0 CMP4
+    LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_CFG_REG, 2  ; TR0 <- Byte0 ICSSG_CMP_CFG_REG
+    SET     TEMP_REG0.t9    ; CMP_EN[9]=1 => CMP4 enabled
+    SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_CFG_REG, 2  ; TR0 -> ICSSG_CMP_CFG_REG Byte0 
+    .endif ; SDFM_TXPRU_CORE
 
     JMP     RET_ADDR_REG
 

source/current_sense/sdfm/firmware/sdfm.h

@@ -198,8 +198,12 @@ PRUn_FD_ZERO_MAX_LIMIT_i_SHIFT  .set 17
 PRUn_FD_ZERO_MAX_LIMIT_i_MASK   .set 0x1F
 
 ;MACRO FOR TASK MANAGER
-COMP4_EVENT_NUMBER        .set  20
+CMP4_EVENT_NUMBER        .set  20
-COMP_EVENT_FOUR_SIFT          .set  8
+CMP_EVENT_BIT_SHIFT          .set  8
+CMP7_EVENT_NUMBER        .set  23
+CMP8_EVENT_NUMBER        .set  24
+
+
 
 ; ICSSG_PRUn_SD_SAMPLE_SIZE_REGi
 ;   n: {0,1}, PRU ID
@@ -230,12 +234,16 @@ ICSSG_IEP_CMP0_REG0             .set 0x0078 ; Compare 0 Low Register
 ICSSG_IEP_CMP0_REG1             .set 0x007C ; Compare 0 High Register
 ICSSG_IEP_CMP1_REG0             .set 0x0080 ; Compare 1 Low Register
 ICSSG_IEP_CMP1_REG1             .set 0x0084 ; Compare 1 High Register
-ICSSG_IEP_CMP2_REG0             .set 0x0088 ; Compare 1 Low Register
+ICSSG_IEP_CMP2_REG0             .set 0x0088 ; Compare 2 Low Register
-ICSSG_IEP_CMP2_REG1             .set 0x008C ; Compare 1 High Register
+ICSSG_IEP_CMP2_REG1             .set 0x008C ; Compare 2 High Register
-ICSSG_IEP_CMP3_REG0             .set 0x0090 ; Compare 1 Low Register
+ICSSG_IEP_CMP3_REG0             .set 0x0090 ; Compare 3 Low Register
-ICSSG_IEP_CMP3_REG1             .set 0x0094 ; Compare 1 High Register
+ICSSG_IEP_CMP3_REG1             .set 0x0094 ; Compare 3 High Register
 ICSSG_IEP_CMP4_REG0             .set 0x0098 ; compare 4 low Register
 ICSSG_IEP_CMP4_REG1             .set 0x009C ; compare 4 High Register
+ICSSG_IEP_CMP7_REG0             .set 0x00B0 ; compare 7 low Register
+ICSSG_IEP_CMP7_REG1             .set 0x00B4 ; compare 7 High Register
+ICSSG_IEP_CMP8_REG0             .set 0x00C0 ; compare 4 low Register
+ICSSG_IEP_CMP8_REG1             .set 0x00C4 ; compare 4 High Register
 ICSSG_IEP_PWM_REG               .set 0x0008 ; PWM Sync Out Register, offset from 0x100
 ; ICSSG_IEP_GLOBAL_CFG_REG:CNT_ENABLE_BN
 CNT_ENABLE_BN                   .set 0

source/current_sense/sdfm/firmware/sdfm_bin.h

@@ -70,7 +70,7 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x10000000,
 0xf1171701,
 0xc9000104,
-0x23022c99,
+0x23022a99,
 0x1d00e1e1,
 0xe1171701,
 0xf1171701,
@@ -79,12 +79,9 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0xcf0001fd,
 0x1f00e1e1,
 0xe1011701,
-0x91340401,
+0x23017099,
-0x1f01e1e1,
-0x81340401,
-0x23017399,
 0x32800000,
-0x23017a99,
+0x23017799,
 0x240c00c2,
 0x24000082,
 0xf1021701,
@@ -108,13 +105,13 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x0b04e1e1,
 0x110fe1e2,
 0x10020256,
-0x23019499,
+0x23019299,
-0x2302c199,
+0x2302bf99,
-0x23019899,
+0x23019699,
-0x2301c899,
+0x2301c699,
-0x23020d99,
+0x23020b99,
 0x1f19fefe,
-0x23021699,
+0x23021499,
 0x240fffd5,
 0x24ffff95,
 0x240000d4,
@@ -140,7 +137,7 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x81001a01,
 0xf114179a,
 0xd1009a02,
-0x21005800,
+0x21005500,
 0xc9019a3f,
 0x10161602,
 0x09020202,
@@ -168,12 +165,12 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1291701,
-0x21007e00,
+0x21007b00,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1281701,
-0x21007e00,
+0x21007b00,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -231,12 +228,12 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1591701,
-0x2100bd00,
+0x2100ba00,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1581701,
-0x2100bd00,
+0x2100ba00,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -294,12 +291,12 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1891701,
-0x2100fc00,
+0x2100f900,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1881701,
-0x2100fc00,
+0x2100f900,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -334,7 +331,8 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x24000000,
 0x107e7e12,
 0x2f852381,
-0x24001001,
+0x91741a01,
+0x1f04e1e1,
 0x81741a01,
 0x240260de,
 0x10000000,
@@ -382,18 +380,17 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x10f5e8e8,
 0x0108f4e1,
 0xe0e13788,
-0xc9017c0c,
+0xc9017c0b,
 0xf1b83781,
 0x91983a82,
 0x00e1e2e1,
 0x240000e2,
 0xf1083782,
-0x58e2e103,
+0x58e2e102,
-0x81983a81,
+0x21015100,
-0x21015500,
 0x04e2e1e1,
 0x81983a81,
-0x21016800,
+0x21016500,
 0x59031c07,
 0xf1b83781,
 0x91983a82,
@@ -425,7 +422,7 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x10000000,
 0x24000b01,
 0x81000a01,
-0x24011781,
+0x24011481,
 0x810c0a81,
 0x24140081,
 0x81380a81,
@@ -436,7 +433,8 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x240000e1,
 0x81143a81,
 0x81103a81,
-0x24001001,
+0x91741a01,
+0x1f04e1e1,
 0x81741a01,
 0x91001a01,
 0x110f0101,
@@ -477,7 +475,7 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x2101c300,
+0x2101c100,
 0x6836030d,
 0xf14e1701,
 0xc9010417,
@@ -490,7 +488,7 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x2101c300,
+0x2101c100,
 0x6856030c,
 0xf17e1701,
 0xc902040a,
@@ -532,7 +530,7 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x21020800,
+0x21020600,
 0x68360314,
 0x24000081,
 0xf16c1741,
@@ -552,7 +550,7 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x21020800,
+0x21020600,
 0x68560313,
 0x24000081,
 0xf19c1741,
@@ -637,53 +635,53 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0xd1005f2e,
 0x01018282,
 0x1b01e3e3,
-0x21027600,
+0x21027400,
 0x01028282,
 0x1b02e3e3,
-0x21027600,
+0x21027400,
 0x01038282,
 0x1b03e3e3,
-0x21027600,
+0x21027400,
 0x01048282,
 0x1b04e3e3,
-0x21027600,
+0x21027400,
 0x01058282,
 0x1b05e3e3,
-0x21027600,
+0x21027400,
 0x01068282,
 0x1b06e3e3,
-0x21027600,
+0x21027400,
 0x01078282,
 0x1b07e3e3,
-0x21027600,
+0x21027400,
 0x01088282,
 0x1b08e3e3,
-0x21027600,
+0x21027400,
 0x01098282,
 0x1b09e3e3,
-0x21027600,
+0x21027400,
 0x010a8282,
 0x1b0ae3e3,
-0x21027600,
+0x21027400,
 0x010b8282,
 0x1b0be3e3,
-0x21027600,
+0x21027400,
 0x010c8282,
 0x1b0ce3e3,
-0x21027600,
+0x21027400,
 0x010d8282,
 0x1b0de3e3,
-0x21027600,
+0x21027400,
 0x010e8282,
 0x1b0ee3e3,
-0x21027600,
+0x21027400,
 0x010f8282,
 0x1b0fe3e3,
-0x21027600,
+0x21027400,
 0x01108282,
 0x1b10e3e3,
 0x24000042,
-0x2102bc00,
+0x2102ba00,
 0x240000e2,
 0x31070043,
 0xd1011f00,
@@ -706,49 +704,49 @@ const uint32_t SDFM_PRU0_image_0[] = {
 0xc9005f2e,
 0x01018282,
 0x1b01e3e3,
-0x2102bb00,
+0x2102b900,
 0x01028282,
 0x1b02e3e3,
-0x2102bb00,
+0x2102b900,
 0x01038282,
 0x1b03e3e3,
-0x2102bb00,
+0x2102b900,
 0x01048282,
 0x1b04e3e3,
-0x2102bb00,
+0x2102b900,
 0x01058282,
 0x1b05e3e3,
-0x2102bb00,
+0x2102b900,
 0x01068282,
 0x1b06e3e3,
-0x2102bb00,
+0x2102b900,
 0x01078282,
 0x1b07e3e3,
-0x2102bb00,
+0x2102b900,
 0x01088282,
 0x1b08e3e3,
-0x2102bb00,
+0x2102b900,
 0x01098282,
 0x1b09e3e3,
-0x2102bb00,
+0x2102b900,
 0x010a8282,
 0x1b0ae3e3,
-0x2102bb00,
+0x2102b900,
 0x010b8282,
 0x1b0be3e3,
-0x2102bb00,
+0x2102b900,
 0x010c8282,
 0x1b0ce3e3,
-0x2102bb00,
+0x2102b900,
 0x010d8282,
 0x1b0de3e3,
-0x2102bb00,
+0x2102b900,
 0x010e8282,
 0x1b0ee3e3,
-0x2102bb00,
+0x2102b900,
 0x010f8282,
 0x1b0fe3e3,
-0x2102bb00,
+0x2102b900,
 0x01108282,
 0x1b10e3e3,
 0x24000142,

source/current_sense/sdfm/firmware/sdfm_pru_bin.h

@@ -70,7 +70,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x10000000,
 0xf1171701,
 0xc9000104,
-0x23022c99,
+0x23022a99,
 0x1d00e1e1,
 0xe1171701,
 0xf1171701,
@@ -79,12 +79,9 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0xcf0001fd,
 0x1f00e1e1,
 0xe1011701,
-0x91340401,
+0x23017099,
-0x1f01e1e1,
-0x81340401,
-0x23017399,
 0x32800000,
-0x23017a99,
+0x23017799,
 0x240c00c2,
 0x24000082,
 0xf1021701,
@@ -108,13 +105,13 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x0b04e1e1,
 0x110fe1e2,
 0x10020256,
-0x23019499,
+0x23019299,
-0x2302c199,
+0x2302bf99,
-0x23019899,
+0x23019699,
-0x2301c899,
+0x2301c699,
-0x23020d99,
+0x23020b99,
 0x1f19fefe,
-0x23021699,
+0x23021499,
 0x240fffd5,
 0x24ffff95,
 0x240000d4,
@@ -140,7 +137,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x81001a01,
 0xf114179a,
 0xd1009a02,
-0x21005800,
+0x21005500,
 0xc9019a3f,
 0x10161602,
 0x09020202,
@@ -168,12 +165,12 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1291701,
-0x21007e00,
+0x21007b00,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1281701,
-0x21007e00,
+0x21007b00,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -231,12 +228,12 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1591701,
-0x2100bd00,
+0x2100ba00,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1581701,
-0x2100bd00,
+0x2100ba00,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -294,12 +291,12 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1891701,
-0x2100fc00,
+0x2100f900,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1881701,
-0x2100fc00,
+0x2100f900,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -334,7 +331,8 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x24000000,
 0x107e7e12,
 0x2f852381,
-0x24001001,
+0x91741a01,
+0x1f04e1e1,
 0x81741a01,
 0x240e60de,
 0x10000000,
@@ -382,18 +380,17 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x10f5e8e8,
 0x0108f4e1,
 0xe0e13788,
-0xc9017c0c,
+0xc9017c0b,
 0xf1b83781,
 0x91983a82,
 0x00e1e2e1,
 0x240000e2,
 0xf1083782,
-0x58e2e103,
+0x58e2e102,
-0x81983a81,
+0x21015100,
-0x21015500,
 0x04e2e1e1,
 0x81983a81,
-0x21016800,
+0x21016500,
 0x59031c07,
 0xf1b83781,
 0x91983a82,
@@ -425,7 +422,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x10000000,
 0x24000b01,
 0x81000a01,
-0x24011781,
+0x24011481,
 0x810c0a81,
 0x24140081,
 0x81380a81,
@@ -436,7 +433,8 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x240000e1,
 0x81143a81,
 0x81103a81,
-0x24001001,
+0x91741a01,
+0x1f04e1e1,
 0x81741a01,
 0x91001a01,
 0x110f0101,
@@ -477,7 +475,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x2101c300,
+0x2101c100,
 0x6836030d,
 0xf14e1701,
 0xc9010417,
@@ -490,7 +488,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x2101c300,
+0x2101c100,
 0x6856030c,
 0xf17e1701,
 0xc902040a,
@@ -532,7 +530,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x21020800,
+0x21020600,
 0x68360314,
 0x24000081,
 0xf16c1741,
@@ -552,7 +550,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x21020800,
+0x21020600,
 0x68560313,
 0x24000081,
 0xf19c1741,
@@ -637,53 +635,53 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0xd1005f2e,
 0x01018282,
 0x1b01e3e3,
-0x21027600,
+0x21027400,
 0x01028282,
 0x1b02e3e3,
-0x21027600,
+0x21027400,
 0x01038282,
 0x1b03e3e3,
-0x21027600,
+0x21027400,
 0x01048282,
 0x1b04e3e3,
-0x21027600,
+0x21027400,
 0x01058282,
 0x1b05e3e3,
-0x21027600,
+0x21027400,
 0x01068282,
 0x1b06e3e3,
-0x21027600,
+0x21027400,
 0x01078282,
 0x1b07e3e3,
-0x21027600,
+0x21027400,
 0x01088282,
 0x1b08e3e3,
-0x21027600,
+0x21027400,
 0x01098282,
 0x1b09e3e3,
-0x21027600,
+0x21027400,
 0x010a8282,
 0x1b0ae3e3,
-0x21027600,
+0x21027400,
 0x010b8282,
 0x1b0be3e3,
-0x21027600,
+0x21027400,
 0x010c8282,
 0x1b0ce3e3,
-0x21027600,
+0x21027400,
 0x010d8282,
 0x1b0de3e3,
-0x21027600,
+0x21027400,
 0x010e8282,
 0x1b0ee3e3,
-0x21027600,
+0x21027400,
 0x010f8282,
 0x1b0fe3e3,
-0x21027600,
+0x21027400,
 0x01108282,
 0x1b10e3e3,
 0x24000042,
-0x2102bc00,
+0x2102ba00,
 0x240000e2,
 0x31070043,
 0xd1011f00,
@@ -706,49 +704,49 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0xc9005f2e,
 0x01018282,
 0x1b01e3e3,
-0x2102bb00,
+0x2102b900,
 0x01028282,
 0x1b02e3e3,
-0x2102bb00,
+0x2102b900,
 0x01038282,
 0x1b03e3e3,
-0x2102bb00,
+0x2102b900,
 0x01048282,
 0x1b04e3e3,
-0x2102bb00,
+0x2102b900,
 0x01058282,
 0x1b05e3e3,
-0x2102bb00,
+0x2102b900,
 0x01068282,
 0x1b06e3e3,
-0x2102bb00,
+0x2102b900,
 0x01078282,
 0x1b07e3e3,
-0x2102bb00,
+0x2102b900,
 0x01088282,
 0x1b08e3e3,
-0x2102bb00,
+0x2102b900,
 0x01098282,
 0x1b09e3e3,
-0x2102bb00,
+0x2102b900,
 0x010a8282,
 0x1b0ae3e3,
-0x2102bb00,
+0x2102b900,
 0x010b8282,
 0x1b0be3e3,
-0x2102bb00,
+0x2102b900,
 0x010c8282,
 0x1b0ce3e3,
-0x2102bb00,
+0x2102b900,
 0x010d8282,
 0x1b0de3e3,
-0x2102bb00,
+0x2102b900,
 0x010e8282,
 0x1b0ee3e3,
-0x2102bb00,
+0x2102b900,
 0x010f8282,
 0x1b0fe3e3,
-0x2102bb00,
+0x2102b900,
 0x01108282,
 0x1b10e3e3,
 0x24000142,

source/current_sense/sdfm/firmware/sdfm_rtu_bin.h

@@ -70,7 +70,7 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x10000000,
 0xf1171701,
 0xc9000104,
-0x23020a99,
+0x23021299,
 0x1d00e1e1,
 0xe1171701,
 0xf1171701,
@@ -79,11 +79,9 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0xcf0001fd,
 0x1f00e1e1,
 0xe1011701,
-0x91340401,
+0x23016599,
-0x1f03e1e1,
-0x81340401,
-0x23015199,
 0x32800000,
+0x23016c99,
 0xf1021701,
 0x51010104,
 0x240002d8,
@@ -100,12 +98,12 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x0b04e1e1,
 0x110fe1e2,
 0x10020256,
-0x23017299,
+0x23017a99,
-0x23017699,
+0x23017e99,
-0x2301a699,
+0x2301ae99,
-0x2301eb99,
+0x2301f399,
 0x1f19fefe,
-0x2301f499,
+0x2301fc99,
 0x240fffd5,
 0x24ffff95,
 0x240000d4,
@@ -128,7 +126,7 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x10c1c1da,
 0xf114179a,
 0xd1009a02,
-0x21004c00,
+0x21004a00,
 0xc9019a3f,
 0x10161602,
 0x09020202,
@@ -156,12 +154,12 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1291701,
-0x21007200,
+0x21007000,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1281701,
-0x21007200,
+0x21007000,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -219,12 +217,12 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1591701,
-0x2100b100,
+0x2100af00,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1581701,
-0x2100b100,
+0x2100af00,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -282,12 +280,12 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1891701,
-0x2100f000,
+0x2100ee00,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1881701,
-0x2100f000,
+0x2100ee00,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -322,6 +320,9 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x24000000,
 0x107e7e12,
 0x2f852381,
+0x91741a01,
+0x1f07e1e1,
+0x81741a01,
 0x240260de,
 0x10000000,
 0x11ffffe2,
@@ -368,15 +369,34 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x10f5e8e8,
 0x0108f4e1,
 0xe0e13788,
-0xc9017c02,
+0xc9017c0b,
+0xf1b83781,
+0x91b03a82,
+0x00e1e2e1,
+0x240000e2,
+0xf1083782,
+0x58e2e102,
 0x21014600,
-0x59031c03,
+0x04e2e1e1,
+0x81b03a81,
+0x21015a00,
+0x59031c07,
+0xf1b83781,
+0x91b03a82,
+0x00e1e2e1,
+0x81b03a81,
 0x01011c1c,
-0x7900000b,
+0x79000011,
-0xd1003c04,
+0xd1003c07,
-0xc9007c03,
+0xc9007c06,
+0xf1b43781,
+0x0501e1e1,
+0x81b03a81,
 0x2400013c,
-0x79000002,
+0x79000005,
+0xf1b03781,
+0x0501e1e1,
+0x81b03a81,
 0x2400003c,
 0x2400001c,
 0xf0f4b784,
@@ -391,36 +411,24 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x10000000,
 0x24000b01,
 0x81000a01,
-0x24010b81,
+0x24010981,
 0x810c0a81,
-0x24140081,
+0x24170081,
 0x81380a81,
 0x20990000,
-0x91001a01,
+0x91741a01,
-0x11fe0101,
+0x1f07e1e1,
-0x81001a01,
-0x240000e1,
-0x81143a81,
-0x81103a81,
-0x24001001,
 0x81741a01,
-0x91001a01,
-0x110f0101,
-0x13100101,
-0x81001a01,
-0x91080801,
-0x1f000101,
-0x81080801,
 0x240000e1,
-0x819c3a81,
+0x81b43a81,
 0xf1b03781,
 0x24ffffe2,
 0x10e1e2e1,
 0x0501e1e1,
-0x81983a81,
+0x81b03a81,
-0x91701a01,
+0x91701a81,
-0x1f05e1e1,
+0x1f08e1e1,
-0x81701a01,
+0x81701a81,
 0x20990000,
 0x24000000,
 0x2effa381,
@@ -443,7 +451,7 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x2101a100,
+0x2101a900,
 0x6836030d,
 0xf14e1701,
 0xc9010417,
@@ -456,7 +464,7 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x2101a100,
+0x2101a900,
 0x6856030c,
 0xf17e1701,
 0xc902040a,
@@ -498,7 +506,7 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x2101e600,
+0x2101ee00,
 0x68360314,
 0x24000081,
 0xf16c1741,
@@ -518,7 +526,7 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x2101e600,
+0x2101ee00,
 0x68560313,
 0x24000081,
 0xf19c1741,
@@ -603,53 +611,53 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0xd1005f2e,
 0x01018282,
 0x1b01e3e3,
-0x21025400,
+0x21025c00,
 0x01028282,
 0x1b02e3e3,
-0x21025400,
+0x21025c00,
 0x01038282,
 0x1b03e3e3,
-0x21025400,
+0x21025c00,
 0x01048282,
 0x1b04e3e3,
-0x21025400,
+0x21025c00,
 0x01058282,
 0x1b05e3e3,
-0x21025400,
+0x21025c00,
 0x01068282,
 0x1b06e3e3,
-0x21025400,
+0x21025c00,
 0x01078282,
 0x1b07e3e3,
-0x21025400,
+0x21025c00,
 0x01088282,
 0x1b08e3e3,
-0x21025400,
+0x21025c00,
 0x01098282,
 0x1b09e3e3,
-0x21025400,
+0x21025c00,
 0x010a8282,
 0x1b0ae3e3,
-0x21025400,
+0x21025c00,
 0x010b8282,
 0x1b0be3e3,
-0x21025400,
+0x21025c00,
 0x010c8282,
 0x1b0ce3e3,
-0x21025400,
+0x21025c00,
 0x010d8282,
 0x1b0de3e3,
-0x21025400,
+0x21025c00,
 0x010e8282,
 0x1b0ee3e3,
-0x21025400,
+0x21025c00,
 0x010f8282,
 0x1b0fe3e3,
-0x21025400,
+0x21025c00,
 0x01108282,
 0x1b10e3e3,
 0x24000042,
-0x21029a00,
+0x2102a200,
 0x240000e2,
 0x31070043,
 0xd1011f00,
@@ -672,49 +680,49 @@ const uint32_t pru_SDFM_RTU0_image_0[] = {
 0xc9005f2e,
 0x01018282,
 0x1b01e3e3,
-0x21029900,
+0x2102a100,
 0x01028282,
 0x1b02e3e3,
-0x21029900,
+0x2102a100,
 0x01038282,
 0x1b03e3e3,
-0x21029900,
+0x2102a100,
 0x01048282,
 0x1b04e3e3,
-0x21029900,
+0x2102a100,
 0x01058282,
 0x1b05e3e3,
-0x21029900,
+0x2102a100,
 0x01068282,
 0x1b06e3e3,
-0x21029900,
+0x2102a100,
 0x01078282,
 0x1b07e3e3,
-0x21029900,
+0x2102a100,
 0x01088282,
 0x1b08e3e3,
-0x21029900,
+0x2102a100,
 0x01098282,
 0x1b09e3e3,
-0x21029900,
+0x2102a100,
 0x010a8282,
 0x1b0ae3e3,
-0x21029900,
+0x2102a100,
 0x010b8282,
 0x1b0be3e3,
-0x21029900,
+0x2102a100,
 0x010c8282,
 0x1b0ce3e3,
-0x21029900,
+0x2102a100,
 0x010d8282,
 0x1b0de3e3,
-0x21029900,
+0x2102a100,
 0x010e8282,
 0x1b0ee3e3,
-0x21029900,
+0x2102a100,
 0x010f8282,
 0x1b0fe3e3,
-0x21029900,
+0x2102a100,
 0x01108282,
 0x1b10e3e3,
 0x24000142,

source/current_sense/sdfm/firmware/sdfm_txpru_bin.h

@@ -70,7 +70,7 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x10000000,
 0xf1171701,
 0xc9000104,
-0x23020999,
+0x23021299,
 0x1d00e1e1,
 0xe1171701,
 0xf1171701,
@@ -79,10 +79,9 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0xcf0001fd,
 0x1f00e1e1,
 0xe1011701,
-0x91340401,
+0x23016599,
-0x81340401,
-0x23015099,
 0x32800000,
+0x23016c99,
 0xf1021701,
 0x51010104,
 0x240002d8,
@@ -99,12 +98,12 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x0b04e1e1,
 0x110fe1e2,
 0x10020256,
-0x23017199,
+0x23017a99,
-0x23017599,
+0x23017e99,
-0x2301a599,
+0x2301ae99,
-0x2301ea99,
-0x1f19fefe,
 0x2301f399,
+0x1f19fefe,
+0x2301fc99,
 0x240fffd5,
 0x24ffff95,
 0x240000d4,
@@ -127,7 +126,7 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x10c1c1da,
 0xf114179a,
 0xd1009a02,
-0x21004b00,
+0x21004a00,
 0xc9019a3f,
 0x10161602,
 0x09020202,
@@ -155,12 +154,12 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1291701,
-0x21007100,
+0x21007000,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1281701,
-0x21007100,
+0x21007000,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -218,12 +217,12 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1591701,
-0x2100b000,
+0x2100af00,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1581701,
-0x2100b000,
+0x2100af00,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -281,12 +280,12 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x58e3fb09,
 0x24000001,
 0xe1891701,
-0x2100ef00,
+0x2100ee00,
 0x1f034141,
 0x80e22481,
 0x24000101,
 0xe1881701,
-0x2100ef00,
+0x2100ee00,
 0x1f034141,
 0x80e22481,
 0x24000101,
@@ -321,6 +320,9 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x24000000,
 0x107e7e12,
 0x2f852381,
+0x91741a01,
+0x1f08e1e1,
+0x81741a01,
 0x241a60de,
 0x10000000,
 0x11ffffe2,
@@ -367,15 +369,34 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x10f5e8e8,
 0x0108f4e1,
 0xe0e13788,
-0xc9017c02,
+0xc9017c0b,
-0x21014500,
+0xf1b83781,
-0x59031c03,
+0x91c03a82,
+0x00e1e2e1,
+0x240000e2,
+0xf1083782,
+0x58e2e102,
+0x21014600,
+0x04e2e1e1,
+0x81c03a81,
+0x21015a00,
+0x59031c07,
+0xf1b83781,
+0x91c03a82,
+0x00e1e2e1,
+0x81c03a81,
 0x01011c1c,
-0x7900000b,
+0x79000011,
-0xd1003c04,
+0xd1003c07,
-0xc9007c03,
+0xc9007c06,
+0xf1b43781,
+0x0501e1e1,
+0x81c03a81,
 0x2400013c,
-0x79000002,
+0x79000005,
+0xf1b03781,
+0x0501e1e1,
+0x81c03a81,
 0x2400003c,
 0x2400001c,
 0xf0f4b784,
@@ -390,36 +411,24 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x10000000,
 0x24000b01,
 0x81001c01,
-0x24010a81,
+0x24010981,
 0x810c1c81,
-0x24140081,
+0x24180081,
 0x81381c81,
 0x20990000,
-0x91001a01,
+0x91741a01,
-0x11fe0101,
+0x1f08e1e1,
-0x81001a01,
-0x240000e1,
-0x81143a81,
-0x81103a81,
-0x24001001,
 0x81741a01,
-0x91001a01,
-0x110f0101,
-0x13100101,
-0x81001a01,
-0x91080801,
-0x1f000101,
-0x81080801,
 0x240000e1,
-0x819c3a81,
+0x81c43a81,
 0xf1b03781,
 0x24ffffe2,
 0x10e1e2e1,
 0x0501e1e1,
-0x81983a81,
+0x81c03a81,
-0x91701a01,
+0x91701a81,
-0x1f05e1e1,
+0x1f09e1e1,
-0x81701a01,
+0x81701a81,
 0x20990000,
 0x24000000,
 0x2effa381,
@@ -442,7 +451,7 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x2101a000,
+0x2101a900,
 0x6836030d,
 0xf14e1701,
 0xc9010417,
@@ -455,7 +464,7 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x2101a000,
+0x2101a900,
 0x6856030c,
 0xf17e1701,
 0xc902040a,
@@ -497,7 +506,7 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x2101e500,
+0x2101ee00,
 0x68360314,
 0x24000081,
 0xf16c1741,
@@ -517,7 +526,7 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x2101e500,
+0x2101ee00,
 0x68560313,
 0x24000081,
 0xf19c1741,
@@ -602,53 +611,53 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0xd1005f2e,
 0x01018282,
 0x1b01e3e3,
-0x21025300,
+0x21025c00,
 0x01028282,
 0x1b02e3e3,
-0x21025300,
+0x21025c00,
 0x01038282,
 0x1b03e3e3,
-0x21025300,
+0x21025c00,
 0x01048282,
 0x1b04e3e3,
-0x21025300,
+0x21025c00,
 0x01058282,
 0x1b05e3e3,
-0x21025300,
+0x21025c00,
 0x01068282,
 0x1b06e3e3,
-0x21025300,
+0x21025c00,
 0x01078282,
 0x1b07e3e3,
-0x21025300,
+0x21025c00,
 0x01088282,
 0x1b08e3e3,
-0x21025300,
+0x21025c00,
 0x01098282,
 0x1b09e3e3,
-0x21025300,
+0x21025c00,
 0x010a8282,
 0x1b0ae3e3,
-0x21025300,
+0x21025c00,
 0x010b8282,
 0x1b0be3e3,
-0x21025300,
+0x21025c00,
 0x010c8282,
 0x1b0ce3e3,
-0x21025300,
+0x21025c00,
 0x010d8282,
 0x1b0de3e3,
-0x21025300,
+0x21025c00,
 0x010e8282,
 0x1b0ee3e3,
-0x21025300,
+0x21025c00,
 0x010f8282,
 0x1b0fe3e3,
-0x21025300,
+0x21025c00,
 0x01108282,
 0x1b10e3e3,
 0x24000042,
-0x21029900,
+0x2102a200,
 0x240000e2,
 0x31070043,
 0xd1011f00,
@@ -671,49 +680,49 @@ const uint32_t pru_SDFM_TXPRU0_image_0[] = {
 0xc9005f2e,
 0x01018282,
 0x1b01e3e3,
-0x21029800,
+0x2102a100,
 0x01028282,
 0x1b02e3e3,
-0x21029800,
+0x2102a100,
 0x01038282,
 0x1b03e3e3,
-0x21029800,
+0x2102a100,
 0x01048282,
 0x1b04e3e3,
-0x21029800,
+0x2102a100,
 0x01058282,
 0x1b05e3e3,
-0x21029800,
+0x2102a100,
 0x01068282,
 0x1b06e3e3,
-0x21029800,
+0x2102a100,
 0x01078282,
 0x1b07e3e3,
-0x21029800,
+0x2102a100,
 0x01088282,
 0x1b08e3e3,
-0x21029800,
+0x2102a100,
 0x01098282,
 0x1b09e3e3,
-0x21029800,
+0x2102a100,
 0x010a8282,
 0x1b0ae3e3,
-0x21029800,
+0x2102a100,
 0x010b8282,
 0x1b0be3e3,
-0x21029800,
+0x2102a100,
 0x010c8282,
 0x1b0ce3e3,
-0x21029800,
+0x2102a100,
 0x010d8282,
 0x1b0de3e3,
-0x21029800,
+0x2102a100,
 0x010e8282,
 0x1b0ee3e3,
-0x21029800,
+0x2102a100,
 0x010f8282,
 0x1b0fe3e3,
-0x21029800,
+0x2102a100,
 0x01108282,
 0x1b10e3e3,
 0x24000142,

source/current_sense/sdfm/include/sdfm_drv.h

@@ -354,11 +354,11 @@ typedef struct SDFM_SampleOutInterface_s
 typedef struct SDFM_s {
     /**< PRU ID */
     PRUICSS_Handle gPruIcssHandle;
-    uint8_t pru_id;
+    uint8_t pruId;
-    uint32_t sdfm_clock;
+    uint32_t sdfmClock;
-    uint32_t iep_clock;
+    uint32_t iepClock;
-    uint32_t pru_core_clk;
+    uint32_t pruCoreClk;
-    uint8_t  iep_inc;
+    uint8_t  iepInc;
     SDFM_Interface * p_sdfm_interface;
     SDFM_SampleOutInterface *sampleOutputInterface;
     void *pruss_cfg;