From ccda32786b63a6a68aa9c3b898df5553fb22cb67 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 31 Oct 2023 13:54:50 +0530 Subject: [PATCH] am64x/am243x: hdsl: Fix SSUM bit in EVENT_S register - Bit should be set if summary is non-zero Fixes: PINDSW-6629 Signed-off-by: Dhaval Khandla --- .../position_sense/hdsl/firmware/defines.inc | 2 +- .../hdsl_master_icssg_multichannel_ch0_bin.h | 44 ++++++------- ...ter_icssg_multichannel_ch0_sync_mode_bin.h | 62 +++++++++--------- .../hdsl_master_icssg_multichannel_ch1_bin.h | 63 ++++++++++--------- ...ter_icssg_multichannel_ch1_sync_mode_bin.h | 63 ++++++++++--------- .../hdsl/firmware/transport.asm | 24 +++---- 6 files changed, 132 insertions(+), 126 deletions(-) diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc index e336c9f..6423ab2 100644 --- a/source/position_sense/hdsl/firmware/defines.inc +++ b/source/position_sense/hdsl/firmware/defines.inc @@ -34,7 +34,7 @@ ; bit7..4 major number FIRMWARE_VERSION_MAJOR .set 0x0 ; bit3..0 minor number -FIRMWARE_VERSION_MINOR .set 0x7 +FIRMWARE_VERSION_MINOR .set 0x8 ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h index 90a931d..2c19c76 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h @@ -51,9 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - const uint32_t Hiperface_DSL2_0_RTU_0[] = { -0x21077f00, +0x21078000, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -116,7 +115,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x23032cd1, 0x1d03c4c4, 0x2302cbd1, -0x23059c9d, +0x23059d9d, 0x05014545, 0x51074514, 0x49004502, @@ -690,7 +689,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21050f00, +0x21051000, 0xd1077905, 0xd104ff00, 0xd703ffff, @@ -747,7 +746,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x106d6d79, 0x2400027b, 0x21035700, -0x21043a00, +0x21043b00, 0xd104ff00, 0xd703ffff, 0xd1074d03, @@ -863,7 +862,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x21062f00, +0x21063000, 0x20d10000, 0x117f6666, 0xc9066604, @@ -941,7 +940,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x2400017b, 0x2102b700, 0x2400017b, -0x21043a00, +0x21043b00, 0xd104ff00, 0xd703ffff, 0xd1077903, @@ -969,7 +968,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x21043a00, +0x21043b00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1031,7 +1030,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x23060fd1, +0x230610d1, 0x10535300, 0x10333320, 0x10131340, @@ -1114,24 +1113,25 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81361800, 0x91081821, 0x10210001, -0x5100010b, +0x51000106, 0x91043880, 0x1f068080, 0x81041880, 0xc8c0c002, 0x2400229f, +0x91361800, +0x91503802, +0x51000009, +0x1f060202, +0x1f060242, 0x913d1880, 0x1f060000, 0x813d1880, 0xc9062002, 0x2400269f, -0x91361800, -0x91503802, +0x79000003, 0x1d060202, 0x1d060242, -0x51000003, -0x1f060202, -0x1f060242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1237,7 +1237,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x230771d1, +0x230772d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1250,7 +1250,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x230771d1, +0x230772d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1293,7 +1293,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x230771d1, +0x230772d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1536,7 +1536,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x2305f6d1, +0x2305f7d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1560,7 +1560,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x2305f6d1, +0x2305f7d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1650,7 +1650,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000700, +0x24000800, 0x810b1800, 0x81441800, 0x2eff8383, @@ -1975,5 +1975,5 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x21062f00}; +0x21063000}; diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h index 826740a..431e917 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h @@ -51,9 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { -0x2107c100, +0x2107c400, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -116,7 +115,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x23034bd1, 0x1d03c4c4, 0x2302ddd1, -0x23060e9d, +0x2306119d, 0x05014545, 0x51074514, 0x49004502, @@ -704,7 +703,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21058300, +0x21058400, 0xd1077905, 0xd104ff00, 0xd703ffff, @@ -761,7 +760,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x106d6d79, 0x2400027b, 0x21037800, -0x2104ae00, +0x2104af00, 0xd104ff00, 0xd703ffff, 0xd1074d03, @@ -894,7 +893,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x2106a100, +0x2106a400, 0x20d10000, 0x117f6666, 0xc9066604, @@ -1057,7 +1056,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400017b, 0x2102c500, 0x2400017b, -0x2104ae00, +0x2104af00, 0xd104ff00, 0xd703ffff, 0xd1077903, @@ -1085,7 +1084,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x2104ae00, +0x2104af00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1147,7 +1146,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x230681d1, +0x230684d1, 0x10535300, 0x10333320, 0x10131340, @@ -1230,24 +1229,25 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81361800, 0x91081821, 0x10210001, -0x5100010b, +0x51000106, 0x91043880, 0x1f068080, 0x81041880, 0xc8c0c002, 0x2400229f, +0x91361800, +0x91503802, +0x51000009, +0x1f060202, +0x1f060242, 0x913d1880, 0x1f060000, 0x813d1880, 0xc9062002, 0x2400269f, -0x91361800, -0x91503802, +0x79000003, 0x1d060202, 0x1d060242, -0x51000003, -0x1f060202, -0x1f060242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1353,7 +1353,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x2307b3d1, +0x2307b6d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1366,7 +1366,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x2307b3d1, +0x2307b6d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1409,7 +1409,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x2307b3d1, +0x2307b6d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1464,7 +1464,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xc9027a02, 0x01081b1b, 0x2102c500, -0xc901c460, +0xc901c462, 0x24001031, 0x91001800, 0xc9060007, @@ -1473,7 +1473,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x79000057, +0x79000059, 0x91351800, 0xc9060007, 0x1d060000, @@ -1481,7 +1481,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x7900004f, +0x79000051, 0xc909c41c, 0x05041b1b, 0x490c1b06, @@ -1489,7 +1489,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x110f3131, 0x69001b02, 0x1d09c4c4, -0x79000047, +0x79000049, 0xc9077a08, 0x905a1831, 0xc9021b03, @@ -1509,7 +1509,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x14809a9a, 0x69101b02, 0x15ff1a1a, -0x79000033, +0x79000035, 0x91401800, 0x513f0013, 0x91531840, @@ -1529,9 +1529,9 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x2400201b, 0x2400403b, 0x1f09c4c4, -0x7900001f, +0x79000021, 0x912c1800, -0xc900001d, +0xc900001f, 0x1d000000, 0x812c1800, 0x1f09c4c4, @@ -1539,9 +1539,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x1d010000, 0x81511800, 0x91283881, +0x1f070101, 0x1001017a, 0x2400101b, -0xc9050102, +0xc9050103, +0x1f074141, 0x01101b1b, 0x0b031b00, 0x8fc4d801, @@ -1650,7 +1652,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x230668d1, +0x23066bd1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1674,7 +1676,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd703ffff, 0x2400001e, 0x2400001e, -0x230668d1, +0x23066bd1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1764,7 +1766,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000700, +0x24000800, 0x810b1800, 0x81441800, 0x2eff8383, @@ -2041,5 +2043,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2106a100}; +0x2106a400}; diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h index d162a80..e031ecb 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h @@ -1,4 +1,3 @@ - /* * * Copyright (c) 2021-2023, Texas Instruments Incorporated @@ -52,9 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - const uint32_t Hiperface_DSL2_0_PRU_0[] = { -0x21077e00, +0x21078100, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -117,7 +115,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x23032cd1, 0x1d03c4c4, 0x2302cbd1, -0x23059a9d, +0x23059d9d, 0x05014545, 0x51074514, 0x49004502, @@ -691,7 +689,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21050f00, +0x21051000, 0xd1077905, 0xd10cff00, 0xd70bffff, @@ -748,7 +746,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x106d6d79, 0x2400027b, 0x21035700, -0x21043a00, +0x21043b00, 0xd10cff00, 0xd70bffff, 0xd1074d03, @@ -864,7 +862,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x21062d00, +0x21063000, 0x20d10000, 0x117f6666, 0xc9066604, @@ -942,7 +940,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400017b, 0x2102b700, 0x2400017b, -0x21043a00, +0x21043b00, 0xd10cff00, 0xd70bffff, 0xd1077903, @@ -970,7 +968,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x21043a00, +0x21043b00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1032,7 +1030,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x23060dd1, +0x230610d1, 0x10535300, 0x10333320, 0x10131340, @@ -1115,24 +1113,25 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81361800, 0x91081821, 0x10210001, -0x5100010b, +0x51000106, 0x91043880, 0x1f068080, 0x81041880, 0xc8c0c002, 0x2400229f, +0x91361800, +0x91503802, +0x51000009, +0x1f060202, +0x1f060242, 0x913d1880, 0x1f060000, 0x813d1880, 0xc9062002, 0x2400269f, -0x91361800, -0x91503802, +0x79000003, 0x1d060202, 0x1d060242, -0x51000003, -0x1f060202, -0x1f060242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1238,7 +1237,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x230770d1, +0x230773d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1251,7 +1250,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x230770d1, +0x230773d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1294,7 +1293,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x230770d1, +0x230773d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1349,7 +1348,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xc9027a02, 0x01081b1b, 0x2102b700, -0xc901c460, +0xc901c462, 0x24001031, 0x91001800, 0xc9060007, @@ -1358,7 +1357,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x79000057, +0x79000059, 0x91351800, 0xc9060007, 0x1d060000, @@ -1366,7 +1365,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x7900004f, +0x79000051, 0xc909c41c, 0x05041b1b, 0x490c1b06, @@ -1374,7 +1373,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x110f3131, 0x69001b02, 0x1d09c4c4, -0x79000047, +0x79000049, 0xc9077a08, 0x905a1831, 0xc9021b03, @@ -1394,7 +1393,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x14809a9a, 0x69101b02, 0x15ff1a1a, -0x79000033, +0x79000035, 0x91401800, 0x513f0013, 0x91531840, @@ -1414,9 +1413,9 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x2400201b, 0x2400403b, 0x1f09c4c4, -0x7900001f, +0x79000021, 0x912c1800, -0xc900001d, +0xc900001f, 0x1d000000, 0x812c1800, 0x1f09c4c4, @@ -1424,9 +1423,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x1d010000, 0x81511800, 0x91283881, +0x1f070101, 0x1001017a, 0x2400101b, -0xc9050102, +0xc9050103, +0x1f074141, 0x01101b1b, 0x0b031b00, 0x8fc4d801, @@ -1535,7 +1536,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x2305f4d1, +0x2305f7d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1559,7 +1560,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x2305f4d1, +0x2305f7d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1650,7 +1651,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000700, +0x24000800, 0x810b1800, 0x81441800, 0x2eff8383, @@ -1975,5 +1976,5 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x21062d00}; +0x21063000}; diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h index 590a7c6..6bf8094 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h @@ -1,4 +1,3 @@ - /* * * Copyright (c) 2021-2023, Texas Instruments Incorporated @@ -52,9 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { -0x2107c200, +0x2107c500, 0x2eff8f8e, 0x24000725, 0x24041e8d, @@ -117,7 +115,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x23034bd1, 0x1d03c4c4, 0x2302ddd1, -0x23060e9d, +0x2306119d, 0x05014545, 0x51074514, 0x49004502, @@ -705,7 +703,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x79000002, 0x2400ff1e, 0x09017979, -0x21058300, +0x21058400, 0xd1077905, 0xd10cff00, 0xd70bffff, @@ -762,7 +760,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x106d6d79, 0x2400027b, 0x21037800, -0x2104ae00, +0x2104af00, 0xd10cff00, 0xd70bffff, 0xd1074d03, @@ -895,7 +893,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x91a91800, 0x01010000, 0x81a91800, -0x2106a100, +0x2106a400, 0x20d10000, 0x117f6666, 0xc9066604, @@ -1058,7 +1056,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400017b, 0x2102c500, 0x2400017b, -0x2104ae00, +0x2104af00, 0xd10cff00, 0xd70bffff, 0xd1077903, @@ -1086,7 +1084,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400ff1e, 0x09017979, 0x2400017b, -0x2104ae00, +0x2104af00, 0x2eff838e, 0x24003f00, 0x81401800, @@ -1148,7 +1146,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x686e5303, 0x24000019, 0x79000002, -0x230681d1, +0x230684d1, 0x10535300, 0x10333320, 0x10131340, @@ -1231,24 +1229,25 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81361800, 0x91081821, 0x10210001, -0x5100010b, +0x51000106, 0x91043880, 0x1f068080, 0x81041880, 0xc8c0c002, 0x2400229f, +0x91361800, +0x91503802, +0x51000009, +0x1f060202, +0x1f060242, 0x913d1880, 0x1f060000, 0x813d1880, 0xc9062002, 0x2400269f, -0x91361800, -0x91503802, +0x79000003, 0x1d060202, 0x1d060242, -0x51000003, -0x1f060202, -0x1f060242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1354,7 +1353,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x24003001, 0xd1066b0e, 0x2400010d, -0x2307b4d1, +0x2307b7d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -1367,7 +1366,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81531800, 0x7900003b, 0x2400020d, -0x2307b4d1, +0x2307b7d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -1410,7 +1409,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x2307b4d1, +0x2307b7d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1465,7 +1464,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xc9027a02, 0x01081b1b, 0x2102c500, -0xc901c460, +0xc901c462, 0x24001031, 0x91001800, 0xc9060007, @@ -1474,7 +1473,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x79000057, +0x79000059, 0x91351800, 0xc9060007, 0x1d060000, @@ -1482,7 +1481,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x7900004f, +0x79000051, 0xc909c41c, 0x05041b1b, 0x490c1b06, @@ -1490,7 +1489,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x110f3131, 0x69001b02, 0x1d09c4c4, -0x79000047, +0x79000049, 0xc9077a08, 0x905a1831, 0xc9021b03, @@ -1510,7 +1509,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x14809a9a, 0x69101b02, 0x15ff1a1a, -0x79000033, +0x79000035, 0x91401800, 0x513f0013, 0x91531840, @@ -1530,9 +1529,9 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x2400201b, 0x2400403b, 0x1f09c4c4, -0x7900001f, +0x79000021, 0x912c1800, -0xc900001d, +0xc900001f, 0x1d000000, 0x812c1800, 0x1f09c4c4, @@ -1540,9 +1539,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x1d010000, 0x81511800, 0x91283881, +0x1f070101, 0x1001017a, 0x2400101b, -0xc9050102, +0xc9050103, +0x1f074141, 0x01101b1b, 0x0b031b00, 0x8fc4d801, @@ -1651,7 +1652,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x230668d1, +0x23066bd1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1675,7 +1676,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd70bffff, 0x2400001e, 0x2400001e, -0x230668d1, +0x23066bd1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1766,7 +1767,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000700, +0x24000800, 0x810b1800, 0x81441800, 0x2eff8383, @@ -2043,5 +2044,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2106a100}; +0x2106a400}; diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 1c21811..9fd7884 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -375,26 +375,28 @@ transport_skip_vpos_update: ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ update_events_no_int7: -;set event_s and generate interrupt_s +summary_no_int: + +; Update SUM and SSUM bits in ONLINE_STATUS registers + lbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM, 1 + lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 + qbeq online_status_sum_clear, REG_TMP0.b0, 0x00 + set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM + set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM +;set SSUM in EVENT_S and generate interrupt_s lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SSUM ;save events sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 qbbc update_events_no_int17, REG_TMP0.b1, EVENT_S_SSUM ; generate interrupt_s - ldi r31.w0, PRU0_ARM_IRQ4 + ldi r31.w0, PRU0_ARM_IRQ4 update_events_no_int17: -summary_no_int: - -; Update SUM and SSUM bits in ONLINE_STATUS registers - lbco ®_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM, 1 - lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 + qba online_status_sum_save +online_status_sum_clear: clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM - qbeq online_status_sum_clear, REG_TMP0.b0, 0x00 - set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM - set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM -online_status_sum_clear: +online_status_sum_save: sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 ;restore REG_FNC.w0 content