diff --git a/docs/MS_TI_AM64x_EVM_3-AXIS_INTERFACE_BOARD_SCH_REV_E1.pdf b/docs/MS_TI_AM64x_EVM_3-AXIS_INTERFACE_BOARD_SCH_REV_E1.pdf new file mode 100644 index 0000000..5e89242 Binary files /dev/null and b/docs/MS_TI_AM64x_EVM_3-AXIS_INTERFACE_BOARD_SCH_REV_E1.pdf differ diff --git a/docs/TIDEP-01015Rev E1.1(001)_Sch.pdf b/docs/TIDEP-01015Rev E1.1(001)_Sch.pdf new file mode 100644 index 0000000..5feb138 Binary files /dev/null and b/docs/TIDEP-01015Rev E1.1(001)_Sch.pdf differ diff --git a/docs_src/docs/api_guide/components/current_sense/current_sense.md b/docs_src/docs/api_guide/components/current_sense/current_sense.md index fa8f4d4..3b33223 100644 --- a/docs_src/docs/api_guide/components/current_sense/current_sense.md +++ b/docs_src/docs/api_guide/components/current_sense/current_sense.md @@ -10,8 +10,8 @@ ICSS %SDFM is a sigma delta interface for phase current measurement in high perf ## Features Supported - 3 %SDFM channels on single PRU core - - Normal current (NC) for data read: SINC3 filter with OSR 16 to 256 - - Overcurrent (OC) for comparator: free running SINC3 filter with OSR 16 to 256 + - Normal Current (NC) for data read: SINC3 filter with Over-samping Ratio (OSR) 16 to 256 + - Over-current (OC) for comparator: free running SINC3 filter with OSR 16 to 256 - Event generation(ARM interrupt for data read from DMEM, GPIO toggle for high and low thresholds) - Single level High and Low threshold comparator - Trigger based normal current sampling diff --git a/docs_src/docs/api_guide/components/current_sense/sdfm_design.md b/docs_src/docs/api_guide/components/current_sense/sdfm_design.md index 2d632fa..82b5a1a 100644 --- a/docs_src/docs/api_guide/components/current_sense/sdfm_design.md +++ b/docs_src/docs/api_guide/components/current_sense/sdfm_design.md @@ -28,12 +28,12 @@ SDK example uses the %SDFM hardware capability in Slice 1 of PRU-ICSSG0. Details - Normal current OSR + Normal Current Over-samping Ratio (OSR) 64 Tested with 16, 32, 64, 128 and 256 - Over current OSR + Over Current OSR 16 Tested with 16, 32, 64, 128 and 256 @@ -77,12 +77,12 @@ Following section describes the firmware implementation of Sigma Delta Decimatio ##### Normal Curent (NC) -This section describes normal current implementation. +This section describes normal current implementation. There are two different variations of normal current. - Trigger based: It starts execution when the trigger point is acquired (first time CMP event hits) and performs four continuous samplings to bring the accumulator and differntiator registers to stable state for the configured normal current OSR. Initially the CMP register is configured with the first sample trigger start time and then until the next third continuous normal current sample it is updated with the normal current OSR sampling time. At the end of the fourth normal current sample again, it is updated with the second sample start time if double update is enabled otherwise with the first sample trigger start time. -- Continuous sampling: It starts execution when the first time CMP event hits. Every time it updates CMP event register with the normal current OSR sampling time for next continuous sample, store sample values in DMEM and trigger R5 intrrupt. +- Continuous sampling: It starts execution when the first time CMP event hits. Every time it updates CMP event register with the normal current OSR sampling time for next continuous sample, store sample values in DMEM and trigger R5 interrupt. \image html SDFM_NC_FLOW_CHART.png "Normal Current" @@ -97,13 +97,13 @@ Normal current sampling is done twice in one EPWM cycle. \image html SDFM_Double_update.PNG "Double Update" -##### Over Current (OC)/Threshold Comparator +##### Over Current (OC)/Threshold Comparator This section describes the over current implementation. It performs continuous sampling (free run) and when the sample value crosses the high or low threshold, the corresponding PWM trip status gets set and TZ_OUT pin goes high. It also stores high and low threshold status in DMEM for all channels, \ref SDFM_getHighThresholdStatus API returns high threshold status for specified SDFM channel number and \ref SDFM_getLowThresholdStatus API returns low threshold status for specified SDFM channel number. \image html SDFM_OC_Flow_Chart.png "Over current" \image html SDFM_OC_ERROR_MAPPING_WITH_PWM_TZ.png "Mapping between Over current errors and PWM TZ blocks" -###### Zero Cross Comparator +###### Zero Cross Comparator This section describes the zero cross implementation. It compares the current sample and the previous sample values with zero cross threshold value. There are two cases: @@ -117,7 +117,7 @@ There are two cases: #### Sync with EPWM and trigger timing This section describes the EPWM to %SDFM synchronization and trigger timing for each EPWM cycle. At the end of the every EPWM cycle, the EPWM generates a sync out event that resets the IEP timer. The firmware initiates normal current sampling at the sample trigger point in each EPWM cycle. It takes four consecutive samples to bring the accumulator and differentiator registers to stable state. It takes the first sample at the trigger point and the next three samples, each after ONE_SAMPLE_TIME. -Here ONE_SAMPLE_TIME is: OSR*(1/SD_CLK) +Here ONE_SAMPLE_TIME is: OSR*(1/SD_CLK) \image html SDFM_epwm_sync_and_trigger_timing.png "Sync with EPWM and trigger timing" #### Fast Detect and Trip generation @@ -128,12 +128,12 @@ Note: To identify the sigma delta fast detect error trip cause, \ref SDFM_getFas \image html SDFM_FD_ERROR_MAPPING_WITH_PWM_TZ.png "Mapping between Fast detect errors and PWM TZ blocks" -#### Data/Clock Phase Compensation +#### Data/Clock Phase Compensation Following points describe the process for measurement of phase difference between clock and data - Set PRU IO mode to GPIO mode (default) for direct capture of input data and clock pins  - First wait for rising edge on the SD data pin, then check the nearest upcoming edge to the SD clock pin. If the nearest edge of clock pin is falling, then it measures the time between the rising edge of the data pin and the falling edge of the SD clock. Otherwise it measures time between the rising edge of both data and clock pins. -- It measures delay 8 times and repeats the measurement until the get like 8 time the same or a max variation of 1 PRU cycle. -- Based on the clock polarity, phase delay is calculated. If clock polarity and upcoming nearest edge of clock pin for rising edge of data pin are same, then final phase delay will be half SD clock duty cycle time minus calculated time. Otherwise phase delay will be SD clock one cycle period time minus calculated time +- It measures delay 8 times and repeats the measurement until the get like 8 time the same or a max variation of 1 PRU cycle. +- Based on the clock polarity, phase delay is calculated. If clock polarity and upcoming nearest edge of clock pin for rising edge of data pin are same, then final phase delay will be half SD clock duty cycle time minus calculated time. Otherwise phase delay will be SD clock one cycle period time minus calculated time \image html SDFM_Phase_delay_flowchart.png "Phase Compensation" #### AM64x/AM243x EVM Pin-Multiplexing @@ -175,7 +175,7 @@ Following points describe the process for measurement of phase difference betwee diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md b/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md index b18364f..da2ed15 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md @@ -1063,7 +1063,7 @@ TI HDSL Solution's register map is compatible with SICK HDSL MASTER IP Core rele @@ -338,10 +338,10 @@ earlier SDKs. -
PRG0_ECAP0_IN_APWM_OUT PIN_PRG0_PRU1_GPO15 - ECAP output frequency + ECAP output frequency
GPIO_MTR_1_PWM_EN @@ -200,7 +200,7 @@ Following points describe the process for measurement of phase difference betwee
GPIO_ZC_TH_CH0 PRG1_PRU0_GPO18 - (J7.64)Ch0 Zero cross output + (J7.64)Ch0 Zero cross output
GPIO_ZC_TH_CH1 @@ -230,7 +230,7 @@ Following points describe the process for measurement of phase difference betwee
PRG0_ECAP0_IN_APWM_OUT PIN_PRG0_PRU1_GPO15 - (J6.59)ECAP output frequency + (J6.59)ECAP output frequency
SD8_CLK diff --git a/docs_src/docs/api_guide/components/position_sense/biss_c.md b/docs_src/docs/api_guide/components/position_sense/biss_c.md index 1899166..e9a0e40 100644 --- a/docs_src/docs/api_guide/components/position_sense/biss_c.md +++ b/docs_src/docs/api_guide/components/position_sense/biss_c.md @@ -17,7 +17,7 @@ BiSS is an open-source digital interface for sensors and actuators. BiSS stands - Support for multiple encoders connected via daisy-chain configuration (up-to 3 encoders) - Support for concurrent multi-channel support on a single PRU (up-to 3 identical encoders) - Support for multi-channel encoders of different make under load share model (each of PRU, RTU-PRU, and TX-PRU from one PRU-ICSSG slice handles one channel) - - Support for up to 100 mtr cable + - Support for up to 100 meter cable ## Features Not Supported diff --git a/docs_src/docs/api_guide/components/position_sense/biss_c_design.md b/docs_src/docs/api_guide/components/position_sense/biss_c_design.md index 41e3f84..9dd3175 100644 --- a/docs_src/docs/api_guide/components/position_sense/biss_c_design.md +++ b/docs_src/docs/api_guide/components/position_sense/biss_c_design.md @@ -19,7 +19,6 @@ Clock, data transmit, data receive and receive enable signals from PRU1 of ICSS_ ## Implementation The BISS-C receiver function is implemented on TI Sitara™ Devices. -Encoder is connected to IDK via universal Digital Interface TIDA-00179(https://www.ti.com/tool/TIDA-00179), TIDEP-01015(3-axis board) and 3 Axis Interface card. Design is split into three parts – 3 channel peripheral interface support in PRU, firmware running in PRU and driver running in ARM. Application is supposed to use the BISS-C driver APIs to leverage 3 channel peripheral interface functionality. SDK examples used the BISS-C hardware capability in Slice 1 (either 1 core or 3 cores based on the confiuration) of PRU-ICSSG0. diff --git a/docs_src/docs/api_guide/components/position_sense/endat_design.md b/docs_src/docs/api_guide/components/position_sense/endat_design.md index 9be6ccb..4be0df6 100644 --- a/docs_src/docs/api_guide/components/position_sense/endat_design.md +++ b/docs_src/docs/api_guide/components/position_sense/endat_design.md @@ -21,13 +21,12 @@ Clock, data transmit, data receive and receive enable signals from PRU1 of ICSS_ ## Implementation The EnDat receiver function is implemented on TI Sitara™ Devices. -Encoder is connected to IDK via universal Digital Interface TIDA-00179(https://www.ti.com/tool/TIDA-00179), TIDEP-01015(3-axis board) and 3 Axis Interface card. +Encoder is connected to IDK via TIDA-00179 Universal Digital Interface to Absolute Position Encoders , TIDEP-01015 3 Axis Board and Interface card connecting EVM and TIDEP-01015 3 Axis . Design is split into three parts – EnDat hardware support in PRU, firmware running in PRU and driver running in ARM. Application is supposed to use the EnDat driver APIs to leverage EnDat functionality. SDK examples used the EnDat hardware capability in Slice 1 (either 1 core or 3 cores based ont the confiuration) of PRU-ICSSG0. Remaining PRUs in the AM64x/AM243x EVM are available for Industrial Ethernet communication and/or motor control interfaces. - ### Specifications diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl.md b/docs_src/docs/api_guide/components/position_sense/hdsl.md index 7c2db5f..7b2456a 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl.md @@ -8,26 +8,30 @@ The HDSL firmware running on ICSS-PRU provides a defined well interface to execu ## Features Supported -- Safe position -- Fast position, speed -- Communication status -- External pulse synchronization -- Register interface to be compatible with SICK HDSL FPGA IP Core (apart from the differences listed in \ref HDSL_EXCEPTIONS_LIST) -- Parameter channel communication +- Safe position +- Fast position, speed +- Communication status +- External pulse synchronization + - 1 to 10 frames per cycle + - 8 kHz to 50 kHz cycle frequency +- Register interface to be compatible with SICK HDSL FPGA IP Core (apart from the differences listed in \ref HDSL_EXCEPTIONS_LIST) +- Parameter channel communication - Short message - Long message -- Safety -- Two channels support on am243x-evm -- Single channel support on am243x-lp -- Tested with three different encoder makes (EDM35, EKS36, EKM36) +- Safety +- Pipeline Channel Data +- Three channel support using single PRU-ICSSG slice + - Three channel support on am243x-evm + - Two channel support on am243x-lp +- Tested with three different encoder makes (EDM35, EKS36, EKM36) ## Features Not Supported In general, peripherals or features not mentioned as part of "Features Supported" section are not supported, including the below - - 100m cable - - Three channel support using single PRU-ICSSG slice - - Pipeline Channel + - 100m cable + - Pipeline Channel Status + ## SysConfig Features @VAR_SYSCFG_USAGE_NOTE @@ -51,6 +55,58 @@ SysConfig can be used to configure things mentioned below: \subpage HDSL_EXCEPTIONS_LIST lists the exceptions TI's HDSL implementation when compared with SICK HDSL FPGA IP Core. Please note that all the corresponding register fields are not implemented. +## Datasheet + +### Synchronization Pulse Jitter + +- Synchronization Pulse Jitter is under 100ns. Please refer to the image below for jitter calculation waveforms. + +\image html hdsl_sync_mode_waveforms.png "HDSL Sync mode waveforms for 2 channels" +\image html hdsl_sync_mode_jitter.jpg "HDSL Sync mode jitter analysis" + +### Protocol Package Lengths with different ES and Sync Pulse Frequency values + +NOTE: Images below show TX_EN signal in "Red" and RX signal in "Yellow". + +
+ + + + + + + + + + + + +
ES Value + Cycle Time (in us) + Cycle Frequency (in kHz) + Observed Protocol Package Length (in us) +
1 + 25 + 40 + 25.06 +
1 + 20 + 50 + 19.942 +
2 + 25 + 40 + Between 12.26 and 12.80 +
5 + 62.5 + 16 + Between 11.94 and 12.60 +
10 + 125 + 8 + Between 11.94 and 12.90 +
+ ## Example \ref EXAMPLE_MOTORCONTROL_HDSL diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl_design.md b/docs_src/docs/api_guide/components/position_sense/hdsl_design.md index 6241868..3739069 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl_design.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl_design.md @@ -18,22 +18,38 @@ Refer PRU-ICSS chapter of AM64x/AM243x Technical Reference Manual ## Software Architecture -The firmware consists of two layers .On the one hand, there is the datalink layer, which is responsible for establishing a communication link to the encoder, monitoring the connection quality and preparing the data. -On the other hand, there is the transport layer that processes the data and determines what information is sent over the parameter channel. Figure "Layer Model" illustrates the relationship between the two layers. -The datalink layer assembles the information from the different channels and puts the data symbol by symbol to the channel buffers. The channel buffers are large enough to carry the data of a whole V-Frame for each channel. . -The transport layer controls the data sent over the parameter channel by setting the symbol to send for the next H-Frame in the parameter channel buffer. This buffer can carry only one symbol. +The Hiperface DSL function is implemented on one PRU-ICSSG to leave the other PRU-ICSSG for Industrial Ethernet functions. + +The firmware consists of two layers + +1. Datalink Layer : It is responsible for establishing a communication link to the encoder, monitoring the connection quality and preparing the data. It assembles the information from the different channels and puts the data symbol by symbol to the channel buffers. The channel buffers are large enough to carry the data of a whole vertical frame for each channel. +2. Transport Layer : It processes the data and determines what information is sent over the parameter channel. It controls the data sent over the parameter channel by setting the symbol to send for the next horizontal frame in the parameter channel buffer. This buffer can carry only one symbol. + Both layers have direct access to the register interface that is provided to the higher layers. +Figure "Layer Model" illustrates the relationship between the two layers. -\image html hdsl_layer_model.png "Layer Model " -Hiperface DSL specifies a state machine for the Receiver. This implementation features an additional state for loading new firmware to the PRU. Figure "State Machine" depicts the modified state machine. -Furthermore, this implementation exhibits three code sections in the firmware. The first one is for initializing the state machine up to the LOADFW state. +\image html hdsl_layer_model.png "Layer Model" + +### Overlay Scheme for TX-PRU + +Each PRU-ICSSG has two slices, and each slice has three cores : PRU, RTU-PRU and TX-PRU. The instruction memory for PRU, RTU-PRU and TX-PRU coreS is 12 kB, 8 kB and 6 kB respctively. Multi-channel implementation of Hiperface DSL is achieved by enabling load share mode of PRU-ICSSG where one core is responsible for one channel. One PRU-ICSSG slice supports three peripheral interfaces for HDSL. Mapping is fixed to channel 0 with RTU-PRU, channel 1 with TX-PRU. To implement an equivalent data link layer and transport layer as the reference IP-core for the Hiperface DSL on FPGA, the instruction memory for TX-PRU is not enough. Hence a code overlay scheme is required only for TX-PRU core, which is only needed if channel 2 is enabled. + +For PRU and RTU-PRU, the firmware for Hiperface DSL fully fits into instruction memory. The firmware for TX-PRU is split into following three code sections based on initialization and normal operation: + +1. Initialization specific code +2. Normal operation code +3. Common code needed during initialization and normal operation + +Part 3 is loaded directly into instruction memory (IMEM) of TX-PRU by ARM core as it will be needed in all states. Part 1 and Part 2 of firmware for TX-PRU are stored in PRU-ICSS Data Memory (DMEM) by ARM core. During initialization (LOADFW1 state shown in next section), part 1 is copied into instruction memory (IMEM) of TX-PRU from Data Memory (DMEM) by RTU-PRU core. After initialization is complete (LOADFW2 state shown in next section), part 2 is copied into instruction memory (IMEM) of TX-PRU from Data Memory (DMEM) by RTU-PRU core. + +### State Machine + +Hiperface DSL specifies a state machine for the Receiver. This implementation features two additional states for loading firmware to the TX-PRU from RTU-PRU. Figure "State Machine" depicts the modified state machine. \image html hdsl_state_machine.png "State Machine" -The second section contains datalink functionalities that are needed for the startup phase as well as for the normal workflow. The transport layer functionalities reside in the third section. - ### Datalink Layer The datalink layer is responsible for handling the communication link to the encoder. This includes the sampling, cable delay compensation, DC line balancing, encoding and decoding of data and the monitoring of the connection quality. @@ -68,7 +84,17 @@ The RSSI is calculated by determining the number of samples between two edges du A 16bit CRC verification of the data is used on multiple occasions. It is used for the vertical channel, secondary channel and messages. In order to distribute the computation load equally over all H-Frames, the firmware calculates a running CRC for those data (except for short messages). The algorithm uses a LUT with 256 entries and 2 bytes per entry, whereas each entry is the 16bit CRC for the corresponding LUT index. The basic approach for the calculation of the 16bit CRC is shown as C code in the following: -uint16_t calc_crc(uint8_t *data, uint32_t size) { uint16_t crc = 0; uint32_t i; for(i = 0; i < size; ++i) { crc = ((*data) << 8) ^ crc; crc = lut[crc>>8] ^ (crc << 8); } return (crc ^ 0xff); } + uint16_t calc_crc(uint8_t *data, uint32_t size) + { + uint16_t crc = 0; + uint32_t i; + for(i = 0; i < size; ++i) + { + crc = ((*data) << 8) ^ crc; + crc = lut[crc>>8] ^ (crc << 8); + } + return (crc ^ 0xff); + } ### Transport Layer @@ -110,24 +136,29 @@ It is possible that these calculations lead to the excess of the maximum or mini The algorithm is given as C code in the following: - /* EXTRA_SIZE equals the number of bits for the EXTRA window minus 1 */ - if(EXTRA_EDGE == 0) - TIME_REST += 8; - short b = (EXTRA_SIZE << 3) + TIME_REST; - short overhead = (EXTRA_SIZE << 3) + 8 - TIME_EXTRA_WINDOW; - EXTRA_SIZE = (b - overhead) >> 3; - TIME_REST = (b - overhead) - (EXTRA_SIZE << 3); + /* EXTRA_SIZE equals the number of bits for the EXTRA window minus 1 */ + if(EXTRA_EDGE == 0) + { + TIME_REST += 8; + } - if(EXTRA_SIZE < 3) { - EXTRA_SIZE += 6; - NUM_STUFFING -= 1; - TIME_EXTRA_WINDOW += (8*6); - } -if(EXTRA_SIZE > 8) { - EXTRA_SIZE -= 6; - NUM_STUFFING += 1; - TIME_EXTRA_WINDOW -= (8*6); - } + short b = (EXTRA_SIZE << 3) + TIME_REST; + short overhead = (EXTRA_SIZE << 3) + 8 - TIME_EXTRA_WINDOW; + EXTRA_SIZE = (b - overhead) >> 3; + TIME_REST = (b - overhead) - (EXTRA_SIZE << 3); + + if(EXTRA_SIZE < 3) + { + EXTRA_SIZE += 6; + NUM_STUFFING -= 1; + TIME_EXTRA_WINDOW += (8*6); + } + if(EXTRA_SIZE > 8) + { + EXTRA_SIZE -= 6; + NUM_STUFFING += 1; + TIME_EXTRA_WINDOW -= (8*6); + } EXTRA_EDGE represents the TIME_REST value in a format that can be pushed to the TX FIFO for transmission. For instance, if TIME_REST is 4, EXTRA_EDGE is 0xf0. The edge would be in the middle of the bit duration. The value NUM_STUFFING gives the number of stuffing blocks (each block consist of 6 bits). @@ -137,7 +168,3 @@ For further improvement of the synchronization, the time difference (∆t) betwe \imageStyle{hdsl_external_sync_sample_edge.png,width:40%} \image html hdsl_external_sync_sample_edge.png "Time difference between External Pulse and Sample Edge" - -Sync pulse jitter is under 100ns. Please refer to the image below for jitter calculation waveforms. -\image html hdsl_sync_mode_waveforms.png "HDSL Sync mode waveforms for 2 channels" -\image html hdsl_sync_mode_jitter.jpg "HDSL Sync mode jitter analysis" diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md b/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md index 4a07901..3dac251 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md @@ -3,7 +3,7 @@ Notable exceptions in TI HDSL Solution when compared with SICK HDSL MASTER IP Core release version 1.07 are described below: 1. SPI interface is not available to access the HDSL Master. Registers are present in Data Memory of Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS), which can be accessed directly by the ARM processor core. -2. Pipeline for SensorHub Channel Data is not available. +2. Pipeline Status for SensorHub Channel is not available. Pipeline data is updated for each horizontal frame. 3. Control signals similar to SICK HDSL MASTER IP Core are not available, except SYNC signal. Instead of INTERRUPT signal, interrupts are triggered to ARM processor core. 4. Test signals similar to SICK HDSL MASTER IP Core are not available. 5. TI HDSL Solution's register map is register compatible with SICK HDSL MASTER IP Core release version 1.07, with few exceptions listed below: @@ -49,7 +49,6 @@ Notable exceptions in TI HDSL Solution when compared with SICK HDSL MASTER IP Co
PIPE_S
- PIPE_D 		**Not available in TI HDSL Solution**
0x2E SensorHub Channel Data -
**NOTE : Not available in TI HDSL Solution** + 8 bit value of the SensorHub Channel Data
PC_DATA diff --git a/docs_src/docs/api_guide/components/position_sense/tamagawa.md b/docs_src/docs/api_guide/components/position_sense/tamagawa.md index 63206d6..c1802fd 100644 --- a/docs_src/docs/api_guide/components/position_sense/tamagawa.md +++ b/docs_src/docs/api_guide/components/position_sense/tamagawa.md @@ -7,7 +7,7 @@ The Tamagawa receiver firmware running on PRU-ICSS provides a defined well interface to execute the Tamagawa protocol. The Tamagawa diagnostic application interacts with the Tamagawa receiver firmware interface. \note -Tamagawa firmware and examples are based on EnDAT hardware interface from PRU-ICSSG. +Tamagawa firmware and examples are based on 3 Channel Peripheral interface from PRU-ICSSG. ## Features Supported diff --git a/docs_src/docs/api_guide/components/pruicss_pwm/pruicss_pwm.md b/docs_src/docs/api_guide/components/pruicss_pwm/pruicss_pwm.md index 0a24658..9e8fa25 100644 --- a/docs_src/docs/api_guide/components/pruicss_pwm/pruicss_pwm.md +++ b/docs_src/docs/api_guide/components/pruicss_pwm/pruicss_pwm.md @@ -32,7 +32,7 @@ SysConfig can be used to configure things mentioned below: ## Important Note -PRUICSS has one pwm module, which has four pwm sets (PWM0, PWM1, PWM2, PWM3) +PRU-ICSS has one PWM module, which has four PWM sets (PWM0, PWM1, PWM2, PWM3) Each Set has six signals (A0,A1,A2,B0,B1,B2) With Reference to Technical Reference Manual, Pwm six signals(A0,A1,A2,B0,B1,B2) Naming convention is is slightly different as mentioned in \ref PRUICSS_PWM_API ## Example Usage diff --git a/docs_src/docs/api_guide/components/dcl/dcl.cfg b/docs_src/docs/api_guide/components/rtlibs/dcl/dcl.cfg similarity index 97% rename from docs_src/docs/api_guide/components/dcl/dcl.cfg rename to docs_src/docs/api_guide/components/rtlibs/dcl/dcl.cfg index 80a55d6..1c8b025 100644 --- a/docs_src/docs/api_guide/components/dcl/dcl.cfg +++ b/docs_src/docs/api_guide/components/rtlibs/dcl/dcl.cfg @@ -1,4 +1,4 @@ -INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/dcl/dcl.md +INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/rtlibs/dcl/dcl.md INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/dcl.h INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/dcl_common.h INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/dcl/pi/dcl_pi.h diff --git a/docs_src/docs/api_guide/components/dcl/dcl.md b/docs_src/docs/api_guide/components/rtlibs/dcl/dcl.md similarity index 100% rename from docs_src/docs/api_guide/components/dcl/dcl.md rename to docs_src/docs/api_guide/components/rtlibs/dcl/dcl.md diff --git a/docs_src/docs/api_guide/components/rtlibs/rtlibs.md b/docs_src/docs/api_guide/components/rtlibs/rtlibs.md new file mode 100644 index 0000000..32fc09d --- /dev/null +++ b/docs_src/docs/api_guide/components/rtlibs/rtlibs.md @@ -0,0 +1,8 @@ +# Real Time Libraries {#REALTIMELIBS} + +[TOC] + +Real Time Libraries module contains following two components: + +- \subpage DCL +- \subpage TRANSFORMS \ No newline at end of file diff --git a/docs_src/docs/api_guide/components/transforms/transforms.cfg b/docs_src/docs/api_guide/components/rtlibs/transforms/transforms.cfg similarity index 89% rename from docs_src/docs/api_guide/components/transforms/transforms.cfg rename to docs_src/docs/api_guide/components/rtlibs/transforms/transforms.cfg index 317d80e..6b4295a 100644 --- a/docs_src/docs/api_guide/components/transforms/transforms.cfg +++ b/docs_src/docs/api_guide/components/rtlibs/transforms/transforms.cfg @@ -1,4 +1,4 @@ -INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/transforms/transforms.md +INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/rtlibs/transforms/transforms.md INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/transforms/clarke/clarke.h INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/transforms/park/park.h INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/transforms/ipark/ipark.h diff --git a/docs_src/docs/api_guide/components/transforms/transforms.md b/docs_src/docs/api_guide/components/rtlibs/transforms/transforms.md similarity index 98% rename from docs_src/docs/api_guide/components/transforms/transforms.md rename to docs_src/docs/api_guide/components/rtlibs/transforms/transforms.md index 386ef84..a51dc5c 100644 --- a/docs_src/docs/api_guide/components/transforms/transforms.md +++ b/docs_src/docs/api_guide/components/rtlibs/transforms/transforms.md @@ -1,4 +1,4 @@ -# Transformation Algorithm {#Transforms} +# Transformation Algorithm {#TRANSFORMS} [TOC] diff --git a/docs_src/docs/api_guide/device/am243x/components.cfg b/docs_src/docs/api_guide/device/am243x/components.cfg index ecd1dd0..1ead426 100644 --- a/docs_src/docs/api_guide/device/am243x/components.cfg +++ b/docs_src/docs/api_guide/device/am243x/components.cfg @@ -13,6 +13,8 @@ INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_se INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/current_sense/current_sense.md INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/current_sense/sdfm_design.md +INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/rtlibs/rtlibs.md + INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/pruicss_pwm/pruicss_pwm.md INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/endat/include/endat_api.h diff --git a/docs_src/docs/api_guide/device/am243x/includes.cfg b/docs_src/docs/api_guide/device/am243x/includes.cfg index a0a67a9..1f01955 100644 --- a/docs_src/docs/api_guide/device/am243x/includes.cfg +++ b/docs_src/docs/api_guide/device/am243x/includes.cfg @@ -11,10 +11,11 @@ INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/main_page/main_page.m INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/migration_guides/mcusdk_migration_guide.md INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes.md INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_00_00.md +INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_01_00.md @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/examples.cfg @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/components.cfg -@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/dcl/dcl.cfg -@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/transforms/transforms.cfg +@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/rtlibs/dcl/dcl.cfg +@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/rtlibs/transforms/transforms.cfg # Used to selectively pick DEVICE specific sections within .md files ENABLED_SECTIONS = SOC_AM243X diff --git a/docs_src/docs/api_guide/device/am243x/release_notes.md b/docs_src/docs/api_guide/device/am243x/release_notes.md index d4c7104..e73dded 100644 --- a/docs_src/docs/api_guide/device/am243x/release_notes.md +++ b/docs_src/docs/api_guide/device/am243x/release_notes.md @@ -4,5 +4,6 @@ Refer the below pages for release specific information +- \subpage RELEASE_NOTES_09_01_00_PAGE - \subpage RELEASE_NOTES_09_00_00_PAGE diff --git a/docs_src/docs/api_guide/device/am243x/release_notes_09_00_00.md b/docs_src/docs/api_guide/device/am243x/release_notes_09_00_00.md index bf3338d..4eb2945 100644 --- a/docs_src/docs/api_guide/device/am243x/release_notes_09_00_00.md +++ b/docs_src/docs/api_guide/device/am243x/release_notes_09_00_00.md @@ -28,7 +28,7 @@ Digital Control Library SOC | Supported CPUs | Boards | Host PC -------|-----------------|-------------------------------------------------------------------------------------------------------------|----------------------------------- -AM243x | R5F | AM243x GP EVM (referred to as am243x-evm in code), \n AM243x LAUNCHPAD (referred to as am243x-lp in code) | Windows 10 64b or Ubuntu 18.04 64b +AM243x | R5F | AM243x EVM (referred to as am243x-evm in code), \n AM243x LAUNCHPAD (referred to as am243x-lp in code) | Windows 10 64b or Ubuntu 18.04 64b ## Tools, Compiler and Other Open Source SW Module Information @@ -203,7 +203,7 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat %SDFM: Incorrect samples seen intermittently with EPWM as %SDFM clock Current Sense %SDFM 9.0 onwards - Use 5MHz %SDFM clock from EPWM1 (tested with 5MHz clock from EPWM) or use PRU-ICSSG ECAP as %SDFM clock source + Use 5MHz %SDFM clock from EPWM1 (tested with 5MHz clock from EPWM) or use PRU-ICSSG ECAP as %SDFM clock source
PINDSW-6628 @@ -228,7 +228,7 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
PINDSW-6931 - Tamagawa: Firmware build failing + Tamagawa: Firmware build failing Position Sense Tamagawa 9.0 onwards 1. Update include path of icss_regs.inc and icss_cfg_regs.inc files to `../../../../mcu_plus_sdk/source/pru_io/firmware/common/ ` path in `tamagawa_main.asm` and `tamagawa_icss_reg_defs.h` files.
2. Replace ED with ENDAT in symbol definitions in tamagawa_main.asm file's lines 101 to 122. (For example, update `ICSS_CFG_PRU0_ED_CH0_CFG1` to `ICSS_CFG_PRU0_ENDAT_CH0_CFG1` )		 Additional Remarks
- - - + + + +
--> @@ -358,7 +358,7 @@ earlier SDKs. Current Sense %SDFM Structure `SdfmPrms_s` Added variables `iep_clock`, `sd_clock`, `en_second_update`, `firstSampTrigTime` and `secondSampTrigTime` - + @@ -393,7 +393,7 @@ earlier SDKs. Current Sense %SDFM `SDFM_setSampleReadingTime` Changed name of API \ref SDFM_setSampleTriggerTime and updated a parameter name `samp_trig_time` - - + - Current Sense %SDFM @@ -404,25 +404,25 @@ earlier SDKs. Current Sense %SDFM \ref SDFM_setCompFilterOverSamplingRatio - Changed type of OSR parameter - uint8_t to uint16_t + Changed type of over-sampling Rate (OSR) parameter + uint8_t to uint16_t Current Sense %SDFM - `SDFM_setAccOverSamplingRatio` + `SDFM_setAccOverSamplingRatio` Removed this API - Current Sense %SDFM - Structure \ref SDFM_Ctrl - Removed variables: `ctrl` and `stat`, and added variables `sdfm_en`, `sdfm_en_ack` and `sdfm_pru_id` - - + Structure \ref SDFM_Ctrl + Removed variables: `ctrl` and `stat`, and added variables `sdfm_en`, `sdfm_en_ack` and `sdfm_pru_id` + - Current Sense %SDFM Structure \ref SDFM_CfgTrigger - Removed variables `trig_samp_time`, `oc_prd_iep_cnt` and `sample_count`, and added variables `en_double_nc_sampling`, `first_samp_trig_time` and `second_samp_trig_time` + Removed variables `trig_samp_time`, `oc_prd_iep_cnt` and `sample_count`, and added variables `en_double_nc_sampling`, `first_samp_trig_time` and `second_samp_trig_time` - diff --git a/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md b/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md new file mode 100644 index 0000000..4aa08b1 --- /dev/null +++ b/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md @@ -0,0 +1,429 @@ +# Release Notes 09.01.00 {#RELEASE_NOTES_09_01_00_PAGE} + +[TOC] + +\attention Also refer to individual module pages for more details on each feature, unsupported features, important usage guidelines. + +\attention For release notes of Industrial Communications SDK and MCU+ SDK, please refer to @VAR_SOC_NAME Industrial Communications SDK Release Notes 09.01.00 and @VAR_SOC_NAME MCU+ SDK Release Notes 09.01.00 respectively. + +\note The examples will show usage of SW modules and APIs on a specific CPU instance and OS combination. \n + Unless noted otherwise, the SW modules would work in both FreeRTOS and NORTOS environment. \n + Unless noted otherwise, the SW modules would work on any of the R5F's present on the SOC. \n + Unless noted otherwise, the SW modules would work on all supported EVMs \n + +\note Tamagawa over SoC UART example is not supported for AM243x + +## New in this Release + +Feature | Module +------------------------------------------------------------------------------------------------|----------------------------------- +EtherCAT-Connected, Single-Chip, Dual-Servo Motor Drive Reference Design (TIDEP-01032) | Reference Design +Three channel BiSS-C with one PRU-ICSSG Slice | Position Sense BiSS-C +Point-to-point and daisy chaining connection support for BiSS-C | Position Sense BiSS-C +Multi channel BiSS-C with daisy chaining | Position Sense BiSS-C +Multiple interface speed support | Position Sense BiSS-C +Long cable (upto 100 meters) | Position Sense BiSS-C +Nine Channel ICSS %SDFM Examples | Current Sense %SDFM +ICSS %SDFM Example with Continuous Normal Current Sampling | Current Sense %SDFM +ICSS %SDFM Example with Phase Compensation | Current Sense %SDFM +Fast Detect | Current Sense %SDFM +Trip Generation using PRU-ICSS TripZone | Current Sense %SDFM +Zero Crossing Detection | Current Sense %SDFM +Three channel support with one PRU-ICSSG Slice | Position Sense HDSL +SYNC Mode support for 1 to 10 frames per cycle and 8 kHz to 50 kHz cycle frequency | Position Sense HDSL +API support for Parameter Channel Long Message Read and Write | Position Sense HDSL +Add support for PIPE_D register for SensorHub Channel | Position Sense HDSL +Add support for PIPE_D register for SensorHub Channel | Position Sense HDSL +Long cable (upto 100 meters) | Position Sense HDSL +Two channel example with LP-AM243 + BP-AM2BLDCSERVO | Position Sense HDSL +Compare event based command trigger support | Position Sense Tamagawa +Two channel example with LP-AM243 + BP-AM2BLDCSERVO | Position Sense Tamagawa +Two channel example with LP-AM243 + BP-AM2BLDCSERVO | Position Sense EnDAT +Three channel PRU-ICSS PWM Example | PRU-ICSS PWM +Transforms Library and Example | Real Time Libraries + +## Device and Validation Information + +SOC | Supported CPUs | Boards | Host PC +-------|-----------------|-------------------------------------------------------------------------------------------------------------|----------------------------------- +AM243x | R5F | AM243x EVM (referred to as am243x-evm in code), \n AM243x LAUNCHPAD (referred to as am243x-lp in code) | Windows 10 64b or Ubuntu 18.04 64b + +## Tools, Compiler and Other Open Source SW Module Information + +Tools / SW module | Supported CPUs | Version +------------------------|----------------|----------------------- +Code Composer Studio | R5F, M4F, A53 | @VAR_CCS_VERSION +SysConfig | R5F, M4F, A53 | @VAR_SYSCFG_VERSION, build @VAR_SYSCFG_BUILD +TI ARM CLANG | R5F, M4F | @VAR_TI_ARM_CLANG_VERSION +FreeRTOS Kernel | R5F, M4F, A53 | @VAR_FREERTOS_KERNEL_VERSION +FreeRTOS SMP Kernel | A53 | @VAR_FREERTOS_SMP_KERNEL_VERSION + +## Key Features + + + + + + + + + +### Position Sense + + + + + + + + + + + + +
Module + Supported CPUs + SysConfig Support + OS Support + Key features tested + Key features not tested +
EnDat + R5F + YES + FreeRTOS, NORTOS + Single channel, Multi channel using single PRU core and three PRU cores (load share mode), Continuous mode, Recovery Time for 2.2 command set, Long cable (upto 100 meters), Boosterpack with AM243x-LP + Encoder receive communication command +
HDSL + R5F + YES + FreeRTOS, NORTOS + Single channel, Multi channel using three PRU cores (load share mode), Free Run mode, Sync mode, Short Message Read and Write, Long Message Read and Write, Pipeline Channel Data, Long cable (upto 100 meters), Boosterpack with AM243x-LP + 225 MHz PRU-ICSSG Core Clock based firmware +
Tamagawa + R5F + YES + FreeRTOS, NORTOS + Absolute position, Encoder ID, Reset, EEPROM Read, EEPROM Write, 2.5 Mbps and 5 Mbps Encoder Support, Boosterpack with AM243x-LP + - +
BiSS-C + R5F + YES + FreeRTOS, NORTOS + Single channel, Multi channel using single PRU core and three PRU cores (load share mode), point-to-point connection, daisy chaining, control communication, automatic processing delay detection and compensation, interface speed of 1, 2, 5, 8, and 10 MHz, Long cable (upto 100 meters) + +
+ +### Current Sense + + + + + + +
Module + Supported CPUs + SysConfig Support + OS Support + Key features tested + Key features not tested +
ICSS %SDFM + R5F + YES + FreeRTOS, NORTOS + Three %SDFM channels on single PRU core, Nine %SDFM channels on three PRU cores (load share mode), %SDFM Sync with EPWM, Single/Double Normal Current Sampling per PWM cycle, Continuous Normal Current Sampling, High and Low Threshold Comparator (Over-current detction), Fast Detect, Phase Compensation, Zero Cross Detection, Trip Generation using PRU-ICSS TripZone, Tested with %SDFM clock from ECAP, Tested with 5MHz Clock from EPWM + - +
+ +## Fixed Issues + + + + + + + + + + + + + + + + + + + + +
ID + Head Line + Module + Applicable Releases + Resolution/Comments +
PINDSW-6628 + HDSL: Reset value of PRST bit is not correct + Position Sense HDSL + 9.0 + - +
PINDSW-6629 + HDSL: SSUM bit in EVENT_S is not set when SUMMARY is non-zero + Position Sense HDSL + 9.0 + SSUM bit in EVENT_S was masked with MASK_SUM which was incorrect. +
PINDSW-6931 + Tamagawa: Firmware build failing + Position Sense Tamagawa + 9.0 + - +
PINDSW-6944 + HDSL: QM increment is not correct + Position Sense HDSL + 9.0 + QM updates for Safe Channel 2 were incorrect. +
PINDSW-7048 + HDSL: SCE bit in ONLINE STATUS 1 gets cleared before seeing a correct CRC in safe channel + Position Sense HDSL + 9.0 + - +
PINDSW-7126 + HDSL: Protocol reset is seen multiple times with certain encoders + Position Sense HDSL + 9.0 + - +
PINDSW-7129 + HDSL: Stuffing Data in Learn state is incorrect with Free Run Mode + Position Sense HDSL + 9.0 + - +
PINDSW-7157 + HDSL : Sync mode does not work for ES value greater than 1 + Position Sense HDSL + 9.0 + - +
+ +## Known Issues + + + + + + + + + + + + + + + + + + + + +
ID + Head Line + Module + Applicable Releases + Workaround +
PINDSW-5537 + HDSL not working with 225 MHz PRU-ICSSG Core Clock Frequency + Position Sense HDSL + 9.0 onwards + Use 300 MHz frequency for PRU-ICSSG Core Clock +
PINDSW-5690 + HDSL: EDGE register is not updated + Position Sense HDSL + 9.0 onwards + - +
PINDSW-6486 + HDSL: RSSI register shows higher values than expected for a non-noisy setup + Position Sense HDSL + 9.0 onwards + - +
PINDSW-6544 + %SDFM: Incorrect samples seen intermittently with EPWM as %SDFM clock + Current Sense %SDFM + 9.0 onwards + Use 5MHz %SDFM clock from EPWM1 (tested with 5MHz clock from EPWM) or use PRU-ICSSG ECAP as %SDFM clock source +
PINDSW-6630 + HDSL: POS bit is not set during initial fast position alignment + Position Sense HDSL + 9.0 onwards + - +
PINDSW-7130 + HDSL: Few protocol resets seen during initialization with Free Run mode on AM243x-LP + Position Sense HDSL + 9.0 onwards + - +
PINDSW-7158 + HDSL: Reset Value of SSUM bit is not correct + Position Sense HDSL + 9.0 onwards + - +
PINDSW-7163 + HDSL: Trailer data contains 4 zeros instead of 5 + Position Sense HDSL + 9.0 onwards + - +
+ + + +## Limitations + + + + + +
ID + Head Line + Module + Reported in Release + Applicable Devices + Workaround +
MCUSDK-208 + gmake with -j can sometimes lock up Windows command prompt + Build + 7.3.0 + AM64x, AM243x + Use bash for windows as part of git for windows or don't use -j option +
+ +## Upgrade and Compatibility Information {#UPGRADE_AND_COMPATIBILITY_INFORMATION_9_1_0} + + + +This section lists changes which could affect user applications developed using older SDK versions. +Read this carefully to see if you need to do any changes in your existing application when migrating to this SDK version relative to +previous SDK version. Also refer to older SDK version release notes to see changes in +earlier SDKs. + + + +### Examples + + + + + + +
Module + Affected API + Change + Additional Remarks +
+ + + +
+ +### Drivers + + + + + + + + +
Module + Affected API + Change + Additional Remarks +
Position Sense HDSL + \ref HDSL_write_pc_buffer + Updated parameters to take only buffer offset and data, instead of data for all buffers. + - +
diff --git a/docs_src/docs/api_guide/device/am263x/components.cfg b/docs_src/docs/api_guide/device/am263x/components.cfg index baac63a..8c815bb 100644 --- a/docs_src/docs/api_guide/device/am263x/components.cfg +++ b/docs_src/docs/api_guide/device/am263x/components.cfg @@ -1,4 +1,6 @@ INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/position_sense.md INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/position_sense/tamagawa_uart.md +INPUT+= $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/rtlibs/rtlibs.md + INPUT+= $(MOTOR_CONTROL_SDK_PATH)/source/position_sense/tamagawa_over_soc_uart/include/tamagawa_soc_uart_interface.h \ No newline at end of file diff --git a/docs_src/docs/api_guide/device/am263x/includes.cfg b/docs_src/docs/api_guide/device/am263x/includes.cfg index 42fcfb0..7b488cf 100644 --- a/docs_src/docs/api_guide/device/am263x/includes.cfg +++ b/docs_src/docs/api_guide/device/am263x/includes.cfg @@ -11,10 +11,11 @@ INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/main_page/main_page.m INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/migration_guides/mcusdk_migration_guide.md INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes.md INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_00_00.md +INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_01_00.md @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/examples.cfg @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/components.cfg -@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/dcl/dcl.cfg -@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/transforms/transforms.cfg +@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/rtlibs/dcl/dcl.cfg +@INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/rtlibs/transforms/transforms.cfg # Used to selectively pick DEVICE specific sections within .md files ENABLED_SECTIONS = SOC_AM263X diff --git a/docs_src/docs/api_guide/device/am263x/release_notes.md b/docs_src/docs/api_guide/device/am263x/release_notes.md index d4c7104..e73dded 100644 --- a/docs_src/docs/api_guide/device/am263x/release_notes.md +++ b/docs_src/docs/api_guide/device/am263x/release_notes.md @@ -4,5 +4,6 @@ Refer the below pages for release specific information +- \subpage RELEASE_NOTES_09_01_00_PAGE - \subpage RELEASE_NOTES_09_00_00_PAGE diff --git a/docs_src/docs/api_guide/device/am263x/release_notes_09_01_00.md b/docs_src/docs/api_guide/device/am263x/release_notes_09_01_00.md new file mode 100644 index 0000000..3d866da --- /dev/null +++ b/docs_src/docs/api_guide/device/am263x/release_notes_09_01_00.md @@ -0,0 +1,198 @@ +# Release Notes 09.01.00 {#RELEASE_NOTES_09_01_00_PAGE} + +[TOC] + +\attention Also refer to individual module pages for more details on each feature, unsupported features, important usage guidelines. + +\attention For release notes of Industrial Communications SDK and MCU+ SDK, please refer to @VAR_SOC_NAME Industrial Communications SDK Release Notes 09.01.00 and @VAR_SOC_NAME MCU+ SDK Release Notes 09.01.00 respectively. + +\note The examples will show usage of SW modules and APIs on a specific CPU instance and OS combination. \n + Unless noted otherwise, the SW modules would work in both FreeRTOS and NORTOS environment. \n + Unless noted otherwise, the SW modules would work on any of the R5F's present on the SOC. \n + Unless noted otherwise, the SW modules would work on all supported EVMs \n + +## New in this Release + +Feature | Module +------------------------------------------------------------------------------------------------|----------------------------------- +Re-baseline to MCU+ SDK 09.01.00 and Industrial Communications SDK 09.01.00 | Motor Control SDK + +## Device and Validation Information + +SOC | Supported CPUs | EVM | Host PC +------|-----------------|------------------------------------------------------------------------------|----------------------------------------- +AM263x| R5F | AM263x ControlCard Revision E1 (referred to as am263x-cc in code). \n | Windows 10 64b or Ubuntu 18.04 64b +AM263x| R5F | AM263x LaunchPad Revision E2 (referred to as am263x-lp in code) | Windows 10 64b or Ubuntu 18.04 64b + +## Tools, Compiler and Other Open Source SW Module Information + +Tools | Supported CPUs | Version +------------------------|----------------|-------------------------------------------------------------- +Code Composer Studio | R5F | @VAR_CCS_VERSION_AM263X +SysConfig | R5F | @VAR_SYSCFG_VERSION_AM263X, build @VAR_SYSCFG_BUILD_AM263X +TI ARM CLANG | R5F | @VAR_TI_ARM_CLANG_VERSION +FreeRTOS Kernel | R5F | @VAR_FREERTOS_KERNEL_VERSION + +## Key Features + +### Position Sense + +Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested +-------------|----------------|-------------------|-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------- +Tamagawa | R5F | YES | FreeRTOS | Absolute position, Encoder ID, Reset, EEPROM Read, EEPROM Write, 2.5 Mbps and 5 Mbps Encoder Support | - + + + + + + + +## Limitations + + + + + +
ID + Head Line + Module + Reported in Release + Applicable Devices + Workaround +
MCUSDK-208 + gmake with -j can sometimes lock up Windows command prompt + Build + 7.3.0 + AM64x, AM243x + Use bash for windows as part of git for windows or don't use -j option +
+ + + + + + + + + + diff --git a/docs_src/docs/api_guide/doxy_warnings_am243x.txt b/docs_src/docs/api_guide/doxy_warnings_am243x.txt index e69de29..76a8f16 100644 --- a/docs_src/docs/api_guide/doxy_warnings_am243x.txt +++ b/docs_src/docs/api_guide/doxy_warnings_am243x.txt @@ -0,0 +1 @@ +C:/ti/motor_control_sdk/docs_src/docs/api_guide/examples/bissc_example.md:71: warning: Found \endcond command without matching \cond diff --git a/docs_src/docs/api_guide/doxygen.cfg b/docs_src/docs/api_guide/doxygen.cfg index acb56f2..8c18892 100644 --- a/docs_src/docs/api_guide/doxygen.cfg +++ b/docs_src/docs/api_guide/doxygen.cfg @@ -219,20 +219,17 @@ ALIASES+=inlineVideo{3}="\htmlonly