am64x/am243: SDFM: Add trigger based normal current sampling

- Add support for trigger based sampling by using IEP compare events - Add support for double update per PWM cycle - Fixed the IEP compare event hit value calculation - Tested with SDFM clock input from EPWM Fixes: PINDSW-5522, PINDSW-6544, PINDSW-6546 Signed-off-by: Achala Ram <a-ram@ti.com>
2023-08-19 14:43:53 +05:30 · 2023-08-19 14:43:53 +05:30 · c41804bd2e
commit c41804bd2e
parent a2640f8fde
43 changed files with 3026 additions and 2043 deletions
--- a/.metadata/.tirex/am243x.content.tirex.json
+++ b/.metadata/.tirex/am243x.content.tirex.json
@ -393,6 +393,38 @@
            ]
        ]
    },
+    {
+        "resourceType": "project.ccs",
+        "resourceClass": [
+            "example"
+        ],
+        "resourceSubClass": [
+            "example.general"
+        ],
+        "description": "A Icss Sdfm Example. CPU is R5FSS0-0 running FREERTOS.",
+        "name": "icss_sdfm",
+        "location": "../../examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
+        "devtools": [
+            "AM243x_LAUNCHPAD"
+        ],
+        "kernel": [
+            "freertos"
+        ],
+        "compiler": [
+            "ticlang"
+        ],
+        "subCategories": [
+            "current_sense",
+            "icss_sdfm",
+            "r5fss0-0_freertos"
+        ],
+        "mainCategories": [
+            [
+                "Examples",
+                "Development Tools"
+            ]
+        ]
+    },
    {
        "resourceType": "web.page",
        "resourceClass": [
--- a/examples/current_sense/icss_sdfm/.project/project_am243x.js
+++ b/examples/current_sense/icss_sdfm/.project/project_am243x.js
@ -4,11 +4,11 @@ let device = "am243x";

 const files = {
    common: [
-        "app_sddf.c",
+        "app_sdfm.c",
        "epwm_dc.c",
        "epwm_drv_aux.c",
        "epwm_mod.c",
-        "sddf.c",
+        "sdfm.c",
        "cfg_pad.c",
        "main.c",
    ],
@ -39,7 +39,7 @@ const includes_freertos_r5f = {
        "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
        "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f",
        "${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include",
-        "${MOTOR_CONTROL_SDK_PATH}/examples/icss_sdfm",
+        "${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm",
    ],
 };

@ -73,13 +73,14 @@ const templates_freertos_r5f =
        input: ".project/templates/am243x/freertos/main_freertos.c.xdt",
        output: "../main.c",
        options: {
-            entryFunction: "sddf_main",
+            entryFunction: "sdfm_main",
        },
    }
 ];

 const buildOptionCombos = [
    { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"},
+    { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-lp", os: "freertos"},
 ];

 function getComponentProperty() {
--- a/examples/current_sense/icss_sdfm/.project/project_am64x.js
+++ b/examples/current_sense/icss_sdfm/.project/project_am64x.js
@ -4,11 +4,11 @@ let device = "am64x";

 const files = {
    common: [
-        "app_sddf.c",
+        "app_sdfm.c",
        "epwm_dc.c",
        "epwm_drv_aux.c",
        "epwm_mod.c",
-        "sddf.c",
+        "sdfm.c",
        "cfg_pad.c",
        "main.c",
    ],
@ -39,7 +39,7 @@ const includes_freertos_r5f = {
        "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
        "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f",
        "${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include",
-        "${MOTOR_CONTROL_SDK_PATH}/examples/icss_sdfm",
+        "${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm",
    ],
 };

@ -74,7 +74,7 @@ const templates_freertos_r5f =
        input: ".project/templates/am64x/freertos/main_freertos.c.xdt",
        output: "../main.c",
        options: {
-            entryFunction: "sddf_main",
+            entryFunction: "sdfm_main",
        },
    }
 ];
--- a/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/main.c
+++ b/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/main.c
@ -45,11 +45,11 @@ StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
 StaticTask_t gMainTaskObj;
 TaskHandle_t gMainTask;

-void sddf_main(void *args);
+void sdfm_main(void *args);

 void freertos_main(void *args)
 {
-    sddf_main(NULL);
+    sdfm_main(NULL);

    vTaskDelete(NULL);
 }
--- a/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@ -36,7 +36,7 @@
            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F
            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f
            -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include
-            -I${MOTOR_CONTROL_SDK_PATH}/examples/icss_sdfm
+            -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm
            -mcpu=cortex-r5
            -mfloat-abi=hard
            -mfpu=vfpv3-d16
@ -96,7 +96,7 @@
            "
        ></configuration>
        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
-        <file path="../../../app_sddf.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        <file path="../../../app_sdfm.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
        <file path="../../../epwm_dc.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
@ -104,7 +104,7 @@
        </file>
        <file path="../../../epwm_mod.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
-        <file path="../../../sddf.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        <file path="../../../sdfm.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
        <file path="../../../cfg_pad.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
--- a/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
@ -38,11 +38,11 @@ ifeq ($(DEVICE_TYPE), HS)
 endif

 FILES_common := \
-	app_sddf.c \
+	app_sdfm.c \
 	epwm_dc.c \
 	epwm_drv_aux.c \
 	epwm_mod.c \
-	sddf.c \
+	sdfm.c \
 	cfg_pad.c \
 	main.c \
 	ti_drivers_config.c \
@ -66,7 +66,7 @@ INCLUDES_common := \
 	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
 	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
 	-I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \
-	-I${MOTOR_CONTROL_SDK_PATH}/examples/icss_sdfm \
+	-I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm \
 	-Igenerated \

 DEFINES_common := \
--- a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/example.syscfg
+++ b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/example.syscfg
@ -0,0 +1,132 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.00.00"
+ * @versions {"tool":"1.17.0+3128"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const epwm       = scripting.addModule("/drivers/epwm/epwm", {}, false);
+const epwm1      = epwm.addInstance();
+const epwm2      = epwm.addInstance();
+const gpio       = scripting.addModule("/drivers/gpio/gpio", {}, false);
+const gpio1      = gpio.addInstance();
+const gpio2      = gpio.addInstance();
+const gpio3      = gpio.addInstance();
+const gpio4      = gpio.addInstance();
+const gpio5      = gpio.addInstance();
+const gpio6      = gpio.addInstance();
+const gpio7      = gpio.addInstance();
+const pruicss    = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1   = pruicss.addInstance();
+const debug_log  = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7  = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+epwm1.$name            = "CONFIG_EPWM0";
+epwm1.EPWM.$assign     = "EHRPWM0";
+epwm1.EPWM.SYNCI.$used = false;
+
+epwm2.$name              = "CONFIG_EPWM1";
+epwm2.EPWM.SYNCO.$assign = "GPMC0_AD1";
+epwm2.EPWM.SYNCO.$used   = false;
+epwm2.EPWM.SYNCI.$used   = false;
+
+gpio1.$name                    = "GPIO_MTR_1_PWM_EN";
+gpio1.pinDir                   = "OUTPUT";
+gpio1.useMcuDomainPeripherals  = true;
+gpio1.MCU_GPIO.gpioPin.$assign = "MCU_UART0_RXD";
+
+gpio2.pinDir               = "OUTPUT";
+gpio2.$name                = "GPIO_HIGH_TH_CH0";
+gpio2.GPIO.$assign         = "GPIO0";
+gpio2.GPIO.gpioPin.rx      = false;
+gpio2.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO18";
+
+gpio3.$name                = "GPIO_LOW_TH_CH0";
+gpio3.pinDir               = "OUTPUT";
+gpio3.GPIO.gpioPin.rx      = false;
+gpio3.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO11";
+
+gpio4.pinDir               = "OUTPUT";
+gpio4.$name                = "GPIO_HIGH_TH_CH1";
+gpio4.GPIO.$assign         = "GPIO0";
+gpio4.GPIO.gpioPin.rx      = false;
+gpio4.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO17";
+
+gpio5.$name                = "GPIO_LOW_TH_CH1";
+gpio5.pinDir               = "OUTPUT";
+gpio5.GPIO.$assign         = "GPIO0";
+gpio5.GPIO.gpioPin.rx      = false;
+gpio5.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO7";
+
+gpio6.pinDir               = "OUTPUT";
+gpio6.$name                = "GPIO_HIGH_TH_CH2";
+gpio6.GPIO.gpioPin.rx      = false;
+gpio6.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO1";
+
+gpio7.$name                = "GPIO_LOW_TH_CH2";
+gpio7.pinDir               = "OUTPUT";
+gpio7.GPIO.gpioPin.rx      = false;
+gpio7.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO2";
+
+pruicss1.$name                           = "CONFIG_PRU_ICSS0";
+pruicss1.coreClk                         = 300000000;
+pruicss1.iepClk                          = 300000000;
+pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
+
+debug_log.enableUartLog        = true;
+debug_log.uartLog.$name        = "CONFIG_UART_CONSOLE";
+debug_log.uartLog.UART.$assign = "USART0";
+
+mpu_armv71.$name             = "CONFIG_MPU_REGION0";
+mpu_armv71.size              = 31;
+mpu_armv71.attributes        = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv71.allowExecute      = false;
+
+mpu_armv72.$name             = "CONFIG_MPU_REGION1";
+mpu_armv72.size              = 15;
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv73.$name             = "CONFIG_MPU_REGION2";
+mpu_armv73.baseAddr          = 0x41010000;
+mpu_armv73.size              = 15;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name             = "CONFIG_MPU_REGION3";
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv74.baseAddr          = 0x70000000;
+mpu_armv74.size              = 21;
+
+mpu_armv75.$name             = "CONFIG_MPU_REGION4";
+mpu_armv75.baseAddr          = 0x60000000;
+mpu_armv75.size              = 28;
+mpu_armv75.accessPermissions = "Supervisor RD, User RD";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+epwm1.EPWM.A.$suggestSolution               = "GPMC0_AD3";
+epwm1.EPWM.B.$suggestSolution               = "GPMC0_AD4";
+epwm1.EPWM.SYNCO.$suggestSolution           = "GPMC0_AD1";
+epwm2.EPWM.$suggestSolution                 = "EHRPWM1";
+epwm2.EPWM.A.$suggestSolution               = "GPMC0_AD5";
+epwm2.EPWM.B.$suggestSolution               = "GPMC0_AD6";
+gpio1.MCU_GPIO.$suggestSolution             = "MCU_GPIO0";
+gpio3.GPIO.$suggestSolution                 = "GPIO1";
+gpio6.GPIO.$suggestSolution                 = "GPIO1";
+gpio7.GPIO.$suggestSolution                 = "GPIO1";
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
--- a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/main.c
+++ b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/main.c
@ -0,0 +1,84 @@
+/*
+ *  Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <kernel/dpl/DebugP.h>
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI  (configMAX_PRIORITIES-1)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void sdfm_main(void *args);
+
+void freertos_main(void *args)
+{
+    sdfm_main(NULL);
+
+    vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+    /* init SOC specific modules */
+    System_init();
+    Board_init();
+
+    /* This task is created at highest priority, it should create more tasks and then delete itself */
+    gMainTask = xTaskCreateStatic( freertos_main,   /* Pointer to the function that implements the task. */
+                                  "freertos_main", /* Text name for the task.  This is to facilitate debugging only. */
+                                  MAIN_TASK_SIZE,  /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+                                  NULL,            /* We are not using the task parameter. */
+                                  MAIN_TASK_PRI,   /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+                                  gMainTaskStack,  /* pointer to stack base */
+                                  &gMainTaskObj ); /* pointer to statically allocated task object memory */
+    configASSERT(gMainTask != NULL);
+
+    /* Start the scheduler to start the tasks executing. */
+    vTaskStartScheduler();
+
+    /* The following line should never be reached because vTaskStartScheduler()
+    will only return if there was not enough FreeRTOS heap memory available to
+    create the Idle and (if configured) Timer tasks.  Heap management, and
+    techniques for trapping heap exhaustion, are described in the book text. */
+    DebugP_assertNoLog(0);
+
+    return 0;
+}
--- a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@ -0,0 +1,125 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="ARM"
+                deviceId="Cortex R.AM2434_ALX"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="Icss Sdfm"
+        name = "icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang"
+        products="sysconfig;com.ti.MOTOR_CONTROL_SDK_AMXXX;"
+        configurations="
+                Debug,
+                Release,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TICLANG"
+        cgtVersion="2.1.3"
+        device="Cortex R.AM2434_ALX"
+        deviceCore="MAIN_PULSAR_Cortex_R5_0_0"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${CG_TOOL_ROOT}/include/c
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source
+            -I${MOTOR_CONTROL_SDK_PATH}/source
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f
+            -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include
+            -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm
+            -mcpu=cortex-r5
+            -mfloat-abi=hard
+            -mfpu=vfpv3-d16
+            -mthumb
+            -Wall
+            -Werror
+            -g
+            -Wno-gnu-variable-sized-type-not-at-end
+            -Wno-unused-function
+            -DSOC_AM243X
+        "
+        linkerBuildOptions="
+            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib
+            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib
+            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib
+            -i${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/lib
+            -i${CG_TOOL_ROOT}/lib
+            -m=icss_sdfm.${ConfigName}.map
+            --diag_suppress=10063
+            --ram_model
+            --reread_libs
+        "
+
+        postBuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=am243x"
+
+        enableSysConfigTool="true"
+        sysConfigBuildOptions="
+            --context r5fss0-0 --part ALX --package ALX
+        "
+
+        description="A Icss Sdfm FREERTOS project">
+
+        <configuration name="Debug"
+            compilerBuildOptions="
+                -D_DEBUG_=1
+            "
+            linkerBuildOptions="
+                -lfreertos.am243x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am243x.r5f.ti-arm-clang.debug.lib
+                -lboard.am243x.r5f.ti-arm-clang.debug.lib
+                -lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.debug.lib
+                -llibc.a
+                -llibsysbm.a
+            "
+        ></configuration>
+        <configuration name="Release"
+            compilerBuildOptions="
+                -Os
+            "
+            linkerBuildOptions="
+                -lfreertos.am243x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am243x.r5f.ti-arm-clang.release.lib
+                -lboard.am243x.r5f.ti-arm-clang.release.lib
+                -lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.release.lib
+                -llibc.a
+                -llibsysbm.a
+            "
+        ></configuration>
+        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
+        <file path="../../../app_sdfm.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../epwm_dc.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../epwm_drv_aux.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../epwm_mod.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../sdfm.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../cfg_pad.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../main.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="linker.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../example.syscfg" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/EXAMPLE_MOTORCONTROL_SDFM.html"
+                openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
+        </file>
+        <file path="syscfg_c.rov.xs" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="makefile_ccs_bootimage_gen" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+    </project>
+</projectSpec>
--- a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@ -0,0 +1,148 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ *   uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors  /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256;  /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256;  /* This is the size of stack when R5 is in UNDEF mode */
+
+SECTIONS
+{
+    /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+    .vectors:{} palign(8) > R5F_VECS
+
+    /* This has the R5F boot code until MPU is enabled,  this MUST be at a address < 0x80000000
+     * i.e this cannot be placed in DDR
+     */
+    GROUP {
+        .text.hwi: palign(8)
+        .text.cache: palign(8)
+        .text.mpu: palign(8)
+        .text.boot: palign(8)
+        .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+    } > MSRAM
+
+    /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .text:   {} palign(8)   /* This is where code resides */
+        .rodata: {} palign(8)   /* This is where const's go */
+    } > MSRAM
+
+    /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .data:   {} palign(8)   /* This is where initialized globals and static go */
+    } > MSRAM
+
+    /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .bss:    {} palign(8)   /* This is where uninitialized globals go */
+        RUN_START(__BSS_START)
+        RUN_END(__BSS_END)
+        .sysmem: {} palign(8)   /* This is where the malloc heap goes */
+        .stack:  {} palign(8)   /* This is where the main() stack goes */
+    } > MSRAM
+
+    /* This is where the stacks for different R5F modes go */
+    GROUP {
+        .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+        RUN_START(__IRQ_STACK_START)
+        RUN_END(__IRQ_STACK_END)
+        .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+        RUN_START(__FIQ_STACK_START)
+        RUN_END(__FIQ_STACK_END)
+        .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+        RUN_START(__SVC_STACK_START)
+        RUN_END(__SVC_STACK_END)
+        .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+        RUN_START(__ABORT_STACK_START)
+        RUN_END(__ABORT_STACK_END)
+        .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+        RUN_START(__UNDEFINED_STACK_START)
+        RUN_END(__UNDEFINED_STACK_END)
+    } > MSRAM
+
+    /* Sections needed for C++ projects */
+    GROUP {
+        .ARM.exidx:  {} palign(8)   /* Needed for C++ exception handling */
+        .init_array: {} palign(8)   /* Contains function pointers called before main */
+        .fini_array: {} palign(8)   /* Contains function pointers called after main */
+    } > MSRAM
+
+    /* General purpose user shared memory, used in some examples */
+    .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+    /* this is used when Debug log's to shared memory are enabled, else this is not used */
+    .bss.log_shared_mem  (NOLOAD) : {} > LOG_SHM_MEM
+    /* this is used only when IPC RPMessage is enabled, else this is not used */
+    .bss.ipc_vring_mem   (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+    /* General purpose non cacheable memory, used in some examples */
+    .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+   0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+   0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+   TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+    R5F_VECS  : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+    R5F_TCMA  : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+    R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+    /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+    NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+    /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+     * this memory does not overlap with other R5F's
+     */
+    MSRAM     : ORIGIN = 0x70080000 , LENGTH = 0x40000
+
+    /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+     * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+     */
+    FLASH     : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+    /* shared memory segments */
+    /* On R5F,
+     * - make sure there is a MPU entry which maps below regions as non-cache
+     */
+    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x180
+    LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
+    RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}
--- a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@ -0,0 +1,314 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=icss_sdfm.$(PROFILE).out
+
+BOOTIMAGE_PATH=$(abspath .)
+BOOTIMAGE_NAME:=icss_sdfm.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=icss_sdfm.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=icss_sdfm.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=icss_sdfm.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=icss_sdfm.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=icss_sdfm.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=icss_sdfm.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=icss_sdfm.$(PROFILE).appimage.hs_fs
+TARGETS := $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_HS)
+endif
+
+FILES_common := \
+	app_sdfm.c \
+	epwm_dc.c \
+	epwm_drv_aux.c \
+	epwm_mod.c \
+	sdfm.c \
+	cfg_pad.c \
+	main.c \
+	ti_drivers_config.c \
+	ti_drivers_open_close.c \
+	ti_board_config.c \
+	ti_board_open_close.c \
+	ti_dpl_config.c \
+	ti_pinmux_config.c \
+	ti_power_clock_config.c \
+
+FILES_PATH_common = \
+	.. \
+	../../.. \
+	generated \
+
+INCLUDES_common := \
+	-I${CG_TOOL_ROOT}/include/c \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+	-I${MOTOR_CONTROL_SDK_PATH}/source \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
+	-I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \
+	-I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm \
+	-Igenerated \
+
+DEFINES_common := \
+	-DSOC_AM243X \
+
+CFLAGS_common := \
+	-mcpu=cortex-r5 \
+	-mfloat-abi=hard \
+	-mfpu=vfpv3-d16 \
+	-mthumb \
+	-Wall \
+	-Werror \
+	-g \
+	-Wno-gnu-variable-sized-type-not-at-end \
+	-Wno-unused-function \
+
+CFLAGS_cpp_common := \
+	-Wno-c99-designator \
+	-Wno-extern-c-compat \
+	-Wno-c++11-narrowing \
+	-Wno-reorder-init-list \
+	-Wno-deprecated-register \
+	-Wno-writable-strings \
+	-Wno-enum-compare \
+	-Wno-reserved-user-defined-literal \
+	-Wno-unused-const-variable \
+	-x c++ \
+
+CFLAGS_debug := \
+	-D_DEBUG_=1 \
+
+CFLAGS_release := \
+	-Os \
+
+LNK_FILES_common = \
+	linker.cmd \
+
+LIBS_PATH_common = \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/lib \
+	-Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+	-lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-llibc.a \
+	-llibsysbm.a \
+
+LFLAGS_common = \
+	-Wl,--diag_suppress=10063 \
+	-Wl,--ram_model \
+	-Wl,--reread_libs \
+
+
+LIBS_NAME = \
+	freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	motorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	libc.a \
+	libsysbm.a \
+
+LIBS_PATH_NAME = \
+	${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+	${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+	${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+	${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/lib \
+	${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+	@echo  Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+	@echo  Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+	$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+	@echo  .
+	@echo  Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
+	$(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
+	@echo  Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+	@echo  .
+
+clean:
+	@echo  Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+	$(RMDIR) $(OBJDIR)
+	$(RM) $(OUTNAME)
+	$(RM) $(BOOTIMAGE_NAME)
+	$(RM) $(BOOTIMAGE_NAME_XIP)
+	$(RM) $(BOOTIMAGE_NAME_SIGNED)
+	$(RM) $(BOOTIMAGE_NAME_HS)
+	$(RM) $(BOOTIMAGE_NAME_HS_FS)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+	$(RMDIR) generated/
+
+scrub:
+	@echo  Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang icss_sdfm ...
+	$(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+	$(RM) \*.out
+	$(RM) \*.map
+	$(RM) \*.appimage*
+	$(RM) \*.rprc*
+	$(RM) \*.tiimage*
+	$(RM) \*.bin
+else
+	$(RM) *.out
+	$(RM) *.map
+	$(RM) *.appimage*
+	$(RM) *.rprc*
+	$(RM) *.tiimage*
+	$(RM) *.bin
+endif
+	$(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+	$(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+syscfg: ../example.syscfg
+	@echo Generating SysConfig files ...
+	$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+
+syscfg-gui:
+	$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALX_beta --context r5fss0-0 --part ALX --package ALX --output generated/  ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+$(BOOTIMAGE_NAME): $(OUTNAME)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+ifneq ($(OS),Windows_NT)
+	$(CHMOD) a+x $(XIPGEN_CMD)
+endif
+	$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
+	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+	@echo  .
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+	@echo  .
+
+$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+	@echo Boot image signing: Encryption is disabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+else
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
+	$(RM) $(BOOTIMAGE_NAME)-enc
+endif
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+	@echo  .
+endif
+-include $(addprefix $(OBJDIR)/, $(DEPS))
--- a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@ -0,0 +1,106 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MOTOR_CONTROL_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
+include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+#	No post build steps
+else
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
+	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+	@echo Boot image signing: Encryption is disabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+	$(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+	@echo  .
+ifeq ($(DEVICE_TYPE),HS)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+	@echo  .
+else
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo  .
+endif
+endif
--- a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
+++ b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
--- a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
+++ b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@ -0,0 +1,8 @@
+/*
+ *  ======== syscfg_c.rov.xs ========
+ *  This file contains the information needed by the Runtime Object
+ *  View (ROV) tool.
+ */
+var crovFiles = [
+    "kernel/freertos/rov/FreeRTOS.rov.js",
+];
--- a/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/main.c
+++ b/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/main.c
@ -45,11 +45,11 @@ StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
 StaticTask_t gMainTaskObj;
 TaskHandle_t gMainTask;

-void sddf_main(void *args);
+void sdfm_main(void *args);

 void freertos_main(void *args)
 {
-    sddf_main(NULL);
+    sdfm_main(NULL);

    vTaskDelete(NULL);
 }
--- a/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@ -36,7 +36,7 @@
            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F
            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f
            -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include
-            -I${MOTOR_CONTROL_SDK_PATH}/examples/icss_sdfm
+            -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm
            -mcpu=cortex-r5
            -mfloat-abi=hard
            -mfpu=vfpv3-d16
@ -96,7 +96,7 @@
            "
        ></configuration>
        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
-        <file path="../../../app_sddf.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        <file path="../../../app_sdfm.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
        <file path="../../../epwm_dc.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
@ -104,7 +104,7 @@
        </file>
        <file path="../../../epwm_mod.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
-        <file path="../../../sddf.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        <file path="../../../sdfm.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
        <file path="../../../cfg_pad.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
--- a/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
@ -38,11 +38,11 @@ ifeq ($(DEVICE_TYPE), HS)
 endif

 FILES_common := \
-	app_sddf.c \
+	app_sdfm.c \
 	epwm_dc.c \
 	epwm_drv_aux.c \
 	epwm_mod.c \
-	sddf.c \
+	sdfm.c \
 	cfg_pad.c \
 	main.c \
 	ti_drivers_config.c \
@ -66,7 +66,7 @@ INCLUDES_common := \
 	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
 	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f \
 	-I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \
-	-I${MOTOR_CONTROL_SDK_PATH}/examples/icss_sdfm \
+	-I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm \
 	-Igenerated \

 DEFINES_common := \
--- a/examples/current_sense/icss_sdfm/app_sdfm.c
+++ b/examples/current_sense/icss_sdfm/app_sdfm.c
@ -41,8 +41,10 @@

 #include "epwm_dc.h"
 #include "cfg_pad.h"
-#include "sddf.h"
+#include "sdfm.h"

+/*EPWM1 configuration for sigma delta clock generation: */
+#define APP_EPWM1_ENABLE  0 /*make sure EPWM1 is added in sysconfig before making true this macro */
 /* Output channel - A or B */
 #define APP_EPWM_OUT_CH_EN              ( 0x1 ) /* ChA enabled */

@ -73,7 +75,9 @@
 #define APP_EPWM_OUTPUT_FREQ            ( APP_EPWM_OUTPUT_FREQ_8K ) /* init freq */

 /*sample Read time */
-#define SAMPLE_READ_TIME                ((float)(1000000/(2*APP_EPWM_OUTPUT_FREQ))) //Middle of PWM loop
+#define FIRST_SAMPLE_TRIGGER_TIME                ((float)((float)1000000/(4*APP_EPWM_OUTPUT_FREQ))) /*sample trigger time for Single Update */
+
+#define SECOND_SAMPLE_TRIGGER_TIME               ((float)((float)3000000/(4*APP_EPWM_OUTPUT_FREQ))) /*Sample trigger time for double update*/

 /* PWM count direction (Up, Down, Up/Down) */
 #define APP_EPWM_TB_COUNTER_DIR         ( EPWM_TB_COUNTER_DIR_UP_DOWN )
@ -87,47 +91,72 @@
 #define TEST_RTU_INST_ID                ( PRUICSS_RTU_PRU0 )

 /* R5F interrupt settings for ICSSG */
-#define ICSSG_PRU_SDDF_INT_NUM          ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_0 )  /* VIM interrupt number */
-#define ICSSG_RTU_SDDF_INT_NUM          ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_1 )  /* VIM interrupt number */
+#define ICSSG_PRU_SDFM_INT_NUM          ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_0 )  /* VIM interrupt number */
+#define ICSSG_RTU_SDFM_INT_NUM          ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_1 )  /* VIM interrupt number */

 /* EPWM0 IRQ handler */
 static void epwmIrqHandler(void *handle);

+/* EPWM1 IRQ handler */
+static void epwmIrqHandler1(void *handle);
+
 /* HWI global variables */
-static HwiP_Object gIcssgPruSddfHwiObject;  /* ICSSG PRU SDDF FW HWI */
-//static HwiP_Object gIcssgRtuSddfHwiObject;  /* ICSSG RTU SDDF FW HWI */
+static HwiP_Object gIcssgPruSdfmHwiObject;  /* ICSSG PRU SDFM FW HWI */
+
+#if APP_EPWM1_ENABLE
+#define APP_EPWM_OUTPUT_FREQ1            (1U*20000000 )
+static HwiP_Object gIcssgRtuSDFMHwiObject;  /* ICSSG RTU SDFM FW HWI */
+
+static HwiP_Object gEpwm1HwiObject;         /* EPWM1 HWI */
+
+uint32_t gEpwm1BaseAddr;    /* EPWM1 base address */
+EPwmObj_t gEpwm1Obj;        /* EPWM1 object */
+Epwm_Handle hEpwm1;         /* EPWM1 handle */
+
+volatile uint32_t gEpwmOutFreq1 = APP_EPWM_OUTPUT_FREQ1; /*EPWM1 output freq. */
+
+#endif
+
 static HwiP_Object gEpwm0HwiObject;         /* EPWM0 HWI */

 /* EPWM global variables */
 uint32_t gEpwm0BaseAddr;    /* EPWM0 base address */
 EPwmObj_t gEpwm0Obj;        /* EPWM0 object */
 Epwm_Handle hEpwm0;         /* EPWM0 handle */
+
+
+
 volatile uint32_t gEpwmOutFreq = APP_EPWM_OUTPUT_FREQ; /* EPWM output frequency */

-/* ICSSG PRU SDDF FW IRQ handler */
-static void pruSddfIrqHandler(void *handle);
+
+/* ICSSG PRU SDFM FW IRQ handler */
+static void pruSdfmIrqHandler(void *handle);


 /* Test ICSSG handle */
 PRUICSS_Handle gPruIcssHandle;

-/* Test SDDF handles */
-sdfm_handle gHPruSddf;
+/* Test Sdfm handles */
+sdfm_handle gHPruSdfm;


-/* Test SDDF parameters */
-SddfPrms gTestSddfPrms = {
-    SAMPLE_READ_TIME,       // trigSampTime in us; always middel of PWM cycle
-    APP_EPWM_OUTPUT_FREQ,        // PWM output frequency
-    {{3500,2500,0},    //threshold parameters(High, low & reserevd)
-    {3500,2500,0},
-    {3500,2500,0}},
-    {{0,0},                //clock sourse & clock inversion for all channels
+/* Test Sdfm parameters */
+SdfmPrms gTestSdfmPrms = {
+    300000000,   /*Value of IEP clock*/
+    20000000,    /*Value of SD clock (It should be exact equal to sd clock value)*/
+    0,                        /*enable double update*/
+    FIRST_SAMPLE_TRIGGER_TIME,       /*first sample  trigger time*/
+    SECOND_SAMPLE_TRIGGER_TIME,       /*second sample trigger time*/
+    APP_EPWM_OUTPUT_FREQ,     /*PWM output frequency*/
+    {{3500, 1000,0},    /*threshold parameters(High, low & reserevd)*/
+    {3500, 1000,0},
+    {3500, 1000,0}},
+    {{0,0},                /*clock sourse & clock inversion for all channels*/
    {0,0},
    {0,0}},
-     32,   //OC osr
-     64,   //NC osr
-     1   //comparator enable
+     15,   /*Over current osr: The effect count is OSR + 1*/
+     128,   /*Normal current osr */
+     1   /*comparator enable*/
 };

 #define PRUICSS_G_MUX_EN    ( 0x1 ) /* ICSSG_SA_MX_REG:G_MUX_EN */
@ -155,12 +184,14 @@ uint32_t sdfm_ch2_idx = 0;


 /* IRQ counters */
-volatile uint32_t gPruSddfIrqCnt=0; /* PRU SDDF FW IRQ count */
+volatile uint32_t gPruSdfmIrqCnt=0; /* PRU Sdfm FW IRQ count */
 volatile uint32_t gEpwmIsrCnt=0;    /* EPWM0 IRQ count */
-
+volatile uint32_t gEpwmIsrCnt1=0;
 /*PWM Parameters*/
 HwiP_Params hwiPrms;
+HwiP_Params hwiPrms1;
 EPwmCfgPrms_t epwmCfgPrms;
+EPwmCfgPrms_t epwm1CfgPrms;

 void init_pwm()
 {
@ -206,6 +237,46 @@ void init_pwm()
    hEpwm0 = epwmInit(&epwmCfgPrms, &gEpwm0Obj);
    DebugP_assert(hEpwm0 != NULL);

+#if APP_EPWM1_ENABLE  // DEBUG code for SDFM clock generation from EPWM1
+    /* EPWM1 for SD clock generation */
+    /* Initialize EPWM1 base address, perform address translation */
+    gEpwm1BaseAddr = (uint32_t)AddrTranslateP_getLocalAddr(CONFIG_EPWM1_BASE_ADDR);
+    /* Register & enable EPWM0 interrupt */
+    HwiP_Params_init(&hwiPrms1);
+    hwiPrms1.intNum      = CONFIG_EPWM1_INTR;
+    hwiPrms1.callback    = &epwmIrqHandler1;
+    hwiPrms1.args        = 0;
+    hwiPrms1.isPulse     = CONFIG_EPWM1_INTR_IS_PULSE;
+    hwiPrms1.isFIQ       = FALSE;
+    status              = HwiP_construct(&gEpwm1HwiObject, &hwiPrms1);
+    DebugP_assert(status == SystemP_SUCCESS);
+    /* Configure EPWM0 */
+    epwm1CfgPrms.epwmId = EPWM_ID_1;
+    epwm1CfgPrms.epwmBaseAddr = gEpwm1BaseAddr;
+    epwm1CfgPrms.epwmOutChEn = APP_EPWM_OUT_CH_EN;
+    epwm1CfgPrms.hspClkDiv = APP_EPWM_FCLK_HSPCLKDIV;
+    epwm1CfgPrms.clkDiv = APP_EPWM_FCLK_CLKDIV;
+    epwm1CfgPrms.epwmTbFreq = APP_EPWM_TB_FREQ;
+    epwm1CfgPrms.epwmOutFreq = gEpwmOutFreq1;
+    epwm1CfgPrms.epwmDutyCycle[EPWM_OUTPUT_CH_A] = APP_EPWM0_DUTY_CYCLE;
+    epwm1CfgPrms.epwmTbCounterDir = APP_EPWM_TB_COUNTER_DIR;
+    epwm1CfgPrms.cfgTbSyncIn = FALSE;
+    epwm1CfgPrms.tbPhsValue = 0;
+    epwm1CfgPrms.cfgTbSyncOut = FALSE;
+    epwm1CfgPrms.tbSyncOutMode = EPWM_TB_SYNC_OUT_EVT_CNT_EQ_ZERO;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].zeroAction = EPWM_AQ_ACTION_DONOTHING;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].prdAction = EPWM_AQ_ACTION_DONOTHING;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpAUpAction = EPWM_AQ_ACTION_HIGH;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpADownAction = EPWM_AQ_ACTION_LOW;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpBUpAction = EPWM_AQ_ACTION_DONOTHING;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpBDownAction = EPWM_AQ_ACTION_DONOTHING;
+    epwm1CfgPrms.cfgDb = FALSE;
+    epwm1CfgPrms.cfgEt = FALSE;
+    epwm1CfgPrms.intSel = EPWM_ET_INTR_EVT_CNT_EQ_ZRO;
+    epwm1CfgPrms.intPrd = EPWM_ET_INTR_PERIOD_FIRST_EVT;
+    hEpwm1 = epwmInit(&epwm1CfgPrms, &gEpwm1Obj);
+    DebugP_assert(hEpwm1 != NULL);
+#endif 
 }

 void init_sdfm()
@ -213,30 +284,31 @@ void init_sdfm()
    int32_t status;
    /* Initialize ICSSG */
    status = initIcss(TEST_ICSSG_INST_ID, TEST_ICSSG_SLICE_ID, PRUICSS_G_MUX_EN, &gPruIcssHandle);
-    if (status != SDDF_ERR_NERR) {
+    if (status != SDFM_ERR_NERR) {
        DebugP_log("Error: initIcss() fail.\r\n");
        return;
    }

-    /* Register & enable ICSSG PRU SDDF FW interrupt */
+    /* Register & enable ICSSG PRU SDFM FW interrupt */
    HwiP_Params_init(&hwiPrms);
-    hwiPrms.intNum      = ICSSG_PRU_SDDF_INT_NUM;
-    hwiPrms.callback    = &pruSddfIrqHandler;
+    hwiPrms.intNum      = ICSSG_PRU_SDFM_INT_NUM;
+    hwiPrms.callback    = &pruSdfmIrqHandler;
    hwiPrms.args        = 0;
    hwiPrms.isPulse     = FALSE;
    hwiPrms.isFIQ       = FALSE;
-    status              = HwiP_construct(&gIcssgPruSddfHwiObject, &hwiPrms);
+    status              = HwiP_construct(&gIcssgPruSdfmHwiObject, &hwiPrms);
    DebugP_assert(status == SystemP_SUCCESS);

-    /* Initialize PRU core for SDDF */
-    status = initPruSddf(gPruIcssHandle, TEST_PRU_INST_ID, &gTestSddfPrms, &gHPruSddf);
-    if (status != SDDF_ERR_NERR) {
-        DebugP_log("Error: initPruSddf() fail.\r\n");
+    /* Initialize PRU core for SDFM */
+    status = initPruSdfm(gPruIcssHandle, TEST_PRU_INST_ID, &gTestSdfmPrms, &gHPruSdfm);
+    if (status != SDFM_ERR_NERR) 
+    {
+        DebugP_log("Error: initPruSdfm() fail.\r\n");
        return;
    }

 }
-void sddf_main(void *args)
+void sdfm_main(void *args)
 {

    /* Open drivers to open the UART driver for console */
@ -260,10 +332,10 @@ void sddf_main(void *args)
    init_pwm();
    DebugP_log("EPWM Configured!\r\n");
    /*
-     *  Configure SDDF
+     *  Configure SDFM
     */

-    /* Configure SOC pads for SDDF.
+    /* Configure SOC pads for SDFM.
       Normally handled via Pinmux_init(),
       but currently no way to pads for ICSSG from Sysconfig. */
    cfgPad();
@ -290,11 +362,8 @@ void sddf_main(void *args)
    /* Destroy EPWM0 HWI */
    HwiP_destruct(&gEpwm0HwiObject);

-    /* Destroy PRU SDDF HWI */
-    HwiP_destruct(&gIcssgPruSddfHwiObject);
-
-    /* Destroy RTU SDDF HWI */
-    //HwiP_destruct(&gIcssgRtuSddfHwiObject);
+    /* Destroy PRU SDFM HWI */
+    HwiP_destruct(&gIcssgPruSdfmHwiObject);

    DebugP_log("All tests have passed!!\r\n");

@ -302,17 +371,17 @@ void sddf_main(void *args)
    Drivers_close();
 }

-/* PRU SDDF FW IRQ handler */
-void pruSddfIrqHandler(void *args)
+/* PRU SDFM FW IRQ handler */
+void pruSdfmIrqHandler(void *args)
 {
-    /* debug, inncrement PRU SDDF IRQ count */
-    gPruSddfIrqCnt++;
+    /* debug, inncrement PRU SDFM IRQ count */
+    gPruSdfmIrqCnt++;
    /* Clear interrupt at source */
    /* Write 18 to ICSSG_STATUS_CLR_INDEX_REG
-        Firmware:   TRIGGER_HOST_SDDF_IRQ defined as 18
+        Firmware:   TRIGGER_HOST_SDFM_IRQ defined as 18
        18 = 16+2, 2 is Host Interrupt Number. See AM64x TRM.
    */
-    PRUICSS_clearEvent(gPruIcssHandle, PRU_TRIGGER_HOST_SDDF_EVT);
+    PRUICSS_clearEvent(gPruIcssHandle, PRU_TRIGGER_HOST_SDFM_EVT);

   /* SDFM Output sample for Channel 0 */
    sdfm_ch0_samples[sdfm_ch0_idx++] = SDFM_getFilterData(0);
@ -342,8 +411,27 @@ static void epwmIrqHandler(void *args)
    gEpwmIsrCnt++;

    status = EPWM_etIntrStatus(gEpwm0BaseAddr);
-    if (status & EPWM_ETFLG_INT_MASK) {
+    if (status & EPWM_ETFLG_INT_MASK) 
+    {
        EPWM_etIntrClear(gEpwm0BaseAddr);
    }
    return;
 }
+
+#if APP_EPWM1_ENABLE //DEBUG code for EPWM1
+/* EPWM0 IRQ handler */
+static void epwmIrqHandler1(void *args)
+{
+    volatile uint16_t status;
+
+    /* debug, inncrement EPWM0 IRQ count */
+    gEpwmIsrCnt1++;
+
+    status = EPWM_etIntrStatus(gEpwm1BaseAddr);
+    if (status & EPWM_ETFLG_INT_MASK) 
+    {
+        EPWM_etIntrClear(gEpwm0BaseAddr);
+    }
+    return;
+}
+#endif
--- a/examples/current_sense/icss_sdfm/cfg_pad.c
+++ b/examples/current_sense/icss_sdfm/cfg_pad.c
@ -33,7 +33,7 @@
 #include <drivers/pinmux.h>
 #include "cfg_pad.h"

-static Pinmux_PerCfg_t gPinMuxMainDomainCfgSddf[] = {
+static Pinmux_PerCfg_t gPinMuxMainDomainCfgsdfm[] = {

    /* PRG0_ECAP0_IN_APWM_OUT,
       PRG0_PRU1_GPO15, PRG0_ECAP0_IN_APWM_OUT, U5, J2.C11  */
@ -65,48 +65,12 @@ static Pinmux_PerCfg_t gPinMuxMainDomainCfgSddf[] = {
        PIN_PRG0_PRU0_GPO5,
        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
    },
-    /* SD3_D,
-       PRG0_PRU0_GPI7,  SD3_D,      T1, J2B:P7  */
-    {
-        PIN_PRG0_PRU0_GPO7,
-        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
-    },
-    /* SD4_D,
-       PRG0_PRU0_GPI18,  SD4_D,     V1, J2B:P9  */
-    {
-        PIN_PRG0_PRU0_GPO18,
-        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
-    },
-    /* SD5_D,
-       PRG0_PRU0_GPI11, SD5_D,      Y3, J2B:P14 */
-    {
-        PIN_PRG0_PRU0_GPO11,
-        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
-    },
-    /* SD6_D,
-       PRG0_PRU0_GPI13, SD6_D,      R6, J2C:P5  */
-    {
-        PIN_PRG0_PRU0_GPO13,
-        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
-    },
-    /* SD7_D,
-       PRG0_PRU0_GPI15, SD7_D,      T5, J2D:P12 */
-    {
-        PIN_PRG0_PRU0_GPO15,
-        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
-    },
-    /* SD8_D,
-       PRG0_PRU0_GPI17, SD8_D,      U1, J2B:P8  */
-    {
-        PIN_PRG0_PRU0_GPO17,
-        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
-    },
-
+    
    {PINMUX_END, PINMUX_END}
 };

 /* Configure SOC pads */
 void cfgPad(void)
 {
-    Pinmux_config(gPinMuxMainDomainCfgSddf, PINMUX_DOMAIN_ID_MAIN);
+    Pinmux_config(gPinMuxMainDomainCfgsdfm, PINMUX_DOMAIN_ID_MAIN);
 }
--- a/examples/current_sense/icss_sdfm/sdfm.c
+++ b/examples/current_sense/icss_sdfm/sdfm.c
@ -41,23 +41,23 @@
 #include <drivers/pruicss.h>
 #include <drivers/sciclient.h>

-#include "tisddf_pruss_intc_mapping.h"  /* INTC configuration */
-#include "current_sense/sdfm/firmware/sdfm_bin.h"            /* SDDF image data */
-#include "sddf.h"
-#include "current_sense/sdfm/include/sddf_api.h"
-/* PRU SDDF FW image info */
-typedef struct PRUSDDF_PruFwImageInfo_s {
+#include "tisdfm_pruss_intc_mapping.h"  /* INTC configuration */
+#include "current_sense/sdfm/firmware/sdfm_bin.h"            /* SDFM image data */
+#include "sdfm.h"
+#include "current_sense/sdfm/include/sdfm_api.h"
+/* PRU SDFM FW image info */
+typedef struct PRUSDFM_PruFwImageInfo_s {
    const uint32_t *pPruImemImg;
    const uint32_t pruImemImgSz;
-} PRUSDDF_PruFwImageInfo;
+} PRUSDFM_PruFwImageInfo;

 /* Number of PRU images */
-#define PRU_SDDF_NUM_PRU_IMAGE  ( 3 )
+#define PRU_SDFM_NUM_PRU_IMAGE  ( 3 )

-/* PRU SDDF image info */
-static PRUSDDF_PruFwImageInfo gPruFwImageInfo[PRU_SDDF_NUM_PRU_IMAGE] =
+/* PRU SDFM image info */
+static PRUSDFM_PruFwImageInfo gPruFwImageInfo[PRU_SDFM_NUM_PRU_IMAGE] =
 {
-    {pru_SDDF_PRU0_image_0, sizeof(pru_SDDF_PRU0_image_0)}, /* PRU FW */
+    {pru_SDFM_PRU0_image_0, sizeof(pru_SDFM_PRU0_image_0)}, /* PRU FW */
    {NULL, 0}
 };

@ -82,7 +82,7 @@ int32_t initIcss(
    /* Open ICSS PRU instance */
    pruIcssHandle = PRUICSS_open(icssInstId);
    if (pruIcssHandle == NULL) {
-        return SDDF_ERR_INIT_ICSSG;
+        return SDFM_ERR_INIT_ICSSG;
    }

    /* Disable slice PRU cores */
@ -90,31 +90,31 @@ int32_t initIcss(
    {
        status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU0);
        if (status != SystemP_SUCCESS) {
-            return SDDF_ERR_INIT_ICSSG;
+            return SDFM_ERR_INIT_ICSSG;
        }
    }
    else if (sliceId == ICSSG_SLICE_ID_1)
    {
        status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU1);
        if (status != SystemP_SUCCESS) {
-            return SDDF_ERR_INIT_ICSSG;
+            return SDFM_ERR_INIT_ICSSG;
        }
    }
    else
    {
-        return SDDF_ERR_INIT_ICSSG;
+        return SDFM_ERR_INIT_ICSSG;
    }

    /* Reset slice memories */
    size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_IRAM_PRU(sliceId));
    if (size == 0)
    {
-        return SDDF_ERR_INIT_ICSSG;
+        return SDFM_ERR_INIT_ICSSG;
    }
    size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_DATARAM(sliceId));
    if (size == 0)
    {
-        return SDDF_ERR_INIT_ICSSG;
+        return SDFM_ERR_INIT_ICSSG;
    }

    /* Set ICSS pin mux */
@ -123,12 +123,12 @@ int32_t initIcss(
    /* Initialize ICSS INTC */
    status = PRUICSS_intcInit(pruIcssHandle, &gPruicssIntcInitdata);
    if (status != SystemP_SUCCESS) {
-        return SDDF_ERR_INIT_ICSSG;
+        return SDFM_ERR_INIT_ICSSG;
    }

    *pPruIcssHandle = pruIcssHandle;

-    return SDDF_ERR_NERR;
+    return SDFM_ERR_NERR;
 }
 void sdfm_configure_gpio_pin(sdfm_handle h_sdfm)
 {
@ -169,95 +169,99 @@ void sdfm_configure_gpio_pin(sdfm_handle h_sdfm)


 }
-/* Initialize SDDF PRU FW */
-int32_t init_sdfm_pru_fw(uint8_t pruId, SddfPrms *pSddfPrms, sdfm_handle *pHSddf)
+/* Initialize SDFM PRU FW */
+int32_t init_sdfm_pru_fw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm)
 {
-    sdfm_handle hSddf;
+    sdfm_handle hSdfm;

-    /* Initialize SDDF instance */
-    hSddf = SDFM_init(pruId);
-    if (hSddf == NULL)
+    /* Initialize SDFM instance */
+    hSdfm = SDFM_init(pruId);
+    if (hSdfm == NULL)
    {
-        return SDDF_ERR_INIT_SDDF;
+        return SDFM_ERR_INIT_SDFM;
    }

    uint8_t SDFM_CH;
-    hSddf->iep_clock = 300000000; //300MHz
-    hSddf->sdfm_clock = 20000000; //20MHz
-    hSddf->iep_inc = 1; // Default IEP increment 1
+    hSdfm->iep_clock = pSdfmPrms->iep_clock; 
+    hSdfm->sdfm_clock = pSdfmPrms->sd_clock; 
+    hSdfm->iep_inc = 1; /* Default IEP increment 1 */
+

-    uint8_t acc_osr = 13;
    uint8_t acc_filter = 0; //SINC3 filter
    uint8_t ecap_divider = 0x0F; //IEP at 300MHz: SD clock = 300/15=20Mhz

    /*configure IEP count for one epwm period*/
-    SDFM_configIepCount(hSddf, pSddfPrms->epwm_out_freq);
+    SDFM_configIepCount(hSdfm, pSdfmPrms->epwm_out_freq);

    /*configure ecap as PWM code for generate 20 MHz sdfm clock*/
-    SDFM_configEcap(hSddf, ecap_divider);
+    SDFM_configEcap(hSdfm, ecap_divider);

-     /*set comparator osr or OC osr*/
-    SDFM_setCompFilterOverSamplingRatio(hSddf, pSddfPrms->ComFilterOsr);
-
-    /*set OC sample count for NC  & NC OSR */
-    SDFM_setFilterOverSamplingRatio(hSddf, pSddfPrms->FilterOsr, pSddfPrms->ComFilterOsr);
+    /*set Noraml current OSR */
+    SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->FilterOsr);

    /*below configuration for all three channel*/
    for(SDFM_CH = 0; SDFM_CH < NUM_CH_SUPPORTED; SDFM_CH++)
    {
-        SDFM_setEnableChannel(hSddf, SDFM_CH);
+        SDFM_setEnableChannel(hSdfm, SDFM_CH);

-        SDFM_setAccOverSamplingRatio(hSddf, SDFM_CH, acc_osr);
+        /*set comparator osr or Over current osr*/
+        SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->ComFilterOsr);

        /*set ACC source or filter type*/
-        SDFM_configDataFilter(hSddf, SDFM_CH, acc_filter);
+        SDFM_configDataFilter(hSdfm, SDFM_CH, acc_filter);

        /*set clock inversion & clock source for all three channel*/
-        SDFM_selectClockSource(hSddf, SDFM_CH, pSddfPrms->clkPrms[SDFM_CH]);
+        SDFM_selectClockSource(hSdfm, SDFM_CH, pSdfmPrms->clkPrms[SDFM_CH]);

        /*set threshold values */
-        SDFM_setCompFilterThresholds(hSddf, SDFM_CH, pSddfPrms->threshold_parms[SDFM_CH]);
-
-
-
-        if(pSddfPrms->en_com)
+        SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->threshold_parms[SDFM_CH]);
+        
+        if(pSdfmPrms->en_com)
        {
-            SDFM_enableComparator(hSddf, SDFM_CH);
+            SDFM_enableComparator(hSdfm, SDFM_CH);       
        }
        else
        {
-            SDFM_disableComparator(hSddf, SDFM_CH);
+            SDFM_disableComparator(hSdfm, SDFM_CH);
        }

    }

    /*GPIO pin configuration for threshold measurment*/
-    sdfm_configure_gpio_pin(hSddf);
+    sdfm_configure_gpio_pin(hSdfm);

-    SDFM_setSampleReadingTime(hSddf, pSddfPrms->trigSampTime);
+    SDFM_setSampleTriggerTime(hSdfm, pSdfmPrms->firstSampTrigTime);
+    if(pSdfmPrms->en_second_update)
+    {
+        SDFM_enableDoubleSampling(hSdfm, pSdfmPrms->secondSampTrigTime);
+    }
+    else
+    {
+        SDFM_disableDoubleSampling(hSdfm);
+    }

-    /* Enable (global) SDDF */
-    SDFM_enable(hSddf);
+    /* Enable (global) SDFM */
+    SDFM_enable(hSdfm);

-    pHSddf = &hSddf;
+    pHSdfm = &hSdfm;

- return SDDF_ERR_NERR;
+ return SDFM_ERR_NERR;
 }

 /*
- *  ======== initPruSddf ========
+ *  ======== initPruSdfm ========
 */
-/* Initialize PRU core for SDDF */
-int32_t initPruSddf(
+/* Initialize PRU core for SDFM */
+int32_t initPruSdfm(
    PRUICSS_Handle pruIcssHandle,
    uint8_t pruInstId,
-    SddfPrms *pSddfPrms,
-    sdfm_handle *pHSddf
+    SdfmPrms *pSdfmPrms,
+    sdfm_handle *pHSdfm
 )
 {
    uint8_t sliceId;
    uint32_t pruIMem;
-    PRUSDDF_PruFwImageInfo *pPruFwImageInfo;
+    PRUSDFM_PruFwImageInfo *pPruFwImageInfo;
    int32_t size;
    const uint32_t *sourceMem;          /* Source memory[ Array of uint32_t ] */
    uint32_t imemOffset;    /* Offset at which write will happen */
@ -268,7 +272,7 @@ int32_t initPruSddf(
    /* Reset PRU */
    status = PRUICSS_resetCore(pruIcssHandle, pruInstId);
    if (status != SystemP_SUCCESS) {
-        return SDDF_ERR_INIT_PRU_SDDF;
+        return SDFM_ERR_INIT_PRU_SDFM;
    }

    /* Calculate slice ID */
@ -299,7 +303,7 @@ int32_t initPruSddf(
    if ((pPruFwImageInfo == NULL) ||
        (pPruFwImageInfo->pPruImemImg == NULL))
    {
-        return SDDF_ERR_INIT_PRU_SDDF;
+        return SDFM_ERR_INIT_PRU_SDFM;
    }

    /* Write IMEM */
@ -309,15 +313,15 @@ int32_t initPruSddf(
    size = PRUICSS_writeMemory(pruIcssHandle, pruIMem, imemOffset, sourceMem, byteLen);
    if (size == 0)
    {
-        return SDDF_ERR_INIT_PRU_SDDF;
+        return SDFM_ERR_INIT_PRU_SDFM;
    }

    /* Enable PRU */
    status = PRUICSS_enableCore(pruIcssHandle, pruInstId);
    if (status != SystemP_SUCCESS) {
-        return SDDF_ERR_INIT_PRU_SDDF;
+        return SDFM_ERR_INIT_PRU_SDFM;
    }
-/* Translate PRU ID to SDDF API */
+/* Translate PRU ID to SDFM API */
    if (pruInstId == PRUICSS_PRU0) {
        pruId = PRU_ID_0;
    }
@ -325,15 +329,15 @@ int32_t initPruSddf(
        pruId = PRU_ID_1;
    }
    else {
-        return SDDF_ERR_INIT_PRU_SDDF;
+        return SDFM_ERR_INIT_PRU_SDFM;
    }

-    /* Initialize SDDF PRU FW */
-    status = init_sdfm_pru_fw(pruId, pSddfPrms, pHSddf);
-    if (status != SDDF_ERR_NERR) {
-        return SDDF_ERR_INIT_PRU_SDDF;
+    /* Initialize SDFM PRU FW */
+    status = init_sdfm_pru_fw(pruId, pSdfmPrms, pHSdfm);
+    if (status != SDFM_ERR_NERR) {
+        return SDFM_ERR_INIT_PRU_SDFM;
    }
-    return SDDF_ERR_NERR;
+    return SDFM_ERR_NERR;

 }

--- a/examples/current_sense/icss_sdfm/sdfm.h
+++ b/examples/current_sense/icss_sdfm/sdfm.h
@ -30,34 +30,34 @@
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

-#ifndef _SDDF_H_
-#define _SDDF_H_
+#ifndef _SDFM_H_
+#define _SDFM_H_

 #include <stdint.h>
 #include <drivers/pruicss.h>
-#include "current_sense/sdfm/include/sddf_api.h"
+#include "current_sense/sdfm/include/sdfm_api.h"

 /* Status codes */
-#define SDDF_ERR_NERR               (  0 )  /* no error */
-#define SDDF_ERR_CFG_PIN_MUX        ( -1 )  /* pin mux configuration error */
-#define SDDF_ERR_CFG_ICSSG_CLKCFG   ( -2 )  /* ICSSG clock configuration error */
-#define SDDF_ERR_INIT_ICSSG         ( -3 )  /* initialize ICSSG error */
-#define SDDF_ERR_CFG_MCU_INTR       ( -4 )  /* interrupt configuration error */
-#define SDDF_ERR_INIT_PRU_SDDF      ( -5 )  /* initialize PRU for SDDF error */
-#define SDDF_ERR_INIT_SDDF          ( -6 )  /* initialize SDDF error */
+#define SDFM_ERR_NERR               (  0 )  /* no error */
+#define SDFM_ERR_CFG_PIN_MUX        ( -1 )  /* pin mux configuration error */
+#define SDFM_ERR_CFG_ICSSG_CLKCFG   ( -2 )  /* ICSSG clock configuration error */
+#define SDFM_ERR_INIT_ICSSG         ( -3 )  /* initialize ICSSG error */
+#define SDFM_ERR_CFG_MCU_INTR       ( -4 )  /* interrupt configuration error */
+#define SDFM_ERR_INIT_PRU_SDFM      ( -5 )  /* initialize PRU for SDFM error */
+#define SDFM_ERR_INIT_SDFM          ( -6 )  /* initialize SDFM error */

-/* Bit for SDDF configuration mask */
-#define SDDF_CFG_CLK                    ( 1<<0 )
-#define SDDF_CFG_OSR                    ( 1<<1 )
-#define SDDF_CFG_TRIG_SAMP_TIME         ( 1<<2 )
-#define SDDF_CFG_TRIG_SAMP_CNT          ( 1<<3 )
-#define SDDF_CFG_CH_EN                  ( 1<<4 )
-#define SDDF_CFG_FD                     ( 1<<5 )
-#define SDDF_CFG_TRIG_OUT_SAMP_BUF      ( 1<<6 )
+/* Bit for SDFM configuration mask */
+#define SDFM_CFG_CLK                    ( 1<<0 )
+#define SDFM_CFG_OSR                    ( 1<<1 )
+#define SDFM_CFG_TRIG_SAMP_TIME         ( 1<<2 )
+#define SDFM_CFG_TRIG_SAMP_CNT          ( 1<<3 )
+#define SDFM_CFG_CH_EN                  ( 1<<4 )
+#define SDFM_CFG_FD                     ( 1<<5 )
+#define SDFM_CFG_TRIG_OUT_SAMP_BUF      ( 1<<6 )

-/* SDDF mode */
-#define SDDF_MODE_TRIG                  ( 0 )
-#define SDDF_MODE_CONT                  ( 1 )
+/* SDFM mode */
+#define SDFM_MODE_TRIG                  ( 0 )
+#define SDFM_MODE_CONT                  ( 1 )

 /* ICSSG Core clock source selection options */
 #define CORE_CLK_SEL_ICSSGn_CORE_CLK    ( 0 )   /* Mux Output */
@ -121,16 +121,31 @@ typedef enum PRUICSS_MaxInstances_s
   PRUICSS_INSTANCE_MAX=2
 } PRUICSS_MaxInstances;

-/* SDDF configuration parameters */
-typedef struct SddfPrms_s {
-    float trigSampTime;
+/* SDFM configuration parameters */
+typedef struct SdfmPrms_s {
+    /**< IEP clock value */
+    uint32_t iep_clock;
+    /**< Sigma delta input clock value  */
+    uint32_t sd_clock;
+    /**< double update enable field  */
+    uint8_t en_second_update;
+    /**< First normal current sample trigger time  */
+    float firstSampTrigTime;
+    /**< First normal current sample trigger time  */
+    float secondSampTrigTime;
+    /**< output freq. of EPWM0  */
    uint32_t epwm_out_freq;
+    /**< Over current threshold parameters  */
    SDFM_ThresholdParms   threshold_parms[NUM_CH_SUPPORTED];
+    /**< SD clock source and clock inversion  */
    SDFM_ClkSourceParms   clkPrms[3];
+    /**< Over current OSR  */
    uint16_t ComFilterOsr;
+    /**< Normal current OSR  */
    uint16_t FilterOsr;
+    /**< over current enable field */
    uint8_t en_com;
-} SddfPrms;
+} SdfmPrms;


 /* Initialize ICSSG */
@ -141,13 +156,13 @@ int32_t initIcss(
    PRUICSS_Handle *pPruIcssHandle
 );

-/* Initialize PRU core for SDDF */
-int32_t initPruSddf(
+/* Initialize PRU core for SDFM */
+int32_t initPruSdfm(
    PRUICSS_Handle pruIcssHandle,
    uint8_t pruInstId,
-    SddfPrms *pSddfPrms,
-    sdfm_handle *pHSddf
+    SdfmPrms *pSdfmPrms,
+    sdfm_handle *pHSdfm
 );


-#endif /* _SDDF_H_ */
+#endif /* _SDFM_H_ */
--- a/examples/current_sense/icss_sdfm/tisdfm_pruss_intc_mapping.h
+++ b/examples/current_sense/icss_sdfm/tisdfm_pruss_intc_mapping.h
--- a/makefile.am243x
+++ b/makefile.am243x
@ -58,6 +58,7 @@ help:
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
+	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
@ -183,6 +184,7 @@ BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0
 BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang
+BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang
 # Various System Example Targets

 BUILD_COMBO_EXAMPLE_PRIVATE_ALL =
@ -243,6 +245,9 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
 icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all

+ icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang:
+	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all
+
 sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt:
 	$(MAKE) -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile all

@ -300,6 +305,7 @@ BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 # Various System Example Clean Targets

 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL =
@ -360,6 +366,9 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
 icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean

+ icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean
+
 sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile clean

@ -417,6 +426,7 @@ BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
+BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
 # Various System Example Scrub Targets

 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL =
@ -477,6 +487,9 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
 icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub

+ icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub:
+	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
+
 sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_scrub:
 	$(MAKE) -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile scrub

--- a/makefile_projectspec.am243x
+++ b/makefile_projectspec.am243x
@ -19,6 +19,7 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_multi_channel_a
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
 # Various System Example Projectspec Build Targets

 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL =
@ -79,6 +80,9 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
 icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all

+ icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build:
+	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
+
 sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_build:
 	$(MAKE) -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec all

@ -137,6 +141,7 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_multi_channel_a
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 # Various System Example Projectspec Clean Targets

 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL =
@ -197,6 +202,9 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
 icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean

+ icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
+
 sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec clean

@ -255,6 +263,7 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_multi_channel_
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
 # Various System Example Projectspec Export Targets

 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL =
@ -315,6 +324,9 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
 icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export

+ icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export:
+	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
+
 sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_export:
 	$(MAKE) -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec export

@ -398,6 +410,7 @@ help:
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
+	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/endat/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
--- a/source/current_sense/sdfm/driver/sdfm_drv.c
+++ b/source/current_sense/sdfm/driver/sdfm_drv.c
@ -34,8 +34,8 @@
 #include <drivers/hw_include/tistdtypes.h>
 #include <drivers/hw_include/hw_types.h>
 #include <current_sense/sdfm/include/sdfm_drv.h>
-#include <current_sense/sdfm/include/sddf_api.h>
-#include <current_sense/sdfm/firmware/icssg_sddf.h>
+#include <current_sense/sdfm/include/sdfm_api.h>
+#include <current_sense/sdfm/firmware/icssg_sdfm.h>
 #include <drivers/hw_include/am64x_am243x/cslr_soc_baseaddress.h>
 #include <drivers/soc.h>
 #include <drivers/gpio.h>
@ -122,11 +122,9 @@ SDFM g_sdfm[NUM_PRU] = {
 sdfm_handle SDFM_init(uint8_t pru_id)
 {
    SDFM *p_sdfm;
-    uint8_t ctrl;
-    uint8_t stat;
-    uint8_t pru_id_ack;

-    if (pru_id == PRU_ID_0) {
+    if (pru_id == PRU_ID_0)
+    {
        /* Initialize PRU 0 SD */

        p_sdfm = &g_sdfm[pru_id];
@ -135,38 +133,22 @@ sdfm_handle SDFM_init(uint8_t pru_id)
        p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + 0x0);

        /* Set FW PRU ID */
-        ctrl = p_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl;
-        ctrl &= ~SDDF_CTRL_BF_PRU_ID_MASK;
-        ctrl |= pru_id << SDDF_CTRL_BF_PRU_ID_SHIFT;
-        p_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl = ctrl;
-
-        /* Wait for FW PRU ID ACK */
-        do {
-            stat = p_sdfm->p_sdfm_interface->sdfm_ctrl.stat;
-            pru_id_ack = (stat & SDDF_STAT_BF_PRU_ID_ACK_MASK) >> SDDF_STAT_BF_PRU_ID_ACK_SHIFT;
-        } while (pru_id_ack != pru_id);
+        p_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_pru_id = pru_id;
    }
-    else if (pru_id == PRU_ID_1) {
+    else if (pru_id == PRU_ID_1)
+    {
        /* Initialize PRU 1 SD */

        p_sdfm = &g_sdfm[pru_id];

        /* Initialize SDFM control address */
-        p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM1_SLV_RAM + 0x0);
+        p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + 0x0);

        /* Set FW PRU ID */
-        ctrl = p_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl;
-        ctrl &= ~SDDF_CTRL_BF_PRU_ID_MASK;
-        ctrl |= pru_id << SDDF_CTRL_BF_PRU_ID_SHIFT;
-        p_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl = ctrl;
-
-        /* Wait for FW PRU ID ACK */
-        do {
-            stat = p_sdfm->p_sdfm_interface->sdfm_ctrl.stat;
-            pru_id_ack = (stat & SDDF_STAT_BF_PRU_ID_ACK_MASK) >> SDDF_STAT_BF_PRU_ID_ACK_SHIFT;
-        } while (pru_id_ack != pru_id);
+        p_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_pru_id = pru_id;
    }
-    else {
+    else
+    {
        p_sdfm = NULL;
    }

@ -199,28 +181,47 @@ void SDFM_configEcap(sdfm_handle h_sdfm, uint8_t ecap_divider)
 }

 /*sdfm Hw osr configuration */
- void SDFM_setAccOverSamplingRatio(sdfm_handle h_sdfm, uint8_t ch_id, uint8_t osr)
+ void SDFM_setCompFilterOverSamplingRatio(sdfm_handle h_sdfm, uint8_t ch_id, uint16_t osr)
 {
-    /*SD Hw OSR*/
+    /*Over current OSR*/
    h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].osr = osr;
 }

 /*sdfm high, low  threshold config */
 void SDFM_setCompFilterThresholds(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_ThresholdParms thresholdParms)
 {
-   /* SD OC high threshold = (OC OSR)^(OC SINC ORDER) = 14^3 = 2744*/
+   /* SD Over current high threshold = (Over current OSR)^(Over current SINC ORDER) = 14^3 = 2744*/
    h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_threshold_parms.high_threshold = thresholdParms.high_threshold;
-    /* SD OC low threshold */
+    /* SD Over current low threshold */
    h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_threshold_parms.low_threshold = thresholdParms.low_threshold;

 }

 /*sdfm smapling time configuation */
-void SDFM_setSampleReadingTime(sdfm_handle h_sdfm, float trig_samp_time)
+void SDFM_setSampleTriggerTime(sdfm_handle h_sdfm, float samp_trig_time)
 {   /*convert sample time into IEP count*/
    /*samp time in us */
-    int32_t count = (h_sdfm->iep_clock /1000000)*((float)trig_samp_time);
-    h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.trig_samp_time = count;
+    int32_t count = (h_sdfm->iep_clock /1000000)*((float)samp_trig_time);
+    h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.first_samp_trig_time = count;
+
+
+
+}
+/*Second normal current sampling configuration*/
+void SDFM_enableDoubleSampling(sdfm_handle h_sdfm, float samp_trig_time)
+{
+    /*Enable double normal current sampling*/
+    h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.en_double_nc_sampling = 1;
+    /*Second sample point*/
+    int32_t count = (h_sdfm->iep_clock /1000000)*((float)samp_trig_time);
+    h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.second_samp_trig_time = count;
+}
+
+/*Disable Double update*/
+void SDFM_disableDoubleSampling(sdfm_handle h_sdfm)
+{
+    /*Enable double normal current sampling*/
+    h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.en_double_nc_sampling = 0;
 }
 /* Enable the channel specified by the channel number parameter*/
 void SDFM_setEnableChannel(sdfm_handle h_sdfm, uint8_t channel_number)
@ -228,17 +229,17 @@ void SDFM_setEnableChannel(sdfm_handle h_sdfm, uint8_t channel_number)

    if(channel_number == 0)
    {
-        h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number << SDDF_CFG_BF_SD_CH0_ID_SHIFT);
+        h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number << SDFM_CFG_BF_SD_CH0_ID_SHIFT);
        h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[channel_number].ch_id = channel_number;
    }
    else if(channel_number == 1)
    {
-        h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number<< SDDF_CFG_BF_SD_CH1_ID_SHIFT);
+        h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number<< SDFM_CFG_BF_SD_CH1_ID_SHIFT);
        h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[channel_number].ch_id = channel_number;
    }
    else
    {
-        h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number << SDDF_CFG_BF_SD_CH2_ID_SHIFT);
+        h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number << SDFM_CFG_BF_SD_CH2_ID_SHIFT);
        h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[channel_number].ch_id = channel_number;
    }
 }
@ -258,7 +259,8 @@ void SDFM_selectClockSource(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_ClkSourcePar
 /* Enable the comparator feature for a specified filter/channel */
 void SDFM_enableComparator(sdfm_handle h_sdfm, uint8_t ch)
 {
-    h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.enable_comparator |= (1 << ch);
+    /*It is setting bits for enable Over current: 0th bit for Over current enable & from 1st bits to 3rd bits are for ch0 to ch2.*/
+    h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.enable_comparator |= ((1 << (ch+1))|(1));
 }

 /* Disable the comparator feature for a specified filter/channel */
@ -288,55 +290,30 @@ uint32_t SDFM_getFilterData(uint8_t ch)
    p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + 0x0);
    return p_sdfm->p_sdfm_interface->curr_out_samp_buf[ch];
 }
-/*Configure Over current OSR*/
-void SDFM_setCompFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t osr)
+
+/*Configure normal current OSR for data filter*/
+void SDFM_setFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t nc_osr)
 {
-    /*; IEP0 counts in OC sampling period:
-    ;   - IEP0 count =
-    ;       (NC OSR * SD clock period)*(IEP0 frequency * IEP default count) =
-    ;       (NC OSR * IEP0 frequency * IEP default count)/(SD clock frequency) =
-    ;       64*300e6*1/20e6 = 960*/
-   //IEP freq. 300MHz //SDFM clock 20MHz
-    // IEP Count = (OSR *(1/SD clock))*(IEP freq.)
+    
+    /*IEP0 counts in normal current sampling period*/
    uint16_t count;
    uint32_t iep_freq = h_sdfm->iep_clock;
    uint32_t sd_clock = h_sdfm->sdfm_clock;
-    count = (osr*(iep_freq/sd_clock));
-    h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.oc_prd_iep_cnt = count;
-
-}
-
-/*Configure normal current OSR*/
-void SDFM_setFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t nc_osr, uint16_t oc_osr)
-{
-    /*OC sample count for NC sampling */
-    uint16_t count;
-    count  = (nc_osr/oc_osr);
-    h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.sample_count = count;
-
-    /*IEP0 counts in NC sampling period*/
-    uint32_t iep_freq = h_sdfm->iep_clock;
-    uint32_t sd_clock = h_sdfm->sdfm_clock;
-    count = (nc_osr*(iep_freq/sd_clock));
+    count = (int)((float)nc_osr*((float)iep_freq/(float)sd_clock));
    h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.nc_prd_iep_cnt = count;
 }
 /* SDFM global enable */
 void SDFM_enable(sdfm_handle h_sdfm)
 {
-    uint8_t sdfm_ctrl;
-    uint8_t sdfm_stat;
    uint8_t sdfm_en_ack;

-    sdfm_ctrl = h_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl;
-    sdfm_ctrl &= ~SDDF_CTRL_BF_SDDF_EN_MASK;
-    sdfm_ctrl |= BF_SDDF_EN_ENABLE << SDDF_CTRL_BF_SDDF_EN_SHIFT;
-    h_sdfm->p_sdfm_interface->sdfm_ctrl.ctrl = sdfm_ctrl;
+    /*Enable SDFM */
+    h_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_en = 1;

    /* wait for ACK */
    do {
-        sdfm_stat = h_sdfm->p_sdfm_interface->sdfm_ctrl.stat;
-        sdfm_en_ack = (sdfm_stat & SDDF_STAT_BF_SDDF_EN_ACK_MASK) >> SDDF_STAT_BF_SDDF_EN_ACK_SHIFT;
-    } while (sdfm_en_ack != BF_SDDF_EN_ENABLE);
+        sdfm_en_ack = h_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_en_ack;
+    } while (sdfm_en_ack != BF_SDFM_EN_ENABLE);


 }
--- a/source/current_sense/sdfm/firmware/.project/project_am243x.js
+++ b/source/current_sense/sdfm/firmware/.project/project_am243x.js
@ -4,7 +4,7 @@ let device = "am243x";

 const files = {
    common: [
-        "sddf.asm",
+        "sdfm.asm",
        "icssg_pru.cmd",
    ],
 };
@ -27,7 +27,7 @@ const readmeDoxygenPageTag = "SDFM_DESIGN";
 const cflags_pru = {
    common: [
        "-v4",
-        "-DSDDF_PRU_CORE",
+        "-DSDFM_PRU_CORE",
        "-o2",
        "--display_error_number",
        "--hardware_mac=on",
@ -37,9 +37,9 @@ const cflags_pru = {
 const lflags_pru = {
    common: [
        "--disable_auto_rts",
-        "--define=SDDF_PRU_CORE=1",
+        "--define=SDFM_PRU_CORE=1",
        "--warn_sections",
-        "--entry_point=SDDF_ENTRY",
+        "--entry_point=SDFM_ENTRY",
        "--zero_init=off",
    ],
 };
@ -53,7 +53,7 @@ const buildOptionCombos = [


 let postBuildStepsPru = [
-   "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDDF_PRU0_image -o sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h;"
+   "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDFM_PRU0_image -o sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h;"
 ];


--- a/source/current_sense/sdfm/firmware/.project/project_am64x.js
+++ b/source/current_sense/sdfm/firmware/.project/project_am64x.js
@ -4,7 +4,7 @@ let device = "am64x";

 const files = {
    common: [
-        "sddf.asm",
+        "sdfm.asm",
        "icssg_pru.cmd",
    ],
 };
@ -27,7 +27,7 @@ const readmeDoxygenPageTag = "SDFM_DESIGN";
 const cflags_pru = {
    common: [
        "-v4",
-        "-DSDDF_PRU_CORE",
+        "-DSDFM_PRU_CORE",
        "-o2",
        "--display_error_number",
        "--hardware_mac=on",
@ -37,9 +37,9 @@ const cflags_pru = {
 const lflags_pru = {
    common: [
        "--disable_auto_rts",
-        "--define=SDDF_PRU_CORE=1",
+        "--define=SDFM_PRU_CORE=1",
        "--warn_sections",
-        "--entry_point=SDDF_ENTRY",
+        "--entry_point=SDFM_ENTRY",
        "--zero_init=off",
    ],
 };
@ -53,7 +53,7 @@ const buildOptionCombos = [


 let postBuildStepsPru = [
-   "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDDF_PRU0_image -o sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h;"
+   "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDFM_PRU0_image -o sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h;"
 ];


--- a/source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/example.projectspec
+++ b/source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/example.projectspec
@ -38,7 +38,7 @@
            -DSLICE0
            -v4
            -v4
-            -DSDDF_PRU_CORE
+            -DSDFM_PRU_CORE
            -o2
            --display_error_number
            --hardware_mac=on
@ -49,14 +49,14 @@
            -m=sdfm_firmware.${ConfigName}.map
            -llibc.a
            --disable_auto_rts
-            --define=SDDF_PRU_CORE=1
+            --define=SDFM_PRU_CORE=1
            --warn_sections
-            --entry_point=SDDF_ENTRY
+            --entry_point=SDFM_ENTRY
            --zero_init=off
        "

        postBuildStep="
-            $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDDF_PRU0_image -o sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h;
+            $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDFM_PRU0_image -o sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h;
        "

        description="A Sdfm Firmware FW project">
@ -76,7 +76,7 @@
            "
        ></configuration>
        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
-        <file path="../../../sddf.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        <file path="../../../sdfm.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
        <file path="../../../icssg_pru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
--- a/source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile
+++ b/source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile
@ -56,7 +56,7 @@ ASM_SRCS__QUOTED += \
 main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDDF_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM243X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${CG_TOOL_ROOT}/include" --include_path="${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
+	"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDFM_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM243X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${CG_TOOL_ROOT}/include" --include_path="${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '

@ -86,7 +86,7 @@ all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
 sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDDF_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM243X  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
+	"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDFM_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM243X  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build
@ -108,7 +108,7 @@ clean:
 	-@echo ' '

 post-build:
-	-$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDDF_PRU0_image -o sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h
+	-$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDFM_PRU0_image -o sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am243x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h
 	-@echo ' '

 .PHONY: all clean dependents
--- a/source/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt/example.projectspec
+++ b/source/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt/example.projectspec
@ -38,7 +38,7 @@
            -DSLICE0
            -v4
            -v4
-            -DSDDF_PRU_CORE
+            -DSDFM_PRU_CORE
            -o2
            --display_error_number
            --hardware_mac=on
@ -49,14 +49,14 @@
            -m=sdfm_firmware.${ConfigName}.map
            -llibc.a
            --disable_auto_rts
-            --define=SDDF_PRU_CORE=1
+            --define=SDFM_PRU_CORE=1
            --warn_sections
-            --entry_point=SDDF_ENTRY
+            --entry_point=SDFM_ENTRY
            --zero_init=off
        "

        postBuildStep="
-            $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDDF_PRU0_image -o sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h;
+            $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDFM_PRU0_image -o sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h;
        "

        description="A Sdfm Firmware FW project">
@ -76,7 +76,7 @@
            "
        ></configuration>
        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
-        <file path="../../../sddf.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        <file path="../../../sdfm.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
        <file path="../../../icssg_pru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
--- a/source/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile
+++ b/source/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt/makefile
@ -56,7 +56,7 @@ ASM_SRCS__QUOTED += \
 main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDDF_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM64X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${CG_TOOL_ROOT}/include" --include_path="${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
+	"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDFM_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM64X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${CG_TOOL_ROOT}/include" --include_path="${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '

@ -86,7 +86,7 @@ all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
 sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDDF_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM64X  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
+	"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU0 -DSLICE0 -v4 -v4 -DSDFM_PRU_CORE -o2 --display_error_number --hardware_mac=on --define=SOC_AM64X  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build
@ -108,7 +108,7 @@ clean:
 	-@echo ' '

 post-build:
-	-$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDDF_PRU0_image -o sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h
+	-$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=pru_SDFM_PRU0_image -o sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.out;  move sdfm_firmware_am64x-evm_icssg0-pru0_fw_ti-pru-cgt.h ${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/firmware/sdfm_bin.h
 	-@echo ' '

 .PHONY: all clean dependents
--- a/source/current_sense/sdfm/firmware/fw_regs.asm
+++ b/source/current_sense/sdfm/firmware/fw_regs.asm
@ -1,103 +0,0 @@
-;
-; Copyright (c) 2023, Texas Instruments Incorporated
-; All rights reserved.
-;
-;  Redistribution and use in source and binary forms, with or without
-;  modification, are permitted provided that the following conditions
-;  are met:
-;
-;  *  Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;
-;  *  Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;
-;  *  Neither the name of Texas Instruments Incorporated nor the names of
-;     its contributors may be used to endorse or promote products derived
-;     from this software without specific prior written permission.
-;
-;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-;  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-;  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-;  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-;  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-;  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-;  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-;  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-;  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-;  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-
-        .cdecls C,NOLIST
-%{
-        #include "icssg_sddf.h"
-%}
-        .include "sddf_cfg.h"
-
-
-; Initial FW register values
-; SDDF_EN=0, PRU_ID=uninitialized
-INIT_SDDF_CTRL                  .set    (SDDF_EN << SDDF_CTRL_BF_SDDF_EN_SHIFT) | (PRU_ID << SDDF_CTRL_BF_PRU_ID_SHIFT)
-; SDDF_EN_ACK=0, PRU_ID_ACK=uninitialized
-INIT_SDDF_STAT                  .set    (SDDF_EN_ACK << SDDF_STAT_BF_SDDF_EN_ACK_SHIFT) | (PRU_ID_ACK << SDDF_STAT_BF_PRU_ID_ACK_SHIFT)
-; IEP0 default increment=1
-INIT_IEP_CFG                    .set    (IEP_DEFAULT_INC << IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT)
-; IEP0 CMP0 count to simulate EPWM (FOC loop) period:
-;   - IEP frequency = 300 MHz
-;   - IEP Default Increment = 1
-;   - Simulated EPWM frequency = 8e3
-; CMP0 = 300e6/1/8e3 = 37500 = 0x927C
-; CMP3 = 300e6/16e3  = 18,750 = 0x493E
-INIT_IEP_CFG_CMP0_CNT_EPWM_PRD  .set    (CMP0_CNT_EPWM_PRD << IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT)
-; SD Ch0 ID=0, Ch1 ID=1, Ch2 ID=2
-INIT_SDDF_CFG_SD_CH_ID          .set    (SD_CH0_ID << SDDF_CFG_BF_SD_CH0_ID_SHIFT) | (SD_CH1_ID << SDDF_CFG_BF_SD_CH1_ID_SHIFT) | (SD_CH2_ID << SDDF_CFG_BF_SD_CH2_ID_SHIFT)
-; SD_PRD_CLOCKS=10 => 20 MHz SD clock, SD_CLK_INV==0 => No clock inversion
-INIT_SDDF_CFG_SD_CLK            .set    (SD_PRD_CLOCKS << SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT) | (SD_CLK_INV << SDDF_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT)
-; SD OC OSR=(13+1)=14
-INIT_SDDF_CFG_OSR               .set    (OC_OSR << SDDF_CFG_OC_OSR_BF_OSR_SHIFT)
-; SD OC positive threshold = (OC OSR)^(OC SINC ORDER) = 14^3 = 2744
-INIT_SDDF_CFG_OC_POS_THR        .set    (OC_POS_THR << SDDF_CFG_OC_POS_THR_SHIFT)
-; SD OC negative threshold = 1
-INIT_SDDF_CFG_OC_NEG_THR        .set    (OC_NEG_THR << SDDF_CFG_OC_NEG_THR_SHIFT)
-; For SD samp freq==20e6, OSR==64, EPWM (FOC) loop freq = 8e3, sddf_setup_time=0 (TBD) &
-; IEP freq = 300e6, IEP counter increment=1:
-;   (1/2*(1/8e3) - 3/2*(64/20e6) - 0)*300e6*1 = 17310
-;   ()
-;
-;for 16KHz  (1/2*(1/16e3)-3/2*(64/20e6)-0)*300e6 = 7935
-;for
-INIT_SDDF_CFG_TRIG_SAMP_TIME    .set    (TRIG_SAMP_TIME << SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT)
-; Generate 3 NC samples after trigger
-INIT_SDDF_CFG_TRIG_SAMP_CNT     .set    (TRIG_SAMP_CNT << SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT)
-; IEP0 counts in NC sampling period:
-;   - IEP0 count =
-;       (NC OSR * SD clock period)*(IEP0 frequency * IEP default count) =
-;       (NC OSR * IEP0 frequency * IEP default count)/(SD clock frequency) =
-;       64*300e6*1/20e6 = 960
-; for NC OSR = 128
-; 128*15 = 1920
-; 256*15 = 3840
-INIT_SDDF_CFG_NC_PRD_IEP_CNT    .set    (NC_PRD_IEP_CNT << SDDF_CFG_NC_PRD_IEP_CNT_SHIFT)
-INIT_SDDF_CFG_OUT_SAMP_BUF      .set    (NC_OUT_SAMP_BUF << SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT)
-
-                                ; SDDF Firmware Registers
-                                .sect   ".fwRegs"
-                                .retain ".fwRegs"
-                                .retainrefs ".fwRegs"
-                                .byte   INIT_SDDF_CTRL
-                                .byte   INIT_SDDF_STAT
-                                .byte   INIT_IEP_CFG
-                                .byte   0   ; RESERVED
-                                .word   INIT_IEP_CFG_CMP0_CNT_EPWM_PRD
-                                .word   INIT_SDDF_CFG_SD_CH_ID
-                                .short  INIT_SDDF_CFG_SD_CLK
-                                .byte   INIT_SDDF_CFG_OSR
-                                .byte   0   ; RESERVED
-                                .short  INIT_SDDF_CFG_OC_POS_THR
-                                .short  INIT_SDDF_CFG_OC_NEG_THR
-                                .word   INIT_SDDF_CFG_TRIG_SAMP_TIME
-                                .short  INIT_SDDF_CFG_TRIG_SAMP_CNT
-                                .short  INIT_SDDF_CFG_NC_PRD_IEP_CNT
-                                .word   INIT_SDDF_CFG_OUT_SAMP_BUF
--- a/source/current_sense/sdfm/firmware/icssg_pru.cmd
+++ b/source/current_sense/sdfm/firmware/icssg_pru.cmd
@ -21,7 +21,7 @@ MEMORY
    /* RAM */
    PRU_FWREGS          : org = 0x00000000 len = 0x00000080
    RTU_FWREGS          : org = 0x00000080 len = 0x00000080
-    PRU_DMEM_0_1_LOW    : org = 0x00000100 len = 0x00000F00         /* 4kB ICSSG Data RAM 0_1 for PRU*/
+    PRU_DMEM_0_1_LOW    : org = 0x00000200 len = 0x00000E00         /* 4kB ICSSG Data RAM 0_1 for PRU*/
    PRU_DMEM_0_1_HIGH   : org = 0x00001000 len = 0x00001000         /* 4kB ICSSG Data RAM 0_1 for RTU*/
    PRU_DMEM_1_0        : org = 0x00002000 len = 0x00002000         /* 8kB ICSSG Data RAM 1_0 */

@ -80,7 +80,7 @@ SECTIONS {
    /* .fardata    >  PRU_DMEM_0_1_LOW, PAGE 1 */

    .text           >  PRU_IMEM, PAGE 0
-#if defined (SDDF_PRU_CORE)
+#if defined (SDFM_PRU_CORE)
    .fwRegs         >  PRU_FWREGS, PAGE 1
    .data           >  PRU_DMEM_0_1_LOW, PAGE 1
    .outSamps       >  PRU_DMEM_0_1_LOW, PAGE 1
--- a/source/current_sense/sdfm/firmware/icssg_sddf.h
+++ b/source/current_sense/sdfm/firmware/icssg_sddf.h
@ -1,341 +0,0 @@
-/*
- * Copyright (c) 2023, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * *  Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * *  Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * *  Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ICSS_SDDF_H_
-#define _ICSS_SDDF_H_
-
-/* Number of SDDF channels per PRU */
-#define ICSSG_NUM_SD_CH         ( 9 )
-/* Number of SDDF channels supported by PRU FW */
-#define ICSSG_NUM_SD_CH_FW      ( 3 )
-
-/* ICSSG INTC events */
-/* Compile-time Host event for SDDF samples available.
-   Ideally Host would provide this to FW via pseudo-register in DMEM. */
-#define PRU_TRIGGER_HOST_SDDF_EVT   ( 2+16 )    /* pr0_pru_mst_intr[2]_intr_req */
-#define RTU_TRIGGER_HOST_SDDF_EVT   ( 3+16 )    /* pr0_pru_mst_intr[3]_intr_req */
-
-
-/*
-    Firmware registers
-*/
-
-/* FW register base addresses */
-#define PRU_ICSSG_SDDF_CTRL_BASE                    ( 0x0000 )
-#define PRU_ICSSG_SDDF_CFG_BASE                     ( 0x0002 )
-#define RTU_ICSSG_SDDF_CTRL_BASE                    ( 0x0080 )
-#define RTU_ICSSG_SDDF_CFG_BASE                     ( 0x0082 )
-
-#if defined (SDDF_PRU_CORE)
-/* SDDF Control */
-#define ICSSG_SDDF_CTRL_BASE                        ( PRU_ICSSG_SDDF_CTRL_BASE )
-/* SDDF Configuration */
-#define ICSSG_SDDF_CFG_BASE                         ( PRU_ICSSG_SDDF_CFG_BASE )
-#elif defined (SDDF_RTU_CORE)
-/* SDDF Control */
-#define ICSSG_SDDF_CTRL_BASE                        ( RTU_ICSSG_SDDF_CTRL_BASE )
-/* SDDF Configuration */
-#define ICSSG_SDDF_CFG_BASE                         ( RTU_ICSSG_SDDF_CFG_BASE )
-#else
-#endif
-
-/* FW register sizes (in bytes) */
-/* SDDF Control */
-#define FW_REG_SDDF_CTRL_SZ                         ( 1 )
-#define FW_REG_SDDF_STAT_SZ                         ( 1 )
-
-/* SDDF Configuration */
-#define FW_REG_SDDF_CFG_IEP_CFG_SZ                  ( 1 )
-#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_SZ     ( 4 )
-#define FW_REG_SDDF_CFG_SD_CH_ID_SZ                 ( 4 )
-#define FW_REG_SDDF_CFG_SD_CLK_SZ                   ( 2 )
-#define FW_REG_SDFM_CFG_OSR_SZ                      ( 1 )
-#define FW_REG_SDFM_CFG_EN_COMP_SZ                  ( 2 )
-#define FW_REG_SDFM_CFG_OC_HIGH_THR_SZ              ( 2 )
-#define FW_REG_SDFM_CFG_OC_LOW_THR_SZ               ( 2 )
-#define FW_REG_SDFM_CFG_ZC_ENABLE_SZ                ( 2 )
-#define FW_REG_SDFM_CFG_ZC_THR_SZ                   ( 4 )
-#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_SZ           ( 1 )
-#define FW_REG_SDFM_CFG_ZC_PREV_VAL_SZ              ( 4 )
-#define FW_REG_SDDF_CFG_OSR_SZ                      ( 1 )
-#define FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_SZ         ( 4 )
-#define FW_REG_SDDF_CFG_TRIG_SAMPLE_CNT_SZ          ( 2 )
-#define FW_REG_SDDF_CFG_NC_PRD_IEP_CNT_SZ           ( 2 )
-#define FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_SZ           ( 2 )
-#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_SZ     ( 4 )
-#define FW_REG_SDDF_CFG_OUT_SAMP_BUF_SZ             ( 4 )
-#define FW_REG_SDFM_CFG_GPIO_VALUE_SZ               ( 4 )
-#define FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ            ( 4 )
-#define FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ            ( 4 )
-#define FW_REG_SDFM_CFG_CURR_VAL_SZ                 ( 4 )
-
-/* FW register offsets from base (in bytes) */
-/* SDDF Control */
-#define FW_REG_SDDF_CTRL_OFFSET                     ( 0x00 )
-#define FW_REG_SDDF_STAT_OFFSET                     ( 0x01 )
-
-/* SDDF Configuration */
-#define FW_REG_SDDF_CFG_IEP_CFG_OFFSET              ( 0x00 )
-#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_OFFSET ( 0x06 )
-#define FW_REG_SDDF_CFG_SD_CLK_OFFSET               ( 0x0A )
-#define FW_REG_SDDF_CFG_SD_CH_ID_OFFSET             ( 0x0E )
-#define FW_REG_SDFM_CFG_SD_EN_COMP_OFFSET           ( 0x12 )
-#define FW_REG_SDFM_CFG_SD_ZC_ENABLE_OFFSET         ( 0x16 )
-#define FW_REG_SDFM_CFG_ZC_START_SZ                 ( 0x18 )
-
-/*SDFM channel offsets*/
-/*ch0 offset*/
-#define FW_REG_SDDF_CFG_CH0_CH_ID_OFFSET            ( 0x1A )
-#define FW_REG_SDDF_CFG_CH0_FILTER_TYPE_OFFSET      ( 0x1B )
-#define FW_REG_SDDF_CFG_CH0_OSR_OFFSET              ( 0x1C )
-#define FW_REG_SDFM_CFG_OC_HIGH_THR_CH0_OFFSET      ( 0x1E )
-#define FW_REG_SDFM_CFG_OC_LOW_THR_CH0_OFFSET       ( 0x22 )
-#define FW_REG_SDFM_CFG_OC_ZC_THR_CH0_OFFSET        ( 0x26 )
-#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_CH0_OFFSET   ( 0x2A )
-#define SDFM_CFG_ZC_CH0_PREV_VAL_OFFSET             ( 0x2E )
-#define FW_REG_SDDF_CFG_CH0_CLOCK_SOURCE_OFFSET     ( 0x32 )
-#define FW_REG_SDDF_CFG_CH0_CLOCK_INVERSION_OFFSET  ( 0x36 )
-#define SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET      ( 0x3A )
-#define SDFM_CFG_HIGH_THR_CH0_SET_VAL_ADDR_OFFSET   ( 0x3E )
-#define SDFM_CFG_HIGH_THR_CH0_CLR_VAL_ADDR_OFFSET   ( 0x42 )
-#define SDFM_CFG_LOW_THR_CH0_WRITE_VAL_OFFSET       ( 0x46 )
-#define SDFM_CFG_LOW_THR_CH0_SET_VAL_ADDR_OFFSET    ( 0x4A )
-#define SDFM_CFG_LOW_THR_CH0_CLR_VAL_ADDR_OFFSET    ( 0x4E )
-#define SDFM_CFG_ZC_THR_CH0_WRITE_VAL_OFFSET        ( 0x52 )
-#define SDFM_CFG_ZC_THR_CH0_SET_VAL_ADDR_OFFSET     ( 0x56 )
-#define SDFM_CFG_ZC_THR_CH0_CLR_VAL_ADDR_OFFSET     ( 0x5A )
-
-/*ch1 offsets*/
-#define FW_REG_SDDF_CFG_CH1_CH_ID_OFFSET            ( 0x5E )
-#define FW_REG_SDDF_CFG_CH1_FILTER_TYPE_OFFSET      ( 0x5F )
-#define FW_REG_SDDF_CFG_CH1_OSR_OFFSET              ( 0x60 )
-#define FW_REG_SDFM_CFG_OC_HIGH_THR_CH1_OFFSET      ( 0x62 )
-#define FW_REG_SDFM_CFG_OC_LOW_THR_CH1_OFFSET       ( 0x66 )
-#define FW_REG_SDFM_CFG_OC_ZC_THR_CH1_OFFSET        ( 0x6A )
-#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_CH1_OFFSET   ( 0x6E )
-#define SDFM_CFG_ZC_CH1_PREV_VAL_OFFSET             ( 0x72 )
-#define FW_REG_SDDF_CFG_CH1_CLOCK_SOURCE_OFFSET     ( 0x76 )
-#define FW_REG_SDDF_CFG_CH1_CLOCK_INVERSION_OFFSET  ( 0x7A )
-#define SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET      ( 0x7E )
-#define SDFM_CFG_HIGH_THR_CH1_SET_VAL_ADDR_OFFSET   ( 0x82 )
-#define SDFM_CFG_HIGH_THR_CH1_CLR_VAL_ADDR_OFFSET   ( 0x86 )
-#define SDFM_CFG_LOW_THR_CH1_WRITE_VAL_OFFSET       ( 0x8A )
-#define SDFM_CFG_LOW_THR_CH1_SET_VAL_ADDR_OFFSET    ( 0x8E )
-#define SDFM_CFG_LOW_THR_CH1_CLR_VAL_ADDR_OFFSET    ( 0x92 )
-#define SDFM_CFG_ZC_THR_CH1_WRITE_VAL_OFFSET        ( 0x96 )
-#define SDFM_CFG_ZC_THR_CH1_SET_VAL_ADDR_OFFSET     ( 0x9A )
-#define SDFM_CFG_ZC_THR_CH1_CLR_VAL_ADDR_OFFSET     ( 0x9E )
-
-
-/*ch2 offsets*/
-#define FW_REG_SDDF_CFG_CH2_CH_ID_OFFSET            ( 0xA2 )
-#define FW_REG_SDDF_CFG_CH2_FILTER_TYPE_OFFSET      ( 0xA3 )
-#define FW_REG_SDDF_CFG_CH2_OSR_OFFSET              ( 0xA4 )
-#define FW_REG_SDFM_CFG_OC_HIGH_THR_CH2_OFFSET      ( 0xA6 )
-#define FW_REG_SDFM_CFG_OC_LOW_THR_CH2_OFFSET       ( 0xAA )
-#define FW_REG_SDFM_CFG_OC_ZC_THR_CH2_OFFSET        ( 0xAE )
-#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_CH2_OFFSET   ( 0xB2 )
-#define SDFM_CFG_ZC_CH2_PREV_VAL_OFFSET             ( 0xB6 )
-#define FW_REG_SDDF_CFG_CH2_CLOCK_SOURCE_OFFSET     ( 0xBA )
-#define FW_REG_SDDF_CFG_CH2_CLOCK_INVERSION_OFFSET  ( 0xBE )
-#define SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET      ( 0xC2 )
-#define SDFM_CFG_HIGH_THR_CH2_SET_VAL_ADDR_OFFSET   ( 0xC6 )
-#define SDFM_CFG_HIGH_THR_CH2_CLR_VAL_ADDR_OFFSET   ( 0xCA )
-#define SDFM_CFG_LOW_THR_CH2_WRITE_VAL_OFFSET       ( 0xCE )
-#define SDFM_CFG_LOW_THR_CH2_SET_VAL_ADDR_OFFSET    ( 0xD2 )
-#define SDFM_CFG_LOW_THR_CH2_CLR_VAL_ADDR_OFFSET    ( 0xD6 )
-#define SDFM_CFG_ZC_THR_CH2_WRITE_VAL_OFFSET        ( 0xDA)
-#define SDFM_CFG_ZC_THR_CH2_SET_VAL_ADDR_OFFSET     ( 0xDE )
-#define SDFM_CFG_ZC_THR_CH2_CLR_VAL_ADDR_OFFSET     ( 0xE2 )
-
-/*sample timing offset*/
-#define FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_OFFSET     ( 0xE6 )
-#define FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_OFFSET       ( 0xEA )
-#define FW_REG_SDDF_CFG_NC_PRD_IEP_CNT_OFFSET       ( 0xEC )
-#define FW_REG_SDDF_CFG_SAMPLE_COUNT                ( 0xEE )
-/*Sample output offset*/
-#define FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET         ( 0xF2 )
-
-
-/*Debug Offset */
-#define DUBG_OFFSET                                   (0x110)
-
-/* FW register addresses */
-
-/* Sigma Delta Filter Control */
-#define FW_REG_SDDF_CTRL                            ( ICSSG_SDDF_CTRL_BASE + FW_REG_SDDF_CTRL_OFFSET )
-/* Sigma Delta Filter Status */
-#define FW_REG_SDDF_STAT                            ( ICSSG_SDDF_CTRL_BASE + FW_REG_SDDF_STAT_OFFSET )
-
-/* Sigma Delta Filter Configuration, IEP configuration */
-#define FW_REG_SDDF_CFG_IEP_CFG                     ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_IEP_CFG_OFFSET )
-/* Sigma Delta Filter Configuration, IEP CMP0 count for simulated EPWM period */
-#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD        ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_OFFSET )
-/* Sigma Delta Filter Configuration, SD channel IDs */
-#define FW_REG_SDDF_CFG_SD_CH_ID                    ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_SD_CH_ID_OFFSET )
-/* Sigma Delta Filter Configuration, SD clock */
-#define FW_REG_SDDF_CFG_SD_CLK                      ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_SD_CLK_OFFSET )
-/* Sigma Delta Filter Configuration, OSR */
-#define FW_REG_SDDF_CFG_OSR                         ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OSR_OFFSET )
-/* Sigma Delta Filter Configuration, positive threshold for OC detect */
-#define FW_REG_SDDF_CFG_OC_POS_THR                  ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OC_POS_THR_OFFSET )
-/* Sigma Delta Filter Configuration, negative threshold for OC detect */
-#define FW_REG_SDDF_CFG_OC_NEG_THR                  ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OC_NEG_THR_OFFSET )
-/* Sigma Delta Filter Configuration, Trigger Sample Time */
-#define FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME            ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_OFFSET )
-/* Sigma Delta Filter Configuration, Trigger Sample Count */
-#define FW_REG_SDDF_CFG_OC_PRD_IEP_CNT             ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_OFFSET )
-/* Sigma Delta Filter Configuration, NC sampling period IEP counts */
-#define FW_REG_SDDF_CFG_NC_PRD_IEP_CNT              ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_NC_PRD_IEP_CNT_OFFSET )
-/* Sigma Delta Filter Configuration, Host Sample Output Buffer */
-#define FW_REG_SDDF_CFG_OUT_SAMP_BUF                ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET )
-
-/*
-    Firmware register bit fields
-*/
-
-/* SDDF_CTRL */
-#define BF_SDDF_EN_MASK                             ( 0x1 )
-#define BF_PRU_ID_MASK                              ( 0x3 )
-#define SDDF_CTRL_BF_SDDF_EN_SHIFT                  ( 0 )
-#define SDDF_CTRL_BF_SDDF_EN_MASK                   ( BF_SDDF_EN_MASK << SDDF_CTRL_BF_SDDF_EN_SHIFT )
-#define SDDF_CTRL_BF_PRU_ID_SHIFT                   ( 1 )
-#define SDDF_CTRL_BF_PRU_ID_MASK                    ( BF_PRU_ID_MASK << SDDF_CTRL_BF_PRU_ID_SHIFT )
-/* SDDF_EN bit field */
-#define BF_SDDF_EN_DISABLE                          ( 0 )
-#define BF_SDDF_EN_ENABLE                           ( 1 )
-/* PRU ID bit field */
-#define BF_PRU_ID_0                                 ( 0 )
-#define BR_PRU_ID_1                                 ( 1 )
-#define BF_PRU_ID_UNINIT                            ( 2 )
-
-/* SDDF_STAT */
-#define BF_SDDF_EN_ACK_MASK                         ( 0x1 )
-#define BF_PRU_ID_ACK_MASK                          ( 0x3 )
-#define SDDF_STAT_BF_SDDF_EN_ACK_SHIFT              ( 0 )
-#define SDDF_STAT_BF_SDDF_EN_ACK_MASK               ( BF_SDDF_EN_ACK_MASK << SDDF_STAT_BF_SDDF_EN_ACK_SHIFT )
-#define SDDF_STAT_BF_PRU_ID_ACK_SHIFT               ( 1 )
-#define SDDF_STAT_BF_PRU_ID_ACK_MASK                ( BF_PRU_ID_ACK_MASK << SDDF_STAT_BF_PRU_ID_ACK_SHIFT )
-
-/* IEP_CFG */
-#define BF_IEP_DEFAULT_INC_MASK                     ( 0xF )
-#define IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT            ( 0 )
-#define IEP_CFG_BF_IEP_DEFAULT_INC_MASK             ( BF_IEP_DEFAULT_INC_MASK << IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT )
-
-/* IEP_CFG_EPWM_PRD */
-#define BF_CMP0_CNT_EPWM_PRD_MASK                   ( 0xFFFFFFFF )
-#define IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT          ( 0 )
-#define IEP_CFG_BF_CMP0_CNT_EPWM_PRD_MASK           ( BF_CMP0_CNT_EPWM_PRD_MASK << IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT )
-
-/* SDDF_CFG_SD_CH_ID */
-#define BF_SD_CH0_ID_MASK                           ( 0xF )
-#define BF_SD_CH1_ID_MASK                           ( 0xF )
-#define BF_SD_CH2_ID_MASK                           ( 0xF )
-#define SDDF_CFG_BF_SD_CH0_ID_SHIFT                 ( 0 )
-#define SDDF_CFG_BF_SD_CH1_ID_SHIFT                 ( 4 )
-#define SDDF_CFG_BF_SD_CH2_ID_SHIFT                 ( 8 )
-#define SDDF_CFG_BF_SD_CH0_ID_MASK                  ( BF_SD_CH0_ID_MASK << SDDF_CFG_BF_SD_CH0_ID_SHIFT )
-#define SDDF_CFG_BF_SD_CH1_ID_MASK                  ( BF_SD_CH1_ID_MASK << SDDF_CFG_BF_SD_CH1_ID_SHIFT )
-#define SDDF_CFG_BF_SD_CH2_ID_MASK                  ( BF_SD_CH2_ID_MASK << SDDF_CFG_BF_SD_CH2_ID_SHIFT )
-
-/* SDDF_CFG_SD_CLK */
-#define BF_SD_PRD_CLOCKS_MASK                       ( 0xFF )
-#define BF_SD_CLK_INV_MASK                          ( 0x1 )
-#define SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT      ( 0 )
-#define SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_MASK       ( BF_SD_PRD_CLOCKS_MASK << SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT )
-#define SDDF_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT         ( 8 )
-#define SDDF_CFG_SD_CLK_BF_SD_CLK_INV_MASK          ( BF_SD_CLK_INV_MASK << SDDF_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT )
-
-/* SDDF_CFG_OSR */
-#define BF_OC_OSR_MASK                              ( 0xFF )
-#define SDDF_CFG_OC_OSR_BF_OSR_SHIFT                ( 0 )
-#define SDDF_CFG_OC_OSR_BF_OSR_MASK                 ( BF_OC_OSR_MASK << SDDF_CFG_OC_OSR_BF_OSR_SHIFT )
-
-/* SDDF_CFG_OC_POS_THR */
-#define BF_OC_POS_THR_MASK                          ( 0xFF )
-#define SDDF_CFG_OC_POS_THR_SHIFT                   ( 0 )
-#define SDDF_CFG_OC_POS_THR_MASK                    ( BF_OC_POS_THR_MASK << SDDF_CFG_OC_POS_THR_SHIFT )
-
-/* SDDF_CFG_OC_NEG_THR */
-#define BF_OC_NEG_THR_MASK                          ( 0xFF )
-#define SDDF_CFG_OC_NEG_THR_SHIFT                   ( 0 )
-#define SDDF_CFG_OC_NEG_THR_MASK                    ( BF_OC_NEG_THR_MASK << SDDF_CFG_OC_NEG_THR_SHIFT )
-
-/* SDFM_CFG_SD_EN_COMP */
-#define SDFM_CFG_BF_SD_CH0_EN_COMP_BIT                  ( 0x00 )
-#define SDFM_CFG_BF_SD_CH1_EN_COMP_BIT                  ( 0x01 )
-#define SDFM_CFG_BF_SD_CH2_EN_COMP_BIT                  ( 0x02 )
-
-/* SDFM_CFG_ZC_ENABLE */
-#define SDFM_CFG_BF_SD_CH0_ZC_ENABLE_BIT                  ( 0x00 )
-#define SDFM_CFG_BF_SD_CH1_ZC_ENABLE_BIT                  ( 0x01 )
-#define SDFM_CFG_BF_SD_CH2_ZC_ENABLE_BIT                  ( 0x02 )
-
-
-/* SDFM_CFG_ZC_START */
-#define SDFM_CFG_BF_SD_CH0_ZC_START_BIT                  ( 0x00 )
-#define SDFM_CFG_BF_SD_CH1_ZC_START_BIT                  ( 0x01 )
-#define SDFM_CFG_BF_SD_CH2_ZC_START_BIT                  ( 0x02 )
-
-
-/* SDFM_CFG_TRIP_STATUS */
-#define SDFM_CFG_BF_SD_TRIP_STATUS_HIGH                  ( 0x01 )
-#define SDFM_CFG_BF_SD_TRIP_STATUS_LOW                   ( 0x00 )
-
-
-/* SDDF_CFG_TRIG_SAMP_TIME */
-#define BF_TRIG_SAMP_TIME_MASK                      ( 0xFFFF )
-#define SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT \
-    ( 0 )
-#define SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_MASK  \
-    ( BF_TRIG_SAMP_TIME_MASK << SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT )
-
-/* SDDF_CFG_TRIG_SAMPLE_CNT */
-#define BF_TRIG_SAMP_CNT_MASK                       ( 0xFFFF )
-#define SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT   \
-    ( 0 )
-#define SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_MASK    \
-    ( BF_TRIG_SAMP_CNT_MASK << SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT )
-
-/* SDDF_CFG_NC_PRD_IEP_CNT */
-#define BF_NC_PRD_IEP_CNT_MASK                      ( 0xFF )
-#define SDDF_CFG_NC_PRD_IEP_CNT_SHIFT               ( 0 )
-#define SDDF_CFG_NC_PRD_IEP_CNT_MASK                ( BF_NC_PRD_IEP_CNT_MASK << SDDF_CFG_NC_PRD_IEP_CNT_SHIFT )
-
-/* SDDF_CFG_NC_OUT_SAMP_BUF */
-#define BF_NC_OUT_SAMP_BUF_MASK                     ( 0xFFFF )
-#define SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT \
-    ( 0 )
-#define SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_MASK \
-    ( BF_NC_OUT_SAMP_BUF_MASK << SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT )
-
-#endif
--- a/source/current_sense/sdfm/firmware/icssg_sdfm.h
+++ b/source/current_sense/sdfm/firmware/icssg_sdfm.h
@ -0,0 +1,328 @@
+/*
+ * Copyright (c) 2023, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ICSS_SDFM_H_
+#define _ICSS_SDFM_H_
+
+/* Number of SDFM channels per PRU */
+#define ICSSG_NUM_SD_CH         ( 9 )
+/* Number of SDFM channels supported by PRU FW */
+#define ICSSG_NUM_SD_CH_FW      ( 3 )
+
+/* ICSSG INTC events */
+/* Compile-time Host event for SDFM samples available.
+   Ideally Host would provide this to FW via pseudo-register in DMEM. */
+#define PRU_TRIGGER_HOST_SDFM_EVT   ( 2+16 )    /* pr0_pru_mst_intr[2]_intr_req */
+#define RTU_TRIGGER_HOST_SDFM_EVT   ( 3+16 )    /* pr0_pru_mst_intr[3]_intr_req */
+
+
+/*
+    Firmware registers
+*/
+
+/* FW register base addresses */
+#define PRU0_DMEM                                   ( 0x0000 )
+
+
+
+/* Base address for SDFM control parameters in DMEM */
+#define ICSSG_SDFM_CTRL_BASE                        ( PRU0_DMEM )
+/* Base address for SDFM Configuration parameters in DMEM */
+#define ICSSG_SDFM_CFG_BASE                         ( PRU0_DMEM + 0x0002)
+
+
+/* FW register sizes (in bytes) */
+/* SDFM ENABLE   */
+#define SDFM_EN_SZ                       ( 1 )
+/* SDFM ENABLE ACK*/
+#define SDFM_EN_ACK_SZ                   ( 1 )
+#define SDFM_PRU_ID_SZ                   ( 1 )
+
+/* SDFM Configuration */
+#define SDFM_CFG_IEP_CFG_SZ                  ( 1 )
+#define SDFM_CFG_IEP_CFG_SIM_EPWM_PRD_SZ     ( 4 )
+
+#define SDFM_CFG_SD_CH_ID_SZ                 ( 4 )
+#define SDFM_CFG_EN_COMP_SZ                  ( 2 )
+
+#define SDFM_CFG_SD_CLK_SZ                   ( 2 )
+
+#define SDFM_CFG_OSR_SZ                      ( 1 )
+#define SDFM_CFG_OC_HIGH_THR_SZ              ( 4 )
+#define SDFM_CFG_OC_LOW_THR_SZ               ( 4 )
+
+
+
+#define SDFM_CFG_TRIG_SAMPLE_TIME_SZ         ( 4 )
+#define SDFM_CFG_TRIG_SAMPLE_CNT_SZ          ( 2 )
+#define SDFM_CFG_NC_PRD_IEP_CNT_SZ           ( 2 )
+#define SDFM_CFG_OC_PRD_IEP_CNT_SZ           ( 2 )
+
+#define SDFM_CFG_OUT_SAMP_BUF_SZ             ( 4 )
+#define SDFM_CFG_GPIO_VALUE_SZ               ( 4 )
+#define SDFM_CFG_GPIO_SET_ADDR_SZ            ( 4 )
+#define SDFM_CFG_GPIO_CLR_ADDR_SZ            ( 4 )
+#define SDFM_CFG_CURR_VAL_SZ                 ( 4 )
+
+/* FW register offsets from base (in bytes) */
+/* SDFM Control */
+#define SDFM_EN_OFFSET                     ( 0x00 )
+#define SDFM_EN_ACK_OFFSET                 ( 0x01 )
+#define SDFM_PRU_ID_OFFSET                 ( 0x02 )
+
+/* SDFM IEP Configuration */
+#define SDFM_CFG_IEP_CFG_OFFSET              ( 0x04 )
+#define SDFM_CFG_IEP_INC_OFFSET              ( 0x04 )
+#define SDFM_CFG_IEP_CFG_SIM_EPWM_PRD_OFFSET ( 0x08 )
+
+/* SDFM Clock Configuration*/
+#define SDFM_CFG_SD_CLK_OFFSET               ( 0x0C )
+#define SDFM_CFG_SD_CLK_INV_OFFSET           ( 0x0D )
+
+/* SDFM Configuration*/
+#define SDFM_CFG_SD_CH_ID_OFFSET             ( 0x10 )
+#define SDFM_CFG_SD_EN_COMP_OFFSET           ( 0x14 )
+#define SDFM_CFG_SD_ZC_ENABLE_OFFSET         ( 0x16 )
+
+
+/*SDFM channel offsets*/
+/*ch0 offset*/
+#define SDFM_CFG_CH0_CH_ID_OFFSET            ( 0x1C )
+#define SDFM_CFG_CH0_FILTER_TYPE_OFFSET      ( 0x1D )
+#define SDFM_CFG_CH0_OSR_OFFSET              ( 0x1E )
+
+#define SDFM_CFG_OC_HIGH_THR_CH0_OFFSET      ( 0x20 )
+#define SDFM_CFG_OC_LOW_THR_CH0_OFFSET       ( 0x24 )
+
+#define SDFM_CFG_CH0_FD_WD_REG_OFFSET        ( 0x2C)
+#define SDFM_CFG_CH0_FD_ZERO_MAX_REG_OFFSET  ( 0x2D)
+#define SDFM_CFG_CH0_FD_ZERO_MIN_REG_OFFSET  ( 0x2E)
+#define SDFM_CFG_CH0_FD_ONE_MAX_REG_OFFSET   ( 0x2F)
+#define SDFM_CFG_CH0_FD_ONE_MIN_REG_OFFSET   ( 0x30)
+
+#define SDFM_CFG_CH0_CLOCK_SOURCE_OFFSET     ( 0x34 )
+#define SDFM_CFG_CH0_CLOCK_INVERSION_OFFSET  ( 0x38 )
+
+#define SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET      ( 0x3C )
+#define SDFM_CFG_HIGH_THR_CH0_SET_VAL_ADDR_OFFSET   ( 0x40 )
+#define SDFM_CFG_HIGH_THR_CH0_CLR_VAL_ADDR_OFFSET   ( 0x44 )
+#define SDFM_CFG_LOW_THR_CH0_WRITE_VAL_OFFSET       ( 0x48 )
+#define SDFM_CFG_LOW_THR_CH0_SET_VAL_ADDR_OFFSET    ( 0x4C )
+#define SDFM_CFG_LOW_THR_CH0_CLR_VAL_ADDR_OFFSET    ( 0x50 )
+
+
+/*ch1 offsets*/
+#define SDFM_CFG_CH1_CH_ID_OFFSET            ( 0x60 )
+#define SDFM_CFG_CH1_FILTER_TYPE_OFFSET      ( 0x61 )
+#define SDFM_CFG_CH1_OSR_OFFSET              ( 0x62 )
+
+#define SDFM_CFG_OC_HIGH_THR_CH1_OFFSET      ( 0x64 )
+#define SDFM_CFG_OC_LOW_THR_CH1_OFFSET       ( 0x68 )
+
+#define SDFM_CFG_CH1_FD_WD_REG_OFFSET        ( 0x70 )
+#define SDFM_CFG_CH1_FD_ZERO_MAX_REG_OFFSET  ( 0x71 )
+#define SDFM_CFG_CH1_FD_ZERO_MIN_REG_OFFSET  ( 0x72 )
+#define SDFM_CFG_CH1_FD_ONE_MAX_REG_OFFSET   ( 0x73 )
+#define SDFM_CFG_CH1_FD_ONE_MIN_REG_OFFSET   ( 0x74 )
+
+#define SDFM_CFG_CH1_CLOCK_SOURCE_OFFSET     ( 0x78 )
+#define SDFM_CFG_CH1_CLOCK_INVERSION_OFFSET  ( 0x7C )
+
+#define SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET      ( 0x80 )
+#define SDFM_CFG_HIGH_THR_CH1_SET_VAL_ADDR_OFFSET   ( 0x84 )
+#define SDFM_CFG_HIGH_THR_CH1_CLR_VAL_ADDR_OFFSET   ( 0x88 )
+#define SDFM_CFG_LOW_THR_CH1_WRITE_VAL_OFFSET       ( 0x8C )
+#define SDFM_CFG_LOW_THR_CH1_SET_VAL_ADDR_OFFSET    ( 0x90 )
+#define SDFM_CFG_LOW_THR_CH1_CLR_VAL_ADDR_OFFSET    ( 0x94 )
+
+
+
+/*ch2 offsets*/
+#define SDFM_CFG_CH2_CH_ID_OFFSET            ( 0xA4 )
+#define SDFM_CFG_CH2_FILTER_TYPE_OFFSET      ( 0xA5 )
+#define SDFM_CFG_CH2_OSR_OFFSET              ( 0xA6 )
+
+#define SDFM_CFG_OC_HIGH_THR_CH2_OFFSET      ( 0xA8 )
+#define SDFM_CFG_OC_LOW_THR_CH2_OFFSET       ( 0xAC )
+
+#define SDFM_CFG_CH2_FD_WD_REG_OFFSET        ( 0xB4 )
+#define SDFM_CFG_CH2_FD_ZERO_MAX_REG_OFFSET  ( 0xB5 )
+#define SDFM_CFG_CH2_FD_ZERO_MIN_REG_OFFSET  ( 0xB6 )
+#define SDFM_CFG_CH2_FD_ONE_MAX_REG_OFFSET   ( 0xB7 )
+#define SDFM_CFG_CH2_FD_ONE_MIN_REG_OFFSET   ( 0xB8 )
+
+
+#define SDFM_CFG_CH2_CLOCK_SOURCE_OFFSET     ( 0xBC )
+#define SDFM_CFG_CH2_CLOCK_INVERSION_OFFSET  ( 0xC0 )
+
+#define SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET      ( 0xC4 )
+#define SDFM_CFG_HIGH_THR_CH2_SET_VAL_ADDR_OFFSET   ( 0xC8 )
+#define SDFM_CFG_HIGH_THR_CH2_CLR_VAL_ADDR_OFFSET   ( 0xCC )
+#define SDFM_CFG_LOW_THR_CH2_WRITE_VAL_OFFSET       ( 0xD0 )
+#define SDFM_CFG_LOW_THR_CH2_SET_VAL_ADDR_OFFSET    ( 0xD4 )
+#define SDFM_CFG_LOW_THR_CH2_CLR_VAL_ADDR_OFFSET    ( 0xD8 )
+
+
+/*sample timing offset*/
+#define SDFM_CFG_EN_DOUBLE_UPDATE                   ( 0xE8 )
+#define FW_REG_SDFM_CFG_FIRST_TRIG_SAMPLE_TIME      ( 0xEC )
+#define FW_REG_SDFM_CFG_SECOND_TRIG_SAMPLE_TIME     ( 0xF0 )
+#define SDFM_CFG_NC_PRD_IEP_CNT_OFFSET              ( 0xF4)
+
+/*Sample output offset*/
+#define SDFM_CFG_OUT_SAMP_BUF_OFFSET         ( 0xF8 )
+
+/*Debug */
+#define SDFM_DUBUG_OFFSET         ( 0x104 )
+
+/*
+    Firmware register bit fields
+*/
+
+/* SDFM_CTRL */
+#define BF_SDFM_EN_MASK                             ( 0x1 )
+#define BF_PRU_ID_MASK                              ( 0x3 )
+#define SDFM_CTRL_BF_SDFM_EN_SHIFT                  ( 0 )
+#define SDFM_CTRL_BF_SDFM_EN_MASK                   ( BF_SDFM_EN_MASK << SDFM_CTRL_BF_SDFM_EN_SHIFT )
+#define SDFM_CTRL_BF_PRU_ID_SHIFT                   ( 1 )
+#define SDFM_CTRL_BF_PRU_ID_MASK                    ( BF_PRU_ID_MASK << SDFM_CTRL_BF_PRU_ID_SHIFT )
+/* SDFM_EN bit field */
+#define BF_SDFM_EN_DISABLE                          ( 0 )
+#define BF_SDFM_EN_ENABLE                           ( 1 )
+/* PRU ID bit field */
+#define BF_PRU_ID_0                                 ( 0 )
+#define BR_PRU_ID_1                                 ( 1 )
+#define BF_PRU_ID_UNINIT                            ( 2 )
+
+/* SDFM_STAT */
+#define BF_SDFM_EN_ACK_MASK                         ( 0x1 )
+#define BF_PRU_ID_ACK_MASK                          ( 0x3 )
+#define SDFM_STAT_BF_SDFM_EN_ACK_SHIFT              ( 0 )
+#define SDFM_STAT_BF_SDFM_EN_ACK_MASK               ( BF_SDFM_EN_ACK_MASK << SDFM_STAT_BF_SDFM_EN_ACK_SHIFT )
+#define SDFM_STAT_BF_PRU_ID_ACK_SHIFT               ( 1 )
+#define SDFM_STAT_BF_PRU_ID_ACK_MASK                ( BF_PRU_ID_ACK_MASK << SDFM_STAT_BF_PRU_ID_ACK_SHIFT )
+
+/* IEP_CFG */
+#define BF_IEP_DEFAULT_INC_MASK                     ( 0xF )
+#define IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT            ( 0 )
+#define IEP_CFG_BF_IEP_DEFAULT_INC_MASK             ( BF_IEP_DEFAULT_INC_MASK << IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT )
+
+/* IEP_CFG_EPWM_PRD */
+#define BF_CMP0_CNT_EPWM_PRD_MASK                   ( 0xFFFFFFFF )
+#define IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT          ( 0 )
+#define IEP_CFG_BF_CMP0_CNT_EPWM_PRD_MASK           ( BF_CMP0_CNT_EPWM_PRD_MASK << IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT )
+
+/* SDFM_CFG_SD_CH_ID */
+#define BF_SD_CH0_ID_MASK                           ( 0xF )
+#define BF_SD_CH1_ID_MASK                           ( 0xF )
+#define BF_SD_CH2_ID_MASK                           ( 0xF )
+#define SDFM_CFG_BF_SD_CH0_ID_SHIFT                 ( 0 )
+#define SDFM_CFG_BF_SD_CH1_ID_SHIFT                 ( 4 )
+#define SDFM_CFG_BF_SD_CH2_ID_SHIFT                 ( 8 )
+#define SDFM_CFG_BF_SD_CH0_ID_MASK                  ( BF_SD_CH0_ID_MASK << SDFM_CFG_BF_SD_CH0_ID_SHIFT )
+#define SDFM_CFG_BF_SD_CH1_ID_MASK                  ( BF_SD_CH1_ID_MASK << SDFM_CFG_BF_SD_CH1_ID_SHIFT )
+#define SDFM_CFG_BF_SD_CH2_ID_MASK                  ( BF_SD_CH2_ID_MASK << SDFM_CFG_BF_SD_CH2_ID_SHIFT )
+
+/* SDFM_CFG_SD_CLK */
+#define BF_SD_PRD_CLOCKS_MASK                       ( 0xFF )
+#define BF_SD_CLK_INV_MASK                          ( 0x1 )
+#define SDFM_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT      ( 0 )
+#define SDFM_CFG_SD_CLK_BF_SD_PRD_CLOCKS_MASK       ( BF_SD_PRD_CLOCKS_MASK << SDFM_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT )
+#define SDFM_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT         ( 8 )
+#define SDFM_CFG_SD_CLK_BF_SD_CLK_INV_MASK          ( BF_SD_CLK_INV_MASK << SDFM_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT )
+
+/* SDFM_CFG_OSR */
+#define BF_OC_OSR_MASK                              ( 0xFF )
+#define SDFM_CFG_OC_OSR_BF_OSR_SHIFT                ( 0 )
+#define SDFM_CFG_OC_OSR_BF_OSR_MASK                 ( BF_OC_OSR_MASK << SDFM_CFG_OC_OSR_BF_OSR_SHIFT )
+
+/* SDFM_CFG_OC_POS_THR */
+#define BF_OC_POS_THR_MASK                          ( 0xFF )
+#define SDFM_CFG_OC_POS_THR_SHIFT                   ( 0 )
+#define SDFM_CFG_OC_POS_THR_MASK                    ( BF_OC_POS_THR_MASK << SDFM_CFG_OC_POS_THR_SHIFT )
+
+/* SDFM_CFG_OC_NEG_THR */
+#define BF_OC_NEG_THR_MASK                          ( 0xFF )
+#define SDFM_CFG_OC_NEG_THR_SHIFT                   ( 0 )
+#define SDFM_CFG_OC_NEG_THR_MASK                    ( BF_OC_NEG_THR_MASK << SDFM_CFG_OC_NEG_THR_SHIFT )
+
+/* SDFM_CFG_SD_EN_COMP */
+#define SDFM_CFG_EN_COMP_BIT                            ( 0x00 )
+#define SDFM_CFG_BF_SD_CH0_EN_COMP_BIT                  ( 0x01 )
+#define SDFM_CFG_BF_SD_CH1_EN_COMP_BIT                  ( 0x02 )
+#define SDFM_CFG_BF_SD_CH2_EN_COMP_BIT                  ( 0x03 )
+
+/* SDFM_CFG_ZC_ENABLE */
+#define SDFM_CFG_BF_SD_CH0_ZC_ENABLE_BIT                  ( 0x00 )
+#define SDFM_CFG_BF_SD_CH1_ZC_ENABLE_BIT                  ( 0x01 )
+#define SDFM_CFG_BF_SD_CH2_ZC_ENABLE_BIT                  ( 0x02 )
+
+
+/* SDFM_CFG_ZC_START */
+#define SDFM_CFG_BF_SD_CH0_ZC_START_BIT                  ( 0x00 )
+#define SDFM_CFG_BF_SD_CH1_ZC_START_BIT                  ( 0x01 )
+#define SDFM_CFG_BF_SD_CH2_ZC_START_BIT                  ( 0x02 )
+
+
+/* SDFM_CFG_TRIP_STATUS */
+#define SDFM_CFG_BF_SD_TRIP_STATUS_HIGH                  ( 0x01 )
+#define SDFM_CFG_BF_SD_TRIP_STATUS_LOW                   ( 0x00 )
+
+
+/* SDFM_CFG_TRIG_SAMP_TIME */
+#define BF_TRIG_SAMP_TIME_MASK                      ( 0xFFFF )
+#define SDFM_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT \
+    ( 0 )
+#define SDFM_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_MASK  \
+    ( BF_TRIG_SAMP_TIME_MASK << SDFM_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT )
+
+/* SDFM_CFG_TRIG_SAMPLE_CNT */
+#define BF_TRIG_SAMP_CNT_MASK                       ( 0xFFFF )
+#define SDFM_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT   \
+    ( 0 )
+#define SDFM_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_MASK    \
+    ( BF_TRIG_SAMP_CNT_MASK << SDFM_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT )
+
+/* SDFM_CFG_NC_PRD_IEP_CNT */
+#define BF_NC_PRD_IEP_CNT_MASK                      ( 0xFF )
+#define SDFM_CFG_NC_PRD_IEP_CNT_SHIFT               ( 0 )
+#define SDFM_CFG_NC_PRD_IEP_CNT_MASK                ( BF_NC_PRD_IEP_CNT_MASK << SDFM_CFG_NC_PRD_IEP_CNT_SHIFT )
+
+/* SDFM_CFG_NC_OUT_SAMP_BUF */
+#define BF_NC_OUT_SAMP_BUF_MASK                     ( 0xFFFF )
+#define SDFM_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT \
+    ( 0 )
+#define SDFM_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_MASK \
+    ( BF_NC_OUT_SAMP_BUF_MASK << SDFM_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT )
+
+
+#endif
--- a/source/current_sense/sdfm/firmware/sddf.asm
+++ b/source/current_sense/sdfm/firmware/sddf.asm
@ -1,885 +0,0 @@
-;
-; Copyright (c) 2023, Texas Instruments Incorporated
-; All rights reserved.
-;
-;  Redistribution and use in source and binary forms, with or without
-;  modification, are permitted provided that the following conditions
-;  are met:
-;
-;  *  Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;
-;  *  Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;
-;  *  Neither the name of Texas Instruments Incorporated nor the names of
-;     its contributors may be used to endorse or promote products derived
-;     from this software without specific prior written permission.
-;
-;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-;  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-;  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-;  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-;  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-;  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-;  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-;  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-;  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-;  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-
-        .cdecls C,NOLIST
-%{
-        #include "icssg_sddf.h"
-%}
-        .include "sddf_cfg.h"
-        .include "sddf.h"
-        .include "sddf_macros.h"
-
-
-; Compile-time Host event for SDDF samples available
-; R31 event interface mapping, add pru<n>_r31_vec_valid to system event number, <sysevt> + 1<<5
-    .if $isdefed("SDDF_PRU_CORE")
-TRIGGER_HOST_SDDF_IRQ   .set PRU_TRIGGER_HOST_SDDF_EVT + 16
-    .elseif $isdefed("SDDF_RTU_CORE")
-TRIGGER_HOST_SDDF_IRQ   .set RTU_TRIGGER_HOST_SDDF_EVT + 16
-    .endif
-
-;SPAD Bank for SD Ch context storage
-BANK_CTXT_NC               .set BANK0
-BANK_CTXT_OC               .set BANK1
-;differentiator state located in BANK locations 9-17
-NUM_REGS_DIFF_STATE    .set  9  ; Number of PRU registers for differentiator state
-OUT_SAMP_MASK           .set 0x0FFFFFFF ; 28-bit mask applied to Integrator & Differentiator output
-
-
-;registers R20 - R24
-;R20: contain address of NC local output
-;R21; output mask
-;R22.w0 channel ID
-;R22.W1 required OC Sample count for NC
-;R23 DMEM base address + (0x02)
-;R24 PRUx CFG base address
-
-
-        ; local interleaved NC output sample buffer
-OUT_SAMP_BUF:   .usect  ".outSamps", ICSSG_NUM_SD_CH_FW*4, 4
-        .retain         ".outSamps"
-        .retainrefs     ".outSamps"
-
-        .def    SDDF_ENTRY  ; global entry point
-        .ref    dbg_setup_pinmux
-
-        .sect   ".text"
-        .retain ".text"
-        .retainrefs ".text"
-SDDF_ENTRY:
-        ; Clear registers R0-R30
-        ZERO    &R0, 124
-
-        ; Disable Task Manager
-        .word 0x32000000
-
-        ; Clear Task Manager status which is sticky after debug halt
-        LDI     TREG0.w0, 0x0fff
-        SBCO    &TREG0.w0, CT_PRU_ICSSG_TM, 0, 2
-        XIN     TM_YIELD_XID, &R0.b3,1
-        LDI     TREG0.w0, 0
-        SBCO    &TREG0.w0, CT_PRU_ICSSG_TM, 0, 2
-
-
-        ; Write C24 block index for access to FW registers
-        WRITE_C24_BLK_INDEX C24_BLK_INDEX_FW_REGS_VAL
-
-;
-; Check PRU ID & set PRU ID acknowledge
-;
-check_pru_id:
-        ; Wait for Host to update PRU ID
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CTRL, FW_REG_SDDF_CTRL_SZ ; Load TR0.b0 <- FW_REG_SDDF_CTRL
-        AND     TREG0.b0, TREG0.b0, SDDF_CTRL_BF_PRU_ID_MASK                            ; Mask PRU_ID bit field in TR0.b0
-        LDI     TREG1.b0, BF_PRU_ID_UNINIT<<SDDF_CTRL_BF_PRU_ID_SHIFT                   ; Load TR1.b0 <- PRU_ID_UNINIT at PRU_ID bit field location
-        SUB     TREG2.b0, TREG0.b0, TREG1.b0                                            ; TR2.b0 = TR1.b0 - TR0.b0
-        QBEQ    check_pru_id, TREG2.b0, 0                                               ; TR2.b0 == 0 indicates PRU_ID is uninitialized,
-                                                                                        ; TR2.b0 != 0 indicates PRU_ID is initialized
-        ; Set PRU ID acknowledge
-        LBCO    &TREG1.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_STAT, FW_REG_SDDF_STAT_SZ ; Load TR1.b0 <- FW_REG_SDDF_STAT
-        AND     TREG2.b0, TREG1.b0, SDDF_STAT_BF_PRU_ID_ACK_MASK                        ; Mask PRU_ID_ACK bit field in TR1.b0
-        QBEQ    check_sddf_en, TREG0.b0, TREG2.b0                                       ; TR0.b0 == TR2.b0 indicates PRU_ID and PRU_ID_ACK bit fields are equal
-        LDI     TREG2.b0, SDDF_STAT_BF_PRU_ID_ACK_MASK                                  ; Load TR2.b0 <- PRU_ID_ACK mask
-        NOT     TREG2.b0, TREG2.b0                                                      ; TR2.b0 = ~(PRU_ID_ACK mask)
-        AND     TREG1.b0, TREG1.b0, TREG2.b0                                            ; Clear PRU_ID_ACK bit field
-        OR      TREG1.b0, TREG1.b0, TREG0.b0                                            ; Insert PRU_ID into PRU_ID_ACK bit field
-        SBCO    &TREG1.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_STAT, FW_REG_SDDF_STAT_SZ ; Store TR1.b0 -> FW_REG_SDDF_STAT
-
-;
-; Check SDDF global enable & set SDDF global enable acknowledge.
-; If SDDF global enable not set, allow re-selection of PRU ID.
-;
-check_sddf_en:
-        ; Check SDDF global enable
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CTRL, FW_REG_SDDF_CTRL_SZ ; Load TR0.b0 <- FW_REG_SDDF_CTRL
-        QBBC    check_pru_id, TREG0.b0, SDDF_CTRL_BF_SDDF_EN_SHIFT                      ; If SDDF_EN not set, re-check PRU_ID
-
-        ; Set SDDF global enable acknowledge
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_STAT, FW_REG_SDDF_STAT_SZ ; Load TR0.b0 <- FW_REG_SDDF_STAT
-        SET     TREG0, TREG0, SDDF_CTRL_BF_SDDF_EN_SHIFT                                ; Set SDDF_EN_ACK bit
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_STAT, FW_REG_SDDF_STAT_SZ ; Store FW_REG_SDDF_STAT -> TR0.b0
-
-;
-; Perform initialization
-;
-init_sddf:
-        ; Enable XIN/XOUT shifting.
-        ; Used for context & SD state save/restore in TM tasks.
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_CFG, ICSSG_CFG_SPPC, 1
-    .if $isdefed("SDDF_PRU_CORE")
-        SET     TREG0, TREG0, XFR_SHIFT_EN_BN   ; ICSSG_SPP_REG:XFR_SHIFT_EN=1
-    .elseif $isdefed("SDDF_RTU_CORE")
-        SET     TREG0, TREG0, RTU_XFR_SHIFT_EN   ; ICSSG_SPP_REG:RTU_XFR_SHIFT_EN=1
-    .endif
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_CFG, ICSSG_CFG_SPPC, 1
-
-        ; Initialize Task Manager
-        JAL     RET_ADDR_REG, tm_init
-
-        ; Enable Task Manager
-        .word   0x32800000
-
-    .if $isdefed("SDDF_PRU_CORE") ; no IEP on RTU
-        ; Initialize IEP0
-        JAL     RET_ADDR_REG, iep0_init
-    .endif
-
-
-        ; Initialize SD mode
-        LDI32   TREG1, PR1_PRUn_GP_MUX_SEL_VAL<<PR1_PRUn_GP_MUX_SEL_SHIFT
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CTRL, FW_REG_SDDF_CTRL_SZ ; Load TR0.b0 <- FW_REG_SDDF_CTRL
-        QBBS    init_pru_id1, TREG0, SDDF_CTRL_BF_PRU_ID_SHIFT                          ; Check PRU ID 0 or 1
-init_pru_id0:
-        SBCO    &TREG1, CT_PRU_ICSSG_CFG, ICSSG_CFG_GPCFG0, 4                           ; Initialize PRU0 SD mode
-        QBA     init_sddf_cont
-init_pru_id1:
-        SBCO    &TREG1, CT_PRU_ICSSG_CFG, ICSSG_CFG_GPCFG1, 4                           ; Initialize PRU1 SD mode
-
-
-init_sddf_cont:
-
-        ; Reset SDDF state
-        JAL     RET_ADDR_REG, reset_sddf_state
-
-        ; Set base pointer to FW Configuration registers
-        LDI     SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_IEP_CFG
-
-        ; Set base point to SD HW registers ; (PRUx_CFG_BASE address)
-        SET_SD_HW_REG_BASE_PTR SD_HW_BASE_PTR_REG
-
-        ; Initialize SD clock
-        JAL     RET_ADDR_REG, init_sd_clock
-
-        ; Configure OSR for SD channels
-        JAL     RET_ADDR_REG, config_oc_osr
-
-        ; Configure SD channels. For all channels, initialize:
-        ;   ACC select: ACC3
-        ;   Clock inversion
-        ;   Clock source: pr1_pru<n>_pru_r31_in[16] Primary Input
-        JAL     RET_ADDR_REG, config_sd_ch
-
-        ; Global enable SD HW,
-        ; reset SD channel HW
-        JAL     RET_ADDR_REG, reset_sd_ch_hw
-        SET     R30.t25 ; R30[25] channel_en = 1, all channels enabled
-
-        ; Initialize dedicated registers:
-        ;   MASK register,
-        ;   Local NC output sample buffer address,
-        ;   clear sample count
-        LDI32   MASK_REG, OUT_SAMP_MASK
-        LDI32   OUT_SAMP_BUF_REG, OUT_SAMP_BUF
-        LDI     SAMP_CNT_REG, 0
-
-    .if $isdefed("SDDF_PRU_CORE") ; no IEP on RTU
-        ; Start IEP
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1
-        SET     TREG0, TREG0, CNT_ENABLE_BN ; ICSSG_IEP_GLOBAL_CFG_REG:CNT_ENABLE=1
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1
-    .endif
-
-        ; Generate OC output samples
-        ;
-        ; TR0.b0: ch ID
-        ; TR0.b1: channel ID FW register shift amount
-        ; TR0.w2: channel ID FW register
-
-        ; Load TR0.w1 <- SDDF_CFG_SD_CH_ID
-        ;LBBO    &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ
-        LBBO    &SD_CH_ID, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ
-        ;LDI     TREG0.b1, 0 ; init Ch ID shift
-        ;LDI     TREG1.w2, 0 ; init OC detect count
-
-Waitloop:
-       JMP Waitloop
-
-
-
-ts1_oc_loop:
-
-
-        ; Save/restore context
-        ; restore differentiator state(R9-R17)
-        xchg    BANK_CTXT_OC, &R9, 4*NUM_REGS_DIFF_STATE
-
-        ; Clear IEP0 CMP4 events
-        .if $isdefed("SDDF_PRU_CORE")
-        LDI		TREG0.b0, 0x10
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
-        .endif
-
-        .if $isdefed("DEBUG_CODE")
-        ;Debug code  :GPIO HIGH
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        ;debug code end
-        .endif
-
-         ; update IEP0 CMP4
-       .if $isdefed("SDDF_PRU_CORE")
-        LDI     TREG0,0
-        LBCO    &TREG0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_OC_PRD_IEP_CNT, FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_SZ
-        LBCO    &TREG1, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4 ;
-        MOV     CURRENT_COMP4_REG_VALUE, TREG1 ; store current cmp4 register value for check time trigger
-        ADD     TREG0, TREG1, TREG0
-        ;read iep counter maximum value
-        LDI     TREG1, 0
-        LBCO    &TREG1, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD, 2
-        QBLE    UPDATE_CMP4_FOR_IEP_RESET,  TREG0, TREG1
-        ;update Cmp4 with old value + next sample time value
-        SBCO    &TREG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4
-        JMP     END_CMP4_UPDATE
-UPDATE_CMP4_FOR_IEP_RESET:
-        ;Update cmp4 according to iep reset
-        SUB      TREG0, TREG0, TREG1
-        SBCO    &TREG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4
-
-END_CMP4_UPDATE:
-       .endif
-
-        ;select ch0, enable all channel, set SD snoop=1 & sample_counter_select=1
-        LDI     R30.w2, (SD_CH0_ID<<10 | 1<<9 | 1<<6 | 1<<5)
-        NOP
-
-        ; Snoop read Ch0 sample_counter,
-        ; wait for ChX sample count+1.
-        AND     TREG1, R31, 0xFF ; snoop read LSB Ch0 sample_counter
-wait_sample_count_incr_oc:
-        AND     TREG2, R31, 0xFF ; snoop read LSB Ch0 sample_counter
-        QBEQ    wait_sample_count_incr_oc, TREG2, TREG1
-
-        ; Snoop read Ch0 ACC3
-        CLR     R30.t21                 ; set SD sample_counter_select=0
-        NOP
-        AND     TREG0, R31, MASK_REG      ; TREG0 = Ch0 SD HW ACC3 output sample
-        CLR     R30.t22                 ; set SD snoop=0
-
-         ;select ch1, enable all channel & set SD snoop=1
-        LDI     R30.w2, (SD_CH1_ID<<10 | 1<<9 | 1<<6)
-        NOP
-
-        ; Snoop read ACC3 for SD Ch1
-        AND     TREG1, R31, MASK_REG    ; TREG1 = Ch1 SD HW ACC3 output sample
-        CLR     R30.t22                 ; set SD snoop=0
-
-        ;select ch2, enable all channel & set SD snoop=1
-        LDI     R30.w2, (SD_CH2_ID<<10 | 1<<9 | 1<<6)
-        NOP
-
-        ; Snoop read ACC3 for SD Ch2
-        AND     TREG2, R31, MASK_REG    ; TREG2 = Ch2 SD HW ACC3 output sample
-        CLR     R30.t22                 ; set SD snoop=0
-
-         ;NC sampling
-         ;One NC sample after every NC_PRD_CNT number of OC sample because NC OSR = NC_PRD_CNT * OC_OSR
-         ;read NC_PRD_CNT
-         LDI     TREG3, 0
-         LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SAMPLE_COUNT, 2
-         SUB     TREG3, TREG3, 1
-         QBLE    read_nc_frame, SAMP_CNT_REG, TREG3
-         ADD     SAMP_CNT_REG, SAMP_CNT_REG, 1   ; increment OC sample count
-         QBA     skip_nc_frame
-read_nc_frame:
-
-          .if $isdefed("DEBUG_CODE")
-        ;Debug code  :GPIO HIGH
-         LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ
-         LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-         SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        ;debug code end
-        .endif
-
-        ; restore differentiator state(R9-R17)
-        xchg    BANK_CTXT_NC, &R9, 4*NUM_REGS_DIFF_STATE
-
-         ; Execute SINC3 differentiation for Ch0
-         MOV     DN0, TREG0 ; DN0 = Ch1 SD HW ACC3 output sample
-        M_ACC3_PROCESS ACC3_DN1_CH0, ACC3_DN3_CH0, ACC3_DN5_CH0
-        ; Save NC output sample to local output sample buffer
-        SBBO    &CN5, OUT_SAMP_BUF_REG, 0, 4
-
-
-        ; Execute SINC3 differentiation for Ch1
-        MOV     DN0, TREG1 ; DN0 = Ch1 SD HW ACC3 output sample
-        M_ACC3_PROCESS ACC3_DN1_CH1, ACC3_DN3_CH1, ACC3_DN5_CH1
-        ; Save output sample to local output sample buffer
-       SBBO    &CN5, OUT_SAMP_BUF_REG, 4, 4
-
-        ; Execute SINC3 differentiation for Ch2
-        MOV     DN0, TREG2 ; DN0 = Ch2 SD HW ACC3 output sample
-        M_ACC3_PROCESS ACC3_DN1_CH2, ACC3_DN3_CH2, ACC3_DN5_CH2
-        ; Save output sample to local output sample buffer
-        SBBO    &CN5, OUT_SAMP_BUF_REG, 8, 4
-
-
-        .if $isdefed("DEBUG_CODE")
-        ;Debug code
-        ; Write local interleaved output samples to Host buffer address
-        LBBO    &TREG3, OUT_SAMP_BUF_REG, 0, ICSSG_NUM_SD_CH_FW*4
-        SBBO    &TREG3,  SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET, ICSSG_NUM_SD_CH_FW*4
-        ; Trigger interrupt
-        LDI     R31.w0, TRIGGER_HOST_SDDF_IRQ
-        .endif
-
-
-         ;sample read
-        LBCO  &TREG3, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME, FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_SZ
-        QBLE    sample_time_before_sample, CURRENT_COMP4_REG_VALUE, TREG3
-        SUB  CURRENT_COMP4_REG_VALUE, TREG3, CURRENT_COMP4_REG_VALUE
-        LBCO  &TREG3, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_NC_PRD_IEP_CNT, FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_SZ
-        ;LDI  TREG3, 0x780
-        LSR  TREG3, TREG3, 1
-        QBGE    skip_sample_read, TREG3, CURRENT_COMP4_REG_VALUE
-        QBA     trigger_intruppt
-sample_time_before_sample:
-        SUB  CURRENT_COMP4_REG_VALUE, CURRENT_COMP4_REG_VALUE, TREG3
-        LBCO  &TREG3, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_NC_PRD_IEP_CNT, FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_SZ
-        ;LDI  TREG3, 0x780
-         LSR  TREG3, TREG3, 1
-        QBLE    skip_sample_read,  CURRENT_COMP4_REG_VALUE, TREG3
-        QBA     trigger_intruppt
-trigger_intruppt:
-
-         .if $isdefed("DEBUG_CODE")
-          ;GPIO HIGH
-           LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ
-          LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-          SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-         .endif
-        ; Write local interleaved output samples to Host buffer address
-        LBBO    &TREG3, OUT_SAMP_BUF_REG, 0, ICSSG_NUM_SD_CH_FW*4
-        SBBO    &TREG3,  SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET, ICSSG_NUM_SD_CH_FW*4
-        ; Trigger interrupt
-        LDI     R31.w0, TRIGGER_HOST_SDDF_IRQ
-
-         .if $isdefed("DEBUG_CODE")
-         ;GPIO LOW
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        .endif
-
-skip_sample_read:
-
-
-
-         ;restore/save contex
-         ;save differentiator state(R9-R17)
-         xchg    BANK_CTXT_NC, &R9, 4*NUM_REGS_DIFF_STATE
-
-         .if $isdefed("DEBUG_CODE")
-        ;GPIO LOW
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        .endif
-
-        LDI     SAMP_CNT_REG, 0 ; reset  sample count
-skip_nc_frame:
-
-        ; Execute SINC3 differentiation for Ch0
-        MOV     DN0, TREG0 ; DN0 = Ch1 SD HW ACC3 output sample
-        MOV     TREG0, TREG1  ;move Ch1 data into TREG0
-        MOV     TREG1, TREG2  ; Move ch2 data into TREG1
-        M_ACC3_PROCESS ACC3_DN1_CH0, ACC3_DN3_CH0, ACC3_DN5_CH0
-
-
-        ;Comparator for Ch0
-        MOV     TREG2, CN5
-
-        .if $isdefed("DEBUG_CODE")
-        SBBO    &CN5, OUT_SAMP_BUF_REG, 0, 4
-        .endif
-
-        ;For the current channel, compare against the High threshold, Low threshold and ZC thresholds (if enabled)
-        ;Load the positive threshold value for current channel
-        LBBO    &OC_HIGH_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_HIGH_THR_CH0_OFFSET, FW_REG_SDFM_CFG_OC_HIGH_THR_SZ
-        ;Load the positive threshold value for current channel
-        LBBO    &OC_LOW_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_LOW_THR_CH0_OFFSET, FW_REG_SDFM_CFG_OC_LOW_THR_SZ
-        ;Load the zero crossing threshold value for current channel
-        LBBO    &OC_ZC_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_ZC_THR_CH0_OFFSET, FW_REG_SDFM_CFG_ZC_THR_SZ
-
-        ;Check if the comparator is enabled for current channel
-        LBBO    &COMPARATOR_EN, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_SD_EN_COMP_OFFSET, FW_REG_SDFM_CFG_EN_COMP_SZ
-        QBBC    comp_ch0_end, COMPARATOR_EN, SDFM_CFG_BF_SD_CH0_EN_COMP_BIT
-        ;Check if the sample value is greater than the high threshold
-        QBGE    over_threshold_start_ch0, OC_HIGH_THR, TREG2
-        ;Check if the sample value is lower than the high threshold
-        QBLE    over_threshold_end_ch0, OC_HIGH_THR, TREG2
-low_threshold_ch0_check:
-        ;Check if the sample value is greater than the low threshold
-        QBGE    below_threshold_end_ch0, OC_LOW_THR, TREG2
-        ;Check if the sample value is lower than the low threshold
-        QBLE    below_threshold_start_ch0, OC_LOW_THR, TREG2
-over_threshold_start_ch0:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        QBA low_threshold_ch0_check
-
-over_threshold_end_ch0:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        QBA low_threshold_ch0_check
-
-below_threshold_end_ch0:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH0_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        QBA comp_ch0_end
-
-below_threshold_start_ch0:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH0_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH0_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-
-
-comp_ch0_end:
-
-
-        ; Execute SINC3 differentiation for Ch1
-        MOV     DN0, TREG0 ; DN0 = Ch1 SD HW ACC3 output sample
-        M_ACC3_PROCESS ACC3_DN1_CH1, ACC3_DN3_CH1, ACC3_DN5_CH1
-
-
-        ;Comparator for ch1
-        MOV     TREG2, CN5
-
-        .if $isdefed("DEBUG_CODE")
-         SBBO    &CN5, OUT_SAMP_BUF_REG, 4, 4
-        .endif
-
-        ;For the current channel, compare against the High threshold, Low threshold and ZC thresholds (if enabled)
-        ;Load the positive threshold value for current channel
-        LBBO    &OC_HIGH_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_HIGH_THR_CH1_OFFSET, FW_REG_SDFM_CFG_OC_HIGH_THR_SZ
-        ;Load the positive threshold value for current channel
-        LBBO    &OC_LOW_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_LOW_THR_CH1_OFFSET, FW_REG_SDFM_CFG_OC_LOW_THR_SZ
-        ;Load the zero crossing threshold value for current channel
-        LBBO    &OC_ZC_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_ZC_THR_CH1_OFFSET, FW_REG_SDFM_CFG_ZC_THR_SZ
-
-        ;Check if the comparator is enabled for current channel
-        LBBO    &COMPARATOR_EN, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_SD_EN_COMP_OFFSET, FW_REG_SDFM_CFG_EN_COMP_SZ
-        QBBC    comp_ch1_end, COMPARATOR_EN, SDFM_CFG_BF_SD_CH1_EN_COMP_BIT
-        ;Check if the sample value is greater than the high threshold
-        QBGE    over_threshold_start_ch1, OC_HIGH_THR, TREG2
-        ;Check if the sample value is lower than the high threshold
-        QBLE    over_threshold_end_ch1, OC_HIGH_THR, TREG2
-low_threshold_ch1_check:
-        ;Check if the sample value is greater than the low threshold
-        QBGE    below_threshold_end_ch1, OC_LOW_THR, TREG2
-        ;Check if the sample value is lower than the low threshold
-        QBLE    below_threshold_start_ch1, OC_LOW_THR, TREG2
-over_threshold_start_ch1:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        QBA low_threshold_ch1_check
-
-over_threshold_end_ch1:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        QBA low_threshold_ch1_check
-
-below_threshold_end_ch1:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH1_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        QBA     comp_ch1_end
-
-below_threshold_start_ch1:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH1_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-
-comp_ch1_end:
-
-        ; Execute SINC3 differentiation for Ch2
-        MOV     DN0, TREG1 ; DN0 = Ch2 SD HW ACC3 output sample
-        M_ACC3_PROCESS ACC3_DN1_CH2, ACC3_DN3_CH2, ACC3_DN5_CH2
-
-
-        ;Comparator for ch2
-        MOV     TREG2, CN5
-
-        .if $isdefed("DEBUG_CODE")
-        SBBO    &CN5, OUT_SAMP_BUF_REG, 8, 4
-        .endif
-
-        ;For the current channel, compare against the High threshold, Low threshold and ZC thresholds (if enabled)
-        ;Load the positive threshold value for current channel
-        LBBO    &OC_HIGH_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_HIGH_THR_CH2_OFFSET, FW_REG_SDFM_CFG_OC_HIGH_THR_SZ
-        ;Load the positive threshold value for current channel
-        LBBO    &OC_LOW_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_LOW_THR_CH2_OFFSET, FW_REG_SDFM_CFG_OC_LOW_THR_SZ
-        ;Load the zero crossing threshold value for current channel
-        LBBO    &OC_ZC_THR, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_OC_ZC_THR_CH2_OFFSET, FW_REG_SDFM_CFG_ZC_THR_SZ
-
-        ;Check if the comparator is enabled for current channel
-        LBBO    &COMPARATOR_EN, SDDF_CFG_BASE_PTR_REG, FW_REG_SDFM_CFG_SD_EN_COMP_OFFSET, FW_REG_SDFM_CFG_EN_COMP_SZ
-        QBBC    comp_ch2_end, COMPARATOR_EN, SDFM_CFG_BF_SD_CH2_EN_COMP_BIT
-        ;Check if the sample value is greater than the high threshold
-        QBGE    over_threshold_start_ch2, OC_HIGH_THR, TREG2
-        ;Check if the sample value is lower than the high threshold
-        QBLE    over_threshold_end_ch2, OC_HIGH_THR, TREG2
-        ;Check if the sample value is greater than the low threshold
-low_threshold_ch2_check:
-        QBGE    below_threshold_end_ch2, OC_LOW_THR, TREG2
-        ;Check if the sample value is lower than the low threshold
-        QBLE    below_threshold_start_ch2, OC_LOW_THR, TREG2
-over_threshold_start_ch2:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        QBA low_threshold_ch2_check
-
-over_threshold_end_ch2:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        QBA low_threshold_ch2_check
-
-below_threshold_end_ch2:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH2_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        QBA comp_ch2_end
-
-below_threshold_start_ch2:
-        LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH2_SET_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-        LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_LOW_THR_CH2_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-comp_ch2_end:
-
-        .if $isdefed("DEBUG_CODE")
-        ;Debug code
-        ; Write local interleaved output samples to Host buffer address
-        LBBO    &TREG3, OUT_SAMP_BUF_REG, 0, ICSSG_NUM_SD_CH_FW*4
-        SBBO    &TREG3,  SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET, ICSSG_NUM_SD_CH_FW*4
-        ; Trigger interrupt
-        LDI     R31.w0, TRIGGER_HOST_SDDF_IRQ
-        .endif
-
-
-
-         .if $isdefed("DEBUG_CODE")
-        ;GPIO LOW
-         LBBO    &GPIO_TGL_ADDR, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_CLR_VAL_ADDR_OFFSET, FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ
-         LBBO    &TREG3, SDDF_CFG_BASE_PTR_REG, SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-         SBBO    &TREG3, GPIO_TGL_ADDR, 0, FW_REG_SDFM_CFG_GPIO_VALUE_SZ
-        .endif
-
-
-        ; Save/restore context
-        ; save differentiator state(R9-R17)
-        xchg    BANK_CTXT_OC, &R9, 4*NUM_REGS_DIFF_STATE
-
-
-
-        XIN     TM_YIELD_XID, &R0.b3,1  ; exit task after two instructions/cycles
-        NOP
-        NOP
-
-;
-; Initialize Task Manager
-;
-tm_init:
-; Configure Task Manager tasks
-;
-        ; TM general purpose mode
-        ; Enable  T1_S1: IEP0 CMP4 task
-        LDI     TREG0.b0, (1b<<3|0b<<2|11b<<0)           ; enable  T1_s1
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_TM, 0, 1
-
-        ;set T1_S1 address
-        LDI     TREG0.w0, $CODE(ts1_oc_loop)
-        SBCO    &TREG0.w0, CT_PRU_ICSSG_TM, TASKS_MGR_TS1_PC_S1, 2
-
-        ; Set Task triggers
-        ; set T1_S1 trigger to IEP0 CMP4 event = 20
-        LDI     TREG0.w0, (COMP4_EVENT_NUMBER<<COMP_EVENT_FOUR_SIFT)
-        SBCO    &TREG0.w0, CT_PRU_ICSSG_TM, TASKS_MGR_TS1_GEN_CFG1, 2
-
-        JMP     RET_ADDR_REG
-
-
-; Initialize IEP0.
-;
-iep0_init:
-        ; Disable IEP0 counter
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1
-        AND     TREG0.b0, TREG0.b0, 0xFE
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1
-
-        ; Set IEP0 counter to zero
-        LDI     TREG0, 0
-        SBCO    &TREG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_COUNT_REG1, 4
-        SBCO    &TREG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_COUNT_REG0, 4
-
-        ; Clear IEP0  CMP4 events
-        LDI		TREG0.b0, 0x10
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_STATUS_REG, 1
-
-        ; Write IEP0 default increment
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1
-        AND     TREG0.b0, TREG0.b0, 0x0F
-        OR      TREG0.b0, TREG0.b0, IEP_DEFAULT_INC<<DEFAULT_INC_BN
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1
-
-        ;Enable IEP0 counter on EPWM0 SYNC0 event
-
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0_0x100, ICSSG_IEP_PWM_REG, 1
-        SET     TREG0.b0.t0 ; IEP_PWM_REG:PWM0_RST_CNT_EN = 1, enable IEP0 counter reset on EPWM0 SYNCO event
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0_0x100, ICSSG_IEP_PWM_REG, 1
-
-
-        ; Initialize Trigger sample time for OC
-        ; Set IEP0 CMP4 value: IEP0_CMP4_REG1:REG0 = 0:TRIG_SAMPLE_TIME
-        LDI     TREG0, 0
-        SBCO    &TREG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG1, 4
-        LBCO    &TREG0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME, FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_SZ
-        LDI     TREG1, SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_MASK
-        AND     TREG0, TREG1, TREG0
-        SUB     TREG0, TREG0, IEP_DEFAULT_INC ; subtract IEP default increment since IEP counts 0...CMP0
-        SBCO    &TREG0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP4_REG0, 4
-        ; Enable IEP0 CMP4
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_CFG_REG, 1  ; TR0 <- Byte0 ICSSG_CMP_CFG_REG
-        SET     TREG0.t5    ; CMP_EN[5]=1 => CMP4 enabled
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_CMP_CFG_REG, 1  ; TR0 -> ICSSG_CMP_CFG_REG Byte0
-
-
-
-        JMP     RET_ADDR_REG
-
-
-;
-; Reset SDDF state
-;
-; Arguments: None
-;
-reset_sddf_state:
-        ZERO    &R9, (4*NUM_REGS_DIFF_STATE)
-        XOUT    BANK_CTXT_OC, &R9, (4*NUM_REGS_DIFF_STATE);clear OC  differentiator state
-
-        XOUT    BANK_CTXT_NC, &R9, (4*NUM_REGS_DIFF_STATE) ;clear NC  differentiator state
-        JMP     RET_ADDR_REG
-
-
-;
-; Configure OC Over Sampling Rate for SD channels
-;
-; Arguments:
-;   SDDF_CFG_BASE_PTR_REG: base address of SD Configuration registers (&IEP_CFG_EPWM_PRD)
-;   SD_HW_BASE_PTR_REG: base address of SD HW configuration registers (&ICSSG_PRUn_SD_CLK_SEL_REG0)
-;
-config_oc_osr:
-
-        ; Load TR1.w0 <- SDDF_CFG_SD_CH_ID = ;LDI      TREG1.w0, 0x210 =001100010000
-
-        LBBO    &TREG1.w0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ
-
-        LOOP    config_osr_loop_end, ICSSG_NUM_SD_CH_FW ; loop over SD channels
-        AND     TREG2.b0, TREG1.b0, BF_SD_CH0_ID_MASK   ; LS byte is ID for Ch0
-        QBNE            SDFM_SKIP0_CH0, TREG2.b0,	0
-        ; Load TR0.b0 <- FW_REG_SDDF_CFG_OSR load osr from DMEM for ch0
-        LBBO    &TREG0.b0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH0_OSR_OFFSET, FW_REG_SDDF_CFG_OSR_SZ
-        JMP    SDFM_SKIP0_CH2
-SDFM_SKIP0_CH0:
-        QBNE            SDFM_SKIP0_CH1, TREG2.b0,	1
-        ; Load TR0.b0 <- FW_REG_SDDF_CFG_OSR load osr from DMEM for ch1
-        LBBO    &TREG0.b0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH1_OSR_OFFSET, FW_REG_SDDF_CFG_OSR_SZ
-        JMP    SDFM_SKIP0_CH2
-SDFM_SKIP0_CH1:
-        QBNE            SDFM_SKIP0_CH2, TREG2.b0,	2
-        ; Load TR0.b0 <- FW_REG_SDDF_CFG_OSR load osr from DMEM for ch2
-        LBBO    &TREG0.b0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH2_OSR_OFFSET, FW_REG_SDDF_CFG_OSR_SZ
-SDFM_SKIP0_CH2:
-
-        LSL     TREG2, TREG2, 3                         ; (ChID*8) bytes to Byte0 PRUn_SD_SAMPLE_SIZE_REG(ChID)
-        ADD     TREG2, TREG2, 4                         ; 4 bytes added for Byte0 PRUn_SD_SAMPLE_SIZE_REG0
-
-        SBBO    &TREG0.b0, SD_HW_BASE_PTR_REG, TREG2, 1 ; TR0.b0 -> PRUn_SD_SAMPLE_SIZE_REG(ChID)
-        LSR     TREG1, TREG1, 4                         ; LS byte is ID for Ch(i+1) ; FL fix me
-config_osr_loop_end:
-
-        JMP     RET_ADDR_REG
-
-
-;
-; Configure SD channels. For SD channels, initialize:
-;   ACC select = ACC3
-;   Clock inversion
-;   Clock source: pr1_pru<n>_pru_r31_in[16] Primary Input
-;
-;   SDDF_CFG_BASE_PTR_REG: base address of SD Configuration registers (&IEP_CFG_EPWM_PRD)
-;   SD_HW_BASE_PTR_REG: base address of SD HW configuration registers (&ICSSG_PRUn_SD_CLK_SEL_REG0)
-;
-config_sd_ch:
-        ; Load TR1.w0 <- SDDF_CFG_SD_CH_ID ;LDI      TREG1.w0, 0x210 =001100010000
-
-        LBBO    &TREG1.w0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ
-
-        LOOP    config_sd_ch_loop_end, ICSSG_NUM_SD_CH_FW   ; loop over SD channels
-        AND     TREG2.b0, TREG1.b0, BF_SD_CH0_ID_MASK       ; LS byte is ID for Chi
-        QBNE            SDFM_SKIP1_CH0, TREG2.b0,	0
-        ; Select clock inversion
-        LDI     TREG0.w0, 0;
-        LBBO    &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH0_CLOCK_INVERSION_OFFSET, 1
-        LSL     TREG0.b2, TREG0.b2, PRUn_SD_CLK_INVi_SHIFT
-        AND     TREG0.b0, TREG0.b2, PRUn_SD_CLK_INVi_MASK<<PRUn_SD_CLK_INVi_SHIFT   ; TR1.b2 = SD_CLK_INV
-
-        ; select clock source
-        LBBO    &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH0_CLOCK_SOURCE_OFFSET, 1
-        LSL     TREG0.b2, TREG0.b2, PRUn_SD_CLK_SELi_SHIFT
-        AND     TREG0.b2, TREG0.b2, PRUn_SD_CLK_SELi_MASK<<PRUn_SD_CLK_SELi_SHIFT
-        OR      TREG0.b0, TREG0.b0, TREG0.b2
-
-        ; select to ACC source
-        LBBO    &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH0_FILTER_TYPE_OFFSET, 1
-        LSL     TREG0.b2, TREG0.b2, PRUn_SD_ACC_SELi_SHIFT
-        AND     TREG0.b2, TREG0.b2, PRUn_SD_ACC_SELi_MASK<<PRUn_SD_ACC_SELi_SHIFT
-        OR      TREG0.b0, TREG0.b0, TREG0.b2
-        JMP    SDFM_SKIP1_CH2
-SDFM_SKIP1_CH0:
-        QBNE            SDFM_SKIP1_CH1, TREG2.b0,	1
-        ; Select clock inversion
-        LDI     TREG0.w0, 0;
-        LBBO    &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH1_CLOCK_INVERSION_OFFSET, 1
-        LSL     TREG0.b2, TREG0.b2, PRUn_SD_CLK_INVi_SHIFT
-        AND     TREG0.b0, TREG0.b2, PRUn_SD_CLK_INVi_MASK<<PRUn_SD_CLK_INVi_SHIFT   ; TR1.b2 = SD_CLK_INV
-
-        ; select clock source
-        LBBO    &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH1_CLOCK_SOURCE_OFFSET, 1
-        LSL     TREG0.b2, TREG0.b2, PRUn_SD_CLK_SELi_SHIFT
-        AND     TREG0.b2, TREG0.b2, PRUn_SD_CLK_SELi_MASK<<PRUn_SD_CLK_SELi_SHIFT
-        OR      TREG0.b0, TREG0.b0, TREG0.b2
-
-        ; select to ACC source
-        LBBO    &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH1_FILTER_TYPE_OFFSET, 1
-        LSL     TREG0.b2, TREG0.b2, PRUn_SD_ACC_SELi_SHIFT
-        AND     TREG0.b2, TREG0.b2, PRUn_SD_ACC_SELi_MASK<<PRUn_SD_ACC_SELi_SHIFT
-        OR      TREG0.b0, TREG0.b0, TREG0.b2
-        JMP    SDFM_SKIP1_CH2
-SDFM_SKIP1_CH1:
-        QBNE            SDFM_SKIP1_CH2, TREG2.b0,	2
-        ; Select clock inversion
-        LDI     TREG0.w0, 0;
-        LBBO    &TREG0.w1, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH2_CLOCK_INVERSION_OFFSET, 1
-        LSL     TREG0.b2, TREG0.b2, PRUn_SD_CLK_INVi_SHIFT
-        AND     TREG0.b0, TREG0.b2, PRUn_SD_CLK_INVi_MASK<<PRUn_SD_CLK_INVi_SHIFT   ; TR1.b2 = SD_CLK_INV
-
-        ; select clock source
-        LBBO    &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH2_CLOCK_SOURCE_OFFSET, 1
-        LSL     TREG0.b2, TREG0.b2, PRUn_SD_CLK_SELi_SHIFT
-        AND     TREG0.b2, TREG0.b2, PRUn_SD_CLK_SELi_MASK<<PRUn_SD_CLK_SELi_SHIFT
-        OR      TREG0.b0, TREG0.b0, TREG0.b2
-
-        ; select to ACC source
-        LBBO    &TREG0.w2, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_CH2_FILTER_TYPE_OFFSET, 1
-        LSL     TREG0.b2, TREG0.b2, PRUn_SD_ACC_SELi_SHIFT
-        AND     TREG0.b2, TREG0.b2, PRUn_SD_ACC_SELi_MASK<<PRUn_SD_ACC_SELi_SHIFT
-        OR      TREG0.b0, TREG0.b0, TREG0.b2
-SDFM_SKIP1_CH2:
-       ;configure source clock, clock inversion & ACC source for all connected channels
-        LSL     TREG2, TREG2, 3                             ; (ChID*8) bytes to Byte0 PRUn_SD_CLK_SEL_REG(ChID)
-        ADD     TREG2, TREG2, 0                             ; 0 bytes to Byte0 PRUn_SD_CLK_SEL_REG0
-
-        SBBO    &TREG0.b0, SD_HW_BASE_PTR_REG, TREG2, 1     ; TR0.b0 -> PRUn_SD_CLK_SEL_REGi
-        LSR     TREG1, TREG1, 4                             ; LS byte is ID for Ch(i+1) ; FL fix me
-config_sd_ch_loop_end:
-
-        JMP     RET_ADDR_REG
-
-
-;
-; Reset SD channel hardware
-;
-;   SDDF_CFG_BASE_PTR_REG: base address of SD Configuration registers (&IEP_CFG_EPWM_PRD)
-;
-reset_sd_ch_hw:
-        ; Load T01.w0 <- SDDF_CFG_SD_CH_ID
-        ;LDI    TREG0.w0, 0x210
-        LBBO    &TREG0.w0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CH_ID_OFFSET, FW_REG_SDDF_CFG_SD_CH_ID_SZ
-
-        LOOP    reset_sd_ch_hw_loop_end, ICSSG_NUM_SD_CH_FW ; loop over SD channels
-        AND     TREG1.b0, TREG0.b0, BF_SD_CH0_ID_MASK       ; LS byte is ID for Chi
-
-        ; Set R30[29-26]:channel_select = channel ID.
-        ; Set R30[25]:channel_en=1 (set Global Channel enable).
-        LSL     TREG1.b0, TREG1.b0, 2                       ; TR1.b0 = TR1.b0<<2 = (Ch ID)<<2
-        SET     TREG1.b0.t1                                 ; R30[25] channel_enable=1
-        MOV     R30.b3, TREG1.b0                            ; R30.b3 = TR1.b0
-                                                            ; select SD Channel (Ch ID)
-        LSR     TREG0, TREG0, 4                             ; LS byte is ID for Ch(i+1) ; FL fix me
-        SET     R31.t23                                     ; R31[23] re_init=1
-reset_sd_ch_hw_loop_end:
-
-        JMP     RET_ADDR_REG
-
-
-;
-; Initialize SD (eCAP PWM) clock
-;
-; Arguments:
-;   SDDF_CFG_BASE_PTR_REG: base address of SD Configuration registers (&IEP_CFG_EPWM_PRD)
-;
-init_sd_clock:
-        ; Set eCAP PWM mode
-        LDI32   TREG0, (SYNCI_EN_VAL<<SYNCI_EN_SHIFT) | (SYNCO_SEL_VAL<<SYNCO_SEL_SHIFT) | (CAP_APWM_VAL<<CAP_APWM_SHIFT) | (APWMPOL_VAL<<APWMPOL_SHIFT)
-        SBCO    &TREG0, CT_PRU_ICSSG_ECAP, ICSSG_eCAP_ECCTL1, 4
-
-        ; Load TR0.w0 <- FW_REG_SDDF_CFG_SD_CLK
-        ; Load PWM devider for SD clock from DMEM
-        LBBO    &TREG0.w0, SDDF_CFG_BASE_PTR_REG, FW_REG_SDDF_CFG_SD_CLK_OFFSET, FW_REG_SDDF_CFG_SD_CLK_SZ
-
-        ; Set period count
-        SUB     TREG1, TREG0.b0, 1  ; TR1 = SD_PRD_CLOCKS - 1
-        SBCO    &TREG1, CT_PRU_ICSSG_ECAP, ICSSG_eCAP_CAP1, 4
-
-        ; Compute & set Duty Cycle count.
-        ; Divide period count by 2, biased rounding.
-        ADD     TREG1, TREG0.b0, 1  ; TR1 = SD_PRD_CLOCKS + 1
-        LSR     TREG1, TREG1, 1     ; TR1 = (SD_PRD_CLOCKS+1)/2
-        SBCO    &TREG1, CT_PRU_ICSSG_ECAP, ICSSG_eCAP_CAP2, 4
-
-        LDI     TREG0, 0x0
-        SBCO    &TREG0, CT_PRU_ICSSG_ECAP, ICSSG_eCAP_CNTPHS, 4 ; clear counter phase
-        SBCO    &TREG0, CT_PRU_ICSSG_ECAP, ICSSG_eCAP_TSCNT, 4  ; reset eCAP PWM Counter
-
-        ; Enable eCAP PWM
-        LBCO    &TREG0, CT_PRU_ICSSG_ECAP, ICSSG_eCAP_ECCTL1, 4
-        SET     TREG0, TREG0, TSCNTSTP_BN   ; ICSSG_ECCTL2_ECCTL1:TSCNTSTP=1
-        SBCO    &TREG0, CT_PRU_ICSSG_ECAP, ICSSG_eCAP_ECCTL1, 4
-
-        JMP     RET_ADDR_REG
--- a/source/current_sense/sdfm/firmware/sddf_cfg.h
+++ b/source/current_sense/sdfm/firmware/sddf_cfg.h
@ -1,119 +0,0 @@
-;
-; sddf_cfg.h
-;
-; Copyright (c) 2023, Texas Instruments Incorporated
-; All rights reserved.
-;
-;  Redistribution and use in source and binary forms, with or without
-;  modification, are permitted provided that the following conditions
-;  are met:
-;
-;  *  Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;
-;  *  Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;
-;  *  Neither the name of Texas Instruments Incorporated nor the names of
-;     its contributors may be used to endorse or promote products derived
-;     from this software without specific prior written permission.
-;
-;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-;  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-;  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-;  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-;  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-;  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-;  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-;  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-;  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-;  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-
-        .if !$defined("__sddf_cfg_h")
-__sddf_cfg_h    .set    1
-
-        .cdecls C,NOLIST
-%{
-        #include "icssg_sddf.h"
-%}
-
-;
-; Symbolic constants for FW configuration
-;
-
-; Provided by compiler
-;SDDF_PRU_CORE                   .set 1 ; build code for PRUn
-;SDDF_RTU_CORE                   .set 1 ; build code for RTUn
-
-; SDDF_CTRL & SDDF_STAT
-SDDF_EN                         .set BF_SDDF_EN_ENABLE
-PRU_ID                          .set BF_PRU_ID_0
-SDDF_EN_ACK                     .set BF_SDDF_EN_DISABLE
-PRU_ID_ACK                      .set BF_PRU_ID_UNINIT
-
-; IEP_CFG
-IEP_DEFAULT_INC                 .set 0x1
-
-; IEP_CFG_EPWM_PRD
-CMP0_CNT_EPWM_PRD               .set 0x927C
-
-; SDDF_CFG_SD_CH_ID
-    .if $isdefed("SDDF_RTU_CORE")
-; Load Sharing: RTUn
-SD_CH0_ID                       .set 0000b
-SD_CH1_ID                       .set 0001b
-SD_CH2_ID                       .set 0010b
-    .elseif $isdefed("SDDF_PRU_CORE")
-; Load Sharing: PRUn
-;SD_CH0_ID                       .set 0011b
-;SD_CH1_ID                       .set 0100b
-;SD_CH2_ID                       .set 0101b
-SD_CH0_ID                       .set 0000b
-SD_CH1_ID                       .set 0001b
-SD_CH2_ID                       .set 0010b
-    .elseif $isdefed("SDDF_TX_PRU_CORE")
-; Load Sharing: TX_PRUn
-SD_CH0_ID                       .set 0110b
-SD_CH1_ID                       .set 0111b
-SD_CH2_ID                       .set 1000b
-    .endif
-
-; SDDF_CFG_SD_CLK
-;SD_CLK_INV                      .set 0b
-;SD_PRD_CLOCKS                   .set 0x0F
-
-; SDDF_CFG_OSR
-;OC_OSR                          .set 0x0D
-;OC_OSR                          .set 0x0E
-
-; SDDF_CFG_OC_POS_THR
-;OC_POS_THR                      .set 0x0AB8
-
-; SDDF_CFG_OC_NEG_THR
-;OC_NEG_THR                      .set 0x0001
-
-; SDDF_CFG_TRIG_SAMP_TIME
-;TRIG_SAMP_TIME                  .set 0x439E
-
-; SDDF_CFG_TRIG_SAMP_CNT
-;TRIG_SAMP_CNT                   .set 0x0003
-
-; SDDF_CFG_NC_PRD_IEP_CNT
-;NC_PRD_IEP_CNT                  .set 0x03C0
-
-; SDDF_CFG_OUT_SAMP_BUF
-    .if $isdefed("SDDF_RTU_CORE")
-; Load Sharing: RTUn
-;NC_OUT_SAMP_BUF                 .set 0x78100000 ; R5F_0_0 BTCM, SoC view
-    .elseif $isdefed("SDDF_PRU_CORE")
-; Load Sharing: PRUn
-;NC_OUT_SAMP_BUF                 .set 0x7810000C ; R5F_0_0 BTCM, SoC view
-    .elseif $isdefed("SDDF_TX_PRU_CORE")
-; Load Sharing: TX_PRUn
-;NC_OUT_SAMP_BUF                 .set 0x78100018 ; R5F_0_0 BTCM, SoC view
-    .endif
-
-    .endif  ; __sddf_cfg_h
--- a/source/current_sense/sdfm/firmware/sdfm.asm
+++ b/source/current_sense/sdfm/firmware/sdfm.asm
--- a/source/current_sense/sdfm/firmware/sdfm.h
+++ b/source/current_sense/sdfm/firmware/sdfm.h
@ -1,5 +1,5 @@
 ;
-; sddf.h
+; sdfm.h
 ;
 ; Copyright (c) 2023, Texas Instruments Incorporated
 ; All rights reserved.
@ -32,8 +32,8 @@
 ;  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;

-        .if !$defined("__sddf_h")
-__sddf_h    .set    1
+        .if !$defined("__sdfm_h")
+__sdfm_h    .set    1

 ;
 ; Substitution symbols
@ -47,35 +47,34 @@ __sddf_h    .set    1
        .asg    C11, CT_PRU_ICSSG_CTRL          ; Constant Table, PRU Control
        .asg    C24, CT_PRU_ICSSG_LOC_DMEM      ; Constant Table, local PRU DMEM
        .asg    C26, CT_PRU_ICSSG_IEP0          ; Constant Table, PRU_ICSSG IEP0
+	    .asg	CT_PRU_ICSSG_LOC_DMEM,		PRUx_DMEM  ;DMEM base address

-        .asg    R1, TREG0                       ; temporary register 0
-        .asg    R2, TREG1                       ; temporary register 1
-        .asg    R3, TREG2                       ; temporary register 2
-        .asg    R4, TREG3                       ; temporary register 3
+        .asg    R1, TEMP_REG0                       ; temporary register 0
+        .asg    R2, TEMP_REG1                       ; temporary register 1
+        .asg    R3, TEMP_REG2                       ; temporary register 2
+        .asg    R4, TEMP_REG3                       ; temporary register 3

-        .asg    R23, SDDF_CFG_BASE_PTR_REG      ; SDDF CFG FW registers base pointer register
+        .asg    R23, SDFM_CFG_BASE_PTR_REG      ; SDFM CFG FW registers base pointer register
        .asg    R24, SD_HW_BASE_PTR_REG         ; SD hardware base pointer register
        .asg    R25.w0, RET_ADDR_REG            ; function return register

        .asg    R5, DN0                         ; SD integrator 3 (ACC3) output
-        .asg    R6, CN3                         ; SDDF differentiator 1 output
-        .asg    R7, CN4                         ; SDDF differentiator 2 output
-        .asg    R8, CN5                         ; SDDF differentiator 3 output
+        .asg    R6, CN3                         ; SDFM differentiator 1 output
+        .asg    R7, CN4                         ; SDFM differentiator 2 output
+        .asg    R8, CN5                         ; SDFM differentiator 3 output
        .asg    R21, MASK_REG                    ; integrator & differentiator output mask
-        .asg    R22.w2, SAMP_CNT_REG             ; NC sample count

        .asg    R26.w0, COMPARATOR_EN           ; SD comparator enable for different channels
        .asg    R26.w2, ZERO_CROSS_EN           ; SD Zero Crossing enable for different channels
        .asg    R19, OC_HIGH_THR              ; SD OC High threshold
        .asg    R27, OC_LOW_THR              ; SD OC Low threshold
-        .asg    R29, OC_ZC_THR                ; SD zero crosssing threshold

-        .asg    R18, GPIO_TGL_ADDR              ; Address to write to for the GPIO toggle

-        .asg    R28, CURRENT_COMP4_REG_VALUE     ; Current Cmp4 register value
+        .asg    R29, GPIO_TGL_ADDR              ; Address to write to for the GPIO toggle

-        .asg    R1, T0_CTXT_BASE_REG            ; base PRU register for T0 context
-        .asg    R9, T1_S0_CTXT_BASE_REG         ; base PRU register for T1_S0 context
+
+       .asg    R1, T0_CTXT_BASE_REG            ; base PRU register for T0 context
+    .asg    R9, T1_S0_CTXT_BASE_REG         ; base PRU register for T1_S0 context

        .asg    R9, ACC3_DN1_CH0                ; Ch X (0...8), differentiator 1 state
        .asg    R10, ACC3_DN3_CH0               ; Ch X (0...8), differentiator 2 state
@ -87,10 +86,26 @@ __sddf_h    .set    1
        .asg    R16, ACC3_DN3_CH2               ; CH Z (0...8), differentiator 2 state
        .asg    R17, ACC3_DN5_CH2               ; CH Z (0...8), differentiator 3 state

-        .asg    R22.w0, SD_CH_ID                ; SD channel IDs
+        .asg    R22.b0, SD_CH0_ID                ; SD channel0 ID
+        .asg    R22.b1, SD_CH1_ID                ; SD Channel1 ID
+        .asg    R22.b2, SD_CH2_ID                ; SD Channel2 ID

        .asg    R20, OUT_SAMP_BUF_REG           ; address of local interleaved NC output sample buffer

+        .asg    R28.b0,  SAMP_CNT_REG             ; NC sample count
+        .asg    R28.b1,  SAMP_NAME                ; First/second sample number
+        .asg    R28.b2,  NC_OUTPUT_SAMP         ;
+        .asg    R28.b3,  EN_DOUBLE_UPDATE
+
+;Fast detect registers(using only in SDFM init)
+
+        .asg R19.b0,  FAST_TZ_OUT_REG
+        .asg R19.b1,  FAST_window_REG
+        .asg R19.b2,  FAST_ONE_max_REG
+        .asg R19.b3,  FAST_ONE_min_REG
+        .asg R27.b0,  FAST_ZERO_max_REG
+        .asg R27.b1,  FAST_ZERO_min_REG
+

 ;
 ; Symbolic constants for ICSSG/PRU HW
@ -122,6 +137,8 @@ NONE_HINT_BIT                   .set 31                 ; ICSSG_PRI_HINT_REG:NON
 ICSSG_CNTLSELF_BASE             .set 0
 PRUx_CNTL_CONST_IDX0_OFFSET     .set 0x0020         ;  Constant Table Block Index Reg 0
 PRUx_CNTLSELF_CONST_IDX0_REG    .set (ICSSG_CNTLSELF_BASE + PRUx_CNTL_CONST_IDX0_OFFSET)
+
+
 ; ICSSG_PRU_CTBIR0:C24_BLK_INDEX, PRU Constant Entry C24 Block Index
 C24_BLK_INDEX_FW_REGS_VAL       .set 0
 C24_BLK_INDEX_OUT_SAMP_BUF_VAL  .set 8
@ -134,6 +151,7 @@ ICSSG_CFG_GPCFG1                .set 0x000C ;  GP IO Configuration Register 1
 ICSSG_CFG_SPPC                  .set 0x0034 ;  Scratch PAD priority and config
 ICSSG_CFG_PRU0_SD0_CLK          .set 0x48
 ICSSG_CFG_PRU1_SD0_CLK          .set 0x94
+ICSSG_CFG_PWM1                   .set 0x134 ; PWM1 trip generation configuration

 ;
 ; ICSSG_GPCFGn_REG:PR1_PRUn_GP_MUX_SEL, Controls the icss_wrap mux sel
@ -255,4 +273,7 @@ TASKS_MGR_TS1_GEN_CFG1          .set 0x38

 TM_YIELD_XID                    .set 252

-    .endif  ; __sddf_h
+;IEP_CFG
+IEP_DEFAULT_INC                 .set 0x1
+
+    .endif  ; __sdfm_h
--- a/source/current_sense/sdfm/firmware/sdfm_bin.h
+++ b/source/current_sense/sdfm/firmware/sdfm_bin.h
@ -1,4 +1,4 @@
-const uint32_t pru_SDDF_PRU0_image_0[] = {
+const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x2effbd80,
 0x32000000,
 0x240fff81,
@ -10,21 +10,7 @@ const uint32_t pru_SDDF_PRU0_image_0[] = {
 0x81200b01,
 0x10000000,
 0x91001801,
-0x11060101,
-0x24000402,
-0x04020103,
-0x570003fc,
-0x91011802,
-0x11060203,
-0x50030106,
-0x24000603,
-0x16000303,
-0x10030202,
-0x12010202,
-0x81011802,
-0x91001801,
-0xcf0001f2,
-0x91011801,
+0xcf0001ff,
 0x1f00e1e1,
 0x81011801,
 0x91340401,
@ -35,50 +21,166 @@ const uint32_t pru_SDDF_PRU0_image_0[] = {
 0x23010499,
 0x240c00c2,
 0x24000082,
-0x91001801,
-0xd101e103,
+0x91021801,
+0x51010103,
 0x81082482,
 0x79000002,
 0x810c2482,
-0x23011e99,
-0x240002f7,
-0x91001801,
-0xd101e104,
+0x91021801,
+0x51010104,
 0x240002d8,
 0x24604898,
 0x79000003,
 0x240002d8,
 0x24609498,
-0x23016c99,
+0x91103881,
+0x110fe1e2,
+0x10020216,
+0x0b04e1e1,
+0x110fe1e2,
+0x10020236,
+0x0b04e1e1,
+0x110fe1e2,
+0x10020256,
+0x23011e99,
+0x23016e99,
 0x23012299,
-0x23013299,
-0x23016399,
+0x23013399,
+0x23016599,
 0x1f19fefe,
 0x240fffd5,
 0x24ffff95,
 0x240000d4,
-0x24010094,
-0x240000d6,
+0x24020094,
+0x2400001c,
+0x91e8187c,
+0x2400003c,
 0x91001a01,
 0x1f00e1e1,
 0x81001a01,
-0xf10e3796,
-0x21004000,
-0x2f859189,
+0x9114189a,
+0xd1009a02,
+0x21003d00,
+0xc9019a26,
+0x10161602,
+0x09020202,
+0x1f010202,
+0x1002027e,
+0x10000000,
+0xc91cff20,
+0x1f18ffff,
+0x10f5ffe5,
+0x0ce5e9e6,
+0x10e5e5e9,
+0x0ce6eae7,
+0x10e6e6ea,
+0x0ce7ebe8,
+0x10e7e7eb,
+0x10f5e8e8,
+0x10e8e8e3,
+0x91203893,
+0x9124389b,
+0x70e3f304,
+0x58e3f307,
+0x70e3fb0a,
+0x58e3fb0d,
+0x9140389d,
+0x913c3884,
+0xe1003d84,
+0x7f0000fb,
+0x9144389d,
+0x913c3884,
+0xe1003d84,
+0x7f0000f7,
+0x9150389d,
+0x91483884,
+0xe1003d84,
+0x79000004,
+0x914c389d,
+0x91483884,
+0xe1003d84,
+0xc9029a26,
+0x10363602,
+0x09020202,
+0x1f010202,
+0x1002027e,
+0x10000000,
+0xc91cff20,
+0x1f18ffff,
+0x10f5ffe5,
+0x0ce5ece6,
+0x10e5e5ec,
+0x0ce6ede7,
+0x10e6e6ed,
+0x0ce7eee8,
+0x10e7e7ee,
+0x10f5e8e8,
+0x10e8e8e3,
+0x91643893,
+0x9168389b,
+0x70e3f304,
+0x58e3f307,
+0x70e3fb0a,
+0x58e3fb0d,
+0x9184389d,
+0x91803884,
+0xe1003d84,
+0x7f0000fb,
+0x9188389d,
+0x91803884,
+0xe1003d84,
+0x7f0000f7,
+0x9194389d,
+0x918c3884,
+0xe1003d84,
+0x79000004,
+0x9190389d,
+0x918c3884,
+0xe1003d84,
+0xc9039a26,
+0x10565682,
+0x09020202,
+0x1f010202,
+0x1002027e,
+0x10000000,
+0xcf1cffae,
+0x1f18ffff,
+0x10f5ffe5,
+0x0ce5efe6,
+0x10e5e5ef,
+0x0ce6f0e7,
+0x10e6e6f0,
+0x0ce7f1e8,
+0x10e7e7f1,
+0x10f5e8e8,
+0x10e8e8e3,
+0x91a83893,
+0x91ac389b,
+0x70e3f304,
+0x58e3f307,
+0x70e3fb0a,
+0x58e3fb0d,
+0x91c8389d,
+0x91c43884,
+0xe1003d84,
+0x7f0000fb,
+0x91cc389d,
+0x91c43884,
+0xe1003d84,
+0x7f0000f7,
+0x91d8389d,
+0x91d03884,
+0xe1003d84,
+0x79000004,
+0x91d4389d,
+0x91d03884,
+0xe1003d84,
+0x7f00008e,
+0x24000000,
+0x107e7e12,
+0x2f852381,
 0x24001001,
 0x81741a01,
-0x240000e1,
-0x91ec1881,
-0x91983a82,
-0x10e2e2fc,
-0x00e1e2e1,
-0x240000e2,
-0x91081882,
-0x58e2e103,
-0x81983a81,
-0x21005000,
-0x04e2e1e1,
-0x81983a81,
 0x240260de,
 0x10000000,
 0x11ffffe2,
@ -86,7 +188,7 @@ const uint32_t pru_SDDF_PRU0_image_0[] = {
 0x56e2e3ff,
 0x1d15fefe,
 0x10000000,
-0x10f5ffe1,
+0x10f5ffe5,
 0x1d16fefe,
 0x240640de,
 0x10000000,
@ -96,14 +198,6 @@ const uint32_t pru_SDDF_PRU0_image_0[] = {
 0x10000000,
 0x10f5ffe3,
 0x1d16fefe,
-0x240000e4,
-0xf1ee1784,
-0x0501e4e4,
-0x58e4d603,
-0x0101d6d6,
-0x7900002e,
-0x2f851189,
-0x10e1e1e5,
 0x0ce5e9e6,
 0x10e5e5e9,
 0x0ce6eae7,
@ -130,131 +224,37 @@ const uint32_t pru_SDDF_PRU0_image_0[] = {
 0x10e7e7f1,
 0x10f5e8e8,
 0xe1083488,
-0x91e83884,
-0x58e4fc06,
-0x04fce4fc,
-0x91ee1884,
-0x0b01e4e4,
-0x70fce40a,
-0x79000006,
-0x04e4fcfc,
-0x91ee1884,
-0x0b01e4e4,
-0x58e4fc05,
-0x79000001,
+0x59031c07,
+0x91f43881,
+0x91983a82,
+0x00e1e2e1,
+0x81983a81,
+0x01011c1c,
+0x79000010,
+0xd1003c07,
+0xc9007c06,
+0x91f03881,
+0x0501e1e1,
+0x81983a81,
+0x2400013c,
+0x79000005,
+0x91ec3881,
+0x0501e1e1,
+0x81983a81,
+0x2400003c,
+0x2400001c,
 0xf100b484,
-0xe1f2b784,
+0x81f8b884,
 0x2400229f,
-0x2f851189,
-0x240000d6,
-0x10e1e1e5,
-0x10e2e2e1,
-0x10e3e3e2,
-0x0ce5e9e6,
-0x10e5e5e9,
-0x0ce6eae7,
-0x10e6e6ea,
-0x0ce7ebe8,
-0x10e7e7eb,
-0x10f5e8e8,
-0x10e8e8e3,
-0xf11e1793,
-0xf122179b,
-0xf126379d,
-0xf112179a,
-0xc9009a14,
-0x70e3f304,
-0x58e3f307,
-0x70e3fb0a,
-0x58e3fb0d,
-0xf13e3792,
-0xf13a3784,
-0xe1003284,
-0x7f0000fb,
-0xf1423792,
-0xf13a3784,
-0xe1003284,
-0x7f0000f7,
-0xf14e3792,
-0xf1463784,
-0xe1003284,
-0x79000004,
-0xf14a3792,
-0xf1463784,
-0xe1003284,
-0x10e1e1e5,
-0x0ce5ece6,
-0x10e5e5ec,
-0x0ce6ede7,
-0x10e6e6ed,
-0x0ce7eee8,
-0x10e7e7ee,
-0x10f5e8e8,
-0x10e8e8e3,
-0xf1621793,
-0xf166179b,
-0xf16a379d,
-0xf112179a,
-0xc9019a14,
-0x70e3f304,
-0x58e3f307,
-0x70e3fb0a,
-0x58e3fb0d,
-0xf1823792,
-0xf17e3784,
-0xe1003284,
-0x7f0000fb,
-0xf1863792,
-0xf17e3784,
-0xe1003284,
-0x7f0000f7,
-0xf1923792,
-0xf18a3784,
-0xe1003284,
-0x79000004,
-0xf18e3792,
-0xf18a3784,
-0xe1003284,
-0x10e2e2e5,
-0x0ce5efe6,
-0x10e5e5ef,
-0x0ce6f0e7,
-0x10e6e6f0,
-0x0ce7f1e8,
-0x10e7e7f1,
-0x10f5e8e8,
-0x10e8e8e3,
-0xf1a61793,
-0xf1aa179b,
-0xf1ae379d,
-0xf112179a,
-0xc9029a14,
-0x70e3f304,
-0x58e3f307,
-0x70e3fb0a,
-0x58e3fb0d,
-0xf1c63792,
-0xf1c23784,
-0xe1003284,
-0x7f0000fb,
-0xf1ca3792,
-0xf1c23784,
-0xe1003284,
-0x7f0000f7,
-0xf1d63792,
-0xf1ce3784,
-0xe1003284,
-0x79000004,
-0xf1d23792,
-0xf1ce3784,
-0xe1003284,
-0x2f859189,
+0x24000000,
+0x2f852381,
+0x1012127e,
 0x2efe0060,
 0x10000000,
 0x10000000,
 0x24000b01,
 0x81000a01,
-0x24004181,
+0x2400b181,
 0x810c0a81,
 0x24140081,
 0x81380a81,
@ -276,7 +276,7 @@ const uint32_t pru_SDDF_PRU0_image_0[] = {
 0x81080801,
 0x240000e1,
 0x819c3a81,
-0x91e83881,
+0x91ec3881,
 0x24ffffe2,
 0x10e1e2e1,
 0x0501e1e1,
@ -285,76 +285,78 @@ const uint32_t pru_SDDF_PRU0_image_0[] = {
 0x1f05e1e1,
 0x81701a01,
 0x20990000,
-0x2eff9189,
-0x2f059189,
-0x2f051189,
+0x24000000,
+0x2effa381,
+0x2f052381,
 0x20990000,
-0xf10e3782,
+0x240000e1,
+0x91103882,
 0x3102000e,
 0x110f0203,
-0x69000303,
-0xf11c1701,
-0x21012d00,
-0x69010303,
-0xf1601701,
-0x21012d00,
-0x69020302,
-0xf1a41701,
+0x68160303,
+0x911e1801,
+0x21012e00,
+0x68360303,
+0x91621801,
+0x21012e00,
+0x68560302,
+0x91a61801,
 0x0903e3e3,
 0x0104e3e3,
-0xe0e31801,
+0xe0e33801,
 0x0b04e2e2,
 0x20990000,
-0xf10e3782,
+0x240000e1,
+0x91103882,
 0x3102002f,
 0x110f0203,
-0x6900030e,
+0x6816030e,
 0x24000081,
-0xf1361741,
+0x91381841,
 0x09024141,
 0x11044101,
-0xf1321741,
+0x91341841,
 0x09004141,
 0x11034141,
 0x12410101,
-0xf11b1741,
+0x911d1841,
 0x09044141,
 0x11304141,
 0x12410101,
-0x21015e00,
-0x6901030e,
+0x21016000,
+0x6836030e,
 0x24000081,
-0xf17a1741,
+0x917c1841,
 0x09024141,
 0x11044101,
-0xf1761741,
+0x91781841,
 0x09004141,
 0x11034141,
 0x12410101,
-0xf15f1741,
+0x91611841,
 0x09044141,
 0x11304141,
 0x12410101,
-0x21015e00,
-0x6902030d,
+0x21016000,
+0x6856030d,
 0x24000081,
-0xf1be1721,
+0x91c01841,
 0x09024141,
 0x11044101,
-0xf1ba1741,
+0x91bc1841,
 0x09004141,
 0x11034141,
 0x12410101,
-0xf1a31741,
+0x91a51841,
 0x09044141,
 0x11304141,
 0x12410101,
 0x0903e3e3,
 0x0100e3e3,
-0xe0e31801,
+0xe0e33801,
 0x0b04e2e2,
 0x20990000,
-0xf10e3781,
+0x91103881,
 0x31020007,
 0x110f0102,
 0x09020202,
@ -366,7 +368,7 @@ const uint32_t pru_SDDF_PRU0_image_0[] = {
 0x240280c1,
 0x24000081,
 0x81282381,
-0xf10a1781,
+0x910c1881,
 0x050101e2,
 0x81082382,
 0x010101e2,
--- a/source/current_sense/sdfm/firmware/sdfm_macros.h
+++ b/source/current_sense/sdfm/firmware/sdfm_macros.h
@ -1,5 +1,5 @@
 ;
-; sddf_macros.h
+; sdfm_macros.h
 ;
 ; Copyright (c) 2023, Texas Instruments Incorporated
 ; All rights reserved.
@ -32,28 +32,30 @@
 ;  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;

-        .if !$defined("__sddf_macros_h")
-__sddf_macros_h .set    1
+        .if !$defined("__sdfm_macros_h")
+__sdfm_macros_h .set    1

-        .include "sddf.h"
+        .include "sdfm.h"

 ;
 ; Macros
 ;
+;

 WRITE_C24_BLK_INDEX .macro blk_index
        ; Set DMEM (C24) block offset
-        LDI     TREG0.b0, blk_index
-        SBCO    &TREG0.b0, CT_PRU_ICSSG_CTRL, PRUx_CNTLSELF_CONST_IDX0_REG, 1
+        LDI     TEMP_REG0.b0, blk_index
+        SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_CTRL, PRUx_CNTLSELF_CONST_IDX0_REG, 1
        NOP ; delay for update to land?
        .endm

+
 ; Set SD HW registers base pointer
 SET_SD_HW_REG_BASE_PTR  .macro  base_ptr
-        ; Load TR0.b0 <- FW_REG_SDDF_CTRL
-        LBCO    &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CTRL, FW_REG_SDDF_CTRL_SZ
+        ; Load TR0.b0 <- FW_REG_SDFM_CTRL
+        LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_LOC_DMEM, SDFM_PRU_ID_OFFSET,  SDFM_PRU_ID_SZ
        ; Check PRU ID 0 or 1
-        QBBS    pru_id1?, TREG0, SDDF_CTRL_BF_PRU_ID_SHIFT
+        QBEQ    pru_id1?, TEMP_REG0.b0, 1
 pru_id0?:
        LDI32   base_ptr, PRUx_CFG_BASE+ICSSG_CFG_PRU0_SD0_CLK
        QBA     set_sd_hw_reg_base_ptr_end?
@ -64,19 +66,19 @@ set_sd_hw_reg_base_ptr_end?:

 ; Configure Triggered mode sample count
 ;CFG_TRIG_MODE_SAMP_CNT  .macro  samp_cnt
-        ; Load samp_cnt <- SDDF_CFG_TRIG_SAMPLE_CNT
-  ;      LBCO    &samp_cnt, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_TRIG_SAMPLE_CNT, FW_REG_SDDF_CFG_TRIG_SAMPLE_CNT_SZ
+        ; Load samp_cnt <- SDFM_CFG_TRIG_SAMPLE_CNT
+  ;      LBCO    &samp_cnt, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDFM_CFG_TRIG_SAMPLE_CNT, FW_REG_SDFM_CFG_TRIG_SAMPLE_CNT_SZ
   ;     .endm

 ; Wait until shadow flag of the channel is set & clear the flag
 ;   args    - ch_idx    : SD channel index {0...ICSSG_NUM_SD_CH-1}
-;;   updates - TREG0.w2  : channel sample buffer offset
+;;   updates - TEMP_REG0.w2  : channel sample buffer offset
 ;
 M_WAIT_SHADOW_FLAG_AND_CLR  .macro  ch_idx
        ; Place ch_idx in R30[29-26], channel_select
-        LSL     TREG1.b0, ch_idx, 2
-        SET     TREG1.b0.t1
-        MOV     R30.b3, TREG1.b0
+        LSL     TEMP_REG1.b0, ch_idx, 2
+        SET     TEMP_REG1.b0.t1
+        MOV     R30.b3, TEMP_REG1.b0
        NOP

 wait_for_shadow_update_cont?:
@ -87,7 +89,7 @@ wait_for_shadow_update_cont?:
        SET     R31, R31.t24
        .endm

-        .endif  ; __sddf_macros_h
+        .endif  ; __sdfm_macros_h

 ; Calculates Sinc3 sample value from ACC3 & Sinc3 variables
 ;   args    - DN1, DN3, DN5 : Sinc3 differntiator state variables
@ -104,3 +106,13 @@ M_ACC3_PROCESS  .macro  DN1, DN3, DN5
        MOV     DN5, CN4
        AND     CN5, CN5, MASK_REG  ; apply limit
        .endm
+
+;Enable task manager
+M_PRU_TM_ENABLE .macro
+    tsen 1
+    .endm
+
+;Disable task manager
+M_PRU_TM_DISABLE .macro
+    tsen 0
+    .endm
--- a/source/current_sense/sdfm/include/sdfm_api.h
+++ b/source/current_sense/sdfm/include/sdfm_api.h
@ -31,15 +31,15 @@
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

-#ifndef _SDDF_API_H_
-#define _SDDF_API_H_
+#ifndef _SDFM_API_H_
+#define _SDFM_API_H_

 #ifdef __cplusplus
 extern "C" {
 #endif

 #include <stdint.h>
-#include "../firmware/icssg_sddf.h"
+#include "../firmware/icssg_sdfm.h"
 #include <current_sense/sdfm/include/sdfm_drv.h>

 /**
@ -124,16 +124,16 @@ void SDFM_setEnableChannel(sdfm_handle h_sdfm, uint8_t channel_number);

 /**
 *
- *  \brief  Configure Accumulator  over sampling ratio
+ *  \brief  Configure comparator filter (over current) sampling ratio
 *
 *  \param[in]  h_sdfm          SDFM handle
 *  \param[in]  ch_id           current ch number
- *  \param[in]  osr             over sampling ratio
+ *  \param[in]  osr             comparator filter/Over current sampling ratio
 *
 *
 *
 */
-void SDFM_setAccOverSamplingRatio(sdfm_handle h_sdfm, uint8_t ch_id, uint8_t osr);
+void SDFM_setCompFilterOverSamplingRatio(sdfm_handle h_sdfm, uint8_t ch_id, uint16_t osr);

 /**
 *
@ -161,15 +161,41 @@ void SDFM_setCompFilterThresholds(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_Thresh

 /**
 *
- *  \brief  configuration of sample read time one Epwm cycle
+ *  \brief  configuration of single sample trigger time one Epwm cycle
 *
 *  \param[in]  h_sdfm          SDFM handle
- *  \param[in] trig_samp_time      sample read time in one pwm cycle
+ *  \param[in] samp_trig_time     first sample trigger time in one pwm cycle
 *
 *
 *
 */
-void SDFM_setSampleReadingTime(sdfm_handle h_sdfm, float trig_samp_time);
+void SDFM_setSampleTriggerTime(sdfm_handle h_sdfm, float samp_trig_time);
+
+/**
+ *
+ *
+ * \brief  configuration and enable second normal current sample starting time one Epwm cycle
+ *
+ *  \param[in]  h_sdfm          SDFM handle
+ *  \param[in] samp_trig_time     second sample trigger time in one PWM cycle
+ *
+ *
+ *
+*/
+void SDFM_enableDoubleSampling(sdfm_handle h_sdfm, float samp_trig_time);
+
+/**
+ *
+ *
+ * \brief  Disable double normal current update/sampling
+ *
+ *  \param[in]  h_sdfm          SDFM handle
+ *
+ *
+ *
+*/
+void SDFM_disableDoubleSampling(sdfm_handle h_sdfm);
+

 /**
 *
@ -250,19 +276,6 @@ void SDFM_configComparatorGpioPins(sdfm_handle h_sdfm, uint8_t ch,uint32_t gpio_
 *
 */
 uint32_t SDFM_getFilterData(uint8_t ch);
-
-/**
- *
- *  \brief  Configure iep count for over current sampling
- *
- *  \param[in]  h_sdfm          SDFM handle
- *  \param[in]  osr             over current osr value
- *
- *
- *
- */
-void SDFM_setCompFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t osr);
-
 /**
 *
 *  \brief  Configure iep count for normal current sampling
@ -273,7 +286,8 @@ void SDFM_setCompFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t osr);
 *
 *
 */
-void SDFM_setFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t nc_osr, uint16_t oc_osr);
+void SDFM_setFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t nc_osr);
+

 /** @} */

--- a/source/current_sense/sdfm/include/sdfm_drv.h
+++ b/source/current_sense/sdfm/include/sdfm_drv.h
@ -31,8 +31,8 @@
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

-#ifndef _SDDF_DRV_H_
-#define _SDDF_DRV_H_
+#ifndef _SDFM_DRV_H_
+#define _SDFM_DRV_H_

 #ifdef __cplusplus
 extern "C" {
@ -111,13 +111,12 @@ extern "C" {
 #define SDFM_RECFG_TRIG_OUT_SAMP_BUF    ( SDFM_RECFG_BF_RECFG_TRIG_OUT_SAMP_BUF_MASK )
 /**    \brief IEP_CFG*/
 #define IEP_DEFAULT_INC                 0x1
-/**    \brief IEP_CFG_EPWM_PRD */
-#define CMP0_CNT_EPWM_PRD               0x927C
+

 /* SDFM output buffer size in 32-bit words */


-#define ICSSG_SD_SAMP_CH_BUF_SZ  128
+#define ICSSG_SD_SAMP_CH_BUF_SZ  ( 128 )
 #define NUM_CH_SUPPORTED        ( 3 )

 /* ========================================================================== */
@ -148,14 +147,14 @@ typedef struct SDFM_CfgSdClk_s
 */
 typedef struct SDFM_CfgTrigger_s
 {
-    /**< time to start sampling after trigger input  */
-    volatile uint32_t trig_samp_time;
-    /**< IEP0 counts in OC sampling period*/
-    volatile uint16_t oc_prd_iep_cnt;
-    /**< IEP0 counts in NC sampling period*/
-    volatile uint16_t nc_prd_iep_cnt;
-    /**< OC Sample count for one NC sample*/
-    volatile uint16_t sample_count;
+    /**< bit-field for enable double update */
+    volatile uint16_t    en_double_nc_sampling;
+    /**< First sample starting point */
+    volatile uint32_t first_samp_trig_time;
+    /**<Second sample starting point*/
+    volatile uint32_t second_samp_trig_time;
+    /**< IEP0 counts in normal current sampling period*/
+    volatile uint32_t nc_prd_iep_cnt;
 } SDFM_CfgTrigger;

 /**
@ -254,10 +253,10 @@ typedef struct SDFM_Cfg_s
    volatile uint8_t    osr;
    /**< sdfm threshold parms*/
    SDFM_ThresholdParms  sdfm_threshold_parms;
-    /**< reserved*/
-    volatile uint8_t    reserved4;
-    /**< reserved*/
-    volatile uint32_t    reserved5;
+    /**< Reserved*/
+    volatile uint32_t    reserved1;
+    /**< reserved */
+    volatile uint8_t    reserved2;
    /**< sdfm ch clock parms*/
    SDFM_ClkSourceParms  sdfm_clk_parms;
    /**< array to store the params for gpio toggle for different channels*/
@ -273,10 +272,12 @@ typedef struct SDFM_Cfg_s
 */
 typedef struct SDFM_Ctrl_s
 {
-    /**< SDFM control */
-    volatile uint8_t  ctrl;
-    /**< SDFM status */
-    volatile uint8_t  stat;
+    /**< SDFM Enable */
+    volatile uint8_t sdfm_en;
+    /**< SDFM Enable Ack */
+    volatile uint8_t  sdfm_en_ack;
+    /**< SDFM PRU ID*/
+    volatile uint8_t  sdfm_pru_id;
 } SDFM_Ctrl;

 typedef struct SDFM_Interface_s{
@ -312,7 +313,7 @@ typedef struct SDFM_s {
 } SDFM;


-#include "sddf_api.h"
+#include "sdfm_api.h"

 #ifdef __cplusplus
 }