diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_dc.c b/examples/current_sense/epwm_dc.c similarity index 100% rename from examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_dc.c rename to examples/current_sense/epwm_dc.c diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_dc.h b/examples/current_sense/epwm_dc.h similarity index 100% rename from examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_dc.h rename to examples/current_sense/epwm_dc.h diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_drv_aux.c b/examples/current_sense/epwm_drv_aux.c similarity index 100% rename from examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_drv_aux.c rename to examples/current_sense/epwm_drv_aux.c diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_drv_aux.h b/examples/current_sense/epwm_drv_aux.h similarity index 100% rename from examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_drv_aux.h rename to examples/current_sense/epwm_drv_aux.h diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_mod.c b/examples/current_sense/epwm_mod.c similarity index 100% rename from examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_mod.c rename to examples/current_sense/epwm_mod.c diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_mod.h b/examples/current_sense/epwm_mod.h similarity index 100% rename from examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_mod.h rename to examples/current_sense/epwm_mod.h diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/.project/project_am243x.js b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/.project/project_am243x.js index 09e096b..30b3b32 100644 --- a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/.project/project_am243x.js +++ b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/.project/project_am243x.js @@ -8,7 +8,7 @@ const files = { "epwm_dc.c", "epwm_drv_aux.c", "epwm_mod.c", - "sdfm.c", + "sdfm_example.c", "main.c", ], }; @@ -20,6 +20,7 @@ const filedirs = { common: [ "..", /* core_os_combo base */ "../../..", /* Example base */ + "../../../..", ], }; @@ -40,6 +41,7 @@ const includes_freertos_r5f = { "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f", "${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include", "${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_nine_channel_load_share_mode", + "${MOTOR_CONTROL_SDK_PATH}/examples/current_sense", "${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include" ], }; diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec index 3251841..66a0697 100644 --- a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec +++ b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -37,6 +37,7 @@ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_nine_channel_load_share_mode + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include -mcpu=cortex-r5 -mfloat-abi=hard @@ -102,13 +103,13 @@ - + - + - + - + diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile index aef6442..411a54b 100644 --- a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile +++ b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -42,7 +42,7 @@ FILES_common := \ epwm_dc.c \ epwm_drv_aux.c \ epwm_mod.c \ - sdfm.c \ + sdfm_example.c \ main.c \ ti_drivers_config.c \ ti_drivers_open_close.c \ @@ -55,6 +55,7 @@ FILES_common := \ FILES_PATH_common = \ .. \ ../../.. \ + ../../../.. \ generated \ INCLUDES_common := \ @@ -66,6 +67,7 @@ INCLUDES_common := \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \ -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \ -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_nine_channel_load_share_mode \ + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense \ -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include \ -Igenerated \ diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec index 8417a3a..69ecbe0 100644 --- a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec +++ b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -37,6 +37,7 @@ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_nine_channel_load_share_mode + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include -mcpu=cortex-r5 -mfloat-abi=hard @@ -102,13 +103,13 @@ - + - + - + - + diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile index dd547b3..3616a6e 100644 --- a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile +++ b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile @@ -42,7 +42,7 @@ FILES_common := \ epwm_dc.c \ epwm_drv_aux.c \ epwm_mod.c \ - sdfm.c \ + sdfm_example.c \ main.c \ ti_drivers_config.c \ ti_drivers_open_close.c \ @@ -55,6 +55,7 @@ FILES_common := \ FILES_PATH_common = \ .. \ ../../.. \ + ../../../.. \ generated \ INCLUDES_common := \ @@ -66,6 +67,7 @@ INCLUDES_common := \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \ -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \ -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_nine_channel_load_share_mode \ + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense \ -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include \ -Igenerated \ diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/app_sdfm.c b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/app_sdfm.c index 502a5ea..768b6ab 100644 --- a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/app_sdfm.c +++ b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/app_sdfm.c @@ -40,7 +40,7 @@ #include "ti_board_open_close.h" #include "epwm_dc.h" -#include "sdfm.h" +#include "sdfm_example.h" /*EPWM1 configuration for sigma delta clock generation: */ #define APP_EPWM1_ENABLE 0 /*make sure EPWM1 is added in sysconfig before making true this macro */ @@ -154,7 +154,8 @@ SdfmPrms gTestSdfmPrms = { ICSSG_PRU_LOAD_SHARE_MODE, TEST_ICSSG_SLICE_ID, PRUICSS_PRU0, - 300000000, /*Value of IEP clock*/ + 300000000, + {300000000,0}, /*index[0]= IEP0 clock for G0, index[1] = reserved */ 20000000, /*Value of SD clock (It should be exact equal to sd clock value)*/ 0, /*enable double update*/ FIRST_SAMPLE_TRIGGER_TIME, /*first sample trigger time*/ @@ -175,6 +176,7 @@ SdfmPrms gTestSdfmPrms = { {4, 18, 2}, {4, 18, 2} }, /*Fast detect fields {Window size, zero count max, zero count min}*/ + 0, /*enable Phase delay measurment */ 0, /*Enable zero cross*/ {1700, 1700, 1700}, /*Zero cross threshold*/ }; diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_dc.h b/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_dc.h deleted file mode 100644 index 077f5a5..0000000 --- a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/epwm_dc.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _EPWM_DC_H_ -#define _EPWM_DC_H_ - -#include -#include -#include - -/* Status return values */ -#define EPWM_DC_SOK ( 0 ) - -#define EPWM_ID_0 ( 0 ) -#define EPWM_ID_1 ( 1 ) -#define EPWM_ID_2 ( 2 ) - -#define EPWM_NUM_OUT_CH ( EPWM_OUTPUT_CH_MAX + 1 ) - -/* EPWM configuration parameters */ -typedef struct _EPwmCfgPrms_t -{ - uint32_t epwmId; /* EPWM ID */ - uint32_t epwmBaseAddr; /* EPWM base address */ - uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */ - uint32_t hspClkDiv; /* EPWM High-Speed Time-base Clock Prescale Bits */ - uint32_t clkDiv; /* EPWM Time-base Clock Prescale Bits */ - uint32_t epwmTbFreq; /* EPWM timebase clock */ - uint32_t epwmOutFreq; /* EPWM output frequency */ - /* EPWM duty cycle */ - uint32_t epwmDutyCycle[EPWM_NUM_OUT_CH]; - uint32_t epwmTbCounterDir; /* EPWM counter direction (Up, Down, Up/Down) */ - - /* TB sync in config */ - Bool cfgTbSyncIn; /* config TB sync in flag (true/false) */ - uint32_t tbPhsValue; /* cfgTbSyncIn==TRUE: timer phase value to load on Sync In event */ - uint32_t tbSyncInCounterDir; /* cfgTbSyncIn==TRUE: counter direction on Sync In event */ - - /* TB sync out config */ - Bool cfgTbSyncOut; /* config TB sync output flag (true/false) */ - uint32_t tbSyncOutMode; /* cfgTbSyncOut==TRUE: Sync Out mode */ - - /* AQ config */ - EPWM_AqActionCfg aqCfg[EPWM_NUM_OUT_CH]; - - /* DB config */ - Bool cfgDb; /* config DB flag (true/false) */ - EPWM_DeadbandCfg dbCfg; /* Deadband config */ - - /* ET config */ - Bool cfgEt; /* config ET module */ - uint32_t intSel; /* ET interrupt select */ - uint32_t intPrd; /* ET interrupt period */ -} EPwmCfgPrms_t; - -/* EPWM object */ -typedef struct _EPwmObj_t -{ - uint32_t epwmId; /* EPWM ID */ - uint32_t epwmBaseAddr; /* EPWM base address */ - uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */ - uint32_t hspClkDiv; /* EPWM High-Speed Time-base Clock Prescale Bits */ - uint32_t clkDiv; /* EPWM Time-base Clock Prescale Bits */ - uint32_t epwmTbFreq; /* EPWM timebase clock */ - uint32_t epwmOutFreq; /* EPWM output frequency */ - /* EPWM duty cycle */ - uint32_t epwmDutyCycle[EPWM_NUM_OUT_CH]; - - uint32_t epwmPrdVal; /* EPWM period value */ - -// Bool updateOut; /* Flag indicates whether to update EPWM A/B outputs */ - - /* For handling up-down count alternating period - when period isn't divisible by 2 */ - Bool toggleEpwmPrd; /* Flag for EPWM in alternating period mode */ - uint8_t toggleEpwmPrdState; /* Alternating period state: - 'Lower' or 'Upper' period written on alternate ISRs */ - uint32_t epwmPrdValL; /* 'Lower' EPWM period value written in 'Lower' state */ - uint32_t epwmPrdValU; /* 'Upper' EPWM period value written in 'Upper' state */ - - /* For handling ChA 100% Duty Cycle */ - uint32_t cmpAVal; /* Current CMPA value */ - Bool cmpANzToZ; /* Flag for EPWM transition CMPA!=0 to CMPA=0 */ - Bool cmpAZToNz; /* Flag for EPWM transition CMPA=0 to CMPA!=0 */ - - /* For handling ChB 100% Duty Cycle */ - uint32_t cmpBVal; /* Current CMPB value */ - Bool cmpBNzToZ; /* Flag for EPWM transition CMPB!=0 to CMPB=0 */ - Bool cmpBZToNz; /* Flag for EPWM transition CMPB=0 to CMPB!=0 */ -} EPwmObj_t; - -/* EPWM Handle */ -typedef EPwmObj_t * Epwm_Handle; - -/* Initialize EPWM */ -Epwm_Handle epwmInit( - EPwmCfgPrms_t *pEpwmCfgPrms, - EPwmObj_t *pEpwmObj -); - -/* Update EPWM period */ -int32_t epwmUpdatePrd( - Epwm_Handle hEpwm, - uint32_t epwmOutFreqSet -); - -/* Update EPWM A/B outputs */ -int32_t epwmUpdateOut( - Epwm_Handle hEpwm, - float VrefA, - float VrefB -); - -#endif /* _EPWM_DC_H_ */ diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/.project/project_am243x.js b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/.project/project_am243x.js index 22bf3ca..bce0b6c 100644 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/.project/project_am243x.js +++ b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/.project/project_am243x.js @@ -8,7 +8,7 @@ const files = { "epwm_dc.c", "epwm_drv_aux.c", "epwm_mod.c", - "sdfm.c", + "sdfm_example.c", "main.c", ], }; @@ -19,7 +19,8 @@ const files = { const filedirs = { common: [ "..", /* core_os_combo base */ - "../../..", /* Example base */ + "../../..", + "../../../..", ], }; @@ -40,6 +41,7 @@ const includes_freertos_r5f = { "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f", "${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include", "${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_single_pru_mode", + "${MOTOR_CONTROL_SDK_PATH}/examples/current_sense", "${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include" ], }; diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec index f9af6d7..424845a 100644 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec +++ b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -37,6 +37,7 @@ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_single_pru_mode + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include -mcpu=cortex-r5 -mfloat-abi=hard @@ -102,13 +103,13 @@ - + - + - + - + diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile index 6c73814..7a52c72 100644 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile +++ b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -42,7 +42,7 @@ FILES_common := \ epwm_dc.c \ epwm_drv_aux.c \ epwm_mod.c \ - sdfm.c \ + sdfm_example.c \ main.c \ ti_drivers_config.c \ ti_drivers_open_close.c \ @@ -55,6 +55,7 @@ FILES_common := \ FILES_PATH_common = \ .. \ ../../.. \ + ../../../.. \ generated \ INCLUDES_common := \ @@ -66,6 +67,7 @@ INCLUDES_common := \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \ -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \ -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_single_pru_mode \ + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense \ -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include \ -Igenerated \ diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec index 1dae0dd..6d446a5 100644 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec +++ b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -37,6 +37,7 @@ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_single_pru_mode + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include -mcpu=cortex-r5 -mfloat-abi=hard @@ -102,13 +103,13 @@ - + - + - + - + diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile index f1a3b42..add0ee3 100644 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile +++ b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile @@ -42,7 +42,7 @@ FILES_common := \ epwm_dc.c \ epwm_drv_aux.c \ epwm_mod.c \ - sdfm.c \ + sdfm_example.c \ main.c \ ti_drivers_config.c \ ti_drivers_open_close.c \ @@ -55,6 +55,7 @@ FILES_common := \ FILES_PATH_common = \ .. \ ../../.. \ + ../../../.. \ generated \ INCLUDES_common := \ @@ -66,6 +67,7 @@ INCLUDES_common := \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \ -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \ -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_single_pru_mode \ + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense \ -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include \ -Igenerated \ diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/app_sdfm.c b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/app_sdfm.c index de81527..197d421 100644 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/app_sdfm.c +++ b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/app_sdfm.c @@ -40,13 +40,15 @@ #include "ti_board_open_close.h" #include "epwm_dc.h" -#include "sdfm.h" +#include "sdfm_example.h" /*EPWM1 configuration for sigma delta clock generation: */ #define APP_EPWM1_ENABLE 0 /*make sure EPWM1 is added in sysconfig before making true this macro */ /* Output channel - A or B */ #define APP_EPWM_OUT_CH_EN ( 0x1 ) /* ChA enabled */ +#define NUM_CH_SUPPORTED ( 3 ) +#define ICSSG_PRU_LOAD_SHARE_MODE ( 0 ) /* EPWM functional clock */ /* Functional clock is the same for all EPWMs */ #define APP_EPWM_FCLK ( CONFIG_EPWM0_FCLK ) @@ -139,9 +141,11 @@ __attribute__((section(".gSdfmSampleOutput"))) uint32_t gSdfm_sampleOutput[NUM_C /* Test Sdfm parameters */ SdfmPrms gTestSdfmPrms = { + 0, /*Load share enable*/ PRUICSS_PRU0, TEST_ICSSG_SLICE_ID, - 300000000, /*Value of IEP clock*/ + 300000000, /*PRU core clock*/ + {300000000, 0}, /*Value of G0IEP0, second index reserved for G1IEP0 */ 20000000, /*Value of SD clock (It should be exact equal to sd clock value)*/ 0, /*enable double update*/ FIRST_SAMPLE_TRIGGER_TIME, /*first sample trigger time*/ @@ -162,6 +166,7 @@ SdfmPrms gTestSdfmPrms = { {4, 18, 2}, {4, 18, 2} }, /*Fast detect fields {Window size, zero count max, zero count min}*/ + 0, /*reserved for phase delay*/ 0, /*Enable zero cross*/ {1700, 1700, 1700}, /*Zero cross threshold*/ }; @@ -286,7 +291,7 @@ void init_sdfm() { int32_t status; /* Initialize ICSSG */ - status = initIcss(TEST_ICSSG_INST_ID, TEST_ICSSG_SLICE_ID, PRUICSS_G_MUX_EN, &gPruIcssHandle); + status = initIcss(TEST_ICSSG_INST_ID, TEST_ICSSG_SLICE_ID, PRUICSS_G_MUX_EN, ICSSG_PRU_LOAD_SHARE_MODE, &gPruIcssHandle); if (status != SDFM_ERR_NERR) { DebugP_log("Error: initIcss() fail.\r\n"); return; diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_dc.c b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_dc.c deleted file mode 100644 index 4217fd6..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_dc.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include "epwm_drv_aux.h" -#include "epwm_mod.h" -#include "epwm_dc.h" - -Epwm_Handle epwmInit( - EPwmCfgPrms_t *pEpwmCfgPrms, - EPwmObj_t *pEpwmObj -) -{ - Epwm_Handle hEpwm; /* EPWM handle */ - uint32_t epwmBaseAddr; /* EPWM base address */ - uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */ - uint32_t epwmTbFreq; /* EPWM time base clock */ - uint32_t epwmOutFreq; /* EPWM output frequency */ - uint32_t epwmTbCounterDir; /* EPWM TB counter direction */ - uint32_t epwmPrdVal; - uint32_t epwmCmpAVal, epwmCmpBVal; - - /* Get configuration parameters */ - epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr; - epwmOutChEn = pEpwmCfgPrms->epwmOutChEn; - epwmTbFreq = pEpwmCfgPrms->epwmTbFreq; - epwmOutFreq = pEpwmCfgPrms->epwmOutFreq; - epwmTbCounterDir = pEpwmCfgPrms->epwmTbCounterDir; - - /* Configure Time Base submodule */ - writeTbClkDiv(epwmBaseAddr, pEpwmCfgPrms->hspClkDiv, pEpwmCfgPrms->clkDiv); - tbPwmFreqCfg(epwmBaseAddr, epwmTbFreq, epwmOutFreq, - epwmTbCounterDir, EPWM_SHADOW_REG_CTRL_ENABLE, &epwmPrdVal); - - /* Configure TB Sync In Mode */ - if (pEpwmCfgPrms->cfgTbSyncIn == FALSE) { - EPWM_tbSyncDisable(epwmBaseAddr); - } - else { - EPWM_tbSyncEnable(epwmBaseAddr, pEpwmCfgPrms->tbPhsValue, pEpwmCfgPrms->tbSyncInCounterDir); - } - - /* Configure TB Sync Out Mode */ - if (pEpwmCfgPrms->cfgTbSyncOut == FALSE) { - EPWM_tbSetSyncOutMode(epwmBaseAddr, EPWM_TB_SYNC_OUT_EVT_DISABLE ); - } - else { - EPWM_tbSetSyncOutMode(epwmBaseAddr, pEpwmCfgPrms->tbSyncOutMode); - } - - /* Configure emulation mode */ - EPWM_tbSetEmulationMode(epwmBaseAddr, EPWM_TB_EMU_MODE_FREE_RUN); - - if ((epwmOutChEn >> 0) & 0x1) { - /* - * COMPA value - this determines the duty cycle - * COMPA = (PRD - ((dutycycle * PRD) / 100) - */ - epwmCmpAVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A] * epwmPrdVal) / 100U)); - //epwmCmpAVal = 1; // FL: force max duty cycle just before 100% DC to see where EPWM period occurs - - /* Configure counter compare submodule */ - EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_A, - epwmCmpAVal, EPWM_SHADOW_REG_CTRL_ENABLE, - EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE); - /* Configure Action Qualifier Submodule */ - EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_A, - &pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_A]); - } - - if ((epwmOutChEn >> 1) & 0x1) { - /* - * COMPB value - this determines the duty cycle - * COMPB = (PRD - ((dutycycle * PRD) / 100) - */ - epwmCmpBVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B] * epwmPrdVal) / 100U)); - - /* Configure counter compare submodule */ - EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_B, - epwmCmpBVal, EPWM_SHADOW_REG_CTRL_ENABLE, - EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE); - /* Configure Action Qualifier Submodule */ - EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_B, - &pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_B]); - } - - if (pEpwmCfgPrms->cfgDb == TRUE) { - /* Configure Dead Band Submodule */ - EPWM_deadbandCfg(epwmBaseAddr, &pEpwmCfgPrms->dbCfg); - } - else { - /* Configure Dead Band Submodule */ - EPWM_deadbandBypass(epwmBaseAddr); - } - - /* Configure Chopper Submodule */ - EPWM_chopperEnable(epwmBaseAddr, FALSE); - - /* Configure trip zone Submodule */ - EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_ONE_SHOT, 0U); - EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_CYCLE_BY_CYCLE, 0U); - - if (pEpwmCfgPrms->cfgEt == TRUE) { - /* Configure event trigger Submodule */ - EPWM_etIntrCfg(epwmBaseAddr, pEpwmCfgPrms->intSel, - pEpwmCfgPrms->intPrd); - EPWM_etIntrEnable(epwmBaseAddr); - } - - /* Init PWM object */ - hEpwm = (Epwm_Handle)pEpwmObj; - hEpwm->epwmId = pEpwmCfgPrms->epwmId; - hEpwm->epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr; - hEpwm->epwmOutChEn = pEpwmCfgPrms->epwmOutChEn; - hEpwm->hspClkDiv = pEpwmCfgPrms->hspClkDiv; - hEpwm->clkDiv = pEpwmCfgPrms->clkDiv; - hEpwm->epwmTbFreq = pEpwmCfgPrms->epwmTbFreq; - hEpwm->epwmOutFreq = pEpwmCfgPrms->epwmOutFreq; - hEpwm->epwmPrdVal = epwmPrdVal; - hEpwm->toggleEpwmPrd = FALSE; - hEpwm->toggleEpwmPrdState = 0; - hEpwm->epwmPrdValL = 0; - hEpwm->epwmPrdValU = 0; - if ((epwmOutChEn >> 0) & 0x1) { - hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_A] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A]; - hEpwm->cmpAVal = epwmCmpAVal; - hEpwm->cmpANzToZ = FALSE; - hEpwm->cmpAZToNz = FALSE; - } - if ((epwmOutChEn >> 1) & 0x1) { - hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_B] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B]; - hEpwm->cmpBVal = epwmCmpBVal; - hEpwm->cmpBNzToZ = FALSE; - hEpwm->cmpBZToNz = FALSE; - } - - return hEpwm; -} - -/* Update EPWM period */ -int32_t epwmUpdatePrd( - Epwm_Handle hEpwm, - uint32_t epwmOutFreqSet -) -{ - float epwmPrdVal_f; - uint32_t epwmPrdVal; - uint32_t rem; - - /* Check for EPWM period toggle */ - if (hEpwm->toggleEpwmPrd == TRUE) { - hEpwm->epwmPrdVal = (hEpwm->toggleEpwmPrdState == 0) ? hEpwm->epwmPrdValL : hEpwm->epwmPrdValU; - hEpwm->toggleEpwmPrdState ^= 0x1; - - /* Write next period count */ - writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal); - } - - /* Check for PWM frequency change */ - if (hEpwm->epwmOutFreq != epwmOutFreqSet) { - epwmPrdVal_f = (float)hEpwm->epwmTbFreq / epwmOutFreqSet; - epwmPrdVal_f = roundf(epwmPrdVal_f); - - epwmPrdVal = (uint32_t)epwmPrdVal_f; - rem = epwmPrdVal - epwmPrdVal/2*2; - if (rem == 0) { - /* Period is divisible by 2, - alternating period not employed */ - hEpwm->toggleEpwmPrd = FALSE; - hEpwm->toggleEpwmPrdState = 0; - hEpwm->epwmPrdValL = 0; - hEpwm->epwmPrdValU = 0; - hEpwm->epwmPrdVal = epwmPrdVal/2; - } else { - /* Period is not divisible by 2, - alternating period employed to provide correct average EPWM frequency: - EPWM period 2*n : TBPRD <- 'Lower' period - EPWM period 2*n+1 : TBPRD <- 'Upper' period - */ - hEpwm->toggleEpwmPrd = TRUE; - hEpwm->toggleEpwmPrdState = 1; - hEpwm->epwmPrdValL = epwmPrdVal/2; - hEpwm->epwmPrdValU = epwmPrdVal/2+1; - hEpwm->epwmPrdVal = hEpwm->epwmPrdValL; - } - - /* Write next period count */ - writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal); - - hEpwm->epwmOutFreq = epwmOutFreqSet; - } - - return EPWM_DC_SOK; -} - -/* Update EPWM A/B outputs */ -int32_t epwmUpdateOut( - Epwm_Handle hEpwm, - float VrefA, - float VrefB -) -{ - float dcVal; /* EPWM duty cycle value */ - uint16_t cmpVal; /* EPWM CMP value */ - - if ((hEpwm->epwmOutChEn >> 0) & 0x1) { - /* Compute next Duty Cycle and CMP values */ - computeCmpx(VrefA, hEpwm->epwmPrdVal, &dcVal, &cmpVal); - - /* Write next CMPA value */ - writeCmpA(hEpwm->epwmBaseAddr, cmpVal); - - /* EPWM 100% Duty Cycle */ - /* Handle transition to 100% Duty Cycle */ - if (hEpwm->cmpANzToZ == TRUE) { - /* restore original AQ */ - cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); - hEpwm->cmpANzToZ = FALSE; - } - if ((hEpwm->cmpAVal != 0) && (cmpVal == 0)) { - /* set AQ to set for next period */ - cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH); - hEpwm->cmpANzToZ = TRUE; - } - - /* Handle transition from 100% Duty Cycle */ - if (hEpwm->cmpAZToNz == TRUE) { - /* restore original AQ */ - cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); - hEpwm->cmpAZToNz = FALSE; - } - if ((hEpwm->cmpAVal == 0) && (cmpVal != 0)) { - /* set AQ to clear for next period */ - cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW); - hEpwm->cmpAZToNz = TRUE; - } - hEpwm->cmpAVal = cmpVal; - } - - if ((hEpwm->epwmOutChEn >> 1) & 0x1) { - /* Compute next Duty Cycle and CMP values */ - computeCmpx(VrefB, hEpwm->epwmPrdVal, &dcVal, &cmpVal); - - /* Write next CMPB value */ - writeCmpB(hEpwm->epwmBaseAddr, cmpVal); - - /* EPWM 100% Duty Cycle */ - /* Handle transition to 100% Duty Cycle */ - if (hEpwm->cmpBNzToZ == TRUE) { - /* restore original AQ */ - cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); - hEpwm->cmpBNzToZ = FALSE; - } - if ((hEpwm->cmpBVal != 0) && (cmpVal == 0)) { - /* set AQ to set for next period */ - cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH); - hEpwm->cmpBNzToZ = TRUE; - } - - /* Handle transition from 100% Duty Cycle */ - if (hEpwm->cmpBZToNz == TRUE) { - /* restore original AQ */ - cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); - hEpwm->cmpBZToNz = FALSE; - } - if ((hEpwm->cmpBVal == 0) && (cmpVal != 0)) { - /* set AQ to clear for next period */ - cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW); - hEpwm->cmpBZToNz = TRUE; - } - hEpwm->cmpBVal = cmpVal; - } - - return EPWM_DC_SOK; -} diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_drv_aux.c b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_drv_aux.c deleted file mode 100644 index 1b240d3..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_drv_aux.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include "epwm_drv_aux.h" - -#include - -/* Configure PWM Time base counter Frequency/Period */ -void tbPwmFreqCfg( - uint32_t baseAddr, - uint32_t tbClk, - uint32_t pwmFreq, - uint32_t counterDir, - uint32_t enableShadowWrite, - uint32_t *pPeriodCount -) -{ - uint32_t tbPeriodCount; - float tbPeriodCount_f; - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_PRDLD, enableShadowWrite); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CTRMODE, counterDir); - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), - (uint16_t)regVal); - - /* compute period using floating point */ - tbPeriodCount_f = (float)tbClk / pwmFreq; - if (EPWM_TB_COUNTER_DIR_UP_DOWN == counterDir) { - tbPeriodCount_f = tbPeriodCount_f / 2.0; - } - tbPeriodCount_f = roundf(tbPeriodCount_f); - tbPeriodCount = (uint32_t)tbPeriodCount_f; - -#if 0 /* use this in case there is some reason not to use floating point */ - /* compute period using fixed point */ - tbPeriodCount = tbClk << 4; /* U32Q4 */ - tbPeriodCount /= pwmFreq; - if (EPWM_TB_COUNTER_DIR_UP_DOWN == counterDir) { - tbPeriodCount /= 2; - } - tbPeriodCount += 1<<3; /* biased rouding to 0.5 */ - tbPeriodCount >>= 4; /* U32Q0 */ -#endif - - regVal = (counterDir == EPWM_TB_COUNTER_DIR_UP_DOWN) ? - tbPeriodCount : tbPeriodCount-1; - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPRD), - (uint16_t)regVal); - - *pPeriodCount = tbPeriodCount; -} diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_drv_aux.h b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_drv_aux.h deleted file mode 100644 index 39a992e..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_drv_aux.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _EPWM_DRV_AUX_H_ -#define _EPWM_DRV_AUX_H_ - -#include -#include -#include - -/* Write EPWM CMPA */ -static inline void writeCmpA( - uint32_t baseAddr, - uint32_t cmpVal -) -{ - HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA, - (uint16_t)cmpVal); -} - -/* Write EPWM CMPB */ -static inline void writeCmpB( - uint32_t baseAddr, - uint32_t cmpVal -) -{ - HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB, - (uint16_t)cmpVal); -} - -/* Write EPWM CMPA/CMPB */ -static inline void writeCmpAB( - uint32_t baseAddr, - uint32_t cmpAVal, - uint32_t cmpBVal -) -{ - /* Write CMPA */ - HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA, - (uint16_t)cmpAVal); - - /* Write CMPB */ - HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB, - (uint16_t)cmpBVal); -} - -/* Configure Output ChannelA AQ Zero */ -static inline void cfgOutChAAqZero( - uint32_t baseAddr, - uint32_t zeroAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_ZRO, zeroAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); -} - -/* Configure Output ChannelA AQ CMPA Up */ -static inline void cfgOutChAAqCAU( - uint32_t baseAddr, - uint32_t cmpAUpAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAU, cmpAUpAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); -}; - -/* Configure Output ChannelA AQ CMPA Down */ -static inline void cfgOutChAAqCAD( - uint32_t baseAddr, - uint32_t cmpADownAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAD, cmpADownAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); -} - -/* Configure Output ChannelB AQ Zero */ -static inline void cfgOutChBAqZero( - uint32_t baseAddr, - uint32_t zeroAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLB); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLB_ZRO, zeroAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLB), (uint16_t)regVal); -} - -/* Configure Output ChannelA AQ CMPB Up */ -static inline void cfgOutChAAqCBU( - uint32_t baseAddr, - uint32_t cmpBUpAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CBU, cmpBUpAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); -} - -/* Write TB Period */ -static inline void writeTbPrd( - uint32_t baseAddr, - uint32_t tbPeriodCount -) -{ - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPRD), (uint16_t)tbPeriodCount); -} - -/* Write TB Phase */ -static inline void writeTbPhase( - uint32_t baseAddr, - uint32_t tbPhsValue -) -{ - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPHS), (uint16_t)tbPhsValue); -} - -/* Write TBCTL HSPDIV & CLKDIV */ -static inline void writeTbClkDiv( - uint32_t baseAddr, - uint32_t hspClkDiv, - uint32_t clkDiv -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CLKDIV, clkDiv); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_HSPCLKDIV, hspClkDiv); - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal); -} - -/* Write TBCTL CTRMODE */ -static inline void writeTbCtrMode( - uint32_t baseAddr, - uint32_t ctrMode -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CTRMODE, ctrMode); - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal); -} - -/* Configure PWM Time base counter Frequency/Period */ -void tbPwmFreqCfg( - uint32_t baseAddr, - uint32_t tbClk, - uint32_t pwmFreq, - uint32_t counterDir, - uint32_t enableShadowWrite, - uint32_t *pPeriodCount -); - -#endif /* _EPWM_DRV_AUX_H_ */ diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_mod.c b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_mod.c deleted file mode 100644 index 7a13302..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_mod.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "epwm_mod.h" - -#include -#include - - -/* Min / max output amplitude. - Waveform amplitude values beyond these thresholds are saturated. */ -#define VREF_MAX ( 1.0f ) -#define VREF_MIN ( -1.0f ) - -/* Compute Duty Cycle & CMPx given Vref & EPWM period */ -void computeCmpx( - float Vref, - uint32_t epwmPrdVal, - float *pEpwmDutyCycle, - uint16_t *pEpwmCmpVal -) -{ - float dc_f; - float cmp_f; - uint16_t cmp; - - if (Vref >= VREF_MAX) { - /* 100% duty cycle */ - dc_f = 1.0; - } - else if (Vref <= VREF_MIN) { - /* 0% duty cycle */ - dc_f = 0.0; - } - else { - /* compute Duty Cycle */ - dc_f = 0.5*(Vref + 1.0); - } - - /* compute CMPx */ - cmp_f = (1.0 - dc_f)*epwmPrdVal; /* up-down count */ - cmp = (uint16_t)roundf(cmp_f); - - *pEpwmDutyCycle = dc_f; - *pEpwmCmpVal = cmp; -} diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_mod.h b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_mod.h deleted file mode 100644 index 8f9506e..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/epwm_mod.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _EPWM_MOD_H_ -#define _EPWM_MOD_H_ - -#include - -/* Compute Duty Cycle & CMPx given Vref */ -void computeCmpx( - float Vref, - uint32_t epwmPrdVal, - float *pEpwmDutyCycle, - uint16_t *pEpwmCmpVal -); - -#endif /* _EPWM_MOD_H_ */ diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/sdfm.c b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/sdfm.c deleted file mode 100644 index c15aa38..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/sdfm.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include "ti_drivers_config.h" -#include "ti_drivers_open_close.h" -#include "ti_board_open_close.h" - -#include -#include -#include -#include - -#include "tisdfm_pruss_intc_mapping.h" /* INTC configuration */ -#include "current_sense/sdfm/firmware/sdfm_bin.h" /* SDFM image data */ - -#include "sdfm.h" -#include "current_sense/sdfm/include/sdfm_api.h" -/* PRU SDFM FW image info */ -typedef struct PRUSDFM_PruFwImageInfo_s -{ - const uint32_t *pPruImemImg; - const uint32_t pruImemImgSz; -} PRUSDFM_PruFwImageInfo; - -/* Number of PRU images */ -#define PRU_SDFM_NUM_PRU_IMAGE ( 1 ) - -/* PRU SDFM image info */ -static PRUSDFM_PruFwImageInfo gPruFwImageInfo[PRU_SDFM_NUM_PRU_IMAGE] = -{ - {SDFM_PRU0_image_0, sizeof(SDFM_PRU0_image_0)} /* single PRU FW binary */ -}; - -/* ICSS INTC configuration */ -static const PRUICSS_IntcInitData gPruicssIntcInitdata = PRUICSS_INTC_INITDATA; - -/* - * ======== initIcss ======== - */ -/* Initialize ICSSG */ -int32_t initIcss( - uint8_t icssInstId, - uint8_t sliceId, - uint8_t saMuxMode, - PRUICSS_Handle *pPruIcssHandle -) -{ - PRUICSS_Handle pruIcssHandle; - int32_t size; - int32_t status; - - /* Open ICSS PRU instance */ - pruIcssHandle = PRUICSS_open(icssInstId); - if (pruIcssHandle == NULL) { - return SDFM_ERR_INIT_ICSSG; - } - - /* Disable slice PRU cores */ - if (sliceId == ICSSG_SLICE_ID_0) - { - status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU0); - if (status != SystemP_SUCCESS) - { - return SDFM_ERR_INIT_ICSSG; - } - - } - else if (sliceId == ICSSG_SLICE_ID_1) - { - status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU1); - if (status != SystemP_SUCCESS) - { - return SDFM_ERR_INIT_ICSSG; - } - - } - else - { - return SDFM_ERR_INIT_ICSSG; - } - - /* Reset slice memories */ - size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_IRAM_PRU(sliceId)); - if (size == 0) - { - return SDFM_ERR_INIT_ICSSG; - } - - size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_DATARAM(sliceId)); - if (size == 0) - { - return SDFM_ERR_INIT_ICSSG; - } - - /* Set ICSS pin mux */ - PRUICSS_setSaMuxMode(pruIcssHandle, saMuxMode); - - /* Initialize ICSS INTC */ - status = PRUICSS_intcInit(pruIcssHandle, &gPruicssIntcInitdata); - if (status != SystemP_SUCCESS) { - return SDFM_ERR_INIT_ICSSG; - } - - *pPruIcssHandle = pruIcssHandle; - - return SDFM_ERR_NERR; -} -void SDFM_configGpioPins(sdfm_handle h_sdfm) -{ - /*ch0 GPIO configuration*/ - uint32_t gpioBaseAddrCh0 = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_ZC_TH_CH0_BASE_ADDR); - uint32_t pinNumCh0 = GPIO_ZC_TH_CH0_PIN; - GPIO_setDirMode(gpioBaseAddrCh0, pinNumCh0, GPIO_ZC_TH_CH0_DIR); - SDFM_configComparatorGpioPins(h_sdfm, 0, gpioBaseAddrCh0, pinNumCh0); - - /*ch1 GPIO configuration*/ - uint32_t gpioBaseAddrCh1 = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_ZC_TH_CH1_BASE_ADDR); - uint32_t pinNumCh1 = GPIO_ZC_TH_CH1_PIN; - GPIO_setDirMode(gpioBaseAddrCh1, pinNumCh1, GPIO_ZC_TH_CH1_DIR); - SDFM_configComparatorGpioPins(h_sdfm, 1, gpioBaseAddrCh1, pinNumCh1); - - /*ch2 GPIO configuration*/ - uint32_t gpioBaseAddrCh2 = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_ZC_TH_CH2_BASE_ADDR); - uint32_t pinNumCh2 = GPIO_ZC_TH_CH2_PIN; - GPIO_setDirMode(gpioBaseAddrCh2, pinNumCh2, GPIO_ZC_TH_CH2_DIR); - SDFM_configComparatorGpioPins(h_sdfm, 2, gpioBaseAddrCh2, pinNumCh2); - -} -/* Initialize SDFM PRU FW */ -int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUICSS_Handle pruIcssHandle) -{ - sdfm_handle hSdfm; - uint8_t SDFM_CH = 0; - /* Initialize SDFM instance */ - hSdfm = SDFM_init(pruId, pSdfmPrms->pruInsId); - - hSdfm->gPruIcssHandle = pruIcssHandle; - hSdfm->pruss_cfg = (void *)(((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->cfgRegBase); - - uint32_t i; - i = SDFM_getFirmwareVersion(hSdfm); - DebugP_log("\n\n\n"); - DebugP_log("SDFM firmware version \t: %x.%x.%x (%s)\n\n", (i >> 24) & 0x7F, - (i >> 16) & 0xFF, i & 0xFFFF, i & (1 << 31) ? "internal" : "release"); - if (hSdfm == NULL) - { - return SDFM_ERR_INIT_SDFM; - } - - hSdfm->iepClock = pSdfmPrms->iepClock; - hSdfm->sdfmClock = pSdfmPrms->sdClock; - hSdfm->sampleOutputInterface = (SDFM_SampleOutInterface *)(pSdfmPrms->samplesBaseAddress); - uint32_t sampleOutputInterfaceGlobalAddr = CPU0_BTCM_SOCVIEW(pSdfmPrms->samplesBaseAddress); - hSdfm->p_sdfm_interface->sampleBufferBaseAdd = sampleOutputInterfaceGlobalAddr; - hSdfm->iepInc = 1; /* Default IEP increment 1 */ - - uint8_t acc_filter = 0; //SINC3 filter - uint8_t ecap_divider = 0x0F; //IEP at 300MHz: SD clock = 300/15=20Mhz - - /*configure IEP count for one epwm period*/ - SDFM_configIepCount(hSdfm, pSdfmPrms->epwmOutFreq); - - /*configure ecap as PWM code for generate 20 MHz sdfm clock*/ - SDFM_configEcap(hSdfm, ecap_divider); - - /*set Noraml current OSR */ - SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->filterOsr); - - /*below configuration for all three channel*/ - for(SDFM_CH = 0; SDFM_CH < NUM_CH_SUPPORTED; SDFM_CH++) - { - SDFM_setEnableChannel(hSdfm, SDFM_CH); - - /*set comparator osr or Over current osr*/ - SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->comFilterOsr); - - /*set ACC source or filter type*/ - SDFM_configDataFilter(hSdfm, SDFM_CH, acc_filter); - - /*set clock inversion & clock source for all three channel*/ - SDFM_selectClockSource(hSdfm, SDFM_CH, pSdfmPrms->clkPrms[SDFM_CH]); - - /*set threshold values */ - SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->thresholdParms[SDFM_CH]); - if(pSdfmPrms->enFastDetect) - { - /*Fast detect configuration */ - SDFM_configFastDetect(hSdfm, SDFM_CH, pSdfmPrms->fastDetect[SDFM_CH]); - } - if(pSdfmPrms->enComparator ) - { - SDFM_enableComparator(hSdfm, SDFM_CH); - } - else - { - SDFM_disableComparator(hSdfm, SDFM_CH); - } - - if(pSdfmPrms->enZeroCross) - { - SDFM_enableZeroCrossDetection(hSdfm, SDFM_CH, pSdfmPrms->zcThr[SDFM_CH]); - } - - } - - /*GPIO pin configuration for threshold measurment*/ - SDFM_configGpioPins(hSdfm); - - SDFM_setSampleTriggerTime(hSdfm, pSdfmPrms->firstSampTrigTime); - if(pSdfmPrms->enSecondUpdate) - { - SDFM_enableDoubleSampling(hSdfm, pSdfmPrms->secondSampTrigTime); - } - else - { - SDFM_disableDoubleSampling(hSdfm); - } - - /* Enable (global) SDFM */ - SDFM_enable(hSdfm); - - *pHSdfm = hSdfm; - - return SDFM_ERR_NERR; -} -/* - * ======== initPruSdfm ======== - */ -/* Initialize PRU core for SDFM */ -int32_t initPruSdfm( - PRUICSS_Handle pruIcssHandle, - uint8_t pruInstId, - SdfmPrms *pSdfmPrms, - sdfm_handle *pHSdfm -) -{ - uint8_t sliceId; - uint32_t pruIMem; - PRUSDFM_PruFwImageInfo *pPruFwImageInfo; - int32_t size; - const uint32_t *sourceMem; /* Source memory[ Array of uint32_t ] */ - uint32_t imemOffset; /* Offset at which write will happen */ - uint32_t byteLen; /* Total number of bytes to be written */ - uint8_t pruId; - int32_t status; - - /* Reset PRU */ - status = PRUICSS_resetCore(pruIcssHandle, pruInstId); - if (status != SystemP_SUCCESS) { - return SDFM_ERR_INIT_PRU_SDFM; - } - - - /* Calculate slice ID */ - sliceId = pruInstId - (uint8_t)pruInstId/ICSSG_NUM_SLICE * ICSSG_NUM_SLICE; - /* Determine PRU DMEM address */ - /* Determine PRU FW image and PRU IMEM address */ - - switch (pruInstId) - { - case PRUICSS_PRU0: - case PRUICSS_PRU1: - pPruFwImageInfo = &gPruFwImageInfo[0]; - pruIMem = PRUICSS_IRAM_PRU(sliceId); - break; - default: - pPruFwImageInfo = NULL; - break; - } - - if ((pPruFwImageInfo == NULL) || - (pPruFwImageInfo->pPruImemImg == NULL)) - { - return SDFM_ERR_INIT_PRU_SDFM; - } - - /* Write IMEM */ - imemOffset = 0; - sourceMem = (uint32_t *)pPruFwImageInfo->pPruImemImg; - byteLen = pPruFwImageInfo->pruImemImgSz; - size = PRUICSS_writeMemory(pruIcssHandle, pruIMem, imemOffset, sourceMem, byteLen); - if (size == 0) - { - return SDFM_ERR_INIT_PRU_SDFM; - } - - /* Enable PRU */ - status = PRUICSS_enableCore(pruIcssHandle, pruInstId); - if (status != SystemP_SUCCESS) { - return SDFM_ERR_INIT_PRU_SDFM; - } -/* Translate PRU ID to SDFM API */ - if (pruInstId == PRUICSS_PRU0) - { - pruId = PRU_ID_0; - } - else if (pruInstId == PRUICSS_PRU1) - { - pruId = PRU_ID_1; - } - else { - return SDFM_ERR_INIT_PRU_SDFM; - } - - /* Initialize SDFM PRU FW */ - status = initSdfmFw(pruId, pSdfmPrms, pHSdfm, pruIcssHandle); - if (status != SDFM_ERR_NERR) { - return SDFM_ERR_INIT_PRU_SDFM; - } - return SDFM_ERR_NERR; - -} - - diff --git a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/sdfm.h b/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/sdfm.h deleted file mode 100644 index 278eb6a..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_single_pru_mode/sdfm.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _SDFM_H_ -#define _SDFM_H_ - -#include -#include -#include "current_sense/sdfm/include/sdfm_api.h" - -/* Status codes */ -#define SDFM_ERR_NERR ( 0 ) /* no error */ -#define SDFM_ERR_CFG_PIN_MUX ( -1 ) /* pin mux configuration error */ -#define SDFM_ERR_CFG_ICSSG_CLKCFG ( -2 ) /* ICSSG clock configuration error */ -#define SDFM_ERR_INIT_ICSSG ( -3 ) /* initialize ICSSG error */ -#define SDFM_ERR_CFG_MCU_INTR ( -4 ) /* interrupt configuration error */ -#define SDFM_ERR_INIT_PRU_SDFM ( -5 ) /* initialize PRU for SDFM error */ -#define SDFM_ERR_INIT_SDFM ( -6 ) /* initialize SDFM error */ - -/* Bit for SDFM configuration mask */ -#define SDFM_CFG_CLK ( 1<<0 ) -#define SDFM_CFG_OSR ( 1<<1 ) -#define SDFM_CFG_TRIG_SAMP_TIME ( 1<<2 ) -#define SDFM_CFG_TRIG_SAMP_CNT ( 1<<3 ) -#define SDFM_CFG_CH_EN ( 1<<4 ) -#define SDFM_CFG_FD ( 1<<5 ) -#define SDFM_CFG_TRIG_OUT_SAMP_BUF ( 1<<6 ) - -/* SDFM mode */ -#define SDFM_MODE_TRIG ( 0 ) -#define SDFM_MODE_CONT ( 1 ) - -/* ICSSG Core clock source selection options */ -#define CORE_CLK_SEL_ICSSGn_CORE_CLK ( 0 ) /* Mux Output */ -#define CORE_CLK_SEL_ICSSGn_ICLK ( 1 ) /* ICSSGn_ICLK = MAIN_SYSCLK0/2 = 250 MHz */ -/* ICSSG Core clock selections in case Mux Output selected */ -#define ICSSGn_CORE_CLK_SEL_MAIN_PLL2_HSDIV0_CLKOUT ( 0 ) /* 225 or 300 MHz, default 225 MHz */ -#define ICSSGn_CORE_CLK_SEL_MAIN_PLL0_HSDIV9_CLKOUT ( 1 ) /* 200, 250, or 333 MHz, default 200 MHz */ -#define ICSSGn_CORE_CLK_SEL_NUMSEL ( 2 ) -/* ICSSG Core clock frequency in case Mux Output selected. - Set to 0 in case clock frequency configuration not desired. */ -#define ICSSGn_CORE_CLK_FREQ_225MHZ ( 225000000UL ) /* MAIN PLL2 HSDIV0, 225 MHz */ -#define ICSSGn_CORE_CLK_FREQ_300MHZ ( 300000000UL ) /* MAIN PLL2 HSDIV0, 300 MHz */ -#define ICSSGn_CORE_CLK_FREQ_200MHZ ( 200000000UL ) /* MAIN PLL0 HSDIV9, 200 MHz */ -#define ICSSGn_CORE_CLK_FREQ_250MHZ ( 250000000UL ) /* MAIN PLL0 HSDIV9, 250 MHz */ -#define ICSSGn_CORE_CLK_FREQ_333MHZ ( 333333333UL ) /* MAIN PLL0 HSDIV9, 333 MHz */ -#define ICSSGn_CORE_CLK_FREQ_NOCFG ( 0UL ) /* No clock frequency reconfig */ -//#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_NOCFG ) -#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_300MHZ ) -//#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_333MHZ ) - -/* ICSSG IEP clock source selection options */ -#define IEP_CLK_SEL_ICSSGn_IEP_CLK ( 0 ) /* Mux Output */ -#define IEP_CLK_SEL_CORE_CLK ( 1 ) /* CORE_CLK */ -/* ICSSG IEP clock selections in case Mux output selected */ -#define ICSSGn_IEP_CLK_SEL_MAIN_PLL2_HSDIV5_CLKOUT ( 0 ) /* Default 225 MHz */ -#define ICSSGn_IEP_CLK_SEL_MAIN_PLL0_HSDIV6_CLKOUT ( 1 ) /* 200 or 250 MHz, default 200 MHz */ -#define ICSSGn_IEP_CLK_SEL_CPSW0_CPTS_RFT_CLK ( 2 ) -#define ICSSGn_IEP_CLK_SEL_CPTS_RFT_CLK ( 3 ) -#define ICSSGn_IEP_CLK_SEL_MCU_EXT_REFCLK0 ( 4 ) -#define ICSSGn_IEP_CLK_SEL_EXT_REFCLK1 ( 5 ) -#define ICSSGn_IEP_CLK_SEL_SERDES0_IP1_LN0_TXMCLK ( 6 ) -#define ICSSGn_IEP_CLK_SEL_SYSCLK0 ( 7 ) -#define ICSSGn_IEP_CLK_SEL_NUMSEL ( 8 ) -/* ICSSG IEP clock frequency in case Mux Output selected. - Set to 0 in case clock frequency configuration not desired. */ -#define ICSSGn_IEP_CLK_FREQ_200MHZ ( 200000000UL ) /* MAIN PLL0 HSDIV6, 200 MHz */ -#define ICSSGn_IEP_CLK_FREQ_250MHZ ( 250000000UL ) /* MAIN PLL0 HSDIV6, 250 MHz */ -#define ICSSGn_IEP_CLK_FREQ_NOCFG ( 0UL ) /* No clock frequency reconfig */ -#define ICSSGn_IEP_CLK_FREQ ( ICSSGn_IEP_CLK_FREQ_NOCFG ) - -/* Default ICSS pin mux setting */ -#define PRUICSS_G_MUX_EN_DEF ( 0x0 ) /* ICSSG_SA_MX_REG:G_MUX_EN */ - -/* Translate the TCM local view addr to SoC view addr */ -#define CPU0_ATCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_ATCM_BASE+(x)) -#define CPU1_ATCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_ATCM_BASE+(x)) -#define CPU0_BTCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_BTCM_BASE+(x - CSL_R5FSS0_BTCM_BASE)) -#define CPU1_BTCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_BTCM_BASE+(x - CSL_R5FSS1_BTCM_BASE)) - -#define ICSSG_SLICE_ID_0 ( 0 ) /* ICSSG slide ID 0 */ -#define ICSSG_SLICE_ID_1 ( 1 ) /* ICSSG slide ID 1 */ -#define ICSSG_NUM_SLICE ( 2 ) /* ICSSG number of slices */ -#define NUM_FD_FIELD ( 3 ) - -#define NUM_CH_SUPPORTED ( 3 ) -/* SDFM Channel IDs*/ -#define SDFM_CH0 (0) -#define SDFM_CH1 (1) -#define SDFM_CH2 (2) -#define SDFM_CH3 (3) -#define SDFM_CH4 (4) -#define SDFM_CH5 (5) -#define SDFM_CH6 (6) -#define SDFM_CH7 (7) -#define SDFM_CH8 (8) - -/*! - * @brief PRUICSS Instance IDs - */ -typedef enum PRUICSS_MaxInstances_s -{ - PRUICSS_INSTANCE_ONE=0, - PRUICSS_INSTANCE_TWO=1, - PRUICSS_INSTANCE_MAX=2 -} PRUICSS_MaxInstances; - -/* SDFM configuration parameters */ -typedef struct SdfmPrms_s -{ - /** - + - + - + - + diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile index 626527a..0c9cc55 100644 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile +++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile @@ -42,7 +42,7 @@ FILES_common := \ epwm_dc.c \ epwm_drv_aux.c \ epwm_mod.c \ - sdfm.c \ + sdfm_example.c \ main.c \ mclk_iep0_sync.c \ ti_drivers_config.c \ @@ -56,6 +56,7 @@ FILES_common := \ FILES_PATH_common = \ .. \ ../../.. \ + ../../../.. \ generated \ INCLUDES_common := \ @@ -66,6 +67,7 @@ INCLUDES_common := \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \ -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \ + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense \ -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation \ -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include \ -Igenerated \ diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec index 96ea882..f539485 100644 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec +++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec @@ -36,6 +36,7 @@ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include -mcpu=cortex-r5 @@ -102,13 +103,13 @@ - + - + - + - + diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile index 79d3669..57d2b00 100644 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile +++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile @@ -42,7 +42,7 @@ FILES_common := \ epwm_dc.c \ epwm_drv_aux.c \ epwm_mod.c \ - sdfm.c \ + sdfm_example.c \ main.c \ mclk_iep0_sync.c \ ti_drivers_config.c \ @@ -56,6 +56,7 @@ FILES_common := \ FILES_PATH_common = \ .. \ ../../.. \ + ../../../.. \ generated \ INCLUDES_common := \ @@ -66,6 +67,7 @@ INCLUDES_common := \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \ -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \ + -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense \ -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation \ -I${MOTOR_CONTROL_SDK_PATH}/source/pruicss_pwm/include \ -Igenerated \ diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/app_sdfm.c b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/app_sdfm.c index 47da97d..e738940 100644 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/app_sdfm.c +++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/app_sdfm.c @@ -40,7 +40,7 @@ #include "ti_board_open_close.h" #include "epwm_dc.h" -#include "sdfm.h" +#include "sdfm_example.h" #include "mclk_iep0_sync.h" /*EPWM1 configuration for sigma delta clock generation: */ @@ -48,6 +48,9 @@ /* Output channel - A or B */ #define APP_EPWM_OUT_CH_EN ( 0x1 ) /* ChA enabled */ +#define NUM_CH_SUPPORTED ( 3 ) +#define ICSSG_PRU_LOAD_SHARE_MODE ( 0 ) + /* EPWM functional clock */ /* Functional clock is the same for all EPWMs */ #define APP_EPWM_FCLK ( CONFIG_EPWM0_FCLK ) @@ -140,11 +143,12 @@ __attribute__((section(".gSdfmSampleOutput"))) uint32_t gSdfm_sampleOutput[NUM_C /* Test Sdfm parameters */ SdfmPrms gTestSdfmPrms = { + ICSSG_PRU_LOAD_SHARE_MODE, PRUICSS_PRU0, /*PRU core ID*/ TEST_ICSSG_SLICE_ID, /*SLICE IDs*/ 300000000, /*PRU Core clock*/ - 300000000, /*Value of ICSSG0_IEP clock*/ - 300000000, /*ICSSG1_IEP_CLOCK*/ + {300000000, /*Value of ICSSG0_IEP clock*/ + 300000000}, /*ICSSG1_IEP_CLOCK*/ 20000000, /*Value of SD clock (It should be exact equal to sd clock value)*/ 0, /*enable double update*/ FIRST_SAMPLE_TRIGGER_TIME, /*first sample trigger time*/ @@ -288,7 +292,7 @@ void init_sdfm() { int32_t status; /* Initialize ICSSG */ - status = initIcss(TEST_ICSSG_INST_ID, TEST_ICSSG_SLICE_ID, PRUICSS_G_MUX_EN, &gPruIcssHandle); + status = initIcss(TEST_ICSSG_INST_ID, TEST_ICSSG_SLICE_ID, PRUICSS_G_MUX_EN, ICSSG_PRU_LOAD_SHARE_MODE, &gPruIcssHandle); if (status != SDFM_ERR_NERR) { DebugP_log("Error: initIcss() fail.\r\n"); return; @@ -351,6 +355,14 @@ void sdfm_main(void *args) init_sdfm(); DebugP_log("SDFM Configured!\r\n"); + /*Read measured delay*/ + float delay; + delay = SDFM_getClockPhaseDelay(gHPruSdfm); + /* Convert nenosec into IEP cycle count */ + uint32_t iepCount = (delay*(gTestSdfmPrms.iepClock[1]))/1000000000; + /* Config IEP SYNC1 delay based on phase compensation */ + config_SYNC_DELAY(iepCount); + /* Start EPWM0 clock */ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN, 1); diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.c b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.c deleted file mode 100644 index 4217fd6..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include "epwm_drv_aux.h" -#include "epwm_mod.h" -#include "epwm_dc.h" - -Epwm_Handle epwmInit( - EPwmCfgPrms_t *pEpwmCfgPrms, - EPwmObj_t *pEpwmObj -) -{ - Epwm_Handle hEpwm; /* EPWM handle */ - uint32_t epwmBaseAddr; /* EPWM base address */ - uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */ - uint32_t epwmTbFreq; /* EPWM time base clock */ - uint32_t epwmOutFreq; /* EPWM output frequency */ - uint32_t epwmTbCounterDir; /* EPWM TB counter direction */ - uint32_t epwmPrdVal; - uint32_t epwmCmpAVal, epwmCmpBVal; - - /* Get configuration parameters */ - epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr; - epwmOutChEn = pEpwmCfgPrms->epwmOutChEn; - epwmTbFreq = pEpwmCfgPrms->epwmTbFreq; - epwmOutFreq = pEpwmCfgPrms->epwmOutFreq; - epwmTbCounterDir = pEpwmCfgPrms->epwmTbCounterDir; - - /* Configure Time Base submodule */ - writeTbClkDiv(epwmBaseAddr, pEpwmCfgPrms->hspClkDiv, pEpwmCfgPrms->clkDiv); - tbPwmFreqCfg(epwmBaseAddr, epwmTbFreq, epwmOutFreq, - epwmTbCounterDir, EPWM_SHADOW_REG_CTRL_ENABLE, &epwmPrdVal); - - /* Configure TB Sync In Mode */ - if (pEpwmCfgPrms->cfgTbSyncIn == FALSE) { - EPWM_tbSyncDisable(epwmBaseAddr); - } - else { - EPWM_tbSyncEnable(epwmBaseAddr, pEpwmCfgPrms->tbPhsValue, pEpwmCfgPrms->tbSyncInCounterDir); - } - - /* Configure TB Sync Out Mode */ - if (pEpwmCfgPrms->cfgTbSyncOut == FALSE) { - EPWM_tbSetSyncOutMode(epwmBaseAddr, EPWM_TB_SYNC_OUT_EVT_DISABLE ); - } - else { - EPWM_tbSetSyncOutMode(epwmBaseAddr, pEpwmCfgPrms->tbSyncOutMode); - } - - /* Configure emulation mode */ - EPWM_tbSetEmulationMode(epwmBaseAddr, EPWM_TB_EMU_MODE_FREE_RUN); - - if ((epwmOutChEn >> 0) & 0x1) { - /* - * COMPA value - this determines the duty cycle - * COMPA = (PRD - ((dutycycle * PRD) / 100) - */ - epwmCmpAVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A] * epwmPrdVal) / 100U)); - //epwmCmpAVal = 1; // FL: force max duty cycle just before 100% DC to see where EPWM period occurs - - /* Configure counter compare submodule */ - EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_A, - epwmCmpAVal, EPWM_SHADOW_REG_CTRL_ENABLE, - EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE); - /* Configure Action Qualifier Submodule */ - EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_A, - &pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_A]); - } - - if ((epwmOutChEn >> 1) & 0x1) { - /* - * COMPB value - this determines the duty cycle - * COMPB = (PRD - ((dutycycle * PRD) / 100) - */ - epwmCmpBVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B] * epwmPrdVal) / 100U)); - - /* Configure counter compare submodule */ - EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_B, - epwmCmpBVal, EPWM_SHADOW_REG_CTRL_ENABLE, - EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE); - /* Configure Action Qualifier Submodule */ - EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_B, - &pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_B]); - } - - if (pEpwmCfgPrms->cfgDb == TRUE) { - /* Configure Dead Band Submodule */ - EPWM_deadbandCfg(epwmBaseAddr, &pEpwmCfgPrms->dbCfg); - } - else { - /* Configure Dead Band Submodule */ - EPWM_deadbandBypass(epwmBaseAddr); - } - - /* Configure Chopper Submodule */ - EPWM_chopperEnable(epwmBaseAddr, FALSE); - - /* Configure trip zone Submodule */ - EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_ONE_SHOT, 0U); - EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_CYCLE_BY_CYCLE, 0U); - - if (pEpwmCfgPrms->cfgEt == TRUE) { - /* Configure event trigger Submodule */ - EPWM_etIntrCfg(epwmBaseAddr, pEpwmCfgPrms->intSel, - pEpwmCfgPrms->intPrd); - EPWM_etIntrEnable(epwmBaseAddr); - } - - /* Init PWM object */ - hEpwm = (Epwm_Handle)pEpwmObj; - hEpwm->epwmId = pEpwmCfgPrms->epwmId; - hEpwm->epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr; - hEpwm->epwmOutChEn = pEpwmCfgPrms->epwmOutChEn; - hEpwm->hspClkDiv = pEpwmCfgPrms->hspClkDiv; - hEpwm->clkDiv = pEpwmCfgPrms->clkDiv; - hEpwm->epwmTbFreq = pEpwmCfgPrms->epwmTbFreq; - hEpwm->epwmOutFreq = pEpwmCfgPrms->epwmOutFreq; - hEpwm->epwmPrdVal = epwmPrdVal; - hEpwm->toggleEpwmPrd = FALSE; - hEpwm->toggleEpwmPrdState = 0; - hEpwm->epwmPrdValL = 0; - hEpwm->epwmPrdValU = 0; - if ((epwmOutChEn >> 0) & 0x1) { - hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_A] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A]; - hEpwm->cmpAVal = epwmCmpAVal; - hEpwm->cmpANzToZ = FALSE; - hEpwm->cmpAZToNz = FALSE; - } - if ((epwmOutChEn >> 1) & 0x1) { - hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_B] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B]; - hEpwm->cmpBVal = epwmCmpBVal; - hEpwm->cmpBNzToZ = FALSE; - hEpwm->cmpBZToNz = FALSE; - } - - return hEpwm; -} - -/* Update EPWM period */ -int32_t epwmUpdatePrd( - Epwm_Handle hEpwm, - uint32_t epwmOutFreqSet -) -{ - float epwmPrdVal_f; - uint32_t epwmPrdVal; - uint32_t rem; - - /* Check for EPWM period toggle */ - if (hEpwm->toggleEpwmPrd == TRUE) { - hEpwm->epwmPrdVal = (hEpwm->toggleEpwmPrdState == 0) ? hEpwm->epwmPrdValL : hEpwm->epwmPrdValU; - hEpwm->toggleEpwmPrdState ^= 0x1; - - /* Write next period count */ - writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal); - } - - /* Check for PWM frequency change */ - if (hEpwm->epwmOutFreq != epwmOutFreqSet) { - epwmPrdVal_f = (float)hEpwm->epwmTbFreq / epwmOutFreqSet; - epwmPrdVal_f = roundf(epwmPrdVal_f); - - epwmPrdVal = (uint32_t)epwmPrdVal_f; - rem = epwmPrdVal - epwmPrdVal/2*2; - if (rem == 0) { - /* Period is divisible by 2, - alternating period not employed */ - hEpwm->toggleEpwmPrd = FALSE; - hEpwm->toggleEpwmPrdState = 0; - hEpwm->epwmPrdValL = 0; - hEpwm->epwmPrdValU = 0; - hEpwm->epwmPrdVal = epwmPrdVal/2; - } else { - /* Period is not divisible by 2, - alternating period employed to provide correct average EPWM frequency: - EPWM period 2*n : TBPRD <- 'Lower' period - EPWM period 2*n+1 : TBPRD <- 'Upper' period - */ - hEpwm->toggleEpwmPrd = TRUE; - hEpwm->toggleEpwmPrdState = 1; - hEpwm->epwmPrdValL = epwmPrdVal/2; - hEpwm->epwmPrdValU = epwmPrdVal/2+1; - hEpwm->epwmPrdVal = hEpwm->epwmPrdValL; - } - - /* Write next period count */ - writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal); - - hEpwm->epwmOutFreq = epwmOutFreqSet; - } - - return EPWM_DC_SOK; -} - -/* Update EPWM A/B outputs */ -int32_t epwmUpdateOut( - Epwm_Handle hEpwm, - float VrefA, - float VrefB -) -{ - float dcVal; /* EPWM duty cycle value */ - uint16_t cmpVal; /* EPWM CMP value */ - - if ((hEpwm->epwmOutChEn >> 0) & 0x1) { - /* Compute next Duty Cycle and CMP values */ - computeCmpx(VrefA, hEpwm->epwmPrdVal, &dcVal, &cmpVal); - - /* Write next CMPA value */ - writeCmpA(hEpwm->epwmBaseAddr, cmpVal); - - /* EPWM 100% Duty Cycle */ - /* Handle transition to 100% Duty Cycle */ - if (hEpwm->cmpANzToZ == TRUE) { - /* restore original AQ */ - cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); - hEpwm->cmpANzToZ = FALSE; - } - if ((hEpwm->cmpAVal != 0) && (cmpVal == 0)) { - /* set AQ to set for next period */ - cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH); - hEpwm->cmpANzToZ = TRUE; - } - - /* Handle transition from 100% Duty Cycle */ - if (hEpwm->cmpAZToNz == TRUE) { - /* restore original AQ */ - cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); - hEpwm->cmpAZToNz = FALSE; - } - if ((hEpwm->cmpAVal == 0) && (cmpVal != 0)) { - /* set AQ to clear for next period */ - cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW); - hEpwm->cmpAZToNz = TRUE; - } - hEpwm->cmpAVal = cmpVal; - } - - if ((hEpwm->epwmOutChEn >> 1) & 0x1) { - /* Compute next Duty Cycle and CMP values */ - computeCmpx(VrefB, hEpwm->epwmPrdVal, &dcVal, &cmpVal); - - /* Write next CMPB value */ - writeCmpB(hEpwm->epwmBaseAddr, cmpVal); - - /* EPWM 100% Duty Cycle */ - /* Handle transition to 100% Duty Cycle */ - if (hEpwm->cmpBNzToZ == TRUE) { - /* restore original AQ */ - cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); - hEpwm->cmpBNzToZ = FALSE; - } - if ((hEpwm->cmpBVal != 0) && (cmpVal == 0)) { - /* set AQ to set for next period */ - cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH); - hEpwm->cmpBNzToZ = TRUE; - } - - /* Handle transition from 100% Duty Cycle */ - if (hEpwm->cmpBZToNz == TRUE) { - /* restore original AQ */ - cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING); - hEpwm->cmpBZToNz = FALSE; - } - if ((hEpwm->cmpBVal == 0) && (cmpVal != 0)) { - /* set AQ to clear for next period */ - cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW); - hEpwm->cmpBZToNz = TRUE; - } - hEpwm->cmpBVal = cmpVal; - } - - return EPWM_DC_SOK; -} diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.h b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.h deleted file mode 100644 index c42545d..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _EPWM_DC_H_ -#define _EPWM_DC_H_ - -#include -#include -#include - -/* Status return values */ -#define EPWM_DC_SOK ( 0 ) - -#define EPWM_ID_0 ( 0 ) -#define EPWM_ID_1 ( 1 ) -#define EPWM_ID_2 ( 2 ) - -#define EPWM_NUM_OUT_CH ( EPWM_OUTPUT_CH_MAX + 1 ) - -/* EPWM configuration parameters */ -typedef struct _EPwmCfgPrms_t -{ - uint32_t epwmId; /* EPWM ID */ - uint32_t epwmBaseAddr; /* EPWM base address */ - uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */ - uint32_t hspClkDiv; /* EPWM High-Speed Time-base Clock Prescale Bits */ - uint32_t clkDiv; /* EPWM Time-base Clock Prescale Bits */ - uint32_t epwmTbFreq; /* EPWM timebase clock */ - uint32_t epwmOutFreq; /* EPWM output frequency */ - /* EPWM duty cycle */ - uint32_t epwmDutyCycle[EPWM_NUM_OUT_CH]; - uint32_t epwmTbCounterDir; /* EPWM counter direction (Up, Down, Up/Down) */ - - /* TB sync in config */ - Bool cfgTbSyncIn; /* config TB sync in flag (true/false) */ - uint32_t tbPhsValue; /* cfgTbSyncIn==TRUE: timer phase value to load on Sync In event */ - uint32_t tbSyncInCounterDir; /* cfgTbSyncIn==TRUE: counter direction on Sync In event */ - - /* TB sync out config */ - Bool cfgTbSyncOut; /* config TB sync output flag (true/false) */ - uint32_t tbSyncOutMode; /* cfgTbSyncOut==TRUE: Sync Out mode */ - - /* AQ config */ - EPWM_AqActionCfg aqCfg[EPWM_NUM_OUT_CH]; - - /* DB config */ - Bool cfgDb; /* config DB flag (true/false) */ - EPWM_DeadbandCfg dbCfg; /* Deadband config */ - - /* ET config */ - Bool cfgEt; /* config ET module */ - uint32_t intSel; /* ET interrupt select */ - uint32_t intPrd; /* ET interrupt period */ -} EPwmCfgPrms_t; - -/* EPWM object */ -typedef struct _EPwmObj_t -{ - uint32_t epwmId; /* EPWM ID */ - uint32_t epwmBaseAddr; /* EPWM base address */ - uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */ - uint32_t hspClkDiv; /* EPWM High-Speed Time-base Clock Prescale Bits */ - uint32_t clkDiv; /* EPWM Time-base Clock Prescale Bits */ - uint32_t epwmTbFreq; /* EPWM timebase clock */ - uint32_t epwmOutFreq; /* EPWM output frequency */ - /* EPWM duty cycle */ - uint32_t epwmDutyCycle[EPWM_NUM_OUT_CH]; - - uint32_t epwmPrdVal; /* EPWM period value */ - - /* For handling up-down count alternating period - when period isn't divisible by 2 */ - Bool toggleEpwmPrd; /* Flag for EPWM in alternating period mode */ - uint8_t toggleEpwmPrdState; /* Alternating period state: - 'Lower' or 'Upper' period written on alternate ISRs */ - uint32_t epwmPrdValL; /* 'Lower' EPWM period value written in 'Lower' state */ - uint32_t epwmPrdValU; /* 'Upper' EPWM period value written in 'Upper' state */ - - /* For handling ChA 100% Duty Cycle */ - uint32_t cmpAVal; /* Current CMPA value */ - Bool cmpANzToZ; /* Flag for EPWM transition CMPA!=0 to CMPA=0 */ - Bool cmpAZToNz; /* Flag for EPWM transition CMPA=0 to CMPA!=0 */ - - /* For handling ChB 100% Duty Cycle */ - uint32_t cmpBVal; /* Current CMPB value */ - Bool cmpBNzToZ; /* Flag for EPWM transition CMPB!=0 to CMPB=0 */ - Bool cmpBZToNz; /* Flag for EPWM transition CMPB=0 to CMPB!=0 */ -} EPwmObj_t; - -/* EPWM Handle */ -typedef EPwmObj_t * Epwm_Handle; - -/* Initialize EPWM */ -Epwm_Handle epwmInit( - EPwmCfgPrms_t *pEpwmCfgPrms, - EPwmObj_t *pEpwmObj -); - -/* Update EPWM period */ -int32_t epwmUpdatePrd( - Epwm_Handle hEpwm, - uint32_t epwmOutFreqSet -); - -/* Update EPWM A/B outputs */ -int32_t epwmUpdateOut( - Epwm_Handle hEpwm, - float VrefA, - float VrefB -); - -#endif /* _EPWM_DC_H_ */ diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.c b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.c deleted file mode 100644 index 1b240d3..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include "epwm_drv_aux.h" - -#include - -/* Configure PWM Time base counter Frequency/Period */ -void tbPwmFreqCfg( - uint32_t baseAddr, - uint32_t tbClk, - uint32_t pwmFreq, - uint32_t counterDir, - uint32_t enableShadowWrite, - uint32_t *pPeriodCount -) -{ - uint32_t tbPeriodCount; - float tbPeriodCount_f; - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_PRDLD, enableShadowWrite); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CTRMODE, counterDir); - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), - (uint16_t)regVal); - - /* compute period using floating point */ - tbPeriodCount_f = (float)tbClk / pwmFreq; - if (EPWM_TB_COUNTER_DIR_UP_DOWN == counterDir) { - tbPeriodCount_f = tbPeriodCount_f / 2.0; - } - tbPeriodCount_f = roundf(tbPeriodCount_f); - tbPeriodCount = (uint32_t)tbPeriodCount_f; - -#if 0 /* use this in case there is some reason not to use floating point */ - /* compute period using fixed point */ - tbPeriodCount = tbClk << 4; /* U32Q4 */ - tbPeriodCount /= pwmFreq; - if (EPWM_TB_COUNTER_DIR_UP_DOWN == counterDir) { - tbPeriodCount /= 2; - } - tbPeriodCount += 1<<3; /* biased rouding to 0.5 */ - tbPeriodCount >>= 4; /* U32Q0 */ -#endif - - regVal = (counterDir == EPWM_TB_COUNTER_DIR_UP_DOWN) ? - tbPeriodCount : tbPeriodCount-1; - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPRD), - (uint16_t)regVal); - - *pPeriodCount = tbPeriodCount; -} diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.h b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.h deleted file mode 100644 index 39a992e..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _EPWM_DRV_AUX_H_ -#define _EPWM_DRV_AUX_H_ - -#include -#include -#include - -/* Write EPWM CMPA */ -static inline void writeCmpA( - uint32_t baseAddr, - uint32_t cmpVal -) -{ - HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA, - (uint16_t)cmpVal); -} - -/* Write EPWM CMPB */ -static inline void writeCmpB( - uint32_t baseAddr, - uint32_t cmpVal -) -{ - HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB, - (uint16_t)cmpVal); -} - -/* Write EPWM CMPA/CMPB */ -static inline void writeCmpAB( - uint32_t baseAddr, - uint32_t cmpAVal, - uint32_t cmpBVal -) -{ - /* Write CMPA */ - HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA, - (uint16_t)cmpAVal); - - /* Write CMPB */ - HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB, - (uint16_t)cmpBVal); -} - -/* Configure Output ChannelA AQ Zero */ -static inline void cfgOutChAAqZero( - uint32_t baseAddr, - uint32_t zeroAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_ZRO, zeroAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); -} - -/* Configure Output ChannelA AQ CMPA Up */ -static inline void cfgOutChAAqCAU( - uint32_t baseAddr, - uint32_t cmpAUpAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAU, cmpAUpAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); -}; - -/* Configure Output ChannelA AQ CMPA Down */ -static inline void cfgOutChAAqCAD( - uint32_t baseAddr, - uint32_t cmpADownAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAD, cmpADownAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); -} - -/* Configure Output ChannelB AQ Zero */ -static inline void cfgOutChBAqZero( - uint32_t baseAddr, - uint32_t zeroAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLB); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLB_ZRO, zeroAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLB), (uint16_t)regVal); -} - -/* Configure Output ChannelA AQ CMPB Up */ -static inline void cfgOutChAAqCBU( - uint32_t baseAddr, - uint32_t cmpBUpAction -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA); - HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CBU, cmpBUpAction); - HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal); -} - -/* Write TB Period */ -static inline void writeTbPrd( - uint32_t baseAddr, - uint32_t tbPeriodCount -) -{ - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPRD), (uint16_t)tbPeriodCount); -} - -/* Write TB Phase */ -static inline void writeTbPhase( - uint32_t baseAddr, - uint32_t tbPhsValue -) -{ - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPHS), (uint16_t)tbPhsValue); -} - -/* Write TBCTL HSPDIV & CLKDIV */ -static inline void writeTbClkDiv( - uint32_t baseAddr, - uint32_t hspClkDiv, - uint32_t clkDiv -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CLKDIV, clkDiv); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_HSPCLKDIV, hspClkDiv); - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal); -} - -/* Write TBCTL CTRMODE */ -static inline void writeTbCtrMode( - uint32_t baseAddr, - uint32_t ctrMode -) -{ - uint32_t regVal = 0U; - - regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL); - HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CTRMODE, ctrMode); - HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal); -} - -/* Configure PWM Time base counter Frequency/Period */ -void tbPwmFreqCfg( - uint32_t baseAddr, - uint32_t tbClk, - uint32_t pwmFreq, - uint32_t counterDir, - uint32_t enableShadowWrite, - uint32_t *pPeriodCount -); - -#endif /* _EPWM_DRV_AUX_H_ */ diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.c b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.c deleted file mode 100644 index 7a13302..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "epwm_mod.h" - -#include -#include - - -/* Min / max output amplitude. - Waveform amplitude values beyond these thresholds are saturated. */ -#define VREF_MAX ( 1.0f ) -#define VREF_MIN ( -1.0f ) - -/* Compute Duty Cycle & CMPx given Vref & EPWM period */ -void computeCmpx( - float Vref, - uint32_t epwmPrdVal, - float *pEpwmDutyCycle, - uint16_t *pEpwmCmpVal -) -{ - float dc_f; - float cmp_f; - uint16_t cmp; - - if (Vref >= VREF_MAX) { - /* 100% duty cycle */ - dc_f = 1.0; - } - else if (Vref <= VREF_MIN) { - /* 0% duty cycle */ - dc_f = 0.0; - } - else { - /* compute Duty Cycle */ - dc_f = 0.5*(Vref + 1.0); - } - - /* compute CMPx */ - cmp_f = (1.0 - dc_f)*epwmPrdVal; /* up-down count */ - cmp = (uint16_t)roundf(cmp_f); - - *pEpwmDutyCycle = dc_f; - *pEpwmCmpVal = cmp; -} diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.h b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.h deleted file mode 100644 index 8f9506e..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _EPWM_MOD_H_ -#define _EPWM_MOD_H_ - -#include - -/* Compute Duty Cycle & CMPx given Vref */ -void computeCmpx( - float Vref, - uint32_t epwmPrdVal, - float *pEpwmDutyCycle, - uint16_t *pEpwmCmpVal -); - -#endif /* _EPWM_MOD_H_ */ diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.c b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.c deleted file mode 100644 index dcb8951..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include "ti_drivers_config.h" -#include "ti_drivers_open_close.h" -#include "ti_board_open_close.h" - -#include -#include -#include -#include - -#include "tisdfm_pruss_intc_mapping.h" /* INTC configuration */ -#include "current_sense/sdfm/firmware/sdfm_bin.h" /* SDFM image data */ -#include "sdfm.h" -#include "current_sense/sdfm/include/sdfm_api.h" -#include "mclk_iep0_sync.h" - -/* PRU SDFM FW image info */ -typedef struct PRUSDFM_PruFwImageInfo_s -{ - const uint32_t *pPruImemImg; - const uint32_t pruImemImgSz; -} PRUSDFM_PruFwImageInfo; - -/* Number of PRU images */ -#define PRU_SDFM_NUM_PRU_IMAGE ( 1 ) - -/* PRU SDFM image info */ -static PRUSDFM_PruFwImageInfo gPruFwImageInfo[PRU_SDFM_NUM_PRU_IMAGE] = -{ - {SDFM_PRU0_image_0, sizeof(SDFM_PRU0_image_0)} /* single PRU FW binary */ -}; - -/* ICSS INTC configuration */ -static const PRUICSS_IntcInitData gPruicssIntcInitdata = PRUICSS_INTC_INITDATA; - -/* - * ======== initIcss ======== - */ -/* Initialize ICSSG */ -int32_t initIcss( - uint8_t icssInstId, - uint8_t sliceId, - uint8_t saMuxMode, - PRUICSS_Handle *pPruIcssHandle -) -{ - PRUICSS_Handle pruIcssHandle; - int32_t size; - int32_t status; - - /* Open ICSS PRU instance */ - pruIcssHandle = PRUICSS_open(icssInstId); - if (pruIcssHandle == NULL) { - return SDFM_ERR_INIT_ICSSG; - } - - /* Disable slice PRU cores */ - if (sliceId == ICSSG_SLICE_ID_0) - { - status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU0); - if (status != SystemP_SUCCESS) - { - return SDFM_ERR_INIT_ICSSG; - } - } - else if (sliceId == ICSSG_SLICE_ID_1) - { - status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU1); - if (status != SystemP_SUCCESS) - { - return SDFM_ERR_INIT_ICSSG; - } - } - else - { - return SDFM_ERR_INIT_ICSSG; - } - - /* Reset slice memories */ - size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_IRAM_PRU(sliceId)); - if (size == 0) - { - return SDFM_ERR_INIT_ICSSG; - } - size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_DATARAM(sliceId)); - if (size == 0) - { - return SDFM_ERR_INIT_ICSSG; - } - - /* Set ICSS pin mux */ - PRUICSS_setSaMuxMode(pruIcssHandle, saMuxMode); - - /* Initialize ICSS INTC */ - status = PRUICSS_intcInit(pruIcssHandle, &gPruicssIntcInitdata); - if (status != SystemP_SUCCESS) { - return SDFM_ERR_INIT_ICSSG; - } - - *pPruIcssHandle = pruIcssHandle; - - return SDFM_ERR_NERR; -} -void SDFM_configGpioPins(sdfm_handle h_sdfm) -{ - /*ch0 GPIO configuration*/ - uint32_t gpioBaseAddrCh0 = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_ZC_TH_CH0_BASE_ADDR); - uint32_t pinNumCh0 = GPIO_ZC_TH_CH0_PIN; - GPIO_setDirMode(gpioBaseAddrCh0, pinNumCh0, GPIO_ZC_TH_CH0_DIR); - SDFM_configComparatorGpioPins(h_sdfm, 0, gpioBaseAddrCh0, pinNumCh0); - - /*ch1 GPIO configuration*/ - uint32_t gpioBaseAddrCh1 = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_ZC_TH_CH1_BASE_ADDR); - uint32_t pinNumCh1 = GPIO_ZC_TH_CH1_PIN; - GPIO_setDirMode(gpioBaseAddrCh1, pinNumCh1, GPIO_ZC_TH_CH1_DIR); - SDFM_configComparatorGpioPins(h_sdfm, 1, gpioBaseAddrCh1, pinNumCh1); - - /*ch2 GPIO configuration*/ - uint32_t gpioBaseAddrCh2 = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_ZC_TH_CH2_BASE_ADDR); - uint32_t pinNumCh2 = GPIO_ZC_TH_CH2_PIN; - GPIO_setDirMode(gpioBaseAddrCh2, pinNumCh2, GPIO_ZC_TH_CH2_DIR); - SDFM_configComparatorGpioPins(h_sdfm, 2, gpioBaseAddrCh2, pinNumCh2); - -} -void SDFM_measurePhaseCompensation(sdfm_handle h_sdfm, uint32_t iep_clk) -{ - - /*waiting till measurment done */ - float delay; - delay = SDFM_measureClockPhaseDelay(h_sdfm, 0); - /*Convert nenosec into IEP cycle count*/ - uint32_t iepCount = (delay*iep_clk)/1000000000; - - /*config IEP SYNC1 delay based on phase compensation */ - config_SYNC_DELAY(iepCount); - -} -/* Initialize SDFM PRU FW */ -int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUICSS_Handle pruIcssHandle) -{ - sdfm_handle hSdfm; - uint8_t SDFM_CH = 0; - /* Initialize SDFM instance */ - hSdfm = SDFM_init(pruId, pSdfmPrms->pruInsId); - - hSdfm->gPruIcssHandle = pruIcssHandle; - hSdfm->pruss_cfg = (void *)(((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->cfgRegBase); - - uint32_t i; - i = SDFM_getFirmwareVersion(hSdfm); - DebugP_log("\n\n\n"); - DebugP_log("SDFM firmware version \t: %x.%x.%x (%s)\n\n", (i >> 24) & 0x7F, - (i >> 16) & 0xFF, i & 0xFFFF, i & (1 << 31) ? "internal" : "release"); - if (hSdfm == NULL) - { - return SDFM_ERR_INIT_SDFM; - } - - hSdfm->pruCoreClk = pSdfmPrms->pruClock; - hSdfm->iepClock = pSdfmPrms->g0IepClock; - hSdfm->sdfmClock = pSdfmPrms->sdClock; - hSdfm->sampleOutputInterface = (SDFM_SampleOutInterface *)(pSdfmPrms->samplesBaseAddress); - uint32_t sampleOutputInterfaceGlobalAddr = CPU0_BTCM_SOCVIEW(pSdfmPrms->samplesBaseAddress); - hSdfm->p_sdfm_interface->sampleBufferBaseAdd = sampleOutputInterfaceGlobalAddr; - hSdfm->iepInc = 1; /* Default IEP increment 1 */ - - uint8_t acc_filter = 0; //SINC3 filter - uint8_t ecap_divider = 0x0F; //IEP at 300MHz: SD clock = 300/15=20Mhz - - if(pSdfmPrms->phaseDelay) - { - SDFM_measurePhaseCompensation(hSdfm, pSdfmPrms->g1IepClock); - } - - - /*configure IEP count for one epwm period*/ - SDFM_configIepCount(hSdfm, pSdfmPrms->epwmOutFreq); - - /*configure ecap as PWM code for generate 20 MHz sdfm clock*/ - SDFM_configEcap(hSdfm, ecap_divider); - - /*set Noraml current OSR */ - SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->filterOsr); - - - /*below configuration for all three channel*/ - for(SDFM_CH = 0; SDFM_CH < NUM_CH_SUPPORTED; SDFM_CH++) - { - SDFM_setEnableChannel(hSdfm, SDFM_CH); - - /*set comparator osr or Over current osr*/ - SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->comFilterOsr); - - /*set ACC source or filter type*/ - SDFM_configDataFilter(hSdfm, SDFM_CH, acc_filter); - - /*set clock inversion & clock source for all three channel*/ - SDFM_selectClockSource(hSdfm, SDFM_CH, pSdfmPrms->clkPrms[SDFM_CH]); - - /*set threshold values */ - SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->thresholdParms[SDFM_CH]); - if(pSdfmPrms->enFastDetect) - { - /*Fast detect configuration */ - SDFM_configFastDetect(hSdfm, SDFM_CH, pSdfmPrms->fastDetect[SDFM_CH]); - } - if(pSdfmPrms->enComparator) - { - SDFM_enableComparator(hSdfm, SDFM_CH); - } - else - { - SDFM_disableComparator(hSdfm, SDFM_CH); - } - - if(pSdfmPrms->enZeroCross) - { - SDFM_enableZeroCrossDetection(hSdfm, SDFM_CH, pSdfmPrms->zcThr[SDFM_CH]); - } - - } - - /*GPIO pin configuration for threshold measurment*/ - SDFM_configGpioPins(hSdfm); - - SDFM_setSampleTriggerTime(hSdfm, pSdfmPrms->firstSampTrigTime); - if(pSdfmPrms->enSecondUpdate) - { - SDFM_enableDoubleSampling(hSdfm, pSdfmPrms->secondSampTrigTime); - } - else - { - SDFM_disableDoubleSampling(hSdfm); - } - - /* Enable (global) SDFM */ - SDFM_enable(hSdfm); - - *pHSdfm = hSdfm; - - return SDFM_ERR_NERR; -} -/* - * ======== initPruSdfm ======== - */ -/* Initialize PRU core for SDFM */ -int32_t initPruSdfm( - PRUICSS_Handle pruIcssHandle, - uint8_t pruInstId, - SdfmPrms *pSdfmPrms, - sdfm_handle *pHSdfm -) -{ - uint8_t sliceId; - uint32_t pruIMem; - PRUSDFM_PruFwImageInfo *pPruFwImageInfo; - int32_t size; - const uint32_t *sourceMem; /* Source memory[ Array of uint32_t ] */ - uint32_t imemOffset; /* Offset at which write will happen */ - uint32_t byteLen; /* Total number of bytes to be written */ - uint8_t pruId; - int32_t status; - - /* Reset PRU */ - status = PRUICSS_resetCore(pruIcssHandle, pruInstId); - if (status != SystemP_SUCCESS) { - return SDFM_ERR_INIT_PRU_SDFM; - } - - - /* Calculate slice ID */ - sliceId = pruInstId - (uint8_t)pruInstId/ICSSG_NUM_SLICE * ICSSG_NUM_SLICE; - /* Determine PRU DMEM address */ - /* Determine PRU FW image and PRU IMEM address */ - switch (pruInstId) - { - case PRUICSS_PRU0: - case PRUICSS_PRU1: - pPruFwImageInfo = &gPruFwImageInfo[0]; - pruIMem = PRUICSS_IRAM_PRU(sliceId); - break; - default: - pPruFwImageInfo = NULL; - break; - } - - if ((pPruFwImageInfo == NULL) || - (pPruFwImageInfo->pPruImemImg == NULL)) - { - return SDFM_ERR_INIT_PRU_SDFM; - } - - /* Write IMEM */ - imemOffset = 0; - sourceMem = (uint32_t *)pPruFwImageInfo->pPruImemImg; - byteLen = pPruFwImageInfo->pruImemImgSz; - size = PRUICSS_writeMemory(pruIcssHandle, pruIMem, imemOffset, sourceMem, byteLen); - if (size == 0) - { - return SDFM_ERR_INIT_PRU_SDFM; - } - - /* Enable PRU */ - status = PRUICSS_enableCore(pruIcssHandle, pruInstId); - if (status != SystemP_SUCCESS) { - return SDFM_ERR_INIT_PRU_SDFM; - } -/* Translate PRU ID to SDFM API */ - if (pruInstId == PRUICSS_PRU0) - { - pruId = PRU_ID_0; - } - else if (pruInstId == PRUICSS_PRU1) - { - pruId = PRU_ID_1; - } - else { - return SDFM_ERR_INIT_PRU_SDFM; - } - - /* Initialize SDFM PRU FW */ - status = initSdfmFw(pruId, pSdfmPrms, pHSdfm, pruIcssHandle); - if (status != SDFM_ERR_NERR) { - return SDFM_ERR_INIT_PRU_SDFM; - } - return SDFM_ERR_NERR; - -} - - diff --git a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.h b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.h deleted file mode 100644 index d82db60..0000000 --- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) 2023 Texas Instruments Incorporated - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _SDFM_H_ -#define _SDFM_H_ - -#include -#include -#include "current_sense/sdfm/include/sdfm_api.h" - -/* Status codes */ -#define SDFM_ERR_NERR ( 0 ) /* no error */ -#define SDFM_ERR_CFG_PIN_MUX ( -1 ) /* pin mux configuration error */ -#define SDFM_ERR_CFG_ICSSG_CLKCFG ( -2 ) /* ICSSG clock configuration error */ -#define SDFM_ERR_INIT_ICSSG ( -3 ) /* initialize ICSSG error */ -#define SDFM_ERR_CFG_MCU_INTR ( -4 ) /* interrupt configuration error */ -#define SDFM_ERR_INIT_PRU_SDFM ( -5 ) /* initialize PRU for SDFM error */ -#define SDFM_ERR_INIT_SDFM ( -6 ) /* initialize SDFM error */ - -/* Bit for SDFM configuration mask */ -#define SDFM_CFG_CLK ( 1<<0 ) -#define SDFM_CFG_OSR ( 1<<1 ) -#define SDFM_CFG_TRIG_SAMP_TIME ( 1<<2 ) -#define SDFM_CFG_TRIG_SAMP_CNT ( 1<<3 ) -#define SDFM_CFG_CH_EN ( 1<<4 ) -#define SDFM_CFG_FD ( 1<<5 ) -#define SDFM_CFG_TRIG_OUT_SAMP_BUF ( 1<<6 ) - -/* SDFM mode */ -#define SDFM_MODE_TRIG ( 0 ) -#define SDFM_MODE_CONT ( 1 ) - -/* ICSSG Core clock source selection options */ -#define CORE_CLK_SEL_ICSSGn_CORE_CLK ( 0 ) /* Mux Output */ -#define CORE_CLK_SEL_ICSSGn_ICLK ( 1 ) /* ICSSGn_ICLK = MAIN_SYSCLK0/2 = 250 MHz */ -/* ICSSG Core clock selections in case Mux Output selected */ -#define ICSSGn_CORE_CLK_SEL_MAIN_PLL2_HSDIV0_CLKOUT ( 0 ) /* 225 or 300 MHz, default 225 MHz */ -#define ICSSGn_CORE_CLK_SEL_MAIN_PLL0_HSDIV9_CLKOUT ( 1 ) /* 200, 250, or 333 MHz, default 200 MHz */ -#define ICSSGn_CORE_CLK_SEL_NUMSEL ( 2 ) -/* ICSSG Core clock frequency in case Mux Output selected. - Set to 0 in case clock frequency configuration not desired. */ -#define ICSSGn_CORE_CLK_FREQ_225MHZ ( 225000000UL ) /* MAIN PLL2 HSDIV0, 225 MHz */ -#define ICSSGn_CORE_CLK_FREQ_300MHZ ( 300000000UL ) /* MAIN PLL2 HSDIV0, 300 MHz */ -#define ICSSGn_CORE_CLK_FREQ_200MHZ ( 200000000UL ) /* MAIN PLL0 HSDIV9, 200 MHz */ -#define ICSSGn_CORE_CLK_FREQ_250MHZ ( 250000000UL ) /* MAIN PLL0 HSDIV9, 250 MHz */ -#define ICSSGn_CORE_CLK_FREQ_333MHZ ( 333333333UL ) /* MAIN PLL0 HSDIV9, 333 MHz */ -#define ICSSGn_CORE_CLK_FREQ_NOCFG ( 0UL ) /* No clock frequency reconfig */ -//#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_NOCFG ) -#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_300MHZ ) -//#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_333MHZ ) - -/* ICSSG IEP clock source selection options */ -#define IEP_CLK_SEL_ICSSGn_IEP_CLK ( 0 ) /* Mux Output */ -#define IEP_CLK_SEL_CORE_CLK ( 1 ) /* CORE_CLK */ -/* ICSSG IEP clock selections in case Mux output selected */ -#define ICSSGn_IEP_CLK_SEL_MAIN_PLL2_HSDIV5_CLKOUT ( 0 ) /* Default 225 MHz */ -#define ICSSGn_IEP_CLK_SEL_MAIN_PLL0_HSDIV6_CLKOUT ( 1 ) /* 200 or 250 MHz, default 200 MHz */ -#define ICSSGn_IEP_CLK_SEL_CPSW0_CPTS_RFT_CLK ( 2 ) -#define ICSSGn_IEP_CLK_SEL_CPTS_RFT_CLK ( 3 ) -#define ICSSGn_IEP_CLK_SEL_MCU_EXT_REFCLK0 ( 4 ) -#define ICSSGn_IEP_CLK_SEL_EXT_REFCLK1 ( 5 ) -#define ICSSGn_IEP_CLK_SEL_SERDES0_IP1_LN0_TXMCLK ( 6 ) -#define ICSSGn_IEP_CLK_SEL_SYSCLK0 ( 7 ) -#define ICSSGn_IEP_CLK_SEL_NUMSEL ( 8 ) -/* ICSSG IEP clock frequency in case Mux Output selected. - Set to 0 in case clock frequency configuration not desired. */ -#define ICSSGn_IEP_CLK_FREQ_200MHZ ( 200000000UL ) /* MAIN PLL0 HSDIV6, 200 MHz */ -#define ICSSGn_IEP_CLK_FREQ_250MHZ ( 250000000UL ) /* MAIN PLL0 HSDIV6, 250 MHz */ -#define ICSSGn_IEP_CLK_FREQ_NOCFG ( 0UL ) /* No clock frequency reconfig */ -#define ICSSGn_IEP_CLK_FREQ ( ICSSGn_IEP_CLK_FREQ_NOCFG ) - -/* Default ICSS pin mux setting */ -#define PRUICSS_G_MUX_EN_DEF ( 0x0 ) /* ICSSG_SA_MX_REG:G_MUX_EN */ - -/* Translate the TCM local view addr to SoC view addr */ -#define CPU0_ATCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_ATCM_BASE+(x)) -#define CPU1_ATCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_ATCM_BASE+(x)) -#define CPU0_BTCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_BTCM_BASE+(x - CSL_R5FSS0_BTCM_BASE)) -#define CPU1_BTCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_BTCM_BASE+(x - CSL_R5FSS1_BTCM_BASE)) - -#define ICSSG_SLICE_ID_0 ( 0 ) /* ICSSG slide ID 0 */ -#define ICSSG_SLICE_ID_1 ( 1 ) /* ICSSG slide ID 1 */ -#define ICSSG_NUM_SLICE ( 2 ) /* ICSSG number of slices */ -#define NUM_FD_FIELD ( 3 ) - -#define NUM_CH_SUPPORTED ( 3 ) -/* SDFM Channel IDs*/ -#define SDFM_CH0 (0) -#define SDFM_CH1 (1) -#define SDFM_CH2 (2) -#define SDFM_CH3 (3) -#define SDFM_CH4 (4) -#define SDFM_CH5 (5) -#define SDFM_CH6 (6) -#define SDFM_CH7 (7) -#define SDFM_CH8 (8) -/*! - * @brief PRUICSS Instance IDs - */ -typedef enum PRUICSS_MaxInstances_s -{ - PRUICSS_INSTANCE_ONE=0, - PRUICSS_INSTANCE_TWO=1, - PRUICSS_INSTANCE_MAX=2 -} PRUICSS_MaxInstances; - -/* SDFM configuration parameters */ -typedef struct SdfmPrms_s -{ - /**pruInsId); - + hSdfm->gPruIcssHandle = pruIcssHandle; hSdfm->pruss_cfg = (void *)(((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->cfgRegBase); @@ -277,15 +280,11 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI SDFM_CH = 0; break; } - } - for(int i = SDFM_CH; iiepClock = pSdfmPrms->iepClock; + hSdfm->pruCoreClk = pSdfmPrms->pruClock; + hSdfm->iepClock = pSdfmPrms->iepClock[0]; hSdfm->sdfmClock = pSdfmPrms->sdClock; hSdfm->sampleOutputInterface = (SDFM_SampleOutInterface *)(pSdfmPrms->samplesBaseAddress); uint32_t sampleOutputInterfaceGlobalAddr = CPU0_BTCM_SOCVIEW(pSdfmPrms->samplesBaseAddress); @@ -305,7 +305,13 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI uint8_t acc_filter = 0; //SINC3 filter uint8_t ecap_divider = 0x0F; //IEP at 300MHz: SD clock = 300/15=20Mhz - + + /*Phase delay calculation for ch0*/ + if(pSdfmPrms->phaseDelay) + { + SDFM_measureClockPhaseDelay(hSdfm, pSdfmPrms->clkPrms[0].clk_inv); + } + /*configure IEP count for one epwm period*/ SDFM_configIepCount(hSdfm, pSdfmPrms->epwmOutFreq); @@ -315,7 +321,6 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI /*set Noraml current OSR */ SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->filterOsr); - /*below configuration for all three channel*/ for(SDFM_CH = 0; SDFM_CH < NUM_CH_SUPPORTED_PER_AXIS; SDFM_CH++) { @@ -336,7 +341,7 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI /*Fast detect configuration */ SDFM_configFastDetect(hSdfm, SDFM_CH, pSdfmPrms->fastDetect[SDFM_CH]); } - if(pSdfmPrms->enComparator ) + if(pSdfmPrms->enComparator) { SDFM_enableComparator(hSdfm, SDFM_CH); } @@ -344,9 +349,10 @@ int32_t initSdfmFw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, PRUI { SDFM_disableComparator(hSdfm, SDFM_CH); } - + /*enabling Zero cross only for first channel of axis*/ - if(pSdfmPrms->enZeroCross && SDFM_CH == 2) + + if(pSdfmPrms->enZeroCross && ((pSdfmPrms->loadShare && SDFM_CH == 2)||(!pSdfmPrms->loadShare))) { SDFM_enableZeroCrossDetection(hSdfm, SDFM_CH, pSdfmPrms->zcThr[SDFM_CH]); } @@ -420,7 +426,6 @@ int32_t initPruSdfm( { pPruFwImageInfo = &gPruFwImageInfo[0]; pruIMem = PRUICSS_IRAM_PRU(sliceId); - } break; case PRUICSS_RTU_PRU0: @@ -469,11 +474,11 @@ int32_t initPruSdfm( } /* Translate PRU ID to SDFM API */ if ((pruInstId == PRUICSS_PRU0) || (pruInstId == PRUICSS_RTU_PRU0) || (pruInstId == PRUICSS_TX_PRU0)) - { + { pruId = PRU_ID_0; } else if ((pruInstId == PRUICSS_PRU1) || (pruInstId == PRUICSS_RTU_PRU1) || (pruInstId == PRUICSS_TX_PRU1)) - { + { pruId = PRU_ID_1; } else @@ -481,7 +486,7 @@ int32_t initPruSdfm( return SDFM_ERR_INIT_PRU_SDFM; } - /* Initialize SDFM PRU FW */ + status = initSdfmFw(pruId, pSdfmPrms, pHSdfm, pruIcssHandle); if (status != SDFM_ERR_NERR) { diff --git a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/sdfm.h b/examples/current_sense/sdfm_example.h similarity index 98% rename from examples/current_sense/icss_sdfm_nine_channel_load_share_mode/sdfm.h rename to examples/current_sense/sdfm_example.h index 58a9f81..7fd28e3 100644 --- a/examples/current_sense/icss_sdfm_nine_channel_load_share_mode/sdfm.h +++ b/examples/current_sense/sdfm_example.h @@ -136,14 +136,15 @@ typedef enum PRUICSS_MaxInstances_s /* SDFM configuration parameters */ typedef struct SdfmPrms_s { - /**p_sdfm_interface->sdfm_ch_ctrl.en_phase_delay = 1; @@ -429,8 +429,11 @@ float SDFM_measureClockPhaseDelay(sdfm_handle h_sdfm, uint16_t clkEdg) /*PRU cycles for one SD clock period*/ uint32_t pruCycles = ceil((float)(h_sdfm->pruCoreClk/(h_sdfm->sdfmClock))); h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay = pruCycles - temp; - } + +} +float SDFM_getClockPhaseDelay(sdfm_handle h_sdfm) +{ /*conversion from PRU cycle to ns */ float phaseDelay = ((float)h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay * 1000000000)/h_sdfm->pruCoreClk; return phaseDelay; diff --git a/source/current_sense/sdfm/include/sdfm_api.h b/source/current_sense/sdfm/include/sdfm_api.h index 800f835..04f8294 100644 --- a/source/current_sense/sdfm/include/sdfm_api.h +++ b/source/current_sense/sdfm/include/sdfm_api.h @@ -361,10 +361,20 @@ void SDFM_enableLoadShareMode(sdfm_handle h_sdfm, uint8_t sliceId); * \param[in] h_sdfm SDFM handle * \param[in] clEdg Clock polarity: 1 -> falling edge, 0 -> raising edge * - * \retval Phase delay in nano sec + * */ -float SDFM_measureClockPhaseDelay(sdfm_handle h_sdfm, uint16_t clEdg); +void SDFM_measureClockPhaseDelay(sdfm_handle h_sdfm, uint16_t clEdg); +/** + * + * \brief This API returns Clock phase compensation + * + * \param[in] h_sdfm SDFM handle + * + * \retval Phase delay in nano sec + * + */ +float SDFM_getClockPhaseDelay(sdfm_handle h_sdfm); /** * * \brief This API returns high threshold Status for specified SDFM channel number